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// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module scales video streams on the DE boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_scaler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Frame's Channel Width
parameter DW = 7; // Frame's Data Width
parameter EW = 0; // Frame's Empty Width
parameter WIW = 9; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 640;
parameter WIDTH_DROP_MASK = 4'b0000;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 9; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 640; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [CW: 0] stream_out_channel;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [CW: 0] internal_channel;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_multiply_height Multiply_Height (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// Bi-Directional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_channel (stream_out_channel),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Multiply_Height.DW = DW,
Multiply_Height.WW = MH_WW,
Multiply_Height.WIDTH = MH_WIDTH_IN,
Multiply_Height.MCW = MH_CW;
endmodule
|
/*
* sram_ctl - Push and pull data to/from the SRAM
*
* This allows the supervisor to put data in the SRAM memory and read it out again.
* Note that this operation halts the CPC clock and so affects CPC timing
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
* Registers:
* 0000 (0x0) Data In/Out
* 1000 (0x8) Set address low byte (0-7)
* 1001 (0x9) Set address middle byte (8-15)
* 1010 (0xa) Set address high byte (16-23)
* 1111 (0xF) Control signals
* b7 - Assert supervisor bus control (halts CPC clock)
* b6 - Use control signals, not memory addresses
*/
`timescale 1ns/1ns
`default_nettype none
module sram_ctl (
// Control signals
input wire clk_i,
input wire reset_i,
// Support Bus signals
input wire [3:0] A_i,
input wire [7:0] D_i,
output wire [7:0] D_o,
input wire rd_i,
input wire wr_i,
output reg wait_o,
// Memory arbiter signals
output reg cpc_pause_o,
input cpc_pause_ack_i,
// CPC Signals/RAMROM signals
input wire [23:0] cpc_A_i,
input wire [7:0] cpc_D_i,
output wire [7:0] cpc_D_o,
input wire cpc_en_i,
input wire cpc_rd_i,
input wire cpc_wr_i,
output wire [63:0] cpc_romflags_o,
// Memory signals
output wire [23:0] mem_A_o,
input wire [15:0] mem_D_i,
output wire [15:0] mem_D_o,
output wire mem_go_o,
output wire [2:0] mem_cmd_o,
input wire mem_busy_i,
input wire mem_valid_i
);
// Wire definitions ===========================================================================
wire rd_rise, wr_rise, crd_rise, cwr_rise, busy_rise;
wire [7:0] support_data_snip;
// Registers ==================================================================================
reg [7:0] A[0:3], DOUT = 8'd0;
reg [1:0] track_rd = 2'd0, track_wr = 2'd0, track_crd = 2'd0, track_cwr = 2'd0;
reg control_ops = 1'd0;
reg old_lsb = 1'b0, incr_address = 1'b0;
reg [63:0] romflags = 64'd0;
// Assignments ================================================================================
assign mem_A_o = (cpc_pause_o & cpc_pause_ack_i) ? {1'b0, A[2], A[1], A[0][7:1]} : {1'b0,cpc_A_i[23:1]}; // A multiplexor
assign mem_D_o = (cpc_pause_o & cpc_pause_ack_i) ? {D_i,D_i} : {cpc_D_i,cpc_D_i}; // D multiplexor
assign mem_go_o = (cpc_pause_o & cpc_pause_ack_i) ? // en multiplexor
((rd_rise | wr_rise) & (A_i==4'd0)) :
((crd_rise | cwr_rise) & cpc_en_i);
assign mem_cmd_o = (cpc_pause_o & cpc_pause_ack_i) ? {control_ops, rd_i, control_ops ? 1'b1 : A[0][0]} : {1'b0, cpc_rd_i, cpc_A_i[0]};
// CPC Output
assign cpc_D_o = cpc_A_i[0] ? mem_D_i[15:8] : mem_D_i[7:0];
// Snip the correct byte from the word returned from memory
assign support_data_snip = (old_lsb ? mem_D_i[15:8] : mem_D_i[7:0]);
// Switch between internal code and memory data
assign D_o = (A_i == 4'd0) ? support_data_snip : DOUT;
// Output the ROMFLAGS
assign cpc_romflags_o = romflags;
// Track rise
assign rd_rise = (track_rd == 2'b01);
assign wr_rise = (track_wr == 2'b01);
assign crd_rise = (track_crd == 2'b01);
assign cwr_rise = (track_cwr == 2'b01);
// Wait signal when processing a txn, and data not yet valid
//assign wait_o = incr_address & ~mem_valid_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Core logic ================================================================================
// Track rises
always @(posedge clk_i) track_rd <= {track_rd[0],rd_i};
always @(posedge clk_i) track_wr <= {track_wr[0],wr_i};
always @(posedge clk_i) track_crd <= {track_rd[0],cpc_rd_i};
always @(posedge clk_i) track_cwr <= {track_wr[0],cpc_wr_i};
// Handle the IO bus signals
always @(posedge clk_i or posedge reset_i)
if( reset_i ) begin
{A[3],A[2],A[1],A[0]} <= 32'd0;
DOUT <= 8'd0;
cpc_pause_o <= 1'b0;
incr_address <= 1'b0;
romflags <= 64'd0;
end else begin
// When controller accepted address, then increment address
if( (mem_valid_i | mem_busy_i) & incr_address ) begin
old_lsb <= A[0][0];
{A[3],A[2],A[1],A[0]} <= {A[3],A[2],A[1],A[0]} + 1'b1;
incr_address <= 1'b0;
end
else
case( A_i )
4'b0000 : begin
// Trigger an update to the address is requested
if( rd_rise | wr_rise ) incr_address <= 1'b1;
end
// Read/write the starting address
4'b1000, 4'b1001, 4'b1010, 4'b1011 : begin
if( rd_i ) DOUT <= A[A_i[1:0]];
else
if( wr_i ) A[A_i[1:0]] <= D_i;
end
// Not really an SRAM function, but manages the rom flags
4'b1100 : begin
if( wr_i ) case( D_i[7:6] )
2'b01 : romflags[D_i[5:0]] <= 1'b0; // Clear
2'b10 : romflags[D_i[5:0]] <= 1'b1; // Set
2'b11 : romflags <= 64'd0; // Flush ROMS
endcase
end
// Control signals
4'b1111 : begin
if( wr_i ) begin
cpc_pause_o <= D_i[7];
control_ops <= D_i[6];
end
else
if( rd_i ) DOUT <= {cpc_pause_ack_i,control_ops,6'd0};
end
default: ;
endcase
end
// Manage WAIT signal
always @(posedge clk_i or posedge reset_i)
if( reset_i ) wait_o <= 1'b0;
else begin
if( ( A_i == 4'd0 ) && (rd_rise/*|wr_rise*/) ) wait_o <= 1'b1;
else if( mem_valid_i | ~mem_busy_i ) wait_o <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_TB_V
`define SKY130_FD_SC_HD__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hd__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_TB_V
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/10ps
module sdram_init (
// -- Clock & Reset
input sdram_clk,
input sdram_rst_,
// -- CKE
// input CKE_IN,
// output reg CKE_OUT,
// -- init output signals
output reg PAA = 0,
output reg SET_MODE
);
parameter
INIT_CNT = 16'h4000,
INIT_HALF_CNT = INIT_CNT >> 1;
/********************************************************/
// -- Internal Signals
reg [15:0] init_counter;
wire init_counter_done;
//wire init_counter_half_done;
assign init_counter_done = (init_counter == INIT_CNT);
//assign init_counter_half_done = (init_counter > INIT_HALF_CNT);
always @(posedge sdram_clk) begin
if (!sdram_rst_)
init_counter <= 'b0;
else if (!init_counter_done)
init_counter <= init_counter + 1'b1;
end
// -- Generate CKE_OUT
//always @(negedge sdram_clk or negedge sdram_rst_) begin
// if (!sdram_rst_)
// CKE_OUT <= 1'b0;
// else
// CKE_OUT <= CKE_IN && init_counter_half_done;
//end
// -- Generate PAA
// -- Wait at least 100us after providing stable sdram CLOCK signal
always @(posedge sdram_clk) begin
PAA <= init_counter_done;
end
// -- Generate SET_MODE
always @(posedge sdram_clk) begin
SET_MODE <= 1'b1;
end
endmodule /* module sdram_init (*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_2_V
`define SKY130_FD_SC_LP__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_4_V
`define SKY130_FD_SC_HD__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_4_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO.v
// Version : 2.4
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//-- The module designed to operate with 32 bit and 64 bit interfaces.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
)(
input user_clk,
input user_reset,
input user_lnk_up,
// AXIS
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
); // synthesis syn_hier = "hard"
// Local wires
wire req_compl;
wire compl_done;
wire pio_reset_n = user_lnk_up && !user_reset;
//
// PIO instance
//
PIO_EP #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) PIO_EP (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.req_compl_o(req_compl), // O
.compl_done_o(compl_done), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable ( cfg_bus_mstr_enable ) // I
);
//
// Turn-Off controller
//
PIO_TO_CTRL PIO_TO (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl_i( req_compl ), // I
.compl_done_i( compl_done ), // I
.cfg_to_turnoff( cfg_to_turnoff ), // I
.cfg_turnoff_ok( cfg_turnoff_ok ) // O
);
endmodule // PIO
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in4.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
|
//======================================================================
//
// fpga_entropy_core.v
// -------------------
// fpga entropy generation core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fpga_entropy_core(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire [31 : 0] opa,
input wire [31 : 0] opb,
input wire update,
output wire [31 : 0] rnd
);
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] shift_reg;
reg shift_we;
reg [31 : 0] rnd_reg;
reg [4 : 0] bit_ctr_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg bit_new;
wire [7 : 0] dout01;
wire [7 : 0] dout02;
wire [7 : 0] dout03;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign rnd = rnd_reg;
//----------------------------------------------------------------
// module instantiations.
//----------------------------------------------------------------
genvar i;
generate
for(i = 0 ; i < 8 ; i = i + 1) begin: oscillators
bp_osc #(.WIDTH(1)) osc01(.clk(clk),
.reset_n(reset_n),
.opa(opa[0]),
.opb(opb[0]),
.dout(dout01[i])
);
bp_osc #(.WIDTH(2)) osc02(.clk(clk),
.reset_n(reset_n),
.opa(opa[1 : 0]),
.opb(opb[1 : 0]),
.dout(dout02[i])
);
bp_osc #(.WIDTH(3)) osc03(.clk(clk),
.reset_n(reset_n),
.opa(opa[2 : 0]),
.opb(opb[2 : 0]),
.dout(dout03[i])
);
end
endgenerate
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
shift_reg <= 32'h00000000;
rnd_reg <= 32'h00000000;
bit_ctr_reg <= 5'h00;
end
else
begin
if (update)
begin
shift_reg <= {shift_reg[30 : 0], bit_new};
bit_ctr_reg <= bit_ctr_reg + 1'b1;
end
if (bit_ctr_reg == 5'h1f)
begin
rnd_reg <= shift_reg;
end
end
end // reg_update
//----------------------------------------------------------------
// rnd_gen
//
// Logic that implements the actual random bit value generator
// by mixing the oscillator outputs.
//----------------------------------------------------------------
always @*
begin : rnd_gen
reg osc1_mix;
reg osc2_mix;
reg osc3_mix;
osc1_mix = ^dout01;
osc2_mix = ^dout02;
osc3_mix = ^dout03;
bit_new = osc1_mix ^ osc2_mix ^ osc3_mix;
end
endmodule // fpga_entropy_core
//======================================================================
// EOF fpga_entropy_core.v
//======================================================================
|
//-------------------------------------------------------------------
//-- sectones_tb.v
//-- Banco de pruebas para el secuenciador de 4 notas
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
module secnotas_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Salidas de los canales
wire ch_out;
//-- Instanciar el componente y establecer el valor del divisor
//-- Se pone un valor bajo para simular (de lo contrario tardaria mucho)
secnotas #(.N0(2), .N1(3), .N2(4), .DUR(10))
dut(
.clk(clk),
.ch_out(ch_out)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("secnotas_tb.vcd");
$dumpvars(0, secnotas_tb);
# 200 $display("FIN de la simulacion");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_FUNCTIONAL_V
`define SKY130_FD_SC_HS__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__inv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_FUNCTIONAL_V |
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import Cpdt.CpdtTactics.
Require Extraction.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** printing <-- $\longleftarrow$ *)
(** %\part{Programming with Dependent Types}
\chapter{Subset Types and Variations}% *)
(** So far, we have seen many examples of what we might call "classical program verification." We write programs, write their specifications, and then prove that the programs satisfy their specifications. The programs that we have written in Coq have been normal functional programs that we could just as well have written in Haskell or ML. In this chapter, we start investigating uses of%\index{dependent types}% _dependent types_ to integrate programming, specification, and proving into a single phase. The techniques we will learn make it possible to reduce the cost of program verification dramatically. *)
(** * Introducing Subset Types *)
(** Let us consider several ways of implementing the natural number predecessor function. We start by displaying the definition from the standard library: *)
Print pred.
(** %\vspace{-.15in}% [[
pred = fun n : nat => match n with
| 0 => 0
| S u => u
end
: nat -> nat
]]
We can use a new command, %\index{Vernacular commands!Extraction}\index{program extraction}\index{extraction|see{program extraction}}%[Extraction], to produce an %\index{OCaml}%OCaml version of this function. *)
Extraction pred.
(** <<
(** val pred : nat -> nat **)
let pred = function
| O -> O
| S u -> u
>>
*)
(** Returning 0 as the predecessor of 0 can come across as somewhat of a hack. In some situations, we might like to be sure that we never try to take the predecessor of 0. We can enforce this by giving [pred] a stronger, dependent type. *)
Lemma zgtz : 0 > 0 -> False.
crush.
Qed.
Definition pred_strong1 (n : nat) : n > 0 -> nat :=
match n with
| O => fun pf : 0 > 0 => match zgtz pf with end
| S n' => fun _ => n'
end.
(** We expand the type of [pred] to include a _proof_ that its argument [n] is greater than 0. When [n] is 0, we use the proof to derive a contradiction, which we can use to build a value of any type via a vacuous pattern match. When [n] is a successor, we have no need for the proof and just return the answer. The proof argument can be said to have a _dependent_ type, because its type depends on the _value_ of the argument [n].
Coq's [Eval] command can execute particular invocations of [pred_strong1] just as easily as it can execute more traditional functional programs. Note that Coq has decided that argument [n] of [pred_strong1] can be made _implicit_, since it can be deduced from the type of the second argument, so we need not write [n] in function calls. *)
Theorem two_gt0 : 2 > 0.
crush.
Qed.
Eval compute in pred_strong1 two_gt0.
(** %\vspace{-.15in}% [[
= 1
: nat
]]
One aspect in particular of the definition of [pred_strong1] may be surprising. We took advantage of [Definition]'s syntactic sugar for defining function arguments in the case of [n], but we bound the proofs later with explicit [fun] expressions. Let us see what happens if we write this function in the way that at first seems most natural.
%\vspace{-.15in}%[[
Definition pred_strong1' (n : nat) (pf : n > 0) : nat :=
match n with
| O => match zgtz pf with end
| S n' => n'
end.
]]
<<
Error: In environment
n : nat
pf : n > 0
The term "pf" has type "n > 0" while it is expected to have type
"0 > 0"
>>
The term [zgtz pf] fails to type-check. Somehow the type checker has failed to take into account information that follows from which [match] branch that term appears in. The problem is that, by default, [match] does not let us use such implied information. To get refined typing, we must always rely on [match] annotations, either written explicitly or inferred.
In this case, we must use a [return] annotation to declare the relationship between the _value_ of the [match] discriminee and the _type_ of the result. There is no annotation that lets us declare a relationship between the discriminee and the type of a variable that is already in scope; hence, we delay the binding of [pf], so that we can use the [return] annotation to express the needed relationship.
We are lucky that Coq's heuristics infer the [return] clause (specifically, [return n > 0 -> nat]) for us in the definition of [pred_strong1], leading to the following elaborated code: *)
Definition pred_strong1' (n : nat) : n > 0 -> nat :=
match n return n > 0 -> nat with
| O => fun pf : 0 > 0 => match zgtz pf with end
| S n' => fun _ => n'
end.
(** By making explicit the functional relationship between value [n] and the result type of the [match], we guide Coq toward proper type checking. The clause for this example follows by simple copying of the original annotation on the definition. In general, however, the [match] annotation inference problem is undecidable. The known undecidable problem of%\index{higher-order unification}% _higher-order unification_ %\cite{HOU}% reduces to the [match] type inference problem. Over time, Coq is enhanced with more and more heuristics to get around this problem, but there must always exist [match]es whose types Coq cannot infer without annotations.
Let us now take a look at the OCaml code Coq generates for [pred_strong1]. *)
Extraction pred_strong1.
(**
<<
(** val pred_strong1 : nat -> nat **)
let pred_strong1 = function
| O -> assert false (* absurd case *)
| S n' -> n'
>>
*)
(** The proof argument has disappeared! We get exactly the OCaml code we would have written manually. This is our first demonstration of the main technically interesting feature of Coq program extraction: proofs are erased systematically.
%\medskip%
We can reimplement our dependently typed [pred] based on%\index{subset types}% _subset types_, defined in the standard library with the type family %\index{Gallina terms!sig}%[sig]. *)
(* begin hide *)
(* begin thide *)
Definition bar := ex.
(* end thide *)
(* end hide *)
Print sig.
(** %\vspace{-.15in}% [[
Inductive sig (A : Type) (P : A -> Prop) : Type :=
exist : forall x : A, P x -> sig P
]]
The family [sig] is a Curry-Howard twin of [ex], except that [sig] is in [Type], while [ex] is in [Prop]. That means that [sig] values can survive extraction, while [ex] proofs will always be erased. The actual details of extraction of [sig]s are more subtle, as we will see shortly.
We rewrite [pred_strong1], using some syntactic sugar for subset types. *)
Locate "{ _ : _ | _ }".
(** %\vspace{-.15in}% [[
Notation
"{ x : A | P }" := sig (fun x : A => P)
]]
*)
Definition pred_strong2 (s : {n : nat | n > 0}) : nat :=
match s with
| exist O pf => match zgtz pf with end
| exist (S n') _ => n'
end.
(** To build a value of a subset type, we use the [exist] constructor, and the details of how to do that follow from the output of our earlier [Print sig] command, where we elided the extra information that parameter [A] is implicit. We need an extra [_] here and not in the definition of [pred_strong2] because _parameters_ of inductive types (like the predicate [P] for [sig]) are not mentioned in pattern matching, but _are_ mentioned in construction of terms (if they are not marked as implicit arguments). *)
Eval compute in pred_strong2 (exist _ 2 two_gt0).
(** %\vspace{-.15in}% [[
= 1
: nat
]]
*)
Extraction pred_strong2.
(**
<<
(** val pred_strong2 : nat -> nat **)
let pred_strong2 = function
| O -> assert false (* absurd case *)
| S n' -> n'
>>
We arrive at the same OCaml code as was extracted from [pred_strong1], which may seem surprising at first. The reason is that a value of [sig] is a pair of two pieces, a value and a proof about it. Extraction erases the proof, which reduces the constructor [exist] of [sig] to taking just a single argument. An optimization eliminates uses of datatypes with single constructors taking single arguments, and we arrive back where we started.
We can continue on in the process of refining [pred]'s type. Let us change its result type to capture that the output is really the predecessor of the input. *)
Definition pred_strong3 (s : {n : nat | n > 0}) : {m : nat | proj1_sig s = S m} :=
match s return {m : nat | proj1_sig s = S m} with
| exist 0 pf => match zgtz pf with end
| exist (S n') pf => exist _ n' (eq_refl _)
end.
(* begin hide *)
(* begin thide *)
Definition ugh := lt.
(* end thide *)
(* end hide *)
Eval compute in pred_strong3 (exist _ 2 two_gt0).
(** %\vspace{-.15in}% [[
= exist (fun m : nat => 2 = S m) 1 (eq_refl 2)
: {m : nat | proj1_sig (exist (lt 0) 2 two_gt0) = S m}
]]
*)
(* begin hide *)
(* begin thide *)
Definition pred_strong := 0.
(* end thide *)
(* end hide *)
(** A value in a subset type can be thought of as a%\index{dependent pair}% _dependent pair_ (or%\index{sigma type}% _sigma type_) of a base value and a proof about it. The function %\index{Gallina terms!proj1\_sig}%[proj1_sig] extracts the first component of the pair. It turns out that we need to include an explicit [return] clause here, since Coq's heuristics are not smart enough to propagate the result type that we wrote earlier.
By now, the reader is probably ready to believe that the new [pred_strong] leads to the same OCaml code as we have seen several times so far, and Coq does not disappoint. *)
Extraction pred_strong3.
(**
<<
(** val pred_strong3 : nat -> nat **)
let pred_strong3 = function
| O -> assert false (* absurd case *)
| S n' -> n'
>>
We have managed to reach a type that is, in a formal sense, the most expressive possible for [pred]. Any other implementation of the same type must have the same input-output behavior. However, there is still room for improvement in making this kind of code easier to write. Here is a version that takes advantage of tactic-based theorem proving. We switch back to passing a separate proof argument instead of using a subset type for the function's input, because this leads to cleaner code. (Recall that [False_rec] is the [Set]-level induction principle for [False], which can be used to produce a value in any [Set] given a proof of [False].) *)
Definition pred_strong4 : forall n : nat, n > 0 -> {m : nat | n = S m}.
refine (fun n =>
match n with
| O => fun _ => False_rec _ _
| S n' => fun _ => exist _ n' _
end).
(* begin thide *)
(** We build [pred_strong4] using tactic-based proving, beginning with a [Definition] command that ends in a period before a definition is given. Such a command enters the interactive proving mode, with the type given for the new identifier as our proof goal. It may seem strange to change perspective so implicitly between programming and proving, but recall that programs and proofs are two sides of the same coin in Coq, thanks to the Curry-Howard correspondence.
We do most of the work with the %\index{tactics!refine}%[refine] tactic, to which we pass a partial "proof" of the type we are trying to prove. There may be some pieces left to fill in, indicated by underscores. Any underscore that Coq cannot reconstruct with type inference is added as a proof subgoal. In this case, we have two subgoals:
[[
2 subgoals
n : nat
_ : 0 > 0
============================
False
subgoal 2 is
S n' = S n'
]]
We can see that the first subgoal comes from the second underscore passed to [False_rec], and the second subgoal comes from the second underscore passed to [exist]. In the first case, we see that, though we bound the proof variable with an underscore, it is still available in our proof context. It is hard to refer to underscore-named variables in manual proofs, but automation makes short work of them. Both subgoals are easy to discharge that way, so let us back up and ask to prove all subgoals automatically. *)
Undo.
refine (fun n =>
match n with
| O => fun _ => False_rec _ _
| S n' => fun _ => exist _ n' _
end); crush.
(* end thide *)
Defined.
(** We end the "proof" with %\index{Vernacular commands!Defined}%[Defined] instead of [Qed], so that the definition we constructed remains visible. This contrasts to the case of ending a proof with [Qed], where the details of the proof are hidden afterward. (More formally, [Defined] marks an identifier as%\index{transparent}% _transparent_, allowing it to be unfolded; while [Qed] marks an identifier as%\index{opaque}% _opaque_, preventing unfolding.) Let us see what our proof script constructed. *)
Print pred_strong4.
(** %\vspace{-.15in}% [[
pred_strong4 =
fun n : nat =>
match n as n0 return (n0 > 0 -> {m : nat | n0 = S m}) with
| 0 =>
fun _ : 0 > 0 =>
False_rec {m : nat | 0 = S m}
(Bool.diff_false_true
(Bool.absurd_eq_true false
(Bool.diff_false_true
(Bool.absurd_eq_true false (pred_strong4_subproof n _)))))
| S n' =>
fun _ : S n' > 0 =>
exist (fun m : nat => S n' = S m) n' (eq_refl (S n'))
end
: forall n : nat, n > 0 -> {m : nat | n = S m}
]]
We see the code we entered, with some proofs filled in. The first proof obligation, the second argument to [False_rec], is filled in with a nasty-looking proof term that we can be glad we did not enter by hand. The second proof obligation is a simple reflexivity proof. *)
Eval compute in pred_strong4 two_gt0.
(** %\vspace{-.15in}% [[
= exist (fun m : nat => 2 = S m) 1 (eq_refl 2)
: {m : nat | 2 = S m}
]]
A tactic modifier called %\index{tactics!abstract}%[abstract] can be helpful for producing shorter terms, by automatically abstracting subgoals into named lemmas. *)
(* begin thide *)
Definition pred_strong4' : forall n : nat, n > 0 -> {m : nat | n = S m}.
refine (fun n =>
match n with
| O => fun _ => False_rec _ _
| S n' => fun _ => exist _ n' _
end); abstract crush.
Defined.
Print pred_strong4'.
(* end thide *)
(** %\vspace{-.15in}% [[
pred_strong4' =
fun n : nat =>
match n as n0 return (n0 > 0 -> {m : nat | n0 = S m}) with
| 0 =>
fun _H : 0 > 0 =>
False_rec {m : nat | 0 = S m} (pred_strong4'_subproof n _H)
| S n' =>
fun _H : S n' > 0 =>
exist (fun m : nat => S n' = S m) n' (pred_strong4'_subproof0 n _H)
end
: forall n : nat, n > 0 -> {m : nat | n = S m}
]]
We are almost done with the ideal implementation of dependent predecessor. We can use Coq's syntax extension facility to arrive at code with almost no complexity beyond a Haskell or ML program with a complete specification in a comment. In this book, we will not dwell on the details of syntax extensions; the Coq manual gives a straightforward introduction to them. *)
Notation "!" := (False_rec _ _).
Notation "[ e ]" := (exist _ e _).
Definition pred_strong5 : forall n : nat, n > 0 -> {m : nat | n = S m}.
refine (fun n =>
match n with
| O => fun _ => !
| S n' => fun _ => [n']
end); crush.
Defined.
(** By default, notations are also used in pretty-printing terms, including results of evaluation. *)
Eval compute in pred_strong5 two_gt0.
(** %\vspace{-.15in}% [[
= [1]
: {m : nat | 2 = S m}
]]
One other alternative is worth demonstrating. Recent Coq versions include a facility called %\index{Program}%[Program] that streamlines this style of definition. Here is a complete implementation using [Program].%\index{Vernacular commands!Obligation Tactic}\index{Vernacular commands!Program Definition}% *)
Obligation Tactic := crush.
Program Definition pred_strong6 (n : nat) (_ : n > 0) : {m : nat | n = S m} :=
match n with
| O => _
| S n' => n'
end.
(** Printing the resulting definition of [pred_strong6] yields a term very similar to what we built with [refine]. [Program] can save time in writing programs that use subset types. Nonetheless, [refine] is often just as effective, and [refine] gives more control over the form the final term takes, which can be useful when you want to prove additional theorems about your definition. [Program] will sometimes insert type casts that can complicate theorem proving. *)
Eval compute in pred_strong6 two_gt0.
(** %\vspace{-.15in}% [[
= [1]
: {m : nat | 2 = S m}
]]
In this case, we see that the new definition yields the same computational behavior as before. *)
(** * Decidable Proposition Types *)
(** There is another type in the standard library that captures the idea of program values that indicate which of two propositions is true.%\index{Gallina terms!sumbool}% *)
Print sumbool.
(** %\vspace{-.15in}% [[
Inductive sumbool (A : Prop) (B : Prop) : Set :=
left : A -> {A} + {B} | right : B -> {A} + {B}
]]
Here, the constructors of [sumbool] have types written in terms of a registered notation for [sumbool], such that the result type of each constructor desugars to [sumbool A B]. We can define some notations of our own to make working with [sumbool] more convenient. *)
Notation "'Yes'" := (left _ _).
Notation "'No'" := (right _ _).
Notation "'Reduce' x" := (if x then Yes else No) (at level 50).
(** The %\coqdocnotation{%#<tt>#Reduce#</tt>#%}% notation is notable because it demonstrates how [if] is overloaded in Coq. The [if] form actually works when the test expression has any two-constructor inductive type. Moreover, in the [then] and [else] branches, the appropriate constructor arguments are bound. This is important when working with [sumbool]s, when we want to have the proof stored in the test expression available when proving the proof obligations generated in the appropriate branch.
Now we can write [eq_nat_dec], which compares two natural numbers, returning either a proof of their equality or a proof of their inequality. *)
Definition eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
refine (fix f (n m : nat) : {n = m} + {n <> m} :=
match n, m with
| O, O => Yes
| S n', S m' => Reduce (f n' m')
| _, _ => No
end); congruence.
Defined.
Eval compute in eq_nat_dec 2 2.
(** %\vspace{-.15in}% [[
= Yes
: {2 = 2} + {2 <> 2}
]]
*)
Eval compute in eq_nat_dec 2 3.
(** %\vspace{-.15in}% [[
= No
: {2 = 3} + {2 <> 3}
]]
Note that the %\coqdocnotation{%#<tt>#Yes#</tt>#%}% and %\coqdocnotation{%#<tt>#No#</tt>#%}% notations are hiding proofs establishing the correctness of the outputs.
Our definition extracts to reasonable OCaml code. *)
Extraction eq_nat_dec.
(**
<<
(** val eq_nat_dec : nat -> nat -> sumbool **)
let rec eq_nat_dec n m =
match n with
| O -> (match m with
| O -> Left
| S n0 -> Right)
| S n' -> (match m with
| O -> Right
| S m' -> eq_nat_dec n' m')
>>
Proving this kind of decidable equality result is so common that Coq comes with a tactic for automating it.%\index{tactics!decide equality}% *)
Definition eq_nat_dec' (n m : nat) : {n = m} + {n <> m}.
decide equality.
Defined.
(** Curious readers can verify that the [decide equality] version extracts to the same OCaml code as our more manual version does. That OCaml code had one undesirable property, which is that it uses <<Left>> and <<Right>> constructors instead of the Boolean values built into OCaml. We can fix this, by using Coq's facility for mapping Coq inductive types to OCaml variant types.%\index{Vernacular commands!Extract Inductive}% *)
Extract Inductive sumbool => "bool" ["true" "false"].
Extraction eq_nat_dec'.
(**
<<
(** val eq_nat_dec' : nat -> nat -> bool **)
let rec eq_nat_dec' n m0 =
match n with
| O -> (match m0 with
| O -> true
| S n0 -> false)
| S n0 -> (match m0 with
| O -> false
| S n1 -> eq_nat_dec' n0 n1)
>>
*)
(** %\smallskip%
We can build "smart" versions of the usual Boolean operators and put them to good use in certified programming. For instance, here is a [sumbool] version of Boolean "or." *)
(* EX: Write a function that decides if an element belongs to a list. *)
(* begin thide *)
Notation "x || y" := (if x then Yes else Reduce y).
(** Let us use it for building a function that decides list membership. We need to assume the existence of an equality decision procedure for the type of list elements. *)
Section In_dec.
Variable A : Set.
Variable A_eq_dec : forall x y : A, {x = y} + {x <> y}.
(** The final function is easy to write using the techniques we have developed so far. *)
Definition In_dec : forall (x : A) (ls : list A), {In x ls} + {~ In x ls}.
refine (fix f (x : A) (ls : list A) : {In x ls} + {~ In x ls} :=
match ls with
| nil => No
| x' :: ls' => A_eq_dec x x' || f x ls'
end); crush.
Defined.
End In_dec.
Eval compute in In_dec eq_nat_dec 2 (1 :: 2 :: nil).
(** %\vspace{-.15in}% [[
= Yes
: {In 2 (1 :: 2 :: nil)} + { ~ In 2 (1 :: 2 :: nil)}
]]
*)
Eval compute in In_dec eq_nat_dec 3 (1 :: 2 :: nil).
(** %\vspace{-.15in}% [[
= No
: {In 3 (1 :: 2 :: nil)} + { ~ In 3 (1 :: 2 :: nil)}
]]
The [In_dec] function has a reasonable extraction to OCaml. *)
Extraction In_dec.
(* end thide *)
(**
<<
(** val in_dec : ('a1 -> 'a1 -> bool) -> 'a1 -> 'a1 list -> bool **)
let rec in_dec a_eq_dec x = function
| Nil -> false
| Cons (x', ls') ->
(match a_eq_dec x x' with
| true -> true
| false -> in_dec a_eq_dec x ls')
>>
This is more or the less code for the corresponding function from the OCaml standard library. *)
(** * Partial Subset Types *)
(** Our final implementation of dependent predecessor used a very specific argument type to ensure that execution could always complete normally. Sometimes we want to allow execution to fail, and we want a more principled way of signaling failure than returning a default value, as [pred] does for [0]. One approach is to define this type family %\index{Gallina terms!maybe}%[maybe], which is a version of [sig] that allows obligation-free failure. *)
Inductive maybe (A : Set) (P : A -> Prop) : Set :=
| Unknown : maybe P
| Found : forall x : A, P x -> maybe P.
(** We can define some new notations, analogous to those we defined for subset types. *)
Notation "{{ x | P }}" := (maybe (fun x => P)).
Notation "??" := (Unknown _).
Notation "[| x |]" := (Found _ x _).
(** Now our next version of [pred] is trivial to write. *)
Definition pred_strong7 : forall n : nat, {{m | n = S m}}.
refine (fun n =>
match n return {{m | n = S m}} with
| O => ??
| S n' => [|n'|]
end); trivial.
Defined.
Eval compute in pred_strong7 2.
(** %\vspace{-.15in}% [[
= [|1|]
: {{m | 2 = S m}}
]]
*)
Eval compute in pred_strong7 0.
(** %\vspace{-.15in}% [[
= ??
: {{m | 0 = S m}}
]]
Because we used [maybe], one valid implementation of the type we gave [pred_strong7] would return [??] in every case. We can strengthen the type to rule out such vacuous implementations, and the type family %\index{Gallina terms!sumor}%[sumor] from the standard library provides the easiest starting point. For type [A] and proposition [B], [A + {B}] desugars to [sumor A B], whose values are either values of [A] or proofs of [B]. *)
Print sumor.
(** %\vspace{-.15in}% [[
Inductive sumor (A : Type) (B : Prop) : Type :=
inleft : A -> A + {B} | inright : B -> A + {B}
]]
We add notations for easy use of the [sumor] constructors. The second notation is specialized to [sumor]s whose [A] parameters are instantiated with regular subset types, since this is how we will use [sumor] below. *)
Notation "!!" := (inright _ _).
Notation "[|| x ||]" := (inleft _ [x]).
(** Now we are ready to give the final version of possibly failing predecessor. The [sumor]-based type that we use is maximally expressive; any implementation of the type has the same input-output behavior. *)
Definition pred_strong8 : forall n : nat, {m : nat | n = S m} + {n = 0}.
refine (fun n =>
match n with
| O => !!
| S n' => [||n'||]
end); trivial.
Defined.
Eval compute in pred_strong8 2.
(** %\vspace{-.15in}% [[
= [||1||]
: {m : nat | 2 = S m} + {2 = 0}
]]
*)
Eval compute in pred_strong8 0.
(** %\vspace{-.15in}% [[
= !!
: {m : nat | 0 = S m} + {0 = 0}
]]
*)
(** As with our other maximally expressive [pred] function, we arrive at quite simple output values, thanks to notations. *)
(** * Monadic Notations *)
(** We can treat [maybe] like a monad%~\cite{Monads}\index{monad}\index{failure monad}%, in the same way that the Haskell <<Maybe>> type is interpreted as a failure monad. Our [maybe] has the wrong type to be a literal monad, but a "bind"-like notation will still be helpful. %Note that the notation definition uses an ASCII \texttt{<-}, while later code uses (in this rendering) a nicer left arrow $\leftarrow$.% *)
Notation "x <- e1 ; e2" := (match e1 with
| Unknown => ??
| Found x _ => e2
end)
(right associativity, at level 60).
(** The meaning of [x <- e1; e2] is: First run [e1]. If it fails to find an answer, then announce failure for our derived computation, too. If [e1] _does_ find an answer, pass that answer on to [e2] to find the final result. The variable [x] can be considered bound in [e2].
This notation is very helpful for composing richly typed procedures. For instance, here is a very simple implementation of a function to take the predecessors of two naturals at once. *)
(* EX: Write a function that tries to compute predecessors of two [nat]s at once. *)
(* begin thide *)
Definition doublePred : forall n1 n2 : nat, {{p | n1 = S (fst p) /\ n2 = S (snd p)}}.
refine (fun n1 n2 =>
m1 <- pred_strong7 n1;
m2 <- pred_strong7 n2;
[|(m1, m2)|]); tauto.
Defined.
(* end thide *)
(** We can build a [sumor] version of the "bind" notation and use it to write a similarly straightforward version of this function. %Again, the notation definition exposes the ASCII syntax with an operator \texttt{<-{}-}, while the later code uses a nicer long left arrow $\longleftarrow$.% *)
(** %\def\indash{-}\catcode`-=13\def-{\indash\kern0pt }% *)
Notation "x <-- e1 ; e2" := (match e1 with
| inright _ => !!
| inleft (exist x _) => e2
end)
(right associativity, at level 60).
(** %\catcode`-=12% *)(* *)
(** printing * $\times$ *)
(* EX: Write a more expressively typed version of the last exercise. *)
(* begin thide *)
Definition doublePred' : forall n1 n2 : nat,
{p : nat * nat | n1 = S (fst p) /\ n2 = S (snd p)}
+ {n1 = 0 \/ n2 = 0}.
refine (fun n1 n2 =>
m1 <-- pred_strong8 n1;
m2 <-- pred_strong8 n2;
[||(m1, m2)||]); tauto.
Defined.
(* end thide *)
(** This example demonstrates how judicious selection of notations can hide complexities in the rich types of programs. *)
(** * A Type-Checking Example *)
(** We can apply these specification types to build a certified type checker for a simple expression language. *)
Inductive exp : Set :=
| Nat : nat -> exp
| Plus : exp -> exp -> exp
| Bool : bool -> exp
| And : exp -> exp -> exp.
(** We define a simple language of types and its typing rules, in the style introduced in Chapter 4. *)
Inductive type : Set := TNat | TBool.
Inductive hasType : exp -> type -> Prop :=
| HtNat : forall n,
hasType (Nat n) TNat
| HtPlus : forall e1 e2,
hasType e1 TNat
-> hasType e2 TNat
-> hasType (Plus e1 e2) TNat
| HtBool : forall b,
hasType (Bool b) TBool
| HtAnd : forall e1 e2,
hasType e1 TBool
-> hasType e2 TBool
-> hasType (And e1 e2) TBool.
(** It will be helpful to have a function for comparing two types. We build one using [decide equality]. *)
(* begin thide *)
Definition eq_type_dec : forall t1 t2 : type, {t1 = t2} + {t1 <> t2}.
decide equality.
Defined.
(** Another notation complements the monadic notation for [maybe] that we defined earlier. Sometimes we want to include "assertions" in our procedures. That is, we want to run a decision procedure and fail if it fails; otherwise, we want to continue, with the proof that it produced made available to us. This infix notation captures that idea, for a procedure that returns an arbitrary two-constructor type. *)
Notation "e1 ;; e2" := (if e1 then e2 else ??)
(right associativity, at level 60).
(** With that notation defined, we can implement a [typeCheck] function, whose code is only more complex than what we would write in ML because it needs to include some extra type annotations. Every [[|e|]] expression adds a [hasType] proof obligation, and [crush] makes short work of them when we add [hasType]'s constructors as hints. *)
(* end thide *)
Definition typeCheck : forall e : exp, {{t | hasType e t}}.
(* begin thide *)
Hint Constructors hasType.
refine (fix F (e : exp) : {{t | hasType e t}} :=
match e return {{t | hasType e t}} with
| Nat _ => [|TNat|]
| Plus e1 e2 =>
t1 <- F e1;
t2 <- F e2;
eq_type_dec t1 TNat;;
eq_type_dec t2 TNat;;
[|TNat|]
| Bool _ => [|TBool|]
| And e1 e2 =>
t1 <- F e1;
t2 <- F e2;
eq_type_dec t1 TBool;;
eq_type_dec t2 TBool;;
[|TBool|]
end); crush.
(* end thide *)
Defined.
(** Despite manipulating proofs, our type checker is easy to run. *)
Eval simpl in typeCheck (Nat 0).
(** %\vspace{-.15in}% [[
= [|TNat|]
: {{t | hasType (Nat 0) t}}
]]
*)
Eval simpl in typeCheck (Plus (Nat 1) (Nat 2)).
(** %\vspace{-.15in}% [[
= [|TNat|]
: {{t | hasType (Plus (Nat 1) (Nat 2)) t}}
]]
*)
Eval simpl in typeCheck (Plus (Nat 1) (Bool false)).
(** %\vspace{-.15in}% [[
= ??
: {{t | hasType (Plus (Nat 1) (Bool false)) t}}
]]
The type checker also extracts to some reasonable OCaml code. *)
Extraction typeCheck.
(**
<<
(** val typeCheck : exp -> type0 maybe **)
let rec typeCheck = function
| Nat n -> Found TNat
| Plus (e1, e2) ->
(match typeCheck e1 with
| Unknown -> Unknown
| Found t1 ->
(match typeCheck e2 with
| Unknown -> Unknown
| Found t2 ->
(match eq_type_dec t1 TNat with
| true ->
(match eq_type_dec t2 TNat with
| true -> Found TNat
| false -> Unknown)
| false -> Unknown)))
| Bool b -> Found TBool
| And (e1, e2) ->
(match typeCheck e1 with
| Unknown -> Unknown
| Found t1 ->
(match typeCheck e2 with
| Unknown -> Unknown
| Found t2 ->
(match eq_type_dec t1 TBool with
| true ->
(match eq_type_dec t2 TBool with
| true -> Found TBool
| false -> Unknown)
| false -> Unknown)))
>>
*)
(** %\smallskip%
We can adapt this implementation to use [sumor], so that we know our type-checker only fails on ill-typed inputs. First, we define an analogue to the "assertion" notation. *)
(* begin thide *)
Notation "e1 ;;; e2" := (if e1 then e2 else !!)
(right associativity, at level 60).
(** Next, we prove a helpful lemma, which states that a given expression can have at most one type. *)
Lemma hasType_det : forall e t1,
hasType e t1
-> forall t2, hasType e t2
-> t1 = t2.
induction 1; inversion 1; crush.
Qed.
(** Now we can define the type-checker. Its type expresses that it only fails on untypable expressions. *)
(* end thide *)
Definition typeCheck' : forall e : exp, {t : type | hasType e t} + {forall t, ~ hasType e t}.
(* begin thide *)
Hint Constructors hasType.
(** We register all of the typing rules as hints. *)
Hint Resolve hasType_det.
(** The lemma [hasType_det] will also be useful for proving proof obligations with contradictory contexts. Since its statement includes [forall]-bound variables that do not appear in its conclusion, only [eauto] will apply this hint. *)
(** Finally, the implementation of [typeCheck] can be transcribed literally, simply switching notations as needed. *)
refine (fix F (e : exp) : {t : type | hasType e t} + {forall t, ~ hasType e t} :=
match e return {t : type | hasType e t} + {forall t, ~ hasType e t} with
| Nat _ => [||TNat||]
| Plus e1 e2 =>
t1 <-- F e1;
t2 <-- F e2;
eq_type_dec t1 TNat;;;
eq_type_dec t2 TNat;;;
[||TNat||]
| Bool _ => [||TBool||]
| And e1 e2 =>
t1 <-- F e1;
t2 <-- F e2;
eq_type_dec t1 TBool;;;
eq_type_dec t2 TBool;;;
[||TBool||]
end); clear F; crush' tt hasType; eauto.
(** We clear [F], the local name for the recursive function, to avoid strange proofs that refer to recursive calls that we never make. Such a step is usually warranted when defining a recursive function with [refine]. The [crush] variant %\index{tactics!crush'}%[crush'] helps us by performing automatic inversion on instances of the predicates specified in its second argument. Once we throw in [eauto] to apply [hasType_det] for us, we have discharged all the subgoals. *)
(* end thide *)
Defined.
(** The short implementation here hides just how time-saving automation is. Every use of one of the notations adds a proof obligation, giving us 12 in total. Most of these obligations require multiple inversions and either uses of [hasType_det] or applications of [hasType] rules.
Our new function remains easy to test: *)
Eval simpl in typeCheck' (Nat 0).
(** %\vspace{-.15in}% [[
= [||TNat||]
: {t : type | hasType (Nat 0) t} +
{(forall t : type, ~ hasType (Nat 0) t)}
]]
*)
Eval simpl in typeCheck' (Plus (Nat 1) (Nat 2)).
(** %\vspace{-.15in}% [[
= [||TNat||]
: {t : type | hasType (Plus (Nat 1) (Nat 2)) t} +
{(forall t : type, ~ hasType (Plus (Nat 1) (Nat 2)) t)}
]]
*)
Eval simpl in typeCheck' (Plus (Nat 1) (Bool false)).
(** %\vspace{-.15in}% [[
= !!
: {t : type | hasType (Plus (Nat 1) (Bool false)) t} +
{(forall t : type, ~ hasType (Plus (Nat 1) (Bool false)) t)}
]]
The results of simplifying calls to [typeCheck'] look deceptively similar to the results for [typeCheck], but now the types of the results provide more information. *)
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
module ram #(
parameter DATA = 1188,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
initial begin : init
integer i;
for(i = 0; i < (2**ADDR); i = i + 1)
mem[i] = 0;
end
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 1023;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
(** * Norm: Normalization of STLC *)
(* Chapter maintained by Andrew Tolmach *)
(* (Based on TAPL Ch. 12.) *)
Require Export Smallstep.
Hint Constructors multi.
(**
(This chapter is optional.)
In this chapter, we consider another fundamental theoretical property
of the simply typed lambda-calculus: the fact that the evaluation of a
well-typed program is guaranteed to halt in a finite number of
steps---i.e., every well-typed term is _normalizable_.
Unlike the type-safety properties we have considered so far, the
normalization property does not extend to full-blown programming
languages, because these languages nearly always extend the simply
typed lambda-calculus with constructs, such as general recursion
(as we discussed in the MoreStlc chapter) or recursive types, that can
be used to write nonterminating programs. However, the issue of
normalization reappears at the level of _types_ when we consider the
metatheory of polymorphic versions of the lambda calculus such as
F_omega: in this system, the language of types effectively contains a
copy of the simply typed lambda-calculus, and the termination of the
typechecking algorithm will hinge on the fact that a ``normalization''
operation on type expressions is guaranteed to terminate.
Another reason for studying normalization proofs is that they are some
of the most beautiful---and mind-blowing---mathematics to be found in
the type theory literature, often (as here) involving the fundamental
proof technique of _logical relations_.
The calculus we shall consider here is the simply typed
lambda-calculus over a single base type [bool] and with pairs. We'll
give full details of the development for the basic lambda-calculus
terms treating [bool] as an uninterpreted base type, and leave the
extension to the boolean operators and pairs to the reader. Even for
the base calculus, normalization is not entirely trivial to prove,
since each reduction of a term can duplicate redexes in subterms. *)
(** **** Exercise: 1 star *)
(** Where do we fail if we attempt to prove normalization by a
straightforward induction on the size of a well-typed term? *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Language *)
(** We begin by repeating the relevant language definition, which is
similar to those in the MoreStlc chapter, and supporting results
including type preservation and step determinism. (We won't need
progress.) You may just wish to skip down to the Normalization
section... *)
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty
| TProd : ty -> ty -> ty
.
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* booleans *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(* i.e., [if t0 then t1 else t2] *)
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tpair t1 t2 => tpair (subst x s t1) (subst x s t2)
| tfst t1 => tfst (subst x s t1)
| tsnd t1 => tsnd (subst x s t1)
| ttrue => ttrue
| tfalse => tfalse
| tif t0 t1 t2 => tif (subst x s t0) (subst x s t1) (subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
| v_true : value ttrue
| v_false : value tfalse
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* booleans *)
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t0 t0' t1 t2,
t0 ==> t0' ->
(tif t0 t1 t2) ==> (tif t0' t1 t2)
where "t1 '==>' t2" := (step t1 t2).
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
Notation step_normal_form := (normal_form step).
Lemma value__normal : forall t, value t -> step_normal_form t.
Proof with eauto.
intros t H; induction H; intros [t' ST]; inversion ST...
Qed.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
has_type Gamma t1 T1 ->
has_type Gamma t2 T2 ->
has_type Gamma (tpair t1 t2) (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tfst t) T1
| T_Snd : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tsnd t) T2
(* booleans *)
| T_True : forall Gamma,
has_type Gamma ttrue TBool
| T_False : forall Gamma,
has_type Gamma tfalse TBool
| T_If : forall Gamma t0 t1 t2 T,
has_type Gamma t0 TBool ->
has_type Gamma t1 T ->
has_type Gamma t2 T ->
has_type Gamma (tif t0 t1 t2) T
.
Hint Constructors has_type.
Hint Extern 2 (has_type _ (tapp _ _) _) => eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* booleans *)
| afi_if0 : forall x t0 t1 t2,
appears_free_in x t0 ->
appears_free_in x (tif t0 t1 t2)
| afi_if1 : forall x t0 t1 t2,
appears_free_in x t1 ->
appears_free_in x (tif t0 t1 t2)
| afi_if2 : forall x t0 t1 t2,
appears_free_in x t2 ->
appears_free_in x (tif t0 t1 t2)
.
Hint Constructors appears_free_in.
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend. destruct (eq_id_dec x y)...
- (* T_Pair *)
apply T_Pair...
- (* T_If *)
eapply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; inversion Hafi; subst...
- (* T_Abs *)
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Qed.
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
intros. unfold closed. intros x H1.
destruct (free_in_context _ _ _ _ H1 H) as [T' C].
inversion C. Qed.
(* ###################################################################### *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- ([x:=v]t) S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
induction t;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
- (* tvar *)
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
+ (* x=y *)
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
- (* tabs *)
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
+ (* x=y *)
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
+ (* x<>y *)
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
+ (* ST_AppAbs *)
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
- (* T_Fst *)
inversion HT...
- (* T_Snd *)
inversion HT...
Qed.
(** [] *)
(* ###################################################################### *)
(** *** Determinism *)
Lemma step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Normalization *)
(** Now for the actual normalization proof.
Our goal is to prove that every well-typed term evaluates to a
normal form. In fact, it turns out to be convenient to prove
something slightly stronger, namely that every well-typed term
evaluates to a _value_. This follows from the weaker property
anyway via the Progress lemma (why?) but otherwise we don't need
Progress, and we didn't bother re-proving it above.
Here's the key definition: *)
Definition halts (t:tm) : Prop := exists t', t ==>* t' /\ value t'.
(** A trivial fact: *)
Lemma value_halts : forall v, value v -> halts v.
Proof.
intros v H. unfold halts.
exists v. split.
apply multi_refl.
assumption.
Qed.
(** The key issue in the normalization proof (as in many proofs by
induction) is finding a strong enough induction hypothesis. To this
end, we begin by defining, for each type [T], a set [R_T] of closed
terms of type [T]. We will specify these sets using a relation [R]
and write [R T t] when [t] is in [R_T]. (The sets [R_T] are sometimes
called _saturated sets_ or _reducibility candidates_.)
Here is the definition of [R] for the base language:
- [R bool t] iff [t] is a closed term of type [bool] and [t] halts in a value
- [R (T1 -> T2) t] iff [t] is a closed term of type [T1 -> T2] and [t] halts
in a value _and_ for any term [s] such that [R T1 s], we have [R
T2 (t s)]. *)
(** This definition gives us the strengthened induction hypothesis that we
need. Our primary goal is to show that all _programs_ ---i.e., all
closed terms of base type---halt. But closed terms of base type can
contain subterms of functional type, so we need to know something
about these as well. Moreover, it is not enough to know that these
subterms halt, because the application of a normalized function to a
normalized argument involves a substitution, which may enable more
evaluation steps. So we need a stronger condition for terms of
functional type: not only should they halt themselves, but, when
applied to halting arguments, they should yield halting results.
The form of [R] is characteristic of the _logical relations_ proof
technique. (Since we are just dealing with unary relations here, we
could perhaps more properly say _logical predicates_.) If we want to
prove some property [P] of all closed terms of type [A], we proceed by
proving, by induction on types, that all terms of type [A] _possess_
property [P], all terms of type [A->A] _preserve_ property [P], all
terms of type [(A->A)->(A->A)] _preserve the property of preserving_
property [P], and so on. We do this by defining a family of
predicates, indexed by types. For the base type [A], the predicate is
just [P]. For functional types, it says that the function should map
values satisfying the predicate at the input type to values satisfying
the predicate at the output type.
When we come to formalize the definition of [R] in Coq, we hit a
problem. The most obvious formulation would be as a parameterized
Inductive proposition like this:
Inductive R : ty -> tm -> Prop :=
| R_bool : forall b t, has_type empty t TBool ->
halts t ->
R TBool t
| R_arrow : forall T1 T2 t, has_type empty t (TArrow T1 T2) ->
halts t ->
(forall s, R T1 s -> R T2 (tapp t s)) ->
R (TArrow T1 T2) t.
Unfortunately, Coq rejects this definition because it violates the
_strict positivity requirement_ for inductive definitions, which says
that the type being defined must not occur to the left of an arrow in
the type of a constructor argument. Here, it is the third argument to
[R_arrow], namely [(forall s, R T1 s -> R TS (tapp t s))], and
specifically the [R T1 s] part, that violates this rule. (The
outermost arrows separating the constructor arguments don't count when
applying this rule; otherwise we could never have genuinely inductive
predicates at all!) The reason for the rule is that types defined
with non-positive recursion can be used to build non-terminating
functions, which as we know would be a disaster for Coq's logical
soundness. Even though the relation we want in this case might be
perfectly innocent, Coq still rejects it because it fails the
positivity test.
Fortunately, it turns out that we _can_ define [R] using a
[Fixpoint]: *)
Fixpoint R (T:ty) (t:tm) {struct T} : Prop :=
has_type empty t T /\ halts t /\
(match T with
| TBool => True
| TArrow T1 T2 => (forall s, R T1 s -> R T2 (tapp t s))
(* FILL IN HERE *)
| TProd T1 T2 => False (* ... and delete this line *)
end).
(** As immediate consequences of this definition, we have that every
element of every set [R_T] halts in a value and is closed with type
[t] :*)
Lemma R_halts : forall {T} {t}, R T t -> halts t.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
Lemma R_typable_empty : forall {T} {t}, R T t -> has_type empty t T.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
(** Now we proceed to show the main result, which is that every
well-typed term of type [T] is an element of [R_T]. Together with
[R_halts], that will show that every well-typed term halts in a
value. *)
(* ###################################################################### *)
(** ** Membership in [R_T] is invariant under evaluation *)
(** We start with a preliminary lemma that shows a kind of strong
preservation property, namely that membership in [R_T] is _invariant_
under evaluation. We will need this property in both directions,
i.e. both to show that a term in [R_T] stays in [R_T] when it takes a
forward step, and to show that any term that ends up in [R_T] after a
step must have been in [R_T] to begin with.
First of all, an easy preliminary lemma. Note that in the forward
direction the proof depends on the fact that our language is
determinstic. This lemma might still be true for non-deterministic
languages, but the proof would be harder! *)
Lemma step_preserves_halting : forall t t', (t ==> t') -> (halts t <-> halts t').
Proof.
intros t t' ST. unfold halts.
split.
- (* -> *)
intros [t'' [STM V]].
inversion STM; subst.
apply ex_falso_quodlibet. apply value__normal in V. unfold normal_form in V. apply V. exists t'. auto.
rewrite (step_deterministic _ _ _ ST H). exists t''. split; assumption.
- (* <- *)
intros [t'0 [STM V]].
exists t'0. split; eauto.
Qed.
(** Now the main lemma, which comes in two parts, one for each
direction. Each proceeds by induction on the structure of the type
[T]. In fact, this is where we make fundamental use of the
structure of types.
One requirement for staying in [R_T] is to stay in type [T]. In the
forward direction, we get this from ordinary type Preservation. *)
Lemma step_preserves_R : forall T t t', (t ==> t') -> R T t -> R T t'.
Proof.
induction T; intros t t' E Rt; unfold R; fold R; unfold R in Rt; fold R in Rt;
destruct Rt as [typable_empty_t [halts_t RRt]].
(* TBool *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
auto.
(* TArrow *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
intros.
eapply IHT2.
apply ST_App1. apply E.
apply RRt; auto.
(* FILL IN HERE *) Admitted.
(** The generalization to multiple steps is trivial: *)
Lemma multistep_preserves_R : forall T t t',
(t ==>* t') -> R T t -> R T t'.
Proof.
intros T t t' STM; induction STM; intros.
assumption.
apply IHSTM. eapply step_preserves_R. apply H. assumption.
Qed.
(** In the reverse direction, we must add the fact that [t] has type
[T] before stepping as an additional hypothesis. *)
Lemma step_preserves_R' : forall T t t',
has_type empty t T -> (t ==> t') -> R T t' -> R T t.
Proof.
(* FILL IN HERE *) Admitted.
Lemma multistep_preserves_R' : forall T t t',
has_type empty t T -> (t ==>* t') -> R T t' -> R T t.
Proof.
intros T t t' HT STM.
induction STM; intros.
assumption.
eapply step_preserves_R'. assumption. apply H. apply IHSTM.
eapply preservation; eauto. auto.
Qed.
(* ###################################################################### *)
(** ** Closed instances of terms of type [T] belong to [R_T] *)
(** Now we proceed to show that every term of type [T] belongs to
[R_T]. Here, the induction will be on typing derivations (it would be
surprising to see a proof about well-typed terms that did not
somewhere involve induction on typing derivations!). The only
technical difficulty here is in dealing with the abstraction case.
Since we are arguing by induction, the demonstration that a term
[tabs x T1 t2] belongs to [R_(T1->T2)] should involve applying the
induction hypothesis to show that [t2] belongs to [R_(T2)]. But
[R_(T2)] is defined to be a set of _closed_ terms, while [t2] may
contain [x] free, so this does not make sense.
This problem is resolved by using a standard trick to suitably
generalize the induction hypothesis: instead of proving a statement
involving a closed term, we generalize it to cover all closed
_instances_ of an open term [t]. Informally, the statement of the
lemma will look like this:
If [x1:T1,..xn:Tn |- t : T] and [v1,...,vn] are values such that
[R T1 v1], [R T2 v2], ..., [R Tn vn], then
[R T ([x1:=v1][x2:=v2]...[xn:=vn]t)].
The proof will proceed by induction on the typing derivation
[x1:T1,..xn:Tn |- t : T]; the most interesting case will be the one
for abstraction. *)
(* ###################################################################### *)
(** *** Multisubstitutions, multi-extensions, and instantiations *)
(** However, before we can proceed to formalize the statement and
proof of the lemma, we'll need to build some (rather tedious)
machinery to deal with the fact that we are performing _multiple_
substitutions on term [t] and _multiple_ extensions of the typing
context. In particular, we must be precise about the order in which
the substitutions occur and how they act on each other. Often these
details are simply elided in informal paper proofs, but of course Coq
won't let us do that. Since here we are substituting closed terms, we
don't need to worry about how one substitution might affect the term
put in place by another. But we still do need to worry about the
_order_ of substitutions, because it is quite possible for the same
identifier to appear multiple times among the [x1,...xn] with
different associated [vi] and [Ti].
To make everything precise, we will assume that environments are
extended from left to right, and multiple substitutions are performed
from right to left. To see that this is consistent, suppose we have
an environment written as [...,y:bool,...,y:nat,...] and a
corresponding term substitution written as [...[y:=(tbool
true)]...[y:=(tnat 3)]...t]. Since environments are extended from
left to right, the binding [y:nat] hides the binding [y:bool]; since
substitutions are performed right to left, we do the substitution
[y:=(tnat 3)] first, so that the substitution [y:=(tbool true)] has
no effect. Substitution thus correctly preserves the type of the term.
With these points in mind, the following definitions should make sense.
A _multisubstitution_ is the result of applying a list of
substitutions, which we call an _environment_. *)
Definition env := list (id * tm).
Fixpoint msubst (ss:env) (t:tm) {struct ss} : tm :=
match ss with
| nil => t
| ((x,s)::ss') => msubst ss' ([x:=s]t)
end.
(** We need similar machinery to talk about repeated extension of a
typing context using a list of (identifier, type) pairs, which we
call a _type assignment_. *)
Definition tass := list (id * ty).
Fixpoint mextend (Gamma : context) (xts : tass) :=
match xts with
| nil => Gamma
| ((x,v)::xts') => extend (mextend Gamma xts') x v
end.
(** We will need some simple operations that work uniformly on
environments and type assigments *)
Fixpoint lookup {X:Set} (k : id) (l : list (id * X)) {struct l} : option X :=
match l with
| nil => None
| (j,x) :: l' =>
if eq_id_dec j k then Some x else lookup k l'
end.
Fixpoint drop {X:Set} (n:id) (nxs:list (id * X)) {struct nxs} : list (id * X) :=
match nxs with
| nil => nil
| ((n',x)::nxs') => if eq_id_dec n' n then drop n nxs' else (n',x)::(drop n nxs')
end.
(** An _instantiation_ combines a type assignment and a value
environment with the same domains, where corresponding elements are
in R *)
Inductive instantiation : tass -> env -> Prop :=
| V_nil : instantiation nil nil
| V_cons : forall x T v c e, value v -> R T v -> instantiation c e -> instantiation ((x,T)::c) ((x,v)::e).
(** We now proceed to prove various properties of these definitions. *)
(* ###################################################################### *)
(** *** More Substitution Facts *)
(** First we need some additional lemmas on (ordinary) substitution. *)
Lemma vacuous_substitution : forall t x,
~ appears_free_in x t ->
forall t', [x:=t']t = t.
Proof with eauto.
(* FILL IN HERE *) Admitted.
Lemma subst_closed: forall t,
closed t ->
forall x t', [x:=t']t = t.
Proof.
intros. apply vacuous_substitution. apply H. Qed.
Lemma subst_not_afi : forall t x v, closed v -> ~ appears_free_in x ([x:=v]t).
Proof with eauto. (* rather slow this way *)
unfold closed, not.
induction t; intros x v P A; simpl in A.
- (* tvar *)
destruct (eq_id_dec x i)...
inversion A; subst. auto.
- (* tapp *)
inversion A; subst...
- (* tabs *)
destruct (eq_id_dec x i)...
inversion A; subst...
inversion A; subst...
- (* tpair *)
inversion A; subst...
- (* tfst *)
inversion A; subst...
- (* tsnd *)
inversion A; subst...
- (* ttrue *)
inversion A.
- (* tfalse *)
inversion A.
- (* tif *)
inversion A; subst...
Qed.
Lemma duplicate_subst : forall t' x t v,
closed v -> [x:=t]([x:=v]t') = [x:=v]t'.
Proof.
intros. eapply vacuous_substitution. apply subst_not_afi. auto.
Qed.
Lemma swap_subst : forall t x x1 v v1, x <> x1 -> closed v -> closed v1 ->
[x1:=v1]([x:=v]t) = [x:=v]([x1:=v1]t).
Proof with eauto.
induction t; intros; simpl.
- (* tvar *)
destruct (eq_id_dec x i); destruct (eq_id_dec x1 i).
subst. apply ex_falso_quodlibet...
subst. simpl. rewrite eq_id. apply subst_closed...
subst. simpl. rewrite eq_id. rewrite subst_closed...
simpl. rewrite neq_id... rewrite neq_id...
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Properties of multi-substitutions *)
Lemma msubst_closed: forall t, closed t -> forall ss, msubst ss t = t.
Proof.
induction ss.
reflexivity.
destruct a. simpl. rewrite subst_closed; assumption.
Qed.
(** Closed environments are those that contain only closed terms. *)
Fixpoint closed_env (env:env) {struct env} :=
match env with
| nil => True
| (x,t)::env' => closed t /\ closed_env env'
end.
(** Next come a series of lemmas charcterizing how [msubst] of closed terms
distributes over [subst] and over each term form *)
Lemma subst_msubst: forall env x v t, closed v -> closed_env env ->
msubst env ([x:=v]t) = [x:=v](msubst (drop x env) t).
Proof.
induction env0; intros.
auto.
destruct a. simpl.
inversion H0. fold closed_env in H2.
destruct (eq_id_dec i x).
subst. rewrite duplicate_subst; auto.
simpl. rewrite swap_subst; eauto.
Qed.
Lemma msubst_var: forall ss x, closed_env ss ->
msubst ss (tvar x) =
match lookup x ss with
| Some t => t
| None => tvar x
end.
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (eq_id_dec i x).
apply msubst_closed. inversion H; auto.
apply IHss. inversion H; auto.
Qed.
Lemma msubst_abs: forall ss x T t,
msubst ss (tabs x T t) = tabs x T (msubst (drop x ss) t).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (eq_id_dec i x); simpl; auto.
Qed.
Lemma msubst_app : forall ss t1 t2, msubst ss (tapp t1 t2) = tapp (msubst ss t1) (msubst ss t2).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. rewrite <- IHss. auto.
Qed.
(** You'll need similar functions for the other term constructors. *)
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** Properties of multi-extensions *)
(** We need to connect the behavior of type assignments with that of their
corresponding contexts. *)
Lemma mextend_lookup : forall (c : tass) (x:id), lookup x c = (mextend empty c) x.
Proof.
induction c; intros.
auto.
destruct a. unfold lookup, mextend, extend. destruct (eq_id_dec i x); auto.
Qed.
Lemma mextend_drop : forall (c: tass) Gamma x x',
mextend Gamma (drop x c) x' = if eq_id_dec x x' then Gamma x' else mextend Gamma c x'.
induction c; intros.
destruct (eq_id_dec x x'); auto.
destruct a. simpl.
destruct (eq_id_dec i x).
subst. rewrite IHc.
destruct (eq_id_dec x x'). auto. unfold extend. rewrite neq_id; auto.
simpl. unfold extend. destruct (eq_id_dec i x').
subst.
destruct (eq_id_dec x x').
subst. exfalso. auto.
auto.
auto.
Qed.
(* ###################################################################### *)
(** *** Properties of Instantiations *)
(** These are strightforward. *)
Lemma instantiation_domains_match: forall {c} {e},
instantiation c e -> forall {x} {T}, lookup x c = Some T -> exists t, lookup x e = Some t.
Proof.
intros c e V. induction V; intros x0 T0 C.
solve by inversion .
simpl in *.
destruct (eq_id_dec x x0); eauto.
Qed.
Lemma instantiation_env_closed : forall c e, instantiation c e -> closed_env e.
Proof.
intros c e V; induction V; intros.
econstructor.
unfold closed_env. fold closed_env.
split. eapply typable_empty__closed. eapply R_typable_empty. eauto.
auto.
Qed.
Lemma instantiation_R : forall c e, instantiation c e ->
forall x t T, lookup x c = Some T ->
lookup x e = Some t -> R T t.
Proof.
intros c e V. induction V; intros x' t' T' G E.
solve by inversion.
unfold lookup in *. destruct (eq_id_dec x x').
inversion G; inversion E; subst. auto.
eauto.
Qed.
Lemma instantiation_drop : forall c env,
instantiation c env -> forall x, instantiation (drop x c) (drop x env).
Proof.
intros c e V. induction V.
intros. simpl. constructor.
intros. unfold drop. destruct (eq_id_dec x x0); auto. constructor; eauto.
Qed.
(* ###################################################################### *)
(** *** Congruence lemmas on multistep *)
(** We'll need just a few of these; add them as the demand arises. *)
Lemma multistep_App2 : forall v t t',
value v -> (t ==>* t') -> (tapp v t) ==>* (tapp v t').
Proof.
intros v t t' V STM. induction STM.
apply multi_refl.
eapply multi_step.
apply ST_App2; eauto. auto.
Qed.
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** The R Lemma. *)
(** We finally put everything together.
The key lemma about preservation of typing under substitution can
be lifted to multi-substitutions: *)
Lemma msubst_preserves_typing : forall c e,
instantiation c e ->
forall Gamma t S, has_type (mextend Gamma c) t S ->
has_type Gamma (msubst e t) S.
Proof.
induction 1; intros.
simpl in H. simpl. auto.
simpl in H2. simpl.
apply IHinstantiation.
eapply substitution_preserves_typing; eauto.
apply (R_typable_empty H0).
Qed.
(** And at long last, the main lemma. *)
Lemma msubst_R : forall c env t T,
has_type (mextend empty c) t T -> instantiation c env -> R T (msubst env t).
Proof.
intros c env0 t T HT V.
generalize dependent env0.
(* We need to generalize the hypothesis a bit before setting up the induction. *)
remember (mextend empty c) as Gamma.
assert (forall x, Gamma x = lookup x c).
intros. rewrite HeqGamma. rewrite mextend_lookup. auto.
clear HeqGamma.
generalize dependent c.
induction HT; intros.
- (* T_Var *)
rewrite H0 in H. destruct (instantiation_domains_match V H) as [t P].
eapply instantiation_R; eauto.
rewrite msubst_var. rewrite P. auto. eapply instantiation_env_closed; eauto.
- (* T_Abs *)
rewrite msubst_abs.
(* We'll need variants of the following fact several times, so its simplest to
establish it just once. *)
assert (WT: has_type empty (tabs x T11 (msubst (drop x env0) t12)) (TArrow T11 T12)).
eapply T_Abs. eapply msubst_preserves_typing. eapply instantiation_drop; eauto.
eapply context_invariance. apply HT.
intros.
unfold extend. rewrite mextend_drop. destruct (eq_id_dec x x0). auto.
rewrite H.
clear - c n. induction c.
simpl. rewrite neq_id; auto.
simpl. destruct a. unfold extend. destruct (eq_id_dec i x0); auto.
unfold R. fold R. split.
auto.
split. apply value_halts. apply v_abs.
intros.
destruct (R_halts H0) as [v [P Q]].
pose proof (multistep_preserves_R _ _ _ P H0).
apply multistep_preserves_R' with (msubst ((x,v)::env0) t12).
eapply T_App. eauto.
apply R_typable_empty; auto.
eapply multi_trans. eapply multistep_App2; eauto.
eapply multi_R.
simpl. rewrite subst_msubst.
eapply ST_AppAbs; eauto.
eapply typable_empty__closed.
apply (R_typable_empty H1).
eapply instantiation_env_closed; eauto.
eapply (IHHT ((x,T11)::c)).
intros. unfold extend, lookup. destruct (eq_id_dec x x0); auto.
constructor; auto.
- (* T_App *)
rewrite msubst_app.
destruct (IHHT1 c H env0 V) as [_ [_ P1]].
pose proof (IHHT2 c H env0 V) as P2. fold R in P1. auto.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Normalization Theorem *)
Theorem normalization : forall t T, has_type empty t T -> halts t.
Proof.
intros.
replace t with (msubst nil t) by reflexivity.
apply (@R_halts T).
apply (msubst_R nil); eauto.
eapply V_nil.
Qed.
(** $Date$ *)
|
// unsaved.v
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module unsaved (
input wire clk_clk, // clk.clk
input wire [4:0] pc_address, // pc.address
input wire pc_debugaccess, // .debugaccess
input wire pc_clken, // .clken
input wire pc_chipselect, // .chipselect
input wire pc_write, // .write
output wire [31:0] pc_readdata, // .readdata
input wire [31:0] pc_writedata, // .writedata
input wire [3:0] pc_byteenable, // .byteenable
input wire reset_reset, // reset.reset
input wire reset_reset_req // .reset_req
);
unsaved_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (pc_address), // s1.address
.debugaccess (pc_debugaccess), // .debugaccess
.clken (pc_clken), // .clken
.chipselect (pc_chipselect), // .chipselect
.write (pc_write), // .write
.readdata (pc_readdata), // .readdata
.writedata (pc_writedata), // .writedata
.byteenable (pc_byteenable), // .byteenable
.reset (reset_reset), // reset1.reset
.reset_req (reset_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
endmodule
|
// ----------------------------
// This module contains both the instantiation and the testbench for the
// scanflop_imp.v circuit.
//
// Note:
// - This module compiles and simulates with Verilog synthesizer
// - async. design follows dual rail encoding that maps
// input to output and output to internal states
//
// author: Tramy Nguyen
// ----------------------------
module scanflop_testbench();
wire q0, q1, ack;
reg in1_0, in1_1, in2_0, in2_1, sel0, sel1, next1, next2, next3, req;
initial begin
next1 = 1'b0;
next2 = 1'b0;
next3 = 1'b0;
in1_0 = 1'b0;
in1_1 = 1'b0;
in2_0 = 1'b0;
in2_1 = 1'b0;
sel0 = 1'b0;
sel1 = 1'b0;
req = 1'b0;
end
scanflop_imp sf_instance(
.in1_0(in1_0),
.in1_1(in1_1),
.in2_0(in2_0),
.in2_1(in2_1),
.sel0(sel0),
.sel1(sel1),
.q0(q0),
.q1(q1),
.req(req),
.ack(ack)
);
always begin
#5 next1 = $random%2;
#5 next2 = $random%2;
#5 next3 = $random%2;
if(next1 != 1'b1) begin
#5 in1_0 = 1'b1;
end
else begin
#5 in1_1 = 1'b1;
end
if(next2 != 1'b1) begin
#5 in2_0 = 1'b1;
end
else begin
#5 in2_1 = 1'b1;
end
if(next3 != 1'b1) begin
#5 sel0 = 1'b1;
end
else begin
#5 sel1 = 1'b1;
end
#5 req = 1'b1;
wait(ack == 1'b1) #5;
#5 req = 1'b0;
if(in1_0 == 1'b1) begin
#5 in1_0 = 1'b0;
end
else begin
#5 in1_1 = 1'b0;
end
if(in2_0 == 1'b1) begin
#5 in2_0 = 1'b0;
end
else begin
#5 in2_1 = 1'b0;
end
if(sel0 == 1'b1) begin
#5 sel0 = 1'b0;
end
else begin
#5 sel1 = 1'b0;
end
wait(ack != 1'b1) #5;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_no_overflow (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 0;
parameter max = ((1<<width)-1);
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NO_OVERFLOW";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_no_overflow_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_no_overflow_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_no_overflow_psl_logic.v"
`else
`endmodule // ovl_no_overflow
`endif
|
/****************************************************************************************
*
* File Name: CY7C1380_PL_SCD.v
* Version: 1.0
* Date: July 28th, 2004
* Model: BUS Functional
* Simulator: Verilog-XL (CADENCE)
*
*
* Queries: MPD Applications
* Website: www.cypress.com/support
* Company: Cypress Semiconductor
* Part #: CY7C1380D (512K x 36)
*
* Description: Cypress 18Mb Synburst SRAM (Pipelined SCD)
*
*
* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
* WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
* Copyright(c) Cypress Semiconductor, 2004
* All rights reserved
*
* Rev Date Changes
* --- ---------- ---------------------------------------
* 1.0 07/28/2004 - New Model
* - New Test Bench
* - New Test Vectors
*
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1ns / 10ps
// Timings for Different Speed Bins (sb): 250MHz, 225MHz, 200MHz, 167MHz, 133MHz
`define sb200
`ifdef sb250
`define tCO 2.6 // Data Output Valid After CLK Rise
`define tCYC 4.0 // Clock cycle time
`define tCH 1.7 // Clock HIGH time
`define tCL 1.7 // Clock LOW time
`define tCHZ 2.6 // Clock to High-Z
`define tCLZ 1.0 // Clock to Low-Z
`define tOEHZ 2.6 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 2.6 // OE# LOW to Output Valid
`define tAS 1.2 // Address Set-up Before CLK Rise
`define tADS 1.2 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.2 // ADV# Set-up Before CLK Rise
`define tWES 1.2 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.2 // Data Input Set-up Before CLK Rise
`define tCES 1.2 // Chip Enable Set-up
`define tAH 0.3 // Address Hold After CLK Rise
`define tADH 0.3 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.3 // ADV# Hold After CLK Rise
`define tWEH 0.3 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.3 // Data Input Hold After CLK Rise
`define tCEH 0.3 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb225
`define tCO 2.8 // Data Output Valid After CLK Rise
`define tCYC 4.4 // Clock cycle time
`define tCH 2.0 // Clock HIGH time
`define tCL 2.0 // Clock LOW time
`define tCHZ 2.8 // Clock to High-Z
`define tCLZ 1.0 // Clock to Low-Z
`define tOEHZ 2.8 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 2.8 // OE# LOW to Output Valid
`define tAS 1.4 // Address Set-up Before CLK Rise
`define tADS 1.4 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.4 // ADV# Set-up Before CLK Rise
`define tWES 1.4 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.4 // Data Input Set-up Before CLK Rise
`define tCES 1.4 // Chip Enable Set-up
`define tAH 0.4 // Address Hold After CLK Rise
`define tADH 0.4 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.4 // ADV# Hold After CLK Rise
`define tWEH 0.4 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.4 // Data Input Hold After CLK Rise
`define tCEH 0.4 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb200
`define tCO 3.0 // Data Output Valid After CLK Rise
`define tCYC 5.0 // Clock cycle time
`define tCH 2.0 // Clock HIGH time
`define tCL 2.0 // Clock LOW time
`define tCHZ 3.0 // Clock to High-Z
`define tCLZ 1.3 // Clock to Low-Z
`define tOEHZ 3.0 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 3.0 // OE# LOW to Output Valid
`define tAS 1.4 // Address Set-up Before CLK Rise
`define tADS 1.4 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.4 // ADV# Set-up Before CLK Rise
`define tWES 1.4 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.4 // Data Input Set-up Before CLK Rise
`define tCES 1.4 // Chip Enable Set-up
`define tAH 0.4 // Address Hold After CLK Rise
`define tADH 0.4 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.4 // ADV# Hold After CLK Rise
`define tWEH 0.4 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.4 // Data Input Hold After CLK Rise
`define tCEH 0.4 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb167
`define tCO 3.4 // Data Output Valid After CLK Rise
`define tCYC 6.0 // Clock cycle time
`define tCH 2.2 // Clock HIGH time
`define tCL 2.2 // Clock LOW time
`define tCHZ 3.4 // Clock to High-Z
`define tCLZ 1.3 // Clock to Low-Z
`define tOEHZ 3.4 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 3.4 // OE# LOW to Output Valid
`define tAS 1.5 // Address Set-up Before CLK Rise
`define tADS 1.5 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.5 // ADV# Set-up Before CLK Rise
`define tWES 1.5 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.5 // Data Input Set-up Before CLK Rise
`define tCES 1.5 // Chip Enable Set-up
`define tAH 0.5 // Address Hold After CLK Rise
`define tADH 0.5 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.5 // ADV# Hold After CLK Rise
`define tWEH 0.5 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.5 // Data Input Hold After CLK Rise
`define tCEH 0.5 // Chip Enable Hold After CLK Rise
`endif
`ifdef sb133
`define tCO 4.2 // Data Output Valid After CLK Rise
`define tCYC 7.5 // Clock cycle time
`define tCH 2.5 // Clock HIGH time
`define tCL 2.5 // Clock LOW time
`define tCHZ 3.4 // Clock to High-Z
`define tCLZ 1.3 // Clock to Low-Z
`define tOEHZ 4.0 // OE# HIGH to Output High-Z
`define tOELZ 0.0 // OE# LOW to Output Low-Z
`define tOEV 4.2 // OE# LOW to Output Valid
`define tAS 1.5 // Address Set-up Before CLK Rise
`define tADS 1.5 // ADSC#, ADSP# Set-up Before CLK Rise
`define tADVS 1.5 // ADV# Set-up Before CLK Rise
`define tWES 1.5 // BWx#, GW#, BWE# Set-up Before CLK Rise
`define tDS 1.5 // Data Input Set-up Before CLK Rise
`define tCES 1.5 // Chip Enable Set-up
`define tAH 0.5 // Address Hold After CLK Rise
`define tADH 0.5 // ADSC#, ADSP# Hold After CLK Rise
`define tADVH 0.5 // ADV# Hold After CLK Rise
`define tWEH 0.5 // BWx#, GW#, BWE# Hold After CLK Rise
`define tDH 0.5 // Data Input Hold After CLK Rise
`define tCEH 0.5 // Chip Enable Hold After CLK Rise
`endif
module CY7C1380_PLSCD (ZZ, Mode, ADDR, GW_N, BWE_N, BWd_N, BWc_N, BWb_N, BWa_N, CE1_N, CE2, CE3_N, ADSP_N, ADSC_N, ADV_N, OE_N, DQ, CLK);
parameter addr_bits = 19; // 19 bits
parameter data_bits = 36; // 36 bits
parameter mem_sizes = 524288; // 512K
inout [(data_bits - 1) : 0] DQ; // Data IO
input [(addr_bits - 1) : 0] ADDR; // ADDRess
input Mode; // Burst Mode
input ADV_N; // Synchronous ADDRess Advance
input CLK; // Clock
input ADSC_N; // Synchronous ADDRess Status Controller
input ADSP_N; // Synchronous ADDRess Status Processor
input BWa_N; // Synchronous Byte Write Enables
input BWb_N; // Synchronous Byte Write Enables
input BWc_N; // Synchronous Byte Write Enables
input BWd_N; // Synchronous Byte Write Enables
input BWE_N; // Byte Write Enable
input GW_N; // Global Write
input CE1_N; // Synchronous Chip Enable
input CE2; // Synchronous Chip Enable
input CE3_N; // Synchronous Chip Enable
input OE_N; // Output Enable
input ZZ; // Snooze Mode
reg [((data_bits / 4) - 1) : 0] bank0 [0 : mem_sizes]; // Memory Bank 0
reg [((data_bits / 4) - 1) : 0] bank1 [0 : mem_sizes]; // Memory Bank 1
reg [((data_bits / 4) - 1) : 0] bank2 [0 : mem_sizes]; // Memory Bank 2
reg [((data_bits / 4) - 1) : 0] bank3 [0 : mem_sizes]; // Memory Bank 3
reg [(data_bits - 1) : 0] din; // Data In
reg [(data_bits - 1) : 0] dout; // Data Out
reg [(addr_bits - 1) : 0] addr_reg_in; // ADDRess Register In
reg [(addr_bits - 1) : 0] addr_reg_read; // ADDRess Register for Read
reg [(addr_bits - 1) : 0] addr_reg_write; // ADDRess Register for Write
reg [1 : 0] bcount; // 2-bit Burst Counter
reg [1 : 0] first_addr; // 2-bit Burst Counter
reg ce_reg;
reg Read_reg;
reg Read_reg_o;
reg WrN_reg;
reg ADSP_N_o;
reg pipe_reg;
reg bwa_reg;
reg bwb_reg;
reg bwc_reg;
reg bwd_reg;
reg Sys_clk;
reg test;
reg pcsr_write;
reg ctlr_write;
reg latch_addr_current;
reg latch_addr_old;
wire ce = (~CE1_N & CE2 & ~CE3_N);
wire Write_n = ~(((~BWa_N | ~BWb_N | ~BWc_N | ~BWd_N) & ~BWE_N) | ~GW_N ) ;
wire Read = (((BWa_N & BWb_N & BWc_N & BWd_N) & ~BWE_N) | (GW_N & BWE_N) | (~ADSP_N & ce)) ;
wire bwa_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWa_N )));
wire bwb_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWb_N )));
wire bwc_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWc_N )));
wire bwd_n = ~(~Write_n & (~GW_N | (~BWE_N & ~BWd_N )));
wire latch_addr = (~ADSC_N | (~ADSP_N & ~CE1_N));
wire #`tOEHZ OeN_HZ = OE_N ? 1 : 0;
wire #`tOEV OeN_DataValid = ~OE_N ? 0 : 1;
wire OeN_efct = ~OE_N ? OeN_DataValid : OeN_HZ;
wire #`tCHZ WR_HZ = WrN_reg ? 1 : 0;
wire #`tCLZ WR_LZ = ~WrN_reg ? 0 : 1;
wire WR_efct = ~WrN_reg ? WR_LZ : WR_HZ;
wire #`tCHZ CE_HZ = (~ce_reg | ~pipe_reg) ? 0 : 1 ;
wire #`tCLZ CE_LZ = pipe_reg ? 1 : 0 ;
wire Pipe_efct = (ce_reg & pipe_reg) ? CE_LZ : CE_HZ ;
wire #`tCHZ RD_HZ = ~Read_reg_o ? 0 : 1 ;
wire #`tCLZ RD_LZ = Read_reg_o ? 1 : 0 ;
wire RD_efct = Read_reg_o ? CE_LZ : CE_HZ ;
//Test
int i;
initial
#0 begin
for(i = 0; i < 640*480/2; i = i + 1)begin
if(i < (640*480)/4)begin
{bank3[i], bank2[i], bank1[i], bank0[i]} = func_data(i*2);//t_test({2{5'hFF, 6'h00, 5'h00}});
end
else begin
{bank3[i], bank2[i], bank1[i], bank0[i]} = func_data(i*2);//t_test({2{5'h0, 6'h00, 5'hFF}});
end
end
end
function [35:0] func_data;
input [15:0] data;
reg [15:0] r_data0;
reg [15:0] r_data1;
begin
r_data0 = data;
r_data1 = data + 1;
func_data = {1'b0, r_data1[15:8], 1'b0, r_data1[7:0], 1'b0, r_data0[15:8], 1'b0, r_data0[7:0]};
end
endfunction
function [35:0] t_test;
input [31:0] data;
begin
t_test = {1'b0, data[31:24], 1'b0, data[23:16], 1'b0, data[15:8], 1'b0, data[7:0]};
end
endfunction
// Initialize
initial begin
ce_reg = 1'b0;
pipe_reg = 1'b0;
Sys_clk = 1'b0;
$timeformat (-9, 1, " ns", 10); // Format time unit
end
// System Clock Decode
always begin
@ (posedge CLK) begin
Sys_clk = ~ZZ;
end
@ (negedge CLK) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Read Register
if (~Write_n) Read_reg_o = 1'b0;
else Read_reg_o = Read_reg;
if (~Write_n) Read_reg = 1'b0;
else Read_reg = Read;
if (Read_reg == 1'b1) begin
pcsr_write = 1'b0;
ctlr_write = 1'b0;
end
// Write Register
if (Read_reg_o == 1'b1) WrN_reg = 1'b1;
else WrN_reg = Write_n;
latch_addr_old = latch_addr_current;
latch_addr_current = latch_addr;
if (latch_addr_old == 1'b1 & ~Write_n & ADSP_N_o == 1'b0)
pcsr_write = 1'b1; //Ctlr Write = 0; Pcsr Write = 1;
else if (latch_addr_current == 1'b1 & ~Write_n & ADSP_N & ~ADSC_N)
ctlr_write = 1'b1; //Ctlr Write = 0; Pcsr Write = 1;
// ADDRess Register
if (latch_addr)
begin
addr_reg_in = ADDR;
bcount = ADDR [1 : 0];
first_addr = ADDR [1 : 0];
end
// ADSP_N Previous-Cycle Register
ADSP_N_o <= ADSP_N;
// Binary Counter and Logic
if (~Mode & ~ADV_N & ~latch_addr) // Linear Burst
bcount = (bcount + 1); // Advance Counter
else if (Mode & ~ADV_N & ~latch_addr) // Interleaved Burst
begin
if (first_addr % 2 == 0)
bcount = (bcount + 1); // Increment Counter
else if (first_addr % 2 == 1)
bcount = (bcount - 1); // Decrement Counter
end
// Read ADDRess
addr_reg_read = addr_reg_write;
// Write ADDRess
addr_reg_write = {addr_reg_in [(addr_bits - 1) : 2], bcount[1], bcount[0]};
// Byte Write Register
bwa_reg = ~bwa_n;
bwb_reg = ~bwb_n;
bwc_reg = ~bwc_n;
bwd_reg = ~bwd_n;
// Enable Register
pipe_reg = ce_reg;
// Enable Register
if (latch_addr) ce_reg = ce;
// Input Register
if (ce_reg & (~bwa_n | ~bwb_n | ~bwc_n | ~bwd_n) & (pcsr_write | ctlr_write)) begin
din = DQ;
end
// Byte Write Driver
if (ce_reg & bwa_reg) begin
bank0 [addr_reg_write] = din [ 8 : 0];
end
if (ce_reg & bwb_reg) begin
bank1 [addr_reg_write] = din [17 : 9];
end
if (ce_reg & bwc_reg) begin
bank2 [addr_reg_write] = din [26 : 18];
end
if (ce_reg & bwd_reg) begin
bank3 [addr_reg_write] = din [35 : 27];
end
// Output Registers
if (~Write_n | pipe_reg == 1'b0)
dout [ 35 : 0] <= #`tCHZ 36'bZ;
else if (Read_reg_o == 1'b1) begin
dout [ 8 : 0] <= #`tCO bank0 [addr_reg_read];
dout [17 : 9] <= #`tCO bank1 [addr_reg_read];
dout [26 : 18] <= #`tCO bank2 [addr_reg_read];
dout [35 : 27] <= #`tCO bank3 [addr_reg_read];
end
end
// Output Buffers
assign DQ = (~OE_N & ~ZZ & Pipe_efct & RD_efct & WR_efct) ? dout : 36'bz;
// Timing Check
specify
$width (negedge CLK, `tCL);
$width (posedge CLK, `tCH);
$period (negedge CLK, `tCYC);
$period (posedge CLK, `tCYC);
$setuphold (posedge CLK, ADSP_N, `tADS, `tADH);
$setuphold (posedge CLK, ADSC_N, `tADS, `tADH);
$setuphold (posedge CLK, ADDR, `tAS, `tAH);
$setuphold (posedge CLK, BWa_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWb_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWc_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWd_N, `tWES, `tWEH);
$setuphold (posedge CLK, BWE_N, `tWES, `tWEH);
$setuphold (posedge CLK, GW_N, `tWES, `tWEH);
$setuphold (posedge CLK, CE1_N, `tCES, `tCEH);
$setuphold (posedge CLK, CE2, `tCES, `tCEH);
$setuphold (posedge CLK, CE3_N, `tCES, `tCEH);
$setuphold (posedge CLK, ADV_N, `tADVS, `tADVH);
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_hdll__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo_ctl.v
// Author : Chih-Tsun Huang
// E-mail : [email protected]
// Revision : 4
// Date : 2014/04/28
// Abstract :
// FIFO controller is mainly the finite state machine and its
// control signals to manage the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo_ctr (
// inputs
input wire clk,
input wire rst_n,
input wire push,
input wire pop,
// outputs
output reg empty,
output reg almost_empty,
output reg full,
output reg almost_full,
output reg error,
output reg cen,
output reg wen,
output reg oen,
output reg [4:0] addr
);
parameter numOfRam = 32;
// small delay of flip-flop outputs
parameter delay = 1.5;
// state encoding
parameter EMPTY = 2'b00;
parameter BETWEEN = 2'b01;
parameter READOUT = 2'b10;
parameter FULL = 2'b11;
// state vector
reg [1:0] state;
reg [1:0] state_next;
// pointers
reg [4:0] head;
reg [4:0] head_next;
reg [4:0] tail;
reg [4:0] tail_next;
reg head_plus;
reg tail_plus;
reg addr_head;
reg addr_tail;
reg do_idle;
reg do_pop;
reg do_push;
reg do_push_pop;
// sequential part
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
state <= EMPTY;
head <= 5'b0;
tail <= 5'b0;
end else begin
state <= #(delay) state_next;
head <= #(delay) head_next;
tail <= #(delay) tail_next;
end
end
// combinational parts
// Lab Note:
// Complete your design here
always @(*) begin
do_idle = 1'b0;
do_pop = 1'b0;
do_push = 1'b0;
do_push_pop = 1'b0;
case ({push,pop})
2'b00: begin do_idle = 1'b1; end
2'b01: begin do_pop = 1'b1; end
2'b10: begin do_push = 1'b1; end
2'b11: begin do_push_pop = 1'b1; end
endcase
end
always @(*) begin
if (head_plus) begin
head_next = (head + 1'b1)%numOfRam;
end else begin
head_next = head;
end
if (tail_plus) begin
tail_next = (tail + 1'b1)%numOfRam;
end else begin
tail_next = tail;
end
end
always @(*) begin
if (tail == head - 1'b1) begin
almost_empty = 1'b1;
end else begin
almost_empty = 1'b0;
end
if (head == tail - 1'b1) begin
almost_full = 1'b1;
end else begin
almost_full = 1'b0;
end
oen = 1'b0;
end
// FSM
always @(*) begin
empty = 1'b0;
full = 1'b0;
error = 1'b0;
cen = 1'b0;
wen = 1'b0;
addr = 5'b0;
head_plus = 1'b0;
tail_plus = 1'b0;
addr_head = 1'b0;
addr_tail = 1'b0;
state_next = state;
case (state)
EMPTY: begin
if (do_idle || do_pop || do_push_pop) begin
error = (do_pop | do_push_pop);
state_next = EMPTY;
end else if (do_push) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end
end
BETWEEN: begin
if (do_push && !almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end else if (do_idle || do_push_pop) begin
error = do_push_pop;
state_next = BETWEEN;
end else if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_push && almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = FULL;
end
end
READOUT: begin
if (!almost_empty) begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = BETWEEN;
end else begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = EMPTY;
end
end
FULL: begin
if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_idle || do_push || do_push_pop) begin
error = (do_push | do_push_pop);
state_next = FULL;
end
end
endcase
end
endmodule
|
//======================================================================
//
// trng.v
// --------
// Top level wrapper for the True Random Number Generator.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module trng(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire avalanche_noise,
input wire cs,
input wire we,
input wire [11 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
output wire [7 : 0] debug,
input wire debug_update,
output wire security_error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter TRNG_PREFIX = 4'h0;
parameter ENTROPY1_PREFIX = 4'h5;
parameter ENTROPY2_PREFIX = 4'h6;
parameter MIXER_PREFIX = 4'ha;
parameter CSPRNG_PREFIX = 4'hb;
parameter DEBUG_ENTROPY0 = 3'h0;
parameter DEBUG_ENTROPY1 = 3'h1;
parameter DEBUG_ENTROPY2 = 3'h2;
parameter DEBUG_MIXER = 3'h3;
parameter DEBUG_CSPRNG = 3'h4;
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_TRNG_CTRL = 8'h10;
parameter TRNG_CTRL_DISCARD_BIT = 0;
parameter TRNG_CTRL_TEST_MODE_BIT = 1;
parameter ADDR_TRNG_STATUS = 8'h11;
parameter ADDR_DEBUG_CTRL = 8'h12;
parameter ADDR_DEBUG_DELAY = 8'h13;
parameter TRNG_NAME0 = 32'h74726e67; // "trng"
parameter TRNG_NAME1 = 32'h20202020; // " "
parameter TRNG_VERSION = 32'h302e3031; // "0.01"
// 20x/s @ 50 MHz.
parameter DEFAULT_DEBUG_DELAY = 32'h002625a0;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg discard_reg;
reg discard_new;
reg test_mode_reg;
reg test_mode_new;
reg test_mode_we;
reg [7 : 0] debug_out_reg;
reg debug_out_we;
reg [2 : 0] debug_mux_reg;
reg [2 : 0] debug_mux_new;
reg debug_mux_we;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
reg [31 : 0] debug_delay_reg;
reg [31 : 0] debug_delay_new;
reg debug_delay_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg trng_api_cs;
reg trng_api_we;
reg [31 : 0] trng_api_read_data;
reg trng_api_error;
wire mixer_more_seed;
wire [511 : 0] mixer_seed_data;
wire mixer_seed_syn;
wire mixer_seed_ack;
reg mixer_api_cs;
reg mixer_api_we;
wire [31 : 0] mixer_api_read_data;
wire mixer_api_error;
wire mixer_security_error;
wire [7 : 0] mixer_debug;
reg mixer_debug_update;
wire csprng_more_seed;
wire csprng_seed_ack;
reg csprng_api_cs;
reg csprng_api_we;
wire [31 : 0] csprng_api_read_data;
wire csprng_api_error;
wire [7 : 0] csprng_debug;
reg csprng_debug_update;
wire csprng_security_error;
wire entropy0_entropy_enabled;
wire [31 : 0] entropy0_entropy_data;
wire entropy0_entropy_syn;
wire entropy0_entropy_ack;
reg entropy1_api_cs;
reg entropy1_api_we;
wire [31 : 0] entropy1_api_read_data;
wire entropy1_api_error;
wire entropy1_entropy_enabled;
wire [31 : 0] entropy1_entropy_data;
wire entropy1_entropy_syn;
wire entropy1_entropy_ack;
wire entropy1_test_mode;
wire [7 : 0] entropy1_debug;
reg entropy1_debug_update;
wire entropy1_security_error;
reg entropy2_api_cs;
reg entropy2_api_we;
wire [31 : 0] entropy2_api_read_data;
wire entropy2_api_error;
wire entropy2_entropy_enabled;
wire [31 : 0] entropy2_entropy_data;
wire entropy2_entropy_syn;
wire entropy2_entropy_ack;
wire entropy2_test_mode;
wire [7 : 0] entropy2_debug;
reg entropy2_debug_update;
wire entropy2_security_error;
reg [7 : 0] api_address;
reg [31 : 0] tmp_read_data;
reg tmp_error;
reg [7 : 0] tmp_debug;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign security_error = entropy1_security_error | entropy2_security_error;
assign debug = debug_out_reg;
// Patches to get our first version to work.
assign entropy0_entropy_enabled = 0;
assign entropy0_entropy_syn = 0;
assign entropy0_entropy_data = 32'h00000000;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
trng_mixer mixer_inst(
.clk(clk),
.reset_n(reset_n),
.cs(mixer_api_cs),
.we(mixer_api_we),
.address(api_address),
.write_data(write_data),
.read_data(mixer_api_read_data),
.error(mixer_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(mixer_security_error),
.more_seed(csprng_more_seed),
.entropy0_enabled(entropy0_entropy_enabled),
.entropy0_syn(entropy0_entropy_syn),
.entropy0_data(entropy0_entropy_data),
.entropy0_ack(entropy0_entropy_ack),
.entropy1_enabled(entropy1_entropy_enabled),
.entropy1_syn(entropy1_entropy_syn),
.entropy1_data(entropy1_entropy_data),
.entropy1_ack(entropy1_entropy_ack),
.entropy2_enabled(entropy2_entropy_enabled),
.entropy2_syn(entropy2_entropy_syn),
.entropy2_data(entropy2_entropy_data),
.entropy2_ack(entropy2_entropy_ack),
.seed_data(mixer_seed_data),
.seed_syn(mixer_seed_syn),
.seed_ack(csprng_seed_ack),
.debug(mixer_debug),
.debug_update(mixer_debug_update)
);
trng_csprng csprng_inst(
.clk(clk),
.reset_n(reset_n),
.cs(csprng_api_cs),
.we(csprng_api_we),
.address(api_address),
.write_data(write_data),
.read_data(csprng_api_read_data),
.error(csprng_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(csprng_security_error),
.more_seed(csprng_more_seed),
.seed_data(mixer_seed_data),
.seed_syn(mixer_seed_syn),
.seed_ack(csprng_seed_ack),
.debug(csprng_debug),
.debug_update(csprng_debug_update)
);
avalanche_entropy entropy1(
.clk(clk),
.reset_n(reset_n),
.noise(avalanche_noise),
.cs(entropy1_api_cs),
.we(entropy1_api_we),
.address(api_address),
.write_data(write_data),
.read_data(entropy1_api_read_data),
.error(entropy1_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(entropy1_security_error),
.entropy_enabled(entropy1_entropy_enabled),
.entropy_data(entropy1_entropy_data),
.entropy_valid(entropy1_entropy_syn),
.entropy_ack(entropy1_entropy_ack),
.debug(entropy1_debug),
.debug_update(entropy1_debug_update)
);
rosc_entropy entropy2(
.clk(clk),
.reset_n(reset_n),
.cs(entropy2_api_cs),
.we(entropy2_api_we),
.address(api_address),
.write_data(write_data),
.read_data(entropy2_api_read_data),
.error(entropy2_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(entropy2_security_error),
.entropy_enabled(entropy2_entropy_enabled),
.entropy_data(entropy2_entropy_data),
.entropy_valid(entropy2_entropy_syn),
.entropy_ack(entropy2_entropy_ack),
.debug(entropy2_debug),
.debug_update(entropy2_debug_update)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
discard_reg <= 0;
test_mode_reg <= 0;
debug_mux_reg <= DEBUG_CSPRNG;
debug_delay_reg <= DEFAULT_DEBUG_DELAY;
debug_delay_ctr_reg <= 32'h00000000;
debug_out_reg <= 8'h00;
end
else
begin
discard_reg <= discard_new;
debug_delay_ctr_reg <= debug_delay_ctr_new;
if (debug_out_we)
begin
debug_out_reg <= tmp_debug;
end
if (test_mode_we)
begin
test_mode_reg <= test_mode_new;
end
if (debug_mux_we)
begin
debug_mux_reg <= debug_mux_new;
end
if (debug_delay_we)
begin
debug_delay_reg <= debug_delay_new;
end
end
end // reg_update
//----------------------------------------------------------------
// debug_update_logic
//
// Debug update counter and update logic.
//----------------------------------------------------------------
always @*
begin : debug_update_logic
if (debug_delay_ctr_reg == debug_delay_reg)
begin
debug_out_we = 1;
debug_delay_ctr_new = 32'h00000000;
end
else
begin
debug_out_we = 0;
debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
end
end // debug_update
//----------------------------------------------------------------
// debug_mux
//
// Select which of the sub modules that are connected to
// the debug port.
//----------------------------------------------------------------
always @*
begin : debug_mux
entropy1_debug_update = 0;
entropy2_debug_update = 0;
mixer_debug_update = 0;
csprng_debug_update = 0;
tmp_debug = 8'h00;
case(debug_mux_reg)
DEBUG_ENTROPY1:
begin
entropy1_debug_update = debug_update;
tmp_debug = entropy1_debug;
end
DEBUG_ENTROPY2:
begin
entropy2_debug_update = debug_update;
tmp_debug = entropy2_debug;
end
DEBUG_MIXER:
begin
mixer_debug_update = debug_update;
tmp_debug = mixer_debug;
end
DEBUG_CSPRNG:
begin
csprng_debug_update = debug_update;
tmp_debug = csprng_debug;
end
default:
begin
end
endcase // case (debug_mux_reg)
end // debug_mux
//----------------------------------------------------------------
// api_mux
//
// This is a simple decoder that looks at the top 4 bits of
// the given api address and selects which of the sub modules
// or the top level mux that gets to handle any API
// operations.
//----------------------------------------------------------------
always @*
begin : api_mux
trng_api_cs = 0;
trng_api_we = 0;
entropy1_api_cs = 0;
entropy1_api_we = 0;
entropy2_api_cs = 0;
entropy2_api_we = 0;
mixer_api_cs = 0;
mixer_api_we = 0;
csprng_api_cs = 0;
csprng_api_we = 0;
api_address = address[7 : 0];
tmp_read_data = 32'h00000000;
tmp_error = 0;
case (address[11 : 8])
TRNG_PREFIX:
begin
trng_api_cs = cs;
trng_api_we = we;
tmp_read_data = trng_api_read_data;
tmp_error = trng_api_error;
end
ENTROPY1_PREFIX:
begin
entropy1_api_cs = cs;
entropy1_api_we = we;
tmp_read_data = entropy1_api_read_data;
tmp_error = entropy1_api_error;
end
ENTROPY2_PREFIX:
begin
entropy2_api_cs = cs;
entropy2_api_we = we;
tmp_read_data = entropy2_api_read_data;
tmp_error = entropy2_api_error;
end
MIXER_PREFIX:
begin
mixer_api_cs = cs;
mixer_api_we = we;
tmp_read_data = mixer_api_read_data;
tmp_error = mixer_api_error;
end
CSPRNG_PREFIX:
begin
csprng_api_cs = cs;
csprng_api_we = we;
tmp_read_data = csprng_api_read_data;
tmp_error = csprng_api_error;
end
default:
begin
end
endcase // case (address[11 : 8])
end // api_mux
//----------------------------------------------------------------
// trng_api_logic
//
// Implementation of the top level api logic.
//----------------------------------------------------------------
always @*
begin : trng_api_logic
discard_new = 0;
test_mode_new = 0;
test_mode_we = 0;
debug_mux_new = 3'h0;
debug_mux_we = 0;
debug_delay_new = 32'h00000000;
debug_delay_we = 0;
trng_api_read_data = 32'h00000000;
trng_api_error = 0;
if (trng_api_cs)
begin
if (trng_api_we)
begin
// Write operations.
case (api_address)
// Write operations.
ADDR_TRNG_CTRL:
begin
discard_new = write_data[TRNG_CTRL_DISCARD_BIT];
test_mode_new = write_data[TRNG_CTRL_TEST_MODE_BIT];
test_mode_we = 1;
end
ADDR_DEBUG_CTRL:
begin
debug_mux_new = write_data[2 : 0];
debug_mux_we = 1;
end
ADDR_DEBUG_DELAY:
begin
debug_delay_new = write_data;
debug_delay_we = 1;
end
default:
begin
trng_api_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
// Read operations.
case (api_address)
// Read operations.
ADDR_NAME0:
begin
trng_api_read_data = TRNG_NAME0;
end
ADDR_NAME1:
begin
trng_api_read_data = TRNG_NAME1;
end
ADDR_VERSION:
begin
trng_api_read_data = TRNG_VERSION;
end
ADDR_TRNG_CTRL:
begin
end
ADDR_TRNG_STATUS:
begin
end
ADDR_DEBUG_CTRL:
begin
trng_api_read_data = debug_mux_new;
end
ADDR_DEBUG_DELAY:
begin
trng_api_read_data = debug_delay_reg;
end
default:
begin
trng_api_error = 1;
end
endcase // case (address)
end
end
end // trng_api_logic
endmodule // trng
//======================================================================
// EOF trng.v
//======================================================================
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Logic Core: PCI/Avalon Bridge Megacore Function
// Company: Altera Corporation.
// www.altera.com
// Author: IPBU SIO Group
//
// Description: Control Register Avalon Interface Module
//
// Copyright (c) 2004 Altera Corporation. All rights reserved. This source code
// is highly confidential and proprietary information of Altera and is being
// provided in accordance with and subject to the protections of a
// Non-Disclosure Agreement which governs its use and disclosure. Altera
// products and services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. Altera
// assumes no responsibility or liability arising out of the application or use
// of this source code.
//
// For Best Viewing Set tab stops to 4 spaces.
//
// $Id: //acds/main/ip/pci_express/src/rtl/lib/avalon/altpciexpav_cr_avalon.v#6 $
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// This sub module of the PCI/Avalon Bridge Control Register module handles the
// handshaking between the Avalon Switch Fabric and the other sub-modules that
// actually implement the registers.
//
// A rough block diagram of this module is:
//
// Avalon Write Data, Byte Enables
// Write Data, >---------------------------------> Broadcast to
// Byte Enables No registers on Write Data, Sub-Modules
// Byte Enables or Address since
// Avalon they are static (WaitReq) Address
// Address >-+-----------------------------------> Broadcast to
// | Sub-Modules
// |
// | +------+ +--+
// +-|Decode|-| |--+----------+
// +------+ |> | | |
// +--+ | +---+ Individual
// | |DE | Read, Write
// +----------+ +-|MUX|-----> Valids to each
// | | +---+ Sub-Module
// +---+ +--+ |
// Sub-Module |MUX|--| |---------)-----------> Read Data
// Read Data >---| | |> | | to Avalon
// +---+ +--+ |
// | |
// Sub-Module +---+ |
// Read Data |MUX|--+ (Selected |
// Valids >------| | | Read |
// +---+ | Valid) |
// | |
// +----------+ |
// | |
// Avalon | +-----+ +--+ State | +------+
// Write, +--|Next |-| |--+------+-|Decode|--> Wait Request
// Read, >------|State| |> | | +------+ to Avalon
// Chip- +--| | +--+ |
// Select | +-----+ |
// | |
// +----------------+
//
// The register sub-module abbreviations and definitions are:
// AdTr - Address Translation (Actually external to Control Register)
// A2PMb - Avalon to PCI Mailbox registers
// P2AMb - PCI to Avalon Mailbox registers
// Rupt - Interrupt Status and Enable registers
// Rp - Root Port Tx Control registers
// RdBak - Parameter ReadBack registers
// Icr - Not a sub-module but Abbreviation for:
// "Internal Control Register broadcast"
//
module altpciexpav_stif_cr_avalon
(
// Avalon Interface signals (all synchronous to CraClk_i)
input CraClk_i, // Clock for register access port
input CraRstn_i, // Reset signal
input CraChipSelect_i, // Chip Select signals
input [13:2] CraAddress_i, // Register (DWORD) specific address
input [3:0] CraByteEnable_i, // Register Byte Enables
input CraRead_i, // Read indication
output reg [31:0] CraReadData_o, // Read data lines
input CraWrite_i, // Write indication
input [31:0] CraWriteData_i, // Write Data in
output reg CraWaitRequest_o, // Wait indication out
input CraBeginTransfer_i, // Start of Transfer (not used)
// Modified Avalon signals to the Address Translation logic
// All synchronous to CraClk_i
output reg AdTrWriteReqVld_o, // Valid Write Cycle to AddrTrans
output reg AdTrReadReqVld_o, // Read Valid out to AddrTrans
output [11:2] AdTrAddress_o, // Register (DWORD) specific address
output [3:0] AdTrByteEnable_o, // Register Byte Enables
input [31:0] AdTrReadData_i, // Read Data in from AddrTrans
output [31:0] AdTrWriteData_o, // Write Data out to AddrTrans
input AdTrReadDataVld_i, // Read Valid in from AddrTrans
// Modified Avalon signals broadcast to internal modules
output reg [13:2] IcrAddress_o, // Address to Internal
output reg [31:0] IcrWriteData_o, // Write Data to Internal
output reg [3:0] IcrByteEnable_o, // Byte Enables to Internal
// Modified Avalon signals to/from specific internal modules
// Avalon to Pci Mailbox
output reg A2PMbWriteReqVld_o, // Valid Write Cycle
output reg A2PMbReadReqVld_o, // Read Valid out
input [31:0] A2PMbReadData_i, // Read Data in
input A2PMbReadDataVld_i, // Read Valid in
// Pci to Avalon Mailbox
output reg P2AMbWriteReqVld_o, // Valid Write Cycle
output reg P2AMbReadReqVld_o, // Read Valid out
input [31:0] P2AMbReadData_i, // Read Data in
input P2AMbReadDataVld_i, // Read Valid in
// Interrupt Module
output reg RuptWriteReqVld_o, // Valid Write Cycle
output reg RuptReadReqVld_o, // Read Valid out
input [31:0] RuptReadData_i, // Read Data in
input RuptReadDataVld_i, // Read Valid in
/// Root Port Module
output reg RpWriteReqVld_o, // Valid Write Cycle
output reg RpReadReqVld_o, // Read Valid out
input [31:0] RpReadData_i, // Read Data in
input RpReadDataVld_i, // Read Valid in
/// Cfg Module
output reg CfgReadReqVld_o, // Read Valid out
input [31:0] CfgReadData_i, // Read Data in
input CfgReadDataVld_i, // Read Valid in
// RdBak Module
output reg RdBakReadReqVld_o, // Read Valid out
input [31:0] RdBakReadData_i, // Read Data in
input RdBakReadDataVld_i, // Read Valid in
input RpTxBusy_i
) ;
// Registered versions of Avalon Inputs
reg sel_read_vld ;
reg [31:0] sel_read_data ;
// State Machine for control the state of the interface
localparam [5:0] CRA_IDLE = 6'b000000 ;
localparam [5:0] CRA_WRITE_ACK = 6'b000011 ;
localparam [5:0] CRA_READ_FIRST = 6'b000101 ;
localparam [5:0] CRA_READ_WAIT = 6'b001001 ;
localparam [5:0] CRA_READ_ACK = 6'b010001 ;
localparam [5:0] CRA_PIPE = 6'b100001 ;
reg [5:0] avalon_state_reg ;
// Decoded Address Register
localparam CRA_NONE_SEL = 0 ;
localparam CRA_A2P_MB_SEL = 1 ;
localparam CRA_P2A_MB_SEL = 2 ;
localparam CRA_RUPT_SEL = 3 ;
localparam CRA_RDBAK_SEL = 4 ;
localparam CRA_ADDRTRANS_SEL = 5 ;
localparam CRA_RP_SEL = 6 ;
localparam CRA_CFG_SEL = 7;
reg [CRA_CFG_SEL:CRA_NONE_SEL] addr_decode_reg ;
reg [13:2] cra_address_reg;
// Address Decode Function
// Encapsulate in a function to make the mainline code
// streamlined and avoid need for another signal if we
// were to do it in a separate combinational always block
function [CRA_CFG_SEL:CRA_NONE_SEL] address_decode ;
input [13:8] Address_i ;
begin
address_decode = 0 ;
casez (Address_i)
// 0000-00FF - PCI Interrupt registers
// 3000-30FF - Avalon Interrupt registers
6'b000000, 6'b110000 :
address_decode[CRA_RUPT_SEL] = 1'b1 ;
// 2000-20FF -- Root Port Tx registers
6'b100000:
address_decode[CRA_RP_SEL] = 1'b1 ;
6'b111100: /// 3CXX
address_decode[CRA_CFG_SEL] = 1'b1 ;
// 1000-1FFF - Address Translation
6'b01????:
address_decode[CRA_ADDRTRANS_SEL] = 1'b1 ;
// 0800-08FF - PCI to Avalon Mailbox R/W
// 3B00-0BFF - PCI to Avalon Mailbox R/O
6'b001000, 6'b111011 :
address_decode[CRA_P2A_MB_SEL] = 1'b1 ;
// 3A00-3AFF - Avalon to PCI Mailbox R/W
// 0900-09FF - Avalon to PCI Mailbox R/O
6'b111010, 6'b001001 :
address_decode[CRA_A2P_MB_SEL] = 1'b1 ;
// 2C00-2FFF - Readback registers
6'b1011?? :
address_decode[CRA_RDBAK_SEL] = 1'b1 ;
default
address_decode[CRA_NONE_SEL] = 1'b1 ;
endcase
end
endfunction // address_decode
always @(posedge CraClk_i or negedge CraRstn_i)
begin
if(~CraRstn_i)
cra_address_reg <= 0;
else if(avalon_state_reg == CRA_IDLE & CraChipSelect_i & (CraRead_i | CraWrite_i))
cra_address_reg <= CraAddress_i;
end
// Address, Data, Control and Address Decode Register
always @(posedge CraClk_i or negedge CraRstn_i)
begin
if (CraRstn_i == 1'b0)
begin
addr_decode_reg <= 7'b000000 ;
CraReadData_o <= 32'h0;
end
else
begin
if (avalon_state_reg == CRA_PIPE)
addr_decode_reg <= address_decode(cra_address_reg[13:8]) ;
else
addr_decode_reg <= addr_decode_reg ;
CraReadData_o <= sel_read_data ;
end
end // always @ (posedge CraClk_i or negedge CraRstn_i)
// Drive these signals straight through for now they are stable for
// multiple cycles
always @(CraWriteData_i or CraByteEnable_i or cra_address_reg)
begin
IcrAddress_o = cra_address_reg ;
IcrByteEnable_o = CraByteEnable_i ;
IcrWriteData_o = CraWriteData_i ;
end
// Provide Copies of these signals so hookup is straightforward at next
// level up
assign AdTrWriteData_o = IcrWriteData_o ;
assign AdTrAddress_o = IcrAddress_o[11:2] ;
assign AdTrByteEnable_o = IcrByteEnable_o ;
// Main state machine
always @(posedge CraClk_i or negedge CraRstn_i)
begin
if (CraRstn_i == 1'b0)
avalon_state_reg <= CRA_IDLE ;
else
case (avalon_state_reg)
CRA_IDLE :
if(CraChipSelect_i & (CraRead_i | CraWrite_i))
avalon_state_reg <= CRA_PIPE ;
CRA_PIPE :
if (CraRead_i == 1'b1)
avalon_state_reg <= CRA_READ_FIRST ;
else if(CraWrite_i == 1'b1 & RpTxBusy_i == 1'b0)
avalon_state_reg <= CRA_WRITE_ACK ;
CRA_READ_FIRST, CRA_READ_WAIT :
begin
if (sel_read_vld == 1'b1)
begin
avalon_state_reg <= CRA_READ_ACK ;
end
else
begin
avalon_state_reg <= CRA_READ_WAIT ;
end
end // case: CRA_READ_FIRST, CRA_READ_WAIT
CRA_READ_ACK, CRA_WRITE_ACK :
begin
avalon_state_reg <= CRA_IDLE ;
end // case: CRA_READ_ACK, CRA_WRITE_ACK
endcase // case(avalon_state_reg)
end // always @ (posedge CraClk_i or negedge CraRstn_i)
// Generate the Output Controls
always @*
begin
if (avalon_state_reg == CRA_READ_FIRST)
begin
AdTrReadReqVld_o = addr_decode_reg[CRA_ADDRTRANS_SEL] ;
A2PMbReadReqVld_o = addr_decode_reg[CRA_A2P_MB_SEL] ;
P2AMbReadReqVld_o = addr_decode_reg[CRA_P2A_MB_SEL] ;
RuptReadReqVld_o = addr_decode_reg[CRA_RUPT_SEL] ;
RpReadReqVld_o = addr_decode_reg[CRA_RP_SEL] ;
CfgReadReqVld_o = addr_decode_reg[CRA_CFG_SEL] ;
RdBakReadReqVld_o = addr_decode_reg[CRA_RDBAK_SEL] ;
end
else
begin
AdTrReadReqVld_o = 1'b0 ;
A2PMbReadReqVld_o = 1'b0 ;
P2AMbReadReqVld_o = 1'b0 ;
RuptReadReqVld_o = 1'b0 ;
RpReadReqVld_o = 1'b0 ;
CfgReadReqVld_o = 1'b0 ;
RdBakReadReqVld_o = 1'b0 ;
end
if (avalon_state_reg == CRA_WRITE_ACK)
begin
AdTrWriteReqVld_o = addr_decode_reg[CRA_ADDRTRANS_SEL] ;
A2PMbWriteReqVld_o = addr_decode_reg[CRA_A2P_MB_SEL] ;
P2AMbWriteReqVld_o = addr_decode_reg[CRA_P2A_MB_SEL] ;
RuptWriteReqVld_o = addr_decode_reg[CRA_RUPT_SEL] ;
RpWriteReqVld_o = addr_decode_reg[CRA_RP_SEL] ;
end
else
begin
AdTrWriteReqVld_o = 1'b0 ;
A2PMbWriteReqVld_o = 1'b0 ;
P2AMbWriteReqVld_o = 1'b0 ;
RuptWriteReqVld_o = 1'b0 ;
RpWriteReqVld_o = 1'b0 ;
end // else: !if(avalon_state_reg == CRA_WRITE_ACK)
if ( (avalon_state_reg == CRA_WRITE_ACK) ||
(avalon_state_reg == CRA_READ_ACK) )
CraWaitRequest_o = 1'b0 ;
else
CraWaitRequest_o = 1'b1 ;
end // always @ (avalon_state_reg or addr_decode_reg)
// Select the returned read data and read valid
always @*
begin
sel_read_vld = 1'b0 ;
sel_read_data = 1'b0 ;
if (addr_decode_reg[CRA_ADDRTRANS_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | AdTrReadDataVld_i ;
sel_read_data = sel_read_data | AdTrReadData_i ;
end
if (addr_decode_reg[CRA_A2P_MB_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | A2PMbReadDataVld_i ;
sel_read_data = sel_read_data | A2PMbReadData_i ;
end
if (addr_decode_reg[CRA_P2A_MB_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | P2AMbReadDataVld_i ;
sel_read_data = sel_read_data | P2AMbReadData_i ;
end
if (addr_decode_reg[CRA_RUPT_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | RuptReadDataVld_i ;
sel_read_data = sel_read_data | RuptReadData_i ;
end
if (addr_decode_reg[CRA_RP_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | RpReadDataVld_i ;
sel_read_data = sel_read_data | RpReadData_i ;
end
if (addr_decode_reg[CRA_CFG_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | CfgReadDataVld_i ;
sel_read_data = sel_read_data | CfgReadData_i ;
end
if (addr_decode_reg[CRA_RDBAK_SEL] == 1'b1)
begin
sel_read_vld = sel_read_vld | RdBakReadDataVld_i ;
sel_read_data = sel_read_data | RdBakReadData_i ;
end
if (addr_decode_reg[CRA_NONE_SEL] == 1'b1)
begin
sel_read_vld = 1'b1 ;
end
end
endmodule // altpciav_cr_avalon
|
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-28 17:47:55
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch2 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
`ifdef SINGLE
CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5 uut (
`endif
`ifdef DOUBLE
CORDIC_Arch2_W64_EW11_SW55_SWR55_EWR6 uut (
`endif
.clk(clk),
.rst(rst),
.beg_fsm_cordic(beg_fsm_cordic),
.ack_cordic(ack_cordic),
.operation(operation),
.data_in(data_in),
.shift_region_flag(shift_region_flag),
.r_mode(r_mode),
.ready_cordic(ready_cordic),
.overflow_flag(overflow_flag),
.underflow_flag(underflow_flag),
.data_output(data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 32'h00000000;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
`ifndef RMODE00
r_mode = 2'b00;
`endif
`ifdef RMODE01
r_mode = 2'b01;
`endif
`ifdef RMODE10
r_mode = 2'b10;
`endif
`ifdef RMODE11
r_mode = 2'b11;
`endif
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
`ifdef SINGLE
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
`endif
`ifdef DOUBLE
$readmemh("CORDIC64_input_angles_hex.txt", Array_IN);
`endif
end
// clock
initial forever #5 clk = ~clk;
always @(posedge clk) begin
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(posedge clk) begin
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_2_V
`define SKY130_FD_SC_LP__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_2_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fetch_cur_chroma.v
// Author : Yufeng Bai
// Email : [email protected]
//
//-------------------------------------------------------------------
//
// Modified : 2015-09-02 by HLL
// Description : rotate by sys_start_i
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fetch_cur_chroma (
clk ,
rstn ,
sysif_start_i ,
mc_cur_4x4_x_i ,
mc_cur_4x4_y_i ,
mc_cur_4x4_idx_i ,
mc_cur_sel_i ,
mc_cur_size_i ,
mc_cur_rden_i ,
mc_cur_pel_o ,
db_cur_4x4_x_i ,
db_cur_4x4_y_i ,
db_cur_4x4_idx_i ,
db_cur_sel_i ,
db_cur_size_i ,
db_cur_rden_i ,
db_cur_pel_o ,
ext_load_done_i ,
ext_load_data_i ,
ext_load_addr_i ,
ext_load_valid_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input sysif_start_i ;
input [4-1:0] mc_cur_4x4_x_i ; // mc current lcu x
input [4-1:0] mc_cur_4x4_y_i ; // mc current lcu y
input [5-1:0] mc_cur_4x4_idx_i ; // mc current lcu idx
input [1-1:0] mc_cur_sel_i ; // mc current lcu chroma/luma sel
input [2-1:0] mc_cur_size_i ; // "mc current lcu size :4x4
input [1-1:0] mc_cur_rden_i ; // mc current lcu read enable
output [32*`PIXEL_WIDTH-1:0] mc_cur_pel_o ; // mc current lcu pixel
input [4-1:0] db_cur_4x4_x_i ; // db current lcu x
input [4-1:0] db_cur_4x4_y_i ; // db current lcu y
input [5-1:0] db_cur_4x4_idx_i ; // db current lcu idx
input [1-1:0] db_cur_sel_i ; // db current lcu chroma/luma sel
input [2-1:0] db_cur_size_i ; // "db current lcu size :4x4
input [1-1:0] db_cur_rden_i ; // db current lcu read enable
output [32*`PIXEL_WIDTH-1:0] db_cur_pel_o ; // db current lcu pixel
input [1-1:0] ext_load_done_i ; // load current lcu done
input [32*`PIXEL_WIDTH-1:0] ext_load_data_i ; // load current lcu data
input [6-1:0] ext_load_addr_i ; // load current lcu address
input [1-1:0] ext_load_valid_i ; // load current lcu data valid
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3-1:0] rotate ; // rotatation counter
reg [4-1:0] cur_00_4x4_x ;
reg [4-1:0] cur_00_4x4_y ;
reg [5-1:0] cur_00_idx ;
reg [1-1:0] cur_00_sel ;
reg [2-1:0] cur_00_size ;
reg [1-1:0] cur_00_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_00_pel ;
wire [32*`PIXEL_WIDTH-1:0] cur_00_rdata ;
reg [4-1:0] cur_01_4x4_x ;
reg [4-1:0] cur_01_4x4_y ;
reg [5-1:0] cur_01_idx ;
reg [1-1:0] cur_01_sel ;
reg [2-1:0] cur_01_size ;
reg [1-1:0] cur_01_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_01_pel ;
wire [32*`PIXEL_WIDTH-1:0] cur_01_rdata ;
reg [4-1:0] cur_02_4x4_x ;
reg [4-1:0] cur_02_4x4_y ;
reg [5-1:0] cur_02_idx ;
reg [1-1:0] cur_02_sel ;
reg [2-1:0] cur_02_size ;
reg [1-1:0] cur_02_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_02_pel ;
wire [32*`PIXEL_WIDTH-1:0] cur_02_rdata ;
reg [1-1:0] cur_00_wen ;
reg [6-1:0] cur_00_waddr ;
reg [32*`PIXEL_WIDTH-1:0] cur_00_wdata ;
reg [1-1:0] cur_01_wen ;
reg [6-1:0] cur_01_waddr ;
reg [32*`PIXEL_WIDTH-1:0] cur_01_wdata ;
reg [1-1:0] cur_02_wen ;
reg [6-1:0] cur_02_waddr ;
reg [32*`PIXEL_WIDTH-1:0] cur_02_wdata ;
reg [32*`PIXEL_WIDTH-1:0] db_cur_pel_o ;
reg [32*`PIXEL_WIDTH-1:0] mc_cur_pel_o ;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always @ (*) begin
case(rotate)
'd0: begin
cur_00_wen = ext_load_valid_i;
cur_00_waddr = ext_load_addr_i;
cur_00_wdata = ext_load_data_i;
cur_00_ren = 'd0;
cur_00_sel = 'd0;
cur_00_size = 'd0;
cur_00_4x4_x = 'd0;
cur_00_4x4_y = 'd0;
cur_00_idx = 'd0;
cur_01_wen = 'd0;
cur_01_waddr = 'd0;
cur_01_wdata = 'd0;
cur_01_ren = db_cur_rden_i;
cur_01_sel = db_cur_sel_i;
cur_01_size = db_cur_size_i;
cur_01_4x4_x = db_cur_4x4_x_i;
cur_01_4x4_y = db_cur_4x4_y_i;
cur_01_idx = db_cur_4x4_idx_i;
cur_02_wen = 'd0;
cur_02_waddr = 'd0;
cur_02_wdata = 'd0;
cur_02_ren = mc_cur_rden_i;
cur_02_sel = mc_cur_sel_i;
cur_02_size = mc_cur_size_i;
cur_02_4x4_x = mc_cur_4x4_x_i;
cur_02_4x4_y = mc_cur_4x4_y_i;
cur_02_idx = mc_cur_4x4_idx_i;
db_cur_pel_o = cur_01_rdata;
mc_cur_pel_o = cur_02_rdata;
end
'd1: begin
cur_00_wen = 'd0;
cur_00_waddr = 'd0;
cur_00_wdata = 'd0;
cur_00_ren = mc_cur_rden_i;
cur_00_sel = mc_cur_sel_i;
cur_00_size = mc_cur_size_i;
cur_00_4x4_x = mc_cur_4x4_x_i;
cur_00_4x4_y = mc_cur_4x4_y_i;
cur_00_idx = mc_cur_4x4_idx_i;
cur_01_wen = ext_load_valid_i;
cur_01_waddr = ext_load_addr_i;
cur_01_wdata = ext_load_data_i;
cur_01_ren = 'd0;
cur_01_sel = 'd0;
cur_01_size = 'd0;
cur_01_4x4_x = 'd0;
cur_01_4x4_y = 'd0;
cur_01_idx = 'd0;
cur_02_wen = 'd0;
cur_02_waddr = 'd0;
cur_02_wdata = 'd0;
cur_02_ren = db_cur_rden_i;
cur_02_sel = db_cur_sel_i;
cur_02_size = db_cur_size_i;
cur_02_4x4_x = db_cur_4x4_x_i;
cur_02_4x4_y = db_cur_4x4_y_i;
cur_02_idx = db_cur_4x4_idx_i;
db_cur_pel_o = cur_02_rdata;
mc_cur_pel_o = cur_00_rdata;
end
'd2: begin
cur_00_wen = 'd0;
cur_00_waddr = 'd0;
cur_00_wdata = 'd0;
cur_00_ren = db_cur_rden_i;
cur_00_sel = db_cur_sel_i;
cur_00_size = db_cur_size_i;
cur_00_4x4_x = db_cur_4x4_x_i;
cur_00_4x4_y = db_cur_4x4_y_i;
cur_00_idx = db_cur_4x4_idx_i;
cur_01_wen = 'd0;
cur_01_waddr = 'd0;
cur_01_wdata = 'd0;
cur_01_ren = mc_cur_rden_i;
cur_01_sel = mc_cur_sel_i;
cur_01_size = mc_cur_size_i;
cur_01_4x4_x = mc_cur_4x4_x_i;
cur_01_4x4_y = mc_cur_4x4_y_i;
cur_01_idx = mc_cur_4x4_idx_i;
cur_02_wen = ext_load_valid_i;
cur_02_waddr = ext_load_addr_i;
cur_02_wdata = ext_load_data_i;
cur_02_ren = 'd0;
cur_02_sel = 'd0;
cur_02_size = 'd0;
cur_02_4x4_x = 'd0;
cur_02_4x4_y = 'd0;
cur_02_idx = 'd0;
db_cur_pel_o = cur_00_rdata;
mc_cur_pel_o = cur_01_rdata;
end
default: begin
cur_00_wen = 'd0;
cur_00_waddr = 'd0;
cur_00_wdata = 'd0;
cur_00_ren = 'd0;
cur_00_sel = 'd0;
cur_00_size = 'd0;
cur_00_4x4_x = 'd0;
cur_00_4x4_y = 'd0;
cur_00_idx = 'd0;
cur_01_wen = 'd0;
cur_01_waddr = 'd0;
cur_01_wdata = 'd0;
cur_01_ren = 'd0;
cur_01_sel = 'd0;
cur_01_size = 'd0;
cur_01_4x4_x = 'd0;
cur_01_4x4_y = 'd0;
cur_01_idx = 'd0;
cur_02_wen = 'd0;
cur_02_waddr = 'd0;
cur_02_wdata = 'd0;
cur_02_ren = 'd0;
cur_02_sel = 'd0;
cur_02_size = 'd0;
cur_02_4x4_x = 'd0;
cur_02_4x4_y = 'd0;
cur_02_idx = 'd0;
db_cur_pel_o = 'd0;
mc_cur_pel_o = 'd0;
end
endcase
end
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if( !rstn )
rotate <= 0 ;
else if ( sysif_start_i ) begin
if( rotate == 2 )
rotate <= 0 ;
else begin
rotate <= rotate + 1 ;
end
end
end
// ********************************************
//
// mem
//
// ********************************************
mem_lipo_1p cur00 (
.clk (clk ),
.rst_n (rstn ),
.a_wen_i (cur_00_wen ),
.a_addr_i ({2'b10,cur_00_waddr}),
.a_wdata_i (cur_00_wdata),
.b_ren_i (cur_00_ren ),
.b_sel_i (cur_00_sel ),
.b_size_i (cur_00_size ),
.b_4x4_x_i (cur_00_4x4_x),
.b_4x4_y_i (cur_00_4x4_y),
.b_idx_i (cur_00_idx ),
.b_rdata_o (cur_00_rdata)
);
mem_lipo_1p cur01 (
.clk (clk ),
.rst_n (rstn ),
.a_wen_i (cur_01_wen ),
.a_addr_i ({2'b10,cur_01_waddr}),
.a_wdata_i (cur_01_wdata),
.b_ren_i (cur_01_ren ),
.b_sel_i (cur_01_sel ),
.b_size_i (cur_01_size ),
.b_4x4_x_i (cur_01_4x4_x),
.b_4x4_y_i (cur_01_4x4_y),
.b_idx_i (cur_01_idx ),
.b_rdata_o (cur_01_rdata)
);
mem_lipo_1p cur02 (
.clk (clk ),
.rst_n (rstn ),
.a_wen_i (cur_02_wen ),
.a_addr_i ({2'b10,cur_02_waddr}),
.a_wdata_i (cur_02_wdata),
.b_ren_i (cur_02_ren ),
.b_sel_i (cur_02_sel ),
.b_size_i (cur_02_size ),
.b_4x4_x_i (cur_02_4x4_x),
.b_4x4_y_i (cur_02_4x4_y),
.b_idx_i (cur_02_idx ),
.b_rdata_o (cur_02_rdata)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:30:52 01/30/2011
// Design Name: MiniAlu
// Module Name: D:/Proyecto/RTL/Dev/MiniALU/TestBench.v
// Project Name: MiniALU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MiniAlu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestBench;
// Inputs
reg Clock;
reg Reset;
//reg response;
// MiniALU Outputs
wire response;
wire [7:0] oLed;
wire [3:0]data;
wire LCDreset;
wire writeEN;
// LCD_Controller OutPuts
wire [3:0]oLCD_Data;
wire oLCD_Enabled;
wire oLCD_RegisterSelect;
wire oLCD_ReadWrite;
wire oLCD_StrataFlashControl;
// Instantiate the Units Under Test (UUT)
MiniAlu uut (
.Clock(Clock),
.Reset(Reset),
.oLed(oLed),
.iLCD_response(response),
.oLCD_data(data),
.oLCD_reset(LCDreset),
.oLCD_writeEN(writeEN),
.oLCD_StrataFlashControl(oLCD_StrataFlashControl)
);
//LCD_controler uut1(
// .clk(Clock),
// .iLCD_data(data),
// .iLCD_reset(LCDreset),
// .iLCD_writeEN(writeEN),
// .oLCD_response(response),
// .oLCD_Data(oLCD_Data),
// .oLCD_Enabled(oLCD_Enabled),
// .oLCD_RegisterSelect(oLCD_RegisterSelect),
// .oLCD_ReadWrite(oLCD_ReadWrite),
// .oLCD_StrataFlashControl(oLCD_StrataFlashControl)
//);
always
begin
#1 Clock = ! Clock;
end
initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;
// Wait 100 ns for global reset to finish
Reset = 1;
#2
Reset = 0;
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_BEHAVIORAL_V |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////d
////////////////////////////////////////////////////////////////////////////////////
// trcam.v: Transposed-RAM Stage CAM Core //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module trcam
#( parameter CAMD = 128 , // CAM depth (power of 2, >=64)
parameter CAMW = 9 , // CAM/pattern width / for one stage (<=14)
parameter INOM = 1 , // binary / Initial CAM with no match
parameter BRAM = "M20K") // BRAM type- "M20K":Altera's M20K; "GEN":generic
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input wrEr , // Write or erase (inverted)
input [`log2(CAMD)-1:0] wAddr , // write address
input [ CAMW -1:0] wPatt , // write pattern
input [ CAMW -1:0] mPatt , // patern to match
output [ CAMD -1:0] match ); // match / one-hot
// Altera's M20K parameters
localparam M20K_nBITS = 16384 ; // total bits
localparam M20K_MIND = 512 ; // minimum depth / widest configuration
localparam M20K_MINAW = `log2(M20K_MIND) ; // minimum address width (=9)
localparam M20K_CAMW = (CAMW<M20K_MINAW) ? M20K_MINAW : CAMW; // effective CAMW >= M20K_MINAW (14)
localparam M20K_DW = (M20K_nBITS/(2**M20K_CAMW))<1 ? 1 : (M20K_nBITS/(2**M20K_CAMW)) ; // M20K data width (=1)
localparam nM20K = CAMD / M20K_DW ; // M20K count (32k)
wire [`log2(CAMD)-`log2(M20K_DW)-1:0] M20KSel_bin = wAddr[`log2(CAMD)-1:`log2(M20K_DW)];
reg [nM20K -1:0] M20KSel_1ht ;
// binary to one-hot
always @(*) begin
M20KSel_1ht = 0 ;
M20KSel_1ht[M20KSel_bin] = wEnb;
end
// generate and instantiate mixed-width BRAMs
genvar gi;
generate
if (BRAM=="M20K")
for (gi=1 ; gi<=nM20K ; gi=gi+1) begin: BRAMgi
if (CAMW<14) // M20K
mwram_m20k #( .WR_DW( 1 ), // write width
.RD_DW( M20K_DW ), // read width
.IZERO( INOM )) // initialize to zeros
mwram_m20k_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( M20KSel_1ht[gi-1] ), // write enable
.wAddr( {`ZPAD(wPatt,M20K_MINAW),wAddr[`log2(M20K_DW)-1:0]} ), // write address [13:0]
.wData( wrEr ), // write data
.rAddr( `ZPAD(mPatt,M20K_MINAW) ), // read address [ 8:0]
.rData( match[gi*M20K_DW-1 -: M20K_DW]) ); // read data [31:0]
else if (CAMW==14) // single bit read/write M20K
mwram_m20k #( .WR_DW( 1 ), // write width
.RD_DW( 1 ), // read width
.IZERO( INOM )) // initialize to zeros
mwram_m20k_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb (M20KSel_1ht[gi-1] ), // write enable
.wAddr( wPatt ), // write address [13:0]
.wData( wrEr ), // write data
.rAddr( mPatt ), // read address [ 8:0]
.rData( match[gi-1]) ); // read data [31:0]
else // CAMW>14
sbram_m20k #( .DEPTH( 2**CAMW ), // RAM depth
.IZERO( INOM )) // initialize to zeros
sbram_m20k_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( M20KSel_1ht[gi-1] ), // write enable
.wAddr( wPatt ), // write address / [`log2(RD_D*RD_DW/WR_DW)-1:0]
.wData( wrEr ), // write data / [WR_DW -1:0]
.rAddr( mPatt ), // read address / [`log2(RD_D) -1:0]
.rData( match[gi-1] )); // read data / [RD_DW -1:0]
end
else // generic
mwram_gen #( .WR_DW( 1 ), // write data width
.RD_DW( CAMD ), // read data width
.RD_D ( 2**CAMW ), // read depth
.IZERO( INOM )) // initialize to zeros
mwram_gen_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnb ), // write enable
.wAddr( {wPatt,wAddr} ), // write address / [`log2(RD_D*RD_DW/WR_DW)-1:0]
.wData( wrEr ), // write data / [WR_DW -1:0]
.rAddr( mPatt ), // read address / [`log2(RD_D) -1:0]
.rData( match )); // read data / [RD_DW -1:0]
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_SYMBOL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapmet1 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V |
/**
* bsg_parallel_in_serial_out_passthrough_dynamic.v
*
* This data structure takes in a multi-word parallel input and serializes
* it to a single word output. This module is helpful on both sides, both v_o
* and ready_and_o are early.
*
* Note:
* A transaction starts when ready_and_o & v_i. data_i must
* stay constant for the entirety of the transaction until
* ready_and_o is asserted.
* This may make the module incompatible with upstream modules that
* multiplex multiple inputs and can change which input they multiplex
* on the fly based on arrival of new inputs.
*
* By definition of ready-and handshaking, ready_and_o must be earlier than
* v_i. Since ready_and_o depends on value of len_i, so len_i must not depend
* on v_i. For this reason, len_i signal is on the serial data side of the
* module and depends on ready_and_i.
*
*/
`include "bsg_defines.v"
module bsg_parallel_in_serial_out_passthrough_dynamic
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(max_els_p)
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Data Input Channel
,input v_i
,input [max_els_p-1:0][width_p-1:0] data_i
,output ready_and_o
// Data Output Channel
,output v_o
,output [width_p-1:0] data_o
,input ready_and_i
//
// When first_o is asserted, the upcoming data is the first word of a new
// transaction. It can be asserted regardless of value of v_o.
,output first_o
//
// len_i indicates the length (number of data words) of the upcoming new
// transaction. User need to guarantee that len_i is valid when first_o and
// ready_and_i are both asserted (when dequeueing the first data word of
// the new transaction).
//
// Note that len_i is represented by (length - 1), in order to use minimum
// number of bits. For example, when a 4-word transaction is coming, len_i
// should be set to 3. Single word transaction should have len_i == 0.
,input [lg_max_els_lp-1:0] len_i
);
if (max_els_p == 1)
begin : single_word
assign v_o = v_i;
assign data_o = data_i;
assign ready_and_o = ready_and_i;
assign first_o = 1'b1;
end
else
begin : multi_word
logic [lg_max_els_lp-1:0] count_r, len_r;
logic is_zero_cnt, is_last_cnt, is_zero_len;
logic en_li, clear_li, up_li;
// Register the length of upcoming transaction
// Add reset to prevent X-pessimism issue in simulation
bsg_dff_reset_en
#(.width_p (lg_max_els_lp)
,.reset_val_p(0 )
) len_dff
(.clk_i (clk_i )
,.reset_i (reset_i )
,.data_i (len_i )
,.en_i (en_li )
,.data_o (len_r )
);
// Count how many words have been sent in each transaction
bsg_counter_clear_up
#(.max_val_p (max_els_p-1)
,.init_val_p(0 )
) ctr
(.clk_i (clk_i )
,.reset_i (reset_i )
,.clear_i (clear_li )
,.up_i (up_li )
,.count_o (count_r )
);
// Zero count means idle state, accepting new transaction
// Last count indicates sending last data word of transaction
// Zero length means the upcoming new transaction has single data word
assign is_zero_cnt = (count_r == (lg_max_els_lp)'(0));
assign is_last_cnt = ~is_zero_cnt & (count_r == len_r);
assign is_zero_len = ready_and_i & (len_i == (lg_max_els_lp)'(0));
// Update length when sending the first data word of new transaction
// Count up when sending out data words
// Clear the counter at the end of each transaction
assign en_li = v_o & ready_and_i & is_zero_cnt;
assign up_li = v_o & ready_and_i & ~clear_li;
assign clear_li = v_i & ready_and_o;
// Output valid data when input data is valid, there is no registered data
// in this module.
assign v_o = v_i;
// Dequeue incoming parallel data at the end of each transaction.
// When incoming data is single-word, dequeue immediately.
assign ready_and_o = (ready_and_i & is_last_cnt) | is_zero_len;
assign first_o = is_zero_cnt;
// Output data
bsg_mux
#(.width_p(width_p )
,.els_p (max_els_p)
) data_mux
(.data_i (data_i )
,.sel_i (count_r )
,.data_o (data_o )
);
//synopsys translate_off
logic [max_els_p-1:0][width_p-1:0] initial_data_r;
bsg_dff_en
#(.width_p(width_p*max_els_p)
) initial_reg
(.clk_i (clk_i )
,.en_i (is_zero_cnt & v_i)
,.data_i (data_i )
,.data_o (initial_data_r )
);
always_ff @(negedge clk_i)
begin
if (~reset_i & ~is_zero_cnt)
begin
assert (v_i)
else $error("v_i must be held high during the entire PISO transaction");
assert (data_i == initial_data_r)
else $error("data_i must be held constant during the entire PISO transaction");
end
end
//synopsys translate_on
//
// Implementation below breaks the constraint that v_i and data_i must hold
// their values, at the cost of (max_els_p-1) more buffering.
//
/*
module bsg_parallel_in_serial_out_passthrough_dynamic
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(max_els_p)
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Data Input Channel
,input v_i
,input [max_els_p-1:0][width_p-1:0] data_i
,output ready_and_o
// Data Output Channel
,output v_o
,output [width_p-1:0] data_o
,input [lg_max_els_lp-1:0] len_i
,input ready_and_i
);
if (max_els_p == 1)
begin : single_word
assign v_o = v_i;
assign data_o = data_i;
assign ready_and_o = ready_and_i;
end
else
begin : multi_word
logic [lg_max_els_lp-1:0] count_r, len_lo;
logic is_zero, is_last, en_li, clear_li, up_li;
logic [max_els_p-1:0][width_p-1:0] data_lo;
bsg_counter_clear_up
#(.max_val_p (max_els_p-1)
,.init_val_p(0 )
) ctr
(.clk_i (clk_i )
,.reset_i (reset_i )
,.clear_i (clear_li )
,.up_i (up_li )
,.count_o (count_r )
);
// reset len_lo to prevent X-pessimism in simulation
bsg_dff_reset_en_bypass
#(.width_p (lg_max_els_lp)
,.reset_val_p(0 )
) len_dff
(.clk_i (clk_i )
,.reset_i (reset_i )
,.en_i (en_li )
,.data_i (len_i )
,.data_o (len_lo )
);
assign data_lo[0] = data_i[0];
bsg_dff_en_bypass
#(.width_p((max_els_p-1)*width_p )
) data_dff
(.clk_i (clk_i )
,.en_i (en_li )
,.data_i (data_i [max_els_p-1:1])
,.data_o (data_lo[max_els_p-1:1])
);
assign is_zero = count_r == (lg_max_els_lp)'(0);
assign is_last = count_r == len_lo;
assign en_li = v_i & is_zero;
assign up_li = v_o & ready_and_i & ~is_last;
assign clear_li = v_o & ready_and_i & is_last;
assign v_o = v_i | ~is_zero;
assign ready_and_o = ready_and_i & is_zero;
bsg_mux
#(.width_p(width_p )
,.els_p (max_els_p)
) data_mux
(.data_i (data_lo )
,.sel_i (count_r )
,.data_o (data_o )
);
*/
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_parallel_in_serial_out_passthrough_dynamic)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_BLACKBOX_V
`define SKY130_FD_SC_HVL__OR3_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_BLACKBOX_V
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import BigNumPrelude.
Require Import CyclicAxioms.
Require Import ROmega.
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr n x := iter_nat n _ shiftr x.
Lemma nshiftr_S :
forall n x, nshiftr (S n) x = shiftr (nshiftr n x).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr (S n) x = nshiftr n (shiftr x).
Proof.
induction n; simpl; auto.
intros; rewrite nshiftr_S, IHn, nshiftr_S; auto.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr n 0 = 0.
Proof.
induction n; simpl; auto.
rewrite nshiftr_S, IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr size x = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr k x = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite nshiftr_S, IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl n x := iter_nat n _ shiftl x.
Lemma nshiftl_S :
forall n x, nshiftl (S n) x = shiftl (nshiftl n x).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl (S n) x = nshiftl n (shiftl x).
Proof.
induction n; simpl; auto.
intros; rewrite nshiftl_S, IHn, nshiftl_S; auto.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl n 0 = 0.
Proof.
induction n; simpl; auto.
rewrite nshiftl_S, IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl size x = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl k x = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite nshiftl_S, IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl (pred size) x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr (pred size) x).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr (pred size) x = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr n x = 0 -> nshiftr p x = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite nshiftr_S; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr n x = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr (size - n) x)).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr (S (size - S n)) x)).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr (size-size) x); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr (size - n) x) =
recr_aux p A case0 caserec (nshiftr (size - n) x).
Proof.
induction n.
simpl; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr (size - S n) x)); auto.
f_equal.
change (shiftr (nshiftr (size - S n) x)) with (nshiftr (S (size - S n)) x).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr (size - size) x).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Zdouble | D1 => Zdouble_plus_one end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Zdouble (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Zdouble_plus_one (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Zdouble (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Zdouble_plus_one (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Zdouble_mult; omega.
specialize IHn with (shiftr x); rewrite Zdouble_plus_one_mult; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr (size-n) x) < 2 ^ (Z_of_nat n))%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr (size - S n) x))).
assert (shiftr (nshiftr (size - S n) x) = nshiftr (size-n) x).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr (size - n) x)) in *.
rewrite inj_S, Zpower_Zsucc; auto with zarith.
case_eq (firstr (nshiftr (size - S n) x)); intros.
rewrite Zdouble_mult; auto with zarith.
rewrite Zdouble_plus_one_mult; auto with zarith.
Qed.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z_of_nat size))%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
split.
apply phibis_aux_pos.
change x with (nshiftr (size-size) x).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr n x) = D1 ->
(2 ^ Z_of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Zdouble_plus_one_mult; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite inj_S, Zpower_Zsucc; auto with zarith.
assert (2^(Z_of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Zdouble (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Zdouble_plus_one_mult; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z_of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl n x = nshiftl n y.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
rewrite 2 nshiftl_S; f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl n x) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1; rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k).
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl k x) = i2l (nshiftl k y)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl k x) = i2l (nshiftl k y)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl k x)), <- (l2i_i2l (nshiftl k y)).
f_equal; auto.
Qed.
(** This equivalence allows to prove easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k).
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)).
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Zdouble_plus_one z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Zdouble z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Zsucc z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite Pplus_one_succ_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr (size-n) x)) =
nshiftr (size-n) x.
Proof.
induction n.
intros; simpl.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr (size-S n) x))).
assert (shiftr (nshiftr (size - S n) x) = nshiftr (size-n) x).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr (size - S n) x)); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr (size - S n) x) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr (size - S n) x) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr (size - size) x) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr n (snd (p2ibis n p)) = 0.
Proof.
induction n.
simpl; intros; auto.
simpl; intros.
destruct p; simpl.
specialize IHn with p.
destruct (p2ibis n p); simpl in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n).
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ l IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n).
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ l IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z_of_N (fst (p2ibis n p)))*2^(Z_of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pmult_1_r; auto.
replace (2^(Z_of_nat (S n)))%Z with (2*2^(Z_of_nat n))%Z by
(rewrite <- Zpower_Zsucc, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Zmult_comm 2).
assert (n<=size)%nat by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Zdouble_plus_one_mult.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Zdouble (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z_of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Zplus_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Zdouble_mult, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Zdouble_plus_one_mult,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z_of_N (fst (positive_to_int31 p)))*2^(Z_of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Zdouble (phi x)) mod 2^(Z_of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Zdouble (phi x)).
rewrite Zdouble_mult; generalize (phi_bounded x); omega.
destruct (Zdouble (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Zdouble_plus_one (phi x)) mod 2^(Z_of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Zdouble_plus_one (phi x)).
rewrite Zdouble_plus_one_mult; generalize (phi_bounded x); omega.
destruct (Zdouble_plus_one (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Zsucc (phi x)) mod 2^(Z_of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Zsucc (phi x)).
change (Zsucc (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Zsucc (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z_of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Zdouble_plus_one_mult.
replace (2*q+1) with (2*(Zsucc q)-1) by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Zdouble_mult, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z_of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z_of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, x at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, x at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Zcompare_Eq_iff_eq; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Zcompare_Eq_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Zcompare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); romega.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Zmult_lt_compat with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Zdiv; destruct (Zdiv_eucl (phi2 a1 a2) [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Zpower_pos 2 31) with wB; change (Zpower_pos 2 31) with wB in H.
rewrite H5, Zmult_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Zmult_gt_0_lt_reg_r with [|b|].
omega.
rewrite Zmult_comm.
apply Zle_lt_trans with ([|b|]*z+z0).
omega.
rewrite <- H5.
apply Zle_lt_trans with ([|a1|]*wB+(wB-1)).
omega.
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Zmult_le_compat; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Zdiv; destruct (Zdiv_eucl [|a|] [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Zmult_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Zle_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Zle_trans with ([|b|]*z); try omega.
rewrite <- (Zmult_1_l z) at 1.
apply Zmult_le_compat; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Zmod.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Zdiv_eucl [|a|] [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl.
rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Psize p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Zabs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- iter_nat_plus.
f_equal.
rewrite Zdouble_mult, Zmult_comm, <- Zplus_diag_eq_mult_2.
symmetry; apply Zabs_nat_Zplus; auto with zarith.
change (iter_nat (S (Zabs_nat z + Zabs_nat z)) A f a =
iter_nat (Zabs_nat (Zdouble_plus_one z)) A f a); f_equal.
rewrite Zdouble_plus_one_mult, Zmult_comm, <- Zplus_diag_eq_mult_2.
rewrite Zabs_nat_Zplus; auto with zarith.
rewrite Zabs_nat_Zplus; auto with zarith.
change (Zabs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Zabs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Zabs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite iter_nat_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z_of_nat (Zabs_nat [|p|])).
rewrite inj_Zabs_nat; symmetry; apply Zabs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs_nat_Z_of_nat.
set (n := Zabs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite inj_le_iff; auto with zarith.
clear p H; revert x y.
induction n.
simpl; intros.
change (Zpower_pos 2 31) with (2^31).
rewrite Zmult_1_r.
replace ([|y|] / 2^31) with 0.
rewrite Zplus_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Zdouble_mult.
rewrite phi_twice_firstl; auto.
change (Zdouble [|y|]) with (2*[|y|]).
rewrite inj_S, Zpower_Zsucc; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
apply Zplus_eq_compat.
ring.
replace (31-Z_of_nat n) with (Zsucc(31-Zsucc(Z_of_nat n))) by ring.
rewrite Zpower_Zsucc, <- Zdiv_Zdiv; auto with zarith.
rewrite Zmult_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Zdouble_plus_one_mult.
rewrite phi_twice; auto.
change (Zdouble [|y|]) with (2*[|y|]).
rewrite inj_S, Zpower_Zsucc; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Zmult_plus_distr_l, Zmult_1_l, <- Zplus_assoc.
f_equal.
apply Zplus_eq_compat.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z_of_nat (pred size)).
replace wB with (2*wB'); [ omega | ].
unfold wB'. rewrite <- Zpower_Zsucc, <- inj_S by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z_of_nat n)*2^(31-Z_of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Zminus; rewrite Zopp_mult_distr_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z_of_nat n) with (Zsucc(31-Zsucc(Z_of_nat n))) by ring.
rewrite Zpower_Zsucc, <- Zdiv_Zdiv; auto with zarith.
rewrite Zmult_comm, Z_div_mult; auto with zarith.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold ZnZ.pos_mod, int31_ops, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Zlt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Zcompare_Eq_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Zmult_0_l, Zplus_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Zle_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Zplus_0_r.
rewrite H4.
apply shift_unshift_mod_2; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z_of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z_of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by (apply plus_0_r; auto).
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z_of_nat (31-S n))|] = Z_of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z_of_nat O); apply inj_le; omega.
apply Zle_lt_trans with (Z_of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite inj_S; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl size x = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z_of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (inj_S (head031_alt n (shiftl x))), Zpower_Zsucc; auto with zarith.
rewrite <- Zmult_assoc, Zmult_comm, <- Zmult_assoc, <-(Zmult_comm 2).
rewrite <- Zdouble_mult, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z_of_nat 0)) with 1; rewrite Zmult_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z_of_nat 31)/2) with (2^(Z_of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z_of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z_of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by (apply plus_0_r; auto).
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z_of_nat (31-S n))|] = Z_of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z_of_nat O); apply inj_le; omega.
apply Zle_lt_trans with (Z_of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite inj_S; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr size x = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z_of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (inj_S (tail031_alt n (shiftr x))), Zpower_Zsucc; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Zdouble_mult, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Zdouble_plus_one_mult; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Zplus_0_l.
apply Zmult_le_0_compat; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Zmult_0_r, Zplus_0_r, Zplus_0_l.
generalize (sqr_pos (Zsucc j / 2)) (quotient_by_2 (Zsucc j));
unfold Zsucc.
rewrite Zpower_2, Zmult_plus_distr_l; repeat rewrite Zmult_plus_distr_r.
auto with zarith.
intros k Hk _.
replace ((Zsucc j + Zsucc k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Zsucc; repeat rewrite Zpower_2;
repeat rewrite Zmult_plus_distr_l; repeat rewrite Zmult_plus_distr_r.
repeat rewrite Zmult_1_l; repeat rewrite Zmult_1_r.
auto with zarith.
rewrite Zplus_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Zdiv); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Zlt_le_trans with (2 := sqrt_main_trick _ _ (Zlt_le_weak _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Zpower_2, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Zmult_plus_distr_l; repeat rewrite Zmult_plus_distr_r.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Zpower_2 in H2 |- *;
repeat (rewrite Zmult_plus_distr_l ||
rewrite Zmult_plus_distr_r ||
rewrite Zmult_1_l || rewrite Zmult_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Zpower_2.
apply Zle_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Zle_or_lt j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Zle_not_lt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Zle_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
(* George's trick *)
Inductive ZcompareSpec (i j: Z): comparison -> Prop :=
ZcompareSpecEq: i = j -> ZcompareSpec i j Eq
| ZcompareSpecLt: i < j -> ZcompareSpec i j Lt
| ZcompareSpecGt: j < i -> ZcompareSpec i j Gt.
Lemma Zcompare_spec i j: ZcompareSpec i j (i ?= j).
Proof.
case_eq (Zcompare i j); intros H.
apply ZcompareSpecEq; apply Zcompare_Eq_eq; auto.
apply ZcompareSpecLt; auto.
apply ZcompareSpecGt; apply Zgt_lt; auto.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (refl_equal Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Zcompare_spec; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec; repeat rewrite div31_phi; auto with zarith.
replace [|(j + fst (i / j)%int31)|] with ([|j|] + [|i|] / [|j|]).
split.
case (Zle_lt_or_eq 1 [|j|]); auto with zarith; intros Hj1.
replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by (apply Z_div_pos; auto with zarith).
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]) ; auto with zarith.
rewrite <- Hj1, Zdiv_1_r.
replace (1 + [|i|])%Z with (1 * 2 + ([|i|] - 1))%Z; try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2)%Z by (apply Z_div_pos; auto with zarith).
change ([|2|]) with 2%Z; auto with zarith.
apply sqrt_test_false; auto with zarith.
rewrite spec_add, div31_phi; auto.
apply sym_equal; apply Zmod_small.
split; auto with zarith.
replace [|j + fst (i / j)%int31|] with ([|j|] + [|i|] / [|j|]).
apply sqrt_main; auto with zarith.
rewrite spec_add, div31_phi; auto.
apply sym_equal; apply Zmod_small.
split; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z_of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z_of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z_of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Zpower_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite inj_S, Zpower_Zsucc.
apply Zle_trans with (2 ^Z_of_nat n + [|j2|]); auto with zarith.
apply Zle_0_nat.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Zcompare_spec; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Zpower_2; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Zle_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Zlt_not_le.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Zle_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Zle_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Zpower_2; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert (([|ih|] < [|j|] + 1)%Z); auto with zarith.
apply Zlt_square_simpl; auto with zarith.
repeat rewrite <-Zpower_2; apply Zle_lt_trans with (2 := H1).
apply Zle_trans with ([|ih|] * base)%Z; unfold phi2, base;
try rewrite Zpower_2; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl fst; apply trans_equal with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (refl_equal Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])%Z) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
unfold phi2; apply Zlt_le_trans with ([|ih|] * base)%Z; auto with zarith.
apply Zmult_lt_0_compat; auto with zarith.
apply Zlt_le_trans with (2:= Hih); auto with zarith.
rewrite spec_compare. case Zcompare_spec; intros Hc1.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Zmult_comm, Z_div_plus_full_l; unfold base; auto with zarith.
unfold Zpower, Zpower_pos in Hj1; simpl in Hj1; auto with zarith.
case (Zle_or_lt (2 ^ 30) [|j|]); intros Hjj.
rewrite spec_compare; case Zcompare_spec;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
assert (Hf1: 0 <= phi2 ih il/ [|j|]) by (apply Z_div_pos; auto with zarith).
case (Zle_lt_or_eq 1 ([|j|])); auto with zarith; intros Hf2.
2: contradict Hc; apply Zle_not_lt; rewrite <- Hf2, Zdiv_1_r; auto with zarith.
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
replace ([|j|] + phi2 ih il/ [|j|])%Z with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ; auto with zarith.
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
apply sqrt_test_false; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; change [|2|] with 2%Z; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith.
rewrite spec_add, div31_phi; change [|2|] with 2%Z; auto.
rewrite Zmult_1_l; intros HH.
rewrite Zplus_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z_of_nat size).
rewrite HH, Zmod_small; auto with zarith.
replace (phi
match j +c fst (div3121 ih il j) with
| C0 m1 => fst (m1 / 2)%int31
| C1 m1 => fst (m1 / 2)%int31 + v30
end) with ((([|j|] + (phi2 ih il)/([|j|]))/2)).
apply sqrt_main; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith.
intros HH; rewrite <- HH.
change (1 * 2 ^ Z_of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Zplus_comm.
rewrite spec_add, Zmod_small.
rewrite div31_phi; auto.
split; auto with zarith.
case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
rewrite div31_phi; change (phi 2) with 2%Z; auto.
change (2 ^Z_of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Zmult_gt_0_lt_reg_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Zle_lt_trans with (phi r).
rewrite Zmult_comm; apply Z_mult_div_ge; auto with zarith.
case (phi_bounded r); auto with zarith.
contradict Hij; apply Zle_not_lt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Zle_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
assert (0 <= 1 + [|j|]); auto with zarith.
apply Zmult_le_compat; auto with zarith.
change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Zle_trans with ([|ih|] * base); auto with zarith.
unfold phi2, base; auto with zarith.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
apply Zle_ge; apply Zle_trans with (([|j|] * base)/[|j|]).
rewrite Zmult_comm, Z_div_mult; auto with zarith.
apply Zge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z_of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Zpower_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite inj_S, Zpower_Zsucc.
apply Zle_trans with (2 ^Z_of_nat n + [|j2|])%Z; auto with zarith.
apply Zle_0_nat.
Qed.
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
change ((phi Tn + 1) ^ 2) with (2^62).
apply Zle_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Zpower_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Zpower, Zpower_pos in H2,H4; simpl in H2,H4.
unfold phi2,Zpower, Zpower_pos; simpl iter_pos; auto with zarith.
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Zlt_not_le.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z_of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
case (Zmult_integral _ _ (sym_equal HH)); auto.
contradict Hs2; apply Zle_not_lt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Zle_trans with (2 ^ Z_of_nat size / 4 * base).
simpl; auto with zarith.
apply Zle_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
simpl interp_carry in Hil2.
rewrite spec_compare; case Zcompare_spec.
unfold interp_carry.
intros H1; split.
rewrite Zpower_2, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Zlt_not_le; rewrite Zpower_2, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Zlt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Zmult_plus_distr_l, Zplus_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Zplus_le_compat; auto with zarith.
unfold interp_carry; change (1 * 2 ^ Z_of_nat size) with base.
rewrite Zpower_2, <- Hihl1, Hil2.
intros H1.
case (Zle_lt_or_eq ([|ih1|] + 1) ([|ih|])); auto with zarith.
intros H2; contradict Hs2; apply Zle_not_lt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
case (phi_bounded il2); rewrite Hil2; auto with zarith.
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z_of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Zle_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Zmult_plus_distr_l.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
intros H2; split.
unfold phi2; rewrite <- H2; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H2; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z_of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z_of_nat size / 4) with 536870912.
split; auto with zarith.
rewrite spec_compare; case Zcompare_spec.
rewrite Hsih.
intros H1; split.
rewrite Zpower_2, <- Hihl1.
unfold phi2; rewrite <-H1.
apply trans_equal with ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z_of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
apply trans_equal with (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z_of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
apply Zle_antisym; auto with zarith.
case (Zle_or_lt [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Zlt_not_le; rewrite Zpower_2, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z_of_nat size) with base;
intros _ Hpil1.
apply Zlt_le_trans with (([|ih|] + 1) * base).
rewrite Zmult_plus_distr_l, Zmult_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Zle_trans with (([|ih1|]) * base); auto with zarith.
rewrite Zpower_2, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Zlt_not_le; rewrite Zpower_2, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Zpower_2, <-Hihl1.
case (Zle_lt_or_eq ([|ih1|] + 2) [|ih|]); auto with zarith.
intros H2; contradict Hs2; apply Zle_not_lt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z_of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Zle_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z_of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Zle_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Zmult_plus_distr_l in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
intros H2; unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z_of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z_of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0; simpl.
unfold compare31; simpl; intros.
change [|0|] with 0 in H.
apply Zcompare_Eq_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even; simpl; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Zcompare_spec; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_j_pack_out_gen.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_j_pack_out_gen -- J_PACK_OUT generator.
// _____________________________________________________________________________
//
`include "sys.h"
`include "jbi.h"
module jbi_j_pack_out_gen (/*AUTOARG*/
// Outputs
jbi_io_j_pack0, jbi_io_j_pack0_en,
jbi_io_j_pack1, jbi_io_j_pack1_en,
// Inputs
min_snp_launch, send_aok_off, send_aok_on, send_dok_off, send_dok_on,
dok_fatal_req_csr, dok_fatal_req_sctag, csr_jbi_error_config_fe_enb,
clk, rst_l, cclk, crst_l, tx_en_local_m1
);
`include "jbi_mout.h"
// COHACK response requests.
input min_snp_launch;
// Flow Control.
input send_aok_off;
input send_aok_on;
input send_dok_off;
input send_dok_on;
// Fatal error control.
input dok_fatal_req_csr; // CSR request for DOK Fatal.
input [3:0] dok_fatal_req_sctag; // SCTAG3-0 requests for DOK Fatal.
input csr_jbi_error_config_fe_enb; // Enable DOK Fatal for non-JBI fatal errors.
// JPack out.
output [2:0] jbi_io_j_pack0;
output jbi_io_j_pack0_en;
output [2:0] jbi_io_j_pack1;
output jbi_io_j_pack1_en;
// Clock and reset.
input clk;
input rst_l;
input cclk;
input crst_l;
input tx_en_local_m1;
// Wires and Regs.
wire cohack_valid, send_dok_fatal;
wire [1:0] state;
reg cohack_dequeue;
reg [1:0] next_state;
reg [2:0] jbi_io_j_pack_out;
// Add last stage of distribution pipeline to 'tx_en'.
dff_ns u_dff_ctu_jbi_tx_en_mout_ff (.din(tx_en_local_m1), .q(tx_en), .clk(cclk));
// J_PACK_OUT encoded state machine.
parameter IDLE = 2'h0,
DOK_FATAL2 = 2'h1,
DOK_FATAL3 = 2'h2,
DOK_FATAL4 = 2'h3,
DOK_X = 2'hx;
parameter JBI_P_X = 3'bx;
dffrl_ns #(2) state_reg (.din(next_state), .q(state), .rst_l(rst_l), .clk(clk));
always @(/*AS*/cohack_dequeue or cohack_valid
or jbi_io_j_pack_out or next_state or send_aok_off or send_aok_on
or send_dok_fatal or send_dok_off or send_dok_on
or state) begin
casex ({ state, send_dok_fatal, send_aok_off, send_dok_off, send_aok_on, send_dok_on, cohack_valid })
`define out { next_state, cohack_dequeue, jbi_io_j_pack_out }
// send send send send send ][
// Current dok aok dok aok dok cohack ][ next cohack j_pack
// State fatal off off on on valid ][ state dequeue out
// ---------------------------------------------------------++-----------------------------------------------
// IDLE - Waiting for a request.
{ IDLE, N, N, N, N, N, N }: `out = { IDLE, N, `JBI_P_IDLE };
{ IDLE, Y, x, x, x, x, x }: `out = { DOK_FATAL2, N, `JBI_P_DOK_ON };
{ IDLE, N, Y, x, x, x, x }: `out = { IDLE, N, `JBI_P_AOK_OFF };
{ IDLE, N, N, Y, x, x, x }: `out = { IDLE, N, `JBI_P_DOK_OFF };
{ IDLE, N, N, N, Y, x, x }: `out = { IDLE, N, `JBI_P_AOK_ON };
{ IDLE, N, N, N, N, Y, x }: `out = { IDLE, N, `JBI_P_DOK_ON };
{ IDLE, N, N, N, N, N, Y }: `out = { IDLE, Y, `JBI_P_COHACK };
// DOK_FATAL - Created by sending a 'DOK_ON' for 4 cycles.
{ DOK_FATAL2, x, x, x, x, x, x }: `out = { DOK_FATAL3, N, `JBI_P_DOK_ON };
{ DOK_FATAL3, x, x, x, x, x, x }: `out = { DOK_FATAL4, N, `JBI_P_DOK_ON };
{ DOK_FATAL4, x, x, x, x, x, x }: `out = { IDLE, N, `JBI_P_DOK_ON };
// CoverMeter line_off
default: `out = { DOK_X, x, JBI_P_X };
// CoverMeter line_on
`undef out
endcase
end
assign jbi_io_j_pack0 = jbi_io_j_pack_out;
assign jbi_io_j_pack0_en = 1'b1;
assign jbi_io_j_pack1 = jbi_io_j_pack_out;
assign jbi_io_j_pack1_en = 1'b1;
// Queue the snoop requests.
jbi_snoop_out_queue snoop_out_queue (
// Tail of queue.
.enqueue (min_snp_launch),
// Head of queue.
.valid (cohack_valid),
.dequeue (cohack_dequeue),
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Register, pulse catch, synchronize, and collect up cmp_clk domain DOK Fatal requests.
//
// Register.
wire next_sctag_req_p1 = (|dok_fatal_req_sctag[3:0]);
dff_ns sctag_req_p1_reg (.din(next_sctag_req_p1), .q(sctag_req_p1), .clk(cclk));
//
// Pulse catcher. Cleared when transferred to 'sctag_req_presync_reg[]'.
wire set_sctag_req_p2 = sctag_req_p1;
wire clr_sctag_req_p2 = tx_en; // Asserting set and clr resolves in favor of set.
srffrl_ns sctag_req_p2_reg (.set(set_sctag_req_p2), .clr(clr_sctag_req_p2), .rst_l(crst_l), .clk(cclk), .q(sctag_req_p2));
//
// Cmp Clock to JBus Clock synchronizer.
wire next_sctag_req_presync = sctag_req_p2;
wire sctag_req_presync_en = tx_en;
dffe_ns sctag_req_presync_reg (.din(next_sctag_req_presync), .en(sctag_req_presync_en), .q(sctag_req_presync), .clk(cclk));
//
wire next_sctag_req_sync = sctag_req_presync;
dff_ns sctag_req_sync_reg (.din(next_sctag_req_sync), .q(sctag_req_sync), .clk(clk));
//
// (send_dok_fatal only needs to be pulsed since the state machine is constructed such that it will always see it.)
assign send_dok_fatal = dok_fatal_req_csr || (sctag_req_sync && csr_jbi_error_config_fe_enb);
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Track DOK/AOK on/off for checks.
reg dok;
reg aok;
initial begin
dok = Y;
aok = Y;
end
always @(posedge clk) begin
if (send_aok_off)
aok <= #1 N;
if (send_aok_on)
aok <= #1 Y;
if (send_dok_off)
dok <= #1 N;
if (send_dok_on)
dok <= #1 Y;
end
// Check: Verify that offs are only requested when on, and that ons are only requested when off.
always @(posedge clk) begin
if (rst_l && (send_aok_off && !aok || send_aok_on && aok)) begin
$dispmon ("jbi_mout_jbi_j_pack_out_gen", 49, "%d %m: ERROR - Duplicate on/off being sent to AOK. (on=%b, off=%b, state=%b).", $time, send_aok_on, send_aok_off, aok);
end
if (rst_l && !send_dok_fatal && (send_dok_off && !dok || send_dok_on && dok)) begin
$dispmon ("jbi_mout_jbi_j_pack_out_gen", 49, "%d %m: ERROR - Duplicate on/off being sent to DOK. (on=%b, off=%b, state=%b).", $time, send_dok_on, send_dok_off, dok);
end
end
// Check: State machine has valid state.
always @(posedge clk) begin
if (next_state === DOK_X) begin
$dispmon ("jbi_mout_jbi_j_pack_out_gen", 49, "%d %m: ERROR - J_PACK_OUT state machine is confused about its next transition. (%b)", $time, state);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../include" "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-auto-read-includes:t
// verilog-module-parents:("jbi_mout")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRTN_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtn (
RESET_B,
D ,
GATE_N ,
Q
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_SYMBOL_V
`define SKY130_FD_SC_LP__SDLCLKP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX_test.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { [email protected], [email protected] } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 36 "Physical Coding Sublayer(PCS) ////
//// and Physical Medium Attachment (PMA) sublayer, type ////
//// 1000BASE-X"; see : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section3.pdf, Clause/Section 36. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module ge_1000baseX_test
(
// --- Resets ---
input reset_pin,
// --- GE 125MHz reference clock ---
input GE_125MHz_ref_ckpin,
// --- FO TBI 125MHz Rx clk ---
input tbi_rx_ckpin,
// --- Fibre-Optic (fo) GE TBI Interface ---
input [9:0] tbi_rxd,
output [9:0] tbi_txd,
// --- GMII interface ---
output [7:0] gmii_rxd,
output gmii_rx_dv,
output gmii_rx_er,
output gmii_col,
output gmii_cs,
input [7:0] gmii_txd,
input gmii_tx_en,
input gmii_tx_er,
// --- Fibre-Optic (fo) ctrl signals ---
output sync_en,
output loop_en,
output prbs_en,
input signal_detect,
input sync,
// --- MDIO interface
inout mdio,
input mdio_ckpin
);
assign sync_en = 1'b0;
assign loop_en = 1'b0;
assign prbs_en = 1'b0;
//----------------------------------------------------------------------------
// MDIO/MDC clock buffering
//----------------------------------------------------------------------------
IBUFG mdio_ckpin_bufi(.I(mdio_ckpin), .O(mdio_ckpin_buf));
BUFG mdio_ck_bufi(.I(mdio_ckpin_buf), .O(mdc));
//----------------------------------------------------------------------------
// GE 125MHz reference clock
//----------------------------------------------------------------------------
IBUFG GE_125MHz_ref_ckpin_bufi(.I(GE_125MHz_ref_ckpin), .O(GE_125MHz_ref_ckpin_buf));
wire GE_125MHz_ref_ck_locked;
DCM #(
.CLKIN_PERIOD(8.0), // Specify period of input clock in ns
.CLKFX_MULTIPLY(5),
.CLKFX_DIVIDE(8)
) GE_125MHz_ref_ck_DCMi(
.CLK0(GE_125MHz_ref_ck_unbuf),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(GE_125MHz_ref_ck_locked),
.PSDONE(),
.STATUS(),
.CLKFB(GE_125MHz_ref_ck),
.CLKIN(GE_125MHz_ref_ckpin_buf),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(reset_pin)
);
//----------------------------------------------------------------------------
// 125MHz refence clock
//----------------------------------------------------------------------------
`ifdef MODEL_TECH
BUFG GE_125MHz_ref_ck_bufi(.I(GE_125MHz_ref_ck_unbuf), .O(GE_125MHz_ref_ck));
`else
BUFGMUX GE_125MHz_ref_ck_bufi(.I1(GE_125MHz_ref_ck_unbuf), .O(GE_125MHz_ref_ck), .S(1'b1));
`endif
//----------------------------------------------------------------------------
// Fibre-Optic (FO) TBI RX clock.
//----------------------------------------------------------------------------
IBUFG tbi_rx_ckpin_bufi(.I(tbi_rx_ckpin), .O(tbi_rx_ckpin_buf));
DCM #(
.CLKIN_PERIOD(8.0)
) tbi_rx_ck_DCMi(
.CLK0(tbi_rx_ck_unbuf),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.LOCKED(tbi_rx_ck_locked),
.PSDONE(),
.STATUS(),
.CLKFB(tbi_rx_ck),
.CLKIN(tbi_rx_ckpin_buf),
.DSSEN(1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(reset_pin)
);
// FO TBI 125MHz rx clock
BUFG tbi_rx_ck_bufi( .I(tbi_rx_ck_unbuf), .O(tbi_rx_ck));
//----------------------------------------------------------------------------
// Reset Cleaners
//----------------------------------------------------------------------------
wire main_clocks_locked = GE_125MHz_ref_ck_locked;
wire tbi_rxck_reset_in = reset_pin | ~main_clocks_locked;
wire GE_125MHz_reset_in = reset_pin | ~main_clocks_locked;
wire mdc_reset_in = reset_pin | ~main_clocks_locked;
wire GE_125MHz_reset, tbi_rx_reset;
clean_rst GE_125MHz_reset_cleaneri(.clk(GE_125MHz_ref_ck), .rsti(GE_125MHz_reset_in), .rsto(GE_125MHz_reset));
clean_rst tbi_rx_reset_cleaneri( .clk(tbi_rx_ck), .rsti(tbi_rxck_reset_in), .rsto(tbi_rx_reset));
clean_rst mdc_reset_cleaneri( .clk(mdc), .rsti(mdc_reset_in), .rsto(mdc_reset));
//-------------------------------------------------------------------------------
// --- IEEE 802.3-2008 1000baseX PCS ---
//-------------------------------------------------------------------------------
ge_1000baseX ge_1000baseX_i(
// --- Clocks ---
.rx_ck(tbi_rx_ck), .tx_ck(GE_125MHz_ref_ck),
// --- resets ---
.tx_reset(GE_125MHz_reset), .rx_reset(tbi_rx_reset),
// --- Startup interface. ---
.startup_enable(~GE_125MHz_reset),
// --- Signal detect from FO transceiver
.signal_detect(signal_detect),
// --- Receive GMII bus ---
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_col(gmii_col),
.gmii_cs(gmii_cs),
// --- Transmit GMII bus ---
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.gmii_txd(gmii_txd),
// --- Receive 8B10B bus ---
.tbi_rxd(tbi_rxd),
// --- Transmit 8B10B bus ---
.tbi_txd(tbi_txd),
// --- Mode of operation ---
.repeater_mode(1'b0),
// --- MDIO interface ---
.mdc_reset(mdc_reset),
.mdc(mdc),
.mdio(mdio)/* synthesis xc_pullup = 1 */
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_0_V
`define SKY130_FD_SC_LP__O311A_0_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_0 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_0 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR3B_BEHAVIORAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_clk_gl(gclk_jbus_c0_r ,clk_fdbk_in ,clk_fdbk_out ,
gclk_cmp_c3_r ,gclk_ddr_c3_r ,gclk_jbus_c2_r ,gclk_cmp_c2_r ,
gclk_ddr_c2_r ,gclk_jbus_c1_r ,gclk_cmp_c1_r ,gclk_ddr_c1_r ,
gclk_cmp_c0_r ,gclk_jbus ,gclk_ddr ,gclk_cmp ,gclk_jbus_c3_r ,
gclk_ddr_c0_r );
output [7:0] gclk_jbus_c0_r ;
output [7:0] gclk_cmp_c3_r ;
output [7:0] gclk_ddr_c3_r ;
output [7:0] gclk_jbus_c2_r ;
output [7:0] gclk_cmp_c2_r ;
output [7:0] gclk_ddr_c2_r ;
output [7:0] gclk_jbus_c1_r ;
output [7:0] gclk_cmp_c1_r ;
output [7:0] gclk_ddr_c1_r ;
output [7:0] gclk_cmp_c0_r ;
output [7:0] gclk_jbus_c3_r ;
output [7:0] gclk_ddr_c0_r ;
output clk_fdbk_out ;
input clk_fdbk_in ;
input gclk_jbus ;
input gclk_ddr ;
input gclk_cmp ;
wire [2:1] ddr_col1_c8 ;
wire [2:1] cmp_col3_c9 ;
wire [3:0] cmp_c11 ;
wire [2:1] ddr_col2_c9 ;
wire [2:1] ddr_col0_c8 ;
wire [2:1] cmp_col0_c8 ;
wire [2:1] ddr_col1_c9 ;
wire [2:1] cmp_col1_c8 ;
wire [2:1] jbus_col3_c8 ;
wire [2:1] ddr_col0_c9 ;
wire [2:1] cmp_col2_c8 ;
wire [3:0] ddr_c11 ;
wire [2:1] ddr_col3_c8 ;
wire [2:1] cmp_col0_c9 ;
wire [3:0] jbus_c11 ;
wire [2:1] cmp_col1_c9 ;
wire [2:1] jbus_col3_c9 ;
wire [2:1] cmp_col2_c9 ;
wire [2:1] jbus_col0_c8 ;
wire [2:1] ddr_col3_c9 ;
wire [2:1] jbus_col1_c8 ;
wire [2:1] jbus_col2_c8 ;
wire [2:1] jbus_col0_c9 ;
wire [2:1] cmp_col3_c8 ;
wire [2:1] jbus_col1_c9 ;
wire [2:1] ddr_col2_c8 ;
wire [2:1] jbus_col2_c9 ;
wire jbus_center ;
wire cmp_center ;
wire fdbk_center ;
wire ddr_center ;
bw_clk_gclk_inv_224x x3 (
.clkout (fdbk_center ),
.clkin (clk_fdbk_in ) );
bw_clk_gclk_sctag_3inv xc2_sctag_0_ (
.jbus_out (jbus_col2_c8[1] ),
.ddr_out (ddr_col2_c8[1] ),
.cmp_out (cmp_col2_c8[1] ),
.jbus_in (jbus_col2_c9[1] ),
.ddr_in (ddr_col2_c9[1] ),
.cmp_in (cmp_col2_c9[1] ) );
bw_clk_gl_vrt_all xcol_0_ (
.cmp_sctag_out ({cmp_col0_c9 } ),
.cmp_sctag_in ({cmp_col0_c8 } ),
.ddr_sctag_in ({ddr_col0_c8 } ),
.ddr_sctag_out ({ddr_col0_c9 } ),
.jbus_sctag_in ({jbus_col0_c8 } ),
.jbus_sctag_out ({jbus_col0_c9 } ),
.gclk_jbus ({gclk_jbus_c0_r } ),
.gclk_cmp ({gclk_cmp_c0_r } ),
.gclk_ddr ({gclk_ddr_c0_r } ),
.jbus_c12 (jbus_c11[0] ),
.cmp_c12 (cmp_c11[0] ),
.ddr_c12 (ddr_c11[0] ) );
bw_clk_gclk_sctag_3inv xc1_sctag_1_ (
.jbus_out (jbus_col1_c8[2] ),
.ddr_out (ddr_col1_c8[2] ),
.cmp_out (cmp_col1_c8[2] ),
.jbus_in (jbus_col1_c9[2] ),
.ddr_in (ddr_col1_c9[2] ),
.cmp_in (cmp_col1_c9[2] ) );
bw_clk_gclk_sctag_3inv xc3_sctag_0_ (
.jbus_out (jbus_col3_c8[1] ),
.ddr_out (ddr_col3_c8[1] ),
.cmp_out (cmp_col3_c8[1] ),
.jbus_in (jbus_col3_c9[1] ),
.ddr_in (ddr_col3_c9[1] ),
.cmp_in (cmp_col3_c9[1] ) );
bw_clk_gclk_sctag_3inv xc2_sctag_1_ (
.jbus_out (jbus_col2_c8[2] ),
.ddr_out (ddr_col2_c8[2] ),
.cmp_out (cmp_col2_c8[2] ),
.jbus_in (jbus_col2_c9[2] ),
.ddr_in (ddr_col2_c9[2] ),
.cmp_in (cmp_col2_c9[2] ) );
bw_clk_gclk_center_3inv xcenter (
.jbus_out (jbus_center ),
.ddr_out (ddr_center ),
.cmp_out (cmp_center ),
.jbus_in (gclk_jbus ),
.ddr_in (gclk_ddr ),
.cmp_in (gclk_cmp ) );
bw_clk_gl_vrt_all xcol_3_ (
.cmp_sctag_out ({cmp_col3_c9 } ),
.cmp_sctag_in ({cmp_col3_c8 } ),
.ddr_sctag_in ({ddr_col3_c8 } ),
.ddr_sctag_out ({ddr_col3_c9 } ),
.jbus_sctag_in ({jbus_col3_c8 } ),
.jbus_sctag_out ({jbus_col3_c9 } ),
.gclk_jbus ({gclk_jbus_c3_r } ),
.gclk_cmp ({gclk_cmp_c3_r } ),
.gclk_ddr ({gclk_ddr_c3_r } ),
.jbus_c12 (jbus_c11[3] ),
.cmp_c12 (cmp_c11[3] ),
.ddr_c12 (ddr_c11[3] ) );
bw_clk_gclk_sctag_3inv xc0_sctag_0_ (
.jbus_out (jbus_col0_c8[1] ),
.ddr_out (ddr_col0_c8[1] ),
.cmp_out (cmp_col0_c8[1] ),
.jbus_in (jbus_col0_c9[1] ),
.ddr_in (ddr_col0_c9[1] ),
.cmp_in (cmp_col0_c9[1] ) );
bw_clk_gclk_sctag_3inv xc3_sctag_1_ (
.jbus_out (jbus_col3_c8[2] ),
.ddr_out (ddr_col3_c8[2] ),
.cmp_out (cmp_col3_c8[2] ),
.jbus_in (jbus_col3_c9[2] ),
.ddr_in (ddr_col3_c9[2] ),
.cmp_in (cmp_col3_c9[2] ) );
bw_clk_gl_fdbk xfdbk (
.clk_fdbk_in (fdbk_center ),
.clk_fdbk_out (clk_fdbk_out ) );
bw_clk_gl_vrt_all xcol_1_ (
.cmp_sctag_out ({cmp_col1_c9 } ),
.cmp_sctag_in ({cmp_col1_c8 } ),
.ddr_sctag_in ({ddr_col1_c8 } ),
.ddr_sctag_out ({ddr_col1_c9 } ),
.jbus_sctag_in ({jbus_col1_c8 } ),
.jbus_sctag_out ({jbus_col1_c9 } ),
.gclk_jbus ({gclk_jbus_c1_r } ),
.gclk_cmp ({gclk_cmp_c1_r } ),
.gclk_ddr ({gclk_ddr_c1_r } ),
.jbus_c12 (jbus_c11[1] ),
.cmp_c12 (cmp_c11[1] ),
.ddr_c12 (ddr_c11[1] ) );
bw_clk_gclk_sctag_3inv xc1_sctag_0_ (
.jbus_out (jbus_col1_c8[1] ),
.ddr_out (ddr_col1_c8[1] ),
.cmp_out (cmp_col1_c8[1] ),
.jbus_in (jbus_col1_c9[1] ),
.ddr_in (ddr_col1_c9[1] ),
.cmp_in (cmp_col1_c9[1] ) );
bw_clk_gl_hz xrow (
.cmp_c11 ({cmp_c11 } ),
.jbus_c11 ({jbus_c11 } ),
.ddr_c11 ({ddr_c11 } ),
.ddr_center (ddr_center ),
.jbus_center (jbus_center ),
.cmp_center (cmp_center ) );
bw_clk_gl_vrt_all xcol_2_ (
.cmp_sctag_out ({cmp_col2_c9 } ),
.cmp_sctag_in ({cmp_col2_c8 } ),
.ddr_sctag_in ({ddr_col2_c8 } ),
.ddr_sctag_out ({ddr_col2_c9 } ),
.jbus_sctag_in ({jbus_col2_c8 } ),
.jbus_sctag_out ({jbus_col2_c9 } ),
.gclk_jbus ({gclk_jbus_c2_r } ),
.gclk_cmp ({gclk_cmp_c2_r } ),
.gclk_ddr ({gclk_ddr_c2_r } ),
.jbus_c12 (jbus_c11[2] ),
.cmp_c12 (cmp_c11[2] ),
.ddr_c12 (ddr_c11[2] ) );
bw_clk_gclk_sctag_3inv xc0_sctag_1_ (
.jbus_out (jbus_col0_c8[2] ),
.ddr_out (ddr_col0_c8[2] ),
.cmp_out (cmp_col0_c8[2] ),
.jbus_in (jbus_col0_c9[2] ),
.ddr_in (ddr_col0_c9[2] ),
.cmp_in (cmp_col0_c9[2] ) );
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:34:54 11/17/2015
// Design Name:
// Module Name: Datapath1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Datapath1(
input clock,
input resetGral,
input uartRxPin,
output uartTxPin,
output ALUzero,
output ALUOverflow,
output ledStep,
output ledCont,
output ledIdle,
output ledSend
);
assign ALUzero=aluZero;
assign ALUOverflow=aluOverflow;
wire [31:0]instruction;
wire [31:0]instructionID;
wire regWrite;
wire regWriteEX;
wire regWriteMEM;
wire regWriteWB;
wire memToReg;
wire memToRegEX;
wire memToRegMEM;
wire memToRegWB;
wire [3:0]memWrite;
wire [3:0]memWriteEX;
wire [3:0]memWriteMEM;
wire [3:0]aluControl;
wire [3:0]aluControlEX;
wire aluSrc;
wire aluSrcEX;
wire aluShiftImm;
wire aluShiftImmEX;
wire regDst;
wire regDstEX;
wire loadImm;
wire loadImmEX;
wire branch;
wire branchType;
wire eopFlag;
wire eopFlagEX;
wire eopFlagMEM;
wire eopFlagWB;
wire [1:0] memReadWidth;
wire [1:0] memReadWidthEX;
wire [1:0] memReadWidthMEM;
wire [31:0]sigExtOut;
wire [31:0]sigExtEX;
wire zeroExtendFlag;
wire [31:0]aluOut;
wire [31:0]aluOutMEM;
wire [31:0]aluOutWB;
wire aluZero;
wire aluOverflow;
wire [31:0]readData1;
wire [31:0]readData1EX;
wire [31:0]readData2;
wire [31:0]readData2EX;
wire [31:0]readDataMemory;
wire [31:0]readDataMemoryMasked;
wire [31:0]memoryOutWB;
wire [7:0] PC;
wire [7:0] pcFE;
wire [7:0] pcNext;
wire [7:0] pcNextID;
wire [4:0]rsEX;
wire [4:0]rtEX;
wire [4:0]rdEX;
wire [4:0]saEX;
wire [4:0]writeRegisterMEM;
wire [4:0]writeRegisterWB;
wire [7:0]pcBranchAddr;
wire [31:0] writeDataEX;
wire [31:0] writeDataMEM;
//Salidas Hazard Unit
wire stallFE;
wire stallID;
wire forwardAID;
wire forwardBID;
wire flushEX;
wire [1:0] forwardAEX;
wire [1:0] forwardBEX;
wire uartWriteFlag;
wire uartReadFlag;
wire [7:0]uartFifoDataIn;
wire uartDataAvailable;
wire [7:0]dataToUartOutFifo;
wire debugEnable;
wire debugReset;
//Multiplexores:
//Declaracion
wire [4:0]writeRegister;
wire [31:0]aluOperand1;
wire [31:0]aluOperand2;
// wire [31:0]sigExtShifted; //No se usa el shifted porque se accede con valores absolutos a la memoria de instr
wire [31:0] resultWB;
wire branchTaken;
//Asignacion
assign writeRegister = (regDstEX)? rdEX : rtEX;
assign aluOperand1 = (loadImmEX)? 'd16 : ((aluShiftImmEX)? saEX: srcAEX);
assign aluOperand2 = (aluSrcEX)? sigExtEX: srcBEX;
// assign sigExtShifted = sigExtOut<<2; //No se usa el shifted porque se accede con valores absolutos a la memoria de instr
assign pcSrc = branch & branchTaken;
assign branchTaken = (branchType)? (branchSrcA!=branchSrcB) : (branchSrcA==branchSrcB); //branchType(flag from control) 1: check if branch NE 0: check if branch EQ
assign resultWB = (memToRegWB)? memoryOutWB : aluOutWB;
assign PC = (pcSrc)? pcBranchAddr : pcNext;
//Multiplexores Hazards:
//Declaracion
wire [31:0]srcAEX;
wire [31:0]srcBEX;
wire [31:0]branchSrcA;
wire [31:0]branchSrcB;
//Asignacion
assign srcAEX= (forwardAEX==0)? readData1EX : ((forwardAEX==1)? resultWB : aluOutMEM);
assign srcBEX= (forwardBEX==0)? readData2EX : ((forwardBEX==1)? resultWB : aluOutMEM);
assign writeDataEX = srcBEX;
assign branchSrcA= (forwardAID)? aluOutMEM: readData1;
assign branchSrcB= (forwardBID)? aluOutMEM: readData2;
ControlUnit control(
.Special(instructionID[31:26]),
.instructionCode(instructionID[5:0]),
.RegDst(regDst),
.Branch(branch),
.BranchType(branchType),
.MemtoReg(memToReg),
.MemWrite(memWrite),
.ALUSrc(aluSrc),
.ALUShiftImm(aluShiftImm),
.RegWrite(regWrite),
.LoadImm(loadImm),
.ZeroEx(zeroExtendFlag),
.EOP(eopFlag),
.memReadWidth(memReadWidth), // 0:Word 1:Halfword 2:Byte
.aluOperation(aluControl)
);
RAM ram(
.clka(clock), // input clka niego el clock para no perder un ciclo en la lectura
.wea(memWriteMEM),
.addra(aluOutMEM[7:0]), // input [7 : 0] addra
.dina(writeDataMEM), // input [31 : 0] dina
.douta(readDataMemory) // output [31 : 0] douta
);
instructionROM instructionMemory (
.clka(clock), // input clka
.addra(pcFE), // input [7 : 0] addra
.douta(instruction) // output [31 : 0] douta
);
REGBANK_banco bank(
.clock(clock),
.regWrite(regWriteWB),
.readReg1(instructionID[25:21]),
.readReg2(instructionID[20:16]),
.writeReg(writeRegisterWB),
.reset(resetGral),
.writeData(resultWB),
.readData1(readData1),
.readData2(readData2)
);
ALU alu(
.op_code(aluControlEX),
.operand1(aluOperand1),
.operand2(aluOperand2),
.result(aluOut),
.zero(aluZero),
.overflow(aluOverflow)
);
SigExt sigext(
.in(instructionID[15:0]),
.zeroEx(zeroExtendFlag),
.out(sigExtOut)
);
Adder branchPCAdd(
.a(pcNextID),
.b(sigExtOut[7:0]),
.sum(pcBranchAddr)
);
Adder PCAdd(
.a(pcFE),
.b(8'b1),
.sum(pcNext)
);
IF_ID if_id(
.clock(clock),
.reset(resetGral),
.debugEnable(debugEnable),
.debugReset(debugReset),
.notEnable(stallID),
.instruction(instruction),
.pcNext(pcNext),
.instructionOut(instructionID),
.pcNextOut(pcNextID),
.clear(pcSrc)
);
EX_MEM ex_mem(
.clock(clock),
.reset(resetGral),
.debugEnable(debugEnable),
.debugReset(debugReset),
.writeRegister(writeRegister),
.writeData(writeDataEX),
.aluOut(aluOut),
.regWrite(regWriteEX),
.memToReg(memToRegEX),
.memWrite(memWriteEX),
.memReadWidth(memReadWidthEX),
.eop(eopFlagEX),
.writeRegisterOut(writeRegisterMEM),
.writeDataOut(writeDataMEM),
.aluOutOut(aluOutMEM),
.regWriteOut(regWriteMEM),
.memToRegOut(memToRegMEM),
.memWriteOut(memWriteMEM),
.memReadWidthOut(memReadWidthMEM),
.eopOut(eopFlagMEM)
);
ID_EX id_ex(
.clock(clock),
.reset(resetGral),
.debugEnable(debugEnable),
.debugReset(debugReset),
.syncClr(flushEX),
.rs(instructionID[25:21]),
.rt(instructionID[20:16]),
.rd(instructionID[15:11]),
.sa(instructionID[10:6]),
.aluOperation(aluControl),
.sigExt(sigExtOut),
.readData1(readData1),
.readData2(readData2),
.aluSrc(aluSrc),
.aluShiftImm(aluShiftImm),
.regDst(regDst),
.loadImm(loadImm),
.memWrite(memWrite),
.memToReg(memToReg),
.memReadWidth(memReadWidth),
.regWrite(regWrite),
.eop(eopFlag),
.aluOperationOut(aluControlEX),
.sigExtOut(sigExtEX),
.readData1Out(readData1EX),
.readData2Out(readData2EX),
.aluSrcOut(aluSrcEX),
.aluShiftImmOut(aluShiftImmEX),
.memWriteOut(memWriteEX),
.memToRegOut(memToRegEX),
.memReadWidthOut(memReadWidthEX),
.rsOut(rsEX),
.rtOut(rtEX),
.rdOut(rdEX),
.saOut(saEX),
.regDstOut(regDstEX),
.loadImmOut(loadImmEX),
.regWriteOut(regWriteEX),
.eopOut(eopFlagEX)
);
MemoryLoadMask mask (
.dataIn(readDataMemory),
.maskLength(memReadWidthMEM),
.dataOut(readDataMemoryMasked)
);
MEM_WB mem_wb(
.clock(clock),
.reset(resetGral),
.debugEnable(debugEnable),
.debugReset(debugReset),
.writeRegister(writeRegisterMEM),
.aluOut(aluOutMEM),
.memoryOut(readDataMemoryMasked),
.regWrite(regWriteMEM),
.memToReg(memToRegMEM),
.eop(eopFlagMEM),
.writeRegisterOut(writeRegisterWB),
.aluOutOut(aluOutWB),
.memoryOutOut(memoryOutWB),
.regWriteOut(regWriteWB),
.memToRegOut(memToRegWB),
.eopOut(eopFlagWB)
);
FE fetch(
.clock(clock),
.reset(resetGral),
.debugEnable(debugEnable),
.debugReset(debugReset),
.notEnable(stallFE),
.pc(PC),
.pcOut(pcFE)
);
HazardsUnit hazards (
.branchID(branch),
.rsID(instructionID[25:21]),
.rtID(instructionID[20:16]),
.rsEX(rsEX),
.rtEX(rtEX),
.writeRegEX(writeRegister),
.writeRegMEM(writeRegisterMEM),
.writeRegWB(writeRegisterWB),
.memToRegEX(memToRegEX),
.memToRegMEM(memToRegMEM),
.regWriteEX(regWriteEX),
.regWriteMEM(regWriteMEM),
.regWriteWB(regWriteWB),
.stallFE(stallFE),
.stallID(stallID),
.forwardAID(forwardAID),
.forwardBID(forwardBID),
.flushEX(flushEX),
.forwardAEX(forwardAEX),
.forwardBEX(forwardBEX)
);
DebugUnit debugUnit(
.clock(clock),
.reset(resetGral),
.endOfProgram(eopFlagWB),
.uartFifoDataIn(uartFifoDataIn),
.uartDataAvailable(uartDataAvailable),
.FE_pc(pcFE),
.IF_ID_instruction(instructionID),
.IF_ID_pcNext(pcNextID),
.ID_EX_aluOperation(aluControlEX),
.ID_EX_sigExt(sigExtEX),
.ID_EX_readData1(readData1EX),
.ID_EX_readData2(readData2EX),
.ID_EX_aluSrc(aluSrcEX),
.ID_EX_aluShiftImm(aluShiftImmEX),
.ID_EX_memWrite(memWriteEX),
.ID_EX_memToReg(memToRegEX),
.ID_EX_memReadWidth(memReadWidthEX),
.ID_EX_rs(rsEX),
.ID_EX_rt(rtEX),
.ID_EX_rd(rdEX),
.ID_EX_sa(saEX),
.ID_EX_regDst(regDstEX),
.ID_EX_loadImm(loadImmEX),
.ID_EX_regWrite(regWriteEX),
.EX_MEM_writeRegister(writeRegisterMEM),
.EX_MEM_writeData(writeDataMEM),
.EX_MEM_aluOut(aluOutMEM),
.EX_MEM_regWrite(regWriteMEM),
.EX_MEM_memToReg(memToRegMEM),
.EX_MEM_memWrite(memWriteMEM),
.EX_MEM_memReadWidth(memReadWidthMEM),
.MEM_WB_writeRegister(writeRegisterWB),
.MEM_WB_aluOut(aluOutWB),
.MEM_WB_memoryOut(memoryOutWB),
.MEM_WB_regWrite(regWriteWB),
.MEM_WB_memToReg(memToRegWB),
.dataToUartOutFifo(dataToUartOutFifo),
.readFifoFlag(uartReadFlag),
.writeFifoFlag(uartWriteFlag),
.pipeEnable(debugEnable),
.pipeReset (debugReset),
.ledStep(ledStep),
.ledCont(ledCont),
.ledIdle(ledIdle),
.ledSend(ledSend)
);
UART_uart uartMod(
.clock(clock),
.uart_rx(uartRxPin),
.uart_reset(resetGral),
.readFlag(uartReadFlag),
.writeFlag(uartWriteFlag),
.dataToSend(dataToUartOutFifo),
.receivedData(uartFifoDataIn),
.dataAvailable(uartDataAvailable),
.uart_tx(uartTxPin)
);
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
`include "config.vh"
module bch_encode #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* First cycle */
input ce, /* Accept input word/cycle output word */
input [BITS-1:0] data_in, /* Input data */
output [BITS-1:0] data_out, /* Encoded output */
output first, /* First output cycle */
output reg last = 0, /* Last output cycle */
output data_bits, /* Current cycle is data */
output ecc_bits, /* Current cycle is ecc */
output ready /* Can accept data */
);
`include "bch.vh"
`include "bch_encode.vh"
localparam M = `BCH_M(P);
localparam TCQ = 1;
localparam ENC = encoder_poly(0);
/* Data cycles required */
localparam DATA_CYCLES = PIPELINE_STAGES + (`BCH_DATA_BITS(P) + BITS - 1) / BITS;
/* ECC cycles required */
localparam ECC_CYCLES = (`BCH_ECC_BITS(P) + BITS - 1) / BITS;
/* Total output cycles required (always at least 2) */
localparam CODE_CYCLES = DATA_CYCLES + ECC_CYCLES;
localparam signed SHIFT = BITS - `BCH_ECC_BITS(P);
localparam SWITCH = lfsr_count(M, DATA_CYCLES - 2);
localparam DONE = lfsr_count(M, CODE_CYCLES - 3);
localparam REM = `BCH_DATA_BITS(P) % BITS;
localparam RUNT = BITS - REM;
if (PIPELINE_STAGES > 1)
encode_only_supports_1_pipeline_stage u_eos1ps();
reg [`BCH_ECC_BITS(P)-1:0] lfsr = 0;
wire [`BCH_ECC_BITS(P)-1:0] lfsr_first;
wire [`BCH_ECC_BITS(P)-1:0] lfsr_next;
wire [BITS-1:0] data_in_pipelined;
wire [BITS-1:0] output_mask;
wire [BITS-1:0] shifted_in;
wire [M-1:0] count;
reg load_lfsr = 0;
reg busy = 0;
reg start_last = 0;
if (CODE_CYCLES < 3)
assign count = 0;
else
lfsr_counter #(M) u_counter(
.clk(clk),
.reset(ce && start),
.ce(ce && busy),
.count(count)
);
/*
* Shift input so that pad the start with 0's, and finish on the final
* bit.
*/
generate
if (REM) begin
reg [RUNT-1:0] runt = 0;
assign shifted_in = (data_in << RUNT) | (start ? 0 : runt);
always @(posedge clk)
if (ce)
runt <= #TCQ data_in << REM;
end else
assign shifted_in = data_in;
endgenerate
wire [BITS-1:0] lfsr_input;
assign lfsr_input = SHIFT > 0 ? (lfsr << SHIFT) : (lfsr >> -SHIFT);
if (`CONFIG_PIPELINE_LFSR) begin
wire [`BCH_ECC_BITS(P)-1:0] in_enc;
wire [`BCH_ECC_BITS(P)-1:0] in_enc_pipelined;
wire [`BCH_ECC_BITS(P)-1:0] lfsr_enc;
lfsr_term #(`BCH_ECC_BITS(P), ENC, BITS) u_in_terms(
.in(shifted_in),
.out(in_enc)
);
pipeline_ce #(PIPELINE_STAGES > 0) u_enc_pipeline [`BCH_ECC_BITS(P)-1:0] (
.clk(clk),
.ce(ce),
.i(in_enc),
.o(in_enc_pipelined)
);
/*
* The below in equivalent to one instance with the vector input being
* data & lfsr. However, with this arrangement, its easy to pipeline
* the incoming data to reduce the number of gates/inputs between lfsr
* stages.
*/
lfsr_term #(`BCH_ECC_BITS(P), ENC, BITS) u_lfsr_terms(
.in(lfsr_input),
.out(lfsr_enc)
);
assign lfsr_first = in_enc_pipelined;
assign lfsr_next = (lfsr << BITS) ^ lfsr_enc ^ in_enc_pipelined;
end else begin
wire [BITS-1:0] shifted_in_pipelined;
pipeline_ce #(PIPELINE_STAGES > 0) u_enc_pipeline [BITS-1:0] (
.clk(clk),
.ce(ce),
.i(shifted_in),
.o(shifted_in_pipelined)
);
function [`BCH_ECC_BITS(P)-1:0] lfsr_rep;
input [`BCH_ECC_BITS(P)-1:0] prev;
input [BITS-1:0] in;
reg [`BCH_ECC_BITS(P)-1:0] ret;
integer i;
begin
ret = prev;
for (i = BITS - 1; i >= 0; i = i - 1)
ret = {ret[`BCH_ECC_BITS(P)-2:0], 1'b0} ^
({`BCH_ECC_BITS(P){ret[`BCH_ECC_BITS(P)-1] ^ in[i]}} & ENC);
lfsr_rep = ret;
end
endfunction
assign lfsr_first = lfsr_rep(0, shifted_in_pipelined);
assign lfsr_next = lfsr_rep(lfsr, shifted_in_pipelined);
end
pipeline_ce #(PIPELINE_STAGES) u_data_pipeline [BITS-1:0] (
.clk(clk),
.ce(ce),
.i(data_in),
.o(data_in_pipelined)
);
assign first = PIPELINE_STAGES ? start_last : (start && !busy);
assign data_bits = (start && !PIPELINE_STAGES) || load_lfsr;
assign ecc_bits = (busy || last) && !data_bits;
if (REM)
assign output_mask = last ? {{RUNT{1'b1}}, {REM{1'b0}}} : {BITS{1'b1}};
else
assign output_mask = {BITS{1'b1}};
assign data_out = data_bits ? data_in_pipelined : (lfsr_input & output_mask);
assign ready = !busy;
always @(posedge clk) begin
if (ce) begin
start_last <= #TCQ start && !busy;
if (start) begin
last <= #TCQ CODE_CYCLES < 3; /* First cycle is last cycle */
busy <= #TCQ 1;
end else if (count == DONE && busy) begin
last <= #TCQ busy;
busy <= #TCQ !PIPELINE_STAGES;
end else if (last) begin
last <= #TCQ 0;
busy <= #TCQ 0;
end
if (start)
load_lfsr <= #TCQ DATA_CYCLES > 1;
else if (count == SWITCH)
load_lfsr <= #TCQ 1'b0;
if (start)
lfsr <= #TCQ PIPELINE_STAGES ? 0 : lfsr_first;
else if (load_lfsr)
lfsr <= #TCQ lfsr_next;
else if (busy)
lfsr <= #TCQ lfsr << BITS;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_zc706.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the ZC706 Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "xilinx.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_zc706
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "Z706")
(// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
input USER_CLK,
input USER_RESET,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "XILINX";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
reg rRxTlpValid;
reg rRxTlpEndFlag;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
translation_xilinx
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.RX_NP_OK (RX_NP_OK),
.RX_NP_REQ (RX_NP_REQ),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_TX_TUSER (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
.TX_CFG_GNT (TX_CFG_GNT),
.FC_SEL (FC_SEL[`SIG_FC_SEL_W-1:0]),
.CFG_INTERRUPT (CFG_INTERRUPT),
// Inputs
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.M_AXIS_RX_TUSER (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.CFG_BUS_NUMBER (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
.CFG_COMMAND (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
.FC_CPLD (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: mb2cpx_sm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* mb2cpx_sm.v State machine for the MicroBlaze FSL to SPARC CPX interface
*
* $Id: mb2cpx_sm.v,v 1.1 2007/06/30 00:23:39 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module mb2cpx_sm (
// Outputs
cpx_fsl_s_read,
cpx_shift_out,
cpx_spc_data_rdy_cx2,
// Inputs
rclk,
reset_l,
fsl_cpx_s_exists,
fsl_cpx_s_control,
atomic_txn
);
parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+3-1)/`FSL_D_WIDTH)+1);
parameter CPX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
(`PCX_WIDTH+3);
parameter [2:0] CPX_FIRST_COUNT = CPX_GEAR_RATIO - 2;
parameter pCPX_IDLE = 0,
pCPX_SHIFT = 1,
pCPX_AT_WAIT = 2;
parameter CPX_IDLE = 3'b001,
CPX_SHIFT = 3'b010,
CPX_AT_WAIT = 3'b100;
// Outputs
output cpx_fsl_s_read;
output cpx_shift_out;
output cpx_spc_data_rdy_cx2;
// Inputs
input rclk;
input reset_l;
input fsl_cpx_s_exists;
input fsl_cpx_s_control;
input atomic_txn;
// Wire definitions for outputs
reg cpx_fsl_s_read;
reg cpx_shift_out;
wire cpx_spc_data_rdy_cx2;
// State machine to control the shifting of data
reg [2:0] curr_state;
reg [2:0] next_state;
reg [2:0] curr_count;
reg [2:0] next_count;
reg atomic_first;
reg atomic_second;
reg next_atomic_first;
reg next_atomic_second;
reg next_shift_out;
reg atomic_second_d1;
reg atomic_second_d2;
reg cpx_shift_out_d1;
always @ (posedge rclk) begin // Start with a synchronous reset
if (!reset_l) begin
curr_state <= CPX_IDLE;
curr_count <= 3'b000;
atomic_first <= 1'b0;
atomic_second <= 1'b0;
cpx_shift_out <= 1'b0;
end
else begin
curr_state <= next_state;
curr_count <= next_count;
atomic_first <= next_atomic_first;
atomic_second <= next_atomic_second;
cpx_shift_out <= next_shift_out;
end
end
always @(posedge rclk) begin
atomic_second_d1 <= atomic_second;
atomic_second_d2 <= atomic_second_d1;
cpx_shift_out_d1 <= cpx_shift_out;
end
always @ (curr_state or fsl_cpx_s_exists or fsl_cpx_s_control or
curr_count or atomic_txn or atomic_first or atomic_second) begin
case (1)
curr_state[pCPX_IDLE] : begin
next_atomic_second = 1'b0;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
next_atomic_first = atomic_txn;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b0;
end
end
curr_state[pCPX_SHIFT] : begin
if (fsl_cpx_s_exists && curr_count == 3'b000) begin
if (atomic_first) begin
next_state = CPX_AT_WAIT;
next_count = curr_count;
next_atomic_first = 1'b0;
next_atomic_second = atomic_first;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = CPX_FIRST_COUNT;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
end
else if (fsl_cpx_s_exists) begin
next_state = CPX_SHIFT;
next_count = curr_count - 3'b001;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b0;
end
else begin
next_state = CPX_SHIFT;
next_count = curr_count;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
end
curr_state[pCPX_AT_WAIT] : begin
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b0;
end
end
default : begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
endcase
end
// Outputs of the state machine
assign cpx_spc_data_rdy_cx2 = (!atomic_second && !atomic_second_d2 &&
cpx_shift_out_d1) ||
(atomic_second_d1 && cpx_shift_out);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : fpga.v
// Description : Prototype FPGA setup for SPI device
// Author : Philip Tracton
// Created On : Fri Jul 8 20:51:04 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Jul 8 20:51:04 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module fpga (/*AUTOARG*/
// Outputs
sck_o, ncs_o, mosi_o,
// Inputs
clk_i, rst_i, miso_i, int1, int2
) ;
input wire clk_i;
input wire rst_i;
output wire sck_o;
output wire ncs_o;
output wire mosi_o;
input wire miso_i;
input wire int1;
input wire int2;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clear_spif; // From controller of spi_controller.v
wire clear_wcol; // From controller of spi_controller.v
wire clk; // From sys_con of system_controller.v
wire inta_o; // From spi of simple_spi_top_modified.v
wire nrst; // From sys_con of system_controller.v
wire [7:0] rfdout; // From spi of simple_spi_top_modified.v
wire rfre; // From controller of spi_controller.v
wire rst; // From sys_con of system_controller.v
wire [7:0] spcr; // From controller of spi_controller.v
wire [7:0] sper; // From controller of spi_controller.v
wire [7:0] spsr; // From spi of simple_spi_top_modified.v
wire [15:0] temperature; // From controller of spi_controller.v
wire [7:0] wfdin; // From controller of spi_controller.v
wire wfwe; // From controller of spi_controller.v
wire wr_spsr; // From controller of spi_controller.v
// End of automatics
//
// System Controller
//
// This module handles all clocks and synchronizes reset from the IO pins
//
system_controller sys_con(/*AUTOINST*/
// Outputs
.clk (clk),
.rst (rst),
.nrst (nrst),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i));
//
// SPI Controller
//
// This is a state machine to control interfacing with the ADXL362
//
spi_controller controller(/*AUTOINST*/
// Outputs
.wfdin (wfdin[7:0]),
.spcr (spcr[7:0]),
.sper (sper[7:0]),
.wfwe (wfwe),
.rfre (rfre),
.wr_spsr (wr_spsr),
.clear_spif (clear_spif),
.clear_wcol (clear_wcol),
.ncs_o (ncs_o),
.temperature (temperature[15:0]),
// Inputs
.clk (clk),
.rst (rst),
.rfdout (rfdout[7:0]),
.inta_o (inta_o),
.spsr (spsr[7:0]));
//
// SPI
//
// This is the SPI module that handles communication with ADXL362
//
simple_spi_top_modified spi(/*AUTOINST*/
// Outputs
.spsr (spsr[7:0]),
.inta_o (inta_o),
.rfdout (rfdout[7:0]),
.sck_o (sck_o),
.mosi_o (mosi_o),
// Inputs
.clk_i (clk_i),
.nrst (nrst),
.spcr (spcr[7:0]),
.sper (sper[7:0]),
.wfwe (wfwe),
.rfre (rfre),
.wr_spsr (wr_spsr),
.clear_spif (clear_spif),
.clear_wcol (clear_wcol),
.wfdin (wfdin[7:0]),
.miso_i (miso_i));
endmodule // fpga
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module write_axi_9bit(
input clock_recovery,
input clock_50,
input reset_n,
input [8:0] data_rec,
output reg [8:0] data_stand
);
always@(posedge clock_50 or negedge reset_n )
begin
if(!reset_n)
begin
data_stand <= 9'd0;
end
else
begin
if(clock_recovery)
data_stand <= data_rec;
else
data_stand <= data_stand;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:26:08 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, enab_cont_iter, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_fmtted_Result_31_, FPSENCOS_enab_d_ff4_Xn,
FPSENCOS_enab_d_ff4_Yn, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_shift_region_flag_out_0_, FPSENCOS_d_ff1_operation_out,
FPSENCOS_enab_d_ff5_data_out, FPSENCOS_enab_RB3,
FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_barrel_shifter_load,
FPMULT_FSM_final_result_load, FPMULT_FSM_adder_round_norm_load,
FPMULT_FSM_load_second_step, FPMULT_FSM_exp_operation_load_result,
FPMULT_FSM_first_phase_load, FPMULT_FSM_add_overflow_flag,
FPADDSUB_N60, FPADDSUB_N59, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_left_right_SHT2, FPADDSUB__6_net_,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_Shift_reg_FLAGS_7_5, FPADDSUB_Shift_reg_FLAGS_7_6,
FPADDSUB_enable_Pipeline_input, FPSENCOS_ITER_CONT_net8049972,
FPSENCOS_ITER_CONT_N5, FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8049918, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8049810,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720,
FPSENCOS_d_ff5_data_out_net8049936,
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648,
FPADDSUB_SGF_STAGE_DMP_net8049702,
FPADDSUB_NRM_STAGE_Raw_mant_net8049684, FPSENCOS_reg_Z0_net8049936,
FPSENCOS_reg_val_muxZ_2stage_net8049936,
FPSENCOS_reg_shift_y_net8049936, FPSENCOS_d_ff4_Xn_net8049936,
FPSENCOS_d_ff4_Yn_net8049936, FPSENCOS_d_ff4_Zn_net8049936,
FPADDSUB_INPUT_STAGE_OPERANDY_net8049648,
FPADDSUB_EXP_STAGE_DMP_net8049702, FPADDSUB_SHT1_STAGE_DMP_net8049702,
FPADDSUB_SHT2_STAGE_DMP_net8049702,
FPADDSUB_SHT2_SHIFT_DATA_net8049684,
FPMULT_Exp_module_exp_result_m_net8049882,
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864,
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846,
FPMULT_Adder_M_Add_Subt_Result_net8049828,
FPMULT_Operands_load_reg_XMRegister_net8049900,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648, n30,
n106, n107, n810, n813, n816, n819, n824, n829, n830, n834, n842,
n843, n844, n846, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n859, n860, n861, n862, n863, n864, n865, n874, n875,
DP_OP_26J308_123_9022_n18, DP_OP_26J308_123_9022_n17,
DP_OP_26J308_123_9022_n16, DP_OP_26J308_123_9022_n15,
DP_OP_26J308_123_9022_n14, DP_OP_26J308_123_9022_n8,
DP_OP_26J308_123_9022_n7, DP_OP_26J308_123_9022_n6,
DP_OP_26J308_123_9022_n5, DP_OP_26J308_123_9022_n4,
DP_OP_26J308_123_9022_n3, DP_OP_26J308_123_9022_n2,
DP_OP_26J308_123_9022_n1, DP_OP_234J308_126_8543_n22,
DP_OP_234J308_126_8543_n21, DP_OP_234J308_126_8543_n20,
DP_OP_234J308_126_8543_n19, DP_OP_234J308_126_8543_n18,
DP_OP_234J308_126_8543_n17, DP_OP_234J308_126_8543_n16,
DP_OP_234J308_126_8543_n15, DP_OP_234J308_126_8543_n9,
DP_OP_234J308_126_8543_n8, DP_OP_234J308_126_8543_n7,
DP_OP_234J308_126_8543_n6, DP_OP_234J308_126_8543_n5,
DP_OP_234J308_126_8543_n4, DP_OP_234J308_126_8543_n3,
DP_OP_234J308_126_8543_n2, DP_OP_234J308_126_8543_n1, intadd_1036_CI,
intadd_1036_n3, intadd_1036_n2, intadd_1036_n1, intadd_1037_CI,
intadd_1037_n3, intadd_1037_n2, intadd_1037_n1, intadd_1038_CI,
intadd_1038_SUM_2_, intadd_1038_SUM_1_, intadd_1038_SUM_0_,
intadd_1038_n3, intadd_1038_n2, intadd_1038_n1,
DP_OP_453J308_122_681_n2086, DP_OP_453J308_122_681_n2084,
DP_OP_453J308_122_681_n2066, DP_OP_453J308_122_681_n1786,
DP_OP_453J308_122_681_n1780, DP_OP_453J308_122_681_n1706,
DP_OP_453J308_122_681_n1705, DP_OP_453J308_122_681_n1589,
DP_OP_453J308_122_681_n1588, DP_OP_453J308_122_681_n1587,
DP_OP_453J308_122_681_n1586, DP_OP_453J308_122_681_n1585,
DP_OP_453J308_122_681_n795, DP_OP_453J308_122_681_n794,
DP_OP_453J308_122_681_n793, DP_OP_453J308_122_681_n792,
DP_OP_453J308_122_681_n791, DP_OP_453J308_122_681_n790,
DP_OP_453J308_122_681_n789, DP_OP_453J308_122_681_n788,
DP_OP_453J308_122_681_n787, DP_OP_453J308_122_681_n786,
DP_OP_453J308_122_681_n785, DP_OP_453J308_122_681_n784,
DP_OP_453J308_122_681_n783, DP_OP_453J308_122_681_n782,
DP_OP_453J308_122_681_n777, DP_OP_453J308_122_681_n775,
DP_OP_453J308_122_681_n774, DP_OP_453J308_122_681_n542,
DP_OP_453J308_122_681_n541, DP_OP_453J308_122_681_n540,
DP_OP_453J308_122_681_n538, DP_OP_453J308_122_681_n537,
DP_OP_453J308_122_681_n536, DP_OP_453J308_122_681_n535,
DP_OP_453J308_122_681_n534, DP_OP_453J308_122_681_n533,
DP_OP_453J308_122_681_n532, DP_OP_453J308_122_681_n531,
DP_OP_453J308_122_681_n529, DP_OP_453J308_122_681_n525,
DP_OP_453J308_122_681_n524, DP_OP_453J308_122_681_n523,
DP_OP_453J308_122_681_n522, DP_OP_453J308_122_681_n521,
DP_OP_453J308_122_681_n520, DP_OP_453J308_122_681_n519,
DP_OP_453J308_122_681_n518, DP_OP_453J308_122_681_n517,
DP_OP_453J308_122_681_n516, DP_OP_453J308_122_681_n512,
DP_OP_453J308_122_681_n511, DP_OP_453J308_122_681_n510,
DP_OP_453J308_122_681_n508, DP_OP_453J308_122_681_n507,
DP_OP_453J308_122_681_n506, DP_OP_453J308_122_681_n505,
DP_OP_453J308_122_681_n504, DP_OP_453J308_122_681_n503,
DP_OP_453J308_122_681_n502, DP_OP_453J308_122_681_n501,
DP_OP_453J308_122_681_n500, DP_OP_453J308_122_681_n499,
DP_OP_453J308_122_681_n495, DP_OP_453J308_122_681_n493,
DP_OP_453J308_122_681_n492, DP_OP_453J308_122_681_n491,
DP_OP_453J308_122_681_n490, DP_OP_453J308_122_681_n489,
DP_OP_453J308_122_681_n488, DP_OP_453J308_122_681_n487,
DP_OP_453J308_122_681_n482, DP_OP_453J308_122_681_n478,
DP_OP_453J308_122_681_n477, DP_OP_453J308_122_681_n476,
DP_OP_453J308_122_681_n475, DP_OP_453J308_122_681_n474,
DP_OP_453J308_122_681_n473, DP_OP_453J308_122_681_n471,
DP_OP_453J308_122_681_n470, DP_OP_453J308_122_681_n469,
DP_OP_453J308_122_681_n468, DP_OP_453J308_122_681_n462,
DP_OP_453J308_122_681_n461, DP_OP_453J308_122_681_n459,
DP_OP_453J308_122_681_n458, DP_OP_453J308_122_681_n457,
DP_OP_453J308_122_681_n455, DP_OP_453J308_122_681_n449,
DP_OP_453J308_122_681_n448, DP_OP_453J308_122_681_n445,
DP_OP_453J308_122_681_n444, DP_OP_453J308_122_681_n442,
DP_OP_453J308_122_681_n435, DP_OP_453J308_122_681_n431,
DP_OP_453J308_122_681_n430, DP_OP_453J308_122_681_n429,
DP_OP_453J308_122_681_n428, DP_OP_453J308_122_681_n427,
DP_OP_453J308_122_681_n426, DP_OP_453J308_122_681_n425,
DP_OP_453J308_122_681_n424, DP_OP_453J308_122_681_n423,
DP_OP_453J308_122_681_n422, DP_OP_453J308_122_681_n421,
DP_OP_453J308_122_681_n420, DP_OP_453J308_122_681_n419,
DP_OP_453J308_122_681_n418, DP_OP_453J308_122_681_n417,
DP_OP_453J308_122_681_n416, DP_OP_453J308_122_681_n415,
DP_OP_453J308_122_681_n414, DP_OP_453J308_122_681_n413,
DP_OP_453J308_122_681_n412, DP_OP_453J308_122_681_n411,
DP_OP_453J308_122_681_n409, DP_OP_453J308_122_681_n408,
DP_OP_453J308_122_681_n407, DP_OP_453J308_122_681_n406,
DP_OP_453J308_122_681_n405, DP_OP_453J308_122_681_n403,
DP_OP_453J308_122_681_n402, DP_OP_453J308_122_681_n401,
DP_OP_453J308_122_681_n400, DP_OP_453J308_122_681_n399,
DP_OP_453J308_122_681_n398, DP_OP_453J308_122_681_n397,
DP_OP_453J308_122_681_n396, DP_OP_453J308_122_681_n394,
DP_OP_453J308_122_681_n393, DP_OP_453J308_122_681_n392,
DP_OP_453J308_122_681_n391, DP_OP_453J308_122_681_n390,
DP_OP_453J308_122_681_n389, DP_OP_453J308_122_681_n388,
DP_OP_453J308_122_681_n387, DP_OP_453J308_122_681_n386,
DP_OP_453J308_122_681_n385, DP_OP_453J308_122_681_n384,
DP_OP_453J308_122_681_n383, DP_OP_453J308_122_681_n382,
DP_OP_453J308_122_681_n380, DP_OP_453J308_122_681_n379,
DP_OP_453J308_122_681_n378, DP_OP_453J308_122_681_n377,
DP_OP_453J308_122_681_n376, DP_OP_453J308_122_681_n375,
DP_OP_453J308_122_681_n374, DP_OP_453J308_122_681_n373,
DP_OP_453J308_122_681_n372, DP_OP_453J308_122_681_n371,
DP_OP_453J308_122_681_n370, DP_OP_453J308_122_681_n369,
DP_OP_453J308_122_681_n368, DP_OP_453J308_122_681_n367,
DP_OP_453J308_122_681_n365, DP_OP_453J308_122_681_n364,
DP_OP_453J308_122_681_n363, DP_OP_453J308_122_681_n362,
DP_OP_453J308_122_681_n361, DP_OP_453J308_122_681_n360,
DP_OP_453J308_122_681_n359, DP_OP_453J308_122_681_n358,
DP_OP_453J308_122_681_n357, DP_OP_453J308_122_681_n356,
DP_OP_453J308_122_681_n355, DP_OP_453J308_122_681_n354,
DP_OP_453J308_122_681_n353, DP_OP_453J308_122_681_n352,
DP_OP_453J308_122_681_n351, DP_OP_453J308_122_681_n350,
DP_OP_453J308_122_681_n349, DP_OP_453J308_122_681_n348,
DP_OP_453J308_122_681_n347, DP_OP_453J308_122_681_n346,
DP_OP_453J308_122_681_n345, DP_OP_453J308_122_681_n344,
DP_OP_453J308_122_681_n343, DP_OP_453J308_122_681_n342,
DP_OP_453J308_122_681_n341, DP_OP_453J308_122_681_n340,
DP_OP_453J308_122_681_n339, DP_OP_453J308_122_681_n338,
DP_OP_453J308_122_681_n337, DP_OP_453J308_122_681_n336,
DP_OP_453J308_122_681_n335, DP_OP_453J308_122_681_n334,
DP_OP_453J308_122_681_n333, DP_OP_453J308_122_681_n332,
DP_OP_453J308_122_681_n331, DP_OP_453J308_122_681_n330,
DP_OP_453J308_122_681_n329, DP_OP_453J308_122_681_n328,
DP_OP_453J308_122_681_n327, DP_OP_453J308_122_681_n326,
DP_OP_453J308_122_681_n325, DP_OP_453J308_122_681_n324,
DP_OP_453J308_122_681_n323, DP_OP_453J308_122_681_n322,
DP_OP_453J308_122_681_n321, DP_OP_453J308_122_681_n320,
DP_OP_453J308_122_681_n319, DP_OP_453J308_122_681_n318,
DP_OP_453J308_122_681_n317, DP_OP_453J308_122_681_n316,
DP_OP_453J308_122_681_n315, DP_OP_453J308_122_681_n314,
DP_OP_453J308_122_681_n312, DP_OP_453J308_122_681_n311,
DP_OP_453J308_122_681_n310, DP_OP_453J308_122_681_n309,
DP_OP_453J308_122_681_n308, DP_OP_453J308_122_681_n307,
DP_OP_453J308_122_681_n306, DP_OP_453J308_122_681_n305,
DP_OP_453J308_122_681_n304, DP_OP_453J308_122_681_n303,
DP_OP_453J308_122_681_n302, DP_OP_453J308_122_681_n301,
DP_OP_453J308_122_681_n300, DP_OP_453J308_122_681_n299,
DP_OP_453J308_122_681_n298, DP_OP_453J308_122_681_n297,
DP_OP_453J308_122_681_n296, DP_OP_453J308_122_681_n295,
DP_OP_453J308_122_681_n294, DP_OP_453J308_122_681_n293,
DP_OP_453J308_122_681_n292, DP_OP_453J308_122_681_n291,
DP_OP_453J308_122_681_n290, DP_OP_453J308_122_681_n289,
DP_OP_453J308_122_681_n288, DP_OP_453J308_122_681_n287,
DP_OP_453J308_122_681_n286, DP_OP_453J308_122_681_n285,
DP_OP_453J308_122_681_n284, DP_OP_453J308_122_681_n283,
DP_OP_453J308_122_681_n282, DP_OP_453J308_122_681_n281,
DP_OP_453J308_122_681_n280, DP_OP_453J308_122_681_n279,
DP_OP_453J308_122_681_n278, DP_OP_453J308_122_681_n277,
DP_OP_453J308_122_681_n276, DP_OP_453J308_122_681_n275,
DP_OP_453J308_122_681_n274, DP_OP_453J308_122_681_n273,
DP_OP_453J308_122_681_n272, DP_OP_453J308_122_681_n271,
DP_OP_453J308_122_681_n270, DP_OP_453J308_122_681_n269,
DP_OP_453J308_122_681_n268, DP_OP_453J308_122_681_n267,
DP_OP_453J308_122_681_n266, DP_OP_453J308_122_681_n265,
DP_OP_453J308_122_681_n264, DP_OP_453J308_122_681_n263,
DP_OP_453J308_122_681_n262, DP_OP_453J308_122_681_n261,
DP_OP_453J308_122_681_n260, DP_OP_453J308_122_681_n259,
DP_OP_453J308_122_681_n258, DP_OP_453J308_122_681_n257,
DP_OP_453J308_122_681_n256, DP_OP_453J308_122_681_n255,
DP_OP_453J308_122_681_n254, DP_OP_453J308_122_681_n253,
DP_OP_453J308_122_681_n252, DP_OP_453J308_122_681_n251,
DP_OP_453J308_122_681_n250, DP_OP_453J308_122_681_n249,
DP_OP_453J308_122_681_n248, DP_OP_453J308_122_681_n247,
DP_OP_453J308_122_681_n246, DP_OP_453J308_122_681_n245,
DP_OP_453J308_122_681_n244, DP_OP_453J308_122_681_n243,
DP_OP_453J308_122_681_n242, DP_OP_453J308_122_681_n241,
DP_OP_453J308_122_681_n240, DP_OP_453J308_122_681_n239,
DP_OP_453J308_122_681_n238, DP_OP_453J308_122_681_n237,
DP_OP_453J308_122_681_n236, DP_OP_453J308_122_681_n235,
DP_OP_453J308_122_681_n234, DP_OP_453J308_122_681_n233,
DP_OP_453J308_122_681_n232, DP_OP_453J308_122_681_n231,
DP_OP_453J308_122_681_n230, DP_OP_453J308_122_681_n229,
DP_OP_453J308_122_681_n228, n910, n911, n912, n913, n914, n915, n916,
n917, n918, n919, n920, n921, n922, n923, n924, n925, n926, n927,
n928, n929, n930, n931, n932, n933, n934, n935, n936, n937, n938,
n939, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949,
n950, n951, n952, n953, n954, n955, n956, n957, n958, n959, n960,
n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n980, n981, n982, n983,
n984, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996,
n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006,
n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016,
n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026,
n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036,
n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046,
n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056,
n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066,
n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076,
n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086,
n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096,
n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106,
n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116,
n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126,
n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136,
n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146,
n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156,
n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166,
n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176,
n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186,
n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196,
n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206,
n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216,
n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226,
n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236,
n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246,
n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256,
n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266,
n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276,
n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286,
n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296,
n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306,
n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316,
n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326,
n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336,
n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346,
n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356,
n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366,
n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376,
n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386,
n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396,
n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406,
n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416,
n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426,
n3427, n3428, n3429, n3431, n3432, n3433, n3435, n3436, n3437, n3438,
n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448,
n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458,
n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468,
n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478,
n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488,
n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498,
n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508,
n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518,
n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528,
n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538,
n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548,
n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558,
n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568,
n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578,
n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588,
n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598,
n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608,
n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618,
n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628,
n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638,
n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648,
n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658,
n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668,
n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678,
n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688,
n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698,
n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708,
n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718,
n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728,
n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738,
n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748,
n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758,
n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768,
n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778,
n3779, n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788,
n3789, n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798,
n3799, n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808,
n3809, n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818,
n3819, n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828,
n3829, n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838,
n3839, n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848,
n3849, n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858,
n3859, n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868,
n3869, n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878,
n3879, n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888,
n3889, n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898,
n3899, n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908,
n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918,
n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928,
n3929, n3930, n3931, n3932, n3933, n3935, n3936, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [22:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:1] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [50:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [28:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:23] FPMULT_Sgf_operation_Result;
wire [23:14] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(FPSENCOS_ITER_CONT_net8049972),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n846), .ENCLK(FPMULT_FS_Module_net8049918), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n875), .ENCLK(FPADDSUB_inst_ShiftRegister_net8049810),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8049936), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8049936),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8049936), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8049936), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8049936), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8049936), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8049936), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8049702), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8049882), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .TE(
1'b0) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n3907), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n3915), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n3906), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n3906), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n3906), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n3907), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n3908), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n3909), .Q(
dataB[28]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n3906), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n3907), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n3939), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3864), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3864), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3838), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3838), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3838), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3838), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3839), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3887), .Q(
FPSENCOS_d_ff1_shift_region_flag_out_0_), .QN(n1089) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3907), .QN(n928) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3906), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3907), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3908), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3909), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3906), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3907), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3908), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3909), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n3689), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3906), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3907), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3908), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3907), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3907), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3916), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3916), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3916), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3916), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n824), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n824), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n824), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n824), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3910), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3907), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3916), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3916), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3898), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3898), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3898), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3911), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3901), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3914), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3914), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3886), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3912), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3885), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3897), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3902), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3901), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3885), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3904), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3899), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3897), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3902), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3901), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3900), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3902), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3902), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3902), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3901), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3901), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3901), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3901), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3900), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3900), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3853), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n1028) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3856), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3868), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3854), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3859), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3854), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3850), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3868), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3863), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3853), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3869), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3853), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3853), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3858), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3853), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3869), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3853), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3853), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3869), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3839), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3862), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3842), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3859), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3870), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3867), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3862), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3899), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3899), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3899), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3898), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3859), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3898), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n2808), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3898), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n2808), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3840), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3846), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3897), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3897), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3897), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3843), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3848), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3897), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3897), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3897), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3913), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3914), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3904), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3916), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n824), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3885), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n2809), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3844), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n824), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3898), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n824), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3916), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n2808), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3898), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3844), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3842), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3898), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3896), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3898), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3896), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3898), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n2888), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3847), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3846), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3913), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3915), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n824), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3916), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3889), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3914), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3915), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3843), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3848), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n2808), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3914), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3913), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3893), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3892), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n2809), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3845), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3892), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3893), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3893), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3895), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3894), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3894), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n2810), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n2888), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3894), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3894), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3894), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3894), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3843), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3848), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3844), .QN(n932) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3914), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3914), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3892), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n824), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n824), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3916), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3913), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3913), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3914), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3845), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n2888), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3914), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3914), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3914), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3895), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3892), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n2810), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n2888), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3895), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3895), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3892), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n2809), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3845), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3895), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3892), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3895), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3892), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3893), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3844), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3847), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3891), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3889), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3887), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3890), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3889), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3868), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3888), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3891), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3890), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3887), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3887), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3857), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3862), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3891), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3889), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3888), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3890), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3890), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3890), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702),
.RN(n3860), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3891), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3887), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3891), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3891), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3888), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3890), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3891), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8049936), .RN(n3891), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3888), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3889), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3857), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n958), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3853), .QN(n931) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3856), .QN(n926) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3868), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3868), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3863), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3850), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8049720), .RN(n3850), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3887), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3888), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3891), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3890), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3891), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3887), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3888), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3887), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3888), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3891), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3891), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3886), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3912), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3885), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3886), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3912), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3885), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3886), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3912), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3885), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3886), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3912), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3885), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3894), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3856), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3892), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3894), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3895), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3892), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3886), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3912), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3886), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3912), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3856), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8049936), .RN(n3891), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3890), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3912), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8049936), .RN(n3885), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3911), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3911), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8049936), .RN(n3911), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8049936), .RN(n3911), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3911), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3854), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3857), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3854), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3857), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3854), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3853), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3859), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3862), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3859), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3862), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3856), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3856), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3850), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3862), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3850), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3866), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3862), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3852), .Q(FPADDSUB_N60) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]) );
DFFRXLTS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8049918),
.RN(n3886), .Q(FPMULT_FS_Module_state_reg[0]), .QN(n927) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3883), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3883), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3883), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3875), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3883), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3873), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3874), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3875), .Q(
FPMULT_Op_MY[23]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[15]), .QN(n1086) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[12]), .QN(n923) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[18]), .QN(n1055) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[17]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3876), .Q(
FPMULT_Op_MX[16]), .QN(n1030) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3871), .Q(
FPMULT_Op_MX[15]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3872), .Q(
FPMULT_Op_MX[14]), .QN(n1067) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[13]), .QN(n1044) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(
FPMULT_Op_MX[3]), .QN(n1033) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n3936), .RN(n3877), .QN(n1071) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .QN(n934) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .QN(n935) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .QN(n936) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .QN(n921) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .QN(n937) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .QN(n938) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n920), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3886), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8049882), .RN(n3874), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3874), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n3961), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3871), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n3959), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3872), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n3957), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3874), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n3955), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3871), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n3953), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3872), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n3951), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3874), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n3949), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n3947), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n3943), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3873), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3872), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3871), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8049648), .RN(
n3883), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n3931), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3850), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n3932), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3863), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n3930), .CK(
FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3859), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n976), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3868), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3866), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3867), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3866), .Q(
FPADDSUB_OP_FLAG_SHT2) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n107), .ENCLK(n3936), .TE(1'b0) );
CMPR32X2TS DP_OP_26J308_123_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n911), .C(DP_OP_26J308_123_9022_n18), .CO(DP_OP_26J308_123_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J308_123_9022_U8 ( .A(DP_OP_26J308_123_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J308_123_9022_n8), .CO(
DP_OP_26J308_123_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J308_123_9022_U7 ( .A(DP_OP_26J308_123_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J308_123_9022_n7), .CO(
DP_OP_26J308_123_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J308_123_9022_U6 ( .A(DP_OP_26J308_123_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J308_123_9022_n6), .CO(
DP_OP_26J308_123_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_234J308_126_8543_U2 ( .A(n2714), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J308_126_8543_n2), .CO(DP_OP_234J308_126_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_1038_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n3809), .C(
intadd_1038_CI), .CO(intadd_1038_n3), .S(intadd_1038_SUM_0_) );
CMPR32X2TS intadd_1038_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n3808), .C(
intadd_1038_n3), .CO(intadd_1038_n2), .S(intadd_1038_SUM_1_) );
CMPR32X2TS intadd_1038_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n3823), .C(
intadd_1038_n2), .CO(intadd_1038_n1), .S(intadd_1038_SUM_2_) );
DFFSX2TS R_13 ( .D(n3829), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .SN(n2808), .Q(n3924)
);
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8049936), .RN(n3915), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3860), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n3824) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff2_X[28]), .QN(n3822) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n3821) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3856), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n3819) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3840), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n3817) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3863), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n3816) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3847), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n3815) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3856), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n3814) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3841), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n3813) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n2809), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n3812) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3846), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n3810) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3843), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n3805) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3844), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n3804) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n976), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n3803) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3862), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n3802) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3861), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n3801) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n2810), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n3800) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3848), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n3799) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3845), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n3798) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n2888), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n3797) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3851), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n3796) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3868), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n3795) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3869), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n3794) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3859), .Q(
FPADDSUB_DMP_SFG[22]), .QN(n3791) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n976), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n3788) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3864), .Q(
FPADDSUB_Data_array_SWR[50]), .QN(n3787) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n2809), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n3786) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3785) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n976), .Q(
FPADDSUB_DMP_SFG[20]), .QN(n3784) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n3939), .CK(
clk), .RN(n3838), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n3783) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(FPMULT_FS_Module_net8049918),
.RN(n3874), .Q(FPMULT_FSM_selector_C), .QN(n3782) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3846), .QN(n3781)
);
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n3838), .Q(ready_add_subt), .QN(n3780) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3854), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n3777) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3861), .Q(
FPADDSUB_intDY_EWSW[28]), .QN(n3775) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3774) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3855), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n3773) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3848), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n3772) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3846), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n3771) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3853), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n3769) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n3767) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3844), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n3766) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3853), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n3765) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3846), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n3764) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3865), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n3763) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3848), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n3760) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3849), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3759) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3861), .Q(
FPADDSUB_DMP_SFG[18]), .QN(n3758) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DMP_SFG[17]), .QN(n3757) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n3756) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DMP_SFG[16]), .QN(n3754) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3859), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n3753) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3752) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3859), .Q(
FPADDSUB_DMP_SFG[14]), .QN(n3751) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n3888), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n3749) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3852), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n3748) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3866), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n3746) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3857), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n3745) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_SFG[12]), .QN(n3742) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n3741) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3854), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n3740) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3850), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n3739) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n3738) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3851), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n3737) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SFG[10]), .QN(n3736) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DMP_SFG[9]), .QN(n3735) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3853), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n3733) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DMP_SFG[8]), .QN(n3732) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3840), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n3731) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DMP_SFG[6]), .QN(n3730) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3861), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3729) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_DMP_SFG[4]), .QN(n3728) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3865), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n3727) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3868), .Q(
FPADDSUB_DMP_SFG[2]), .QN(n3726) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3869), .Q(
FPADDSUB_DMP_SFG[0]), .QN(n3725) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3850), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n3724) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3859), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n3722) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3862), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n3721) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3870), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n3720) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3843), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n3719) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n3718) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DMP_SFG[21]), .QN(n3717) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8049918),
.RN(n3886), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n3715) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DMP_SFG[19]), .QN(n3714) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[24]), .QN(n3713) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3857), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n3711) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3842), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n3710) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n3709) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3857), .QN(n3708)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n3707) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3854), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n3706) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3845), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n3705) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n2809), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n3703) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3858), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n3702) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3851), .Q(
FPADDSUB_DMP_SFG[15]), .QN(n3701) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3863), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n3699) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DMP_SFG[13]), .QN(n3698) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3870), .Q(
FPADDSUB_DMP_SFG[11]), .QN(n3696) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3856), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n3695) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3857), .Q(
FPADDSUB_DMP_SFG[7]), .QN(n3694) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DMP_SFG[5]), .QN(n3693) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3864), .Q(
FPADDSUB_DMP_SFG[3]), .QN(n3692) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3855), .Q(
FPADDSUB_DMP_SFG[1]), .QN(n3691) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n3909), .Q(NaN_flag)
);
CMPR32X2TS DP_OP_234J308_126_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n2714), .C(DP_OP_234J308_126_8543_n22), .CO(DP_OP_234J308_126_8543_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J308_126_8543_U9 ( .A(DP_OP_234J308_126_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J308_126_8543_n9), .CO(
DP_OP_234J308_126_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J308_126_8543_U8 ( .A(DP_OP_234J308_126_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J308_126_8543_n8), .CO(
DP_OP_234J308_126_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J308_126_8543_U7 ( .A(DP_OP_234J308_126_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J308_126_8543_n7), .CO(
DP_OP_234J308_126_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J308_126_8543_U6 ( .A(DP_OP_234J308_126_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J308_126_8543_n6), .CO(
DP_OP_234J308_126_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J308_126_8543_U5 ( .A(DP_OP_234J308_126_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J308_126_8543_n5), .CO(
DP_OP_234J308_126_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J308_126_8543_U4 ( .A(DP_OP_234J308_126_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J308_126_8543_n4), .CO(
DP_OP_234J308_126_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_26J308_123_9022_U5 ( .A(DP_OP_26J308_123_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J308_123_9022_n5), .CO(
DP_OP_26J308_123_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J308_123_9022_U4 ( .A(n911), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J308_123_9022_n4), .CO(
DP_OP_26J308_123_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J308_123_9022_U3 ( .A(n911), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J308_123_9022_n3), .CO(
DP_OP_26J308_123_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_234J308_126_8543_U3 ( .A(DP_OP_234J308_126_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J308_126_8543_n3), .CO(
DP_OP_234J308_126_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_26J308_123_9022_U2 ( .A(n911), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J308_123_9022_n2), .CO(
DP_OP_26J308_123_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR42X2TS DP_OP_453J308_122_681_U316 ( .A(DP_OP_453J308_122_681_n405), .B(
DP_OP_453J308_122_681_n541), .C(DP_OP_453J308_122_681_n406), .D(
DP_OP_453J308_122_681_n431), .ICI(DP_OP_453J308_122_681_n793), .S(
DP_OP_453J308_122_681_n403), .ICO(DP_OP_453J308_122_681_n401), .CO(
DP_OP_453J308_122_681_n402) );
CMPR42X2TS DP_OP_453J308_122_681_U296 ( .A(DP_OP_453J308_122_681_n361), .B(
DP_OP_453J308_122_681_n424), .C(DP_OP_453J308_122_681_n786), .D(
DP_OP_453J308_122_681_n353), .ICI(DP_OP_453J308_122_681_n357), .S(
DP_OP_453J308_122_681_n350), .ICO(DP_OP_453J308_122_681_n348), .CO(
DP_OP_453J308_122_681_n349) );
CMPR42X2TS DP_OP_453J308_122_681_U292 ( .A(DP_OP_453J308_122_681_n352), .B(
DP_OP_453J308_122_681_n423), .C(DP_OP_453J308_122_681_n785), .D(
DP_OP_453J308_122_681_n342), .ICI(DP_OP_453J308_122_681_n348), .S(
DP_OP_453J308_122_681_n339), .ICO(DP_OP_453J308_122_681_n337), .CO(
DP_OP_453J308_122_681_n338) );
CMPR42X2TS DP_OP_453J308_122_681_U288 ( .A(DP_OP_453J308_122_681_n341), .B(
DP_OP_453J308_122_681_n337), .C(DP_OP_453J308_122_681_n331), .D(
DP_OP_453J308_122_681_n422), .ICI(DP_OP_453J308_122_681_n784), .S(
DP_OP_453J308_122_681_n328), .ICO(DP_OP_453J308_122_681_n326), .CO(
DP_OP_453J308_122_681_n327) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[19]), .QN(n1049) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[22]), .QN(DP_OP_453J308_122_681_n1780) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[20]), .QN(DP_OP_453J308_122_681_n1786) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[21]) );
DFFSXLTS R_11 ( .D(n3831), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3879), .Q(n3925),
.QN(n3807) );
DFFSX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n3685), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3878), .QN(
FPMULT_Op_MX[19]) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n3697), .CK(
FPSENCOS_ITER_CONT_net8049972), .RN(n3898), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n3697) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3838), .Q(busy), .QN(
n3826) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8049972), .RN(n3886), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n3689) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8049972), .RN(n3887), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n3690) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(FPMULT_FS_Module_net8049918),
.RN(n3875), .Q(FPMULT_FSM_selector_B[1]), .QN(n3744) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3869), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n3789) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(clk), .RN(n3907), .Q(
FPSENCOS_cont_var_out[0]), .QN(n3700) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8049918),
.RN(n3885), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n3704) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3847), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n3712) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n3820) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3863), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n3762) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n2809), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n3770) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n976), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n3761) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3856), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n3768) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3848), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n3811) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3854), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n3792) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3847), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n3793) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3855), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n3818) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3862), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n3734) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(
FPMULT_Op_MX[0]), .QN(n1038) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[20]) );
DFFSX1TS R_19_IP ( .D(n1036), .CK(clk), .SN(n3910), .QN(n3919) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3841), .QN(n3837)
);
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n3936), .RN(n3877), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(clk), .RN(n3907), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3864), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3849), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n3888), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3862), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3865), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3866), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3842), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3863), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3860), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3841), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3840), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3870), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3853), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3850), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3864), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3859), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3852), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3863), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(clk), .RN(n3838), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3866), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3851), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3849), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3856), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n2810), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3853), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3848), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3845), .Q(
FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3857), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n3890), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3854), .Q(
result_add_subt[7]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3864), .Q(
result_add_subt[6]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3855), .Q(
result_add_subt[3]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3852), .Q(
result_add_subt[1]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3849), .Q(
result_add_subt[0]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3864), .Q(
result_add_subt[31]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3868), .Q(
result_add_subt[9]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3865), .Q(
result_add_subt[12]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3866), .Q(
result_add_subt[10]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3857), .Q(
result_add_subt[8]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3844), .Q(
result_add_subt[11]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3845), .Q(
result_add_subt[14]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3843), .Q(
result_add_subt[13]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3844), .Q(
result_add_subt[5]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n2888), .Q(
result_add_subt[15]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3847), .Q(
result_add_subt[4]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3848), .Q(
result_add_subt[17]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n2810), .Q(
result_add_subt[20]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n2809), .Q(
result_add_subt[18]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3843), .Q(
result_add_subt[16]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n2888), .Q(
result_add_subt[2]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3846), .Q(
result_add_subt[21]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3860), .Q(
result_add_subt[19]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3850), .Q(
result_add_subt[22]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3850), .Q(
result_add_subt[30]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[28]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[27]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[26]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[24]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8049648), .RN(n3867), .Q(
result_add_subt[23]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n3945), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .QN(
n1087) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3847), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3860), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3854), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3838), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n3942), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n3944), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n3946), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n3948), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n3950), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n3952), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n3954), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3876), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n3956), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3875), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n3958), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n3960), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3876), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(n960), .CK(clk), .RN(n3910), .Q(
operation_reg[0]) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n3938), .CK(
FPSENCOS_reg_Z0_net8049936), .RN(n3905), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n3910),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n3962), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3883), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3842), .Q(FPADDSUB_N59) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8049810), .RN(n3838), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n3891), .Q(
dataA[29]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8049972), .RN(n3898), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n3743) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3868), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n3747) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3864), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n3755) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3858), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n3776) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3901), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3903), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n3907), .Q(
dataB[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3885), .Q(
FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3912), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3886), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3885), .Q(
FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3912), .Q(
FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3877), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3877), .Q(
FPMULT_Add_result[23]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n3906), .Q(
dataA[28]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3853), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n3893), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3858), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3846), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3849), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3842), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3845), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3849), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3870), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3839), .Q(
FPADDSUB_intDX_EWSW[30]) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n3688), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3879), .Q(
DP_OP_453J308_122_681_n2084), .QN(FPMULT_Op_MY[21]) );
DFFSX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n3686), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3878), .Q(
DP_OP_453J308_122_681_n1706), .QN(FPMULT_Op_MX[9]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n3838), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n3912), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n1088) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n3907), .Q(
dataB[24]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n3906), .Q(
dataB[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n3940), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n920) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8049918),
.RN(n3886), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n1070) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n3933), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8049684), .RN(n3866), .Q(
FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n3941), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3873), .Q(
FPMULT_Sgf_normalized_result[1]), .QN(n933) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n3908), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MX[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3861), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3877), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n3910), .Q(
dataA[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n2810), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3842), .Q(
FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3876), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3875), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3885), .Q(
FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3886), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3912), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3885), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3886), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3912), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3884), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3912), .Q(
FPMULT_P_Sgf[46]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n3915), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n3906), .Q(
dataA[24]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n3963), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8049846), .RN(n3874), .QN(
n1035) );
DFFSX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n3684), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3880), .Q(
DP_OP_453J308_122_681_n1705), .QN(n913) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .QN(n925)
);
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(n914),
.QN(n1034) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
n916), .QN(n1051) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(n918),
.QN(n1031) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(n915),
.QN(n1032) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n3927), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3880), .Q(
DP_OP_453J308_122_681_n2086), .QN(n917) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[16]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[14]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MY[1]), .QN(n1056) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MX[8]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3878), .Q(
FPMULT_Op_MX[6]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(
FPMULT_Op_MX[4]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(
FPMULT_Op_MX[2]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n3910), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_1 ( .D(n3835), .CK(clk), .SN(n3908), .Q(n3921) );
DFFSX1TS R_3 ( .D(n3833), .CK(clk), .SN(n3909), .Q(n3917) );
DFFSX1TS R_4 ( .D(n3832), .CK(clk), .SN(n3907), .Q(n3918) );
DFFSXLTS R_12 ( .D(n3830), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648),
.SN(n3857), .Q(n3929) );
DFFSX1TS R_18 ( .D(n3828), .CK(clk), .SN(n3906), .Q(n3920) );
DFFSXLTS R_20 ( .D(n3827), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .SN(n3906), .Q(n3923)
);
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3904), .Q(FPSENCOS_d_ff2_X[23]), .QN(n3779) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8049936), .RN(n3902), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n3778) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3875), .Q(
FPMULT_Op_MY[22]), .QN(DP_OP_453J308_122_681_n2066) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n3928), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3880), .QN(
FPMULT_Op_MY[18]) );
DFFSX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n3683), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3879), .QN(
FPMULT_Op_MX[10]) );
DFFSX1TS R_2 ( .D(n3834), .CK(clk), .SN(n3909), .Q(n3922) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(FPMULT_FS_Module_net8049918),
.RN(n3875), .Q(FPMULT_FSM_selector_B[0]), .QN(n3750) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3852), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n3809) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n3823) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8049702), .RN(n3849), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n3808) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8049648), .RN(n3840), .QN(n3836)
);
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n3935), .CK(n3936),
.RN(n3877), .Q(underflow_flag_mult), .QN(n3825) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3843), .Q(
FPADDSUB_Data_array_SWR[45]), .QN(n3790) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3867), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n3716) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8049828), .RN(n3877), .Q(
FPMULT_FSM_add_overflow_flag), .QN(n3806) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8049864), .RN(n3912), .Q(
FPMULT_P_Sgf[47]), .QN(n3723) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n3893), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
CMPR42X1TS DP_OP_453J308_122_681_U290 ( .A(DP_OP_453J308_122_681_n346), .B(
DP_OP_453J308_122_681_n336), .C(DP_OP_453J308_122_681_n493), .D(
DP_OP_453J308_122_681_n506), .ICI(DP_OP_453J308_122_681_n519), .S(
DP_OP_453J308_122_681_n334), .ICO(DP_OP_453J308_122_681_n332), .CO(
DP_OP_453J308_122_681_n333) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MY[2]), .QN(n1064) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MY[6]), .QN(n1076) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n3926), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3879), .Q(
DP_OP_453J308_122_681_n1589), .QN(FPMULT_Op_MY[7]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MY[3]), .QN(n1048) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[11]), .QN(DP_OP_453J308_122_681_n1585) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[10]), .QN(DP_OP_453J308_122_681_n1586) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MY[5]), .QN(n1075) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n3687), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .SN(n3879), .Q(
DP_OP_453J308_122_681_n1588), .QN(FPMULT_Op_MY[8]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3879), .Q(
FPMULT_Op_MY[4]), .QN(n1068) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3880), .Q(
FPMULT_Op_MY[9]), .QN(DP_OP_453J308_122_681_n1587) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8049900), .RN(n3877), .Q(
n912), .QN(n924) );
CMPR42X1TS DP_OP_453J308_122_681_U314 ( .A(DP_OP_453J308_122_681_n540), .B(
DP_OP_453J308_122_681_n400), .C(DP_OP_453J308_122_681_n401), .D(
DP_OP_453J308_122_681_n792), .ICI(DP_OP_453J308_122_681_n430), .S(
DP_OP_453J308_122_681_n398), .ICO(DP_OP_453J308_122_681_n396), .CO(
DP_OP_453J308_122_681_n397) );
CMPR42X1TS DP_OP_453J308_122_681_U307 ( .A(DP_OP_453J308_122_681_n382), .B(
DP_OP_453J308_122_681_n511), .C(DP_OP_453J308_122_681_n524), .D(
DP_OP_453J308_122_681_n386), .ICI(DP_OP_453J308_122_681_n537), .S(
DP_OP_453J308_122_681_n380), .ICO(DP_OP_453J308_122_681_n378), .CO(
DP_OP_453J308_122_681_n379) );
CMPR42X1TS DP_OP_453J308_122_681_U309 ( .A(DP_OP_453J308_122_681_n538), .B(
DP_OP_453J308_122_681_n790), .C(DP_OP_453J308_122_681_n388), .D(
DP_OP_453J308_122_681_n428), .ICI(DP_OP_453J308_122_681_n389), .S(
DP_OP_453J308_122_681_n385), .ICO(DP_OP_453J308_122_681_n383), .CO(
DP_OP_453J308_122_681_n384) );
CMPR42X1TS DP_OP_453J308_122_681_U306 ( .A(DP_OP_453J308_122_681_n387), .B(
DP_OP_453J308_122_681_n380), .C(DP_OP_453J308_122_681_n427), .D(
DP_OP_453J308_122_681_n789), .ICI(DP_OP_453J308_122_681_n383), .S(
DP_OP_453J308_122_681_n377), .ICO(DP_OP_453J308_122_681_n375), .CO(
DP_OP_453J308_122_681_n376) );
CMPR42X1TS DP_OP_453J308_122_681_U304 ( .A(DP_OP_453J308_122_681_n510), .B(
DP_OP_453J308_122_681_n374), .C(DP_OP_453J308_122_681_n378), .D(
DP_OP_453J308_122_681_n523), .ICI(DP_OP_453J308_122_681_n536), .S(
DP_OP_453J308_122_681_n372), .ICO(DP_OP_453J308_122_681_n370), .CO(
DP_OP_453J308_122_681_n371) );
CMPR42X1TS DP_OP_453J308_122_681_U298 ( .A(DP_OP_453J308_122_681_n469), .B(
DP_OP_453J308_122_681_n482), .C(DP_OP_453J308_122_681_n495), .D(
DP_OP_453J308_122_681_n365), .ICI(DP_OP_453J308_122_681_n521), .S(
DP_OP_453J308_122_681_n356), .ICO(DP_OP_453J308_122_681_n354), .CO(
DP_OP_453J308_122_681_n355) );
CMPR42X1TS DP_OP_453J308_122_681_U294 ( .A(DP_OP_453J308_122_681_n468), .B(
DP_OP_453J308_122_681_n435), .C(DP_OP_453J308_122_681_n347), .D(
DP_OP_453J308_122_681_n354), .ICI(DP_OP_453J308_122_681_n507), .S(
DP_OP_453J308_122_681_n345), .ICO(DP_OP_453J308_122_681_n343), .CO(
DP_OP_453J308_122_681_n344) );
CMPR42X1TS DP_OP_453J308_122_681_U293 ( .A(DP_OP_453J308_122_681_n520), .B(
DP_OP_453J308_122_681_n533), .C(DP_OP_453J308_122_681_n355), .D(
DP_OP_453J308_122_681_n351), .ICI(DP_OP_453J308_122_681_n345), .S(
DP_OP_453J308_122_681_n342), .ICO(DP_OP_453J308_122_681_n340), .CO(
DP_OP_453J308_122_681_n341) );
CMPR42X1TS DP_OP_453J308_122_681_U286 ( .A(DP_OP_453J308_122_681_n335), .B(
DP_OP_453J308_122_681_n505), .C(DP_OP_453J308_122_681_n325), .D(
DP_OP_453J308_122_681_n492), .ICI(DP_OP_453J308_122_681_n332), .S(
DP_OP_453J308_122_681_n323), .ICO(DP_OP_453J308_122_681_n321), .CO(
DP_OP_453J308_122_681_n322) );
CMPR42X1TS DP_OP_453J308_122_681_U285 ( .A(DP_OP_453J308_122_681_n531), .B(
DP_OP_453J308_122_681_n518), .C(DP_OP_453J308_122_681_n333), .D(
DP_OP_453J308_122_681_n329), .ICI(DP_OP_453J308_122_681_n323), .S(
DP_OP_453J308_122_681_n320), .ICO(DP_OP_453J308_122_681_n318), .CO(
DP_OP_453J308_122_681_n319) );
CMPR42X1TS DP_OP_453J308_122_681_U282 ( .A(DP_OP_453J308_122_681_n314), .B(
DP_OP_453J308_122_681_n324), .C(DP_OP_453J308_122_681_n478), .D(
DP_OP_453J308_122_681_n491), .ICI(DP_OP_453J308_122_681_n321), .S(
DP_OP_453J308_122_681_n312), .ICO(DP_OP_453J308_122_681_n310), .CO(
DP_OP_453J308_122_681_n311) );
CMPR42X1TS DP_OP_453J308_122_681_U280 ( .A(DP_OP_453J308_122_681_n420), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[14]), .C(DP_OP_453J308_122_681_n319),
.D(DP_OP_453J308_122_681_n309), .ICI(DP_OP_453J308_122_681_n315), .S(
DP_OP_453J308_122_681_n306), .ICO(DP_OP_453J308_122_681_n304), .CO(
DP_OP_453J308_122_681_n305) );
CMPR42X1TS DP_OP_453J308_122_681_U276 ( .A(DP_OP_453J308_122_681_n419), .B(
DP_OP_453J308_122_681_n782), .C(DP_OP_453J308_122_681_n308), .D(
DP_OP_453J308_122_681_n304), .ICI(DP_OP_453J308_122_681_n298), .S(
DP_OP_453J308_122_681_n295), .ICO(DP_OP_453J308_122_681_n293), .CO(
DP_OP_453J308_122_681_n294) );
CMPR42X1TS DP_OP_453J308_122_681_U272 ( .A(DP_OP_453J308_122_681_n297), .B(
DP_OP_453J308_122_681_n418), .C(n1041), .D(DP_OP_453J308_122_681_n293),
.ICI(DP_OP_453J308_122_681_n287), .S(DP_OP_453J308_122_681_n284),
.ICO(DP_OP_453J308_122_681_n282), .CO(DP_OP_453J308_122_681_n283) );
CMPR42X1TS DP_OP_453J308_122_681_U269 ( .A(
FPMULT_Sgf_operation_EVEN1_Q_left[17]), .B(DP_OP_453J308_122_681_n278),
.C(DP_OP_453J308_122_681_n417), .D(DP_OP_453J308_122_681_n286), .ICI(
DP_OP_453J308_122_681_n282), .S(DP_OP_453J308_122_681_n275), .ICO(
DP_OP_453J308_122_681_n273), .CO(DP_OP_453J308_122_681_n274) );
CMPR42X1TS DP_OP_453J308_122_681_U263 ( .A(DP_OP_453J308_122_681_n261), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[19]), .C(DP_OP_453J308_122_681_n415),
.D(DP_OP_453J308_122_681_n268), .ICI(DP_OP_453J308_122_681_n264), .S(
DP_OP_453J308_122_681_n258), .ICO(DP_OP_453J308_122_681_n256), .CO(
DP_OP_453J308_122_681_n257) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3868), .Q(
FPADDSUB_ADD_OVRFLW_NRM2), .QN(n911) );
CMPR42X1TS DP_OP_453J308_122_681_U253 ( .A(DP_OP_453J308_122_681_n455), .B(
DP_OP_453J308_122_681_n442), .C(DP_OP_453J308_122_681_n234), .D(n2239),
.ICI(DP_OP_453J308_122_681_n231), .S(DP_OP_453J308_122_681_n230),
.ICO(DP_OP_453J308_122_681_n228), .CO(DP_OP_453J308_122_681_n229) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n3881), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8049684), .RN(n3869), .Q(
FPADDSUB_left_right_SHT2), .QN(n919) );
CMPR32X2TS intadd_1037_U4 ( .A(n3743), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1037_CI), .CO(intadd_1037_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1036_U4 ( .A(n3743), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1036_CI), .CO(intadd_1036_n3), .S(FPSENCOS_sh_exp_x[1]) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8049702), .RN(n3867), .Q(n910), .QN(n3882)
);
CMPR32X2TS intadd_1037_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n3689), .C(
intadd_1037_n3), .CO(intadd_1037_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS intadd_1036_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n3689), .C(
intadd_1036_n3), .CO(intadd_1036_n2), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS intadd_1037_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n3690), .C(
intadd_1037_n2), .CO(intadd_1037_n1), .S(FPSENCOS_sh_exp_y[3]) );
CMPR32X2TS intadd_1036_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n3690), .C(
intadd_1036_n2), .CO(intadd_1036_n1), .S(FPSENCOS_sh_exp_x[3]) );
BUFX3TS U1399 ( .A(n2885), .Y(n3626) );
AOI222X4TS U1400 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(FPADDSUB_DMP_SFG[22]), .B1(n3425),
.C0(FPADDSUB_DmP_mant_SFG_SWR[24]), .C1(n3425), .Y(n3431) );
AOI211X2TS U1401 ( .A0(FPADDSUB_Data_array_SWR[41]), .A1(n2815), .B0(n2848),
.C0(n2847), .Y(n2919) );
NAND2X4TS U1402 ( .A(n2099), .B(n2583), .Y(n2611) );
AOI211X2TS U1403 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n2815), .B0(n2848),
.C0(n2825), .Y(n2869) );
NOR2X1TS U1404 ( .A(n2097), .B(n2584), .Y(n2615) );
NAND2X1TS U1405 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .B(n2594), .Y(
n2236) );
AOI222X4TS U1406 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(FPADDSUB_DMP_SFG[20]), .B1(n3211),
.C0(FPADDSUB_DmP_mant_SFG_SWR[22]), .C1(n3211), .Y(n3420) );
INVX2TS U1407 ( .A(n3141), .Y(n3056) );
NAND2X1TS U1408 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n3183), .Y(n3182)
);
AND2X2TS U1409 ( .A(n3068), .B(n3067), .Y(n3069) );
CLKXOR2X2TS U1410 ( .A(n1428), .B(n1427), .Y(n2099) );
NAND2X1TS U1411 ( .A(n3010), .B(operation[2]), .Y(n3646) );
XOR2X1TS U1412 ( .A(n1453), .B(n1452), .Y(n2097) );
NOR2X1TS U1413 ( .A(n2096), .B(n2105), .Y(n2619) );
NAND2X1TS U1414 ( .A(n2096), .B(n2105), .Y(n2620) );
NAND2X1TS U1415 ( .A(n1094), .B(n1426), .Y(n1427) );
NOR2X1TS U1416 ( .A(n1100), .B(n2202), .Y(n2594) );
BUFX3TS U1417 ( .A(n2681), .Y(n3582) );
NOR2X1TS U1418 ( .A(n3010), .B(n3481), .Y(n3532) );
AOI21X1TS U1419 ( .A0(n2086), .A1(n1411), .B0(n1410), .Y(n1428) );
AOI222X4TS U1420 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(FPADDSUB_DMP_SFG[18]), .B1(n3061),
.C0(FPADDSUB_DmP_mant_SFG_SWR[20]), .C1(n3061), .Y(n3413) );
NAND2X1TS U1421 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n3186), .Y(n3185)
);
NOR3X1TS U1422 ( .A(FPSENCOS_cont_var_out[1]), .B(n3010), .C(n3700), .Y(
n2681) );
OAI21X1TS U1423 ( .A0(n1446), .A1(n1449), .B0(n1450), .Y(n1410) );
NAND2X1TS U1424 ( .A(n2076), .B(n2585), .Y(n2624) );
NOR2X1TS U1425 ( .A(n1046), .B(n2206), .Y(n2599) );
INVX4TS U1426 ( .A(n960), .Y(n3010) );
NOR2X1TS U1427 ( .A(n2073), .B(n2587), .Y(n2629) );
NAND2X1TS U1428 ( .A(n2074), .B(n2586), .Y(n2626) );
XOR2X1TS U1429 ( .A(n1463), .B(n1462), .Y(n2076) );
NAND2X1TS U1430 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .B(n2185), .Y(
n2206) );
NAND2X1TS U1431 ( .A(n2078), .B(n1409), .Y(n1445) );
AOI222X4TS U1432 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(FPADDSUB_DMP_SFG[16]), .B1(n3051),
.C0(FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n3051), .Y(n3408) );
NAND2X1TS U1433 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n3189), .Y(n3188)
);
AOI21X1TS U1434 ( .A0(n2080), .A1(n1409), .B0(n1408), .Y(n1446) );
OAI22X1TS U1435 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(n3754), .B0(n3050),
.B1(n3049), .Y(n3409) );
INVX2TS U1436 ( .A(n959), .Y(n960) );
NOR2X1TS U1437 ( .A(n2082), .B(n2087), .Y(n1409) );
AOI22X1TS U1438 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n3752), .B0(n3405), .B1(
n3404), .Y(n3049) );
NAND2X1TS U1439 ( .A(DP_OP_453J308_122_681_n238), .B(
DP_OP_453J308_122_681_n243), .Y(n2081) );
NAND2X1TS U1440 ( .A(DP_OP_453J308_122_681_n237), .B(
DP_OP_453J308_122_681_n233), .Y(n2088) );
NAND2X1TS U1441 ( .A(n2071), .B(n2588), .Y(n2634) );
AOI222X4TS U1442 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n3045),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n3045), .Y(n3403) );
NAND2X1TS U1443 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n3192), .Y(n3191)
);
OAI22X1TS U1444 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(n3751), .B0(n3044),
.B1(n3043), .Y(n3404) );
NAND2X1TS U1445 ( .A(DP_OP_453J308_122_681_n244), .B(
DP_OP_453J308_122_681_n249), .Y(n1473) );
NAND2X1TS U1446 ( .A(n3149), .B(n3737), .Y(n3169) );
AOI22X1TS U1447 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n3741), .B0(n3400), .B1(
n3399), .Y(n3043) );
CMPR32X2TS U1448 ( .A(n2262), .B(n2261), .C(DP_OP_453J308_122_681_n239),
.CO(DP_OP_453J308_122_681_n234), .S(DP_OP_453J308_122_681_n235) );
NOR2X1TS U1449 ( .A(DP_OP_453J308_122_681_n250), .B(
DP_OP_453J308_122_681_n257), .Y(n1470) );
CMPR42X1TS U1450 ( .A(DP_OP_453J308_122_681_n241), .B(
DP_OP_453J308_122_681_n412), .C(DP_OP_453J308_122_681_n774), .D(
DP_OP_453J308_122_681_n775), .ICI(DP_OP_453J308_122_681_n242), .S(
DP_OP_453J308_122_681_n238), .ICO(DP_OP_453J308_122_681_n236), .CO(
DP_OP_453J308_122_681_n237) );
AOI222X4TS U1451 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(FPADDSUB_DMP_SFG[12]), .B1(n3038),
.C0(FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n3038), .Y(n3398) );
NAND2X1TS U1452 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n3195), .Y(n3194)
);
OAI22X1TS U1453 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n3742), .B0(n3037),
.B1(n3036), .Y(n3399) );
NAND2X1TS U1454 ( .A(n3166), .B(n3733), .Y(n3152) );
XNOR2X1TS U1455 ( .A(n2061), .B(n2027), .Y(n2031) );
AOI22X1TS U1456 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n3738), .B0(n3031), .B1(
n3030), .Y(n3036) );
NAND2X1TS U1457 ( .A(DP_OP_453J308_122_681_n266), .B(
DP_OP_453J308_122_681_n274), .Y(n2057) );
NAND2X1TS U1458 ( .A(DP_OP_453J308_122_681_n265), .B(
DP_OP_453J308_122_681_n258), .Y(n2064) );
NAND2X1TS U1459 ( .A(n2009), .B(n2593), .Y(n2654) );
AOI222X4TS U1460 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(FPADDSUB_DMP_SFG[10]), .B1(n3027),
.C0(FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n3027), .Y(n3032) );
CMPR42X1TS U1461 ( .A(DP_OP_453J308_122_681_n777), .B(
DP_OP_453J308_122_681_n414), .C(n1100), .D(DP_OP_453J308_122_681_n253),
.ICI(DP_OP_453J308_122_681_n256), .S(DP_OP_453J308_122_681_n250),
.ICO(DP_OP_453J308_122_681_n248), .CO(DP_OP_453J308_122_681_n249) );
NAND2X1TS U1462 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n3198), .Y(n3197)
);
XOR2X1TS U1463 ( .A(n2012), .B(n2005), .Y(n2009) );
NAND2X1TS U1464 ( .A(n3163), .B(n2778), .Y(n2788) );
CMPR32X2TS U1465 ( .A(n2304), .B(n2303), .C(n2302), .CO(
DP_OP_453J308_122_681_n254), .S(DP_OP_453J308_122_681_n255) );
NOR2X1TS U1466 ( .A(DP_OP_453J308_122_681_n284), .B(
DP_OP_453J308_122_681_n294), .Y(n2026) );
NAND2X1TS U1467 ( .A(DP_OP_453J308_122_681_n284), .B(
DP_OP_453J308_122_681_n294), .Y(n2032) );
AOI222X4TS U1468 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(FPADDSUB_DMP_SFG[8]), .B1(n3014),
.C0(FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n3014), .Y(n3021) );
NAND2X1TS U1469 ( .A(n2001), .B(n2421), .Y(n2658) );
CMPR32X2TS U1470 ( .A(n2319), .B(n2318), .C(n2317), .CO(
DP_OP_453J308_122_681_n262), .S(DP_OP_453J308_122_681_n263) );
OR2X2TS U1471 ( .A(n1992), .B(n1991), .Y(n1039) );
NAND2X1TS U1472 ( .A(n3160), .B(n2777), .Y(n3162) );
NOR2X1TS U1473 ( .A(n2530), .B(n1989), .Y(n2740) );
NAND2X1TS U1474 ( .A(n2530), .B(n1989), .Y(n2741) );
AOI222X4TS U1475 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(FPADDSUB_DMP_SFG[6]), .B1(n2965),
.C0(FPADDSUB_DmP_mant_SFG_SWR[8]), .C1(n2965), .Y(n3006) );
NOR2X1TS U1476 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n2782), .Y(n2777) );
NAND2X1TS U1477 ( .A(n2140), .B(n2139), .Y(n2163) );
NAND2X1TS U1478 ( .A(n2142), .B(n2141), .Y(n2168) );
CMPR32X2TS U1479 ( .A(DP_OP_453J308_122_681_n1780), .B(n2227), .C(n2226),
.CO(n2232), .S(n2197) );
NOR2X1TS U1480 ( .A(n2531), .B(n1988), .Y(n2753) );
NAND2X1TS U1481 ( .A(n3156), .B(n3153), .Y(n2782) );
AOI21X2TS U1482 ( .A0(n2174), .A1(n2138), .B0(n2137), .Y(n2222) );
CMPR32X2TS U1483 ( .A(n2130), .B(n2129), .C(n2128), .CO(n2142), .S(n2139) );
CMPR32X2TS U1484 ( .A(n2149), .B(n2148), .C(n2147), .CO(n2155), .S(n2141) );
CMPR32X2TS U1485 ( .A(n2347), .B(n2346), .C(n2345), .CO(
DP_OP_453J308_122_681_n291), .S(DP_OP_453J308_122_681_n292) );
CMPR32X2TS U1486 ( .A(n2195), .B(n2194), .C(n2193), .CO(n2198), .S(n2154) );
NOR2X1TS U1487 ( .A(n2176), .B(n2180), .Y(n2138) );
AOI222X4TS U1488 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(FPADDSUB_DMP_SFG[4]), .B1(n2935),
.C0(FPADDSUB_DmP_mant_SFG_SWR[6]), .C1(n2935), .Y(n2959) );
NOR2X1TS U1489 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n2781), .Y(n3156) );
CMPR32X2TS U1490 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[21]), .C(n2196),
.CO(n2226), .S(n2194) );
CMPR32X2TS U1491 ( .A(DP_OP_453J308_122_681_n1786), .B(n2153), .C(n2152),
.CO(n2193), .S(n2148) );
CMPR32X2TS U1492 ( .A(n2134), .B(n2133), .C(n2132), .CO(n2147), .S(n2129) );
NAND2X1TS U1493 ( .A(n1372), .B(n1371), .Y(n2175) );
NAND2X1TS U1494 ( .A(n2136), .B(n2135), .Y(n2181) );
BUFX3TS U1495 ( .A(n1436), .Y(n2225) );
NAND2X1TS U1496 ( .A(n3147), .B(n3144), .Y(n2781) );
CMPR32X2TS U1497 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .C(n2131),
.CO(n2149), .S(n2132) );
CMPR32X2TS U1498 ( .A(n2359), .B(n2358), .C(n2357), .CO(
DP_OP_453J308_122_681_n302), .S(DP_OP_453J308_122_681_n303) );
NAND2X1TS U1499 ( .A(n1355), .B(n1354), .Y(n1441) );
CMPR32X2TS U1500 ( .A(n2108), .B(n2107), .C(n2106), .CO(n2136), .S(n1371) );
CMPR32X2TS U1501 ( .A(n2119), .B(n2118), .C(n2117), .CO(n2140), .S(n2135) );
AOI222X4TS U1502 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(FPADDSUB_DMP_SFG[2]), .B1(n2912),
.C0(FPADDSUB_DmP_mant_SFG_SWR[4]), .C1(n2912), .Y(n2929) );
CMPR32X2TS U1503 ( .A(n2116), .B(n2115), .C(n2114), .CO(n2117), .S(n2107) );
CMPR32X2TS U1504 ( .A(n2127), .B(n2126), .C(n2125), .CO(n2128), .S(n2118) );
CMPR32X2TS U1505 ( .A(n1358), .B(n1357), .C(n1356), .CO(n1372), .S(n1355) );
NAND2X1TS U1506 ( .A(n1326), .B(n1325), .Y(n1437) );
CMPR32X2TS U1507 ( .A(n2361), .B(n2505), .C(n2360), .CO(n2357), .S(
DP_OP_453J308_122_681_n314) );
NOR2X1TS U1508 ( .A(n2535), .B(n1982), .Y(n2719) );
NAND2XLTS U1509 ( .A(n1091), .B(n1084), .Y(n1396) );
NOR2X1TS U1510 ( .A(n1819), .B(n1877), .Y(n1849) );
CMPR32X2TS U1511 ( .A(n1370), .B(n1369), .C(n1368), .CO(n2106), .S(n1356) );
CMPR32X2TS U1512 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[17]), .C(n2112),
.CO(n2126), .S(n2116) );
NOR2X1TS U1513 ( .A(n1326), .B(n1325), .Y(n1353) );
CMPR32X2TS U1514 ( .A(n1055), .B(n2121), .C(n2120), .CO(n2130), .S(n2125) );
CMPR32X2TS U1515 ( .A(n2111), .B(n2110), .C(n2109), .CO(n2119), .S(n2114) );
CMPR32X2TS U1516 ( .A(n2367), .B(n2366), .C(n2365), .CO(
DP_OP_453J308_122_681_n324), .S(DP_OP_453J308_122_681_n325) );
CMPR32X2TS U1517 ( .A(n1352), .B(n1351), .C(n1350), .CO(n1354), .S(n1326) );
CMPR32X2TS U1518 ( .A(n1030), .B(n1363), .C(n1362), .CO(n2115), .S(n1370) );
CMPR32X2TS U1519 ( .A(n1361), .B(n1360), .C(n1359), .CO(n2108), .S(n1368) );
CMPR32X2TS U1520 ( .A(n1829), .B(n1828), .C(n1827), .CO(n1836), .S(n1820) );
NAND2X1TS U1521 ( .A(n1302), .B(n1301), .Y(n1334) );
AOI21X2TS U1522 ( .A0(n1911), .A1(n1810), .B0(n1809), .Y(n1887) );
CMPR32X2TS U1523 ( .A(n1343), .B(n1342), .C(n1341), .CO(n1357), .S(n1350) );
CMPR32X2TS U1524 ( .A(n1340), .B(n1339), .C(n1338), .CO(n1358), .S(n1352) );
NAND2X1TS U1525 ( .A(DP_OP_453J308_122_681_n377), .B(
DP_OP_453J308_122_681_n384), .Y(n1894) );
CMPR32X2TS U1526 ( .A(n2372), .B(n2371), .C(n2370), .CO(
DP_OP_453J308_122_681_n335), .S(DP_OP_453J308_122_681_n336) );
NAND2X1TS U1527 ( .A(n1300), .B(n1299), .Y(n1432) );
NAND2X1TS U1528 ( .A(DP_OP_453J308_122_681_n385), .B(
DP_OP_453J308_122_681_n390), .Y(n1907) );
CMPR32X2TS U1529 ( .A(n1324), .B(n1323), .C(n1322), .CO(n1325), .S(n1302) );
NOR2X1TS U1530 ( .A(n1913), .B(n1901), .Y(n1810) );
XNOR2X1TS U1531 ( .A(n2543), .B(n2542), .Y(n2718) );
CMPR32X2TS U1532 ( .A(n1321), .B(n1320), .C(n1319), .CO(n1341), .S(n1324) );
CMPR32X2TS U1533 ( .A(n1312), .B(n1311), .C(n1310), .CO(n1351), .S(n1322) );
CMPR32X2TS U1534 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(n1349),
.CO(n1359), .S(n1338) );
CMPR32X2TS U1535 ( .A(n1346), .B(n1345), .C(n1344), .CO(n1369), .S(n1342) );
CMPR32X2TS U1536 ( .A(n1781), .B(n1780), .C(n1779), .CO(n1816), .S(n1813) );
CMPR32X2TS U1537 ( .A(n1793), .B(n1792), .C(n1791), .CO(n1814), .S(n1811) );
CMPR32X2TS U1538 ( .A(n1796), .B(n1795), .C(n1794), .CO(n1821), .S(n1815) );
NAND2X1TS U1539 ( .A(n1806), .B(n1805), .Y(n1914) );
NOR2X2TS U1540 ( .A(n1300), .B(n1299), .Y(n1431) );
XNOR2X1TS U1541 ( .A(n2549), .B(n2548), .Y(n2955) );
CMPR32X2TS U1542 ( .A(n1778), .B(n1777), .C(n1776), .CO(n1779), .S(n1792) );
CMPR32X2TS U1543 ( .A(n1748), .B(n1747), .C(n1746), .CO(n1808), .S(n1805) );
CMPR32X2TS U1544 ( .A(n1787), .B(n1786), .C(n1785), .CO(n1794), .S(n1780) );
CMPR32X2TS U1545 ( .A(FPMULT_Op_MX[13]), .B(n1067), .C(n1308), .CO(n1339),
.S(n1319) );
CMPR32X2TS U1546 ( .A(n2391), .B(n2390), .C(n2389), .CO(
DP_OP_453J308_122_681_n363), .S(DP_OP_453J308_122_681_n364) );
CMPR32X2TS U1547 ( .A(n1149), .B(n1148), .C(n1147), .CO(n1301), .S(n1300) );
CMPR32X2TS U1548 ( .A(n1315), .B(n1314), .C(n1313), .CO(n1343), .S(n1311) );
CMPR32X2TS U1549 ( .A(n1166), .B(n1165), .C(n1164), .CO(n1299), .S(n1298) );
CMPR32X2TS U1550 ( .A(n1790), .B(n1789), .C(n1788), .CO(n1812), .S(n1807) );
CMPR32X2TS U1551 ( .A(n1800), .B(n1799), .C(n1798), .CO(n1827), .S(n1795) );
CLKXOR2X2TS U1552 ( .A(n1481), .B(n1480), .Y(n2586) );
XOR2X1TS U1553 ( .A(n2554), .B(n2553), .Y(n2717) );
CMPR32X2TS U1554 ( .A(n2401), .B(n2400), .C(n2399), .CO(
DP_OP_453J308_122_681_n373), .S(DP_OP_453J308_122_681_n374) );
CMPR32X2TS U1555 ( .A(n1146), .B(n1145), .C(n1144), .CO(n1323), .S(n1147) );
CMPR32X2TS U1556 ( .A(n1754), .B(n1753), .C(n1752), .CO(n1789), .S(n1746) );
CMPR32X2TS U1557 ( .A(n1134), .B(n1133), .C(n1132), .CO(n1310), .S(n1149) );
CMPR32X2TS U1558 ( .A(n1770), .B(n1769), .C(n1768), .CO(n1791), .S(n1788) );
CMPR32X2TS U1559 ( .A(n1163), .B(n1162), .C(n1161), .CO(n1148), .S(n1164) );
NOR2X1TS U1560 ( .A(DP_OP_453J308_122_681_n398), .B(
DP_OP_453J308_122_681_n402), .Y(n1928) );
NOR2X1TS U1561 ( .A(n1802), .B(n1801), .Y(n1921) );
CMPR32X2TS U1562 ( .A(n1773), .B(n1772), .C(n1771), .CO(n1781), .S(n1776) );
CMPR32X2TS U1563 ( .A(n1044), .B(n1051), .C(n1131), .CO(n1320), .S(n1132) );
CMPR32X2TS U1564 ( .A(n2408), .B(n2407), .C(n2406), .CO(
DP_OP_453J308_122_681_n392), .S(DP_OP_453J308_122_681_n393) );
CMPR32X2TS U1565 ( .A(n1124), .B(n1123), .C(n1122), .CO(n1312), .S(n1145) );
CMPR32X2TS U1566 ( .A(n1152), .B(n1151), .C(n1150), .CO(n1144), .S(n1166) );
CMPR32X2TS U1567 ( .A(n1758), .B(n1757), .C(n1756), .CO(n1769), .S(n1754) );
NAND2X1TS U1568 ( .A(n1290), .B(n1289), .Y(n1478) );
CMPR32X2TS U1569 ( .A(n1731), .B(n1730), .C(n1729), .CO(n1806), .S(n1803) );
NAND2X1TS U1570 ( .A(DP_OP_453J308_122_681_n403), .B(
DP_OP_453J308_122_681_n407), .Y(n1937) );
CMPR32X2TS U1571 ( .A(n1140), .B(n1139), .C(n1138), .CO(n1146), .S(n1162) );
CMPR32X2TS U1572 ( .A(n1763), .B(n1762), .C(n1761), .CO(n1793), .S(n1768) );
CMPR32X2TS U1573 ( .A(n1712), .B(n1711), .C(n1710), .CO(n1804), .S(n1802) );
CMPR32X2TS U1574 ( .A(n1751), .B(n1750), .C(n1749), .CO(n1790), .S(n1752) );
CMPR32X2TS U1575 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1297), .S(n1296) );
NOR2X1TS U1576 ( .A(n996), .B(DP_OP_453J308_122_681_n1588), .Y(n1799) );
NOR2X1TS U1577 ( .A(n1945), .B(n1956), .Y(n1686) );
NOR2X1TS U1578 ( .A(n2251), .B(n2253), .Y(n2259) );
XNOR2X1TS U1579 ( .A(n2495), .B(n1004), .Y(n2480) );
XNOR2X1TS U1580 ( .A(n2512), .B(n999), .Y(n2515) );
CMPR32X2TS U1581 ( .A(n1718), .B(n1717), .C(n1716), .CO(n1730), .S(n1710) );
CMPR32X2TS U1582 ( .A(n2418), .B(n2417), .C(n2416), .CO(
DP_OP_453J308_122_681_n399), .S(DP_OP_453J308_122_681_n400) );
CMPR32X2TS U1583 ( .A(n1182), .B(n1181), .C(n1180), .CO(n1165), .S(n1183) );
CMPR32X2TS U1584 ( .A(n1737), .B(n1736), .C(n1735), .CO(n1747), .S(n1729) );
CMPR32X2TS U1585 ( .A(n1169), .B(n1168), .C(n1167), .CO(n1161), .S(n1185) );
CMPR32X2TS U1586 ( .A(n912), .B(n1130), .C(n1129), .CO(n1133), .S(n1150) );
NOR2X2TS U1587 ( .A(n1682), .B(n1681), .Y(n1956) );
NAND2X1TS U1588 ( .A(n1422), .B(n1421), .Y(n2241) );
OAI21X2TS U1589 ( .A0(n1420), .A1(n2274), .B0(n1419), .Y(n2316) );
XNOR2X1TS U1590 ( .A(n2495), .B(n1001), .Y(n2499) );
CMPR32X2TS U1591 ( .A(n1288), .B(n1287), .C(n1286), .CO(n1291), .S(n1290) );
CMPR32X2TS U1592 ( .A(n1723), .B(n1722), .C(n1721), .CO(n1736), .S(n1717) );
CMPR32X2TS U1593 ( .A(n1533), .B(n1532), .C(n1531), .CO(n1683), .S(n1682) );
CMPR32X2TS U1594 ( .A(n1188), .B(n1187), .C(n1186), .CO(n1180), .S(n1285) );
CMPR32X2TS U1595 ( .A(n1741), .B(n1740), .C(n1739), .CO(n1753), .S(n1737) );
ADDHXLTS U1596 ( .A(n1142), .B(n1141), .CO(n1151), .S(n1168) );
CMPR32X2TS U1597 ( .A(n1715), .B(n1714), .C(n1713), .CO(n1731), .S(n1716) );
NAND2X1TS U1598 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .Y(n2313) );
CMPR32X2TS U1599 ( .A(n1157), .B(n1156), .C(n1155), .CO(n1163), .S(n1181) );
CMPR32X2TS U1600 ( .A(n1734), .B(n1733), .C(n1732), .CO(n1748), .S(n1735) );
CMPR32X2TS U1601 ( .A(n1709), .B(n1708), .C(n1707), .CO(n1801), .S(n1684) );
NOR2X1TS U1602 ( .A(n996), .B(n1076), .Y(n1773) );
XNOR2X1TS U1603 ( .A(n2495), .B(n999), .Y(n2518) );
CMPR32X2TS U1604 ( .A(n1530), .B(n1529), .C(n1528), .CO(n1708), .S(n1531) );
CMPR32X2TS U1605 ( .A(n1516), .B(n1515), .C(n1514), .CO(n1709), .S(n1533) );
CMPR32X2TS U1606 ( .A(n1279), .B(n1278), .C(n1277), .CO(n1284), .S(n1286) );
CMPR32X2TS U1607 ( .A(n1694), .B(n1693), .C(n1692), .CO(n1711), .S(n1707) );
CMPR32X2TS U1608 ( .A(n1728), .B(n1727), .C(n1726), .CO(n1732), .S(n1713) );
NAND2X1TS U1609 ( .A(n1678), .B(n1677), .Y(n2540) );
NAND2X1TS U1610 ( .A(n1672), .B(n1671), .Y(n2551) );
NAND2X1TS U1611 ( .A(n1680), .B(n1679), .Y(n1969) );
NOR2X1TS U1612 ( .A(n1678), .B(n1677), .Y(n1966) );
CMPR32X2TS U1613 ( .A(n1273), .B(n1272), .C(n1271), .CO(n1197), .S(n1288) );
CMPR32X2TS U1614 ( .A(n2423), .B(n2422), .C(n2421), .CO(
DP_OP_453J308_122_681_n409), .S(n1389) );
NOR2X1TS U1615 ( .A(FPMULT_Op_MY[9]), .B(n994), .Y(n2251) );
NOR2X2TS U1616 ( .A(n1680), .B(n1679), .Y(n1968) );
AOI21X1TS U1617 ( .A0(n2344), .A1(n2342), .B0(n2306), .Y(n2311) );
CMPR32X2TS U1618 ( .A(n1506), .B(n1034), .C(n1505), .CO(n1694), .S(n1529) );
CMPR32X2TS U1619 ( .A(n1568), .B(n1567), .C(n1566), .CO(n1679), .S(n1678) );
CMPR32X2TS U1620 ( .A(n1550), .B(n1549), .C(n1548), .CO(n1681), .S(n1680) );
CMPR32X2TS U1621 ( .A(n1691), .B(n1690), .C(n1689), .CO(n1712), .S(n1692) );
CMPR32X2TS U1622 ( .A(n1667), .B(n1666), .C(n1665), .CO(n1673), .S(n1672) );
CMPR32X2TS U1623 ( .A(n1282), .B(n1281), .C(n1280), .CO(n1289), .S(n1267) );
CMPR32X2TS U1624 ( .A(n1263), .B(n1262), .C(n1261), .CO(n1264), .S(n1233) );
CMPR32X2TS U1625 ( .A(n1260), .B(n1259), .C(n1258), .CO(n1266), .S(n1265) );
CMPR32X2TS U1626 ( .A(n1697), .B(n1696), .C(n1695), .CO(n1718), .S(n1693) );
CMPR32X2TS U1627 ( .A(n1174), .B(n1173), .C(n1172), .CO(n1182), .S(n1195) );
NAND2X4TS U1628 ( .A(n1011), .B(DP_OP_453J308_122_681_n2066), .Y(n2229) );
CMPR32X2TS U1629 ( .A(n1547), .B(n1546), .C(n1545), .CO(n1532), .S(n1548) );
CMPR32X2TS U1630 ( .A(n1565), .B(n1564), .C(n1563), .CO(n1549), .S(n1566) );
CMPR32X2TS U1631 ( .A(n1664), .B(n1663), .C(n1662), .CO(n1654), .S(n1665) );
CMPR32X2TS U1632 ( .A(n1257), .B(n1256), .C(n1255), .CO(n1281), .S(n1258) );
CMPR32X2TS U1633 ( .A(n1237), .B(n1236), .C(n1235), .CO(n1277), .S(n1282) );
CMPR32X2TS U1634 ( .A(n1254), .B(n1253), .C(n1252), .CO(n1259), .S(n1261) );
CMPR32X2TS U1635 ( .A(n1704), .B(n1513), .C(n1512), .CO(n1689), .S(n1514) );
CMPR32X2TS U1636 ( .A(n1579), .B(n1578), .C(n1577), .CO(n1567), .S(n1653) );
CMPR32X2TS U1637 ( .A(n1536), .B(n1535), .C(n1534), .CO(n1528), .S(n1550) );
CMPR32X2TS U1638 ( .A(n1276), .B(n1275), .C(n1274), .CO(n1287), .S(n1280) );
CMPR32X2TS U1639 ( .A(n1705), .B(n1704), .C(n1703), .CO(n1714), .S(n1690) );
NAND2X1TS U1640 ( .A(n1213), .B(n1212), .Y(n2028) );
NAND2X1TS U1641 ( .A(n1207), .B(n1206), .Y(n2019) );
CMPR32X2TS U1642 ( .A(n1661), .B(n1660), .C(n1659), .CO(n1577), .S(n1666) );
CMPR32X2TS U1643 ( .A(n1544), .B(n1543), .C(n1542), .CO(n1547), .S(n1563) );
CMPR32X2TS U1644 ( .A(n1504), .B(n1503), .C(n1502), .CO(n1515), .S(n1534) );
CMPR32X2TS U1645 ( .A(n1553), .B(n1552), .C(n1551), .CO(n1545), .S(n1568) );
CMPR32X2TS U1646 ( .A(n1571), .B(n1570), .C(n1569), .CO(n1564), .S(n1655) );
CMPR32X2TS U1647 ( .A(n1645), .B(n1644), .C(n1643), .CO(n1646), .S(n1613) );
ADDHXLTS U1648 ( .A(n1574), .B(n1573), .CO(n1579), .S(n1663) );
CMPR32X2TS U1649 ( .A(n1589), .B(n1588), .C(n1587), .CO(n1612), .S(n1611) );
CMPR32X2TS U1650 ( .A(n1522), .B(n1521), .C(n1520), .CO(n1530), .S(n1546) );
CMPR32X2TS U1651 ( .A(n1558), .B(n1557), .C(n1556), .CO(n1565), .S(n1578) );
ADDFX2TS U1652 ( .A(n1670), .B(n1669), .CI(n1668), .CO(n1671), .S(n1649) );
CMPR32X2TS U1653 ( .A(n1221), .B(n1220), .C(n1219), .CO(n1222), .S(n1213) );
NAND2X1TS U1654 ( .A(n992), .B(FPMULT_Op_MY[5]), .Y(n2341) );
BUFX4TS U1655 ( .A(n2228), .Y(n1011) );
OAI21X1TS U1656 ( .A0(n1594), .A1(n1593), .B0(n1592), .Y(n2580) );
CMPR32X2TS U1657 ( .A(n1658), .B(n1657), .C(n1656), .CO(n1667), .S(n1668) );
CMPR32X2TS U1658 ( .A(n1639), .B(n1638), .C(n1637), .CO(n1669), .S(n1640) );
CMPR32X2TS U1659 ( .A(n1618), .B(n1617), .C(n1616), .CO(n1662), .S(n1670) );
CMPR32X2TS U1660 ( .A(n1636), .B(n1635), .C(n1634), .CO(n1641), .S(n1643) );
ADDHXLTS U1661 ( .A(n1586), .B(n1585), .CO(n1644), .S(n1587) );
INVX4TS U1662 ( .A(n949), .Y(n996) );
INVX2TS U1663 ( .A(n1049), .Y(n988) );
INVX4TS U1664 ( .A(DP_OP_453J308_122_681_n2086), .Y(n992) );
CLKBUFX2TS U1665 ( .A(n1830), .Y(n1015) );
INVX4TS U1666 ( .A(n1031), .Y(n993) );
INVX4TS U1667 ( .A(n1032), .Y(n990) );
INVX4TS U1668 ( .A(FPMULT_Op_MX[0]), .Y(n1628) );
NOR2X1TS U1669 ( .A(n992), .B(FPMULT_Op_MY[5]), .Y(n2305) );
NAND2X1TS U1670 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[15]), .Y(n2337) );
NOR2XLTS U1671 ( .A(n996), .B(n1075), .Y(n1757) );
OAI21XLTS U1672 ( .A0(FPMULT_Op_MX[22]), .A1(FPMULT_Op_MX[10]), .B0(
FPMULT_Op_MX[9]), .Y(n1422) );
ADDHXLTS U1673 ( .A(n2410), .B(n2409), .CO(DP_OP_453J308_122_681_n394), .S(
n2408) );
OR2X1TS U1674 ( .A(n2258), .B(FPMULT_Op_MY[11]), .Y(n1073) );
CLKBUFX2TS U1675 ( .A(n2123), .Y(n1025) );
OAI21XLTS U1676 ( .A0(n1195), .A1(n1194), .B0(n1197), .Y(n1179) );
CMPR42X1TS U1677 ( .A(DP_OP_453J308_122_681_n449), .B(
DP_OP_453J308_122_681_n501), .C(DP_OP_453J308_122_681_n475), .D(
DP_OP_453J308_122_681_n462), .ICI(DP_OP_453J308_122_681_n291), .S(
DP_OP_453J308_122_681_n281), .ICO(DP_OP_453J308_122_681_n279), .CO(
DP_OP_453J308_122_681_n280) );
CLKBUFX2TS U1678 ( .A(n2150), .Y(n1023) );
NAND2X1TS U1679 ( .A(n1802), .B(n1801), .Y(n1933) );
NAND2X1TS U1680 ( .A(DP_OP_453J308_122_681_n398), .B(
DP_OP_453J308_122_681_n402), .Y(n1929) );
NOR2XLTS U1681 ( .A(n1886), .B(n1877), .Y(n1879) );
ADDHXLTS U1682 ( .A(n1527), .B(n1526), .CO(n1535), .S(n1551) );
ADDHXLTS U1683 ( .A(n1251), .B(n1250), .CO(n1274), .S(n1260) );
NOR2XLTS U1684 ( .A(n2229), .B(FPMULT_Op_MX[22]), .Y(n2196) );
CLKBUFX2TS U1685 ( .A(n1766), .Y(n1019) );
OR2X1TS U1686 ( .A(n1816), .B(n1815), .Y(n1060) );
CMPR42X1TS U1687 ( .A(DP_OP_453J308_122_681_n373), .B(
DP_OP_453J308_122_681_n535), .C(DP_OP_453J308_122_681_n522), .D(
DP_OP_453J308_122_681_n364), .ICI(DP_OP_453J308_122_681_n370), .S(
DP_OP_453J308_122_681_n362), .ICO(DP_OP_453J308_122_681_n360), .CO(
DP_OP_453J308_122_681_n361) );
AOI21X1TS U1688 ( .A0(n1083), .A1(n1919), .B0(n1392), .Y(n1909) );
NOR2X1TS U1689 ( .A(n2058), .B(n2063), .Y(n1405) );
ADDHXLTS U1690 ( .A(n1633), .B(n1632), .CO(n1656), .S(n1642) );
NOR2X1TS U1691 ( .A(n1389), .B(n2768), .Y(n1961) );
OAI21XLTS U1692 ( .A0(n1887), .A1(n1852), .B0(n1851), .Y(n1853) );
NOR2XLTS U1693 ( .A(n3261), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3262) );
NOR2X1TS U1694 ( .A(n2537), .B(n1979), .Y(n2727) );
NOR2XLTS U1695 ( .A(n1477), .B(n1465), .Y(n1294) );
NAND2X1TS U1696 ( .A(DP_OP_453J308_122_681_n230), .B(
DP_OP_453J308_122_681_n232), .Y(n1450) );
NAND2X1TS U1697 ( .A(DP_OP_453J308_122_681_n250), .B(
DP_OP_453J308_122_681_n257), .Y(n1482) );
OAI21X1TS U1698 ( .A0(n1401), .A1(n1846), .B0(n1400), .Y(n2003) );
OAI21XLTS U1699 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n3820), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n3268) );
OR2X1TS U1700 ( .A(n2232), .B(n2231), .Y(n1040) );
NAND2X1TS U1701 ( .A(n2535), .B(n1982), .Y(n2720) );
NOR2XLTS U1702 ( .A(n2215), .B(n2190), .Y(n2192) );
OAI21XLTS U1703 ( .A0(n1481), .A1(n1477), .B0(n1478), .Y(n1469) );
AOI21X1TS U1704 ( .A0(n1074), .A1(n2007), .B0(n1205), .Y(n2021) );
OAI21XLTS U1705 ( .A0(n2222), .A1(n2144), .B0(n2143), .Y(n2145) );
NAND2X1TS U1706 ( .A(n2531), .B(n1988), .Y(n2754) );
OR2X1TS U1707 ( .A(DP_OP_453J308_122_681_n774), .B(n2236), .Y(n1104) );
OAI21X2TS U1708 ( .A0(n2719), .A1(n2722), .B0(n2720), .Y(n2766) );
NAND2X1TS U1709 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .B(n2599), .Y(
n2202) );
XOR2X1TS U1710 ( .A(n2091), .B(n2090), .Y(n2096) );
XOR2X1TS U1711 ( .A(n2235), .B(n2234), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[23]) );
XNOR2X1TS U1712 ( .A(n2562), .B(n2561), .Y(n2716) );
NAND2X1TS U1713 ( .A(n2023), .B(n2592), .Y(n2650) );
NOR2XLTS U1714 ( .A(n2608), .B(DP_OP_453J308_122_681_n782), .Y(n2605) );
NOR2XLTS U1715 ( .A(n2611), .B(n2206), .Y(n2207) );
OR2X1TS U1716 ( .A(n2074), .B(n2586), .Y(n1102) );
OR2X1TS U1717 ( .A(n2023), .B(n2592), .Y(n1099) );
INVX2TS U1718 ( .A(n3646), .Y(n3629) );
BUFX4TS U1719 ( .A(n3599), .Y(n3636) );
OAI21X2TS U1720 ( .A0(n2649), .A1(n2645), .B0(n2646), .Y(n2644) );
AOI21X2TS U1721 ( .A0(n2635), .A1(n1042), .B0(n2072), .Y(n2632) );
OAI21XLTS U1722 ( .A0(n3009), .A1(n3013), .B0(n3008), .Y(n3007) );
NAND2X1TS U1723 ( .A(n3068), .B(n3057), .Y(n3042) );
NOR2X2TS U1724 ( .A(n3010), .B(operation[2]), .Y(n3599) );
OAI21XLTS U1725 ( .A0(n3127), .A1(n954), .B0(n3083), .Y(
FPADDSUB_Data_array_SWR[6]) );
OAI21XLTS U1726 ( .A0(n3137), .A1(n956), .B0(n3136), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI21XLTS U1727 ( .A0(n3454), .A1(n948), .B0(n3071), .Y(
FPADDSUB_Data_array_SWR[22]) );
OAI21XLTS U1728 ( .A0(n3115), .A1(n954), .B0(n3080), .Y(
FPADDSUB_Data_array_SWR[10]) );
OAI21XLTS U1729 ( .A0(n3121), .A1(n3453), .B0(n3103), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI21XLTS U1730 ( .A0(n3127), .A1(n3042), .B0(n3108), .Y(
FPADDSUB_Data_array_SWR[7]) );
INVX4TS U1731 ( .A(DP_OP_453J308_122_681_n1705), .Y(n949) );
INVX4TS U1732 ( .A(operation[1]), .Y(n959) );
NAND2X8TS U1733 ( .A(n2616), .B(n2098), .Y(n2613) );
INVX2TS U1734 ( .A(n2642), .Y(n2046) );
INVX1TS U1735 ( .A(n2615), .Y(n2617) );
XOR2X1TS U1736 ( .A(n2049), .B(n2048), .Y(n2053) );
XNOR2X1TS U1737 ( .A(n2086), .B(n1484), .Y(n2073) );
INVX2TS U1738 ( .A(n2080), .Y(n2083) );
AOI22X1TS U1739 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n3774), .B0(n3415), .B1(
n3414), .Y(n3418) );
INVX1TS U1740 ( .A(n2054), .Y(n2055) );
NAND2X1TS U1741 ( .A(n2533), .B(n1985), .Y(n2745) );
INVX1TS U1742 ( .A(n1429), .Y(n1330) );
NAND2X2TS U1743 ( .A(n1912), .B(n1810), .Y(n1886) );
NAND2X1TS U1744 ( .A(n1686), .B(n1955), .Y(n1688) );
NOR2X2TS U1745 ( .A(n1372), .B(n1371), .Y(n2176) );
OAI21XLTS U1746 ( .A0(n2962), .A1(n2964), .B0(n2961), .Y(n2960) );
NAND2X1TS U1747 ( .A(n2042), .B(n2041), .Y(n2043) );
XNOR2X1TS U1748 ( .A(n2498), .B(n1009), .Y(n2368) );
NOR2X2TS U1749 ( .A(n1806), .B(n1805), .Y(n1913) );
NAND2X1TS U1750 ( .A(n1078), .B(n1077), .Y(n1652) );
AOI21X1TS U1751 ( .A0(n2344), .A1(n2278), .B0(n2280), .Y(n2277) );
OAI211XLTS U1752 ( .A0(operation[1]), .A1(n2687), .B0(n2686), .C0(n2711),
.Y(add_subt_data2[14]) );
OAI211XLTS U1753 ( .A0(operation[1]), .A1(n2713), .B0(n2712), .C0(n2711),
.Y(add_subt_data2[5]) );
OAI211XLTS U1754 ( .A0(operation[1]), .A1(n2710), .B0(n2709), .C0(n2708),
.Y(add_subt_data2[3]) );
OAI211XLTS U1755 ( .A0(operation[1]), .A1(n3926), .B0(n2699), .C0(n2705),
.Y(add_subt_data2[7]) );
OAI211XLTS U1756 ( .A0(operation[1]), .A1(n2698), .B0(n2697), .C0(n2696),
.Y(add_subt_data2[15]) );
OAI211XLTS U1757 ( .A0(operation[1]), .A1(n3928), .B0(n2690), .C0(n2689),
.Y(add_subt_data2[18]) );
OAI211XLTS U1758 ( .A0(operation[1]), .A1(n2707), .B0(n2706), .C0(n2705),
.Y(add_subt_data2[11]) );
OAI211XLTS U1759 ( .A0(operation[1]), .A1(n2695), .B0(n2694), .C0(n2696),
.Y(add_subt_data2[20]) );
OAI211XLTS U1760 ( .A0(operation[1]), .A1(n2683), .B0(n2682), .C0(n2689),
.Y(add_subt_data2[13]) );
OAI211XLTS U1761 ( .A0(operation[1]), .A1(n2693), .B0(n2692), .C0(n2691),
.Y(add_subt_data2[22]) );
AO21X1TS U1762 ( .A0(n2486), .A1(n998), .B0(n2483), .Y(
DP_OP_453J308_122_681_n500) );
AO22XLTS U1763 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n3783), .B1(n3650),
.Y(n3652) );
ADDFX1TS U1764 ( .A(n1231), .B(n1230), .CI(n1229), .CO(n1232), .S(n1223) );
NAND2BXLTS U1765 ( .AN(n3485), .B(n3484), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
INVX3TS U1766 ( .A(n3461), .Y(n3462) );
BUFX3TS U1767 ( .A(n3582), .Y(n3531) );
AO21X1TS U1768 ( .A0(n1700), .A1(n1008), .B0(n1033), .Y(n1722) );
BUFX4TS U1769 ( .A(n3599), .Y(n3633) );
BUFX4TS U1770 ( .A(n3629), .Y(n3632) );
BUFX4TS U1771 ( .A(n3629), .Y(n3635) );
AO22XLTS U1772 ( .A0(operation[2]), .A1(n3516), .B0(n3517), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
OAI211XLTS U1773 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n3814), .B0(n3242), .C0(
n3245), .Y(n3256) );
NAND2X1TS U1774 ( .A(n2265), .B(n2264), .Y(n2377) );
OAI21XLTS U1775 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n3717), .B0(n3424),
.Y(n3421) );
NAND2X1TS U1776 ( .A(n2329), .B(n2328), .Y(n2379) );
CLKAND2X2TS U1777 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3736), .Y(n3026)
);
CLKAND2X2TS U1778 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n3742), .Y(n3037)
);
AO22XLTS U1779 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n3517),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
INVX4TS U1780 ( .A(n1086), .Y(n989) );
XOR2X1TS U1781 ( .A(n2209), .B(n1046), .Y(FPMULT_Sgf_operation_Result[42])
);
NOR2X2TS U1782 ( .A(n2053), .B(n2589), .Y(n2637) );
INVX2TS U1783 ( .A(n2650), .Y(n2024) );
XOR2X1TS U1784 ( .A(n2067), .B(n2066), .Y(n2071) );
INVX2TS U1785 ( .A(n2658), .Y(n2002) );
XOR2X1TS U1786 ( .A(n1476), .B(n1475), .Y(n2074) );
NOR2X2TS U1787 ( .A(n2031), .B(n2591), .Y(n2645) );
XOR2X1TS U1788 ( .A(n3436), .B(n3435), .Y(FPADDSUB_Raw_mant_SGF[25]) );
OAI32X1TS U1789 ( .A0(n3882), .A1(n3433), .A2(n3432), .B0(n3431), .B1(n910),
.Y(n3435) );
AOI21X1TS U1790 ( .A0(n2061), .A1(n2034), .B0(n2033), .Y(n2039) );
NOR2X2TS U1791 ( .A(n2009), .B(n2593), .Y(n2653) );
AOI21X1TS U1792 ( .A0(n2086), .A1(n1483), .B0(n1471), .Y(n1476) );
XOR2X1TS U1793 ( .A(n2000), .B(n1999), .Y(n2001) );
AOI21X1TS U1794 ( .A0(n1997), .A1(n1093), .B0(n1996), .Y(n2000) );
NAND2X1TS U1795 ( .A(n1474), .B(n1473), .Y(n1475) );
XOR2X1TS U1796 ( .A(n1862), .B(n1861), .Y(n1989) );
INVX2TS U1797 ( .A(n1846), .Y(n1997) );
INVX2TS U1798 ( .A(n1472), .Y(n1474) );
INVX2TS U1799 ( .A(n1840), .Y(n1862) );
INVX1TS U1800 ( .A(n2056), .Y(n2059) );
AOI21X1TS U1801 ( .A0(n1092), .A1(n1996), .B0(n1399), .Y(n1400) );
XOR2X1TS U1802 ( .A(n1876), .B(n1875), .Y(n1988) );
OAI22X2TS U1803 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n3758), .B0(n3060),
.B1(n3059), .Y(n3414) );
NOR2X2TS U1804 ( .A(DP_OP_453J308_122_681_n238), .B(
DP_OP_453J308_122_681_n243), .Y(n2082) );
OAI21X2TS U1805 ( .A0(n1396), .A1(n1872), .B0(n1395), .Y(n1840) );
BUFX3TS U1806 ( .A(n3056), .Y(n3455) );
AOI22X2TS U1807 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n3702), .B0(n3410), .B1(
n3409), .Y(n3059) );
NOR2X2TS U1808 ( .A(DP_OP_453J308_122_681_n275), .B(
DP_OP_453J308_122_681_n283), .Y(n2035) );
BUFX3TS U1809 ( .A(n3042), .Y(n3453) );
OR2X2TS U1810 ( .A(DP_OP_453J308_122_681_n369), .B(
DP_OP_453J308_122_681_n376), .Y(n1084) );
AO22XLTS U1811 ( .A0(n3518), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n3084), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
XNOR2X1TS U1812 ( .A(n1920), .B(n1919), .Y(n1982) );
AO22XLTS U1813 ( .A0(n3518), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n3734), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22XLTS U1814 ( .A0(n3881), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n3734), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
INVX2TS U1815 ( .A(n2585), .Y(DP_OP_453J308_122_681_n786) );
INVX2TS U1816 ( .A(n2105), .Y(DP_OP_453J308_122_681_n785) );
INVX4TS U1817 ( .A(n1328), .Y(n2095) );
INVX3TS U1818 ( .A(n1940), .Y(n2543) );
NOR2X1TS U1819 ( .A(n1329), .B(n1431), .Y(n1332) );
OAI21X1TS U1820 ( .A0(n1330), .A1(n1431), .B0(n1432), .Y(n1331) );
XOR2X1TS U1821 ( .A(n3016), .B(n3015), .Y(FPADDSUB_Raw_mant_SGF[11]) );
NOR2X1TS U1822 ( .A(n1897), .B(n1913), .Y(n1900) );
AOI21X1TS U1823 ( .A0(n2562), .A1(n1077), .B0(n2556), .Y(n2559) );
XNOR2X1TS U1824 ( .A(n2568), .B(n2567), .Y(n2715) );
INVX1TS U1825 ( .A(n2172), .Y(n2173) );
INVX1TS U1826 ( .A(n2174), .Y(n2177) );
AOI21X2TS U1827 ( .A0(n1464), .A1(n1294), .B0(n1293), .Y(n1328) );
OAI21X2TS U1828 ( .A0(n2555), .A1(n1652), .B0(n1651), .Y(n2544) );
AOI21X1TS U1829 ( .A0(n1686), .A1(n1954), .B0(n1685), .Y(n1687) );
NAND2X1TS U1830 ( .A(n1467), .B(n1466), .Y(n1468) );
XNOR2X1TS U1831 ( .A(n2508), .B(n999), .Y(n2511) );
OAI21X1TS U1832 ( .A0(n1950), .A1(n1058), .B0(n1951), .Y(n1938) );
OAI22X1TS U1833 ( .A0(n2368), .A1(n1003), .B0(n2460), .B1(n2373), .Y(n2371)
);
OAI21X1TS U1834 ( .A0(n1901), .A1(n1914), .B0(n1902), .Y(n1809) );
OAI22X1TS U1835 ( .A0(n2480), .A1(n2487), .B0(n2482), .B1(n2486), .Y(n2390)
);
OAI22X1TS U1836 ( .A0(n2445), .A1(n2356), .B0(n2354), .B1(n2446), .Y(n2358)
);
OAI22X1TS U1837 ( .A0(n2455), .A1(n1002), .B0(n2368), .B1(n2460), .Y(n2366)
);
XNOR2X2TS U1838 ( .A(n2052), .B(n2051), .Y(n2589) );
OAI22X1TS U1839 ( .A0(n2501), .A1(n2503), .B0(n2412), .B1(n2500), .Y(n2407)
);
NAND2X1TS U1840 ( .A(n1804), .B(n1803), .Y(n1924) );
NOR2X4TS U1841 ( .A(n1674), .B(n1673), .Y(n2545) );
AOI21X1TS U1842 ( .A0(n2344), .A1(n2285), .B0(n2284), .Y(n2290) );
AOI21X1TS U1843 ( .A0(n2316), .A1(n2259), .B0(n2258), .Y(n2260) );
NAND2X1TS U1844 ( .A(n1077), .B(n2560), .Y(n2561) );
NOR2X2TS U1845 ( .A(n1672), .B(n1671), .Y(n2550) );
AOI21X1TS U1846 ( .A0(n2316), .A1(n2314), .B0(n2252), .Y(n2257) );
OR2X2TS U1847 ( .A(n1265), .B(n1264), .Y(n1097) );
OAI21X1TS U1848 ( .A0(n2340), .A1(n2336), .B0(n2337), .Y(n2335) );
AO21X1TS U1849 ( .A0(n2470), .A1(n1000), .B0(n2398), .Y(n2304) );
XOR3X2TS U1850 ( .A(n1834), .B(n1833), .C(n1832), .Y(n1835) );
NAND2BXLTS U1851 ( .AN(n951), .B(n1004), .Y(n2404) );
NAND2BXLTS U1852 ( .AN(n951), .B(n1006), .Y(n2397) );
AO21X1TS U1853 ( .A0(n1767), .A1(n1020), .B0(n1031), .Y(n1771) );
INVX4TS U1854 ( .A(n2807), .Y(n2888) );
AO21X1TS U1855 ( .A0(n1743), .A1(n1014), .B0(n1032), .Y(n1751) );
OAI22X1TS U1856 ( .A0(n1743), .A1(n1582), .B0(n1014), .B1(n1627), .Y(n1635)
);
AO21X1TS U1857 ( .A0(n1831), .A1(n1016), .B0(n996), .Y(n1832) );
XOR2X1TS U1858 ( .A(n2270), .B(n2294), .Y(n2271) );
NAND2X1TS U1859 ( .A(n2380), .B(n2379), .Y(n2381) );
XNOR2X1TS U1860 ( .A(n2383), .B(n2378), .Y(n2382) );
NOR2X1TS U1861 ( .A(n2269), .B(n2268), .Y(n2270) );
INVX2TS U1862 ( .A(n2781), .Y(n2795) );
INVX2TS U1863 ( .A(n1384), .Y(n1414) );
NOR2BX1TS U1864 ( .AN(n912), .B(n1025), .Y(n1253) );
XNOR2X1TS U1865 ( .A(n992), .B(FPMULT_Op_MX[16]), .Y(n1241) );
NAND2X4TS U1866 ( .A(n986), .B(n1628), .Y(n1631) );
XNOR2X1TS U1867 ( .A(n993), .B(FPMULT_Op_MY[5]), .Y(n1517) );
NOR2X1TS U1868 ( .A(n987), .B(FPMULT_Op_MX[15]), .Y(n2378) );
XNOR2X1TS U1869 ( .A(n992), .B(FPMULT_Op_MX[17]), .Y(n1175) );
XNOR2X1TS U1870 ( .A(n990), .B(FPMULT_Op_MY[6]), .Y(n1539) );
XNOR2X1TS U1871 ( .A(n993), .B(FPMULT_Op_MY[4]), .Y(n1540) );
XNOR2X1TS U1872 ( .A(n993), .B(FPMULT_Op_MY[3]), .Y(n1559) );
XNOR2X1TS U1873 ( .A(n2268), .B(n2263), .Y(n2267) );
XNOR2X1TS U1874 ( .A(n990), .B(FPMULT_Op_MY[5]), .Y(n1554) );
AND2X2TS U1875 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3732), .Y(n3013) );
AND2X2TS U1876 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3730), .Y(n2964) );
AND2X2TS U1877 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n3728), .Y(n2934) );
XOR2X1TS U1878 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n2268) );
XNOR2X1TS U1879 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[19]), .Y(n1170) );
NAND2X1TS U1880 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2264) );
OAI21X1TS U1881 ( .A0(FPMULT_Op_MX[4]), .A1(FPMULT_Op_MX[16]), .B0(
FPMULT_Op_MX[15]), .Y(n2265) );
XOR2X1TS U1882 ( .A(n2201), .B(DP_OP_453J308_122_681_n774), .Y(
FPMULT_Sgf_operation_Result[46]) );
XOR2X1TS U1883 ( .A(n2603), .B(DP_OP_453J308_122_681_n777), .Y(
FPMULT_Sgf_operation_Result[43]) );
XOR2X1TS U1884 ( .A(n2213), .B(n1041), .Y(FPMULT_Sgf_operation_Result[40])
);
XOR2X1TS U1885 ( .A(n2610), .B(DP_OP_453J308_122_681_n782), .Y(
FPMULT_Sgf_operation_Result[38]) );
XOR2X1TS U1886 ( .A(n2205), .B(n1100), .Y(FPMULT_Sgf_operation_Result[44])
);
XOR2X1TS U1887 ( .A(n2104), .B(n2103), .Y(FPMULT_Sgf_operation_Result[41])
);
XOR2X1TS U1888 ( .A(n2598), .B(DP_OP_453J308_122_681_n775), .Y(
FPMULT_Sgf_operation_Result[45]) );
XOR2X1TS U1889 ( .A(n2607), .B(n2606), .Y(FPMULT_Sgf_operation_Result[39])
);
OR2X4TS U1890 ( .A(n1101), .B(n2615), .Y(n2098) );
XOR2X1TS U1891 ( .A(n2618), .B(n1101), .Y(FPMULT_Sgf_operation_Result[36])
);
XOR2X1TS U1892 ( .A(n2623), .B(n2622), .Y(FPMULT_Sgf_operation_Result[35])
);
XOR2X1TS U1893 ( .A(n2633), .B(n2632), .Y(FPMULT_Sgf_operation_Result[32])
);
XOR2X1TS U1894 ( .A(n2641), .B(n2640), .Y(FPMULT_Sgf_operation_Result[30])
);
XOR2X1TS U1895 ( .A(n2649), .B(n2648), .Y(FPMULT_Sgf_operation_Result[28])
);
XOR2X1TS U1896 ( .A(n2657), .B(n2656), .Y(FPMULT_Sgf_operation_Result[26])
);
NOR2X1TS U1897 ( .A(n2608), .B(n2600), .Y(n2602) );
NOR2X1TS U1898 ( .A(n2608), .B(n2210), .Y(n2212) );
NOR2X1TS U1899 ( .A(n2611), .B(n2202), .Y(n2203) );
NOR2X1TS U1900 ( .A(n2611), .B(n2600), .Y(n2601) );
NOR2X1TS U1901 ( .A(n2608), .B(n2206), .Y(n2208) );
NOR2X1TS U1902 ( .A(n2611), .B(n2210), .Y(n2211) );
OAI21X2TS U1903 ( .A0(n1995), .A1(n2667), .B0(n1994), .Y(n2660) );
NOR2X1TS U1904 ( .A(n2608), .B(n2202), .Y(n2204) );
NOR2X1TS U1905 ( .A(n2611), .B(n2236), .Y(n2186) );
NOR2X1TS U1906 ( .A(n2608), .B(n2595), .Y(n2597) );
NOR2X1TS U1907 ( .A(n2608), .B(n2236), .Y(n2187) );
XOR2X1TS U1908 ( .A(n2665), .B(n2664), .Y(FPMULT_Sgf_operation_Result[24])
);
NOR2X1TS U1909 ( .A(n2611), .B(n2595), .Y(n2596) );
NOR2X1TS U1910 ( .A(n2608), .B(n2100), .Y(n2102) );
NOR2X1TS U1911 ( .A(n2611), .B(n2100), .Y(n2101) );
NOR2X1TS U1912 ( .A(n2611), .B(DP_OP_453J308_122_681_n782), .Y(n2604) );
NOR2X1TS U1913 ( .A(n2608), .B(n1104), .Y(n2238) );
INVX2TS U1914 ( .A(n2634), .Y(n2072) );
NOR2X1TS U1915 ( .A(n2611), .B(n1104), .Y(n2237) );
OR2X2TS U1916 ( .A(n2045), .B(n2590), .Y(n1037) );
INVX2TS U1917 ( .A(n2662), .Y(n2667) );
OR2X2TS U1918 ( .A(n2076), .B(n2585), .Y(n1103) );
OR2X2TS U1919 ( .A(n2071), .B(n2588), .Y(n1042) );
NAND2X2TS U1920 ( .A(n2053), .B(n2589), .Y(n2638) );
NAND2X2TS U1921 ( .A(n2045), .B(n2590), .Y(n2642) );
NAND2X2TS U1922 ( .A(n2097), .B(n2584), .Y(n2616) );
XOR2X2TS U1923 ( .A(n2039), .B(n2038), .Y(n2045) );
XNOR2X2TS U1924 ( .A(n2017), .B(n2016), .Y(n2023) );
AOI21X1TS U1925 ( .A0(n2061), .A1(n2054), .B0(n2056), .Y(n2049) );
AOI21X1TS U1926 ( .A0(n2062), .A1(n2061), .B0(n2060), .Y(n2067) );
OR2X2TS U1927 ( .A(n2001), .B(n2421), .Y(n1045) );
XOR2X1TS U1928 ( .A(n3428), .B(n3427), .Y(FPADDSUB_Raw_mant_SGF[24]) );
XOR2X1TS U1929 ( .A(n3422), .B(n3421), .Y(FPADDSUB_Raw_mant_SGF[23]) );
AOI21X2TS U1930 ( .A0(n2003), .A1(n1403), .B0(n1402), .Y(n2025) );
OAI21X1TS U1931 ( .A0(n3064), .A1(n3419), .B0(n3063), .Y(n3062) );
XNOR2X1TS U1932 ( .A(n1845), .B(n1844), .Y(n1990) );
NOR2X1TS U1933 ( .A(n1445), .B(n1449), .Y(n1411) );
NOR2X1TS U1934 ( .A(n2079), .B(n2082), .Y(n2085) );
OAI21X1TS U1935 ( .A0(n3109), .A1(n3453), .B0(n3086), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI21X1TS U1936 ( .A0(n3120), .A1(n3453), .B0(n3092), .Y(
FPADDSUB_Data_array_SWR[17]) );
OAI21X1TS U1937 ( .A0(n3125), .A1(n3453), .B0(n3124), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI21X1TS U1938 ( .A0(n3115), .A1(n3453), .B0(n3105), .Y(
FPADDSUB_Data_array_SWR[11]) );
OAI21X1TS U1939 ( .A0(n2083), .A1(n2082), .B0(n2081), .Y(n2084) );
OAI21X1TS U1940 ( .A0(n3143), .A1(n3453), .B0(n3142), .Y(
FPADDSUB_Data_array_SWR[20]) );
OAI21X1TS U1941 ( .A0(n3121), .A1(n954), .B0(n3077), .Y(
FPADDSUB_Data_array_SWR[18]) );
OAI21X1TS U1942 ( .A0(n3119), .A1(n3453), .B0(n3118), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI21X1TS U1943 ( .A0(n3114), .A1(n3453), .B0(n3096), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI21X1TS U1944 ( .A0(n3099), .A1(n3453), .B0(n3098), .Y(
FPADDSUB_Data_array_SWR[3]) );
OAI21X1TS U1945 ( .A0(n3133), .A1(n954), .B0(n3074), .Y(
FPADDSUB_Data_array_SWR[14]) );
OAI21X1TS U1946 ( .A0(n3113), .A1(n3042), .B0(n3112), .Y(
FPADDSUB_Data_array_SWR[1]) );
OAI21X1TS U1947 ( .A0(n3131), .A1(n956), .B0(n3130), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI21X1TS U1948 ( .A0(n3132), .A1(n956), .B0(n3094), .Y(
FPADDSUB_Data_array_SWR[13]) );
OAI21X1TS U1949 ( .A0(n3138), .A1(n3453), .B0(n3088), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI21X1TS U1950 ( .A0(n3126), .A1(n956), .B0(n3090), .Y(
FPADDSUB_Data_array_SWR[5]) );
OAI21X1TS U1951 ( .A0(n3133), .A1(n956), .B0(n3101), .Y(
FPADDSUB_Data_array_SWR[15]) );
XOR2X1TS U1952 ( .A(n3417), .B(n3416), .Y(FPADDSUB_Raw_mant_SGF[21]) );
OAI21X1TS U1953 ( .A0(n1862), .A1(n1858), .B0(n1859), .Y(n1845) );
OAI21X1TS U1954 ( .A0(n2063), .A1(n2057), .B0(n2064), .Y(n1404) );
OAI21X1TS U1955 ( .A0(n2013), .A1(n2010), .B0(n2014), .Y(n1402) );
NOR2X2TS U1956 ( .A(n1470), .B(n1472), .Y(n2078) );
OAI21X2TS U1957 ( .A0(n2035), .A1(n2032), .B0(n2036), .Y(n2056) );
OAI21X1TS U1958 ( .A0(n2087), .A1(n2081), .B0(n2088), .Y(n1408) );
OAI21X1TS U1959 ( .A0(n3055), .A1(n3060), .B0(n3054), .Y(n3053) );
NOR2X2TS U1960 ( .A(n2026), .B(n2035), .Y(n2054) );
OR2X2TS U1961 ( .A(DP_OP_453J308_122_681_n229), .B(n1425), .Y(n1094) );
NOR2X2TS U1962 ( .A(DP_OP_453J308_122_681_n295), .B(
DP_OP_453J308_122_681_n305), .Y(n2013) );
OAI211X1TS U1963 ( .A0(n3109), .A1(n3056), .B0(n3113), .C0(n3058), .Y(
FPADDSUB_Data_array_SWR[0]) );
NOR2X1TS U1964 ( .A(n1841), .B(n1858), .Y(n1398) );
OAI21X1TS U1965 ( .A0(n1841), .A1(n1859), .B0(n1842), .Y(n1397) );
XOR2X1TS U1966 ( .A(n3412), .B(n3411), .Y(FPADDSUB_Raw_mant_SGF[19]) );
NAND2X2TS U1967 ( .A(DP_OP_453J308_122_681_n339), .B(
DP_OP_453J308_122_681_n349), .Y(n1842) );
OR2X2TS U1968 ( .A(DP_OP_453J308_122_681_n328), .B(
DP_OP_453J308_122_681_n338), .Y(n1093) );
AOI21X2TS U1969 ( .A0(n1079), .A1(n2949), .B0(n1978), .Y(n2730) );
NOR2X4TS U1970 ( .A(DP_OP_453J308_122_681_n339), .B(
DP_OP_453J308_122_681_n349), .Y(n1841) );
OAI21X1TS U1971 ( .A0(n3048), .A1(n3050), .B0(n3047), .Y(n3046) );
AOI21X2TS U1972 ( .A0(n1091), .A1(n1873), .B0(n1394), .Y(n1395) );
OAI21X1TS U1973 ( .A0(n3454), .A1(n3453), .B0(n3170), .Y(
FPADDSUB_Data_array_SWR[25]) );
NAND2X2TS U1974 ( .A(DP_OP_453J308_122_681_n350), .B(
DP_OP_453J308_122_681_n358), .Y(n1859) );
XOR2X1TS U1975 ( .A(n3407), .B(n3406), .Y(FPADDSUB_Raw_mant_SGF[17]) );
OAI21X1TS U1976 ( .A0(n3041), .A1(n3044), .B0(n3040), .Y(n3039) );
OAI21X2TS U1977 ( .A0(n1909), .A1(n1906), .B0(n1907), .Y(n1896) );
INVX2TS U1978 ( .A(n2718), .Y(DP_OP_453J308_122_681_n423) );
NOR3X1TS U1979 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n3018), .Y(n3935) );
XOR2X1TS U1980 ( .A(n3402), .B(n3401), .Y(FPADDSUB_Raw_mant_SGF[15]) );
CLKXOR2X2TS U1981 ( .A(n1917), .B(n1916), .Y(n2535) );
NAND2X1TS U1982 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[14]), .Y(n2210) );
XNOR2X2TS U1983 ( .A(n1936), .B(n1935), .Y(n2537) );
OAI21X1TS U1984 ( .A0(n3035), .A1(n3037), .B0(n3034), .Y(n3033) );
OAI21X2TS U1985 ( .A0(n1931), .A1(n1928), .B0(n1929), .Y(n1919) );
BUFX3TS U1986 ( .A(n2824), .Y(n961) );
CLKXOR2X2TS U1987 ( .A(n1435), .B(n1434), .Y(n2583) );
AOI21X1TS U1988 ( .A0(n2095), .A1(n1430), .B0(n1429), .Y(n1435) );
XNOR2X2TS U1989 ( .A(n1469), .B(n1468), .Y(n2585) );
AOI21X2TS U1990 ( .A0(n1066), .A1(n1938), .B0(n1391), .Y(n1931) );
XOR2X1TS U1991 ( .A(n3029), .B(n3028), .Y(FPADDSUB_Raw_mant_SGF[13]) );
AOI21X1TS U1992 ( .A0(n1436), .A1(n2172), .B0(n2174), .Y(n1375) );
OAI21X1TS U1993 ( .A0(n2177), .A1(n2176), .B0(n2175), .Y(n2178) );
OAI21X2TS U1994 ( .A0(n1306), .A1(n1328), .B0(n1305), .Y(n1436) );
NOR2X1TS U1995 ( .A(n2173), .B(n2176), .Y(n2179) );
NOR2X6TS U1996 ( .A(n3931), .B(n3932), .Y(n2824) );
OAI21X1TS U1997 ( .A0(n2222), .A1(n2190), .B0(n2189), .Y(n2191) );
NOR2X1TS U1998 ( .A(n1886), .B(n1824), .Y(n1826) );
OAI21X1TS U1999 ( .A0(n1887), .A1(n1824), .B0(n1823), .Y(n1825) );
OAI21X1TS U2000 ( .A0(n2222), .A1(n2164), .B0(n2163), .Y(n2165) );
OAI21X1TS U2001 ( .A0(n3024), .A1(n3026), .B0(n3023), .Y(n3022) );
NOR2X1TS U2002 ( .A(n2215), .B(n2164), .Y(n2166) );
NOR2X1TS U2003 ( .A(n2215), .B(n2144), .Y(n2146) );
NOR2X1TS U2004 ( .A(n2215), .B(n2221), .Y(n2224) );
OAI31X1TS U2005 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n2790), .A2(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n2789), .Y(n3168) );
OAI21X1TS U2006 ( .A0(n2222), .A1(n2221), .B0(n2220), .Y(n2223) );
OAI21X1TS U2007 ( .A0(n1898), .A1(n1913), .B0(n1914), .Y(n1899) );
OAI21X1TS U2008 ( .A0(n1887), .A1(n1877), .B0(n1890), .Y(n1878) );
INVX2TS U2009 ( .A(n2544), .Y(n2554) );
NOR2X1TS U2010 ( .A(n1886), .B(n1866), .Y(n1868) );
NOR2X1TS U2011 ( .A(n1941), .B(n1956), .Y(n1944) );
OAI21X1TS U2012 ( .A0(n1942), .A1(n1956), .B0(n1957), .Y(n1943) );
NOR2X1TS U2013 ( .A(n1886), .B(n1852), .Y(n1854) );
OAI21X1TS U2014 ( .A0(n1887), .A1(n1866), .B0(n1865), .Y(n1867) );
AND3X2TS U2015 ( .A(n2704), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n2703),
.Y(n3932) );
INVX2TS U2016 ( .A(n1430), .Y(n1329) );
XNOR2X2TS U2017 ( .A(n2070), .B(n2069), .Y(n2588) );
AOI21X1TS U2018 ( .A0(n1304), .A1(n1429), .B0(n1303), .Y(n1305) );
INVX2TS U2019 ( .A(n1912), .Y(n1897) );
AOI21X2TS U2020 ( .A0(n1078), .A1(n2556), .B0(n1650), .Y(n1651) );
OAI22X1TS U2021 ( .A0(n2511), .A1(n2526), .B0(n2509), .B1(n2527), .Y(
DP_OP_453J308_122_681_n533) );
OAI22X1TS U2022 ( .A0(n2515), .A1(n2526), .B0(n2513), .B1(n2527), .Y(
DP_OP_453J308_122_681_n535) );
OAI21X2TS U2023 ( .A0(n1923), .A1(n1933), .B0(n1924), .Y(n1911) );
OAI21X1TS U2024 ( .A0(n1819), .A1(n1890), .B0(n1818), .Y(n1850) );
NAND2BX1TS U2025 ( .AN(n3152), .B(n995), .Y(n3161) );
NAND2X1TS U2026 ( .A(n2541), .B(n2540), .Y(n2542) );
NOR2X2TS U2027 ( .A(n1804), .B(n1803), .Y(n1923) );
XNOR2X1TS U2028 ( .A(n2504), .B(n999), .Y(n2507) );
XNOR2X1TS U2029 ( .A(n2506), .B(n999), .Y(n2509) );
XNOR2X1TS U2030 ( .A(n2516), .B(n1004), .Y(n2481) );
NAND2X1TS U2031 ( .A(n1479), .B(n1478), .Y(n1480) );
OAI22X1TS U2032 ( .A0(n2518), .A1(n2527), .B0(n2521), .B1(n2526), .Y(n2406)
);
XOR2X2TS U2033 ( .A(n2044), .B(n2043), .Y(n2590) );
AO21X1TS U2034 ( .A0(n2218), .A1(n1050), .B0(n2217), .Y(n1027) );
OAI21X2TS U2035 ( .A0(n2545), .A1(n2551), .B0(n2546), .Y(n1675) );
XNOR2X1TS U2036 ( .A(n2498), .B(n1010), .Y(n2356) );
NOR2X1TS U2037 ( .A(n2424), .B(n1423), .Y(n1424) );
XNOR2X1TS U2038 ( .A(n2510), .B(n999), .Y(n2513) );
XNOR2X1TS U2039 ( .A(n2495), .B(n1009), .Y(n2455) );
NOR2X2TS U2040 ( .A(n1812), .B(n1811), .Y(n1877) );
NAND2X2TS U2041 ( .A(n1674), .B(n1673), .Y(n2546) );
XNOR2X1TS U2042 ( .A(n2498), .B(n999), .Y(n2521) );
AOI31X1TS U2043 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n2797), .A2(n3753),
.B0(n2796), .Y(n2798) );
XNOR2X1TS U2044 ( .A(n2495), .B(n1010), .Y(n2354) );
CLKXOR2X2TS U2045 ( .A(n2257), .B(n2256), .Y(n2508) );
AND2X2TS U2046 ( .A(n1054), .B(n1050), .Y(n1029) );
CLKXOR2X2TS U2047 ( .A(n2260), .B(FPMULT_Op_MY[11]), .Y(n2506) );
OR2X2TS U2048 ( .A(n2198), .B(n2197), .Y(n1050) );
OR2X2TS U2049 ( .A(n1814), .B(n1813), .Y(n1061) );
XNOR2X1TS U2050 ( .A(n2520), .B(n999), .Y(n2524) );
AOI21X2TS U2051 ( .A0(n2316), .A1(n2259), .B0(n1073), .Y(n2424) );
XNOR2X1TS U2052 ( .A(n2520), .B(n1001), .Y(n2501) );
XNOR2X1TS U2053 ( .A(n2581), .B(n2580), .Y(n2759) );
XNOR2X2TS U2054 ( .A(n2030), .B(n2029), .Y(n2591) );
XNOR2X1TS U2055 ( .A(n2520), .B(n1009), .Y(n2373) );
AOI21X2TS U2056 ( .A0(n2580), .A1(n1047), .B0(n1602), .Y(n2578) );
NOR2X1TS U2057 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n3162), .Y(n2778) );
OR2X2TS U2058 ( .A(n1821), .B(n1820), .Y(n1059) );
NAND2BX1TS U2059 ( .AN(n3162), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n3157)
);
OR2X2TS U2060 ( .A(n1836), .B(n1835), .Y(n1072) );
NAND3BX1TS U2061 ( .AN(n3261), .B(n3259), .C(n3258), .Y(n3278) );
OAI21X2TS U2062 ( .A0(n2018), .A1(n2021), .B0(n2019), .Y(n2029) );
OAI22X1TS U2063 ( .A0(n1423), .A1(n2363), .B0(n2431), .B1(n2362), .Y(n2367)
);
NOR2XLTS U2064 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3681), .Y(n3680) );
AO21X1TS U2065 ( .A0(n2445), .A1(n1005), .B0(n2434), .Y(
DP_OP_453J308_122_681_n455) );
AOI211X1TS U2066 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n3653), .B0(n3650), .C0(n2947), .Y(FPADDSUB_enable_Pipeline_input) );
AO21X1TS U2067 ( .A0(n2460), .A1(n1003), .B0(n2447), .Y(
DP_OP_453J308_122_681_n470) );
CLKINVX3TS U2068 ( .A(n3320), .Y(n962) );
BUFX3TS U2069 ( .A(n3370), .Y(n968) );
CLKINVX3TS U2070 ( .A(n3323), .Y(n966) );
XNOR2X2TS U2071 ( .A(n2008), .B(n2007), .Y(n2593) );
AOI31X1TS U2072 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n2795), .A2(n3740),
.B0(n3154), .Y(n2787) );
AOI31X1TS U2073 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n2795), .A2(n2794),
.B0(n3154), .Y(n2799) );
NOR2XLTS U2074 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3678), .Y(n3677) );
BUFX3TS U2075 ( .A(n3589), .Y(n3593) );
NAND2X4TS U2076 ( .A(n950), .B(n3755), .Y(n2816) );
NAND2BXLTS U2077 ( .AN(n951), .B(n1001), .Y(n2413) );
NAND2BXLTS U2078 ( .AN(n952), .B(n1010), .Y(n2433) );
NAND2BXLTS U2079 ( .AN(n952), .B(n1009), .Y(n2376) );
AO21X1TS U2080 ( .A0(n2151), .A1(n1024), .B0(DP_OP_453J308_122_681_n2084),
.Y(n2195) );
AO21X1TS U2081 ( .A0(n1365), .A1(n1018), .B0(DP_OP_453J308_122_681_n2086),
.Y(n2111) );
OAI21XLTS U2082 ( .A0(n2941), .A1(n2938), .B0(n3782), .Y(n834) );
BUFX3TS U2083 ( .A(n3503), .Y(n3592) );
BUFX3TS U2084 ( .A(n2673), .Y(n3557) );
BUFX3TS U2085 ( .A(n3503), .Y(n3588) );
AO21X1TS U2086 ( .A0(n1783), .A1(n1022), .B0(DP_OP_453J308_122_681_n1706),
.Y(n1796) );
NAND3XLTS U2087 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2890), .C(n2896),
.Y(n2894) );
AND2X4TS U2088 ( .A(n2897), .B(n2813), .Y(n2714) );
AO21X1TS U2089 ( .A0(n1317), .A1(n1013), .B0(n1086), .Y(n1345) );
AO21X1TS U2090 ( .A0(n2124), .A1(n1026), .B0(n1049), .Y(n2133) );
OAI211X1TS U2091 ( .A0(n3220), .A1(n3275), .B0(n3219), .C0(n3218), .Y(n3225)
);
CLKXOR2X2TS U2092 ( .A(n2296), .B(n2295), .Y(n1002) );
INVX4TS U2093 ( .A(n1423), .Y(n2431) );
NAND2X4TS U2094 ( .A(n978), .B(n3755), .Y(n2833) );
NOR2X4TS U2095 ( .A(n978), .B(n2837), .Y(n2822) );
INVX3TS U2096 ( .A(n2363), .Y(n952) );
AOI21X2TS U2097 ( .A0(n1053), .A1(n1414), .B0(n1413), .Y(n2352) );
NAND3XLTS U2098 ( .A(n3704), .B(n2896), .C(n2890), .Y(n2938) );
OR2X1TS U2099 ( .A(n3782), .B(n3324), .Y(n3321) );
OR2X1TS U2100 ( .A(n3322), .B(n3782), .Y(n3320) );
NOR2X1TS U2101 ( .A(FPMULT_FSM_selector_C), .B(n3324), .Y(n3325) );
OR2X1TS U2102 ( .A(FPMULT_FSM_selector_C), .B(n3322), .Y(n3323) );
OAI21X1TS U2103 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(n980), .B0(n3439),
.Y(n3437) );
NAND3XLTS U2104 ( .A(enab_cont_iter), .B(n3639), .C(n3598), .Y(n3484) );
XOR2X1TS U2105 ( .A(n2300), .B(n2299), .Y(n2301) );
NOR2X1TS U2106 ( .A(DP_OP_453J308_122_681_n1589), .B(n996), .Y(n1772) );
NAND2X1TS U2107 ( .A(n2321), .B(n1043), .Y(n2322) );
NOR2X1TS U2108 ( .A(n2325), .B(n2324), .Y(n2326) );
NOR2X1TS U2109 ( .A(n996), .B(n1048), .Y(n1727) );
NAND2X1TS U2110 ( .A(n2333), .B(n2332), .Y(n2334) );
AOI221X4TS U2111 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3881), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n3066), .C0(n3084), .Y(n3454) );
INVX4TS U2112 ( .A(n1382), .Y(n2527) );
NOR2X1TS U2113 ( .A(n996), .B(DP_OP_453J308_122_681_n1587), .Y(n1800) );
NOR2X6TS U2114 ( .A(n3010), .B(n2670), .Y(n2673) );
NOR2X1TS U2115 ( .A(n2298), .B(n2297), .Y(n2300) );
CLKINVX3TS U2116 ( .A(n3170), .Y(n958) );
XNOR2X1TS U2117 ( .A(FPMULT_Op_MY[9]), .B(n990), .Y(n1511) );
XNOR2X1TS U2118 ( .A(n990), .B(FPMULT_Op_MY[4]), .Y(n1575) );
XNOR2X1TS U2119 ( .A(FPMULT_Op_MY[11]), .B(n993), .Y(n1759) );
NOR2X2TS U2120 ( .A(FPMULT_Op_MY[7]), .B(n988), .Y(n2282) );
OAI21X1TS U2121 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n2784), .B0(n3747),
.Y(n2785) );
XNOR2X1TS U2122 ( .A(FPMULT_Op_MX[19]), .B(n946), .Y(n1245) );
NAND2BXLTS U2123 ( .AN(n983), .B(n993), .Y(n1621) );
CLKINVX3TS U2124 ( .A(n2860), .Y(n2818) );
XNOR2X1TS U2125 ( .A(FPMULT_Op_MY[8]), .B(n990), .Y(n1493) );
XNOR2X1TS U2126 ( .A(n990), .B(FPMULT_Op_MY[3]), .Y(n1626) );
XOR2X1TS U2127 ( .A(n990), .B(FPMULT_Op_MX[6]), .Y(n2269) );
NAND2BXLTS U2128 ( .AN(n912), .B(n988), .Y(n1240) );
INVX1TS U2129 ( .A(n3144), .Y(n3146) );
NOR2X1TS U2130 ( .A(n3240), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3241) );
NAND2BXLTS U2131 ( .AN(n983), .B(n949), .Y(n1519) );
OAI211X2TS U2132 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n3762), .B0(n3252),
.C0(n3238), .Y(n3254) );
XNOR2X1TS U2133 ( .A(FPMULT_Op_MY[7]), .B(n990), .Y(n1500) );
XNOR2X1TS U2134 ( .A(FPMULT_Op_MX[20]), .B(n946), .Y(n1192) );
OAI211X2TS U2135 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n3805), .B0(n3290),
.C0(n3257), .Y(n3266) );
INVX1TS U2136 ( .A(n3153), .Y(n3155) );
NOR2X1TS U2137 ( .A(FPMULT_Op_MX[21]), .B(n991), .Y(n2245) );
NOR2X1TS U2138 ( .A(n3274), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3216) );
NAND3X1TS U2139 ( .A(n3817), .B(n3217), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3219) );
XNOR2X1TS U2140 ( .A(FPMULT_Op_MX[22]), .B(n946), .Y(n1154) );
NOR2X1TS U2141 ( .A(n2242), .B(n2244), .Y(n2243) );
XNOR2X1TS U2142 ( .A(n988), .B(FPMULT_Op_MX[13]), .Y(n1244) );
XNOR2X1TS U2143 ( .A(FPMULT_Op_MX[21]), .B(n946), .Y(n1171) );
XNOR2X2TS U2144 ( .A(n987), .B(FPMULT_Op_MX[15]), .Y(n2380) );
NAND2BX1TS U2145 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3263) );
NAND2BX1TS U2146 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3257) );
NOR3X1TS U2147 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n3147) );
NAND2BX1TS U2148 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3218) );
NAND2BX1TS U2149 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3217) );
NAND2BX1TS U2150 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(n3699), .Y(n2791)
);
NOR2X1TS U2151 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n2793) );
NOR3X1TS U2152 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n3160) );
NOR3X1TS U2153 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n3153) );
NOR2X6TS U2154 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2815) );
OAI21X1TS U2155 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n3811), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3248) );
NAND2BX1TS U2156 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3272) );
NAND2BX1TS U2157 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3242) );
NAND2BX1TS U2158 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3238) );
XOR2X1TS U2159 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[8]), .Y(n2297) );
OAI21X1TS U2160 ( .A0(FPMULT_Op_MX[20]), .A1(FPMULT_Op_MX[8]), .B0(n918),
.Y(n2247) );
NOR2X1TS U2161 ( .A(n1051), .B(n923), .Y(n1130) );
OAI21X1TS U2162 ( .A0(FPMULT_Op_MX[6]), .A1(FPMULT_Op_MX[18]), .B0(
FPMULT_Op_MX[17]), .Y(n2273) );
XOR2X1TS U2163 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n2244) );
XNOR2X1TS U2164 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MY[15]), .Y(n1153) );
XNOR2X1TS U2165 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[13]), .Y(n1176) );
XOR2X1TS U2166 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2324) );
NOR2X1TS U2167 ( .A(n914), .B(FPMULT_Op_MX[13]), .Y(n2320) );
XNOR2X2TS U2168 ( .A(n915), .B(FPMULT_Op_MX[17]), .Y(n2385) );
XOR2X1TS U2169 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2383) );
NOR2X4TS U2170 ( .A(n960), .B(operation[2]), .Y(n2885) );
INVX4TS U2171 ( .A(rst), .Y(n824) );
AOI21X4TS U2172 ( .A0(n1103), .A1(n922), .B0(n2077), .Y(n2622) );
AO21X4TS U2173 ( .A0(n1102), .A1(n2627), .B0(n2075), .Y(n922) );
AOI21X4TS U2174 ( .A0(n2660), .A1(n1045), .B0(n2002), .Y(n2657) );
OA21X2TS U2175 ( .A0(n2753), .A1(n2756), .B0(n2754), .Y(n1082) );
AOI21X2TS U2176 ( .A0(n1081), .A1(n2763), .B0(n1987), .Y(n2756) );
NOR2X2TS U2177 ( .A(n1456), .B(n1454), .Y(n1430) );
XNOR2X4TS U2178 ( .A(n987), .B(FPMULT_Op_MX[4]), .Y(n1742) );
OA21X4TS U2179 ( .A0(n2622), .A1(n2619), .B0(n2620), .Y(n1101) );
OR2X2TS U2180 ( .A(n2529), .B(n1990), .Y(n1090) );
AOI21X1TS U2181 ( .A0(n1884), .A1(n1084), .B0(n1873), .Y(n1876) );
OAI22X1TS U2182 ( .A0(n1743), .A1(n1493), .B0(n1511), .B1(n1014), .Y(n1513)
);
OAI22X1TS U2183 ( .A0(n1743), .A1(n1500), .B0(n1493), .B1(n1014), .Y(n1503)
);
OAI22X1TS U2184 ( .A0(n1743), .A1(n1626), .B0(n1014), .B1(n1575), .Y(n1617)
);
XNOR2X1TS U2185 ( .A(n2510), .B(n1009), .Y(n2451) );
ADDHX1TS U2186 ( .A(n2420), .B(n2419), .CO(n2416), .S(
DP_OP_453J308_122_681_n405) );
OAI22X1TS U2187 ( .A0(n2500), .A1(n2497), .B0(n2503), .B1(n2413), .Y(n2420)
);
INVX2TS U2188 ( .A(n2538), .Y(DP_OP_453J308_122_681_n420) );
NAND2X1TS U2189 ( .A(n1092), .B(n1093), .Y(n1401) );
INVX2TS U2190 ( .A(n1998), .Y(n1399) );
INVX4TS U2191 ( .A(n2466), .Y(n1006) );
OAI22X1TS U2192 ( .A0(n2353), .A1(n2431), .B0(n2355), .B1(n1423), .Y(n2359)
);
NOR2BX1TS U2193 ( .AN(n952), .B(n2431), .Y(n2372) );
XNOR2X2TS U2194 ( .A(n2297), .B(n2292), .Y(n2296) );
NOR2X1TS U2195 ( .A(FPMULT_Op_MX[19]), .B(n993), .Y(n2292) );
NAND2X1TS U2196 ( .A(n2385), .B(n2377), .Y(n2266) );
NOR2X1TS U2197 ( .A(n915), .B(FPMULT_Op_MX[17]), .Y(n2263) );
XNOR2X1TS U2198 ( .A(n2508), .B(n1006), .Y(n2463) );
OAI22X1TS U2199 ( .A0(n2432), .A1(n2431), .B0(n2430), .B1(n1423), .Y(
DP_OP_453J308_122_681_n449) );
CMPR42X1TS U2200 ( .A(DP_OP_453J308_122_681_n459), .B(
DP_OP_453J308_122_681_n262), .C(DP_OP_453J308_122_681_n255), .D(
DP_OP_453J308_122_681_n259), .ICI(DP_OP_453J308_122_681_n260), .S(
DP_OP_453J308_122_681_n253), .ICO(DP_OP_453J308_122_681_n251), .CO(
DP_OP_453J308_122_681_n252) );
OAI21X1TS U2201 ( .A0(n1465), .A1(n1478), .B0(n1466), .Y(n1293) );
NOR2X1TS U2202 ( .A(n2013), .B(n2011), .Y(n1403) );
NAND2X1TS U2203 ( .A(DP_OP_453J308_122_681_n275), .B(
DP_OP_453J308_122_681_n283), .Y(n2036) );
XNOR2X1TS U2204 ( .A(n2520), .B(n1010), .Y(n2364) );
INVX2TS U2205 ( .A(n2523), .Y(n2355) );
NOR2X1TS U2206 ( .A(n996), .B(n1056), .Y(n1728) );
XNOR2X1TS U2207 ( .A(FPMULT_Op_MY[11]), .B(n990), .Y(n1719) );
XNOR2X1TS U2208 ( .A(FPMULT_Op_MY[10]), .B(n993), .Y(n1738) );
NOR2X1TS U2209 ( .A(n996), .B(n1068), .Y(n1758) );
INVX2TS U2210 ( .A(n1728), .Y(n1704) );
XNOR2X1TS U2211 ( .A(FPMULT_Op_MY[7]), .B(n993), .Y(n1507) );
XNOR2X1TS U2212 ( .A(n2512), .B(n1010), .Y(n2439) );
INVX2TS U2213 ( .A(n2516), .Y(n2429) );
INVX2TS U2214 ( .A(n2495), .Y(n2432) );
XNOR2X1TS U2215 ( .A(n2512), .B(n1009), .Y(n2452) );
XNOR2X1TS U2216 ( .A(n2514), .B(n1009), .Y(n2454) );
INVX2TS U2217 ( .A(n2520), .Y(n2353) );
XNOR2X1TS U2218 ( .A(n2516), .B(n1010), .Y(n2441) );
XNOR2X1TS U2219 ( .A(n2516), .B(n1009), .Y(n2456) );
XNOR2X1TS U2220 ( .A(n2512), .B(n1006), .Y(n2465) );
NAND2X1TS U2221 ( .A(n2314), .B(n2313), .Y(n2315) );
OAI22X1TS U2222 ( .A0(n2312), .A1(n1423), .B0(n2428), .B1(n2431), .Y(n2303)
);
INVX2TS U2223 ( .A(n2253), .Y(n2255) );
XNOR2X1TS U2224 ( .A(FPMULT_Op_MY[11]), .B(n986), .Y(n1501) );
XNOR2X1TS U2225 ( .A(FPMULT_Op_MY[10]), .B(n986), .Y(n1538) );
XNOR2X1TS U2226 ( .A(n2324), .B(n2320), .Y(n2323) );
NAND2X4TS U2227 ( .A(n1383), .B(n2527), .Y(n2526) );
XOR2X1TS U2228 ( .A(n1038), .B(n2321), .Y(n1383) );
OAI22X1TS U2229 ( .A0(n1247), .A1(n1246), .B0(n1245), .B1(n923), .Y(n1251)
);
ADDHX1TS U2230 ( .A(n1226), .B(n1225), .CO(n1262), .S(n1229) );
OAI22X1TS U2231 ( .A0(n1247), .A1(n1227), .B0(n1246), .B1(n923), .Y(n1254)
);
XNOR2X1TS U2232 ( .A(n2245), .B(n2244), .Y(n2249) );
NAND2X1TS U2233 ( .A(n2299), .B(n2291), .Y(n2248) );
INVX2TS U2234 ( .A(n1877), .Y(n1891) );
XNOR2X1TS U2235 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[4]), .Y(n1622) );
XNOR2X1TS U2236 ( .A(FPMULT_Op_MY[7]), .B(n986), .Y(n1629) );
XNOR2X1TS U2237 ( .A(n993), .B(FPMULT_Op_MY[2]), .Y(n1576) );
XOR2X1TS U2238 ( .A(n918), .B(FPMULT_Op_MX[6]), .Y(n1492) );
NOR2X2TS U2239 ( .A(n1921), .B(n1923), .Y(n1912) );
CMPR42X1TS U2240 ( .A(DP_OP_453J308_122_681_n247), .B(
DP_OP_453J308_122_681_n413), .C(FPMULT_Sgf_operation_EVEN1_Q_left[21]),
.D(DP_OP_453J308_122_681_n252), .ICI(DP_OP_453J308_122_681_n248), .S(
DP_OP_453J308_122_681_n244), .ICO(DP_OP_453J308_122_681_n242), .CO(
DP_OP_453J308_122_681_n243) );
INVX2TS U2241 ( .A(n2531), .Y(DP_OP_453J308_122_681_n413) );
INVX2TS U2242 ( .A(n2533), .Y(DP_OP_453J308_122_681_n415) );
CMPR42X1TS U2243 ( .A(DP_OP_453J308_122_681_n416), .B(n2103), .C(n1046), .D(
DP_OP_453J308_122_681_n269), .ICI(DP_OP_453J308_122_681_n273), .S(
DP_OP_453J308_122_681_n266), .ICO(DP_OP_453J308_122_681_n264), .CO(
DP_OP_453J308_122_681_n265) );
INVX2TS U2244 ( .A(n2534), .Y(DP_OP_453J308_122_681_n416) );
INVX2TS U2245 ( .A(n2537), .Y(DP_OP_453J308_122_681_n419) );
INVX2TS U2246 ( .A(n2584), .Y(DP_OP_453J308_122_681_n784) );
INVX2TS U2247 ( .A(n2952), .Y(DP_OP_453J308_122_681_n422) );
NAND2X2TS U2248 ( .A(n1812), .B(n1811), .Y(n1890) );
XNOR2X1TS U2249 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[3]), .Y(n1584) );
XOR2X1TS U2250 ( .A(n987), .B(FPMULT_Op_MX[2]), .Y(n1495) );
XOR2X1TS U2251 ( .A(n915), .B(FPMULT_Op_MX[4]), .Y(n1491) );
NAND2X1TS U2252 ( .A(n1821), .B(n1820), .Y(n1855) );
NOR2X2TS U2253 ( .A(DP_OP_453J308_122_681_n265), .B(
DP_OP_453J308_122_681_n258), .Y(n2063) );
NAND2X1TS U2254 ( .A(n1304), .B(n1430), .Y(n1306) );
NOR2X1TS U2255 ( .A(n1333), .B(n1431), .Y(n1304) );
NOR2X2TS U2256 ( .A(DP_OP_453J308_122_681_n266), .B(
DP_OP_453J308_122_681_n274), .Y(n2058) );
NAND2X1TS U2257 ( .A(n2037), .B(n2036), .Y(n2038) );
INVX2TS U2258 ( .A(n2035), .Y(n2037) );
INVX2TS U2259 ( .A(n2555), .Y(n2562) );
INVX2TS U2260 ( .A(n2411), .Y(n2362) );
XNOR2X1TS U2261 ( .A(FPMULT_Op_MY[9]), .B(n993), .Y(n1720) );
NOR2X1TS U2262 ( .A(n996), .B(n1064), .Y(n1705) );
XNOR2X1TS U2263 ( .A(FPMULT_Op_MY[8]), .B(n993), .Y(n1698) );
XNOR2X1TS U2264 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[3]), .Y(n1508) );
XNOR2X1TS U2265 ( .A(n2504), .B(n1006), .Y(n2461) );
INVX2TS U2266 ( .A(n2514), .Y(n2312) );
XNOR2X1TS U2267 ( .A(n2510), .B(n1006), .Y(n2464) );
XNOR2X1TS U2268 ( .A(n2504), .B(n1004), .Y(n2474) );
INVX2TS U2269 ( .A(n2498), .Y(n2430) );
XNOR2X1TS U2270 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[15]), .Y(n1117) );
XNOR2X1TS U2271 ( .A(n992), .B(FPMULT_Op_MX[19]), .Y(n1135) );
XNOR2X1TS U2272 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MY[15]), .Y(n1136) );
NAND2X1TS U2273 ( .A(n2350), .B(n2349), .Y(n2351) );
NAND2X1TS U2274 ( .A(n2338), .B(n2337), .Y(n2339) );
NAND2X1TS U2275 ( .A(n2288), .B(n2287), .Y(n2289) );
INVX2TS U2276 ( .A(n2286), .Y(n2288) );
NAND2X1TS U2277 ( .A(n2342), .B(n2341), .Y(n2343) );
INVX4TS U2278 ( .A(n2453), .Y(n1009) );
NAND2X1TS U2279 ( .A(n2309), .B(n2308), .Y(n2310) );
NAND2X1TS U2280 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2328) );
XNOR2X1TS U2281 ( .A(FPMULT_Op_MX[20]), .B(n992), .Y(n1121) );
XNOR2X1TS U2282 ( .A(FPMULT_Op_MX[21]), .B(n992), .Y(n1125) );
XNOR2X1TS U2283 ( .A(n992), .B(FPMULT_Op_MX[22]), .Y(n1309) );
XNOR2X1TS U2284 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[15]), .Y(n1189) );
XNOR2X1TS U2285 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[16]), .Y(n1160) );
XNOR2X1TS U2286 ( .A(n992), .B(FPMULT_Op_MX[18]), .Y(n1158) );
XNOR2X1TS U2287 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[18]), .Y(n1193) );
XNOR2X1TS U2288 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[17]), .Y(n1248) );
XNOR2X1TS U2289 ( .A(n992), .B(FPMULT_Op_MX[15]), .Y(n1242) );
XNOR2X1TS U2290 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[14]), .Y(n1243) );
XNOR2X1TS U2291 ( .A(n2510), .B(n1010), .Y(n2437) );
XNOR2X1TS U2292 ( .A(n2508), .B(n1010), .Y(n2438) );
XNOR2X1TS U2293 ( .A(n2508), .B(n1009), .Y(n2450) );
XNOR2X1TS U2294 ( .A(n2506), .B(n1009), .Y(n2449) );
XNOR2X1TS U2295 ( .A(n2506), .B(n1004), .Y(n2475) );
XNOR2X1TS U2296 ( .A(n2510), .B(n1004), .Y(n2477) );
XNOR2X1TS U2297 ( .A(n2504), .B(n1001), .Y(n2489) );
XNOR2X1TS U2298 ( .A(n2506), .B(n1001), .Y(n2490) );
XNOR2X1TS U2299 ( .A(n2508), .B(n1004), .Y(n2476) );
XNOR2X1TS U2300 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[17]), .Y(n1143) );
OAI22X1TS U2301 ( .A0(n1247), .A1(n1154), .B0(n923), .B1(n946), .Y(n1142) );
XNOR2X1TS U2302 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[19]), .Y(n1127) );
XNOR2X1TS U2303 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[18]), .Y(n1128) );
XOR2X1TS U2304 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[19]), .Y(n2298) );
INVX2TS U2305 ( .A(n1773), .Y(n1763) );
OAI22X1TS U2306 ( .A0(n1767), .A1(n1759), .B0(n1020), .B1(n1031), .Y(n1762)
);
XNOR2X1TS U2307 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MX[3]), .Y(n1497) );
XNOR2X1TS U2308 ( .A(FPMULT_Op_MY[9]), .B(n986), .Y(n1555) );
XNOR2X1TS U2309 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MX[3]), .Y(n1537) );
XNOR2X1TS U2310 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MX[3]), .Y(n1518) );
XOR2X1TS U2311 ( .A(n2326), .B(n2380), .Y(n2327) );
XOR2X1TS U2312 ( .A(n986), .B(FPMULT_Op_MX[2]), .Y(n2325) );
XOR2X1TS U2313 ( .A(n2386), .B(n2385), .Y(n2387) );
NOR2X1TS U2314 ( .A(n2384), .B(n2383), .Y(n2386) );
XOR2X1TS U2315 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[4]), .Y(n2384) );
XOR2X1TS U2316 ( .A(FPMULT_Op_MY[18]), .B(n988), .Y(n1115) );
XNOR2X1TS U2317 ( .A(n917), .B(FPMULT_Op_MX[13]), .Y(n1224) );
XNOR2X1TS U2318 ( .A(n917), .B(FPMULT_Op_MX[14]), .Y(n1238) );
XOR2X1TS U2319 ( .A(n992), .B(FPMULT_Op_MY[16]), .Y(n1119) );
CMPR42X1TS U2320 ( .A(DP_OP_453J308_122_681_n488), .B(
DP_OP_453J308_122_681_n288), .C(DP_OP_453J308_122_681_n281), .D(
DP_OP_453J308_122_681_n289), .ICI(DP_OP_453J308_122_681_n285), .S(
DP_OP_453J308_122_681_n278), .ICO(DP_OP_453J308_122_681_n276), .CO(
DP_OP_453J308_122_681_n277) );
XOR2X1TS U2321 ( .A(n989), .B(FPMULT_Op_MY[14]), .Y(n1116) );
NAND2X1TS U2322 ( .A(n1418), .B(n2278), .Y(n1420) );
AOI21X1TS U2323 ( .A0(n1418), .A1(n2280), .B0(n1417), .Y(n1419) );
NOR2X1TS U2324 ( .A(n2282), .B(n2286), .Y(n1418) );
NAND2X1TS U2325 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n1421) );
INVX2TS U2326 ( .A(n1933), .Y(n1922) );
INVX2TS U2327 ( .A(n1921), .Y(n1934) );
INVX2TS U2328 ( .A(n1886), .Y(n1889) );
XNOR2X1TS U2329 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[5]), .Y(n1624) );
XNOR2X1TS U2330 ( .A(FPMULT_Op_MY[8]), .B(n986), .Y(n1625) );
XNOR2X1TS U2331 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[6]), .Y(n1623) );
XNOR2X1TS U2332 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[3]), .Y(n1560) );
NOR2BX1TS U2333 ( .AN(n983), .B(n996), .Y(n1504) );
OAI22X1TS U2334 ( .A0(n1631), .A1(n1538), .B0(n1501), .B1(n1628), .Y(n1526)
);
INVX2TS U2335 ( .A(n2530), .Y(DP_OP_453J308_122_681_n412) );
INVX2TS U2336 ( .A(n2532), .Y(DP_OP_453J308_122_681_n414) );
INVX2TS U2337 ( .A(n2536), .Y(DP_OP_453J308_122_681_n418) );
INVX2TS U2338 ( .A(n1849), .Y(n1852) );
INVX2TS U2339 ( .A(n1850), .Y(n1851) );
XOR2X1TS U2340 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[22]), .Y(n2242) );
CMPR42X1TS U2341 ( .A(DP_OP_453J308_122_681_n235), .B(
DP_OP_453J308_122_681_n240), .C(DP_OP_453J308_122_681_n411), .D(
FPMULT_Sgf_operation_EVEN1_Q_left[23]), .ICI(
DP_OP_453J308_122_681_n236), .S(DP_OP_453J308_122_681_n233), .ICO(
DP_OP_453J308_122_681_n231), .CO(DP_OP_453J308_122_681_n232) );
INVX2TS U2342 ( .A(n2529), .Y(DP_OP_453J308_122_681_n411) );
NAND2X4TS U2343 ( .A(n2241), .B(n949), .Y(n1423) );
NAND2X1TS U2344 ( .A(n1814), .B(n1813), .Y(n1880) );
NOR2X2TS U2345 ( .A(n1808), .B(n1807), .Y(n1901) );
NAND2X1TS U2346 ( .A(n1808), .B(n1807), .Y(n1902) );
XNOR2X1TS U2347 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MY[2]), .Y(n1590) );
OAI22X1TS U2348 ( .A0(n1631), .A1(n1630), .B0(n1629), .B1(n1628), .Y(n1632)
);
NAND2X1TS U2349 ( .A(n1915), .B(n1914), .Y(n1916) );
INVX2TS U2350 ( .A(n1913), .Y(n1915) );
INVX2TS U2351 ( .A(n1874), .Y(n1394) );
OAI21X2TS U2352 ( .A0(n2163), .A1(n2167), .B0(n2168), .Y(n2219) );
OAI21X1TS U2353 ( .A0(n2180), .A1(n2175), .B0(n2181), .Y(n2137) );
NOR2X2TS U2354 ( .A(n2140), .B(n2139), .Y(n2164) );
INVX2TS U2355 ( .A(n2222), .Y(n2158) );
INVX2TS U2356 ( .A(n2215), .Y(n2159) );
NOR2X2TS U2357 ( .A(n1302), .B(n1301), .Y(n1333) );
NAND2X1TS U2358 ( .A(n1860), .B(n1859), .Y(n1861) );
INVX2TS U2359 ( .A(n1858), .Y(n1860) );
NAND2X2TS U2360 ( .A(n2172), .B(n2138), .Y(n2215) );
INVX2TS U2361 ( .A(n2214), .Y(n2144) );
INVX2TS U2362 ( .A(n2219), .Y(n2143) );
NAND2X1TS U2363 ( .A(n1091), .B(n1874), .Y(n1875) );
CLKXOR2X2TS U2364 ( .A(n1871), .B(n1870), .Y(n2531) );
NAND2X1TS U2365 ( .A(n1060), .B(n1869), .Y(n1870) );
INVX2TS U2366 ( .A(n2557), .Y(n1650) );
NOR2X2TS U2367 ( .A(DP_OP_453J308_122_681_n350), .B(
DP_OP_453J308_122_681_n358), .Y(n1858) );
INVX2TS U2368 ( .A(n1834), .Y(n1829) );
OAI22X1TS U2369 ( .A0(n1831), .A1(n1797), .B0(n1016), .B1(n996), .Y(n1828)
);
INVX2TS U2370 ( .A(n1855), .Y(n1822) );
AOI21X1TS U2371 ( .A0(n2219), .A1(n1054), .B0(n2218), .Y(n2189) );
NAND2X1TS U2372 ( .A(n1092), .B(n1998), .Y(n1999) );
NAND2X1TS U2373 ( .A(n2015), .B(n2014), .Y(n2016) );
INVX2TS U2374 ( .A(n2013), .Y(n2015) );
NAND2X1TS U2375 ( .A(n2065), .B(n2064), .Y(n2066) );
INVX2TS U2376 ( .A(n2063), .Y(n2065) );
NOR2X2TS U2377 ( .A(n2142), .B(n2141), .Y(n2167) );
NAND2X1TS U2378 ( .A(n1373), .B(n2175), .Y(n1374) );
INVX2TS U2379 ( .A(n2176), .Y(n1373) );
INVX2TS U2380 ( .A(n1353), .Y(n1439) );
INVX2TS U2381 ( .A(n1465), .Y(n1467) );
INVX2TS U2382 ( .A(n2058), .Y(n2047) );
NAND2X1TS U2383 ( .A(n1433), .B(n1432), .Y(n1434) );
XOR2X1TS U2384 ( .A(n2559), .B(n2558), .Y(n2751) );
AOI21X2TS U2385 ( .A0(n2661), .A1(n1039), .B0(n1993), .Y(n1994) );
INVX2TS U2386 ( .A(n2663), .Y(n1993) );
INVX2TS U2387 ( .A(n2608), .Y(n2612) );
INVX2TS U2388 ( .A(n2626), .Y(n2075) );
NAND2X2TS U2389 ( .A(n2031), .B(n2591), .Y(n2646) );
NOR2X4TS U2390 ( .A(n2099), .B(n2583), .Y(n2608) );
AOI22X1TS U2391 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n3695), .B0(n3020), .B1(
n3019), .Y(n3025) );
XOR2X1TS U2392 ( .A(n2573), .B(n2572), .Y(n2760) );
XOR2X1TS U2393 ( .A(n2578), .B(n2577), .Y(n2770) );
XNOR2X1TS U2394 ( .A(n2523), .B(n1010), .Y(n2369) );
NAND2X1TS U2395 ( .A(n2273), .B(n2272), .Y(n2293) );
NAND2X1TS U2396 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .Y(n2272) );
XNOR2X1TS U2397 ( .A(FPMULT_Op_MY[10]), .B(n990), .Y(n1706) );
INVX2TS U2398 ( .A(n1412), .Y(n1413) );
NOR2X1TS U2399 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2348) );
NAND2X1TS U2400 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2349) );
INVX2TS U2401 ( .A(n2330), .Y(n2340) );
INVX2TS U2402 ( .A(n2280), .Y(n2283) );
NOR2X1TS U2403 ( .A(n2279), .B(n2282), .Y(n2285) );
INVX2TS U2404 ( .A(n2341), .Y(n2306) );
INVX2TS U2405 ( .A(n2305), .Y(n2342) );
INVX2TS U2406 ( .A(n2274), .Y(n2344) );
XNOR2X1TS U2407 ( .A(n1009), .B(n2523), .Y(n2457) );
XNOR2X1TS U2408 ( .A(n1009), .B(n2411), .Y(n2459) );
XNOR2X2TS U2409 ( .A(FPMULT_Op_MX[19]), .B(n918), .Y(n2294) );
XNOR2X1TS U2410 ( .A(n2514), .B(n1010), .Y(n2440) );
XNOR2X1TS U2411 ( .A(n2514), .B(n1006), .Y(n2467) );
OAI22X1TS U2412 ( .A0(n2355), .A1(n2431), .B0(n1423), .B1(n2362), .Y(n2361)
);
XNOR2X1TS U2413 ( .A(n2495), .B(n1006), .Y(n2468) );
XNOR2X1TS U2414 ( .A(n2512), .B(n1004), .Y(n2478) );
XNOR2X1TS U2415 ( .A(n2516), .B(n1006), .Y(n2469) );
INVX2TS U2416 ( .A(n2251), .Y(n2314) );
INVX2TS U2417 ( .A(n2313), .Y(n2252) );
NAND2X1TS U2418 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .Y(n2287) );
NOR2X2TS U2419 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .Y(n2331) );
OAI21X2TS U2420 ( .A0(n2352), .A1(n2348), .B0(n2349), .Y(n2330) );
NOR2X2TS U2421 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[15]), .Y(n2336) );
NAND2X1TS U2422 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .Y(n2332) );
NAND2X1TS U2423 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2308) );
NOR2X2TS U2424 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2307) );
INVX2TS U2425 ( .A(n1758), .Y(n1741) );
OAI22X1TS U2426 ( .A0(n1743), .A1(n1719), .B0(n1014), .B1(n1032), .Y(n1740)
);
XNOR2X1TS U2427 ( .A(n1010), .B(n2411), .Y(n2443) );
XNOR2X1TS U2428 ( .A(n2514), .B(n1004), .Y(n2479) );
ADDHX1TS U2429 ( .A(n2403), .B(n2402), .CO(n2399), .S(
DP_OP_453J308_122_681_n382) );
OAI22X1TS U2430 ( .A0(n2470), .A1(n2396), .B0(n2473), .B1(n2395), .Y(n2403)
);
CLKAND2X2TS U2431 ( .A(FPMULT_Op_MX[0]), .B(n984), .Y(n1043) );
XNOR2X2TS U2432 ( .A(n914), .B(FPMULT_Op_MX[13]), .Y(n2321) );
XNOR2X1TS U2433 ( .A(n2520), .B(n1006), .Y(n2471) );
XNOR2X1TS U2434 ( .A(n2498), .B(n1006), .Y(n2472) );
OAI22X1TS U2435 ( .A0(n1700), .A1(n1508), .B0(n1008), .B1(n1033), .Y(n1696)
);
XNOR2X1TS U2436 ( .A(n2504), .B(n1009), .Y(n2448) );
INVX2TS U2437 ( .A(n2512), .Y(n2428) );
OAI22X1TS U2438 ( .A0(n2429), .A1(n1423), .B0(n2312), .B1(n2431), .Y(n2319)
);
OAI22X1TS U2439 ( .A0(n2461), .A1(n2470), .B0(n1000), .B1(n2398), .Y(n2318)
);
XNOR2X1TS U2440 ( .A(n989), .B(FPMULT_Op_MX[15]), .Y(n1228) );
XNOR2X1TS U2441 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[16]), .Y(n1249) );
XNOR2X1TS U2442 ( .A(n2506), .B(n1006), .Y(n2462) );
CMPR42X1TS U2443 ( .A(DP_OP_453J308_122_681_n500), .B(
DP_OP_453J308_122_681_n448), .C(DP_OP_453J308_122_681_n461), .D(
DP_OP_453J308_122_681_n487), .ICI(DP_OP_453J308_122_681_n474), .S(
DP_OP_453J308_122_681_n272), .ICO(DP_OP_453J308_122_681_n270), .CO(
DP_OP_453J308_122_681_n271) );
OAI22X1TS U2444 ( .A0(n2429), .A1(n2431), .B0(n2432), .B1(n1423), .Y(
DP_OP_453J308_122_681_n448) );
CMPR42X1TS U2445 ( .A(DP_OP_453J308_122_681_n516), .B(
DP_OP_453J308_122_681_n490), .C(DP_OP_453J308_122_681_n477), .D(
DP_OP_453J308_122_681_n303), .ICI(DP_OP_453J308_122_681_n310), .S(
DP_OP_453J308_122_681_n301), .ICO(DP_OP_453J308_122_681_n299), .CO(
DP_OP_453J308_122_681_n300) );
CMPR42X1TS U2446 ( .A(DP_OP_453J308_122_681_n476), .B(
DP_OP_453J308_122_681_n302), .C(DP_OP_453J308_122_681_n502), .D(
DP_OP_453J308_122_681_n489), .ICI(DP_OP_453J308_122_681_n299), .S(
DP_OP_453J308_122_681_n290), .ICO(DP_OP_453J308_122_681_n288), .CO(
DP_OP_453J308_122_681_n289) );
OAI22X1TS U2447 ( .A0(n2430), .A1(n2431), .B0(n2353), .B1(n1423), .Y(n2346)
);
AO21XLTS U2448 ( .A0(n2500), .A1(n997), .B0(n2497), .Y(n2347) );
XNOR2X1TS U2449 ( .A(n2508), .B(n1001), .Y(n2491) );
OAI22X1TS U2450 ( .A0(n1136), .A1(n1317), .B0(n1117), .B1(n1013), .Y(n1139)
);
OAI22X1TS U2451 ( .A0(n1136), .A1(n1013), .B0(n1317), .B1(n1153), .Y(n1156)
);
NAND2X1TS U2452 ( .A(n2247), .B(n2246), .Y(n2291) );
NAND2X1TS U2453 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[8]), .Y(n2246) );
INVX2TS U2454 ( .A(n2424), .Y(n2504) );
XNOR2X1TS U2455 ( .A(n2506), .B(n1010), .Y(n2436) );
INVX2TS U2456 ( .A(n2510), .Y(n2427) );
NAND2X1TS U2457 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n2254) );
NOR2X2TS U2458 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .Y(n2286) );
AOI21X2TS U2459 ( .A0(n2330), .A1(n1416), .B0(n1415), .Y(n2274) );
OAI21X1TS U2460 ( .A0(n2331), .A1(n2337), .B0(n2332), .Y(n1415) );
NOR2X1TS U2461 ( .A(n2331), .B(n2336), .Y(n1416) );
OAI21X2TS U2462 ( .A0(n2307), .A1(n2341), .B0(n2308), .Y(n2280) );
NOR2X2TS U2463 ( .A(n2307), .B(n2305), .Y(n2278) );
OAI22X1TS U2464 ( .A0(n1783), .A1(n1765), .B0(n1775), .B1(n1022), .Y(n1777)
);
CMPR42X1TS U2465 ( .A(DP_OP_453J308_122_681_n499), .B(
DP_OP_453J308_122_681_n512), .C(DP_OP_453J308_122_681_n394), .D(
DP_OP_453J308_122_681_n525), .ICI(DP_OP_453J308_122_681_n392), .S(
DP_OP_453J308_122_681_n388), .ICO(DP_OP_453J308_122_681_n386), .CO(
DP_OP_453J308_122_681_n387) );
OAI22X1TS U2466 ( .A0(n1831), .A1(n1744), .B0(n1760), .B1(n1016), .Y(n1750)
);
OAI22X1TS U2467 ( .A0(n1783), .A1(n1725), .B0(n1745), .B1(n1022), .Y(n1733)
);
XNOR2X1TS U2468 ( .A(n993), .B(FPMULT_Op_MY[6]), .Y(n1494) );
XNOR2X1TS U2469 ( .A(n2512), .B(n1001), .Y(n2493) );
XNOR2X1TS U2470 ( .A(n2510), .B(n1001), .Y(n2492) );
INVX2TS U2471 ( .A(n1799), .Y(n1787) );
OAI22X1TS U2472 ( .A0(n1831), .A1(n1774), .B0(n1016), .B1(n1784), .Y(n1786)
);
XNOR2X1TS U2473 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[22]), .Y(n1367) );
OAI22X1TS U2474 ( .A0(n1365), .A1(n992), .B0(n1018), .B1(
DP_OP_453J308_122_681_n2086), .Y(n1363) );
OAI22X1TS U2475 ( .A0(n1125), .A1(n1018), .B0(n1365), .B1(n1121), .Y(n1123)
);
OAI22X1TS U2476 ( .A0(n1125), .A1(n1365), .B0(n1309), .B1(n1018), .Y(n1314)
);
XNOR2X1TS U2477 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[20]), .Y(n1307) );
XNOR2X1TS U2478 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MY[19]), .Y(n1348) );
OAI22X1TS U2479 ( .A0(n2151), .A1(n1177), .B0(n1023), .B1(n1176), .Y(n1272)
);
OAI22X1TS U2480 ( .A0(n2151), .A1(n1176), .B0(n1023), .B1(n1159), .Y(n1187)
);
OAI22X1TS U2481 ( .A0(n1171), .A1(n923), .B0(n1247), .B1(n1192), .Y(n1190)
);
OAI22X1TS U2482 ( .A0(n1171), .A1(n1247), .B0(n1154), .B1(n923), .Y(n1172)
);
CMPR42X1TS U2483 ( .A(DP_OP_453J308_122_681_n445), .B(
DP_OP_453J308_122_681_n471), .C(DP_OP_453J308_122_681_n458), .D(
DP_OP_453J308_122_681_n254), .ICI(DP_OP_453J308_122_681_n251), .S(
DP_OP_453J308_122_681_n247), .ICO(DP_OP_453J308_122_681_n245), .CO(
DP_OP_453J308_122_681_n246) );
OAI22X1TS U2484 ( .A0(n2428), .A1(n1423), .B0(n2427), .B1(n2431), .Y(
DP_OP_453J308_122_681_n445) );
OAI22X1TS U2485 ( .A0(n2124), .A1(n1239), .B0(n1025), .B1(n1244), .Y(n1256)
);
OAI22X1TS U2486 ( .A0(n1247), .A1(n1245), .B0(n1192), .B1(n923), .Y(n1237)
);
OAI22X1TS U2487 ( .A0(n2124), .A1(n1244), .B0(n1025), .B1(n1243), .Y(n1275)
);
CMPR42X1TS U2488 ( .A(DP_OP_453J308_122_681_n473), .B(
DP_OP_453J308_122_681_n270), .C(DP_OP_453J308_122_681_n263), .D(
DP_OP_453J308_122_681_n271), .ICI(DP_OP_453J308_122_681_n267), .S(
DP_OP_453J308_122_681_n261), .ICO(DP_OP_453J308_122_681_n259), .CO(
DP_OP_453J308_122_681_n260) );
CMPR42X1TS U2489 ( .A(DP_OP_453J308_122_681_n279), .B(
DP_OP_453J308_122_681_n280), .C(DP_OP_453J308_122_681_n272), .D(
DP_OP_453J308_122_681_n276), .ICI(DP_OP_453J308_122_681_n277), .S(
DP_OP_453J308_122_681_n269), .ICO(DP_OP_453J308_122_681_n267), .CO(
DP_OP_453J308_122_681_n268) );
CMPR42X1TS U2490 ( .A(DP_OP_453J308_122_681_n292), .B(
DP_OP_453J308_122_681_n300), .C(DP_OP_453J308_122_681_n290), .D(
DP_OP_453J308_122_681_n296), .ICI(n2606), .S(
DP_OP_453J308_122_681_n287), .ICO(DP_OP_453J308_122_681_n285), .CO(
DP_OP_453J308_122_681_n286) );
CMPR42X1TS U2491 ( .A(DP_OP_453J308_122_681_n517), .B(
DP_OP_453J308_122_681_n504), .C(DP_OP_453J308_122_681_n322), .D(
DP_OP_453J308_122_681_n312), .ICI(DP_OP_453J308_122_681_n318), .S(
DP_OP_453J308_122_681_n309), .ICO(DP_OP_453J308_122_681_n307), .CO(
DP_OP_453J308_122_681_n308) );
OAI22X1TS U2492 ( .A0(n2509), .A1(n2526), .B0(n2507), .B1(n2527), .Y(
DP_OP_453J308_122_681_n532) );
XNOR2X1TS U2493 ( .A(n2504), .B(n1010), .Y(n2435) );
INVX2TS U2494 ( .A(n2508), .Y(n2426) );
CMPR42X1TS U2495 ( .A(DP_OP_453J308_122_681_n470), .B(
DP_OP_453J308_122_681_n444), .C(DP_OP_453J308_122_681_n457), .D(
DP_OP_453J308_122_681_n245), .ICI(DP_OP_453J308_122_681_n246), .S(
DP_OP_453J308_122_681_n241), .ICO(DP_OP_453J308_122_681_n239), .CO(
DP_OP_453J308_122_681_n240) );
OAI22X1TS U2496 ( .A0(n2426), .A1(n2431), .B0(n2427), .B1(n1423), .Y(
DP_OP_453J308_122_681_n444) );
OAI21X1TS U2497 ( .A0(n2253), .A1(n2313), .B0(n2254), .Y(n2258) );
CMPR42X1TS U2498 ( .A(DP_OP_453J308_122_681_n399), .B(
DP_OP_453J308_122_681_n393), .C(DP_OP_453J308_122_681_n396), .D(
DP_OP_453J308_122_681_n791), .ICI(DP_OP_453J308_122_681_n429), .S(
DP_OP_453J308_122_681_n391), .ICO(DP_OP_453J308_122_681_n389), .CO(
DP_OP_453J308_122_681_n390) );
XNOR2X1TS U2499 ( .A(n990), .B(FPMULT_Op_MY[2]), .Y(n1627) );
NAND2X1TS U2500 ( .A(DP_OP_453J308_122_681_n391), .B(
DP_OP_453J308_122_681_n397), .Y(n1918) );
OAI22X1TS U2501 ( .A0(n1631), .A1(n1501), .B0(n1034), .B1(n1628), .Y(n1521)
);
OAI22X1TS U2502 ( .A0(n1631), .A1(n1555), .B0(n1538), .B1(n1628), .Y(n1556)
);
OAI22X1TS U2503 ( .A0(n1700), .A1(n1560), .B0(n1537), .B1(n1007), .Y(n1557)
);
OAI22X1TS U2504 ( .A0(n1700), .A1(n1537), .B0(n1518), .B1(n1008), .Y(n1543)
);
CMPR42X1TS U2505 ( .A(DP_OP_453J308_122_681_n529), .B(
DP_OP_453J308_122_681_n542), .C(DP_OP_453J308_122_681_n795), .D(
DP_OP_453J308_122_681_n794), .ICI(DP_OP_453J308_122_681_n409), .S(
DP_OP_453J308_122_681_n408), .ICO(DP_OP_453J308_122_681_n406), .CO(
DP_OP_453J308_122_681_n407) );
CMPR42X1TS U2506 ( .A(DP_OP_453J308_122_681_n379), .B(
DP_OP_453J308_122_681_n372), .C(DP_OP_453J308_122_681_n375), .D(
DP_OP_453J308_122_681_n426), .ICI(DP_OP_453J308_122_681_n788), .S(
DP_OP_453J308_122_681_n369), .ICO(DP_OP_453J308_122_681_n367), .CO(
DP_OP_453J308_122_681_n368) );
CMPR42X1TS U2507 ( .A(DP_OP_453J308_122_681_n363), .B(
DP_OP_453J308_122_681_n508), .C(DP_OP_453J308_122_681_n534), .D(
DP_OP_453J308_122_681_n360), .ICI(DP_OP_453J308_122_681_n356), .S(
DP_OP_453J308_122_681_n353), .ICO(DP_OP_453J308_122_681_n351), .CO(
DP_OP_453J308_122_681_n352) );
OAI22X1TS U2508 ( .A0(n2511), .A1(n2527), .B0(n2513), .B1(n2526), .Y(
DP_OP_453J308_122_681_n534) );
INVX2TS U2509 ( .A(n1894), .Y(n1393) );
INVX2TS U2510 ( .A(n1880), .Y(n1863) );
NAND2X1TS U2511 ( .A(n1061), .B(n1060), .Y(n1819) );
NAND2BXLTS U2512 ( .AN(n984), .B(n946), .Y(n1112) );
OAI22X1TS U2513 ( .A0(n2229), .A1(FPMULT_Op_MX[19]), .B0(n1011), .B1(
FPMULT_Op_MX[20]), .Y(n2121) );
OAI22X1TS U2514 ( .A0(n2229), .A1(FPMULT_Op_MX[21]), .B0(n1011), .B1(
FPMULT_Op_MX[22]), .Y(n2153) );
OAI22X1TS U2515 ( .A0(n2151), .A1(n1366), .B0(n2113), .B1(n1024), .Y(n2110)
);
OAI22X1TS U2516 ( .A0(n2124), .A1(n1348), .B0(n1026), .B1(n1367), .Y(n1360)
);
OAI21X1TS U2517 ( .A0(n1333), .A1(n1432), .B0(n1334), .Y(n1303) );
OAI2BB1X1TS U2518 ( .A0N(n1194), .A1N(n1195), .B0(n1179), .Y(n1184) );
OAI21X2TS U2519 ( .A0(n1485), .A1(n1270), .B0(n1269), .Y(n1464) );
AOI21X1TS U2520 ( .A0(n1096), .A1(n1486), .B0(n1268), .Y(n1269) );
NAND2X1TS U2521 ( .A(n1096), .B(n1097), .Y(n1270) );
INVX2TS U2522 ( .A(n1487), .Y(n1268) );
ADDFX2TS U2523 ( .A(n1285), .B(n1284), .CI(n1283), .CO(n1295), .S(n1292) );
XNOR2X1TS U2524 ( .A(n1197), .B(n1196), .Y(n1283) );
XNOR2X1TS U2525 ( .A(n1195), .B(n1194), .Y(n1196) );
AOI21X2TS U2526 ( .A0(n2052), .A1(n1098), .B0(n1234), .Y(n1485) );
INVX2TS U2527 ( .A(n2050), .Y(n1234) );
OAI22X1TS U2528 ( .A0(n1365), .A1(DP_OP_453J308_122_681_n2086), .B0(n1017),
.B1(n1216), .Y(n1230) );
NAND2BXLTS U2529 ( .AN(n984), .B(n917), .Y(n1216) );
INVX2TS U2530 ( .A(n2535), .Y(DP_OP_453J308_122_681_n417) );
OAI22X1TS U2531 ( .A0(n1247), .A1(n1208), .B0(n1217), .B1(n923), .Y(n1220)
);
CMPR42X1TS U2532 ( .A(DP_OP_453J308_122_681_n330), .B(
DP_OP_453J308_122_681_n421), .C(DP_OP_453J308_122_681_n783), .D(
DP_OP_453J308_122_681_n320), .ICI(DP_OP_453J308_122_681_n326), .S(
DP_OP_453J308_122_681_n317), .ICO(DP_OP_453J308_122_681_n315), .CO(
DP_OP_453J308_122_681_n316) );
INVX2TS U2533 ( .A(n2583), .Y(DP_OP_453J308_122_681_n783) );
INVX2TS U2534 ( .A(n2539), .Y(DP_OP_453J308_122_681_n421) );
AOI21X1TS U2535 ( .A0(n1398), .A1(n1840), .B0(n1397), .Y(n1846) );
NOR2X2TS U2536 ( .A(n2164), .B(n2167), .Y(n2214) );
NAND2X1TS U2537 ( .A(n2214), .B(n1029), .Y(n2221) );
NOR2X1TS U2538 ( .A(n1296), .B(n1295), .Y(n1454) );
INVX2TS U2539 ( .A(n2506), .Y(n2425) );
OAI22X1TS U2540 ( .A0(n2426), .A1(n1423), .B0(n2425), .B1(n2431), .Y(n2261)
);
NAND2X1TS U2541 ( .A(DP_OP_453J308_122_681_n359), .B(
DP_OP_453J308_122_681_n368), .Y(n1874) );
INVX2TS U2542 ( .A(n1883), .Y(n1873) );
NAND2X1TS U2543 ( .A(n1816), .B(n1815), .Y(n1869) );
NAND2X1TS U2544 ( .A(n1891), .B(n1061), .Y(n1866) );
AOI21X1TS U2545 ( .A0(n1061), .A1(n1864), .B0(n1863), .Y(n1865) );
INVX2TS U2546 ( .A(n1890), .Y(n1864) );
NAND2BXLTS U2547 ( .AN(n982), .B(FPMULT_Op_MX[3]), .Y(n1595) );
NAND2X1TS U2548 ( .A(DP_OP_453J308_122_681_n369), .B(
DP_OP_453J308_122_681_n376), .Y(n1883) );
INVX2TS U2549 ( .A(n1872), .Y(n1884) );
CLKXOR2X2TS U2550 ( .A(n1927), .B(n1926), .Y(n2536) );
NAND2X1TS U2551 ( .A(n1925), .B(n1924), .Y(n1926) );
INVX2TS U2552 ( .A(n1923), .Y(n1925) );
XOR2X1TS U2553 ( .A(n1932), .B(n1931), .Y(n1980) );
NAND2X1TS U2554 ( .A(n1930), .B(n1929), .Y(n1932) );
XNOR2X1TS U2555 ( .A(n1939), .B(n1938), .Y(n1979) );
NAND2X1TS U2556 ( .A(n1934), .B(n1933), .Y(n1935) );
XNOR2X1TS U2557 ( .A(n1896), .B(n1895), .Y(n1985) );
CLKXOR2X2TS U2558 ( .A(n1893), .B(n1892), .Y(n2533) );
INVX2TS U2559 ( .A(n1887), .Y(n1888) );
OAI22X1TS U2560 ( .A0(n1767), .A1(n1031), .B0(n1020), .B1(n1621), .Y(n1638)
);
OAI22X1TS U2561 ( .A0(n1631), .A1(n1629), .B0(n1625), .B1(n1628), .Y(n1657)
);
OAI22X1TS U2562 ( .A0(n1700), .A1(n1623), .B0(n1560), .B1(n1007), .Y(n1660)
);
NAND2BXLTS U2563 ( .AN(n983), .B(n991), .Y(n1572) );
OAI22X1TS U2564 ( .A0(n1767), .A1(n1559), .B0(n1019), .B1(n1540), .Y(n1570)
);
OAI22X1TS U2565 ( .A0(n1783), .A1(n1541), .B0(n1525), .B1(n1022), .Y(n1552)
);
NAND2X1TS U2566 ( .A(n982), .B(FPMULT_Op_MY[12]), .Y(n1384) );
NAND2X1TS U2567 ( .A(n1682), .B(n1681), .Y(n1957) );
INVX2TS U2568 ( .A(n1954), .Y(n1942) );
INVX2TS U2569 ( .A(n1955), .Y(n1941) );
NAND2X1TS U2570 ( .A(n1684), .B(n1683), .Y(n1946) );
NOR2X1TS U2571 ( .A(DP_OP_453J308_122_681_n408), .B(n1390), .Y(n1950) );
NAND2X1TS U2572 ( .A(DP_OP_453J308_122_681_n408), .B(n1390), .Y(n1951) );
NAND3XLTS U2573 ( .A(n3814), .B(n3242), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3243) );
CMPR42X1TS U2574 ( .A(DP_OP_453J308_122_681_n371), .B(
DP_OP_453J308_122_681_n362), .C(DP_OP_453J308_122_681_n425), .D(
DP_OP_453J308_122_681_n787), .ICI(DP_OP_453J308_122_681_n367), .S(
DP_OP_453J308_122_681_n359), .ICO(DP_OP_453J308_122_681_n357), .CO(
DP_OP_453J308_122_681_n358) );
INVX2TS U2575 ( .A(n2586), .Y(DP_OP_453J308_122_681_n787) );
INVX2TS U2576 ( .A(n2717), .Y(DP_OP_453J308_122_681_n425) );
NOR2X1TS U2577 ( .A(n996), .B(DP_OP_453J308_122_681_n1586), .Y(n1834) );
AOI21X1TS U2578 ( .A0(n1863), .A1(n1060), .B0(n1817), .Y(n1818) );
INVX2TS U2579 ( .A(n1869), .Y(n1817) );
NAND2X1TS U2580 ( .A(n1849), .B(n1059), .Y(n1824) );
NOR2X2TS U2581 ( .A(n1684), .B(n1683), .Y(n1945) );
NOR2X2TS U2582 ( .A(n1968), .B(n1966), .Y(n1955) );
OAI21X2TS U2583 ( .A0(n1968), .A1(n2540), .B0(n1969), .Y(n1954) );
OAI21X1TS U2584 ( .A0(n1945), .A1(n1957), .B0(n1946), .Y(n1685) );
INVX2TS U2585 ( .A(n2188), .Y(n2218) );
NAND2X1TS U2586 ( .A(n2214), .B(n1054), .Y(n2190) );
NAND2X1TS U2587 ( .A(DP_OP_453J308_122_681_n317), .B(
DP_OP_453J308_122_681_n327), .Y(n1998) );
OR2X2TS U2588 ( .A(DP_OP_453J308_122_681_n317), .B(
DP_OP_453J308_122_681_n327), .Y(n1092) );
INVX2TS U2589 ( .A(n1847), .Y(n1996) );
NAND2X1TS U2590 ( .A(DP_OP_453J308_122_681_n305), .B(
DP_OP_453J308_122_681_n295), .Y(n2014) );
NOR2X1TS U2591 ( .A(n1223), .B(n1222), .Y(n2040) );
AOI21X1TS U2592 ( .A0(n2029), .A1(n1095), .B0(n1214), .Y(n2044) );
NAND2X1TS U2593 ( .A(n1223), .B(n1222), .Y(n2041) );
INVX2TS U2594 ( .A(n2032), .Y(n2033) );
NAND2X1TS U2595 ( .A(n1265), .B(n1264), .Y(n2068) );
OAI21X1TS U2596 ( .A0(n2059), .A1(n2058), .B0(n2057), .Y(n2060) );
NOR2X1TS U2597 ( .A(n2055), .B(n2058), .Y(n2062) );
INVX2TS U2598 ( .A(n1482), .Y(n1471) );
NOR2X2TS U2599 ( .A(DP_OP_453J308_122_681_n244), .B(
DP_OP_453J308_122_681_n249), .Y(n1472) );
NAND2X1TS U2600 ( .A(n1296), .B(n1295), .Y(n2092) );
NOR2X2TS U2601 ( .A(DP_OP_453J308_122_681_n237), .B(
DP_OP_453J308_122_681_n233), .Y(n2087) );
INVX2TS U2602 ( .A(n2078), .Y(n2079) );
OAI21X2TS U2603 ( .A0(n1440), .A1(n1437), .B0(n1441), .Y(n2174) );
NOR2X2TS U2604 ( .A(n1353), .B(n1440), .Y(n2172) );
NOR2X2TS U2605 ( .A(n1298), .B(n1297), .Y(n1456) );
INVX2TS U2606 ( .A(n1454), .Y(n2093) );
INVX2TS U2607 ( .A(n2092), .Y(n1455) );
NAND2X1TS U2608 ( .A(n1298), .B(n1297), .Y(n1457) );
NOR2X2TS U2609 ( .A(DP_OP_453J308_122_681_n230), .B(
DP_OP_453J308_122_681_n232), .Y(n1449) );
INVX2TS U2610 ( .A(n1446), .Y(n1447) );
INVX2TS U2611 ( .A(n1445), .Y(n1448) );
NOR2X2TS U2612 ( .A(n1292), .B(n1291), .Y(n1465) );
INVX2TS U2613 ( .A(n1464), .Y(n1481) );
NOR2X2TS U2614 ( .A(n1290), .B(n1289), .Y(n1477) );
NAND2X1TS U2615 ( .A(n1292), .B(n1291), .Y(n1466) );
OAI21X2TS U2616 ( .A0(n1472), .A1(n1482), .B0(n1473), .Y(n2080) );
NAND2X1TS U2617 ( .A(n1267), .B(n1266), .Y(n1487) );
INVX2TS U2618 ( .A(n2068), .Y(n1486) );
INVX2TS U2619 ( .A(n1485), .Y(n2070) );
INVX2TS U2620 ( .A(n1470), .Y(n1483) );
NAND2X1TS U2621 ( .A(n1233), .B(n1232), .Y(n2050) );
OAI21X2TS U2622 ( .A0(n2044), .A1(n2040), .B0(n2041), .Y(n2052) );
INVX2TS U2623 ( .A(n2026), .Y(n2034) );
INVX2TS U2624 ( .A(n2025), .Y(n2061) );
NOR2X2TS U2625 ( .A(DP_OP_453J308_122_681_n306), .B(
DP_OP_453J308_122_681_n316), .Y(n2011) );
NAND2X1TS U2626 ( .A(DP_OP_453J308_122_681_n306), .B(
DP_OP_453J308_122_681_n316), .Y(n2010) );
INVX2TS U2627 ( .A(n2003), .Y(n2012) );
CLKXOR2X2TS U2628 ( .A(n1857), .B(n1856), .Y(n2530) );
NAND2X1TS U2629 ( .A(n1059), .B(n1855), .Y(n1856) );
NAND2X1TS U2630 ( .A(DP_OP_453J308_122_681_n328), .B(
DP_OP_453J308_122_681_n338), .Y(n1847) );
NAND2X1TS U2631 ( .A(n2155), .B(n2154), .Y(n2188) );
XNOR2X1TS U2632 ( .A(n2230), .B(FPMULT_Op_MX[22]), .Y(n2231) );
CLKAND2X2TS U2633 ( .A(n2229), .B(n1011), .Y(n2230) );
INVX2TS U2634 ( .A(n1011), .Y(n2227) );
AOI21X1TS U2635 ( .A0(n2219), .A1(n1029), .B0(n1027), .Y(n2220) );
OAI21X2TS U2636 ( .A0(n1456), .A1(n2092), .B0(n1457), .Y(n1429) );
OAI22X1TS U2637 ( .A0(n2425), .A1(n1423), .B0(n2424), .B1(n2431), .Y(
DP_OP_453J308_122_681_n442) );
XOR2X1TS U2638 ( .A(DP_OP_453J308_122_681_n228), .B(n1424), .Y(n1425) );
NAND2X1TS U2639 ( .A(n1405), .B(n2054), .Y(n1407) );
AOI21X1TS U2640 ( .A0(n1405), .A1(n2056), .B0(n1404), .Y(n1406) );
XNOR2X1TS U2641 ( .A(n1885), .B(n1884), .Y(n1986) );
NAND2X1TS U2642 ( .A(n1084), .B(n1883), .Y(n1885) );
CLKXOR2X2TS U2643 ( .A(n1882), .B(n1881), .Y(n2532) );
NAND2X1TS U2644 ( .A(n1061), .B(n1880), .Y(n1881) );
XOR2X1TS U2645 ( .A(n1910), .B(n1909), .Y(n1983) );
NAND2X1TS U2646 ( .A(n1908), .B(n1907), .Y(n1910) );
CLKXOR2X2TS U2647 ( .A(n1905), .B(n1904), .Y(n2534) );
INVX2TS U2648 ( .A(n1901), .Y(n1903) );
ADDFX2TS U2649 ( .A(n1605), .B(n1604), .CI(n1603), .CO(n1610), .S(n1609) );
OAI22X1TS U2650 ( .A0(n1700), .A1(n1596), .B0(n1008), .B1(n1590), .Y(n1604)
);
OAI22X1TS U2651 ( .A0(n1700), .A1(n1590), .B0(n1008), .B1(n1584), .Y(n1588)
);
OAI21X1TS U2652 ( .A0(n2578), .A1(n2574), .B0(n2575), .Y(n2563) );
ADDFX2TS U2653 ( .A(n1642), .B(n1641), .CI(n1640), .CO(n1648), .S(n1647) );
AOI21X2TS U2654 ( .A0(n1615), .A1(n2563), .B0(n1614), .Y(n2555) );
OAI21X1TS U2655 ( .A0(n2564), .A1(n2570), .B0(n2565), .Y(n1614) );
NOR2X1TS U2656 ( .A(n2564), .B(n2569), .Y(n1615) );
NAND2X1TS U2657 ( .A(n2536), .B(n1980), .Y(n2724) );
NAND2X1TS U2658 ( .A(n2537), .B(n1979), .Y(n2728) );
NOR2X1TS U2659 ( .A(n2533), .B(n1985), .Y(n2744) );
NAND2X1TS U2660 ( .A(n1649), .B(n1648), .Y(n2557) );
INVX2TS U2661 ( .A(n2560), .Y(n2556) );
ADDFX2TS U2662 ( .A(n1655), .B(n1654), .CI(n1653), .CO(n1677), .S(n1674) );
CLKXOR2X2TS U2663 ( .A(n1960), .B(n1959), .Y(n2539) );
NAND2X1TS U2664 ( .A(n1958), .B(n1957), .Y(n1959) );
AOI21X1TS U2665 ( .A0(n2543), .A1(n1955), .B0(n1954), .Y(n1960) );
INVX2TS U2666 ( .A(n1956), .Y(n1958) );
XOR2X1TS U2667 ( .A(n1965), .B(n1964), .Y(n1976) );
CLKXOR2X2TS U2668 ( .A(n1949), .B(n1948), .Y(n2538) );
NAND2X1TS U2669 ( .A(n1947), .B(n1946), .Y(n1948) );
AOI21X1TS U2670 ( .A0(n2543), .A1(n1944), .B0(n1943), .Y(n1949) );
INVX2TS U2671 ( .A(n1945), .Y(n1947) );
NOR2X1TS U2672 ( .A(n996), .B(DP_OP_453J308_122_681_n1585), .Y(n1833) );
NAND2X1TS U2673 ( .A(n2198), .B(n2197), .Y(n2216) );
XNOR2X2TS U2674 ( .A(n2095), .B(n2094), .Y(n2105) );
NAND2X1TS U2675 ( .A(n2093), .B(n2092), .Y(n2094) );
NAND2X1TS U2676 ( .A(n2089), .B(n2088), .Y(n2090) );
AOI21X1TS U2677 ( .A0(n2086), .A1(n2085), .B0(n2084), .Y(n2091) );
INVX2TS U2678 ( .A(n2087), .Y(n2089) );
NAND2X1TS U2679 ( .A(n2160), .B(n2163), .Y(n2161) );
AOI21X1TS U2680 ( .A0(n2225), .A1(n2159), .B0(n2158), .Y(n2162) );
INVX2TS U2681 ( .A(n2164), .Y(n2160) );
NOR2X2TS U2682 ( .A(n2136), .B(n2135), .Y(n2180) );
NOR2X1TS U2683 ( .A(n1041), .B(n2210), .Y(n2185) );
NOR2X2TS U2684 ( .A(n1355), .B(n1354), .Y(n1440) );
INVX2TS U2685 ( .A(n1437), .Y(n1438) );
XNOR2X2TS U2686 ( .A(n1436), .B(n1327), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[15]) );
NAND2X1TS U2687 ( .A(n1335), .B(n1334), .Y(n1336) );
AOI21X1TS U2688 ( .A0(n2095), .A1(n1332), .B0(n1331), .Y(n1337) );
CLKXOR2X2TS U2689 ( .A(n1460), .B(n1459), .Y(n2584) );
NAND2X1TS U2690 ( .A(n1458), .B(n1457), .Y(n1459) );
AOI21X1TS U2691 ( .A0(n2095), .A1(n2093), .B0(n1455), .Y(n1460) );
INVX2TS U2692 ( .A(n1456), .Y(n1458) );
NAND2X1TS U2693 ( .A(n1451), .B(n1450), .Y(n1452) );
AOI21X1TS U2694 ( .A0(n2086), .A1(n1448), .B0(n1447), .Y(n1453) );
INVX2TS U2695 ( .A(n1449), .Y(n1451) );
NAND2X1TS U2696 ( .A(n1461), .B(n2081), .Y(n1462) );
AOI21X1TS U2697 ( .A0(n2086), .A1(n2078), .B0(n2080), .Y(n1463) );
INVX2TS U2698 ( .A(n2082), .Y(n1461) );
CLKXOR2X2TS U2699 ( .A(n1489), .B(n1488), .Y(n2587) );
NAND2X1TS U2700 ( .A(n1096), .B(n1487), .Y(n1488) );
AOI21X1TS U2701 ( .A0(n2070), .A1(n1097), .B0(n1486), .Y(n1489) );
NAND2X1TS U2702 ( .A(n1483), .B(n1482), .Y(n1484) );
NAND2X1TS U2703 ( .A(n1095), .B(n2028), .Y(n2030) );
NAND2X1TS U2704 ( .A(n2034), .B(n2032), .Y(n2027) );
NAND2X1TS U2705 ( .A(n2004), .B(n2010), .Y(n2005) );
INVX2TS U2706 ( .A(n2011), .Y(n2004) );
XNOR2X1TS U2707 ( .A(n1997), .B(n1848), .Y(n1992) );
NAND2X1TS U2708 ( .A(n1093), .B(n1847), .Y(n1848) );
NAND2X1TS U2709 ( .A(n1054), .B(n2188), .Y(n2156) );
AOI21X1TS U2710 ( .A0(n2225), .A1(n2146), .B0(n2145), .Y(n2157) );
AOI21X1TS U2711 ( .A0(n2225), .A1(n2224), .B0(n2223), .Y(n2235) );
NAND2X1TS U2712 ( .A(DP_OP_453J308_122_681_n229), .B(n1425), .Y(n1426) );
NAND2X1TS U2713 ( .A(n1601), .B(n1600), .Y(n2579) );
NOR2X1TS U2714 ( .A(n1609), .B(n1608), .Y(n2574) );
NAND2X1TS U2715 ( .A(n1609), .B(n1608), .Y(n2575) );
NAND2X1TS U2716 ( .A(n2532), .B(n1986), .Y(n2762) );
NAND2X1TS U2717 ( .A(n2534), .B(n1983), .Y(n2765) );
NOR2X2TS U2718 ( .A(n1611), .B(n1610), .Y(n2569) );
NAND2X1TS U2719 ( .A(n1613), .B(n1612), .Y(n2565) );
NAND2X1TS U2720 ( .A(n1611), .B(n1610), .Y(n2570) );
NOR2X2TS U2721 ( .A(n1613), .B(n1612), .Y(n2564) );
NAND2X1TS U2722 ( .A(n1647), .B(n1646), .Y(n2560) );
OR2X1TS U2723 ( .A(n1647), .B(n1646), .Y(n1077) );
NAND2X1TS U2724 ( .A(n2742), .B(n2741), .Y(n2743) );
XOR2X1TS U2725 ( .A(n2723), .B(n2722), .Y(n2739) );
XOR2X1TS U2726 ( .A(FPMULT_Op_MX[0]), .B(n984), .Y(n1382) );
NOR2X1TS U2727 ( .A(n2539), .B(n1976), .Y(n2732) );
NAND2X1TS U2728 ( .A(n2539), .B(n1976), .Y(n2733) );
NAND2X1TS U2729 ( .A(n2538), .B(n1977), .Y(n2948) );
NAND2X1TS U2730 ( .A(n1843), .B(n1842), .Y(n1844) );
CLKXOR2X2TS U2731 ( .A(n1839), .B(n1838), .Y(n2529) );
NAND2X1TS U2732 ( .A(n1072), .B(n1837), .Y(n1838) );
NAND2X1TS U2733 ( .A(n1836), .B(n1835), .Y(n1837) );
XOR2X1TS U2734 ( .A(n2200), .B(n2199), .Y(n2582) );
NAND2X1TS U2735 ( .A(n1050), .B(n2216), .Y(n2199) );
AOI21X1TS U2736 ( .A0(n2225), .A1(n2192), .B0(n2191), .Y(n2200) );
INVX2TS U2737 ( .A(n2624), .Y(n2077) );
INVX2TS U2738 ( .A(n2185), .Y(n2100) );
INVX2TS U2739 ( .A(n2599), .Y(n2600) );
XNOR2X2TS U2740 ( .A(n2171), .B(n2170), .Y(n1100) );
NAND2X1TS U2741 ( .A(n2169), .B(n2168), .Y(n2170) );
INVX2TS U2742 ( .A(n2167), .Y(n2169) );
XNOR2X2TS U2743 ( .A(n2184), .B(n2183), .Y(n1046) );
NAND2X1TS U2744 ( .A(n2182), .B(n2181), .Y(n2183) );
AOI21X1TS U2745 ( .A0(n2225), .A1(n2179), .B0(n2178), .Y(n2184) );
INVX2TS U2746 ( .A(n2180), .Y(n2182) );
XNOR2X2TS U2747 ( .A(n1444), .B(n1443), .Y(n1041) );
NAND2X1TS U2748 ( .A(n1442), .B(n1441), .Y(n1443) );
AOI21X1TS U2749 ( .A0(n2225), .A1(n1439), .B0(n1438), .Y(n1444) );
INVX2TS U2750 ( .A(n1440), .Y(n1442) );
NAND2X1TS U2751 ( .A(n2073), .B(n2587), .Y(n2630) );
NAND2X1TS U2752 ( .A(n1992), .B(n1991), .Y(n2663) );
OAI21X2TS U2753 ( .A0(n2740), .A1(n1082), .B0(n2741), .Y(n2662) );
INVX2TS U2754 ( .A(n2666), .Y(n2661) );
INVX2TS U2755 ( .A(n2594), .Y(n2595) );
CLKAND2X2TS U2756 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3751), .Y(n3044)
);
OAI21XLTS U2757 ( .A0(n2860), .A1(n3777), .B0(n2859), .Y(n2861) );
AO22XLTS U2758 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n941), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n2857) );
CLKAND2X2TS U2759 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n3784), .Y(n3419)
);
OAI21XLTS U2760 ( .A0(n2860), .A1(n3787), .B0(n2855), .Y(n2856) );
OAI21XLTS U2761 ( .A0(n2860), .A1(n3720), .B0(n2853), .Y(n2854) );
OAI21XLTS U2762 ( .A0(n3776), .A1(n2860), .B0(n2838), .Y(n2839) );
AO22XLTS U2763 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n2840) );
CLKAND2X2TS U2764 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3754), .Y(n3050)
);
CLKAND2X2TS U2765 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n3758), .Y(n3060)
);
BUFX4TS U2766 ( .A(n2673), .Y(n3503) );
BUFX4TS U2767 ( .A(n3532), .Y(n3500) );
BUFX4TS U2768 ( .A(n3500), .Y(n3589) );
XOR2X1TS U2769 ( .A(n2757), .B(n2756), .Y(n2761) );
NAND2X1TS U2770 ( .A(n2755), .B(n2754), .Y(n2757) );
XNOR2X1TS U2771 ( .A(n2764), .B(n2763), .Y(n2772) );
NAND2X1TS U2772 ( .A(n1081), .B(n2762), .Y(n2764) );
XOR2X1TS U2773 ( .A(n2743), .B(n1082), .Y(n2750) );
NAND2X1TS U2774 ( .A(n2547), .B(n2546), .Y(n2548) );
OAI21X1TS U2775 ( .A0(n2554), .A1(n2550), .B0(n2551), .Y(n2549) );
CLKXOR2X2TS U2776 ( .A(n1972), .B(n1971), .Y(n2952) );
AOI21X1TS U2777 ( .A0(n2543), .A1(n2541), .B0(n1967), .Y(n1972) );
OAI21X1TS U2778 ( .A0(n2732), .A1(n2953), .B0(n2733), .Y(n2949) );
NAND2X1TS U2779 ( .A(n2952), .B(n2951), .Y(n2953) );
INVX2TS U2780 ( .A(FPMULT_Sgf_normalized_result[13]), .Y(n3193) );
NAND2X1TS U2781 ( .A(n2529), .B(n1990), .Y(n2666) );
INVX2TS U2782 ( .A(n2788), .Y(n2789) );
CLKAND2X2TS U2783 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n3726), .Y(n2911)
);
OAI211XLTS U2784 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n3783), .B0(n3651), .C0(n3373), .Y(n875) );
AOI21X1TS U2785 ( .A0(n2187), .A1(n2613), .B0(n2186), .Y(n2201) );
NAND2X1TS U2786 ( .A(n1045), .B(n2658), .Y(n2659) );
NAND2X1TS U2787 ( .A(n1099), .B(n2650), .Y(n2651) );
NAND2X1TS U2788 ( .A(n1037), .B(n2642), .Y(n2643) );
NAND2X1TS U2789 ( .A(n1042), .B(n2634), .Y(n2636) );
NAND2X1TS U2790 ( .A(n1102), .B(n2626), .Y(n2628) );
NAND2X1TS U2791 ( .A(n2621), .B(n2620), .Y(n2623) );
INVX2TS U2792 ( .A(n2619), .Y(n2621) );
NAND2X1TS U2793 ( .A(n2612), .B(n2611), .Y(n2614) );
AOI21X1TS U2794 ( .A0(n2613), .A1(n2605), .B0(n2604), .Y(n2607) );
AOI21X1TS U2795 ( .A0(n2602), .A1(n2613), .B0(n2601), .Y(n2603) );
AOI21X1TS U2796 ( .A0(n2204), .A1(n2613), .B0(n2203), .Y(n2205) );
XOR2XLTS U2797 ( .A(n2967), .B(n2966), .Y(FPADDSUB_Raw_mant_SGF[9]) );
AOI21X1TS U2798 ( .A0(n2208), .A1(n2613), .B0(n2207), .Y(n2209) );
AOI21X1TS U2799 ( .A0(n2212), .A1(n2613), .B0(n2211), .Y(n2213) );
AOI21X1TS U2800 ( .A0(n2613), .A1(n2612), .B0(n2609), .Y(n2610) );
INVX2TS U2801 ( .A(n2611), .Y(n2609) );
NAND2X1TS U2802 ( .A(n2617), .B(n2616), .Y(n2618) );
NAND2X1TS U2803 ( .A(n1103), .B(n2624), .Y(n2625) );
NAND2X1TS U2804 ( .A(n2631), .B(n2630), .Y(n2633) );
INVX2TS U2805 ( .A(n2629), .Y(n2631) );
NAND2X1TS U2806 ( .A(n2639), .B(n2638), .Y(n2641) );
NAND2X1TS U2807 ( .A(n2647), .B(n2646), .Y(n2648) );
INVX2TS U2808 ( .A(n2645), .Y(n2647) );
NAND2X1TS U2809 ( .A(n2655), .B(n2654), .Y(n2656) );
INVX2TS U2810 ( .A(n2653), .Y(n2655) );
NAND2X1TS U2811 ( .A(n1039), .B(n2663), .Y(n2664) );
AOI21X1TS U2812 ( .A0(n2662), .A1(n1090), .B0(n2661), .Y(n2665) );
AOI21X1TS U2813 ( .A0(n2597), .A1(n2613), .B0(n2596), .Y(n2598) );
AOI2BB1XLTS U2814 ( .A0N(n3931), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n3932), .Y(FPADDSUB_formatted_number_W[31]) );
OAI21XLTS U2815 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n3757), .B0(n3410),
.Y(n3411) );
OAI21XLTS U2816 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n3714), .B0(n3415),
.Y(n3416) );
OAI31X1TS U2817 ( .A0(n3654), .A1(FPSENCOS_cont_var_out[1]), .A2(n3700),
.B0(n3171), .Y(n842) );
XOR2X1TS U2818 ( .A(n2240), .B(n2239), .Y(FPMULT_Sgf_operation_Result[47])
);
AOI21X1TS U2819 ( .A0(n2238), .A1(n2613), .B0(n2237), .Y(n2240) );
OAI211XLTS U2820 ( .A0(operation[1]), .A1(n2675), .B0(n2674), .C0(n2678),
.Y(add_subt_data2[29]) );
OAI211XLTS U2821 ( .A0(n960), .A1(n2672), .B0(n2671), .C0(n2691), .Y(
add_subt_data2[19]) );
OAI21XLTS U2822 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n3701), .B0(n3405),
.Y(n3406) );
OAI211XLTS U2823 ( .A0(operation[1]), .A1(n2677), .B0(n2676), .C0(n2678),
.Y(add_subt_data2[28]) );
OAI222X1TS U2824 ( .A0(n3056), .A1(n3454), .B0(n956), .B1(n3452), .C0(n954),
.C1(n3451), .Y(FPADDSUB_Data_array_SWR[23]) );
OAI211XLTS U2825 ( .A0(n960), .A1(n2685), .B0(n2684), .C0(n2708), .Y(
add_subt_data2[16]) );
OAI211XLTS U2826 ( .A0(n960), .A1(n2680), .B0(n2679), .C0(n2678), .Y(
add_subt_data2[27]) );
OAI211XLTS U2827 ( .A0(n960), .A1(n3927), .B0(n2688), .C0(n2696), .Y(
add_subt_data2[17]) );
AND4X1TS U2828 ( .A(n2776), .B(n2775), .C(n2774), .D(n2773), .Y(n3827) );
AO22XLTS U2829 ( .A0(operation[1]), .A1(n3212), .B0(n3561), .B1(operation[0]), .Y(n3215) );
MX2X1TS U2830 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
OAI21XLTS U2831 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n2874), .B0(n2881), .Y(
n2875) );
MX2X1TS U2832 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U2833 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U2834 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U2835 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U2836 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U2837 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U2838 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
XOR2X1TS U2839 ( .A(n2668), .B(n2667), .Y(FPMULT_Sgf_operation_Result[23])
);
NAND2X1TS U2840 ( .A(n1090), .B(n2666), .Y(n2668) );
NAND4X1TS U2841 ( .A(n3168), .B(n2800), .C(n2799), .D(n2798), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
NAND2BXLTS U2842 ( .AN(enab_cont_iter), .B(n3885), .Y(n2807) );
NAND2BXLTS U2843 ( .AN(FPADDSUB_intDX_EWSW[30]), .B(n3837), .Y(
FPADDSUB_DMP_INIT_EWSW[30]) );
NAND2X1TS U2844 ( .A(n1069), .B(n1384), .Y(n2363) );
OR2X1TS U2845 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n2846), .Y(n929) );
OR2X1TS U2846 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n2970), .Y(n930) );
BUFX3TS U2847 ( .A(n3325), .Y(n3370) );
INVX2TS U2848 ( .A(n929), .Y(n939) );
INVX2TS U2849 ( .A(n929), .Y(n940) );
INVX2TS U2850 ( .A(n930), .Y(n941) );
INVX2TS U2851 ( .A(n930), .Y(n942) );
INVX2TS U2852 ( .A(n2819), .Y(n943) );
INVX2TS U2853 ( .A(n943), .Y(n944) );
INVX2TS U2854 ( .A(n943), .Y(n945) );
INVX4TS U2855 ( .A(n1051), .Y(n946) );
INVX2TS U2856 ( .A(n3107), .Y(n947) );
INVX2TS U2857 ( .A(n3107), .Y(n948) );
INVX2TS U2858 ( .A(n978), .Y(n950) );
INVX2TS U2859 ( .A(n2363), .Y(n951) );
INVX2TS U2860 ( .A(n3069), .Y(n953) );
INVX4TS U2861 ( .A(n3069), .Y(n954) );
INVX2TS U2862 ( .A(n3453), .Y(n955) );
INVX2TS U2863 ( .A(n955), .Y(n956) );
INVX2TS U2864 ( .A(n3170), .Y(n957) );
INVX3TS U2865 ( .A(n3320), .Y(n963) );
CLKINVX3TS U2866 ( .A(n3321), .Y(n964) );
INVX3TS U2867 ( .A(n3321), .Y(n965) );
INVX3TS U2868 ( .A(n3323), .Y(n967) );
OAI221X1TS U2869 ( .A0(n3766), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n3770),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n3291), .Y(n3294) );
OAI21X1TS U2870 ( .A0(n2970), .A1(n3776), .B0(n2969), .Y(n2817) );
OAI21X1TS U2871 ( .A0(n2970), .A1(n3777), .B0(n2969), .Y(n2829) );
XNOR2X1TS U2872 ( .A(n2660), .B(n2659), .Y(FPMULT_Sgf_operation_Result[25])
);
XNOR2X1TS U2873 ( .A(n2652), .B(n2651), .Y(FPMULT_Sgf_operation_Result[27])
);
XNOR2X1TS U2874 ( .A(n2636), .B(n2635), .Y(FPMULT_Sgf_operation_Result[31])
);
XNOR2X1TS U2875 ( .A(n2628), .B(n2627), .Y(FPMULT_Sgf_operation_Result[33])
);
XNOR2X1TS U2876 ( .A(n2614), .B(n2613), .Y(FPMULT_Sgf_operation_Result[37])
);
INVX2TS U2877 ( .A(n938), .Y(n969) );
INVX2TS U2878 ( .A(n937), .Y(n970) );
INVX2TS U2879 ( .A(n921), .Y(n971) );
INVX2TS U2880 ( .A(n936), .Y(n972) );
INVX2TS U2881 ( .A(n935), .Y(n973) );
INVX2TS U2882 ( .A(n934), .Y(n974) );
INVX2TS U2883 ( .A(n932), .Y(n975) );
ADDHX1TS U2884 ( .A(n2375), .B(n2374), .CO(DP_OP_453J308_122_681_n346), .S(
DP_OP_453J308_122_681_n347) );
ADDHX1TS U2885 ( .A(n1191), .B(n1190), .CO(n1194), .S(n1278) );
ADDHX1TS U2886 ( .A(n2393), .B(n2392), .CO(DP_OP_453J308_122_681_n365), .S(
n2389) );
NOR4X2TS U2887 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n2804) );
OR2X4TS U2888 ( .A(FPSENCOS_cont_iter_out[2]), .B(n3375), .Y(n3463) );
NAND3X2TS U2889 ( .A(n3690), .B(n3697), .C(n3743), .Y(n3375) );
BUFX4TS U2890 ( .A(n3913), .Y(n3887) );
BUFX4TS U2891 ( .A(n3913), .Y(n3888) );
BUFX4TS U2892 ( .A(n3913), .Y(n3891) );
BUFX4TS U2893 ( .A(n3913), .Y(n3890) );
BUFX4TS U2894 ( .A(n3914), .Y(n3894) );
BUFX4TS U2895 ( .A(n3914), .Y(n3893) );
BUFX4TS U2896 ( .A(n3914), .Y(n3892) );
BUFX4TS U2897 ( .A(n3914), .Y(n3895) );
BUFX4TS U2898 ( .A(n3904), .Y(n3899) );
BUFX4TS U2899 ( .A(n3896), .Y(n3897) );
BUFX4TS U2900 ( .A(n2808), .Y(n3900) );
NOR4X1TS U2901 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[28]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[30]), .Y(n3665) );
NOR4X1TS U2902 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[9]), .C(
FPMULT_Op_MY[1]), .D(FPMULT_Op_MY[20]), .Y(n3662) );
NOR4X1TS U2903 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[4]), .C(
FPMULT_Op_MX[8]), .D(FPMULT_Op_MX[20]), .Y(n3671) );
CLKINVX6TS U2904 ( .A(n3648), .Y(n3878) );
BUFX4TS U2905 ( .A(n3848), .Y(n3869) );
BUFX4TS U2906 ( .A(n3898), .Y(n3901) );
BUFX4TS U2907 ( .A(n3898), .Y(n3902) );
AOI21X2TS U2908 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n2849),
.Y(n2923) );
BUFX4TS U2909 ( .A(n3915), .Y(n3907) );
BUFX4TS U2910 ( .A(n3893), .Y(n3885) );
BUFX4TS U2911 ( .A(n3915), .Y(n3912) );
BUFX4TS U2912 ( .A(n3915), .Y(n3886) );
BUFX4TS U2913 ( .A(n3905), .Y(n3904) );
BUFX3TS U2914 ( .A(n3913), .Y(n2808) );
BUFX4TS U2915 ( .A(n3916), .Y(n3898) );
AOI21X2TS U2916 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n2849),
.Y(n2926) );
OAI21X1TS U2917 ( .A0(n2283), .A1(n2282), .B0(n2281), .Y(n2284) );
OAI21X1TS U2918 ( .A0(n2286), .A1(n2281), .B0(n2287), .Y(n1417) );
NAND2X1TS U2919 ( .A(n2275), .B(n2281), .Y(n2276) );
BUFX4TS U2920 ( .A(n2809), .Y(n3849) );
AOI21X2TS U2921 ( .A0(FPADDSUB_Data_array_SWR[47]), .A1(n2815), .B0(n2849),
.Y(n2987) );
AOI21X2TS U2922 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[48]), .B0(n2849),
.Y(n2977) );
BUFX3TS U2923 ( .A(n3843), .Y(n976) );
BUFX4TS U2924 ( .A(n3845), .Y(n3863) );
BUFX4TS U2925 ( .A(n3844), .Y(n3864) );
BUFX4TS U2926 ( .A(n3847), .Y(n3866) );
BUFX4TS U2927 ( .A(n3846), .Y(n3842) );
BUFX3TS U2928 ( .A(n2888), .Y(n2809) );
AOI21X2TS U2929 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n2968),
.Y(n2983) );
OAI21X1TS U2930 ( .A0(n2970), .A1(n3787), .B0(n2969), .Y(n2968) );
AOI21X2TS U2931 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2971),
.Y(n2998) );
OAI21X1TS U2932 ( .A0(n2970), .A1(n3720), .B0(n2969), .Y(n2971) );
NOR2X4TS U2933 ( .A(n3689), .B(n3690), .Y(n3639) );
INVX2TS U2934 ( .A(FPADDSUB_left_right_SHT2), .Y(n977) );
INVX2TS U2935 ( .A(n977), .Y(n978) );
BUFX4TS U2936 ( .A(n3457), .Y(n3458) );
BUFX4TS U2937 ( .A(n3457), .Y(n3456) );
NAND2BX1TS U2938 ( .AN(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n3373) );
NAND2X1TS U2939 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3783),
.Y(n3651) );
INVX2TS U2940 ( .A(n928), .Y(n980) );
INVX2TS U2941 ( .A(n931), .Y(n981) );
OAI21X2TS U2942 ( .A0(n3745), .A1(n3170), .B0(n3072), .Y(n3135) );
OAI21X2TS U2943 ( .A0(n3733), .A1(n3170), .B0(n3081), .Y(n3129) );
OAI21X2TS U2944 ( .A0(n3746), .A1(n3170), .B0(n3075), .Y(n3123) );
AOI222X4TS U2945 ( .A0(n3084), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n3881),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.C1(n957), .Y(n3099) );
INVX2TS U2946 ( .A(n925), .Y(n982) );
INVX4TS U2947 ( .A(n925), .Y(n983) );
XNOR2X1TS U2948 ( .A(n946), .B(FPMULT_Op_MX[18]), .Y(n1246) );
NAND2X1TS U2949 ( .A(FPMULT_Op_MY[1]), .B(n916), .Y(n1412) );
XNOR2X1TS U2950 ( .A(n946), .B(FPMULT_Op_MX[15]), .Y(n1208) );
NAND2X4TS U2951 ( .A(n946), .B(n923), .Y(n1247) );
INVX2TS U2952 ( .A(n924), .Y(n984) );
INVX4TS U2953 ( .A(n1034), .Y(n986) );
NOR4X1TS U2954 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[0]), .C(n949), .D(
FPMULT_Op_MX[6]), .Y(n3668) );
XNOR2X1TS U2955 ( .A(n949), .B(FPMULT_Op_MY[11]), .Y(n1797) );
XNOR2X1TS U2956 ( .A(n949), .B(FPMULT_Op_MY[10]), .Y(n1784) );
XNOR2X1TS U2957 ( .A(n949), .B(FPMULT_Op_MY[9]), .Y(n1774) );
XNOR2X1TS U2958 ( .A(n949), .B(FPMULT_Op_MY[8]), .Y(n1764) );
XNOR2X1TS U2959 ( .A(FPMULT_Op_MY[7]), .B(n949), .Y(n1760) );
XOR2X1TS U2960 ( .A(n2243), .B(n949), .Y(n2250) );
XNOR2X1TS U2961 ( .A(n949), .B(FPMULT_Op_MY[6]), .Y(n1744) );
XNOR2X1TS U2962 ( .A(n949), .B(FPMULT_Op_MY[5]), .Y(n1724) );
XNOR2X1TS U2963 ( .A(n949), .B(FPMULT_Op_MY[4]), .Y(n1701) );
XNOR2X1TS U2964 ( .A(n913), .B(FPMULT_Op_MY[1]), .Y(n1523) );
XNOR2X1TS U2965 ( .A(n913), .B(FPMULT_Op_MY[2]), .Y(n1498) );
XNOR2X1TS U2966 ( .A(n913), .B(FPMULT_Op_MY[3]), .Y(n1509) );
XOR2X1TS U2967 ( .A(n913), .B(FPMULT_Op_MX[10]), .Y(n1496) );
INVX2TS U2968 ( .A(n1033), .Y(n987) );
BUFX4TS U2969 ( .A(FPMULT_Op_MX[9]), .Y(n991) );
NOR4X1TS U2970 ( .A(n990), .B(n993), .C(n991), .D(n986), .Y(n3670) );
XNOR2X1TS U2971 ( .A(n991), .B(FPMULT_Op_MY[11]), .Y(n1775) );
XNOR2X1TS U2972 ( .A(n991), .B(FPMULT_Op_MY[10]), .Y(n1765) );
XNOR2X1TS U2973 ( .A(n991), .B(FPMULT_Op_MY[8]), .Y(n1745) );
XNOR2X1TS U2974 ( .A(n991), .B(FPMULT_Op_MY[9]), .Y(n1755) );
XNOR2X1TS U2975 ( .A(n991), .B(FPMULT_Op_MY[7]), .Y(n1725) );
XNOR2X1TS U2976 ( .A(n991), .B(FPMULT_Op_MY[3]), .Y(n1525) );
XNOR2X1TS U2977 ( .A(n991), .B(FPMULT_Op_MY[5]), .Y(n1510) );
XNOR2X1TS U2978 ( .A(n991), .B(n983), .Y(n1562) );
XNOR2X1TS U2979 ( .A(n991), .B(FPMULT_Op_MY[1]), .Y(n1561) );
XNOR2X1TS U2980 ( .A(n991), .B(FPMULT_Op_MY[4]), .Y(n1499) );
XNOR2X1TS U2981 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MY[2]), .Y(n1541) );
XNOR2X1TS U2982 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MY[6]), .Y(n1702) );
XNOR2X2TS U2983 ( .A(FPMULT_Op_MX[21]), .B(n991), .Y(n2299) );
XOR2X1TS U2984 ( .A(n991), .B(FPMULT_Op_MX[8]), .Y(n1490) );
INVX4TS U2985 ( .A(DP_OP_453J308_122_681_n2084), .Y(n994) );
NOR4X1TS U2986 ( .A(n946), .B(FPMULT_Op_MY[18]), .C(FPMULT_Op_MY[19]), .D(
n994), .Y(n3664) );
XNOR2X1TS U2987 ( .A(n994), .B(FPMULT_Op_MX[22]), .Y(n2122) );
XNOR2X1TS U2988 ( .A(n994), .B(FPMULT_Op_MX[19]), .Y(n1347) );
XNOR2X1TS U2989 ( .A(n994), .B(FPMULT_Op_MX[20]), .Y(n1366) );
XNOR2X1TS U2990 ( .A(FPMULT_Op_MX[21]), .B(n994), .Y(n2113) );
XNOR2X1TS U2991 ( .A(n994), .B(FPMULT_Op_MX[18]), .Y(n1318) );
XNOR2X1TS U2992 ( .A(n994), .B(FPMULT_Op_MX[17]), .Y(n1126) );
NAND2BX1TS U2993 ( .AN(n912), .B(n994), .Y(n1178) );
XNOR2X1TS U2994 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[15]), .Y(n1137) );
XNOR2X1TS U2995 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[14]), .Y(n1159) );
XNOR2X1TS U2996 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[16]), .Y(n1120) );
XNOR2X1TS U2997 ( .A(FPMULT_Op_MY[21]), .B(n912), .Y(n1177) );
XOR2X1TS U2998 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[20]), .Y(n1118) );
AOI221X1TS U2999 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n3837), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n3836), .C0(n3222), .Y(n3224) );
OAI221X1TS U3000 ( .A0(n3837), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n3772),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n3297), .Y(n3312) );
NOR2X1TS U3001 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n3163) );
NOR4X1TS U3002 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n3159), .Y(n2783) );
INVX2TS U3003 ( .A(n926), .Y(n995) );
AOI222X4TS U3004 ( .A0(n3084), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(n3881),
.B1(FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.C1(n958), .Y(n3109) );
OA21XLTS U3005 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n3149), .Y(n2790) );
NOR4X4TS U3006 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n2884), .D(n3749), .Y(
enab_cont_iter) );
NOR4X2TS U3007 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2806) );
NAND3BX1TS U3008 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n2944), .Y(n3483) );
OAI221X1TS U3009 ( .A0(n3765), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n3711), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n3283), .Y(n3286) );
OAI221X1TS U3010 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n3719), .B0(n3786),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n3300), .Y(n3310) );
OAI221X1TS U3011 ( .A0(n3781), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n3712), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n3289), .Y(n3296) );
XNOR2X1TS U3012 ( .A(n2625), .B(n922), .Y(FPMULT_Sgf_operation_Result[34])
);
NAND4X1TS U3013 ( .A(n3151), .B(n2787), .C(n2786), .D(n2785), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
NOR4X1TS U3014 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[13]), .C(
FPMULT_Op_MX[21]), .D(n912), .Y(n3672) );
NOR2X2TS U3015 ( .A(n3715), .B(n3318), .Y(n2890) );
BUFX4TS U3016 ( .A(n3848), .Y(n3853) );
NOR2X4TS U3017 ( .A(n3697), .B(n3743), .Y(n3598) );
BUFX3TS U3018 ( .A(n824), .Y(n3916) );
BUFX3TS U3019 ( .A(n824), .Y(n3915) );
BUFX3TS U3020 ( .A(n824), .Y(n3913) );
BUFX4TS U3021 ( .A(n824), .Y(n3914) );
NOR3X2TS U3022 ( .A(n3704), .B(n2896), .C(n2889), .Y(n107) );
OAI32X4TS U3023 ( .A0(n1089), .A1(FPSENCOS_d_ff1_operation_out), .A2(n980),
.B0(FPSENCOS_d_ff1_shift_region_flag_out_0_), .B1(n3439), .Y(n3440) );
NAND2X1TS U3024 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n3201), .Y(n3200)
);
NAND2X1TS U3025 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n3204), .Y(n3203)
);
AOI21X1TS U3026 ( .A0(n1936), .A1(n1854), .B0(n1853), .Y(n1857) );
AOI21X1TS U3027 ( .A0(n1936), .A1(n1826), .B0(n1825), .Y(n1839) );
AOI21X1TS U3028 ( .A0(n1936), .A1(n1868), .B0(n1867), .Y(n1871) );
AOI21X1TS U3029 ( .A0(n1936), .A1(n1889), .B0(n1888), .Y(n1893) );
AOI21X1TS U3030 ( .A0(n1936), .A1(n1879), .B0(n1878), .Y(n1882) );
AOI21X1TS U3031 ( .A0(n1936), .A1(n1912), .B0(n1911), .Y(n1917) );
AOI21X1TS U3032 ( .A0(n1936), .A1(n1900), .B0(n1899), .Y(n1905) );
AOI21X1TS U3033 ( .A0(n1936), .A1(n1934), .B0(n1922), .Y(n1927) );
AOI21X2TS U3034 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3690), .B0(n2812),
.Y(n2916) );
OAI21X2TS U3035 ( .A0(n3066), .A1(n3737), .B0(n3065), .Y(n3140) );
OAI221X1TS U3036 ( .A0(n3836), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n3771),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n3281), .Y(n3288) );
AOI21X2TS U3037 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n2829),
.Y(n2995) );
AOI21X2TS U3038 ( .A0(n2815), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n2817),
.Y(n2992) );
NOR3BX2TS U3039 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2805),
.C(n2802), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR4BX2TS U3040 ( .AN(n2806), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n2805), .D(n1088), .Y(FPSENCOS_enab_RB3) );
AOI222X4TS U3041 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n3725), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n3395), .C0(n3725), .C1(n3395), .Y(
n2906) );
NAND2X1TS U3042 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n3394) );
CLKBUFX2TS U3043 ( .A(n2503), .Y(n997) );
OAI22X1TS U3044 ( .A0(n2490), .A1(n2500), .B0(n2489), .B1(n997), .Y(
DP_OP_453J308_122_681_n517) );
OAI22X1TS U3045 ( .A0(n2489), .A1(n2500), .B0(n997), .B1(n2497), .Y(
DP_OP_453J308_122_681_n516) );
OAI22X1TS U3046 ( .A0(n2491), .A1(n2500), .B0(n2490), .B1(n997), .Y(
DP_OP_453J308_122_681_n518) );
OAI22X1TS U3047 ( .A0(n2491), .A1(n2503), .B0(n2492), .B1(n2500), .Y(
DP_OP_453J308_122_681_n519) );
OAI22X1TS U3048 ( .A0(n2493), .A1(n2500), .B0(n2492), .B1(n2503), .Y(
DP_OP_453J308_122_681_n520) );
NAND2X4TS U3049 ( .A(n2503), .B(n2327), .Y(n2500) );
CLKBUFX2TS U3050 ( .A(n2487), .Y(n998) );
OAI22X1TS U3051 ( .A0(n2476), .A1(n2486), .B0(n2475), .B1(n998), .Y(
DP_OP_453J308_122_681_n503) );
OAI22X1TS U3052 ( .A0(n2476), .A1(n998), .B0(n2477), .B1(n2486), .Y(
DP_OP_453J308_122_681_n504) );
OAI22X1TS U3053 ( .A0(n2475), .A1(n2486), .B0(n2474), .B1(n998), .Y(
DP_OP_453J308_122_681_n502) );
OAI22X1TS U3054 ( .A0(n2478), .A1(n2486), .B0(n2477), .B1(n2487), .Y(
DP_OP_453J308_122_681_n505) );
OAI22X1TS U3055 ( .A0(n2481), .A1(n2487), .B0(n2480), .B1(n2486), .Y(
DP_OP_453J308_122_681_n508) );
OAI22X1TS U3056 ( .A0(n2479), .A1(n2486), .B0(n2478), .B1(n2487), .Y(
DP_OP_453J308_122_681_n506) );
OAI22X1TS U3057 ( .A0(n2486), .A1(n2405), .B0(n2487), .B1(n2485), .Y(n2409)
);
NAND2X4TS U3058 ( .A(n2487), .B(n2387), .Y(n2486) );
OAI32X1TS U3059 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n3748), .B0(n3699), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2784) );
OAI2BB1X1TS U3060 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n958), .B0(
n3078), .Y(n3117) );
NAND2X2TS U3061 ( .A(n981), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2969)
);
NOR4X2TS U3062 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3144) );
OAI22X1TS U3063 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n3732), .B0(n3013),
.B1(n3012), .Y(n3019) );
OAI22X1TS U3064 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n3736), .B0(n3026),
.B1(n3025), .Y(n3030) );
OAI22X1TS U3065 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n3784), .B0(n3419),
.B1(n3418), .Y(n3423) );
XOR2X1TS U3066 ( .A(n2321), .B(n1043), .Y(n2522) );
INVX4TS U3067 ( .A(n2522), .Y(n999) );
INVX2TS U3068 ( .A(n999), .Y(n2505) );
CLKBUFX2TS U3069 ( .A(n2473), .Y(n1000) );
OAI22X1TS U3070 ( .A0(n2463), .A1(n2470), .B0(n2462), .B1(n1000), .Y(
DP_OP_453J308_122_681_n488) );
OAI22X1TS U3071 ( .A0(n2462), .A1(n2470), .B0(n2461), .B1(n1000), .Y(
DP_OP_453J308_122_681_n487) );
OAI22X1TS U3072 ( .A0(n2463), .A1(n2473), .B0(n2464), .B1(n2470), .Y(
DP_OP_453J308_122_681_n489) );
OAI22X1TS U3073 ( .A0(n2467), .A1(n2470), .B0(n2465), .B1(n2473), .Y(
DP_OP_453J308_122_681_n491) );
OAI22X1TS U3074 ( .A0(n2465), .A1(n2470), .B0(n2464), .B1(n2473), .Y(
DP_OP_453J308_122_681_n490) );
OAI22X1TS U3075 ( .A0(n2469), .A1(n2470), .B0(n2467), .B1(n2473), .Y(
DP_OP_453J308_122_681_n492) );
OAI22X1TS U3076 ( .A0(n2469), .A1(n2473), .B0(n2468), .B1(n2470), .Y(
DP_OP_453J308_122_681_n493) );
OAI22X1TS U3077 ( .A0(n2468), .A1(n2473), .B0(n2472), .B1(n2470), .Y(n2374)
);
OAI22X1TS U3078 ( .A0(n2471), .A1(n2473), .B0(n2394), .B1(n2470), .Y(n2393)
);
OAI22X1TS U3079 ( .A0(n2470), .A1(n2398), .B0(n2473), .B1(n2397), .Y(n2402)
);
NAND2X4TS U3080 ( .A(n2473), .B(n2271), .Y(n2470) );
CLKXOR2X2TS U3081 ( .A(n2380), .B(n2379), .Y(n2497) );
INVX4TS U3082 ( .A(n2497), .Y(n1001) );
XNOR2X1TS U3083 ( .A(n2516), .B(n1001), .Y(n2496) );
XNOR2X1TS U3084 ( .A(n2498), .B(n1001), .Y(n2502) );
CLKXOR2X4TS U3085 ( .A(n2296), .B(n2295), .Y(n1003) );
OAI22X1TS U3086 ( .A0(n2448), .A1(n2460), .B0(n1002), .B1(n2447), .Y(
DP_OP_453J308_122_681_n471) );
OAI22X1TS U3087 ( .A0(n2449), .A1(n2460), .B0(n2448), .B1(n1003), .Y(n2302)
);
OAI22X1TS U3088 ( .A0(n2450), .A1(n1003), .B0(n2451), .B1(n2460), .Y(
DP_OP_453J308_122_681_n474) );
OAI22X1TS U3089 ( .A0(n2456), .A1(n2460), .B0(n2454), .B1(n1002), .Y(
DP_OP_453J308_122_681_n477) );
OAI22X1TS U3090 ( .A0(n2456), .A1(n1003), .B0(n2455), .B1(n2460), .Y(
DP_OP_453J308_122_681_n478) );
OAI22X1TS U3091 ( .A0(n2452), .A1(n2460), .B0(n2451), .B1(n1003), .Y(
DP_OP_453J308_122_681_n475) );
OAI22X1TS U3092 ( .A0(n2454), .A1(n2460), .B0(n2452), .B1(n1002), .Y(
DP_OP_453J308_122_681_n476) );
OAI22X1TS U3093 ( .A0(n2460), .A1(n2457), .B0(n2373), .B1(n1002), .Y(n2375)
);
OAI22X1TS U3094 ( .A0(n2460), .A1(n2459), .B0(n1003), .B1(n2457), .Y(
DP_OP_453J308_122_681_n482) );
OAI22X1TS U3095 ( .A0(n2460), .A1(n2388), .B0(n1002), .B1(n2459), .Y(n2392)
);
NAND2X4TS U3096 ( .A(n2458), .B(n2301), .Y(n2460) );
NAND2X1TS U3097 ( .A(n2294), .B(n2293), .Y(n2295) );
CLKXOR2X2TS U3098 ( .A(n2296), .B(n2295), .Y(n2458) );
CLKXOR2X2TS U3099 ( .A(n2385), .B(n2377), .Y(n2483) );
INVX4TS U3100 ( .A(n2483), .Y(n1004) );
XNOR2X1TS U3101 ( .A(n2498), .B(n1004), .Y(n2482) );
XNOR2X1TS U3102 ( .A(n2520), .B(n1004), .Y(n2484) );
CLKBUFX2TS U3103 ( .A(n2446), .Y(n1005) );
OAI22X1TS U3104 ( .A0(n2435), .A1(n2445), .B0(n1005), .B1(n2434), .Y(n2262)
);
OAI22X1TS U3105 ( .A0(n2436), .A1(n2445), .B0(n2435), .B1(n1005), .Y(
DP_OP_453J308_122_681_n457) );
OAI22X1TS U3106 ( .A0(n2438), .A1(n2446), .B0(n2437), .B1(n2445), .Y(
DP_OP_453J308_122_681_n459) );
OAI22X1TS U3107 ( .A0(n2439), .A1(n2445), .B0(n2437), .B1(n2446), .Y(n2317)
);
OAI22X1TS U3108 ( .A0(n2440), .A1(n2445), .B0(n2439), .B1(n2446), .Y(
DP_OP_453J308_122_681_n461) );
OAI22X1TS U3109 ( .A0(n2441), .A1(n2446), .B0(n2445), .B1(n2354), .Y(n2345)
);
OAI22X1TS U3110 ( .A0(n2441), .A1(n2445), .B0(n2440), .B1(n2446), .Y(
DP_OP_453J308_122_681_n462) );
OAI22X1TS U3111 ( .A0(n2445), .A1(n2364), .B0(n2356), .B1(n2446), .Y(n2360)
);
OAI22X1TS U3112 ( .A0(n2445), .A1(n2369), .B0(n2364), .B1(n2446), .Y(n2365)
);
OAI22X1TS U3113 ( .A0(n2445), .A1(n2443), .B0(n2446), .B1(n2369), .Y(n2370)
);
OAI22X1TS U3114 ( .A0(n2445), .A1(n2434), .B0(n2446), .B1(n2433), .Y(
DP_OP_453J308_122_681_n435) );
NOR2BX1TS U3115 ( .AN(n952), .B(n2446), .Y(DP_OP_453J308_122_681_n469) );
NAND2X4TS U3116 ( .A(n2250), .B(n2446), .Y(n2445) );
XOR2X1TS U3117 ( .A(n2294), .B(n2293), .Y(n2466) );
INVX2TS U3118 ( .A(n1006), .Y(n2398) );
XNOR2X1TS U3119 ( .A(n2523), .B(n1006), .Y(n2394) );
XNOR2X1TS U3120 ( .A(n1006), .B(n2411), .Y(n2395) );
BUFX3TS U3121 ( .A(n1699), .Y(n1007) );
BUFX3TS U3122 ( .A(n1699), .Y(n1008) );
OAI22X1TS U3123 ( .A0(n1700), .A1(n1518), .B0(n1497), .B1(n1008), .Y(n1522)
);
OAI22X1TS U3124 ( .A0(n1700), .A1(n1622), .B0(n1008), .B1(n1624), .Y(n1637)
);
OAI22X1TS U3125 ( .A0(n1700), .A1(n1497), .B0(n1508), .B1(n1008), .Y(n1506)
);
OAI22X1TS U3126 ( .A0(n1700), .A1(n1624), .B0(n1008), .B1(n1623), .Y(n1658)
);
OAI22X1TS U3127 ( .A0(n1700), .A1(n1584), .B0(n1008), .B1(n1622), .Y(n1634)
);
NAND2X4TS U3128 ( .A(n1495), .B(n1007), .Y(n1700) );
XNOR2X1TS U3129 ( .A(n914), .B(FPMULT_Op_MX[2]), .Y(n1699) );
XOR2X1TS U3130 ( .A(n2299), .B(n2291), .Y(n2453) );
INVX2TS U3131 ( .A(n1009), .Y(n2447) );
BUFX4TS U3132 ( .A(n2442), .Y(n1010) );
INVX2TS U3133 ( .A(n1010), .Y(n2434) );
XNOR2X1TS U3134 ( .A(n2241), .B(n949), .Y(n2442) );
OAI22X1TS U3135 ( .A0(n2229), .A1(FPMULT_Op_MX[20]), .B0(n1011), .B1(
FPMULT_Op_MX[21]), .Y(n2131) );
OAI22X1TS U3136 ( .A0(n2229), .A1(FPMULT_Op_MX[16]), .B0(n1011), .B1(
FPMULT_Op_MX[17]), .Y(n1346) );
OAI22X1TS U3137 ( .A0(n2229), .A1(FPMULT_Op_MX[17]), .B0(n1011), .B1(
FPMULT_Op_MX[18]), .Y(n1362) );
OAI22X1TS U3138 ( .A0(n2229), .A1(FPMULT_Op_MX[18]), .B0(n1011), .B1(
FPMULT_Op_MX[19]), .Y(n2112) );
OAI22X1TS U3139 ( .A0(n2229), .A1(FPMULT_Op_MX[14]), .B0(n1011), .B1(
FPMULT_Op_MX[15]), .Y(n1124) );
OAI22X1TS U3140 ( .A0(n2229), .A1(n912), .B0(n1011), .B1(FPMULT_Op_MX[13]),
.Y(n1169) );
OAI22X1TS U3141 ( .A0(n2229), .A1(FPMULT_Op_MX[13]), .B0(n1011), .B1(
FPMULT_Op_MX[14]), .Y(n1140) );
NOR2BX1TS U3142 ( .AN(n912), .B(n1011), .Y(n1174) );
OAI21X1TS U3143 ( .A0(n1011), .A1(n912), .B0(n2229), .Y(n1141) );
XNOR2X1TS U3144 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[22]), .Y(n2228) );
CLKBUFX2TS U3145 ( .A(n1316), .Y(n1012) );
BUFX3TS U3146 ( .A(n1316), .Y(n1013) );
OAI22X1TS U3147 ( .A0(n1317), .A1(FPMULT_Op_MY[15]), .B0(n1013), .B1(n1086),
.Y(n1308) );
OAI22X1TS U3148 ( .A0(n1317), .A1(n1117), .B0(n1013), .B1(FPMULT_Op_MY[15]),
.Y(n1131) );
OAI22X1TS U3149 ( .A0(n1317), .A1(n1248), .B0(n1193), .B1(n1013), .Y(n1235)
);
OAI22X1TS U3150 ( .A0(n1317), .A1(n1193), .B0(n1170), .B1(n1013), .Y(n1191)
);
OAI22X1TS U3151 ( .A0(n1317), .A1(n1249), .B0(n1248), .B1(n1013), .Y(n1250)
);
OAI22X1TS U3152 ( .A0(n1317), .A1(n1170), .B0(n1153), .B1(n1013), .Y(n1173)
);
OAI22X1TS U3153 ( .A0(n1317), .A1(n1218), .B0(n1228), .B1(n1012), .Y(n1225)
);
OAI22X1TS U3154 ( .A0(n1317), .A1(n1228), .B0(n1249), .B1(n1012), .Y(n1252)
);
OAI22X1TS U3155 ( .A0(n1317), .A1(n1209), .B0(n1218), .B1(n1012), .Y(n1219)
);
NAND2X4TS U3156 ( .A(n1116), .B(n1012), .Y(n1317) );
XNOR2X1TS U3157 ( .A(FPMULT_Op_MY[14]), .B(n916), .Y(n1316) );
BUFX3TS U3158 ( .A(n1742), .Y(n1014) );
OAI22X1TS U3159 ( .A0(n1743), .A1(n1706), .B0(n1719), .B1(n1014), .Y(n1726)
);
OAI22X1TS U3160 ( .A0(n1743), .A1(n1583), .B0(n1014), .B1(n1582), .Y(n1589)
);
OAI22X1TS U3161 ( .A0(n1743), .A1(n1539), .B0(n1500), .B1(n1014), .Y(n1527)
);
OAI22X1TS U3162 ( .A0(n1743), .A1(n1032), .B0(n1742), .B1(n1580), .Y(n1586)
);
OAI22X1TS U3163 ( .A0(n1743), .A1(n1511), .B0(n1706), .B1(n1014), .Y(n1703)
);
OAI22X1TS U3164 ( .A0(n1743), .A1(n1575), .B0(n1742), .B1(n1554), .Y(n1574)
);
OAI22X1TS U3165 ( .A0(n1743), .A1(n1554), .B0(n1742), .B1(n1539), .Y(n1571)
);
OAI22X1TS U3166 ( .A0(n1743), .A1(n1627), .B0(n1742), .B1(n1626), .Y(n1633)
);
NAND2X4TS U3167 ( .A(n1491), .B(n1742), .Y(n1743) );
BUFX3TS U3168 ( .A(n1830), .Y(n1016) );
OAI22X1TS U3169 ( .A0(n1831), .A1(n1784), .B0(n1797), .B1(n1016), .Y(n1798)
);
OAI22X1TS U3170 ( .A0(n1831), .A1(n1760), .B0(n1764), .B1(n1016), .Y(n1761)
);
OAI22X1TS U3171 ( .A0(n1831), .A1(n1724), .B0(n1016), .B1(n1744), .Y(n1734)
);
OAI22X1TS U3172 ( .A0(n1831), .A1(n1701), .B0(n1016), .B1(n1724), .Y(n1721)
);
OAI22X1TS U3173 ( .A0(n1831), .A1(n1509), .B0(n1016), .B1(n1701), .Y(n1695)
);
OAI22X1TS U3174 ( .A0(n1831), .A1(n1523), .B0(n1015), .B1(n1498), .Y(n1520)
);
OAI22X1TS U3175 ( .A0(n1831), .A1(n1524), .B0(n1015), .B1(n1523), .Y(n1553)
);
OAI22X1TS U3176 ( .A0(n1831), .A1(n996), .B0(n1015), .B1(n1519), .Y(n1542)
);
OAI22X1TS U3177 ( .A0(n1831), .A1(n1498), .B0(n1015), .B1(n1509), .Y(n1505)
);
NOR2BX1TS U3178 ( .AN(n983), .B(n1015), .Y(n1558) );
NAND2X4TS U3179 ( .A(n1496), .B(n1015), .Y(n1831) );
XNOR2X1TS U3180 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[10]), .Y(n1830) );
BUFX3TS U3181 ( .A(n1364), .Y(n1017) );
BUFX3TS U3182 ( .A(n1364), .Y(n1018) );
OAI22X1TS U3183 ( .A0(n1365), .A1(n1309), .B0(n1018), .B1(n992), .Y(n1349)
);
OAI22X1TS U3184 ( .A0(n1365), .A1(n1135), .B0(n1121), .B1(n1018), .Y(n1129)
);
OAI22X1TS U3185 ( .A0(n1365), .A1(n1158), .B0(n1018), .B1(n1135), .Y(n1157)
);
OAI22X1TS U3186 ( .A0(n1365), .A1(n1175), .B0(n1018), .B1(n1158), .Y(n1188)
);
OAI22X1TS U3187 ( .A0(n1365), .A1(n1241), .B0(n1018), .B1(n1175), .Y(n1273)
);
OAI22X1TS U3188 ( .A0(n1365), .A1(n1242), .B0(n1018), .B1(n1241), .Y(n1276)
);
OAI22X1TS U3189 ( .A0(n1365), .A1(n1238), .B0(n1017), .B1(n1242), .Y(n1257)
);
OAI22X1TS U3190 ( .A0(n1365), .A1(n1224), .B0(n1017), .B1(n1238), .Y(n1263)
);
OAI22X1TS U3191 ( .A0(n1365), .A1(n1215), .B0(n1017), .B1(n1224), .Y(n1231)
);
NOR2BX1TS U3192 ( .AN(n912), .B(n1017), .Y(n1221) );
NAND2X4TS U3193 ( .A(n1119), .B(n1017), .Y(n1365) );
XNOR2X1TS U3194 ( .A(n989), .B(FPMULT_Op_MY[16]), .Y(n1364) );
BUFX3TS U3195 ( .A(n1766), .Y(n1020) );
OAI22X1TS U3196 ( .A0(n1767), .A1(n1720), .B0(n1738), .B1(n1020), .Y(n1739)
);
OAI22X1TS U3197 ( .A0(n1767), .A1(n1738), .B0(n1759), .B1(n1020), .Y(n1756)
);
OAI22X1TS U3198 ( .A0(n1767), .A1(n1698), .B0(n1720), .B1(n1020), .Y(n1723)
);
OAI22X1TS U3199 ( .A0(n1767), .A1(n1507), .B0(n1698), .B1(n1020), .Y(n1697)
);
OAI22X1TS U3200 ( .A0(n1767), .A1(n1517), .B0(n1020), .B1(n1494), .Y(n1502)
);
OAI22X1TS U3201 ( .A0(n1767), .A1(n1494), .B0(n1507), .B1(n1020), .Y(n1512)
);
OAI22X1TS U3202 ( .A0(n1767), .A1(n1540), .B0(n1020), .B1(n1517), .Y(n1544)
);
OAI22X1TS U3203 ( .A0(n1767), .A1(n1619), .B0(n1019), .B1(n1576), .Y(n1616)
);
OAI22X1TS U3204 ( .A0(n1767), .A1(n1576), .B0(n1019), .B1(n1559), .Y(n1661)
);
OAI22X1TS U3205 ( .A0(n1767), .A1(n1620), .B0(n1019), .B1(n1619), .Y(n1639)
);
NOR2BX1TS U3206 ( .AN(n983), .B(n1019), .Y(n1636) );
NAND2X4TS U3207 ( .A(n1492), .B(n1019), .Y(n1767) );
XNOR2X1TS U3208 ( .A(n915), .B(FPMULT_Op_MX[6]), .Y(n1766) );
CLKBUFX2TS U3209 ( .A(n1782), .Y(n1021) );
BUFX3TS U3210 ( .A(n1782), .Y(n1022) );
OAI22X1TS U3211 ( .A0(n1783), .A1(n1775), .B0(DP_OP_453J308_122_681_n1706),
.B1(n1022), .Y(n1785) );
OAI22X1TS U3212 ( .A0(n1783), .A1(n1755), .B0(n1765), .B1(n1022), .Y(n1770)
);
OAI22X1TS U3213 ( .A0(n1783), .A1(n1745), .B0(n1755), .B1(n1022), .Y(n1749)
);
OAI22X1TS U3214 ( .A0(n1783), .A1(n1702), .B0(n1725), .B1(n1022), .Y(n1715)
);
OAI22X1TS U3215 ( .A0(n1783), .A1(n1499), .B0(n1510), .B1(n1022), .Y(n1516)
);
OAI22X1TS U3216 ( .A0(n1783), .A1(n1525), .B0(n1499), .B1(n1022), .Y(n1536)
);
OAI22X1TS U3217 ( .A0(n1783), .A1(n1510), .B0(n1702), .B1(n1021), .Y(n1691)
);
OAI22X1TS U3218 ( .A0(n1783), .A1(DP_OP_453J308_122_681_n1706), .B0(n1572),
.B1(n1021), .Y(n1664) );
OAI22X1TS U3219 ( .A0(n1783), .A1(n1561), .B0(n1541), .B1(n1021), .Y(n1569)
);
OAI22X1TS U3220 ( .A0(n1783), .A1(n1562), .B0(n1561), .B1(n1021), .Y(n1659)
);
NOR2BX1TS U3221 ( .AN(n983), .B(n1021), .Y(n1618) );
NAND2X4TS U3222 ( .A(n1490), .B(n1021), .Y(n1783) );
XNOR2X1TS U3223 ( .A(n918), .B(FPMULT_Op_MX[8]), .Y(n1782) );
BUFX3TS U3224 ( .A(n2150), .Y(n1024) );
OAI22X1TS U3225 ( .A0(n2151), .A1(n994), .B0(n1024), .B1(
DP_OP_453J308_122_681_n2084), .Y(n2152) );
OAI22X1TS U3226 ( .A0(n2151), .A1(n2122), .B0(n1024), .B1(n994), .Y(n2134)
);
OAI22X1TS U3227 ( .A0(n2151), .A1(n2113), .B0(n1024), .B1(n2122), .Y(n2120)
);
OAI22X1TS U3228 ( .A0(n2151), .A1(n1318), .B0(n1024), .B1(n1347), .Y(n1344)
);
OAI22X1TS U3229 ( .A0(n2151), .A1(n1347), .B0(n1024), .B1(n1366), .Y(n1361)
);
OAI22X1TS U3230 ( .A0(n2151), .A1(n1126), .B0(n1024), .B1(n1318), .Y(n1313)
);
OAI22X1TS U3231 ( .A0(n2151), .A1(n1120), .B0(n1024), .B1(n1126), .Y(n1122)
);
OAI22X1TS U3232 ( .A0(n2151), .A1(n1159), .B0(n1024), .B1(n1137), .Y(n1155)
);
OAI22X1TS U3233 ( .A0(n2151), .A1(n1137), .B0(n1023), .B1(n1120), .Y(n1138)
);
OAI22X1TS U3234 ( .A0(n2151), .A1(DP_OP_453J308_122_681_n2084), .B0(n1023),
.B1(n1178), .Y(n1271) );
NOR2BX1TS U3235 ( .AN(n912), .B(n1023), .Y(n1236) );
NAND2X4TS U3236 ( .A(n1118), .B(n1023), .Y(n2151) );
XNOR2X1TS U3237 ( .A(n988), .B(FPMULT_Op_MY[20]), .Y(n2150) );
BUFX3TS U3238 ( .A(n2123), .Y(n1026) );
OAI22X1TS U3239 ( .A0(n2124), .A1(FPMULT_Op_MY[19]), .B0(n1026), .B1(n1049),
.Y(n2127) );
OAI22X1TS U3240 ( .A0(n2124), .A1(n1307), .B0(n1348), .B1(n1026), .Y(n1340)
);
OAI22X1TS U3241 ( .A0(n2124), .A1(n1127), .B0(n1026), .B1(n1307), .Y(n1321)
);
OAI22X1TS U3242 ( .A0(n2124), .A1(n1367), .B0(n1026), .B1(FPMULT_Op_MY[19]),
.Y(n2109) );
OAI22X1TS U3243 ( .A0(n2124), .A1(n1128), .B0(n1026), .B1(n1127), .Y(n1134)
);
OAI22X1TS U3244 ( .A0(n2124), .A1(n1143), .B0(n1026), .B1(n1128), .Y(n1152)
);
OAI22X1TS U3245 ( .A0(n2124), .A1(n1160), .B0(n1026), .B1(n1143), .Y(n1167)
);
OAI22X1TS U3246 ( .A0(n2124), .A1(n1189), .B0(n1026), .B1(n1160), .Y(n1186)
);
OAI22X1TS U3247 ( .A0(n2124), .A1(n1243), .B0(n1026), .B1(n1189), .Y(n1279)
);
OAI22X1TS U3248 ( .A0(n2124), .A1(n1049), .B0(n1025), .B1(n1240), .Y(n1255)
);
NAND2X4TS U3249 ( .A(n1115), .B(n1025), .Y(n2124) );
XNOR2X1TS U3250 ( .A(FPMULT_Op_MY[18]), .B(n917), .Y(n2123) );
NOR3BX2TS U3251 ( .AN(FPSENCOS_cont_var_out[1]), .B(n3780), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
NOR2X4TS U3252 ( .A(n950), .B(n2837), .Y(n2834) );
AND3X1TS U3253 ( .A(n1111), .B(n1110), .C(n1109), .Y(n1036) );
CLKXOR2X2TS U3254 ( .A(n2162), .B(n2161), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[19]) );
INVX2TS U3255 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(
DP_OP_453J308_122_681_n777) );
OR2X1TS U3256 ( .A(n1601), .B(n1600), .Y(n1047) );
OR2X1TS U3257 ( .A(n1114), .B(n1113), .Y(n1052) );
OR2X1TS U3258 ( .A(FPMULT_Op_MY[1]), .B(n946), .Y(n1053) );
OR2X2TS U3259 ( .A(n2155), .B(n2154), .Y(n1054) );
OR2X1TS U3260 ( .A(n1388), .B(n1387), .Y(n1057) );
OA21XLTS U3261 ( .A0(n1961), .A1(n1964), .B0(n1962), .Y(n1058) );
OR2X1TS U3262 ( .A(n2952), .B(n2951), .Y(n1062) );
CLKAND2X2TS U3263 ( .A(n1062), .B(n2953), .Y(n1063) );
OR2X1TS U3264 ( .A(n2536), .B(n1980), .Y(n1065) );
OR2X1TS U3265 ( .A(DP_OP_453J308_122_681_n403), .B(
DP_OP_453J308_122_681_n407), .Y(n1066) );
OR2X1TS U3266 ( .A(n982), .B(FPMULT_Op_MY[12]), .Y(n1069) );
INVX2TS U3267 ( .A(n2811), .Y(n3318) );
INVX2TS U3268 ( .A(FPMULT_FS_Module_state_reg[2]), .Y(n2811) );
INVX2TS U3269 ( .A(FPMULT_FS_Module_state_reg[0]), .Y(n2896) );
INVX2TS U3270 ( .A(n2896), .Y(n3319) );
OR2X1TS U3271 ( .A(n1204), .B(n1203), .Y(n1074) );
OR2X2TS U3272 ( .A(n1649), .B(n1648), .Y(n1078) );
OR2X1TS U3273 ( .A(n2538), .B(n1977), .Y(n1079) );
OR2X1TS U3274 ( .A(n2534), .B(n1983), .Y(n1080) );
OR2X1TS U3275 ( .A(n2532), .B(n1986), .Y(n1081) );
OR2X1TS U3276 ( .A(DP_OP_453J308_122_681_n391), .B(
DP_OP_453J308_122_681_n397), .Y(n1083) );
OR2X1TS U3277 ( .A(DP_OP_453J308_122_681_n377), .B(
DP_OP_453J308_122_681_n384), .Y(n1085) );
OR2X2TS U3278 ( .A(DP_OP_453J308_122_681_n359), .B(
DP_OP_453J308_122_681_n368), .Y(n1091) );
OR2X1TS U3279 ( .A(n1213), .B(n1212), .Y(n1095) );
OR2X2TS U3280 ( .A(n1267), .B(n1266), .Y(n1096) );
OR2X1TS U3281 ( .A(n1233), .B(n1232), .Y(n1098) );
CLKXOR2X2TS U3282 ( .A(n1337), .B(n1336), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[14]) );
INVX2TS U3283 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[14]), .Y(
DP_OP_453J308_122_681_n782) );
INVX2TS U3284 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(n2606) );
INVX2TS U3285 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .Y(n2239) );
INVX2TS U3286 ( .A(n2582), .Y(DP_OP_453J308_122_681_n774) );
CLKXOR2X2TS U3287 ( .A(n2157), .B(n2156), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[21]) );
INVX2TS U3288 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(
DP_OP_453J308_122_681_n775) );
CLKXOR2X2TS U3289 ( .A(n1375), .B(n1374), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[17]) );
INVX2TS U3290 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(n2103) );
OAI21X1TS U3291 ( .A0(FPMULT_Op_MX[2]), .A1(FPMULT_Op_MX[14]), .B0(
FPMULT_Op_MX[13]), .Y(n2329) );
NAND2X1TS U3292 ( .A(FPMULT_Op_MY[7]), .B(n988), .Y(n2281) );
XNOR2X1TS U3293 ( .A(n1001), .B(n951), .Y(n2415) );
XNOR2X1TS U3294 ( .A(n1004), .B(n2411), .Y(n2485) );
NAND2X1TS U3295 ( .A(n2255), .B(n2254), .Y(n2256) );
OAI22X1TS U3296 ( .A0(n2500), .A1(n2415), .B0(n2503), .B1(n2414), .Y(n2419)
);
OAI22X1TS U3297 ( .A0(n1831), .A1(n1764), .B0(n1016), .B1(n1774), .Y(n1778)
);
NOR2X2TS U3298 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n2253) );
INVX2TS U3299 ( .A(n2592), .Y(DP_OP_453J308_122_681_n793) );
XNOR2X1TS U3300 ( .A(n2514), .B(n1001), .Y(n2494) );
OAI22X1TS U3301 ( .A0(n2460), .A1(n2447), .B0(n1003), .B1(n2376), .Y(n2391)
);
OAI22X1TS U3302 ( .A0(n2445), .A1(n2444), .B0(n2446), .B1(n2443), .Y(
DP_OP_453J308_122_681_n468) );
OAI22X1TS U3303 ( .A0(n2474), .A1(n2486), .B0(n2487), .B1(n2483), .Y(
DP_OP_453J308_122_681_n501) );
INVX2TS U3304 ( .A(n2216), .Y(n2217) );
INVX2TS U3305 ( .A(n1911), .Y(n1898) );
INVX2TS U3306 ( .A(n1937), .Y(n1391) );
XNOR2X1TS U3307 ( .A(n949), .B(n983), .Y(n1524) );
OAI22X1TS U3308 ( .A0(n2528), .A1(n2527), .B0(n2526), .B1(n2525), .Y(
DP_OP_453J308_122_681_n542) );
OAI22X1TS U3309 ( .A0(n2507), .A1(n2526), .B0(n2505), .B1(n2527), .Y(
DP_OP_453J308_122_681_n531) );
OAI22X1TS U3310 ( .A0(n2450), .A1(n2460), .B0(n2449), .B1(n1002), .Y(
DP_OP_453J308_122_681_n473) );
OAI22X1TS U3311 ( .A0(n2438), .A1(n2445), .B0(n2436), .B1(n1005), .Y(
DP_OP_453J308_122_681_n458) );
OAI22X1TS U3312 ( .A0(n2229), .A1(FPMULT_Op_MX[15]), .B0(n1011), .B1(
FPMULT_Op_MX[16]), .Y(n1315) );
NOR2X2TS U3313 ( .A(DP_OP_453J308_122_681_n385), .B(
DP_OP_453J308_122_681_n390), .Y(n1906) );
OAI22X1TS U3314 ( .A0(n1631), .A1(n1625), .B0(n1555), .B1(n1628), .Y(n1573)
);
AOI21X2TS U3315 ( .A0(n1896), .A1(n1085), .B0(n1393), .Y(n1872) );
CMPR42X1TS U3316 ( .A(DP_OP_453J308_122_681_n343), .B(
DP_OP_453J308_122_681_n532), .C(DP_OP_453J308_122_681_n344), .D(
DP_OP_453J308_122_681_n340), .ICI(DP_OP_453J308_122_681_n334), .S(
DP_OP_453J308_122_681_n331), .ICO(DP_OP_453J308_122_681_n329), .CO(
DP_OP_453J308_122_681_n330) );
CMPR42X1TS U3317 ( .A(DP_OP_453J308_122_681_n503), .B(
DP_OP_453J308_122_681_n311), .C(DP_OP_453J308_122_681_n301), .D(
DP_OP_453J308_122_681_n307), .ICI(
FPMULT_Sgf_operation_EVEN1_Q_left[15]), .S(DP_OP_453J308_122_681_n298),
.ICO(DP_OP_453J308_122_681_n296), .CO(DP_OP_453J308_122_681_n297) );
NAND2X1TS U3318 ( .A(n1903), .B(n1902), .Y(n1904) );
NAND2X1TS U3319 ( .A(n1891), .B(n1890), .Y(n1892) );
AOI21X1TS U3320 ( .A0(n1850), .A1(n1059), .B0(n1822), .Y(n1823) );
ADDHX1TS U3321 ( .A(n1211), .B(n1210), .CO(n1212), .S(n1207) );
ADDHX1TS U3322 ( .A(n1607), .B(n1606), .CO(n1608), .S(n1601) );
NOR2X1TS U3323 ( .A(n2545), .B(n2550), .Y(n1676) );
NAND2X1TS U3324 ( .A(n1970), .B(n1969), .Y(n1971) );
INVX2TS U3325 ( .A(n1841), .Y(n1843) );
INVX2TS U3326 ( .A(n1431), .Y(n1433) );
NAND2X1TS U3327 ( .A(n2232), .B(n2231), .Y(n2233) );
INVX2TS U3328 ( .A(n2579), .Y(n1602) );
INVX2TS U3329 ( .A(n2564), .Y(n2566) );
NOR2X1TS U3330 ( .A(n1377), .B(n1376), .Y(n1594) );
OAI21X1TS U3331 ( .A0(n2012), .A1(n2011), .B0(n2010), .Y(n2017) );
NAND2X1TS U3332 ( .A(n2047), .B(n2057), .Y(n2048) );
INVX2TS U3333 ( .A(n1333), .Y(n1335) );
NAND2X1TS U3334 ( .A(n1040), .B(n2233), .Y(n2234) );
NOR3XLTS U3335 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n1107) );
OAI21X2TS U3336 ( .A0(n2744), .A1(n2747), .B0(n2745), .Y(n2763) );
XOR2X1TS U3337 ( .A(n2731), .B(n2730), .Y(n2737) );
INVX2TS U3338 ( .A(n2545), .Y(n2547) );
NAND2X1TS U3339 ( .A(n1439), .B(n1437), .Y(n1327) );
AOI21X1TS U3340 ( .A0(n2225), .A1(n2166), .B0(n2165), .Y(n2171) );
NOR2XLTS U3341 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n3145) );
BUFX3TS U3342 ( .A(n3532), .Y(n3558) );
XOR2X1TS U3343 ( .A(n2748), .B(n2747), .Y(n2749) );
NAND2X1TS U3344 ( .A(n1090), .B(n1039), .Y(n1995) );
INVX2TS U3345 ( .A(n2637), .Y(n2639) );
NOR2XLTS U3346 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n2794) );
OR2X1TS U3347 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n3395) );
OAI21XLTS U3348 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n3692), .B0(n2928),
.Y(n2913) );
OAI21XLTS U3349 ( .A0(n2932), .A1(n2934), .B0(n2931), .Y(n2930) );
AOI21X1TS U3350 ( .A0(n2102), .A1(n2613), .B0(n2101), .Y(n2104) );
OAI21XLTS U3351 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n3735), .B0(n3020),
.Y(n3015) );
OAI21XLTS U3352 ( .A0(n2909), .A1(n2911), .B0(n2908), .Y(n2907) );
NOR2XLTS U3353 ( .A(n3003), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
OAI211XLTS U3354 ( .A0(n3172), .A1(n1071), .B0(n2904), .C0(n2900), .Y(
FPMULT_FS_Module_state_next[3]) );
OR2X1TS U3355 ( .A(n3458), .B(FPMULT_exp_oper_result[0]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
NOR2XLTS U3356 ( .A(n3190), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
NOR2XLTS U3357 ( .A(n920), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
XNOR2X1TS U3358 ( .A(n2644), .B(n2643), .Y(FPMULT_Sgf_operation_Result[29])
);
OAI21XLTS U3359 ( .A0(n3679), .A1(n3821), .B0(n3678), .Y(
FPSENCOS_sh_exp_y[5]) );
OR2X1TS U3360 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OAI21XLTS U3361 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n1028), .B0(n2899),
.Y(FPADDSUB_Shift_amount_EXP_EW[0]) );
NOR4X1TS U3362 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n1111) );
NOR4X1TS U3363 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n1110) );
NOR4X1TS U3364 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n1108) );
NOR4X1TS U3365 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n1106) );
NOR4X1TS U3366 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n1105) );
AND4X1TS U3367 ( .A(n1108), .B(n1107), .C(n1106), .D(n1105), .Y(n1109) );
INVX2TS U3368 ( .A(Data_1[10]), .Y(n3683) );
INVX2TS U3369 ( .A(Data_1[11]), .Y(n3684) );
INVX2TS U3370 ( .A(Data_1[19]), .Y(n3685) );
INVX2TS U3371 ( .A(Data_1[9]), .Y(n3686) );
INVX2TS U3372 ( .A(Data_2[8]), .Y(n3687) );
INVX2TS U3373 ( .A(Data_2[21]), .Y(n3688) );
NAND2X1TS U3374 ( .A(n1112), .B(n1247), .Y(n1114) );
XNOR2X1TS U3375 ( .A(n916), .B(FPMULT_Op_MX[13]), .Y(n1201) );
OAI22X1TS U3376 ( .A0(n1247), .A1(n984), .B0(n1201), .B1(n923), .Y(n1113) );
NAND2X1TS U3377 ( .A(n1114), .B(n1113), .Y(n1202) );
NAND2X1TS U3378 ( .A(n1052), .B(n1202), .Y(DP_OP_453J308_122_681_n795) );
XNOR2X1TS U3379 ( .A(n946), .B(FPMULT_Op_MX[14]), .Y(n1200) );
OAI22X1TS U3380 ( .A0(n1247), .A1(n1200), .B0(n1208), .B1(n923), .Y(n1211)
);
XNOR2X1TS U3381 ( .A(n989), .B(n984), .Y(n1198) );
XNOR2X1TS U3382 ( .A(n989), .B(FPMULT_Op_MX[13]), .Y(n1209) );
OAI22X1TS U3383 ( .A0(n1317), .A1(n1198), .B0(n1209), .B1(n1012), .Y(n1210)
);
NAND2BXLTS U3384 ( .AN(n912), .B(FPMULT_Op_MY[15]), .Y(n1199) );
OAI22X1TS U3385 ( .A0(n1317), .A1(n1086), .B0(n1013), .B1(n1199), .Y(n1206)
);
NOR2X2TS U3386 ( .A(n1207), .B(n1206), .Y(n2018) );
OAI22X1TS U3387 ( .A0(n1247), .A1(n1201), .B0(n1200), .B1(n923), .Y(n1204)
);
NOR2BX1TS U3388 ( .AN(n912), .B(n1012), .Y(n1203) );
INVX2TS U3389 ( .A(n1202), .Y(n2007) );
NAND2X1TS U3390 ( .A(n1204), .B(n1203), .Y(n2006) );
INVX2TS U3391 ( .A(n2006), .Y(n1205) );
XNOR2X1TS U3392 ( .A(n946), .B(FPMULT_Op_MX[16]), .Y(n1217) );
XNOR2X1TS U3393 ( .A(n989), .B(FPMULT_Op_MX[14]), .Y(n1218) );
INVX2TS U3394 ( .A(n2028), .Y(n1214) );
XNOR2X1TS U3395 ( .A(n992), .B(n984), .Y(n1215) );
XNOR2X1TS U3396 ( .A(n946), .B(FPMULT_Op_MX[17]), .Y(n1227) );
OAI22X1TS U3397 ( .A0(n1247), .A1(n1217), .B0(n1227), .B1(n923), .Y(n1226)
);
XNOR2X1TS U3398 ( .A(n988), .B(n912), .Y(n1239) );
XNOR2X1TS U3399 ( .A(n914), .B(FPMULT_Op_MY[1]), .Y(n1380) );
XNOR2X1TS U3400 ( .A(n914), .B(FPMULT_Op_MY[2]), .Y(n1599) );
OAI22X1TS U3401 ( .A0(n1631), .A1(n1380), .B0(n1599), .B1(n1628), .Y(n1377)
);
NOR2BX1TS U3402 ( .AN(n982), .B(n1007), .Y(n1376) );
INVX2TS U3403 ( .A(n1594), .Y(n1378) );
NAND2X1TS U3404 ( .A(n1377), .B(n1376), .Y(n1592) );
NAND2X1TS U3405 ( .A(n1378), .B(n1592), .Y(n1381) );
NAND2BXLTS U3406 ( .AN(n982), .B(n986), .Y(n1379) );
NAND2X1TS U3407 ( .A(n1379), .B(n1631), .Y(n1388) );
OAI22X1TS U3408 ( .A0(n1631), .A1(n982), .B0(n1380), .B1(n1628), .Y(n1387)
);
NAND2X1TS U3409 ( .A(n1388), .B(n1387), .Y(n1593) );
XOR2X1TS U3410 ( .A(n1381), .B(n1593), .Y(n2954) );
INVX2TS U3411 ( .A(n2954), .Y(n1390) );
NAND2X1TS U3412 ( .A(n1053), .B(n1412), .Y(n1385) );
XNOR2X4TS U3413 ( .A(n1385), .B(n1414), .Y(n2411) );
XNOR2X1TS U3414 ( .A(n2411), .B(n999), .Y(n2525) );
OAI22X1TS U3415 ( .A0(n2526), .A1(n952), .B0(n2525), .B1(n2527), .Y(n2423)
);
NAND2BXLTS U3416 ( .AN(n951), .B(n999), .Y(n1386) );
NAND2X1TS U3417 ( .A(n1386), .B(n2526), .Y(n2422) );
INVX2TS U3418 ( .A(DP_OP_453J308_122_681_n795), .Y(n2421) );
NAND2X1TS U3419 ( .A(n1057), .B(n1593), .Y(n2768) );
NOR2BX2TS U3420 ( .AN(n912), .B(n923), .Y(n1991) );
INVX2TS U3421 ( .A(n1991), .Y(n1975) );
NOR2BX1TS U3422 ( .AN(n983), .B(n1628), .Y(n2758) );
INVX2TS U3423 ( .A(n2758), .Y(n1974) );
NOR2BX1TS U3424 ( .AN(n952), .B(n2527), .Y(n1973) );
NAND2X1TS U3425 ( .A(n1389), .B(n2768), .Y(n1962) );
INVX2TS U3426 ( .A(n1918), .Y(n1392) );
OAI21X4TS U3427 ( .A0(n1407), .A1(n2025), .B0(n1406), .Y(n2086) );
INVX2TS U3428 ( .A(n1477), .Y(n1479) );
XNOR2X1TS U3429 ( .A(n993), .B(FPMULT_Op_MY[1]), .Y(n1619) );
XNOR2X1TS U3430 ( .A(n986), .B(FPMULT_Op_MY[5]), .Y(n1581) );
XNOR2X1TS U3431 ( .A(n986), .B(FPMULT_Op_MY[6]), .Y(n1630) );
OAI22X1TS U3432 ( .A0(n1631), .A1(n1581), .B0(n1630), .B1(n1628), .Y(n1645)
);
NAND2BX1TS U3433 ( .AN(n982), .B(n990), .Y(n1580) );
XNOR2X1TS U3434 ( .A(n986), .B(FPMULT_Op_MY[4]), .Y(n1591) );
OAI22X1TS U3435 ( .A0(n1631), .A1(n1591), .B0(n1581), .B1(n1628), .Y(n1585)
);
XNOR2X1TS U3436 ( .A(n990), .B(FPMULT_Op_MY[1]), .Y(n1582) );
XNOR2X1TS U3437 ( .A(n990), .B(n983), .Y(n1583) );
NOR2BX1TS U3438 ( .AN(n983), .B(n1742), .Y(n1605) );
XNOR2X1TS U3439 ( .A(n987), .B(FPMULT_Op_MY[1]), .Y(n1596) );
XNOR2X1TS U3440 ( .A(n986), .B(FPMULT_Op_MY[3]), .Y(n1598) );
OAI22X1TS U3441 ( .A0(n1631), .A1(n1598), .B0(n1591), .B1(n1628), .Y(n1603)
);
OAI22X1TS U3442 ( .A0(n1700), .A1(n1033), .B0(n1007), .B1(n1595), .Y(n1607)
);
XNOR2X1TS U3443 ( .A(FPMULT_Op_MX[3]), .B(n982), .Y(n1597) );
OAI22X1TS U3444 ( .A0(n1700), .A1(n1597), .B0(n1007), .B1(n1596), .Y(n1606)
);
OAI22X1TS U3445 ( .A0(n1631), .A1(n1599), .B0(n1598), .B1(n1628), .Y(n1600)
);
XNOR2X1TS U3446 ( .A(n993), .B(n983), .Y(n1620) );
AOI21X4TS U3447 ( .A0(n2544), .A1(n1676), .B0(n1675), .Y(n1940) );
OAI21X4TS U3448 ( .A0(n1688), .A1(n1940), .B0(n1687), .Y(n1936) );
NAND2X1TS U3449 ( .A(n1085), .B(n1894), .Y(n1895) );
INVX2TS U3450 ( .A(n1906), .Y(n1908) );
NAND2X1TS U3451 ( .A(n1083), .B(n1918), .Y(n1920) );
INVX2TS U3452 ( .A(n1928), .Y(n1930) );
NAND2X1TS U3453 ( .A(n1066), .B(n1937), .Y(n1939) );
INVX2TS U3454 ( .A(n1950), .Y(n1952) );
NAND2X1TS U3455 ( .A(n1952), .B(n1951), .Y(n1953) );
XOR2X1TS U3456 ( .A(n1953), .B(n1058), .Y(n1977) );
INVX2TS U3457 ( .A(n1961), .Y(n1963) );
NAND2X1TS U3458 ( .A(n1963), .B(n1962), .Y(n1965) );
INVX2TS U3459 ( .A(n1966), .Y(n2541) );
INVX2TS U3460 ( .A(n2540), .Y(n1967) );
INVX2TS U3461 ( .A(n1968), .Y(n1970) );
AFHCONX2TS U3462 ( .A(n1975), .B(n1974), .CI(n1973), .CON(n1964), .S(n2951)
);
INVX2TS U3463 ( .A(n2948), .Y(n1978) );
OAI21X4TS U3464 ( .A0(n2727), .A1(n2730), .B0(n2728), .Y(n2725) );
INVX2TS U3465 ( .A(n2724), .Y(n1981) );
AOI21X4TS U3466 ( .A0(n1065), .A1(n2725), .B0(n1981), .Y(n2722) );
INVX2TS U3467 ( .A(n2765), .Y(n1984) );
AOI21X4TS U3468 ( .A0(n1080), .A1(n2766), .B0(n1984), .Y(n2747) );
INVX2TS U3469 ( .A(n2762), .Y(n1987) );
NAND2X1TS U3470 ( .A(n1074), .B(n2006), .Y(n2008) );
OAI21X4TS U3471 ( .A0(n2657), .A1(n2653), .B0(n2654), .Y(n2652) );
INVX2TS U3472 ( .A(n2018), .Y(n2020) );
NAND2X1TS U3473 ( .A(n2020), .B(n2019), .Y(n2022) );
CLKXOR2X2TS U3474 ( .A(n2022), .B(n2021), .Y(n2592) );
AOI21X4TS U3475 ( .A0(n2652), .A1(n1099), .B0(n2024), .Y(n2649) );
INVX2TS U3476 ( .A(n2040), .Y(n2042) );
AOI21X4TS U3477 ( .A0(n2644), .A1(n1037), .B0(n2046), .Y(n2640) );
NAND2X1TS U3478 ( .A(n1098), .B(n2050), .Y(n2051) );
OAI21X4TS U3479 ( .A0(n2640), .A1(n2637), .B0(n2638), .Y(n2635) );
NAND2X1TS U3480 ( .A(n1097), .B(n2068), .Y(n2069) );
OAI21X4TS U3481 ( .A0(n2629), .A1(n2632), .B0(n2630), .Y(n2627) );
CLKXOR2X4TS U3482 ( .A(n2249), .B(n2248), .Y(n2446) );
CLKXOR2X4TS U3483 ( .A(n2267), .B(n2266), .Y(n2473) );
INVX2TS U3484 ( .A(n2282), .Y(n2275) );
CLKXOR2X4TS U3485 ( .A(n2277), .B(n2276), .Y(n2514) );
INVX2TS U3486 ( .A(n2278), .Y(n2279) );
CLKXOR2X4TS U3487 ( .A(n2290), .B(n2289), .Y(n2512) );
INVX2TS U3488 ( .A(n2307), .Y(n2309) );
CLKXOR2X4TS U3489 ( .A(n2311), .B(n2310), .Y(n2516) );
XNOR2X4TS U3490 ( .A(n2316), .B(n2315), .Y(n2510) );
CLKXOR2X4TS U3491 ( .A(n2323), .B(n2322), .Y(n2503) );
INVX2TS U3492 ( .A(n2331), .Y(n2333) );
XNOR2X4TS U3493 ( .A(n2335), .B(n2334), .Y(n2498) );
INVX2TS U3494 ( .A(n2336), .Y(n2338) );
CLKXOR2X4TS U3495 ( .A(n2340), .B(n2339), .Y(n2520) );
XNOR2X4TS U3496 ( .A(n2344), .B(n2343), .Y(n2495) );
INVX2TS U3497 ( .A(n2348), .Y(n2350) );
CLKXOR2X4TS U3498 ( .A(n2352), .B(n2351), .Y(n2523) );
CLKXOR2X4TS U3499 ( .A(n2382), .B(n2381), .Y(n2487) );
XNOR2X1TS U3500 ( .A(n1009), .B(n952), .Y(n2388) );
OAI22X1TS U3501 ( .A0(n2394), .A1(n2473), .B0(n2470), .B1(n2395), .Y(n2401)
);
NOR2BX1TS U3502 ( .AN(n952), .B(n2458), .Y(n2400) );
XNOR2X1TS U3503 ( .A(n1006), .B(n951), .Y(n2396) );
OAI22X1TS U3504 ( .A0(n2486), .A1(n2483), .B0(n2487), .B1(n2404), .Y(n2410)
);
XNOR2X1TS U3505 ( .A(n1004), .B(n951), .Y(n2405) );
XNOR2X1TS U3506 ( .A(n2523), .B(n1001), .Y(n2412) );
NOR2BX1TS U3507 ( .AN(n952), .B(n2487), .Y(n2418) );
XNOR2X1TS U3508 ( .A(n1001), .B(n2411), .Y(n2414) );
OAI22X1TS U3509 ( .A0(n2412), .A1(n2503), .B0(n2500), .B1(n2414), .Y(n2417)
);
XNOR2X1TS U3510 ( .A(n1010), .B(n952), .Y(n2444) );
OAI22X1TS U3511 ( .A0(n2472), .A1(n2473), .B0(n2471), .B1(n2470), .Y(
DP_OP_453J308_122_681_n495) );
NOR2BX1TS U3512 ( .AN(n952), .B(n2473), .Y(DP_OP_453J308_122_681_n499) );
OAI22X1TS U3513 ( .A0(n2481), .A1(n2486), .B0(n2479), .B1(n2487), .Y(
DP_OP_453J308_122_681_n507) );
OAI22X1TS U3514 ( .A0(n2482), .A1(n2487), .B0(n2484), .B1(n2486), .Y(
DP_OP_453J308_122_681_n510) );
XNOR2X1TS U3515 ( .A(n2523), .B(n1004), .Y(n2488) );
OAI22X1TS U3516 ( .A0(n2484), .A1(n2487), .B0(n2488), .B1(n2486), .Y(
DP_OP_453J308_122_681_n511) );
OAI22X1TS U3517 ( .A0(n2488), .A1(n2487), .B0(n2486), .B1(n2485), .Y(
DP_OP_453J308_122_681_n512) );
OAI22X1TS U3518 ( .A0(n2494), .A1(n2500), .B0(n2493), .B1(n2503), .Y(
DP_OP_453J308_122_681_n521) );
OAI22X1TS U3519 ( .A0(n2496), .A1(n2500), .B0(n2494), .B1(n2503), .Y(
DP_OP_453J308_122_681_n522) );
OAI22X1TS U3520 ( .A0(n2496), .A1(n2503), .B0(n2499), .B1(n2500), .Y(
DP_OP_453J308_122_681_n523) );
OAI22X1TS U3521 ( .A0(n2499), .A1(n2503), .B0(n2502), .B1(n2500), .Y(
DP_OP_453J308_122_681_n524) );
OAI22X1TS U3522 ( .A0(n2502), .A1(n2503), .B0(n2501), .B1(n2500), .Y(
DP_OP_453J308_122_681_n525) );
NOR2BX1TS U3523 ( .AN(n952), .B(n2503), .Y(DP_OP_453J308_122_681_n529) );
XNOR2X1TS U3524 ( .A(n2514), .B(n999), .Y(n2517) );
OAI22X1TS U3525 ( .A0(n2517), .A1(n2526), .B0(n2515), .B1(n2527), .Y(
DP_OP_453J308_122_681_n536) );
XNOR2X1TS U3526 ( .A(n2516), .B(n999), .Y(n2519) );
OAI22X1TS U3527 ( .A0(n2519), .A1(n2526), .B0(n2517), .B1(n2527), .Y(
DP_OP_453J308_122_681_n537) );
OAI22X1TS U3528 ( .A0(n2519), .A1(n2527), .B0(n2518), .B1(n2526), .Y(
DP_OP_453J308_122_681_n538) );
OAI22X1TS U3529 ( .A0(n2521), .A1(n2527), .B0(n2524), .B1(n2526), .Y(
DP_OP_453J308_122_681_n540) );
XNOR2X1TS U3530 ( .A(n2523), .B(n999), .Y(n2528) );
OAI22X1TS U3531 ( .A0(n2524), .A1(n2527), .B0(n2528), .B1(n2526), .Y(
DP_OP_453J308_122_681_n541) );
INVX2TS U3532 ( .A(n2955), .Y(DP_OP_453J308_122_681_n424) );
INVX2TS U3533 ( .A(n2550), .Y(n2552) );
NAND2X1TS U3534 ( .A(n2552), .B(n2551), .Y(n2553) );
NAND2X1TS U3535 ( .A(n1078), .B(n2557), .Y(n2558) );
INVX2TS U3536 ( .A(n2751), .Y(DP_OP_453J308_122_681_n426) );
INVX2TS U3537 ( .A(n2716), .Y(DP_OP_453J308_122_681_n427) );
INVX2TS U3538 ( .A(n2563), .Y(n2573) );
OAI21X1TS U3539 ( .A0(n2573), .A1(n2569), .B0(n2570), .Y(n2568) );
NAND2X1TS U3540 ( .A(n2566), .B(n2565), .Y(n2567) );
INVX2TS U3541 ( .A(n2715), .Y(DP_OP_453J308_122_681_n428) );
INVX2TS U3542 ( .A(n2569), .Y(n2571) );
NAND2X1TS U3543 ( .A(n2571), .B(n2570), .Y(n2572) );
INVX2TS U3544 ( .A(n2760), .Y(DP_OP_453J308_122_681_n429) );
INVX2TS U3545 ( .A(n2574), .Y(n2576) );
NAND2X1TS U3546 ( .A(n2576), .B(n2575), .Y(n2577) );
INVX2TS U3547 ( .A(n2770), .Y(DP_OP_453J308_122_681_n430) );
NAND2X1TS U3548 ( .A(n1047), .B(n2579), .Y(n2581) );
INVX2TS U3549 ( .A(n2759), .Y(DP_OP_453J308_122_681_n431) );
INVX2TS U3550 ( .A(n2587), .Y(DP_OP_453J308_122_681_n788) );
INVX2TS U3551 ( .A(n2588), .Y(DP_OP_453J308_122_681_n789) );
INVX2TS U3552 ( .A(n2589), .Y(DP_OP_453J308_122_681_n790) );
INVX2TS U3553 ( .A(n2590), .Y(DP_OP_453J308_122_681_n791) );
INVX2TS U3554 ( .A(n2591), .Y(DP_OP_453J308_122_681_n792) );
INVX2TS U3555 ( .A(n2593), .Y(DP_OP_453J308_122_681_n794) );
NOR4X1TS U3556 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n3833) );
NOR4X1TS U3557 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3835) );
NOR4X1TS U3558 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3834) );
NOR4X1TS U3559 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n3832) );
OR4X2TS U3560 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n2669) );
NOR4X1TS U3561 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n2669),
.Y(n3828) );
INVX2TS U3562 ( .A(Data_2[19]), .Y(n2672) );
BUFX4TS U3563 ( .A(n2681), .Y(n3594) );
NAND2X1TS U3564 ( .A(FPSENCOS_cont_var_out[1]), .B(n3700), .Y(n2670) );
AOI22X1TS U3565 ( .A0(n3594), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n3503),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n2671) );
NAND2X1TS U3566 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n3481) );
NAND2X1TS U3567 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n2691) );
INVX2TS U3568 ( .A(Data_2[29]), .Y(n2675) );
AOI22X1TS U3569 ( .A0(n3594), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n2674) );
NAND2X1TS U3570 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n2678) );
INVX2TS U3571 ( .A(Data_2[28]), .Y(n2677) );
AOI22X1TS U3572 ( .A0(n3594), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n3503),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n2676) );
INVX2TS U3573 ( .A(Data_2[27]), .Y(n2680) );
AOI22X1TS U3574 ( .A0(n3594), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n3503),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n2679) );
INVX2TS U3575 ( .A(Data_2[13]), .Y(n2683) );
BUFX4TS U3576 ( .A(n3531), .Y(n3585) );
AOI22X1TS U3577 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n2682) );
NAND2X1TS U3578 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n2689) );
INVX2TS U3579 ( .A(Data_2[16]), .Y(n2685) );
AOI22X1TS U3580 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n2684) );
NAND2X1TS U3581 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n2708) );
INVX2TS U3582 ( .A(Data_2[14]), .Y(n2687) );
AOI22X1TS U3583 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n2686) );
NAND2X1TS U3584 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n2711) );
INVX2TS U3585 ( .A(Data_2[17]), .Y(n3927) );
AOI22X1TS U3586 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n2688) );
NAND2X1TS U3587 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n2696) );
INVX2TS U3588 ( .A(Data_2[18]), .Y(n3928) );
AOI22X1TS U3589 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n3503),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n2690) );
INVX2TS U3590 ( .A(Data_2[22]), .Y(n2693) );
AOI22X1TS U3591 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n3503),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n2692) );
INVX2TS U3592 ( .A(Data_2[20]), .Y(n2695) );
AOI22X1TS U3593 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n3503),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n2694) );
INVX2TS U3594 ( .A(Data_2[15]), .Y(n2698) );
AOI22X1TS U3595 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n2697) );
INVX2TS U3596 ( .A(Data_2[7]), .Y(n3926) );
AOI22X1TS U3597 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n2699) );
NAND2X1TS U3598 ( .A(n3500), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n2705) );
XNOR2X2TS U3599 ( .A(DP_OP_26J308_123_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n2704) );
OR4X2TS U3600 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n2700) );
OR4X2TS U3601 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n2700), .Y(n2701) );
NOR3X6TS U3602 ( .A(n2704), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n2701),
.Y(n3931) );
AND4X1TS U3603 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n2702) );
AND4X1TS U3604 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n2702), .Y(n2703) );
INVX2TS U3605 ( .A(Data_2[11]), .Y(n2707) );
BUFX4TS U3606 ( .A(n3531), .Y(n3566) );
AOI22X1TS U3607 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n2706) );
INVX2TS U3608 ( .A(Data_2[3]), .Y(n2710) );
AOI22X1TS U3609 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2709) );
INVX2TS U3610 ( .A(Data_2[5]), .Y(n2713) );
AOI22X1TS U3611 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2673),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n2712) );
NOR2X2TS U3612 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n1070), .Y(n2897) );
NOR2X1TS U3613 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3319), .Y(n2813) );
NOR4X1TS U3614 ( .A(n2718), .B(n2717), .C(n2716), .D(n2715), .Y(n2776) );
INVX2TS U3615 ( .A(n2719), .Y(n2721) );
NAND2X1TS U3616 ( .A(n2721), .B(n2720), .Y(n2723) );
NAND2X1TS U3617 ( .A(n1065), .B(n2724), .Y(n2726) );
XNOR2X1TS U3618 ( .A(n2726), .B(n2725), .Y(n2738) );
INVX2TS U3619 ( .A(n2727), .Y(n2729) );
NAND2X1TS U3620 ( .A(n2729), .B(n2728), .Y(n2731) );
INVX2TS U3621 ( .A(n2732), .Y(n2734) );
NAND2X1TS U3622 ( .A(n2734), .B(n2733), .Y(n2735) );
XOR2X1TS U3623 ( .A(n2735), .B(n2953), .Y(n2736) );
NOR4X1TS U3624 ( .A(n2739), .B(n2738), .C(n2737), .D(n2736), .Y(n2752) );
INVX2TS U3625 ( .A(n2740), .Y(n2742) );
INVX2TS U3626 ( .A(n2744), .Y(n2746) );
NAND2X1TS U3627 ( .A(n2746), .B(n2745), .Y(n2748) );
NOR4BX1TS U3628 ( .AN(n2752), .B(n2751), .C(n2750), .D(n2749), .Y(n2775) );
INVX2TS U3629 ( .A(n2753), .Y(n2755) );
NOR4X1TS U3630 ( .A(n2761), .B(n2760), .C(n2759), .D(n2758), .Y(n2774) );
NAND2X1TS U3631 ( .A(n1080), .B(n2765), .Y(n2767) );
XNOR2X1TS U3632 ( .A(n2767), .B(n2766), .Y(n2771) );
INVX2TS U3633 ( .A(n2768), .Y(n2769) );
NOR4X1TS U3634 ( .A(n2772), .B(n2771), .C(n2770), .D(n2769), .Y(n2773) );
BUFX4TS U3635 ( .A(n3734), .Y(n3084) );
OR2X2TS U3636 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3734), .Y(n3066) );
INVX4TS U3637 ( .A(n3066), .Y(n3881) );
NAND2X2TS U3638 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n3170) );
INVX2TS U3639 ( .A(n2777), .Y(n3159) );
NOR2X1TS U3640 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n3159), .Y(n2797) );
OAI21X1TS U3641 ( .A0(n2781), .A1(n3746), .B0(n3157), .Y(n2796) );
NOR2X2TS U3642 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n2788), .Y(n3166) );
AOI21X1TS U3643 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3739), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2779) );
NOR3X2TS U3644 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n995), .C(n3152), .Y(
n3149) );
OAI22X1TS U3645 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n3161), .B0(n2779),
.B1(n3169), .Y(n2780) );
AOI211X1TS U3646 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n2797), .B0(n2796), .C0(n2780), .Y(n3151) );
NOR2X2TS U3647 ( .A(n3745), .B(n2782), .Y(n3154) );
AOI22X1TS U3648 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n2783), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n3166), .Y(n2786) );
NOR2X1TS U3649 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n2792) );
AOI32X1TS U3650 ( .A0(n2793), .A1(n2792), .A2(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B0(n2791), .B1(n2792), .Y(n2800) );
NOR2X1TS U3651 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3318), .Y(n2814) );
INVX2TS U3652 ( .A(n2814), .Y(n2889) );
INVX2TS U3653 ( .A(n3639), .Y(n865) );
NAND2X1TS U3654 ( .A(n3689), .B(FPSENCOS_cont_iter_out[3]), .Y(n2892) );
INVX2TS U3655 ( .A(n2892), .Y(n2812) );
NAND2X1TS U3656 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n3644) );
INVX2TS U3657 ( .A(n3644), .Y(n3643) );
NOR2X1TS U3658 ( .A(n2812), .B(n3643), .Y(n3640) );
OAI211X1TS U3659 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3697), .B0(n3689),
.C0(n3743), .Y(n3642) );
OAI21XLTS U3660 ( .A0(n3640), .A1(n3743), .B0(n3642), .Y(n854) );
OR2X1TS U3661 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2805) );
NAND2X1TS U3662 ( .A(n2806), .B(n1088), .Y(n2802) );
NOR2X1TS U3663 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n3374) );
NAND2X1TS U3664 ( .A(n3825), .B(n3374), .Y(n3457) );
OR2X1TS U3665 ( .A(n3456), .B(FPMULT_exp_oper_result[7]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2X1TS U3666 ( .A(n3598), .B(n3689), .Y(n2891) );
OAI31X1TS U3667 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n3689), .B0(n2891), .Y(n856) );
OAI31X4TS U3668 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n3697), .B0(n865), .Y(n3641) );
OAI21XLTS U3669 ( .A0(n3639), .A1(n3743), .B0(n3641), .Y(n859) );
OAI21XLTS U3670 ( .A0(n3743), .A1(n3641), .B0(n2892), .Y(n860) );
AOI22X1TS U3671 ( .A0(n3924), .A1(n3923), .B0(r_mode[0]), .B1(r_mode[1]),
.Y(n2801) );
OAI221X1TS U3672 ( .A0(n3807), .A1(r_mode[1]), .B0(n3925), .B1(r_mode[0]),
.C0(n2801), .Y(n2941) );
NAND2BX1TS U3673 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n2804),
.Y(n2884) );
NOR2X1TS U3674 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2802),
.Y(n2945) );
NAND3BXLTS U3675 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n2945), .Y(n3001) );
NOR2XLTS U3676 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2803) );
NAND4X1TS U3677 ( .A(n2804), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n2803), .D(n3749), .Y(n3478) );
NAND2X1TS U3678 ( .A(n3001), .B(n3478), .Y(FPSENCOS_enab_d_ff_RB1) );
BUFX3TS U3679 ( .A(n3894), .Y(n3884) );
CLKBUFX2TS U3680 ( .A(n3885), .Y(n3911) );
BUFX3TS U3681 ( .A(n3913), .Y(n3889) );
CLKBUFX2TS U3682 ( .A(n2888), .Y(n2810) );
BUFX3TS U3683 ( .A(n3843), .Y(n3841) );
BUFX3TS U3684 ( .A(n3846), .Y(n3870) );
BUFX3TS U3685 ( .A(n3915), .Y(n3906) );
BUFX3TS U3686 ( .A(n3847), .Y(n3867) );
BUFX3TS U3687 ( .A(n3915), .Y(n3905) );
CLKBUFX2TS U3688 ( .A(n3916), .Y(n3910) );
CLKBUFX2TS U3689 ( .A(n3915), .Y(n3909) );
BUFX3TS U3690 ( .A(n3913), .Y(n3903) );
BUFX3TS U3691 ( .A(n3848), .Y(n3858) );
BUFX3TS U3692 ( .A(n3847), .Y(n3852) );
BUFX3TS U3693 ( .A(n3843), .Y(n3840) );
BUFX3TS U3694 ( .A(n3844), .Y(n3838) );
BUFX3TS U3695 ( .A(n3846), .Y(n3862) );
BUFX3TS U3696 ( .A(n3844), .Y(n3851) );
BUFX3TS U3697 ( .A(n3846), .Y(n3859) );
BUFX3TS U3698 ( .A(n3845), .Y(n3868) );
BUFX3TS U3699 ( .A(n3847), .Y(n3865) );
BUFX3TS U3700 ( .A(n3847), .Y(n3860) );
BUFX3TS U3701 ( .A(n3844), .Y(n3856) );
BUFX3TS U3702 ( .A(n3845), .Y(n3855) );
CLKBUFX2TS U3703 ( .A(n3915), .Y(n3908) );
BUFX3TS U3704 ( .A(n3845), .Y(n3850) );
BUFX3TS U3705 ( .A(n3843), .Y(n3861) );
BUFX3TS U3706 ( .A(n2809), .Y(n3857) );
BUFX3TS U3707 ( .A(n3891), .Y(n3896) );
BUFX3TS U3708 ( .A(n2809), .Y(n3839) );
BUFX3TS U3709 ( .A(n2809), .Y(n3854) );
OR2X1TS U3710 ( .A(n3456), .B(FPMULT_exp_oper_result[6]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OR2X1TS U3711 ( .A(n3458), .B(FPMULT_exp_oper_result[4]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
OR2X1TS U3712 ( .A(n3456), .B(FPMULT_exp_oper_result[1]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
OR2X1TS U3713 ( .A(n3458), .B(FPMULT_exp_oper_result[5]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
OR2X1TS U3714 ( .A(n3456), .B(FPMULT_exp_oper_result[3]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OR2X1TS U3715 ( .A(n3458), .B(FPMULT_exp_oper_result[2]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
INVX2TS U3716 ( .A(n2897), .Y(n2895) );
OAI32X1TS U3717 ( .A0(n3704), .A1(n3318), .A2(n2896), .B0(
FPMULT_FS_Module_state_reg[1]), .B1(n2895), .Y(
FPMULT_FS_Module_state_next[2]) );
NAND2X1TS U3718 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2897), .Y(n2900) );
NAND2X1TS U3719 ( .A(n2894), .B(n2900), .Y(FPMULT_FSM_barrel_shifter_load)
);
NAND2X1TS U3720 ( .A(n2916), .B(n3644), .Y(n851) );
NAND2X4TS U3721 ( .A(n2814), .B(n2813), .Y(n3883) );
INVX4TS U3722 ( .A(n3883), .Y(n3648) );
NOR2BX2TS U3723 ( .AN(n981), .B(n2815), .Y(n2849) );
NAND2BX2TS U3724 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2970) );
NAND3X2TS U3725 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n3755), .Y(n2860) );
NAND2X1TS U3726 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n3759), .Y(n2846)
);
AOI22X1TS U3727 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n2821) );
NOR2BX1TS U3728 ( .AN(n2815), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n2819) );
AOI22X1TS U3729 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[32]), .B0(n945),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n2820) );
OAI211X1TS U3730 ( .A0(n2992), .A1(n3755), .B0(n2821), .C0(n2820), .Y(n2844)
);
NAND2X1TS U3731 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n981), .Y(n2837)
);
AOI21X1TS U3732 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2844), .B0(n2822), .Y(
n2823) );
OAI21X1TS U3733 ( .A0(n2977), .A1(n2816), .B0(n2823), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
CLKAND2X2TS U3734 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
NOR2X2TS U3735 ( .A(n2969), .B(n3759), .Y(n2848) );
OAI22X1TS U3736 ( .A0(n2970), .A1(n3716), .B0(n2846), .B1(n3787), .Y(n2825)
);
AOI22X1TS U3737 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[31]), .B0(n945),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n2827) );
AOI22X1TS U3738 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n2826) );
OAI211X1TS U3739 ( .A0(n2869), .A1(n3755), .B0(n2827), .C0(n2826), .Y(n2924)
);
AOI21X1TS U3740 ( .A0(n978), .A1(n2924), .B0(n2822), .Y(n2828) );
OAI21X1TS U3741 ( .A0(n2926), .A1(n2816), .B0(n2828), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
CLKAND2X2TS U3742 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AOI22X1TS U3743 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n2831) );
AOI22X1TS U3744 ( .A0(n942), .A1(n975), .B0(n945), .B1(
FPADDSUB_Data_array_SWR[29]), .Y(n2830) );
OAI211X1TS U3745 ( .A0(n2995), .A1(n3755), .B0(n2831), .C0(n2830), .Y(n2835)
);
AOI21X1TS U3746 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2835), .B0(n2822), .Y(
n2832) );
OAI21X1TS U3747 ( .A0(n2987), .A1(n2816), .B0(n2832), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
CLKAND2X2TS U3748 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AOI21X1TS U3749 ( .A0(n977), .A1(n2835), .B0(n2834), .Y(n2836) );
OAI21X1TS U3750 ( .A0(n2833), .A1(n2987), .B0(n2836), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
CLKAND2X2TS U3751 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
INVX2TS U3752 ( .A(n2837), .Y(n2862) );
AOI22X1TS U3753 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n2838) );
AOI211X1TS U3754 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n940), .B0(n2862),
.C0(n2839), .Y(n2865) );
OR2X1TS U3755 ( .A(n2848), .B(n2862), .Y(n2858) );
AOI211X1TS U3756 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[48]), .B0(n2858),
.C0(n2840), .Y(n2866) );
AOI22X1TS U3757 ( .A0(n978), .A1(n2865), .B0(n2866), .B1(n977), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U3758 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
AOI22X1TS U3759 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n2842) );
AOI22X1TS U3760 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n945),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n2841) );
OAI211X1TS U3761 ( .A0(n3755), .A1(n2926), .B0(n2842), .C0(n2841), .Y(n2867)
);
AOI21X1TS U3762 ( .A0(n950), .A1(n2867), .B0(n2834), .Y(n2843) );
OAI21X1TS U3763 ( .A0(n2869), .A1(n2833), .B0(n2843), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
CLKAND2X2TS U3764 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
AOI21X1TS U3765 ( .A0(n950), .A1(n2844), .B0(n2834), .Y(n2845) );
OAI21X1TS U3766 ( .A0(n2977), .A1(n2833), .B0(n2845), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
CLKAND2X2TS U3767 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
OAI22X1TS U3768 ( .A0(n2970), .A1(n3790), .B0(n2846), .B1(n3720), .Y(n2847)
);
AOI22X1TS U3769 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n940),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n2851) );
AOI22X1TS U3770 ( .A0(n944), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n2818),
.B1(FPADDSUB_Data_array_SWR[46]), .Y(n2850) );
OAI211X1TS U3771 ( .A0(n3755), .A1(n2923), .B0(n2851), .C0(n2850), .Y(n2863)
);
AOI21X1TS U3772 ( .A0(n950), .A1(n2863), .B0(n2834), .Y(n2852) );
OAI21X1TS U3773 ( .A0(n2919), .A1(n2833), .B0(n2852), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
CLKAND2X2TS U3774 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
AOI22X1TS U3775 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2853) );
AOI211X1TS U3776 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2862),
.C0(n2854), .Y(n2872) );
AOI22X1TS U3777 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2855) );
AOI211X1TS U3778 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n2862),
.C0(n2856), .Y(n2873) );
AOI22X1TS U3779 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2872), .B0(n2873),
.B1(n977), .Y(FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U3780 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
AOI211X1TS U3781 ( .A0(FPADDSUB_Data_array_SWR[47]), .A1(n940), .B0(n2858),
.C0(n2857), .Y(n2870) );
AOI22X1TS U3782 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n2859) );
AOI211X1TS U3783 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n2862),
.C0(n2861), .Y(n2871) );
AOI22X1TS U3784 ( .A0(n978), .A1(n2870), .B0(n2871), .B1(n977), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U3785 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
AOI21X1TS U3786 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2863), .B0(n2822), .Y(
n2864) );
OAI21X1TS U3787 ( .A0(n2919), .A1(n2816), .B0(n2864), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
CLKAND2X2TS U3788 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AOI22X1TS U3789 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2866), .B0(n2865),
.B1(n950), .Y(FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U3790 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
AOI21X1TS U3791 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2867), .B0(n2822), .Y(
n2868) );
OAI21X1TS U3792 ( .A0(n2869), .A1(n2816), .B0(n2868), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
CLKAND2X2TS U3793 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AOI22X1TS U3794 ( .A0(n978), .A1(n2871), .B0(n2870), .B1(n977), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U3795 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
AOI22X1TS U3796 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2873), .B0(n2872),
.B1(n977), .Y(FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U3797 ( .A(n2824), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
NOR2XLTS U3798 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n2874) );
OR2X2TS U3799 ( .A(FPMULT_FSM_selector_B[1]), .B(n3750), .Y(n2881) );
XOR2X1TS U3800 ( .A(n2714), .B(n2875), .Y(DP_OP_234J308_126_8543_n22) );
OAI2BB1X1TS U3801 ( .A0N(FPMULT_Op_MY[24]), .A1N(n3744), .B0(n2881), .Y(
n2876) );
XOR2X1TS U3802 ( .A(n2714), .B(n2876), .Y(DP_OP_234J308_126_8543_n21) );
OAI2BB1X1TS U3803 ( .A0N(FPMULT_Op_MY[25]), .A1N(n3744), .B0(n2881), .Y(
n2877) );
XOR2X1TS U3804 ( .A(n2714), .B(n2877), .Y(DP_OP_234J308_126_8543_n20) );
OAI2BB1X1TS U3805 ( .A0N(FPMULT_Op_MY[26]), .A1N(n3744), .B0(n2881), .Y(
n2878) );
XOR2X1TS U3806 ( .A(n2714), .B(n2878), .Y(DP_OP_234J308_126_8543_n19) );
OAI2BB1X1TS U3807 ( .A0N(FPMULT_Op_MY[27]), .A1N(n3744), .B0(n2881), .Y(
n2879) );
XOR2X1TS U3808 ( .A(n2714), .B(n2879), .Y(DP_OP_234J308_126_8543_n18) );
OAI2BB1X1TS U3809 ( .A0N(FPMULT_Op_MY[28]), .A1N(n3744), .B0(n2881), .Y(
n2880) );
XOR2X1TS U3810 ( .A(n2714), .B(n2880), .Y(DP_OP_234J308_126_8543_n17) );
OAI2BB1X1TS U3811 ( .A0N(FPMULT_Op_MY[29]), .A1N(n3744), .B0(n2881), .Y(
n2882) );
XOR2X1TS U3812 ( .A(n2714), .B(n2882), .Y(DP_OP_234J308_126_8543_n16) );
NOR3BX1TS U3813 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n2883) );
XOR2X1TS U3814 ( .A(n2714), .B(n2883), .Y(DP_OP_234J308_126_8543_n15) );
NOR2X1TS U3815 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n2884),
.Y(n2944) );
NAND3BX1TS U3816 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n2944), .Y(n3474) );
INVX2TS U3817 ( .A(n3474), .Y(n2887) );
BUFX4TS U3818 ( .A(n2885), .Y(n3638) );
NAND2X1TS U3819 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3318), .Y(n2939) );
NOR3X2TS U3820 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3319), .C(n2939),
.Y(n3649) );
AOI22X1TS U3821 ( .A0(n3638), .A1(ready_add_subt), .B0(n3649), .B1(n3632),
.Y(n2886) );
OAI2BB1X1TS U3822 ( .A0N(n2887), .A1N(n3599), .B0(n2886), .Y(operation_ready) );
INVX4TS U3823 ( .A(n3648), .Y(n3876) );
INVX4TS U3824 ( .A(n3648), .Y(n3871) );
INVX4TS U3825 ( .A(n3648), .Y(n3872) );
INVX4TS U3826 ( .A(n3648), .Y(n3873) );
INVX4TS U3827 ( .A(n3648), .Y(n3877) );
INVX4TS U3828 ( .A(n3648), .Y(n3879) );
INVX4TS U3829 ( .A(n3648), .Y(n3880) );
INVX4TS U3830 ( .A(n3648), .Y(n3875) );
BUFX3TS U3831 ( .A(n2888), .Y(n3846) );
INVX4TS U3832 ( .A(n3648), .Y(n3874) );
BUFX3TS U3833 ( .A(n2888), .Y(n3848) );
BUFX3TS U3834 ( .A(n2888), .Y(n3847) );
BUFX3TS U3835 ( .A(n2888), .Y(n3845) );
BUFX3TS U3836 ( .A(n2888), .Y(n3844) );
BUFX3TS U3837 ( .A(n2888), .Y(n3843) );
NAND2X1TS U3838 ( .A(n3779), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1036_CI) );
OAI21XLTS U3839 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3779), .B0(
intadd_1036_CI), .Y(FPSENCOS_sh_exp_x[0]) );
NAND2X1TS U3840 ( .A(n3778), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1037_CI) );
OAI21XLTS U3841 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3778), .B0(
intadd_1037_CI), .Y(FPSENCOS_sh_exp_y[0]) );
NAND2X1TS U3842 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n1028), .Y(n2899) );
NAND2X1TS U3843 ( .A(n3704), .B(n3319), .Y(n2903) );
NOR2XLTS U3844 ( .A(n2903), .B(n2889), .Y(FPMULT_FSM_first_phase_load) );
NAND2X1TS U3845 ( .A(n933), .B(n920), .Y(n3207) );
OAI21XLTS U3846 ( .A0(n920), .A1(n933), .B0(n3207), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
INVX2TS U3847 ( .A(FPMULT_Sgf_normalized_result[9]), .Y(n3199) );
NOR2XLTS U3848 ( .A(n3199), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
INVX2TS U3849 ( .A(FPMULT_Sgf_normalized_result[19]), .Y(n3184) );
NOR2XLTS U3850 ( .A(n3184), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
INVX2TS U3851 ( .A(FPMULT_Sgf_normalized_result[11]), .Y(n3196) );
NOR2XLTS U3852 ( .A(n3196), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
NOR2XLTS U3853 ( .A(n3193), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
INVX2TS U3854 ( .A(FPMULT_Sgf_normalized_result[15]), .Y(n3190) );
INVX2TS U3855 ( .A(FPMULT_Sgf_normalized_result[17]), .Y(n3187) );
NOR2XLTS U3856 ( .A(n3187), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
INVX2TS U3857 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n3181) );
NOR2XLTS U3858 ( .A(n3181), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
INVX2TS U3859 ( .A(FPMULT_Sgf_normalized_result[3]), .Y(n3205) );
NOR2XLTS U3860 ( .A(n3205), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
NOR2XLTS U3861 ( .A(n1087), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
NOR2XLTS U3862 ( .A(n933), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
INVX2TS U3863 ( .A(FPMULT_Sgf_normalized_result[7]), .Y(n3202) );
NOR2XLTS U3864 ( .A(n3202), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
INVX2TS U3865 ( .A(intadd_1038_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
NOR2X1TS U3866 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n2893) );
NOR2XLTS U3867 ( .A(n3598), .B(n2893), .Y(FPSENCOS_ITER_CONT_N3) );
OAI21XLTS U3868 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n3651), .B0(n3373), .Y(n874) );
INVX2TS U3869 ( .A(intadd_1038_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
INVX2TS U3870 ( .A(n2890), .Y(n2904) );
NOR3XLTS U3871 ( .A(n3704), .B(n2896), .C(n2904), .Y(
FPMULT_FSM_final_result_load) );
OAI21XLTS U3872 ( .A0(n3639), .A1(FPSENCOS_cont_iter_out[1]), .B0(n2916),
.Y(n864) );
OAI211XLTS U3873 ( .A0(n2893), .A1(n2892), .B0(n2891), .C0(n3375), .Y(n855)
);
OAI22X1TS U3874 ( .A0(n3319), .A1(n2895), .B0(n2894), .B1(n3806), .Y(
FPMULT_FSM_load_second_step) );
OR2X1TS U3875 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
INVX2TS U3876 ( .A(intadd_1038_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
INVX2TS U3877 ( .A(n2903), .Y(n2940) );
CLKAND2X2TS U3878 ( .A(n2940), .B(n2897), .Y(n3176) );
AOI22X1TS U3879 ( .A0(n3176), .A1(n3723), .B0(n2714), .B1(n1071), .Y(n2898)
);
OAI21XLTS U3880 ( .A0(n3319), .A1(n3318), .B0(n2898), .Y(
FPMULT_FS_Module_state_next[0]) );
NOR2X1TS U3881 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_1037_n1), .Y(n3679) );
OR3X1TS U3882 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_1037_n1), .Y(n3678) );
NOR2X1TS U3883 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1036_n1), .Y(n3682) );
OR3X1TS U3884 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1036_n1), .Y(n3681) );
OAI21XLTS U3885 ( .A0(n3682), .A1(n3822), .B0(n3681), .Y(
FPSENCOS_sh_exp_x[5]) );
INVX2TS U3886 ( .A(n2899), .Y(intadd_1038_CI) );
INVX2TS U3887 ( .A(n2714), .Y(n3172) );
AOI22X1TS U3888 ( .A0(n910), .A1(n2906), .B0(n3394), .B1(n3882), .Y(n2902)
);
NAND2X1TS U3889 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n3691), .Y(n2905) );
OAI21XLTS U3890 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n3691), .B0(n2905),
.Y(n2901) );
XOR2XLTS U3891 ( .A(n2902), .B(n2901), .Y(FPADDSUB_Raw_mant_SGF[3]) );
NOR2X1TS U3892 ( .A(n2904), .B(n2903), .Y(FPMULT_FSM_adder_round_norm_load)
);
NAND2X1TS U3893 ( .A(FPSENCOS_cont_iter_out[2]), .B(n3598), .Y(n3597) );
CLKAND2X2TS U3894 ( .A(n3597), .B(n3690), .Y(n857) );
NOR2X1TS U3895 ( .A(n3690), .B(n3597), .Y(n3003) );
OAI21XLTS U3896 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n3644), .Y(
n849) );
OAI21XLTS U3897 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3641), .B0(n2916),
.Y(n862) );
NOR2X1TS U3898 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n3726), .Y(n2909) );
AOI22X1TS U3899 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n3724), .B0(n2906), .B1(
n2905), .Y(n2910) );
AOI222X4TS U3900 ( .A0(n3691), .A1(n3394), .B0(n3691), .B1(n3724), .C0(n3394), .C1(n3724), .Y(n2912) );
BUFX3TS U3901 ( .A(n3882), .Y(n3052) );
AOI22X1TS U3902 ( .A0(n910), .A1(n2910), .B0(n2912), .B1(n3052), .Y(n2908)
);
OAI31X1TS U3903 ( .A0(n2909), .A1(n2908), .A2(n2911), .B0(n2907), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
BUFX3TS U3904 ( .A(n3463), .Y(n3464) );
BUFX3TS U3905 ( .A(n3464), .Y(n3461) );
OR2X1TS U3906 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n3462), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X1TS U3907 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n3462), .Y(
FPSENCOS_first_mux_X[26]) );
OR2X1TS U3908 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n3462), .Y(
FPSENCOS_first_mux_X[13]) );
OR2X1TS U3909 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n3462), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X1TS U3910 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n3462), .Y(
FPSENCOS_first_mux_X[17]) );
OR2X1TS U3911 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n3462), .Y(
FPSENCOS_first_mux_X[29]) );
OR2X1TS U3912 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n3462), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X1TS U3913 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n3462), .Y(
FPSENCOS_first_mux_X[24]) );
OR2X1TS U3914 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n3462), .Y(
FPSENCOS_first_mux_X[20]) );
OR2X1TS U3915 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n3462), .Y(
FPSENCOS_first_mux_X[14]) );
OR2X1TS U3916 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n3462), .Y(
FPSENCOS_first_mux_X[27]) );
OR2X1TS U3917 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n3462), .Y(
FPSENCOS_first_mux_X[28]) );
OAI22X1TS U3918 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n3726), .B0(n2911),
.B1(n2910), .Y(n2927) );
AOI22X1TS U3919 ( .A0(n910), .A1(n2927), .B0(n2929), .B1(n3052), .Y(n2914)
);
NAND2X1TS U3920 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n3692), .Y(n2928) );
XOR2XLTS U3921 ( .A(n2914), .B(n2913), .Y(FPADDSUB_Raw_mant_SGF[5]) );
INVX2TS U3922 ( .A(n3461), .Y(n2915) );
OR2X1TS U3923 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n2915), .Y(
FPSENCOS_first_mux_X[1]) );
OR2X1TS U3924 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n2915), .Y(
FPSENCOS_first_mux_X[10]) );
OR2X1TS U3925 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n2915), .Y(
FPSENCOS_first_mux_X[12]) );
OR2X1TS U3926 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n2915), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U3927 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n2915), .Y(
FPSENCOS_first_mux_X[3]) );
OR2X1TS U3928 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n2915), .Y(
FPSENCOS_first_mux_X[7]) );
OR2X1TS U3929 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n2915), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U3930 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n2915), .Y(
FPSENCOS_first_mux_X[2]) );
OAI21X1TS U3931 ( .A0(n3639), .A1(n3743), .B0(n2916), .Y(n863) );
OR2X1TS U3932 ( .A(n863), .B(n3643), .Y(n850) );
AOI22X1TS U3933 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n940),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n2918) );
AOI22X1TS U3934 ( .A0(n945), .A1(FPADDSUB_Data_array_SWR[26]), .B0(n2818),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2917) );
OAI211X1TS U3935 ( .A0(n2919), .A1(n3755), .B0(n2918), .C0(n2917), .Y(n2921)
);
AOI21X1TS U3936 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2921), .B0(n2822), .Y(
n2920) );
OAI21XLTS U3937 ( .A0(n2923), .A1(n2816), .B0(n2920), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
AOI21X1TS U3938 ( .A0(n977), .A1(n2921), .B0(n2834), .Y(n2922) );
OAI21XLTS U3939 ( .A0(n2833), .A1(n2923), .B0(n2922), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
AOI21X1TS U3940 ( .A0(n977), .A1(n2924), .B0(n2834), .Y(n2925) );
OAI21XLTS U3941 ( .A0(n2833), .A1(n2926), .B0(n2925), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
NOR2X1TS U3942 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n3728), .Y(n2932) );
AOI22X1TS U3943 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n3727), .B0(n2928), .B1(
n2927), .Y(n2933) );
AOI222X4TS U3944 ( .A0(n2929), .A1(n3692), .B0(n2929), .B1(n3727), .C0(n3692), .C1(n3727), .Y(n2935) );
AOI22X1TS U3945 ( .A0(n910), .A1(n2933), .B0(n2935), .B1(n3052), .Y(n2931)
);
OAI31X1TS U3946 ( .A0(n2932), .A1(n2931), .A2(n2934), .B0(n2930), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
OAI22X1TS U3947 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n3728), .B0(n2934),
.B1(n2933), .Y(n2957) );
AOI22X1TS U3948 ( .A0(n910), .A1(n2957), .B0(n2959), .B1(n3052), .Y(n2937)
);
NAND2X1TS U3949 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n3693), .Y(n2958) );
OAI21XLTS U3950 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n3693), .B0(n2958),
.Y(n2936) );
XOR2XLTS U3951 ( .A(n2937), .B(n2936), .Y(FPADDSUB_Raw_mant_SGF[7]) );
INVX2TS U3952 ( .A(n2938), .Y(n2942) );
AOI22X1TS U3953 ( .A0(n2942), .A1(n2941), .B0(n2940), .B1(n2939), .Y(n2943)
);
OAI31X1TS U3954 ( .A0(n3319), .A1(n3318), .A2(n3704), .B0(n2943), .Y(
FPMULT_FS_Module_state_next[1]) );
OR2X1TS U3955 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
OR2X1TS U3956 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U3957 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X1TS U3958 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U3959 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U3960 ( .A(n3931), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
INVX2TS U3961 ( .A(n3373), .Y(n3653) );
NAND3BX1TS U3962 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n2945),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3482) );
NAND2X1TS U3963 ( .A(n3483), .B(n3482), .Y(n2946) );
AOI22X1TS U3964 ( .A0(n960), .A1(n2946), .B0(begin_operation), .B1(n3638),
.Y(n3650) );
INVX2TS U3965 ( .A(n3651), .Y(n2947) );
NAND2X1TS U3966 ( .A(n1079), .B(n2948), .Y(n2950) );
XNOR2X1TS U3967 ( .A(n2950), .B(n2949), .Y(n2956) );
NOR4X1TS U3968 ( .A(n2956), .B(n1063), .C(n2955), .D(n2954), .Y(n3829) );
NOR2X1TS U3969 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3730), .Y(n2962) );
AOI22X1TS U3970 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n3729), .B0(n2958), .B1(
n2957), .Y(n2963) );
AOI222X4TS U3971 ( .A0(n2959), .A1(n3693), .B0(n2959), .B1(n3729), .C0(n3693), .C1(n3729), .Y(n2965) );
AOI22X1TS U3972 ( .A0(n910), .A1(n2963), .B0(n2965), .B1(n3052), .Y(n2961)
);
OAI31X1TS U3973 ( .A0(n2962), .A1(n2961), .A2(n2964), .B0(n2960), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
OAI22X1TS U3974 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n3730), .B0(n2964),
.B1(n2963), .Y(n3004) );
AOI22X1TS U3975 ( .A0(n910), .A1(n3004), .B0(n3006), .B1(n3052), .Y(n2967)
);
NAND2X1TS U3976 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n3694), .Y(n3005) );
OAI21XLTS U3977 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n3694), .B0(n3005),
.Y(n2966) );
AOI22X1TS U3978 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2973) );
AOI22X1TS U3979 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n945),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n2972) );
OAI211X1TS U3980 ( .A0(n2998), .A1(n3755), .B0(n2973), .C0(n2972), .Y(n2979)
);
AOI21X1TS U3981 ( .A0(n919), .A1(n2979), .B0(n2834), .Y(n2974) );
OAI21X1TS U3982 ( .A0(n2983), .A1(n2833), .B0(n2974), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI22X1TS U3983 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n2976) );
AOI22X1TS U3984 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[36]), .B0(n945),
.B1(n975), .Y(n2975) );
OAI211X1TS U3985 ( .A0(n3755), .A1(n2977), .B0(n2976), .C0(n2975), .Y(n2990)
);
AOI21X1TS U3986 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2990), .B0(n2822), .Y(
n2978) );
OAI21X1TS U3987 ( .A0(n2992), .A1(n2816), .B0(n2978), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI21X1TS U3988 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2979), .B0(n2822), .Y(
n2980) );
OAI21X1TS U3989 ( .A0(n2983), .A1(n2816), .B0(n2980), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AOI22X1TS U3990 ( .A0(n2818), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2982) );
AOI22X1TS U3991 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n945),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n2981) );
OAI211X1TS U3992 ( .A0(n2983), .A1(n3755), .B0(n2982), .C0(n2981), .Y(n2996)
);
AOI21X1TS U3993 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2996), .B0(n2822), .Y(
n2984) );
OAI21X1TS U3994 ( .A0(n2998), .A1(n2816), .B0(n2984), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
AOI22X1TS U3995 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n2818), .B0(
FPADDSUB_Data_array_SWR[39]), .B1(n939), .Y(n2986) );
AOI22X1TS U3996 ( .A0(n942), .A1(FPADDSUB_Data_array_SWR[35]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n944), .Y(n2985) );
OAI211X1TS U3997 ( .A0(n3755), .A1(n2987), .B0(n2986), .C0(n2985), .Y(n2993)
);
AOI21X1TS U3998 ( .A0(n978), .A1(n2993), .B0(n2822), .Y(n2989) );
OAI21X1TS U3999 ( .A0(n2995), .A1(n2816), .B0(n2989), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U4000 ( .A0(n919), .A1(n2990), .B0(n2834), .Y(n2991) );
OAI21X1TS U4001 ( .A0(n2992), .A1(n2833), .B0(n2991), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
AOI21X1TS U4002 ( .A0(n950), .A1(n2993), .B0(n2834), .Y(n2994) );
OAI21X1TS U4003 ( .A0(n2995), .A1(n2833), .B0(n2994), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U4004 ( .A0(n950), .A1(n2996), .B0(n2834), .Y(n2997) );
OAI21X1TS U4005 ( .A0(n2998), .A1(n2833), .B0(n2997), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
NOR2BX1TS U4006 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2999) );
XOR2X1TS U4007 ( .A(n911), .B(n2999), .Y(DP_OP_26J308_123_9022_n15) );
NOR2BX1TS U4008 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3000) );
XOR2X1TS U4009 ( .A(n911), .B(n3000), .Y(DP_OP_26J308_123_9022_n14) );
INVX2TS U4010 ( .A(enab_cont_iter), .Y(n3002) );
OAI21XLTS U4011 ( .A0(n3003), .A1(n3002), .B0(n3001), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
NOR2X1TS U4012 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3732), .Y(n3009) );
AOI22X1TS U4013 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n3731), .B0(n3005), .B1(
n3004), .Y(n3012) );
AOI222X4TS U4014 ( .A0(n3006), .A1(n3694), .B0(n3006), .B1(n3731), .C0(n3694), .C1(n3731), .Y(n3014) );
AOI22X1TS U4015 ( .A0(n910), .A1(n3012), .B0(n3014), .B1(n3052), .Y(n3008)
);
OAI31X1TS U4016 ( .A0(n3009), .A1(n3008), .A2(n3013), .B0(n3007), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
AOI222X1TS U4017 ( .A0(n3010), .A1(Data_2[30]), .B0(n2673), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n3566), .Y(n3011) );
INVX2TS U4018 ( .A(n3011), .Y(add_subt_data2[30]) );
AOI22X1TS U4019 ( .A0(n910), .A1(n3019), .B0(n3021), .B1(n3052), .Y(n3016)
);
NAND2X1TS U4020 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n3735), .Y(n3020) );
AND4X1TS U4021 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n3017) );
AND4X1TS U4022 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n3017), .Y(n3018) );
CLKAND2X2TS U4023 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
NOR2X1TS U4024 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3736), .Y(n3024) );
INVX4TS U4025 ( .A(n3882), .Y(n3426) );
AOI222X4TS U4026 ( .A0(n3021), .A1(n3735), .B0(n3021), .B1(n3695), .C0(n3735), .C1(n3695), .Y(n3027) );
AOI22X1TS U4027 ( .A0(n3426), .A1(n3025), .B0(n3027), .B1(n3052), .Y(n3023)
);
OAI31X1TS U4028 ( .A0(n3024), .A1(n3023), .A2(n3026), .B0(n3022), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
AOI22X1TS U4029 ( .A0(n3426), .A1(n3030), .B0(n3032), .B1(n3052), .Y(n3029)
);
NAND2X1TS U4030 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n3696), .Y(n3031) );
OAI21XLTS U4031 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n3696), .B0(n3031),
.Y(n3028) );
NOR2X1TS U4032 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n3742), .Y(n3035) );
AOI222X4TS U4033 ( .A0(n3032), .A1(n3696), .B0(n3032), .B1(n3738), .C0(n3696), .C1(n3738), .Y(n3038) );
AOI22X1TS U4034 ( .A0(n3426), .A1(n3036), .B0(n3038), .B1(n3052), .Y(n3034)
);
OAI31X1TS U4035 ( .A0(n3035), .A1(n3034), .A2(n3037), .B0(n3033), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
NOR2X1TS U4036 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3751), .Y(n3041) );
NAND2X1TS U4037 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n3698), .Y(n3400) );
AOI222X4TS U4038 ( .A0(n3398), .A1(n3698), .B0(n3398), .B1(n3741), .C0(n3698), .C1(n3741), .Y(n3045) );
AOI22X1TS U4039 ( .A0(n3426), .A1(n3043), .B0(n3045), .B1(n3882), .Y(n3040)
);
OAI31X1TS U4040 ( .A0(n3041), .A1(n3040), .A2(n3044), .B0(n3039), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
AOI22X2TS U4041 ( .A0(n3881), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n3084), .Y(n3068) );
OAI22X2TS U4042 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n3066), .Y(n3057) );
NOR2X1TS U4043 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3754), .Y(n3048) );
NAND2X1TS U4044 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n3701), .Y(n3405) );
AOI222X4TS U4045 ( .A0(n3403), .A1(n3701), .B0(n3403), .B1(n3752), .C0(n3701), .C1(n3752), .Y(n3051) );
AOI22X1TS U4046 ( .A0(n3426), .A1(n3049), .B0(n3051), .B1(n3052), .Y(n3047)
);
OAI31X1TS U4047 ( .A0(n3048), .A1(n3047), .A2(n3050), .B0(n3046), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
NOR2X1TS U4048 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n3758), .Y(n3055) );
NAND2X1TS U4049 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n3757), .Y(n3410) );
AOI222X4TS U4050 ( .A0(n3408), .A1(n3757), .B0(n3408), .B1(n3702), .C0(n3757), .C1(n3702), .Y(n3061) );
AOI22X1TS U4051 ( .A0(n3426), .A1(n3059), .B0(n3061), .B1(n3052), .Y(n3054)
);
OAI31X1TS U4052 ( .A0(n3055), .A1(n3054), .A2(n3060), .B0(n3053), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
INVX2TS U4053 ( .A(n3057), .Y(n3067) );
NOR2X4TS U4054 ( .A(n3068), .B(n3067), .Y(n3141) );
AOI22X1TS U4055 ( .A0(n3881), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n958), .Y(n3113) );
NOR2X4TS U4056 ( .A(n3057), .B(n3068), .Y(n3107) );
INVX2TS U4057 ( .A(n3099), .Y(n3111) );
AOI22X1TS U4058 ( .A0(n3881), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n3107),
.B1(n3111), .Y(n3058) );
NOR3X2TS U4059 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n3206) );
NOR2X2TS U4060 ( .A(n3205), .B(n3206), .Y(n3209) );
NOR2X2TS U4061 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n3209), .Y(n3208)
);
NOR2X2TS U4062 ( .A(n1087), .B(n3208), .Y(n3204) );
NOR2X2TS U4063 ( .A(n3202), .B(n3203), .Y(n3201) );
NOR2X2TS U4064 ( .A(n3199), .B(n3200), .Y(n3198) );
NOR2X2TS U4065 ( .A(n3196), .B(n3197), .Y(n3195) );
NOR2X2TS U4066 ( .A(n3193), .B(n3194), .Y(n3192) );
NOR2X2TS U4067 ( .A(n3190), .B(n3191), .Y(n3189) );
NOR2X2TS U4068 ( .A(n3187), .B(n3188), .Y(n3186) );
NOR2X2TS U4069 ( .A(n3184), .B(n3185), .Y(n3183) );
NOR2X2TS U4070 ( .A(n3181), .B(n3182), .Y(n3180) );
NAND2X1TS U4071 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n3180), .Y(n3179)
);
NOR2X1TS U4072 ( .A(n1035), .B(n3179), .Y(FPMULT_Adder_M_result_A_adder[24])
);
NOR2X1TS U4073 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n3784), .Y(n3064) );
NAND2X1TS U4074 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n3714), .Y(n3415) );
AOI222X4TS U4075 ( .A0(n3413), .A1(n3714), .B0(n3413), .B1(n3774), .C0(n3714), .C1(n3774), .Y(n3211) );
AOI22X1TS U4076 ( .A0(n3426), .A1(n3418), .B0(n3211), .B1(n3882), .Y(n3063)
);
OAI31X1TS U4077 ( .A0(n3064), .A1(n3063), .A2(n3419), .B0(n3062), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
AOI22X1TS U4078 ( .A0(n957), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n3084), .Y(n3065) );
BUFX3TS U4079 ( .A(n3084), .Y(n3656) );
INVX4TS U4080 ( .A(n3066), .Y(n3518) );
AOI222X4TS U4081 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n958), .C0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C1(n3518), .Y(n3451) );
AOI222X4TS U4082 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n958), .C0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C1(n3518), .Y(n3452) );
OAI22X1TS U4083 ( .A0(n3451), .A1(n3455), .B0(n3452), .B1(n954), .Y(n3070)
);
AOI21X1TS U4084 ( .A0(n955), .A1(n3140), .B0(n3070), .Y(n3071) );
AOI222X4TS U4085 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n3881), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n957), .Y(n3133) );
AOI22X1TS U4086 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n3881), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n3084), .Y(n3072) );
AOI222X4TS U4087 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n3881), .B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(
n957), .Y(n3120) );
AOI222X4TS U4088 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n3881), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n957), .Y(n3125) );
OAI22X1TS U4089 ( .A0(n3120), .A1(n947), .B0(n3125), .B1(n3455), .Y(n3073)
);
AOI21X1TS U4090 ( .A0(n955), .A1(n3135), .B0(n3073), .Y(n3074) );
AOI222X4TS U4091 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n958), .C0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n3518), .Y(n3121) );
AOI22X1TS U4092 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n3881), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n3084), .Y(n3075) );
AOI222X4TS U4093 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n958), .C0(n995), .C1(n3518), .Y(
n3138) );
AOI222X4TS U4094 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n958), .C0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n3518), .Y(n3143) );
OAI22X1TS U4095 ( .A0(n3138), .A1(n948), .B0(n3143), .B1(n3455), .Y(n3076)
);
AOI21X1TS U4096 ( .A0(n955), .A1(n3123), .B0(n3076), .Y(n3077) );
AOI222X4TS U4097 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n958), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n3518), .Y(n3115) );
AOI22X1TS U4098 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n3881), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n3084), .Y(n3078) );
AOI222X4TS U4099 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n3518), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n957), .Y(n3132) );
AOI222X4TS U4100 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n957), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n3518), .Y(n3137) );
OAI22X1TS U4101 ( .A0(n3132), .A1(n948), .B0(n3137), .B1(n3455), .Y(n3079)
);
AOI21X1TS U4102 ( .A0(n955), .A1(n3117), .B0(n3079), .Y(n3080) );
AOI222X4TS U4103 ( .A0(n3084), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n3518),
.B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .C0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.C1(n957), .Y(n3127) );
AOI22X1TS U4104 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n3881), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n3084), .Y(n3081) );
AOI222X4TS U4105 ( .A0(n3084), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n958), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n3518), .Y(n3114) );
AOI222X4TS U4106 ( .A0(n3656), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n957), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n3518), .Y(n3119) );
OAI22X1TS U4107 ( .A0(n3114), .A1(n947), .B0(n3119), .B1(n3455), .Y(n3082)
);
AOI21X1TS U4108 ( .A0(n955), .A1(n3129), .B0(n3082), .Y(n3083) );
AOI222X4TS U4109 ( .A0(n3084), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(n3518),
.B1(FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C1(n957), .Y(n3126) );
AOI222X4TS U4110 ( .A0(n3084), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n3518),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(n995), .C1(n958), .Y(n3131) );
OAI22X1TS U4111 ( .A0(n3126), .A1(n948), .B0(n3131), .B1(n3455), .Y(n3085)
);
AOI21X1TS U4112 ( .A0(n3069), .A1(n3111), .B0(n3085), .Y(n3086) );
OAI22X1TS U4113 ( .A0(n3451), .A1(n948), .B0(n3452), .B1(n3455), .Y(n3087)
);
AOI21X1TS U4114 ( .A0(n3069), .A1(n3140), .B0(n3087), .Y(n3088) );
OAI22X1TS U4115 ( .A0(n3119), .A1(n947), .B0(n3127), .B1(n3455), .Y(n3089)
);
AOI21X1TS U4116 ( .A0(n3069), .A1(n3129), .B0(n3089), .Y(n3090) );
OAI22X1TS U4117 ( .A0(n3143), .A1(n948), .B0(n3121), .B1(n3455), .Y(n3091)
);
AOI21X1TS U4118 ( .A0(n3069), .A1(n3123), .B0(n3091), .Y(n3092) );
OAI22X1TS U4119 ( .A0(n3125), .A1(n947), .B0(n3133), .B1(n3455), .Y(n3093)
);
AOI21X1TS U4120 ( .A0(n3069), .A1(n3135), .B0(n3093), .Y(n3094) );
OAI22X1TS U4121 ( .A0(n3137), .A1(n947), .B0(n3115), .B1(n3455), .Y(n3095)
);
AOI21X1TS U4122 ( .A0(n3069), .A1(n3117), .B0(n3095), .Y(n3096) );
OAI22X1TS U4123 ( .A0(n3126), .A1(n3455), .B0(n3131), .B1(n954), .Y(n3097)
);
AOI21X1TS U4124 ( .A0(n3107), .A1(n3129), .B0(n3097), .Y(n3098) );
OAI22X1TS U4125 ( .A0(n3120), .A1(n3056), .B0(n3125), .B1(n953), .Y(n3100)
);
AOI21X1TS U4126 ( .A0(n3107), .A1(n3123), .B0(n3100), .Y(n3101) );
OAI22X1TS U4127 ( .A0(n3138), .A1(n3056), .B0(n3143), .B1(n954), .Y(n3102)
);
AOI21X1TS U4128 ( .A0(n3107), .A1(n3140), .B0(n3102), .Y(n3103) );
OAI22X1TS U4129 ( .A0(n3132), .A1(n3056), .B0(n3137), .B1(n953), .Y(n3104)
);
AOI21X1TS U4130 ( .A0(n3107), .A1(n3135), .B0(n3104), .Y(n3105) );
OAI22X1TS U4131 ( .A0(n3114), .A1(n3056), .B0(n3119), .B1(n954), .Y(n3106)
);
AOI21X1TS U4132 ( .A0(n3107), .A1(n3117), .B0(n3106), .Y(n3108) );
OAI22X1TS U4133 ( .A0(n3131), .A1(n948), .B0(n3109), .B1(n954), .Y(n3110) );
AOI21X1TS U4134 ( .A0(n3141), .A1(n3111), .B0(n3110), .Y(n3112) );
OAI22X1TS U4135 ( .A0(n3115), .A1(n947), .B0(n3114), .B1(n953), .Y(n3116) );
AOI21X1TS U4136 ( .A0(n3141), .A1(n3117), .B0(n3116), .Y(n3118) );
OAI22X1TS U4137 ( .A0(n3121), .A1(n948), .B0(n3120), .B1(n954), .Y(n3122) );
AOI21X1TS U4138 ( .A0(n3141), .A1(n3123), .B0(n3122), .Y(n3124) );
OAI22X1TS U4139 ( .A0(n3127), .A1(n947), .B0(n3126), .B1(n953), .Y(n3128) );
AOI21X1TS U4140 ( .A0(n3141), .A1(n3129), .B0(n3128), .Y(n3130) );
OAI22X1TS U4141 ( .A0(n3133), .A1(n947), .B0(n3132), .B1(n953), .Y(n3134) );
AOI21X1TS U4142 ( .A0(n3141), .A1(n3135), .B0(n3134), .Y(n3136) );
OAI22X1TS U4143 ( .A0(n3452), .A1(n948), .B0(n3138), .B1(n953), .Y(n3139) );
AOI21X1TS U4144 ( .A0(n3141), .A1(n3140), .B0(n3139), .Y(n3142) );
OAI22X1TS U4145 ( .A0(n3147), .A1(n3146), .B0(n3145), .B1(n3159), .Y(n3148)
);
AOI21X1TS U4146 ( .A0(n3149), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n3148),
.Y(n3150) );
OAI211X1TS U4147 ( .A0(n3152), .A1(n3789), .B0(n3151), .C0(n3150), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
NOR3X1TS U4148 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(n3169), .C(n3739), .Y(
n3165) );
AOI211X1TS U4149 ( .A0(n3156), .A1(n3155), .B0(n3154), .C0(n3165), .Y(n3158)
);
OAI211X1TS U4150 ( .A0(n3160), .A1(n3159), .B0(n3158), .C0(n3157), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
OAI31X1TS U4151 ( .A0(n3163), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n3162),
.B0(n3161), .Y(n3164) );
AOI211X1TS U4152 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n3166), .B0(n3165),
.C0(n3164), .Y(n3167) );
OAI211X1TS U4153 ( .A0(n3824), .A1(n3169), .B0(n3168), .C0(n3167), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NOR3XLTS U4154 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n3780), .Y(FPSENCOS_enab_d_ff4_Xn) );
NOR3XLTS U4155 ( .A(FPSENCOS_cont_var_out[1]), .B(n3700), .C(n3780), .Y(
FPSENCOS_enab_d_ff4_Yn) );
OAI21XLTS U4156 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n911), .B0(n3170),
.Y(n810) );
INVX2TS U4157 ( .A(n3482), .Y(n3480) );
NOR2X1TS U4158 ( .A(enab_cont_iter), .B(n3480), .Y(n3476) );
NAND2X1TS U4159 ( .A(n3476), .B(n3780), .Y(n3655) );
INVX2TS U4160 ( .A(n3655), .Y(n3654) );
OAI21XLTS U4161 ( .A0(n3654), .A1(n3700), .B0(FPSENCOS_cont_var_out[1]), .Y(
n3171) );
XNOR2X1TS U4162 ( .A(DP_OP_234J308_126_8543_n1), .B(n3172), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR2BX1TS U4163 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3173) );
XOR2X1TS U4164 ( .A(n911), .B(n3173), .Y(DP_OP_26J308_123_9022_n16) );
NOR2BX1TS U4165 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3174) );
XOR2X1TS U4166 ( .A(n911), .B(n3174), .Y(DP_OP_26J308_123_9022_n17) );
OR2X1TS U4167 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n3175) );
XOR2X1TS U4168 ( .A(n911), .B(n3175), .Y(DP_OP_26J308_123_9022_n18) );
NOR2X1TS U4169 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n3177)
);
NAND2X1TS U4170 ( .A(n3176), .B(FPMULT_P_Sgf[47]), .Y(n3178) );
OAI2BB1X1TS U4171 ( .A0N(FPMULT_FSM_selector_B[1]), .A1N(n3177), .B0(n3178),
.Y(n829) );
OAI2BB1X1TS U4172 ( .A0N(FPMULT_FSM_selector_B[0]), .A1N(n3178), .B0(n3177),
.Y(n830) );
NOR2BX1TS U4173 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3932), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI21X1TS U4174 ( .A0(n3179), .A1(n1035), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
OA21XLTS U4175 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n3180), .B0(
n3179), .Y(FPMULT_Adder_M_result_A_adder[22]) );
AOI21X1TS U4176 ( .A0(n3181), .A1(n3182), .B0(n3180), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
OA21XLTS U4177 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n3183), .B0(
n3182), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AOI21X1TS U4178 ( .A0(n3184), .A1(n3185), .B0(n3183), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
OA21XLTS U4179 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n3186), .B0(
n3185), .Y(FPMULT_Adder_M_result_A_adder[18]) );
AOI21X1TS U4180 ( .A0(n3187), .A1(n3188), .B0(n3186), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
OA21XLTS U4181 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n3189), .B0(
n3188), .Y(FPMULT_Adder_M_result_A_adder[16]) );
AOI21X1TS U4182 ( .A0(n3190), .A1(n3191), .B0(n3189), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
OA21XLTS U4183 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n3192), .B0(
n3191), .Y(FPMULT_Adder_M_result_A_adder[14]) );
AOI21X1TS U4184 ( .A0(n3193), .A1(n3194), .B0(n3192), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
OA21XLTS U4185 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n3195), .B0(
n3194), .Y(FPMULT_Adder_M_result_A_adder[12]) );
AOI21X1TS U4186 ( .A0(n3196), .A1(n3197), .B0(n3195), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
OA21XLTS U4187 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n3198), .B0(
n3197), .Y(FPMULT_Adder_M_result_A_adder[10]) );
AOI21X1TS U4188 ( .A0(n3199), .A1(n3200), .B0(n3198), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
OA21XLTS U4189 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n3201), .B0(n3200), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AOI21X1TS U4190 ( .A0(n3202), .A1(n3203), .B0(n3201), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
OA21XLTS U4191 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n3204), .B0(n3203), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AOI21X1TS U4192 ( .A0(n3208), .A1(n1087), .B0(n3204), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U4193 ( .A0(n3206), .A1(n3205), .B0(n3209), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
AO21XLTS U4194 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n3207), .B0(n3206), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO21XLTS U4195 ( .A0(n3209), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n3208), .Y(FPMULT_Adder_M_result_A_adder[4]) );
XOR2XLTS U4196 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n3210) );
XOR2XLTS U4197 ( .A(intadd_1038_n1), .B(n3210), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
AOI222X4TS U4198 ( .A0(n3420), .A1(n3717), .B0(n3420), .B1(n3785), .C0(n3717), .C1(n3785), .Y(n3425) );
CLKINVX1TS U4199 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n3436) );
AOI21X1TS U4200 ( .A0(n3431), .A1(n3436), .B0(n910), .Y(n3933) );
BUFX4TS U4201 ( .A(n3010), .Y(n3561) );
NOR2BX1TS U4202 ( .AN(operation[0]), .B(n3561), .Y(n3938) );
AOI2BB2XLTS U4203 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n3212) );
AOI222X1TS U4204 ( .A0(n3010), .A1(Data_2[31]), .B0(n2673), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n3566), .Y(n3213) );
INVX2TS U4205 ( .A(n3213), .Y(n3214) );
XNOR2X1TS U4206 ( .A(n3215), .B(n3214), .Y(n3830) );
NOR2X1TS U4207 ( .A(n3813), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3274) );
AOI22X1TS U4208 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n3813), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3216), .Y(n3220) );
OAI21X1TS U4209 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n3817), .B0(n3217), .Y(
n3275) );
NOR2X1TS U4210 ( .A(n3837), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3223) );
NOR2X1TS U4211 ( .A(n3836), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3221) );
AOI211X1TS U4212 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3756), .B0(n3223),
.C0(n3221), .Y(n3273) );
NOR3X1TS U4213 ( .A(n3756), .B(n3221), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3222) );
AOI2BB2X1TS U4214 ( .B0(n3225), .B1(n3273), .A0N(n3224), .A1N(n3223), .Y(
n3279) );
NOR2X1TS U4215 ( .A(n3812), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3261) );
NOR2X1TS U4216 ( .A(n3810), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3240) );
AOI21X1TS U4217 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3761), .B0(n3240), .Y(
n3245) );
OAI2BB1X1TS U4218 ( .A0N(n3781), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3226) );
OAI22X1TS U4219 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3226), .B0(n3781), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3237) );
OAI2BB1X1TS U4220 ( .A0N(n3708), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3227) );
OAI22X1TS U4221 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3227), .B0(n3708), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3236) );
OAI21XLTS U4222 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n3816), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3228) );
OAI2BB2XLTS U4223 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3228), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n3816), .Y(n3230) );
NAND2BXLTS U4224 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3229) );
OAI211XLTS U4225 ( .A0(n3818), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3230), .C0(
n3229), .Y(n3233) );
OAI21XLTS U4226 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n3818), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3231) );
AOI2BB2XLTS U4227 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n3818), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n3231), .Y(n3232) );
AOI222X1TS U4228 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3712), .B0(n3233), .B1(
n3232), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n3781), .Y(n3235) );
AOI22X1TS U4229 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3708), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n3768), .Y(n3234) );
OAI32X1TS U4230 ( .A0(n3237), .A1(n3236), .A2(n3235), .B0(n3234), .B1(n3236),
.Y(n3255) );
OA22X1TS U4231 ( .A0(n3719), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n3811), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3252) );
OAI21XLTS U4232 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n3799), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n3239) );
OAI2BB2XLTS U4233 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3239), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n3799), .Y(n3251) );
AOI22X1TS U4234 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n3810), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n3241), .Y(n3247) );
NAND2BXLTS U4235 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3244) );
AOI21X1TS U4236 ( .A0(n3244), .A1(n3243), .B0(n3254), .Y(n3246) );
OAI2BB2XLTS U4237 ( .B0(n3247), .B1(n3254), .A0N(n3246), .A1N(n3245), .Y(
n3250) );
OAI2BB2XLTS U4238 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3248), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n3811), .Y(n3249) );
AOI211X1TS U4239 ( .A0(n3252), .A1(n3251), .B0(n3250), .C0(n3249), .Y(n3253)
);
OAI31X1TS U4240 ( .A0(n3256), .A1(n3255), .A2(n3254), .B0(n3253), .Y(n3259)
);
OA22X1TS U4241 ( .A0(n3722), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n3820), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n3290) );
OAI21X1TS U4242 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n3815), .B0(n3263), .Y(
n3267) );
AOI211X1TS U4243 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3770), .B0(n3266),
.C0(n3267), .Y(n3258) );
OAI21XLTS U4244 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n3804), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3260) );
OAI2BB2XLTS U4245 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3260), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n3804), .Y(n3271) );
AOI22X1TS U4246 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n3812), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3262), .Y(n3265) );
AOI32X1TS U4247 ( .A0(n3815), .A1(n3263), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n3721), .Y(n3264) );
OAI32X1TS U4248 ( .A0(n3267), .A1(n3266), .A2(n3265), .B0(n3264), .B1(n3266),
.Y(n3270) );
OAI2BB2XLTS U4249 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3268), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n3820), .Y(n3269) );
AOI211X1TS U4250 ( .A0(n3290), .A1(n3271), .B0(n3270), .C0(n3269), .Y(n3277)
);
NAND4BBX1TS U4251 ( .AN(n3275), .BN(n3274), .C(n3273), .D(n3272), .Y(n3276)
);
AOI32X1TS U4252 ( .A0(n3279), .A1(n3278), .A2(n3277), .B0(n3276), .B1(n3279),
.Y(n3280) );
INVX4TS U4253 ( .A(n3280), .Y(n3443) );
BUFX4TS U4254 ( .A(n3443), .Y(n3446) );
NAND2X1TS U4255 ( .A(FPADDSUB_intDY_EWSW[18]), .B(n3771), .Y(n3281) );
AOI22X1TS U4256 ( .A0(n3775), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n3768), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n3282) );
OAI221XLTS U4257 ( .A0(n3775), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n3768),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n3282), .Y(n3287) );
AOI22X1TS U4258 ( .A0(n3765), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n3711), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n3283) );
AOI22X1TS U4259 ( .A0(n3709), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n3773), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n3284) );
OAI221XLTS U4260 ( .A0(n3709), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n3773),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n3284), .Y(n3285) );
NOR4X1TS U4261 ( .A(n3288), .B(n3287), .C(n3286), .D(n3285), .Y(n3315) );
AOI22X1TS U4262 ( .A0(n3781), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n3712), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n3289) );
OAI221XLTS U4263 ( .A0(n3718), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n3788),
.B1(FPADDSUB_intDY_EWSW[22]), .C0(n3290), .Y(n3295) );
AOI22X1TS U4264 ( .A0(n3766), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n3770), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n3291) );
AOI22X1TS U4265 ( .A0(n3710), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3769), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n3292) );
OAI221XLTS U4266 ( .A0(n3710), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3769),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n3292), .Y(n3293) );
NOR4X1TS U4267 ( .A(n3296), .B(n3295), .C(n3294), .D(n3293), .Y(n3314) );
NAND2X1TS U4268 ( .A(FPADDSUB_intDY_EWSW[20]), .B(n3772), .Y(n3297) );
AOI22X1TS U4269 ( .A0(n3767), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n3713), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n3298) );
OAI221XLTS U4270 ( .A0(n3767), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n3713),
.B1(FPADDSUB_intDY_EWSW[24]), .C0(n3298), .Y(n3311) );
OAI22X1TS U4271 ( .A0(n3763), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n3707), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n3299) );
AOI221X1TS U4272 ( .A0(n3763), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n3707), .C0(n3299), .Y(n3300) );
OAI22X1TS U4273 ( .A0(n3762), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n3705), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n3301) );
AOI221X1TS U4274 ( .A0(n3762), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n3705), .C0(n3301), .Y(n3308) );
OAI22X1TS U4275 ( .A0(n3708), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n3706), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n3302) );
AOI221X1TS U4276 ( .A0(n3708), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n3706), .C0(n3302), .Y(n3307) );
OAI22X1TS U4277 ( .A0(n3761), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n3760), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n3303) );
AOI221X1TS U4278 ( .A0(n3761), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n3760), .C0(n3303), .Y(n3306) );
OAI22X1TS U4279 ( .A0(n3764), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n3703), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n3304) );
AOI221X1TS U4280 ( .A0(n3764), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n3703), .C0(n3304), .Y(n3305) );
NAND4XLTS U4281 ( .A(n3308), .B(n3307), .C(n3306), .D(n3305), .Y(n3309) );
NOR4X1TS U4282 ( .A(n3312), .B(n3311), .C(n3310), .D(n3309), .Y(n3313) );
BUFX3TS U4283 ( .A(n3443), .Y(n3447) );
AOI31XLTS U4284 ( .A0(n3315), .A1(n3314), .A2(n3313), .B0(n3280), .Y(n3316)
);
AOI2BB2XLTS U4285 ( .B0(n3446), .B1(n3929), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n3316), .Y(n3930) );
OAI21X2TS U4288 ( .A0(n3318), .A1(FPMULT_FSM_add_overflow_flag), .B0(n927),
.Y(n3324) );
AOI22X1TS U4289 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n3782), .Y(n3317) );
AOI22X1TS U4290 ( .A0(n1070), .A1(n3319), .B0(n3324), .B1(n3317), .Y(n3963)
);
AOI32X1TS U4291 ( .A0(n2896), .A1(n2811), .A2(n3806), .B0(n3319), .B1(n3318),
.Y(n3322) );
AOI22X1TS U4292 ( .A0(n962), .A1(FPMULT_Add_result[22]), .B0(n964), .B1(
FPMULT_Add_result[23]), .Y(n3327) );
AOI22X1TS U4293 ( .A0(n967), .A1(FPMULT_P_Sgf[45]), .B0(n3370), .B1(
FPMULT_P_Sgf[46]), .Y(n3326) );
NAND2X1TS U4294 ( .A(n3327), .B(n3326), .Y(n3962) );
AOI22X1TS U4295 ( .A0(n962), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Add_result[22]), .B1(n964), .Y(n3329) );
AOI22X1TS U4296 ( .A0(n966), .A1(FPMULT_P_Sgf[44]), .B0(FPMULT_P_Sgf[45]),
.B1(n968), .Y(n3328) );
NAND2X1TS U4297 ( .A(n3329), .B(n3328), .Y(n3961) );
AOI22X1TS U4298 ( .A0(n962), .A1(FPMULT_Add_result[20]), .B0(n964), .B1(
FPMULT_Add_result[21]), .Y(n3331) );
AOI22X1TS U4299 ( .A0(n967), .A1(FPMULT_P_Sgf[43]), .B0(n3370), .B1(
FPMULT_P_Sgf[44]), .Y(n3330) );
NAND2X1TS U4300 ( .A(n3331), .B(n3330), .Y(n3960) );
AOI22X1TS U4301 ( .A0(n962), .A1(FPMULT_Add_result[19]), .B0(n964), .B1(
FPMULT_Add_result[20]), .Y(n3333) );
AOI22X1TS U4302 ( .A0(n966), .A1(FPMULT_P_Sgf[42]), .B0(n968), .B1(
FPMULT_P_Sgf[43]), .Y(n3332) );
NAND2X1TS U4303 ( .A(n3333), .B(n3332), .Y(n3959) );
AOI22X1TS U4304 ( .A0(n963), .A1(FPMULT_Add_result[18]), .B0(n965), .B1(
FPMULT_Add_result[19]), .Y(n3335) );
AOI22X1TS U4305 ( .A0(n966), .A1(FPMULT_P_Sgf[41]), .B0(n968), .B1(
FPMULT_P_Sgf[42]), .Y(n3334) );
NAND2X1TS U4306 ( .A(n3335), .B(n3334), .Y(n3958) );
AOI22X1TS U4307 ( .A0(n962), .A1(FPMULT_Add_result[17]), .B0(n964), .B1(
FPMULT_Add_result[18]), .Y(n3337) );
AOI22X1TS U4308 ( .A0(n966), .A1(FPMULT_P_Sgf[40]), .B0(n968), .B1(
FPMULT_P_Sgf[41]), .Y(n3336) );
NAND2X1TS U4309 ( .A(n3337), .B(n3336), .Y(n3957) );
AOI22X1TS U4310 ( .A0(n963), .A1(FPMULT_Add_result[16]), .B0(n965), .B1(
FPMULT_Add_result[17]), .Y(n3339) );
AOI22X1TS U4311 ( .A0(n966), .A1(FPMULT_P_Sgf[39]), .B0(n968), .B1(
FPMULT_P_Sgf[40]), .Y(n3338) );
NAND2X1TS U4312 ( .A(n3339), .B(n3338), .Y(n3956) );
AOI22X1TS U4313 ( .A0(n962), .A1(FPMULT_Add_result[15]), .B0(n964), .B1(
FPMULT_Add_result[16]), .Y(n3341) );
AOI22X1TS U4314 ( .A0(n966), .A1(FPMULT_P_Sgf[38]), .B0(n968), .B1(
FPMULT_P_Sgf[39]), .Y(n3340) );
NAND2X1TS U4315 ( .A(n3341), .B(n3340), .Y(n3955) );
AOI22X1TS U4316 ( .A0(n963), .A1(n974), .B0(n965), .B1(FPMULT_Add_result[15]), .Y(n3343) );
AOI22X1TS U4317 ( .A0(n967), .A1(FPMULT_P_Sgf[37]), .B0(n3370), .B1(
FPMULT_P_Sgf[38]), .Y(n3342) );
NAND2X1TS U4318 ( .A(n3343), .B(n3342), .Y(n3954) );
AOI22X1TS U4319 ( .A0(n962), .A1(FPMULT_Add_result[13]), .B0(n964), .B1(n974), .Y(n3345) );
AOI22X1TS U4320 ( .A0(n966), .A1(FPMULT_P_Sgf[36]), .B0(n968), .B1(
FPMULT_P_Sgf[37]), .Y(n3344) );
NAND2X1TS U4321 ( .A(n3345), .B(n3344), .Y(n3953) );
AOI22X1TS U4322 ( .A0(n963), .A1(n973), .B0(n965), .B1(FPMULT_Add_result[13]), .Y(n3347) );
AOI22X1TS U4323 ( .A0(n967), .A1(FPMULT_P_Sgf[35]), .B0(n3370), .B1(
FPMULT_P_Sgf[36]), .Y(n3346) );
NAND2X1TS U4324 ( .A(n3347), .B(n3346), .Y(n3952) );
AOI22X1TS U4325 ( .A0(n962), .A1(FPMULT_Add_result[11]), .B0(n964), .B1(n973), .Y(n3349) );
AOI22X1TS U4326 ( .A0(n966), .A1(FPMULT_P_Sgf[34]), .B0(n968), .B1(
FPMULT_P_Sgf[35]), .Y(n3348) );
NAND2X1TS U4327 ( .A(n3349), .B(n3348), .Y(n3951) );
AOI22X1TS U4328 ( .A0(n963), .A1(n972), .B0(n965), .B1(FPMULT_Add_result[11]), .Y(n3351) );
AOI22X1TS U4329 ( .A0(n967), .A1(FPMULT_P_Sgf[33]), .B0(n3370), .B1(
FPMULT_P_Sgf[34]), .Y(n3350) );
NAND2X1TS U4330 ( .A(n3351), .B(n3350), .Y(n3950) );
AOI22X1TS U4331 ( .A0(n962), .A1(FPMULT_Add_result[9]), .B0(n964), .B1(n972),
.Y(n3353) );
AOI22X1TS U4332 ( .A0(n966), .A1(FPMULT_P_Sgf[32]), .B0(n968), .B1(
FPMULT_P_Sgf[33]), .Y(n3352) );
NAND2X1TS U4333 ( .A(n3353), .B(n3352), .Y(n3949) );
AOI22X1TS U4334 ( .A0(n963), .A1(FPMULT_Add_result[8]), .B0(n965), .B1(
FPMULT_Add_result[9]), .Y(n3355) );
AOI22X1TS U4335 ( .A0(n967), .A1(FPMULT_P_Sgf[31]), .B0(n3370), .B1(
FPMULT_P_Sgf[32]), .Y(n3354) );
NAND2X1TS U4336 ( .A(n3355), .B(n3354), .Y(n3948) );
AOI22X1TS U4337 ( .A0(n962), .A1(FPMULT_Add_result[7]), .B0(n964), .B1(
FPMULT_Add_result[8]), .Y(n3357) );
AOI22X1TS U4338 ( .A0(n966), .A1(FPMULT_P_Sgf[30]), .B0(n968), .B1(
FPMULT_P_Sgf[31]), .Y(n3356) );
NAND2X1TS U4339 ( .A(n3357), .B(n3356), .Y(n3947) );
AOI22X1TS U4340 ( .A0(n963), .A1(FPMULT_Add_result[6]), .B0(n965), .B1(
FPMULT_Add_result[7]), .Y(n3359) );
AOI22X1TS U4341 ( .A0(n967), .A1(FPMULT_P_Sgf[29]), .B0(n3370), .B1(
FPMULT_P_Sgf[30]), .Y(n3358) );
NAND2X1TS U4342 ( .A(n3359), .B(n3358), .Y(n3946) );
AOI22X1TS U4343 ( .A0(n963), .A1(n971), .B0(n965), .B1(FPMULT_Add_result[6]),
.Y(n3361) );
AOI22X1TS U4344 ( .A0(n967), .A1(FPMULT_P_Sgf[28]), .B0(n3370), .B1(
FPMULT_P_Sgf[29]), .Y(n3360) );
NAND2X1TS U4345 ( .A(n3361), .B(n3360), .Y(n3945) );
AOI22X1TS U4346 ( .A0(n963), .A1(n970), .B0(n965), .B1(n971), .Y(n3363) );
AOI22X1TS U4347 ( .A0(n967), .A1(FPMULT_P_Sgf[27]), .B0(n3370), .B1(
FPMULT_P_Sgf[28]), .Y(n3362) );
NAND2X1TS U4348 ( .A(n3363), .B(n3362), .Y(n3944) );
AOI22X1TS U4349 ( .A0(n962), .A1(FPMULT_Add_result[3]), .B0(n964), .B1(n970),
.Y(n3365) );
AOI22X1TS U4350 ( .A0(n966), .A1(FPMULT_P_Sgf[26]), .B0(n968), .B1(
FPMULT_P_Sgf[27]), .Y(n3364) );
NAND2X1TS U4351 ( .A(n3365), .B(n3364), .Y(n3943) );
AOI22X1TS U4352 ( .A0(n963), .A1(n969), .B0(n965), .B1(FPMULT_Add_result[3]),
.Y(n3367) );
AOI22X1TS U4353 ( .A0(n967), .A1(FPMULT_P_Sgf[25]), .B0(n3370), .B1(
FPMULT_P_Sgf[26]), .Y(n3366) );
NAND2X1TS U4354 ( .A(n3367), .B(n3366), .Y(n3942) );
AOI22X1TS U4355 ( .A0(n963), .A1(FPMULT_Add_result[1]), .B0(n965), .B1(n969),
.Y(n3369) );
AOI22X1TS U4356 ( .A0(n967), .A1(FPMULT_P_Sgf[24]), .B0(n3370), .B1(
FPMULT_P_Sgf[25]), .Y(n3368) );
NAND2X1TS U4357 ( .A(n3369), .B(n3368), .Y(n3941) );
AOI22X1TS U4358 ( .A0(n963), .A1(FPMULT_Add_result[0]), .B0(n965), .B1(
FPMULT_Add_result[1]), .Y(n3372) );
AOI22X1TS U4359 ( .A0(n967), .A1(FPMULT_P_Sgf[23]), .B0(n3370), .B1(
FPMULT_P_Sgf[24]), .Y(n3371) );
NAND2X1TS U4360 ( .A(n3372), .B(n3371), .Y(n3940) );
AOI22X1TS U4361 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3373), .B1(n3783),
.Y(n3939) );
XNOR2X1TS U4362 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n3831) );
INVX2TS U4363 ( .A(n3374), .Y(n3516) );
AOI2BB1XLTS U4364 ( .A0N(n3807), .A1N(underflow_flag_mult), .B0(n3516), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AOI32X1TS U4365 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3375), .A2(n3743),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n3375), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U4366 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3597), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n3598), .Y(FPSENCOS_data_out_LUT[25])
);
NAND4XLTS U4367 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n3377) );
NAND4XLTS U4368 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n3376) );
NOR3X1TS U4369 ( .A(n3919), .B(n3377), .C(n3376), .Y(n3382) );
NOR4X1TS U4370 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n3379) );
NOR3XLTS U4371 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n3378) );
NAND4XLTS U4372 ( .A(n3382), .B(operation_reg[1]), .C(n3379), .D(n3378), .Y(
n3380) );
NOR3XLTS U4373 ( .A(operation_reg[0]), .B(dataB[31]), .C(n3380), .Y(n3381)
);
OAI211XLTS U4374 ( .A0(dataB[27]), .A1(n3381), .B0(n3918), .C0(n3917), .Y(
n3392) );
NOR4X1TS U4375 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n3385) );
NOR4BX1TS U4376 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n3384) );
NOR4X1TS U4377 ( .A(n3919), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n3383) );
NOR2BX1TS U4378 ( .AN(n3382), .B(operation_reg[1]), .Y(n3390) );
AOI31XLTS U4379 ( .A0(n3385), .A1(n3384), .A2(n3383), .B0(n3390), .Y(n3388)
);
NAND3XLTS U4380 ( .A(dataB[23]), .B(dataB[28]), .C(dataB[25]), .Y(n3387) );
NAND4XLTS U4381 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n3386) );
OAI31X1TS U4382 ( .A0(n3388), .A1(n3387), .A2(n3386), .B0(dataB[27]), .Y(
n3389) );
NAND4XLTS U4383 ( .A(n3922), .B(n3921), .C(n3920), .D(n3389), .Y(n3391) );
OAI2BB2XLTS U4384 ( .B0(n3392), .B1(n3391), .A0N(n3390), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U4385 ( .A(FPADDSUB_N59), .B(n910), .Y(n3393) );
XNOR2X1TS U4386 ( .A(n3393), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
OAI21XLTS U4387 ( .A0(FPADDSUB_DMP_SFG[0]), .A1(FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n3394), .Y(n3397) );
NAND2X1TS U4388 ( .A(n3395), .B(n910), .Y(n3396) );
XOR2XLTS U4389 ( .A(n3397), .B(n3396), .Y(FPADDSUB_Raw_mant_SGF[2]) );
AOI22X1TS U4390 ( .A0(n3426), .A1(n3399), .B0(n3398), .B1(n3882), .Y(n3402)
);
OAI21XLTS U4391 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n3698), .B0(n3400),
.Y(n3401) );
AOI22X1TS U4392 ( .A0(n3426), .A1(n3404), .B0(n3403), .B1(n3882), .Y(n3407)
);
AOI22X1TS U4393 ( .A0(n3426), .A1(n3409), .B0(n3408), .B1(n3882), .Y(n3412)
);
AOI22X1TS U4394 ( .A0(n3426), .A1(n3414), .B0(n3413), .B1(n3882), .Y(n3417)
);
AOI22X1TS U4395 ( .A0(n3426), .A1(n3423), .B0(n3420), .B1(n3882), .Y(n3422)
);
NAND2X1TS U4396 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n3717), .Y(n3424) );
NOR2X1TS U4397 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n3791), .Y(n3433) );
AOI21X1TS U4398 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n3791), .B0(n3433),
.Y(n3428) );
AOI22X1TS U4399 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n3785), .B0(n3424), .B1(
n3423), .Y(n3429) );
AOI22X1TS U4400 ( .A0(n3426), .A1(n3429), .B0(n3425), .B1(n3882), .Y(n3427)
);
AOI21X1TS U4401 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n3791), .B0(n3429),
.Y(n3432) );
NAND2X1TS U4402 ( .A(FPSENCOS_d_ff1_operation_out), .B(n980), .Y(n3439) );
XOR2X1TS U4403 ( .A(n1089), .B(n3437), .Y(n3438) );
INVX2TS U4404 ( .A(n3438), .Y(n3470) );
INVX3TS U4405 ( .A(n3470), .Y(n3469) );
BUFX3TS U4406 ( .A(n3470), .Y(n3468) );
AOI22X1TS U4407 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n3468), .Y(n3441) );
XNOR2X1TS U4408 ( .A(n3441), .B(n3440), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U4409 ( .A0(n3445), .A1(n3819), .B0(n3711), .B1(n3446), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U4410 ( .A0(n3450), .A1(n3816), .B0(n3765), .B1(n3446), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U4411 ( .A0(n3445), .A1(n3800), .B0(n3705), .B1(n3446), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
BUFX4TS U4412 ( .A(n3446), .Y(n3444) );
AOI22X1TS U4413 ( .A0(n3450), .A1(n3818), .B0(n3773), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
INVX4TS U4414 ( .A(n3447), .Y(n3442) );
AOI22X1TS U4415 ( .A0(n3442), .A1(n3798), .B0(n3712), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U4416 ( .A0(n3442), .A1(n3793), .B0(n3781), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U4417 ( .A0(n3442), .A1(n3796), .B0(n3768), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U4418 ( .A0(n3442), .A1(n3792), .B0(n3708), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U4419 ( .A0(n3442), .A1(n3814), .B0(n3769), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U4420 ( .A0(n3442), .A1(n3802), .B0(n3706), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U4421 ( .A0(n3442), .A1(n3795), .B0(n3761), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U4422 ( .A0(n3442), .A1(n3810), .B0(n3760), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U4423 ( .A0(n3442), .A1(n3762), .B0(n3794), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U4424 ( .A0(n3442), .A1(n3799), .B0(n3703), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U4425 ( .A0(n3442), .A1(n3719), .B0(n3786), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U4426 ( .A0(n3442), .A1(n3811), .B0(n3764), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U4427 ( .A0(n3442), .A1(n3797), .B0(n3770), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
INVX4TS U4428 ( .A(n3447), .Y(n3448) );
AOI22X1TS U4429 ( .A0(n3448), .A1(n3812), .B0(n3766), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U4430 ( .A0(n3448), .A1(n3815), .B0(n3771), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U4431 ( .A0(n3448), .A1(n3721), .B0(n3763), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U4432 ( .A0(n3448), .A1(n3805), .B0(n3772), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U4433 ( .A0(n3448), .A1(n3804), .B0(n3710), .B1(n3444), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U4434 ( .A0(n3448), .A1(n3722), .B0(n3788), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U4435 ( .A0(n3448), .A1(n3820), .B0(n3718), .B1(n3449), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U4436 ( .A0(n3448), .A1(n3801), .B0(n3713), .B1(n3446), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U4437 ( .A0(n3448), .A1(n3813), .B0(n3767), .B1(n3443), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U4438 ( .A0(n3448), .A1(n3817), .B0(n3709), .B1(n3449), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U4439 ( .A0(n3448), .A1(n3803), .B0(n3707), .B1(n3446), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U4440 ( .A0(n3448), .A1(n3711), .B0(n3819), .B1(n3446), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
INVX4TS U4441 ( .A(n3446), .Y(n3445) );
AOI22X1TS U4442 ( .A0(n3445), .A1(n3765), .B0(n3816), .B1(n3443), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U4443 ( .A0(n3445), .A1(n3705), .B0(n3800), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U4444 ( .A0(n3445), .A1(n3773), .B0(n3818), .B1(n3443), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U4445 ( .A0(n3445), .A1(n3712), .B0(n3798), .B1(n3444), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U4446 ( .A0(n3445), .A1(n3781), .B0(n3793), .B1(n3443), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U4447 ( .A0(n3445), .A1(n3768), .B0(n3796), .B1(n3447), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U4448 ( .A0(n3445), .A1(n3708), .B0(n3792), .B1(n3443), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U4449 ( .A0(n3445), .A1(n3769), .B0(n3814), .B1(n3443), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U4450 ( .A0(n3445), .A1(n3706), .B0(n3802), .B1(n3446), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U4451 ( .A0(n3445), .A1(n3761), .B0(n3795), .B1(n3447), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U4452 ( .A0(n3445), .A1(n3760), .B0(n3810), .B1(n3446), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U4453 ( .A0(n3445), .A1(n3794), .B0(n3762), .B1(n3447), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U4454 ( .A0(n3445), .A1(n3703), .B0(n3799), .B1(n3443), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
INVX4TS U4455 ( .A(n3446), .Y(n3450) );
AOI22X1TS U4456 ( .A0(n3450), .A1(n3786), .B0(n3719), .B1(n3447), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
BUFX3TS U4457 ( .A(n3447), .Y(n3449) );
AOI22X1TS U4458 ( .A0(n3450), .A1(n3764), .B0(n3811), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U4459 ( .A0(n3450), .A1(n3770), .B0(n3797), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U4460 ( .A0(n3450), .A1(n3766), .B0(n3812), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U4461 ( .A0(n3450), .A1(n3771), .B0(n3815), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U4462 ( .A0(n3448), .A1(n3763), .B0(n3721), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U4463 ( .A0(n3450), .A1(n3772), .B0(n3805), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U4464 ( .A0(n3450), .A1(n3710), .B0(n3804), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U4465 ( .A0(n3450), .A1(n3788), .B0(n3722), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U4466 ( .A0(n3450), .A1(n3718), .B0(n3820), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U4467 ( .A0(n3450), .A1(n3713), .B0(n3801), .B1(n3449), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U4468 ( .A0(n3450), .A1(n3767), .B0(n3813), .B1(n3446), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U4469 ( .A0(n3450), .A1(n3709), .B0(n3817), .B1(n3446), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U4470 ( .A0(n3450), .A1(n3707), .B0(n3803), .B1(n3446), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U4471 ( .B0(n3442), .B1(n3775), .A0N(n3442), .A1N(
FPADDSUB_intDX_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U4472 ( .B0(n3448), .B1(n3836), .A0N(n3448), .A1N(
FPADDSUB_intDX_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U4473 ( .A0(n3451), .A1(n3453), .B0(n3454), .B1(n954), .Y(
FPADDSUB_Data_array_SWR[24]) );
NAND2X1TS U4474 ( .A(n3474), .B(n3484), .Y(FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U4475 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U4476 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
CLKAND2X2TS U4477 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U4478 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U4479 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U4480 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U4481 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
CLKAND2X2TS U4482 ( .A(n961), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
NOR2BX1TS U4483 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U4484 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U4485 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n3457), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U4486 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U4487 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U4488 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U4489 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U4490 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U4491 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n3458), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U4492 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U4493 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n3456), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
INVX4TS U4494 ( .A(n3461), .Y(n3459) );
NOR2BX1TS U4495 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n3459), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U4496 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n3459), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U4497 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n3459), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U4498 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n3459), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U4499 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n3459), .Y(
FPSENCOS_first_mux_X[11]) );
INVX4TS U4500 ( .A(n3461), .Y(n3467) );
NOR2BX1TS U4501 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n3467), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U4502 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n3459), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U4503 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n3467), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U4504 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n3459), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U4505 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n3459), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U4506 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n3459), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U4507 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n3459), .Y(
FPSENCOS_first_mux_X[31]) );
INVX4TS U4508 ( .A(n3463), .Y(n3466) );
NOR2BX1TS U4509 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[0]) );
INVX4TS U4510 ( .A(n3463), .Y(n3460) );
NOR2BX1TS U4511 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[1]) );
INVX4TS U4512 ( .A(n3463), .Y(n3465) );
NOR2BX1TS U4513 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n3465), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U4514 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U4515 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U4516 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U4517 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n3459), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U4518 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U4519 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U4520 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U4521 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n3459), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U4522 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U4523 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U4524 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U4525 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n3459), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U4526 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U4527 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n3465), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U4528 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U4529 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U4530 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U4531 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U4532 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U4533 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U4534 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n3459), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U4535 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U4536 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U4537 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n3459), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U4538 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U4539 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U4540 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U4541 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n3460), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U4542 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n3466), .Y(
FPSENCOS_first_mux_Y[31]) );
AO22XLTS U4543 ( .A0(n3462), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22XLTS U4544 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U4545 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U4546 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
AO22XLTS U4547 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
AO22XLTS U4548 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U4549 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22XLTS U4550 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22XLTS U4551 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AO22XLTS U4552 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AO22XLTS U4553 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U4554 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22XLTS U4555 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22XLTS U4556 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U4557 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U4558 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U4559 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U4560 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO22XLTS U4561 ( .A0(n3466), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22XLTS U4562 ( .A0(n3466), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U4563 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AO22XLTS U4564 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U4565 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U4566 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22XLTS U4567 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U4568 ( .A0(n3466), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
AO22XLTS U4569 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U4570 ( .A0(n3466), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22XLTS U4571 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
AO22XLTS U4572 ( .A0(n3465), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22XLTS U4573 ( .A0(n3466), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n3461), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
AO22XLTS U4574 ( .A0(n3467), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n3463), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
BUFX3TS U4575 ( .A(n3468), .Y(n3472) );
AO22XLTS U4576 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22XLTS U4577 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U4578 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U4579 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U4580 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22XLTS U4581 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U4582 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
AO22XLTS U4583 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U4584 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U4585 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U4586 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
AO22XLTS U4587 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n3470), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U4588 ( .A0(n3469), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n3470), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
INVX3TS U4589 ( .A(n3470), .Y(n3471) );
AO22XLTS U4590 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n3470), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U4591 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n3470), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U4592 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n3470), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U4593 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n3470), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U4594 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n3468), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U4595 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U4596 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U4597 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U4598 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U4599 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO22XLTS U4600 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U4601 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U4602 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U4603 ( .A0(n3471), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
INVX2TS U4604 ( .A(n3468), .Y(n3473) );
AO22XLTS U4605 ( .A0(n3473), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U4606 ( .A0(n3473), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U4607 ( .A0(n3473), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U4608 ( .A0(n3473), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n3472), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
AOI21X1TS U4609 ( .A0(operation[1]), .A1(ack_operation), .B0(n3474), .Y(
n3485) );
NOR3XLTS U4610 ( .A(FPSENCOS_enab_RB3), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .C(FPSENCOS_enab_d_ff_RB1),
.Y(n3475) );
NAND3XLTS U4611 ( .A(n3476), .B(n3483), .C(n3475), .Y(n3477) );
BUFX4TS U4612 ( .A(n3010), .Y(n3569) );
NOR2BX1TS U4613 ( .AN(begin_operation), .B(n3569), .Y(n3479) );
OAI22X1TS U4614 ( .A0(n3485), .A1(n3477), .B0(n3479), .B1(n3478), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U4615 ( .AN(n3479), .B(n3478), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U4616 ( .A0(n3480), .A1(n3481), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI22X1TS U4617 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n3483), .B0(n3482), .B1(
n3481), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U4618 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n3483), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
AOI22X1TS U4619 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n3588), .B0(Data_2[0]), .B1(n959), .Y(n3487) );
AOI22X1TS U4620 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n3589),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n3486) );
NAND2X1TS U4621 ( .A(n3487), .B(n3486), .Y(add_subt_data2[0]) );
AOI22X1TS U4622 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n3592), .B0(Data_2[1]), .B1(n959), .Y(n3489) );
AOI22X1TS U4623 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n3488) );
NAND2X1TS U4624 ( .A(n3489), .B(n3488), .Y(add_subt_data2[1]) );
AOI22X1TS U4625 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n3503), .B0(Data_2[2]), .B1(n959), .Y(n3491) );
AOI22X1TS U4626 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n3490) );
NAND2X1TS U4627 ( .A(n3491), .B(n3490), .Y(add_subt_data2[2]) );
AOI22X1TS U4628 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n3503), .B0(Data_2[4]), .B1(n959), .Y(n3493) );
AOI22X1TS U4629 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n3492) );
NAND2X1TS U4630 ( .A(n3493), .B(n3492), .Y(add_subt_data2[4]) );
AOI22X1TS U4631 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n3503), .B0(Data_2[6]), .B1(n959), .Y(n3495) );
AOI22X1TS U4632 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n3494) );
NAND2X1TS U4633 ( .A(n3495), .B(n3494), .Y(add_subt_data2[6]) );
AOI22X1TS U4634 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n3503), .B0(Data_2[8]), .B1(n959), .Y(n3497) );
AOI22X1TS U4635 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n3496) );
NAND2X1TS U4636 ( .A(n3497), .B(n3496), .Y(add_subt_data2[8]) );
AOI22X1TS U4637 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n3503), .B0(Data_2[9]), .B1(n959), .Y(n3499) );
AOI22X1TS U4638 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n3498) );
NAND2X1TS U4639 ( .A(n3499), .B(n3498), .Y(add_subt_data2[9]) );
AOI22X1TS U4640 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n3503), .B0(
Data_2[10]), .B1(n3010), .Y(n3502) );
AOI22X1TS U4641 ( .A0(n3566), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n3500),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n3501) );
NAND2X1TS U4642 ( .A(n3502), .B(n3501), .Y(add_subt_data2[10]) );
AOI22X1TS U4643 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n3503), .B0(
Data_2[12]), .B1(n3010), .Y(n3505) );
AOI22X1TS U4644 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n3593),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n3504) );
NAND2X1TS U4645 ( .A(n3505), .B(n3504), .Y(add_subt_data2[12]) );
AOI22X1TS U4646 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n3592), .B0(
Data_2[21]), .B1(n3561), .Y(n3507) );
AOI22X1TS U4647 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n3593),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n3506) );
NAND2X1TS U4648 ( .A(n3507), .B(n3506), .Y(add_subt_data2[21]) );
AOI22X1TS U4649 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n3592), .B0(
Data_2[23]), .B1(n959), .Y(n3509) );
AOI22X1TS U4650 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n3593),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n3508) );
NAND2X1TS U4651 ( .A(n3509), .B(n3508), .Y(add_subt_data2[23]) );
AOI22X1TS U4652 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n3592), .B0(
Data_2[24]), .B1(n3010), .Y(n3511) );
AOI22X1TS U4653 ( .A0(n3585), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n3593),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n3510) );
NAND2X1TS U4654 ( .A(n3511), .B(n3510), .Y(add_subt_data2[24]) );
AOI22X1TS U4655 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n3592), .B0(
Data_2[25]), .B1(n3561), .Y(n3513) );
AOI22X1TS U4656 ( .A0(n3594), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n3593),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n3512) );
NAND2X1TS U4657 ( .A(n3513), .B(n3512), .Y(add_subt_data2[25]) );
AOI22X1TS U4658 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n3592), .B0(
Data_2[26]), .B1(n3561), .Y(n3515) );
AOI22X1TS U4659 ( .A0(n3594), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n3593),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n3514) );
NAND2X1TS U4660 ( .A(n3515), .B(n3514), .Y(add_subt_data2[26]) );
INVX2TS U4661 ( .A(operation[2]), .Y(n3517) );
AOI22X1TS U4662 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n3592), .B0(Data_1[0]), .B1(
n3561), .Y(n3520) );
AOI22X1TS U4663 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[0]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n3519) );
NAND2X1TS U4664 ( .A(n3520), .B(n3519), .Y(add_subt_data1[0]) );
AOI22X1TS U4665 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n3592), .B0(Data_1[1]), .B1(
n3561), .Y(n3522) );
AOI22X1TS U4666 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[1]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n3521) );
NAND2X1TS U4667 ( .A(n3522), .B(n3521), .Y(add_subt_data1[1]) );
AOI22X1TS U4668 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n3592), .B0(Data_1[2]), .B1(
n3561), .Y(n3524) );
AOI22X1TS U4669 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[2]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n3523) );
NAND2X1TS U4670 ( .A(n3524), .B(n3523), .Y(add_subt_data1[2]) );
AOI22X1TS U4671 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n3592), .B0(Data_1[3]), .B1(
n3561), .Y(n3526) );
AOI22X1TS U4672 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[3]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n3525) );
NAND2X1TS U4673 ( .A(n3526), .B(n3525), .Y(add_subt_data1[3]) );
AOI22X1TS U4674 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n3592), .B0(Data_1[4]), .B1(
n3561), .Y(n3528) );
AOI22X1TS U4675 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[4]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n3527) );
NAND2X1TS U4676 ( .A(n3528), .B(n3527), .Y(add_subt_data1[4]) );
AOI22X1TS U4677 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n3592), .B0(Data_1[5]), .B1(
n3561), .Y(n3530) );
AOI22X1TS U4678 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[5]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n3529) );
NAND2X1TS U4679 ( .A(n3530), .B(n3529), .Y(add_subt_data1[5]) );
AOI22X1TS U4680 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n3557), .B0(Data_1[6]), .B1(
n3561), .Y(n3534) );
AOI22X1TS U4681 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[6]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n3533) );
NAND2X1TS U4682 ( .A(n3534), .B(n3533), .Y(add_subt_data1[6]) );
AOI22X1TS U4683 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n3557), .B0(Data_1[7]), .B1(
n3561), .Y(n3536) );
AOI22X1TS U4684 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[7]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n3535) );
NAND2X1TS U4685 ( .A(n3536), .B(n3535), .Y(add_subt_data1[7]) );
AOI22X1TS U4686 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n3557), .B0(Data_1[8]), .B1(
n3561), .Y(n3538) );
AOI22X1TS U4687 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[8]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n3537) );
NAND2X1TS U4688 ( .A(n3538), .B(n3537), .Y(add_subt_data1[8]) );
AOI22X1TS U4689 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n3557), .B0(Data_1[9]), .B1(
n3569), .Y(n3540) );
AOI22X1TS U4690 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[9]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n3539) );
NAND2X1TS U4691 ( .A(n3540), .B(n3539), .Y(add_subt_data1[9]) );
AOI22X1TS U4692 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n3557), .B0(Data_1[10]),
.B1(n3569), .Y(n3542) );
AOI22X1TS U4693 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[10]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n3541) );
NAND2X1TS U4694 ( .A(n3542), .B(n3541), .Y(add_subt_data1[10]) );
AOI22X1TS U4695 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n3557), .B0(Data_1[11]),
.B1(n3569), .Y(n3544) );
AOI22X1TS U4696 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[11]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n3543) );
NAND2X1TS U4697 ( .A(n3544), .B(n3543), .Y(add_subt_data1[11]) );
AOI22X1TS U4698 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n3557), .B0(Data_1[12]),
.B1(n3569), .Y(n3546) );
AOI22X1TS U4699 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[12]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n3545) );
NAND2X1TS U4700 ( .A(n3546), .B(n3545), .Y(add_subt_data1[12]) );
AOI22X1TS U4701 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n3557), .B0(Data_1[13]),
.B1(n3569), .Y(n3548) );
AOI22X1TS U4702 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[13]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n3547) );
NAND2X1TS U4703 ( .A(n3548), .B(n3547), .Y(add_subt_data1[13]) );
AOI22X1TS U4704 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n3557), .B0(Data_1[14]),
.B1(n3569), .Y(n3550) );
AOI22X1TS U4705 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[14]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n3549) );
NAND2X1TS U4706 ( .A(n3550), .B(n3549), .Y(add_subt_data1[14]) );
AOI22X1TS U4707 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n3557), .B0(Data_1[15]),
.B1(n3569), .Y(n3552) );
AOI22X1TS U4708 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[15]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n3551) );
NAND2X1TS U4709 ( .A(n3552), .B(n3551), .Y(add_subt_data1[15]) );
AOI22X1TS U4710 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n3557), .B0(Data_1[16]),
.B1(n3569), .Y(n3554) );
AOI22X1TS U4711 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[16]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n3553) );
NAND2X1TS U4712 ( .A(n3554), .B(n3553), .Y(add_subt_data1[16]) );
AOI22X1TS U4713 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n3557), .B0(Data_1[17]),
.B1(n3569), .Y(n3556) );
AOI22X1TS U4714 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[17]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n3555) );
NAND2X1TS U4715 ( .A(n3556), .B(n3555), .Y(add_subt_data1[17]) );
AOI22X1TS U4716 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n3557), .B0(Data_1[18]),
.B1(n3569), .Y(n3560) );
AOI22X1TS U4717 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[18]), .B0(n3558), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n3559) );
NAND2X1TS U4718 ( .A(n3560), .B(n3559), .Y(add_subt_data1[18]) );
AOI22X1TS U4719 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n3588), .B0(Data_1[19]),
.B1(n3561), .Y(n3563) );
AOI22X1TS U4720 ( .A0(n3566), .A1(FPSENCOS_d_ff2_X[19]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n3562) );
NAND2X1TS U4721 ( .A(n3563), .B(n3562), .Y(add_subt_data1[19]) );
AOI22X1TS U4722 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n3588), .B0(Data_1[20]),
.B1(n3569), .Y(n3565) );
AOI22X1TS U4723 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[20]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n3564) );
NAND2X1TS U4724 ( .A(n3565), .B(n3564), .Y(add_subt_data1[20]) );
AOI22X1TS U4725 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n3588), .B0(Data_1[21]),
.B1(n3569), .Y(n3568) );
AOI22X1TS U4726 ( .A0(n3566), .A1(FPSENCOS_d_ff2_X[21]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n3567) );
NAND2X1TS U4727 ( .A(n3568), .B(n3567), .Y(add_subt_data1[21]) );
AOI22X1TS U4728 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n3588), .B0(Data_1[22]),
.B1(n3569), .Y(n3571) );
AOI22X1TS U4729 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[22]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n3570) );
NAND2X1TS U4730 ( .A(n3571), .B(n3570), .Y(add_subt_data1[22]) );
AOI22X1TS U4731 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3588), .B0(Data_1[23]),
.B1(n959), .Y(n3573) );
AOI22X1TS U4732 ( .A0(n3531), .A1(FPSENCOS_d_ff2_X[23]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n3572) );
NAND2X1TS U4733 ( .A(n3573), .B(n3572), .Y(add_subt_data1[23]) );
AOI22X1TS U4734 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n3588), .B0(Data_1[24]),
.B1(n959), .Y(n3575) );
AOI22X1TS U4735 ( .A0(n3585), .A1(FPSENCOS_d_ff2_X[24]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n3574) );
NAND2X1TS U4736 ( .A(n3575), .B(n3574), .Y(add_subt_data1[24]) );
AOI22X1TS U4737 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n3588), .B0(Data_1[25]),
.B1(n959), .Y(n3577) );
AOI22X1TS U4738 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[25]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n3576) );
NAND2X1TS U4739 ( .A(n3577), .B(n3576), .Y(add_subt_data1[25]) );
AOI22X1TS U4740 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n3588), .B0(Data_1[26]),
.B1(n959), .Y(n3579) );
AOI22X1TS U4741 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[26]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n3578) );
NAND2X1TS U4742 ( .A(n3579), .B(n3578), .Y(add_subt_data1[26]) );
AOI22X1TS U4743 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n3588), .B0(Data_1[27]),
.B1(n3010), .Y(n3581) );
AOI22X1TS U4744 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n3580) );
NAND2X1TS U4745 ( .A(n3581), .B(n3580), .Y(add_subt_data1[27]) );
AOI22X1TS U4746 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n3588), .B0(Data_1[28]),
.B1(n959), .Y(n3584) );
AOI22X1TS U4747 ( .A0(n3582), .A1(FPSENCOS_d_ff2_X[28]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n3583) );
NAND2X1TS U4748 ( .A(n3584), .B(n3583), .Y(add_subt_data1[28]) );
AOI22X1TS U4749 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n3588), .B0(Data_1[29]),
.B1(n959), .Y(n3587) );
AOI22X1TS U4750 ( .A0(n3585), .A1(FPSENCOS_d_ff2_X[29]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n3586) );
NAND2X1TS U4751 ( .A(n3587), .B(n3586), .Y(add_subt_data1[29]) );
AOI22X1TS U4752 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n3588), .B0(Data_1[30]),
.B1(n3010), .Y(n3591) );
AOI22X1TS U4753 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[30]), .B0(n3589), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n3590) );
NAND2X1TS U4754 ( .A(n3591), .B(n3590), .Y(add_subt_data1[30]) );
AOI22X1TS U4755 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n3592), .B0(Data_1[31]),
.B1(n3010), .Y(n3596) );
AOI22X1TS U4756 ( .A0(n3594), .A1(FPSENCOS_d_ff2_X[31]), .B0(n3593), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n3595) );
NAND2X1TS U4757 ( .A(n3596), .B(n3595), .Y(add_subt_data1[31]) );
OA21XLTS U4758 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3598), .B0(n3597), .Y(
FPSENCOS_ITER_CONT_N4) );
AOI22X1TS U4759 ( .A0(n3636), .A1(cordic_result[31]), .B0(n3635), .B1(
mult_result[31]), .Y(n3600) );
OAI2BB1X1TS U4760 ( .A0N(n3638), .A1N(result_add_subt[31]), .B0(n3600), .Y(
op_result[31]) );
AOI22X1TS U4761 ( .A0(n3636), .A1(cordic_result[30]), .B0(n3635), .B1(
mult_result[30]), .Y(n3601) );
OAI2BB1X1TS U4762 ( .A0N(n3626), .A1N(result_add_subt[30]), .B0(n3601), .Y(
op_result[30]) );
AOI22X1TS U4763 ( .A0(n3636), .A1(cordic_result[29]), .B0(n3635), .B1(
mult_result[29]), .Y(n3602) );
OAI2BB1X1TS U4764 ( .A0N(n3638), .A1N(result_add_subt[29]), .B0(n3602), .Y(
op_result[29]) );
AOI22X1TS U4765 ( .A0(n3636), .A1(cordic_result[28]), .B0(n3635), .B1(
mult_result[28]), .Y(n3603) );
OAI2BB1X1TS U4766 ( .A0N(n2885), .A1N(result_add_subt[28]), .B0(n3603), .Y(
op_result[28]) );
AOI22X1TS U4767 ( .A0(n3636), .A1(cordic_result[27]), .B0(n3635), .B1(
mult_result[27]), .Y(n3604) );
OAI2BB1X1TS U4768 ( .A0N(n2885), .A1N(result_add_subt[27]), .B0(n3604), .Y(
op_result[27]) );
AOI22X1TS U4769 ( .A0(n3636), .A1(cordic_result[26]), .B0(n3635), .B1(
mult_result[26]), .Y(n3605) );
OAI2BB1X1TS U4770 ( .A0N(n2885), .A1N(result_add_subt[26]), .B0(n3605), .Y(
op_result[26]) );
AOI22X1TS U4771 ( .A0(n3636), .A1(cordic_result[25]), .B0(n3635), .B1(
mult_result[25]), .Y(n3606) );
OAI2BB1X1TS U4772 ( .A0N(n2885), .A1N(result_add_subt[25]), .B0(n3606), .Y(
op_result[25]) );
AOI22X1TS U4773 ( .A0(n3636), .A1(cordic_result[24]), .B0(n3635), .B1(
mult_result[24]), .Y(n3607) );
OAI2BB1X1TS U4774 ( .A0N(n3626), .A1N(result_add_subt[24]), .B0(n3607), .Y(
op_result[24]) );
AOI22X1TS U4775 ( .A0(n3636), .A1(cordic_result[23]), .B0(n3635), .B1(
mult_result[23]), .Y(n3608) );
OAI2BB1X1TS U4776 ( .A0N(n3626), .A1N(result_add_subt[23]), .B0(n3608), .Y(
op_result[23]) );
AOI22X1TS U4777 ( .A0(n3636), .A1(cordic_result[22]), .B0(n3635), .B1(
mult_result[22]), .Y(n3609) );
OAI2BB1X1TS U4778 ( .A0N(n3626), .A1N(result_add_subt[22]), .B0(n3609), .Y(
op_result[22]) );
AOI22X1TS U4779 ( .A0(n3636), .A1(cordic_result[21]), .B0(n3635), .B1(
mult_result[21]), .Y(n3610) );
OAI2BB1X1TS U4780 ( .A0N(n3626), .A1N(result_add_subt[21]), .B0(n3610), .Y(
op_result[21]) );
AOI22X1TS U4781 ( .A0(n3636), .A1(cordic_result[20]), .B0(n3635), .B1(
mult_result[20]), .Y(n3611) );
OAI2BB1X1TS U4782 ( .A0N(n3626), .A1N(result_add_subt[20]), .B0(n3611), .Y(
op_result[20]) );
AOI22X1TS U4783 ( .A0(n3636), .A1(cordic_result[19]), .B0(n3635), .B1(
mult_result[19]), .Y(n3612) );
OAI2BB1X1TS U4784 ( .A0N(n3626), .A1N(result_add_subt[19]), .B0(n3612), .Y(
op_result[19]) );
AOI22X1TS U4785 ( .A0(n3633), .A1(cordic_result[18]), .B0(n3632), .B1(
mult_result[18]), .Y(n3613) );
OAI2BB1X1TS U4786 ( .A0N(n3626), .A1N(result_add_subt[18]), .B0(n3613), .Y(
op_result[18]) );
AOI22X1TS U4787 ( .A0(n3633), .A1(cordic_result[17]), .B0(n3632), .B1(
mult_result[17]), .Y(n3614) );
OAI2BB1X1TS U4788 ( .A0N(n3626), .A1N(result_add_subt[17]), .B0(n3614), .Y(
op_result[17]) );
AOI22X1TS U4789 ( .A0(n3633), .A1(cordic_result[16]), .B0(n3632), .B1(
mult_result[16]), .Y(n3615) );
OAI2BB1X1TS U4790 ( .A0N(n3626), .A1N(result_add_subt[16]), .B0(n3615), .Y(
op_result[16]) );
AOI22X1TS U4791 ( .A0(n3633), .A1(cordic_result[15]), .B0(n3632), .B1(
mult_result[15]), .Y(n3616) );
OAI2BB1X1TS U4792 ( .A0N(n3626), .A1N(result_add_subt[15]), .B0(n3616), .Y(
op_result[15]) );
AOI22X1TS U4793 ( .A0(n3633), .A1(cordic_result[14]), .B0(n3632), .B1(
mult_result[14]), .Y(n3617) );
OAI2BB1X1TS U4794 ( .A0N(n3626), .A1N(result_add_subt[14]), .B0(n3617), .Y(
op_result[14]) );
AOI22X1TS U4795 ( .A0(n3633), .A1(cordic_result[13]), .B0(n3632), .B1(
mult_result[13]), .Y(n3618) );
OAI2BB1X1TS U4796 ( .A0N(n3626), .A1N(result_add_subt[13]), .B0(n3618), .Y(
op_result[13]) );
AOI22X1TS U4797 ( .A0(n3633), .A1(cordic_result[12]), .B0(n3632), .B1(
mult_result[12]), .Y(n3619) );
OAI2BB1X1TS U4798 ( .A0N(n3626), .A1N(result_add_subt[12]), .B0(n3619), .Y(
op_result[12]) );
AOI22X1TS U4799 ( .A0(n3633), .A1(cordic_result[11]), .B0(n3632), .B1(
mult_result[11]), .Y(n3620) );
OAI2BB1X1TS U4800 ( .A0N(n3638), .A1N(result_add_subt[11]), .B0(n3620), .Y(
op_result[11]) );
AOI22X1TS U4801 ( .A0(n3633), .A1(cordic_result[10]), .B0(n3632), .B1(
mult_result[10]), .Y(n3621) );
OAI2BB1X1TS U4802 ( .A0N(n3638), .A1N(result_add_subt[10]), .B0(n3621), .Y(
op_result[10]) );
AOI22X1TS U4803 ( .A0(n3633), .A1(cordic_result[9]), .B0(n3632), .B1(
mult_result[9]), .Y(n3622) );
OAI2BB1X1TS U4804 ( .A0N(n3638), .A1N(result_add_subt[9]), .B0(n3622), .Y(
op_result[9]) );
AOI22X1TS U4805 ( .A0(n3633), .A1(cordic_result[8]), .B0(n3632), .B1(
mult_result[8]), .Y(n3623) );
OAI2BB1X1TS U4806 ( .A0N(n3638), .A1N(result_add_subt[8]), .B0(n3623), .Y(
op_result[8]) );
AOI22X1TS U4807 ( .A0(n3633), .A1(cordic_result[7]), .B0(n3632), .B1(
mult_result[7]), .Y(n3624) );
OAI2BB1X1TS U4808 ( .A0N(n3638), .A1N(result_add_subt[7]), .B0(n3624), .Y(
op_result[7]) );
AOI22X1TS U4809 ( .A0(n3633), .A1(cordic_result[6]), .B0(n3632), .B1(
mult_result[6]), .Y(n3625) );
OAI2BB1X1TS U4810 ( .A0N(n3626), .A1N(result_add_subt[6]), .B0(n3625), .Y(
op_result[6]) );
AOI22X1TS U4811 ( .A0(n3599), .A1(cordic_result[5]), .B0(n3629), .B1(
mult_result[5]), .Y(n3627) );
OAI2BB1X1TS U4812 ( .A0N(n3638), .A1N(result_add_subt[5]), .B0(n3627), .Y(
op_result[5]) );
AOI22X1TS U4813 ( .A0(n3599), .A1(cordic_result[4]), .B0(n3629), .B1(
mult_result[4]), .Y(n3628) );
OAI2BB1X1TS U4814 ( .A0N(n3638), .A1N(result_add_subt[4]), .B0(n3628), .Y(
op_result[4]) );
AOI22X1TS U4815 ( .A0(n3633), .A1(cordic_result[3]), .B0(n3629), .B1(
mult_result[3]), .Y(n3630) );
OAI2BB1X1TS U4816 ( .A0N(n3638), .A1N(result_add_subt[3]), .B0(n3630), .Y(
op_result[3]) );
AOI22X1TS U4817 ( .A0(n3636), .A1(cordic_result[2]), .B0(n3635), .B1(
mult_result[2]), .Y(n3631) );
OAI2BB1X1TS U4818 ( .A0N(n3638), .A1N(result_add_subt[2]), .B0(n3631), .Y(
op_result[2]) );
AOI22X1TS U4819 ( .A0(n3633), .A1(cordic_result[1]), .B0(n3632), .B1(
mult_result[1]), .Y(n3634) );
OAI2BB1X1TS U4820 ( .A0N(n3638), .A1N(result_add_subt[1]), .B0(n3634), .Y(
op_result[1]) );
AOI22X1TS U4821 ( .A0(n3636), .A1(cordic_result[0]), .B0(n3635), .B1(
mult_result[0]), .Y(n3637) );
OAI2BB1X1TS U4822 ( .A0N(n3638), .A1N(result_add_subt[0]), .B0(n3637), .Y(
op_result[0]) );
AOI22X1TS U4823 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3641), .B0(n3639),
.B1(n3743), .Y(n861) );
AOI22X1TS U4824 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3641), .B0(n3640),
.B1(n3743), .Y(n853) );
OAI2BB1X1TS U4825 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n851), .B0(n3642),
.Y(n852) );
AOI22X1TS U4826 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3644), .B0(n3643),
.B1(n3743), .Y(n848) );
INVX2TS U4827 ( .A(n3649), .Y(n3645) );
AOI22X1TS U4828 ( .A0(ack_operation), .A1(n3883), .B0(begin_operation), .B1(
n3645), .Y(n3647) );
OAI22X1TS U4829 ( .A0(n3649), .A1(n3648), .B0(n3647), .B1(n3646), .Y(n846)
);
OAI22X1TS U4830 ( .A0(n3653), .A1(n3652), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n3651), .Y(n844) );
AOI22X1TS U4831 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n3655), .B0(n3654),
.B1(n3700), .Y(n843) );
NAND2X1TS U4832 ( .A(n3656), .B(n3826), .Y(FPADDSUB__6_net_) );
NOR4X1TS U4833 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[2]), .C(
FPMULT_Op_MY[3]), .D(FPMULT_Op_MY[14]), .Y(n3660) );
NOR4X1TS U4834 ( .A(n992), .B(FPMULT_Op_MY[16]), .C(n989), .D(n983), .Y(
n3659) );
NOR4X1TS U4835 ( .A(FPMULT_Op_MY[24]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[27]), .Y(n3658) );
NOR4X1TS U4836 ( .A(FPMULT_Op_MY[28]), .B(FPMULT_Op_MY[29]), .C(
FPMULT_Op_MY[11]), .D(FPMULT_Op_MY[30]), .Y(n3657) );
NAND4XLTS U4837 ( .A(n3660), .B(n3659), .C(n3658), .D(n3657), .Y(n3676) );
NOR4X1TS U4838 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[5]), .C(
FPMULT_Op_MY[6]), .D(FPMULT_Op_MY[8]), .Y(n3663) );
NOR3XLTS U4839 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[12]), .C(
FPMULT_Op_MY[23]), .Y(n3661) );
NAND4XLTS U4840 ( .A(n3664), .B(n3663), .C(n3662), .D(n3661), .Y(n3675) );
NOR4X1TS U4841 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[15]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[14]), .Y(n3667) );
NOR4X1TS U4842 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_Op_MX[25]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[27]), .Y(n3666) );
NAND4XLTS U4843 ( .A(n3668), .B(n3667), .C(n3666), .D(n3665), .Y(n3674) );
NOR3XLTS U4844 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(
FPMULT_Op_MX[24]), .Y(n3669) );
NAND4XLTS U4845 ( .A(n3672), .B(n3671), .C(n3670), .D(n3669), .Y(n3673) );
OAI22X1TS U4846 ( .A0(n3676), .A1(n3675), .B0(n3674), .B1(n3673), .Y(n106)
);
AO22XLTS U4847 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n3826), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
AO22XLTS U4848 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n3734), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n816) );
XNOR2X1TS U4849 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n3929), .Y(n30) );
AO22XLTS U4850 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n3826), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n813) );
NOR2BX1TS U4851 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
XOR2XLTS U4852 ( .A(n3677), .B(FPSENCOS_d_ff2_Y[30]), .Y(
FPSENCOS_sh_exp_y[7]) );
XNOR2X1TS U4853 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3678), .Y(
FPSENCOS_sh_exp_y[6]) );
AO21XLTS U4854 ( .A0(intadd_1037_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n3679),
.Y(FPSENCOS_sh_exp_y[4]) );
XOR2XLTS U4855 ( .A(n3680), .B(FPSENCOS_d_ff2_X[30]), .Y(
FPSENCOS_sh_exp_x[7]) );
XNOR2X1TS U4856 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3681), .Y(
FPSENCOS_sh_exp_x[6]) );
AO21XLTS U4857 ( .A0(intadd_1036_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3682),
.Y(FPSENCOS_sh_exp_x[4]) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_KOA_1STAGE_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_PP_BLACKBOX_V
|
// --------------------------------------------------------------------
// ng_AGC CPM Micro code ROM decoder
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_SUB(
input [ 7:0] SUBSEQ, // Sub-Sequence input
output [22:0] SUBSEQ_BUS // Sub sequence output
);
// --------------------------------------------------------------------
// Input assignments:
// --------------------------------------------------------------------
wire SB_02 = SUBSEQ[ 7]; // Sub-Select 2
wire SB_01 = SUBSEQ[ 6]; // Sub-Select 1
wire [ 3:0] SQ = SUBSEQ[5:2]; // Sequence Pulses
wire STB_1 = SUBSEQ[ 1]; // Stage 1
wire STB_0 = SUBSEQ[ 0]; // Stage 0
// --------------------------------------------------------------------
// Output assignments
// --------------------------------------------------------------------
assign SUBSEQ_BUS[22 ] = PINC;
assign SUBSEQ_BUS[21 ] = MINC;
assign SUBSEQ_BUS[20:0] = NSUBSQ;
// --------------------------------------------------------------------
// Sub-branch decode
// --------------------------------------------------------------------
wire PINC = !( SB_01 & !SB_02); // Decode SB signals
wire MINC = !(!SB_01 & SB_02);
// --------------------------------------------------------------------
// Sub Sequence decoder - only needed for debugging
// --------------------------------------------------------------------
reg [19:0] NSUBSQ; // Sub sequence output
wire [5:0] subseq = {SQ[3:0], STB_1,STB_0}; // Decoder address
always @(subseq) begin // (Dec) (Oct) (Dec Dec)
case(subseq) // Sgnl Indx Row Col
6'b0000_00 : NSUBSQ <= 20'b11111111111111111110; // TC0 = 0 o00 _ 0 0
6'b0001_00 : NSUBSQ <= 20'b11111111111111111101; // CCS0 = 1 o01 _ 0 1
6'b0010_00 : NSUBSQ <= 20'b11111111111111111011; // CCS1 = 2 o02 _ 0 2
6'b0011_00 : NSUBSQ <= 20'b11111111111111110111; // NDX0 = 3 o03 _ 0 3
6'b1001_00 : NSUBSQ <= 20'b11111111111111101111; // NDX1 = 4 o11 _ 0 4
6'b1010_00 : NSUBSQ <= 20'b11111111111111011111; // RSM3 = 5 o12 _ 0 5
6'b1011_00 : NSUBSQ <= 20'b11111111111110111111; // XCH0 = 6 o13 _ 0 6
6'b1100_00 : NSUBSQ <= 20'b11111111111101111111; // CS0 = 7 o14 _ 0 7
6'b1101_00 : NSUBSQ <= 20'b11111111111011111111; // TS0 = 8 o15 _ 0 8
6'b1110_00 : NSUBSQ <= 20'b11111111110111111111; // AD0 = 9 o16 _ 0 9
6'b1111_00 : NSUBSQ <= 20'b11111111101111111111; // MASK0 = 10 o17 _ 0 10
6'b0000_01 : NSUBSQ <= 20'b11111111011111111111; // MP0 = 11 o00 _ 1 11
6'b0001_01 : NSUBSQ <= 20'b11111110111111111111; // MP1 = 12 o01 _ 1 12
6'b0010_01 : NSUBSQ <= 20'b11111101111111111111; // MP3 = 13 o02 _ 1 13
6'b1001_01 : NSUBSQ <= 20'b11111011111111111111; // DV0 = 14 o11 _ 1 14
6'b1010_01 : NSUBSQ <= 20'b11110111111111111111; // DV1 = 15 o12 _ 1 15
6'b0000_10 : NSUBSQ <= 20'b11101111111111111111; // SU0 = 16 o00 _ 2 16
6'b0011_10 : NSUBSQ <= 20'b11011111111111111111; // RUPT1 = 17 o03 _ 2 17
6'b1010_10 : NSUBSQ <= 20'b10111111111111111111; // RUPT3 = 18 o12 _ 2 18
6'b1011_10 : NSUBSQ <= 20'b01111111111111111111; // STD2 = 19 o13 _ 2 19
default : NSUBSQ <= 20'b11111111111111111111; // NOSEQ = XX All others
endcase
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkbuf (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_log.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc, [email protected] ////
//// - Tadej Markovic, [email protected] ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, [email protected] ////
//// Tadej Markovic, [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
module uart_log;
parameter testcase_name = "";
integer report_log_file_desc;
integer verbose_log_file_desc;
reg free;
integer tests_ok;
integer tests_failed;
initial free = 1;
initial tests_ok = 0;
initial tests_failed = 0;
task start_log;
output ok_o;
begin
report_log_file_desc = $fopen({"../log/", testcase_name, "_report.log"});
verbose_log_file_desc = $fopen({"../log/", testcase_name, "_verbose.log"});
if ((report_log_file_desc == 0) || (verbose_log_file_desc == 0))
ok_o = 1'b0;
else
ok_o = 1'b1;
end
endtask // start_log
task end_log;
begin
report_add_delimiter;
$fdisplay(report_log_file_desc, "TEST CASE execution summary:");
$fdisplay(report_log_file_desc, "Number of tests PASSED=%0d", tests_ok);
$fdisplay(report_log_file_desc, "Number of tests FAILED=%0d", tests_failed);
$fdisplay(report_log_file_desc, " Simulation End Time: %t", $time);
report_add_delimiter;
$fclose(report_log_file_desc);
$fclose(verbose_log_file_desc);
end
endtask // end_log
task report_test_name;
input [1599:0] test_i;
begin
report_add_delimiter;
$fdisplay(report_log_file_desc, "%0s", test_i);
end
endtask // report_test_name
task report_test_failed;
input [7999:0] message_i;
begin
$fdisplay(report_log_file_desc, " FAILED!");
$fdisplay(report_log_file_desc, " Failure message: %0s.", message_i);
$fdisplay(report_log_file_desc, " Simulation Time: %t", $time);
end
endtask // report_test_failed
task report_test_ok;
begin
$fdisplay(report_log_file_desc, " PASSED!");
$fdisplay(report_log_file_desc, " Simulation Time: %t", $time);
end
endtask // report_test_ok
task report_add_delimiter;
begin
$fdisplay(report_log_file_desc, "");
$fdisplay(report_log_file_desc, "%0s", {75{"-"}});
$fdisplay(report_log_file_desc, "");
end
endtask // report_add_delimiter
task report_add_text;
input [7999:0] text_i;
begin
$fdisplay(report_log_file_desc, " %0s", text_i);
end
endtask // report_add_text
task verbose_test_name;
input [1599:0] test_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "");
$fdisplay(verbose_log_file_desc, "%0s", {75{"-"}});
$fdisplay(verbose_log_file_desc, "- %0s", test_i);
$fdisplay(verbose_log_file_desc, "%0s", {75{"-"}});
$fdisplay(verbose_log_file_desc, "");
free = 1;
end
endtask // verbose_test_name
task verbose_severe_err;
input [7999:0] time_i;
input [7999:0] severe_error_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*E, Reporting severe error:");
$fdisplay(verbose_log_file_desc, " %0s", severe_error_i);
free = 1;
end
endtask // verbose_severe_err
task verbose_err;
input [7999:0] time_i;
input [7999:0] error_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*E, %0s", error_i);
free = 1;
end
endtask // verbose_err
task verbose_wrn;
input [7999:0] time_i;
input [7999:0] warning_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*W, %0s", warning_i);
free = 1;
end
endtask // verbose_wrn
task verbose_msg;
input [7999:0] time_i;
input [7999:0] message_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*N, %0s", message_i);
free = 1;
end
endtask // verbose_msg
task verbose_val;
input [7999:0] time_i;
input [7999:0] message_i;
input [31:0] value_i;
begin
free = 0;
$fdisplay(verbose_log_file_desc, "%0s", time_i);
$fdisplay(verbose_log_file_desc, "*N, %0s %0h.", message_i, value_i);
free = 1;
end
endtask // verbose_val
endmodule // uart_log
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 11:48:22 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/fifo_generator_rx_inst/fifo_generator_rx_inst_sim_netlist.v
// Design : fifo_generator_rx_inst
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module fifo_generator_rx_inst
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [11:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [11:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [11:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4094" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "4093" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
fifo_generator_rx_inst_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[11:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[11:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[11:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module fifo_generator_rx_inst_blk_mem_gen_generic_cstr
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.clk(clk),
.din(din[3:0]),
.dout(dout[3:0]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.clk(clk),
.din(din[12:4]),
.dout(dout[12:4]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.Q(Q),
.clk(clk),
.din(din[21:13]),
.dout(dout[21:13]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.Q(Q),
.clk(clk),
.din(din[30:22]),
.dout(dout[30:22]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.Q(Q),
.clk(clk),
.din(din[39:31]),
.dout(dout[39:31]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.Q(Q),
.clk(clk),
.din(din[48:40]),
.dout(dout[48:40]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.Q(Q),
.clk(clk),
.din(din[57:49]),
.dout(dout[57:49]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.Q(Q),
.clk(clk),
.din(din[63:58]),
.dout(dout[63:58]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [3:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [3:0]din;
wire [11:0]Q;
wire clk;
wire [3:0]din;
wire [3:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized3
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized5
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_width__parameterized6
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [5:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [5:0]din;
wire [11:0]Q;
wire clk;
wire [5:0]din;
wire [5:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [3:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [3:0]din;
wire [11:0]Q;
wire clk;
wire [3:0]din;
wire [3:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({Q,1'b0,1'b0}),
.ADDRBWRADDR({\gc0.count_d1_reg[11] ,1'b0,1'b0}),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized3
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized5
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module fifo_generator_rx_inst_blk_mem_gen_prim_wrapper__parameterized6
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [5:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [5:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [11:0]Q;
wire clk;
wire [5:0]din;
wire [5:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module fifo_generator_rx_inst_blk_mem_gen_top
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_4" *)
module fifo_generator_rx_inst_blk_mem_gen_v8_3_4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_4_synth" *)
module fifo_generator_rx_inst_blk_mem_gen_v8_3_4_synth
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_generator_rx_inst_compare
(ram_full_comb,
v1_reg,
wr_en,
comp1,
wr_rst_busy,
out,
E);
output ram_full_comb;
input [5:0]v1_reg;
input wr_en;
input comp1;
input wr_rst_busy;
input out;
input [0:0]E;
wire [0:0]E;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire out;
wire ram_full_comb;
wire [5:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT6 #(
.INIT(64'h0055000000FFC0C0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(wr_rst_busy),
.I4(out),
.I5(E),
.O(ram_full_comb));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_generator_rx_inst_compare_3
(comp1,
v1_reg_0);
output comp1;
input [5:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire [5:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg_0[5:4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_generator_rx_inst_compare_4
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gcc0.gc0.count_d1_reg[10] ,\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module fifo_generator_rx_inst_compare_5
(comp1,
v1_reg);
output comp1;
input [5:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire [5:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module fifo_generator_rx_inst_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.rd_n_14 ;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire \gntv_or_sync_fifo.gl0.wr_n_23 ;
wire \gntv_or_sync_fifo.gl0.wr_n_24 ;
wire \gntv_or_sync_fifo.gl0.wr_n_25 ;
wire \gntv_or_sync_fifo.gl0.wr_n_26 ;
wire [5:0]\grss.rsts/c2/v1_reg ;
wire [11:0]p_0_out;
wire [11:0]p_11_out;
wire p_2_out;
wire rd_en;
wire [11:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_en;
wire wr_rst_busy;
wire [1:1]wr_rst_i;
fifo_generator_rx_inst_rd_logic \gntv_or_sync_fifo.gl0.rd
(.D(rd_pntr_plus1),
.E(\gntv_or_sync_fifo.gl0.rd_n_14 ),
.Q(p_0_out),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.wr_n_26 ),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_23 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_24 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_25 ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (rd_rst_i[2]),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.rd_en(rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
fifo_generator_rx_inst_wr_logic \gntv_or_sync_fifo.gl0.wr
(.D(rd_pntr_plus1),
.E(\gntv_or_sync_fifo.gl0.rd_n_14 ),
.Q(p_11_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[11] (p_0_out),
.\gcc0.gc0.count_d1_reg[11] (\gntv_or_sync_fifo.gl0.wr_n_2 ),
.\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (wr_rst_i),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_23 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_24 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_25 ),
.ram_empty_i_reg_4(\gntv_or_sync_fifo.gl0.wr_n_26 ),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
fifo_generator_rx_inst_memory \gntv_or_sync_fifo.mem
(.Q(p_11_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (p_0_out),
.out(rd_rst_i[0]),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.tmp_ram_rd_en(tmp_ram_rd_en));
fifo_generator_rx_inst_reset_blk_ramfifo rstblk
(.clk(clk),
.\gc0.count_reg[0] ({rd_rst_i[2],rd_rst_i[0]}),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module fifo_generator_rx_inst_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
fifo_generator_rx_inst_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4094" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "4093" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_2" *)
module fifo_generator_rx_inst_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [11:0]prog_empty_thresh;
input [11:0]prog_empty_thresh_assert;
input [11:0]prog_empty_thresh_negate;
input [11:0]prog_full_thresh;
input [11:0]prog_full_thresh_assert;
input [11:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [11:0]data_count;
output [11:0]rd_data_count;
output [11:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[11] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[11] = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[11] = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
fifo_generator_rx_inst_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_1_2_synth" *)
module fifo_generator_rx_inst_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
fifo_generator_rx_inst_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "memory" *)
module fifo_generator_rx_inst_memory
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
fifo_generator_rx_inst_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module fifo_generator_rx_inst_rd_bin_cntr
(D,
Q,
ram_empty_fb_i_reg,
clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output [11:0]D;
output [11:0]Q;
input ram_empty_fb_i_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [11:0]D;
wire [11:0]Q;
wire clk;
wire \gc0.count[0]_i_2_n_0 ;
wire \gc0.count[0]_i_3_n_0 ;
wire \gc0.count[0]_i_4_n_0 ;
wire \gc0.count[0]_i_5_n_0 ;
wire \gc0.count[4]_i_2_n_0 ;
wire \gc0.count[4]_i_3_n_0 ;
wire \gc0.count[4]_i_4_n_0 ;
wire \gc0.count[4]_i_5_n_0 ;
wire \gc0.count[8]_i_2_n_0 ;
wire \gc0.count[8]_i_3_n_0 ;
wire \gc0.count[8]_i_4_n_0 ;
wire \gc0.count[8]_i_5_n_0 ;
wire \gc0.count_reg[0]_i_1_n_0 ;
wire \gc0.count_reg[0]_i_1_n_1 ;
wire \gc0.count_reg[0]_i_1_n_2 ;
wire \gc0.count_reg[0]_i_1_n_3 ;
wire \gc0.count_reg[0]_i_1_n_4 ;
wire \gc0.count_reg[0]_i_1_n_5 ;
wire \gc0.count_reg[0]_i_1_n_6 ;
wire \gc0.count_reg[0]_i_1_n_7 ;
wire \gc0.count_reg[4]_i_1_n_0 ;
wire \gc0.count_reg[4]_i_1_n_1 ;
wire \gc0.count_reg[4]_i_1_n_2 ;
wire \gc0.count_reg[4]_i_1_n_3 ;
wire \gc0.count_reg[4]_i_1_n_4 ;
wire \gc0.count_reg[4]_i_1_n_5 ;
wire \gc0.count_reg[4]_i_1_n_6 ;
wire \gc0.count_reg[4]_i_1_n_7 ;
wire \gc0.count_reg[8]_i_1_n_1 ;
wire \gc0.count_reg[8]_i_1_n_2 ;
wire \gc0.count_reg[8]_i_1_n_3 ;
wire \gc0.count_reg[8]_i_1_n_4 ;
wire \gc0.count_reg[8]_i_1_n_5 ;
wire \gc0.count_reg[8]_i_1_n_6 ;
wire \gc0.count_reg[8]_i_1_n_7 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire ram_empty_fb_i_reg;
wire [3:3]\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_2
(.I0(D[3]),
.O(\gc0.count[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_3
(.I0(D[2]),
.O(\gc0.count[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_4
(.I0(D[1]),
.O(\gc0.count[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_5
(.I0(D[0]),
.O(\gc0.count[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_2
(.I0(D[7]),
.O(\gc0.count[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_3
(.I0(D[6]),
.O(\gc0.count[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_4
(.I0(D[5]),
.O(\gc0.count[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_5
(.I0(D[4]),
.O(\gc0.count[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_2
(.I0(D[11]),
.O(\gc0.count[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_3
(.I0(D[10]),
.O(\gc0.count[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_4
(.I0(D[9]),
.O(\gc0.count[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_5
(.I0(D[8]),
.O(\gc0.count[8]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[11]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.D(\gc0.count_reg[0]_i_1_n_7 ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(D[0]));
CARRY4 \gc0.count_reg[0]_i_1
(.CI(1'b0),
.CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }),
.S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_5 ),
.Q(D[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[11]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_4 ),
.Q(D[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[0]_i_1_n_6 ),
.Q(D[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[0]_i_1_n_5 ),
.Q(D[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[0]_i_1_n_4 ),
.Q(D[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_7 ),
.Q(D[4]));
CARRY4 \gc0.count_reg[4]_i_1
(.CI(\gc0.count_reg[0]_i_1_n_0 ),
.CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }),
.S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_6 ),
.Q(D[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_5 ),
.Q(D[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_4 ),
.Q(D[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_7 ),
.Q(D[8]));
CARRY4 \gc0.count_reg[8]_i_1
(.CI(\gc0.count_reg[4]_i_1_n_0 ),
.CO({\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }),
.S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_6 ),
.Q(D[9]));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module fifo_generator_rx_inst_rd_logic
(out,
empty,
D,
E,
Q,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
v1_reg,
clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [11:0]D;
output [0:0]E;
output [11:0]Q;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input [5:0]v1_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [11:0]D;
wire [0:0]E;
wire [11:0]Q;
wire clk;
wire empty;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire out;
wire ram_full_fb_i_reg;
wire rd_en;
wire [5:0]v1_reg;
wire wr_en;
fifo_generator_rx_inst_rd_status_flags_ss \grss.rsts
(.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[11] (E),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
fifo_generator_rx_inst_rd_bin_cntr rpntr
(.D(D),
.Q(Q),
.clk(clk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.ram_empty_fb_i_reg(E));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_ss" *)
module fifo_generator_rx_inst_rd_status_flags_ss
(out,
empty,
\gc0.count_d1_reg[11] ,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
v1_reg,
clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output \gc0.count_d1_reg[11] ;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input [5:0]v1_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire c1_n_0;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire [5:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
fifo_generator_rx_inst_compare_4 c1
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
fifo_generator_rx_inst_compare_5 c2
(.comp1(comp1),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[11]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(\gc0.count_d1_reg[11] ));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module fifo_generator_rx_inst_reset_blk_ramfifo
(out,
\gc0.count_reg[0] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [0:0]out;
output [1:0]\gc0.count_reg[0] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire clk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[0] [1] = rd_rst_reg[2];
assign \gc0.count_reg[0] [0] = rd_rst_reg[0];
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[0] = wr_rst_reg[1];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
fifo_generator_rx_inst_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.clk(clk),
.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out));
fifo_generator_rx_inst_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.clk(clk),
.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out));
fifo_generator_rx_inst_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.clk(clk),
.in0(rd_rst_asreg),
.out(p_7_out));
fifo_generator_rx_inst_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.clk(clk),
.in0(wr_rst_asreg),
.out(p_8_out));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_generator_rx_inst_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_generator_rx_inst_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_generator_rx_inst_synchronizer_ff_1
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module fifo_generator_rx_inst_synchronizer_ff_2
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module fifo_generator_rx_inst_wr_bin_cntr
(v1_reg_0,
Q,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
ram_empty_i_reg_4,
ram_full_fb_i_reg,
clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
\gc0.count_d1_reg[11] ,
D);
output [5:0]v1_reg_0;
output [11:0]Q;
output [5:0]v1_reg;
output [5:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
output ram_empty_i_reg_4;
input ram_full_fb_i_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [11:0]\gc0.count_d1_reg[11] ;
input [11:0]D;
wire [11:0]D;
wire [11:0]Q;
wire clk;
wire [11:0]\gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count[0]_i_2_n_0 ;
wire \gcc0.gc0.count[0]_i_3_n_0 ;
wire \gcc0.gc0.count[0]_i_4_n_0 ;
wire \gcc0.gc0.count[0]_i_5_n_0 ;
wire \gcc0.gc0.count[4]_i_2_n_0 ;
wire \gcc0.gc0.count[4]_i_3_n_0 ;
wire \gcc0.gc0.count[4]_i_4_n_0 ;
wire \gcc0.gc0.count[4]_i_5_n_0 ;
wire \gcc0.gc0.count[8]_i_2_n_0 ;
wire \gcc0.gc0.count[8]_i_3_n_0 ;
wire \gcc0.gc0.count[8]_i_4_n_0 ;
wire \gcc0.gc0.count[8]_i_5_n_0 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_0 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_7 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_0 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_7 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_7 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [11:0]p_12_out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire ram_empty_i_reg_4;
wire ram_full_fb_i_reg;
wire [5:0]v1_reg;
wire [5:0]v1_reg_0;
wire [5:0]v1_reg_1;
wire [3:3]\NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_2
(.I0(p_12_out[3]),
.O(\gcc0.gc0.count[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_3
(.I0(p_12_out[2]),
.O(\gcc0.gc0.count[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_4
(.I0(p_12_out[1]),
.O(\gcc0.gc0.count[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_5
(.I0(p_12_out[0]),
.O(\gcc0.gc0.count[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_2
(.I0(p_12_out[7]),
.O(\gcc0.gc0.count[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_3
(.I0(p_12_out[6]),
.O(\gcc0.gc0.count[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_4
(.I0(p_12_out[5]),
.O(\gcc0.gc0.count[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_5
(.I0(p_12_out[4]),
.O(\gcc0.gc0.count[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_2
(.I0(p_12_out[11]),
.O(\gcc0.gc0.count[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_3
(.I0(p_12_out[10]),
.O(\gcc0.gc0.count[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_4
(.I0(p_12_out[9]),
.O(\gcc0.gc0.count[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_5
(.I0(p_12_out[8]),
.O(\gcc0.gc0.count[8]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[10]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[11]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[0]_i_1_n_7 ),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(p_12_out[0]));
CARRY4 \gcc0.gc0.count_reg[0]_i_1
(.CI(1'b0),
.CO({\gcc0.gc0.count_reg[0]_i_1_n_0 ,\gcc0.gc0.count_reg[0]_i_1_n_1 ,\gcc0.gc0.count_reg[0]_i_1_n_2 ,\gcc0.gc0.count_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\gcc0.gc0.count_reg[0]_i_1_n_4 ,\gcc0.gc0.count_reg[0]_i_1_n_5 ,\gcc0.gc0.count_reg[0]_i_1_n_6 ,\gcc0.gc0.count_reg[0]_i_1_n_7 }),
.S({\gcc0.gc0.count[0]_i_2_n_0 ,\gcc0.gc0.count[0]_i_3_n_0 ,\gcc0.gc0.count[0]_i_4_n_0 ,\gcc0.gc0.count[0]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[10]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_5 ),
.Q(p_12_out[10]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[11]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_4 ),
.Q(p_12_out[11]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[0]_i_1_n_6 ),
.Q(p_12_out[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[0]_i_1_n_5 ),
.Q(p_12_out[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[0]_i_1_n_4 ),
.Q(p_12_out[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_7 ),
.Q(p_12_out[4]));
CARRY4 \gcc0.gc0.count_reg[4]_i_1
(.CI(\gcc0.gc0.count_reg[0]_i_1_n_0 ),
.CO({\gcc0.gc0.count_reg[4]_i_1_n_0 ,\gcc0.gc0.count_reg[4]_i_1_n_1 ,\gcc0.gc0.count_reg[4]_i_1_n_2 ,\gcc0.gc0.count_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gcc0.gc0.count_reg[4]_i_1_n_4 ,\gcc0.gc0.count_reg[4]_i_1_n_5 ,\gcc0.gc0.count_reg[4]_i_1_n_6 ,\gcc0.gc0.count_reg[4]_i_1_n_7 }),
.S({\gcc0.gc0.count[4]_i_2_n_0 ,\gcc0.gc0.count[4]_i_3_n_0 ,\gcc0.gc0.count[4]_i_4_n_0 ,\gcc0.gc0.count[4]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_6 ),
.Q(p_12_out[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_5 ),
.Q(p_12_out[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_4 ),
.Q(p_12_out[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_7 ),
.Q(p_12_out[8]));
CARRY4 \gcc0.gc0.count_reg[8]_i_1
(.CI(\gcc0.gc0.count_reg[4]_i_1_n_0 ),
.CO({\NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gcc0.gc0.count_reg[8]_i_1_n_1 ,\gcc0.gc0.count_reg[8]_i_1_n_2 ,\gcc0.gc0.count_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gcc0.gc0.count_reg[8]_i_1_n_4 ,\gcc0.gc0.count_reg[8]_i_1_n_5 ,\gcc0.gc0.count_reg[8]_i_1_n_6 ,\gcc0.gc0.count_reg[8]_i_1_n_7 }),
.S({\gcc0.gc0.count[8]_i_2_n_0 ,\gcc0.gc0.count[8]_i_3_n_0 ,\gcc0.gc0.count[8]_i_4_n_0 ,\gcc0.gc0.count[8]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_6 ),
.Q(p_12_out[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(Q[0]),
.I1(D[0]),
.I2(Q[1]),
.I3(D[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(Q[2]),
.I1(D[2]),
.I2(Q[3]),
.I3(D[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(Q[4]),
.I1(D[4]),
.I2(Q[5]),
.I3(D[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(Q[6]),
.I1(D[6]),
.I2(Q[7]),
.I3(D[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(Q[8]),
.I1(D[8]),
.I2(Q[9]),
.I3(D[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(ram_empty_i_reg_3));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(Q[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(v1_reg_0[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__0
(.I0(Q[10]),
.I1(D[10]),
.I2(Q[11]),
.I3(D[11]),
.O(v1_reg[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__1
(.I0(p_12_out[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(p_12_out[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(v1_reg_1[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__2
(.I0(Q[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(Q[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(ram_empty_i_reg_4));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module fifo_generator_rx_inst_wr_logic
(out,
full,
\gcc0.gc0.count_d1_reg[11] ,
Q,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
ram_empty_i_reg_4,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
wr_en,
\gc0.count_d1_reg[11] ,
D,
wr_rst_busy,
E);
output out;
output full;
output \gcc0.gc0.count_d1_reg[11] ;
output [11:0]Q;
output [5:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
output ram_empty_i_reg_4;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input wr_en;
input [11:0]\gc0.count_d1_reg[11] ;
input [11:0]D;
input wr_rst_busy;
input [0:0]E;
wire [11:0]D;
wire [0:0]E;
wire [11:0]Q;
wire [5:0]\c0/v1_reg ;
wire [5:0]\c1/v1_reg ;
wire clk;
wire full;
wire [11:0]\gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count_d1_reg[11] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire ram_empty_i_reg_4;
wire [5:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
fifo_generator_rx_inst_wr_status_flags_ss \gwss.wsts
(.E(E),
.clk(clk),
.full(full),
.\gcc0.gc0.count_d1_reg[11] (\gcc0.gc0.count_d1_reg[11] ),
.\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ),
.out(out),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
fifo_generator_rx_inst_wr_bin_cntr wpntr
(.D(D),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.ram_empty_i_reg_4(ram_empty_i_reg_4),
.ram_full_fb_i_reg(\gcc0.gc0.count_d1_reg[11] ),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_ss" *)
module fifo_generator_rx_inst_wr_status_flags_ss
(out,
full,
\gcc0.gc0.count_d1_reg[11] ,
v1_reg,
v1_reg_0,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy,
E);
output out;
output full;
output \gcc0.gc0.count_d1_reg[11] ;
input [5:0]v1_reg;
input [5:0]v1_reg_0;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
input [0:0]E;
wire [0:0]E;
wire clk;
wire comp1;
wire \gcc0.gc0.count_d1_reg[11] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire ram_full_comb;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [5:0]v1_reg;
wire [5:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(\gcc0.gc0.count_d1_reg[11] ));
fifo_generator_rx_inst_compare c0
(.E(E),
.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_comb(ram_full_comb),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
fifo_generator_rx_inst_compare_3 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b1),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b1),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Sun Mar 13 07:43:22 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/dcfifo_32in_32out_8kb/dcfifo_32in_32out_8kb_stub.v
// Design : dcfifo_32in_32out_8kb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_8kb(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[1:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [1:0]wr_data_count;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p0_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p0_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
scache0_pcx_stall_bufp0even_pq,
// Inputs
arbpc0_pcxdp_grant_bufp1_pa_l, arbpc0_pcxdp_q0_hold_bufp1_pa,
arbpc0_pcxdp_qsel0_bufp1_pa_l, arbpc0_pcxdp_qsel1_bufp1_pa,
arbpc0_pcxdp_shift_bufp1_px_l, arbpc2_pcxdp_grant_bufp1_pa_l,
arbpc2_pcxdp_q0_hold_bufp1_pa, arbpc2_pcxdp_qsel0_bufp1_pa_l,
arbpc2_pcxdp_qsel1_bufp1_pa, arbpc2_pcxdp_shift_bufp1_px_l,
scache0_pcx_stall_pq
);
output arbpc0_pcxdp_grant_pa;
output arbpc0_pcxdp_q0_hold_pa_l;
output arbpc0_pcxdp_qsel0_pa;
output arbpc0_pcxdp_qsel1_pa_l;
output arbpc0_pcxdp_shift_px;
output arbpc2_pcxdp_grant_pa;
output arbpc2_pcxdp_q0_hold_pa_l;
output arbpc2_pcxdp_qsel0_pa;
output arbpc2_pcxdp_qsel1_pa_l;
output arbpc2_pcxdp_shift_px;
output scache0_pcx_stall_bufp0even_pq;
input arbpc0_pcxdp_grant_bufp1_pa_l;
input arbpc0_pcxdp_q0_hold_bufp1_pa;
input arbpc0_pcxdp_qsel0_bufp1_pa_l;
input arbpc0_pcxdp_qsel1_bufp1_pa;
input arbpc0_pcxdp_shift_bufp1_px_l;
input arbpc2_pcxdp_grant_bufp1_pa_l;
input arbpc2_pcxdp_q0_hold_bufp1_pa;
input arbpc2_pcxdp_qsel0_bufp1_pa_l;
input arbpc2_pcxdp_qsel1_bufp1_pa;
input arbpc2_pcxdp_shift_bufp1_px_l;
input scache0_pcx_stall_pq;
assign arbpc0_pcxdp_grant_pa = ~arbpc0_pcxdp_grant_bufp1_pa_l;
assign arbpc0_pcxdp_q0_hold_pa_l = ~arbpc0_pcxdp_q0_hold_bufp1_pa;
assign arbpc0_pcxdp_qsel0_pa = ~arbpc0_pcxdp_qsel0_bufp1_pa_l;
assign arbpc0_pcxdp_qsel1_pa_l = ~arbpc0_pcxdp_qsel1_bufp1_pa;
assign arbpc0_pcxdp_shift_px = ~arbpc0_pcxdp_shift_bufp1_px_l;
assign arbpc2_pcxdp_grant_pa = ~arbpc2_pcxdp_grant_bufp1_pa_l;
assign arbpc2_pcxdp_q0_hold_pa_l = ~arbpc2_pcxdp_q0_hold_bufp1_pa;
assign arbpc2_pcxdp_qsel0_pa = ~arbpc2_pcxdp_qsel0_bufp1_pa_l;
assign arbpc2_pcxdp_qsel1_pa_l = ~arbpc2_pcxdp_qsel1_bufp1_pa;
assign arbpc2_pcxdp_shift_px = ~arbpc2_pcxdp_shift_bufp1_px_l;
assign scache0_pcx_stall_bufp0even_pq = scache0_pcx_stall_pq;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
`include "prog_counter2.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module tb_prog_counter2();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter2 pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#19
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright (c) 2015, Arch Labolatory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*L2 cache for Nexys4 DDR (4way 4word) */
`default_nettype none
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w);
parameter cache_entry = 14;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
wire [3:0] hit;
wire [3:0] modify;
wire [3:0] miss;
wire [3:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [7:0] r_cm_data;
wire [1:0] hit_num;
reg [2:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [3:0] write_set;
reg [3:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write0),
.word_en(word_en), // 4word r/w change
.readdata(readdata0),
.wb_addr(wb_addr0),
.hit(hit[0]),
.modify(modify[0]),
.miss(miss[0]),
.valid(valid[0]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write1),
.word_en(word_en), // 4word r/w change
.readdata(readdata1),
.wb_addr(wb_addr1),
.hit(hit[1]),
.modify(modify[1]),
.miss(miss[1]),
.valid(valid[1]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write2),
.word_en(word_en), // 4word r/w change
.readdata(readdata2),
.wb_addr(wb_addr2),
.hit(hit[2]),
.modify(modify[2]),
.miss(miss[2]),
.valid(valid[2]),
.read_miss(read_buf));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.write(write3),
.word_en(word_en), // 4word r/w change
.readdata(readdata3),
.wb_addr(wb_addr3),
.hit(hit[3]),
.modify(modify[3]),
.miss(miss[3]),
.valid(valid[3]),
.read_miss(read_buf));
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign addr = (o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 : (hit[1]) ? 1 : (hit[2]) ? 2 : 3;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if((|hit) && read_buf) begin
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= (hit[0]) ? readdata0[31:0] : (hit[1]) ? readdata1[31:0] : (hit[2]) ? readdata2[31:0] : readdata3[31:0];
2'b01: o_p_readdata <= (hit[0]) ? readdata0[63:32] : (hit[1]) ? readdata1[63:32] : (hit[2]) ? readdata2[63:32] : readdata3[63:32];
2'b10: o_p_readdata <= (hit[0]) ? readdata0[95:64] : (hit[1]) ? readdata1[95:64] : (hit[2]) ? readdata2[95:64] : readdata3[95:64];
2'b11: o_p_readdata <= (hit[0]) ? readdata0[127:96] : (hit[1]) ? readdata1[127:96] : (hit[2]) ? readdata2[127:96] : readdata3[127:96];
endcase
o_p_readdata_valid <= 1;
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
cnt_hit_r <= cnt_hit_r + 1;
state <= IDLE;
end else if(!(&valid) || miss[r_cm_data[1:0]]) begin
state <= FETCH1;
if(!valid[0]) begin
fetch_write <= 4'b0001;
w_cm_data <= 8'b11100100;
w_cm <= 1;
end else if(!valid[1]) begin
fetch_write <= 4'b0010;
w_cm_data <= (r_cm_data[1:0] == 2'b01) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b01) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b01) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(!valid[2]) begin
fetch_write <= 4'b0100;
w_cm_data <= (r_cm_data[1:0] == 2'b10) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b10) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b10) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(!valid[3]) begin
fetch_write <= 4'b1000;
w_cm_data <= (r_cm_data[1:0] == 2'b11) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == 2'b11) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == 2'b11) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
w_cm <= 1;
end else if(miss[r_cm_data[1:0]]) begin
if(r_cm_data[1:0] == 2'b00) fetch_write <= 4'b0001;
else if(r_cm_data[1:0] == 2'b01) fetch_write <= 4'b0010;
else if(r_cm_data[1:0] == 2'b10) fetch_write <= 4'b0100;
else if(r_cm_data[1:0] == 2'b11) fetch_write <= 4'b1000;
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
w_cm <= 1;
end
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
end else begin
state <= WB1;
if(r_cm_data[1:0] == 2'b00) fetch_write <= 4'b0001;
else if(r_cm_data[1:0] == 2'b01) fetch_write <= 4'b0010;
else if(r_cm_data[1:0] == 2'b10) fetch_write <= 4'b0100;
else if(r_cm_data[1:0] == 2'b11) fetch_write <= 4'b1000;
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
w_cm <= 1;
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end //1/13
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} : {wb_addr3, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 : readdata3;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
endcase // case (state)
end
end
endmodule // cache
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
modify,
miss,
valid,
read_miss);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire write;
input wire [3:0] word_en;
input wire read_miss;
output wire [127:0] readdata;
output wire [22:0] wb_addr;
output wire hit, modify, miss, valid;
wire [22-cache_entry:0] i_tag;
wire dirty;
wire [24-cache_entry:0] write_tag_data;
assign hit = valid && (o_tag == i_tag);
assign modify = valid && (o_tag != i_tag) && dirty;
assign miss = !valid || ((o_tag != i_tag) && !dirty);
assign wb_addr = {i_tag, entry};
//write -> [3:0] write, writedata/readdata 32bit -> 128bit
simple_ram #(.width(8), .widthad(cache_entry)) ram11_3(clk, entry, write && word_en[3] && byte_en[3], writedata[127:120], entry, readdata[127:120]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_2(clk, entry, write && word_en[3] && byte_en[2], writedata[119:112], entry, readdata[119:112]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_1(clk, entry, write && word_en[3] && byte_en[1], writedata[111:104], entry, readdata[111:104]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_0(clk, entry, write && word_en[3] && byte_en[0], writedata[103:96], entry, readdata[103:96]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_3(clk, entry, write && word_en[2] && byte_en[3], writedata[95:88], entry, readdata[95:88]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_2(clk, entry, write && word_en[2] && byte_en[2], writedata[87:80], entry, readdata[87:80]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_1(clk, entry, write && word_en[2] && byte_en[1], writedata[79:72], entry, readdata[79:72]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_0(clk, entry, write && word_en[2] && byte_en[0], writedata[71:64], entry, readdata[71:64]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_3(clk, entry, write && word_en[1] && byte_en[3], writedata[63:56], entry, readdata[63:56]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_2(clk, entry, write && word_en[1] && byte_en[2], writedata[55:48], entry, readdata[55:48]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_1(clk, entry, write && word_en[1] && byte_en[1], writedata[47:40], entry, readdata[47:40]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_0(clk, entry, write && word_en[1] && byte_en[0], writedata[39:32], entry, readdata[39:32]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_3(clk, entry, write && word_en[0] && byte_en[3], writedata[31:24], entry, readdata[31:24]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_2(clk, entry, write && word_en[0] && byte_en[2], writedata[23:16], entry, readdata[23:16]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_1(clk, entry, write && word_en[0] && byte_en[1], writedata[15: 8], entry, readdata[15:8]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_0(clk, entry, write && word_en[0] && byte_en[0], writedata[ 7: 0], entry, readdata[ 7:0]);
assign write_tag_data = (read_miss) ? {1'b0, 1'b1, o_tag} : (modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
simple_ram #(.width(25-cache_entry), .widthad(cache_entry)) ram_tag(clk, entry, write, write_tag_data, entry, {dirty, valid, i_tag});
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_tag.mem[i] = 0;
end
end
`endif
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: io_mux.v
//
// *Module Description:
// I/O mux for port function selection.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
module io_mux (
// Function A (typically GPIO)
a_din,
a_dout,
a_dout_en,
// Function B (Timer A, ...)
b_din,
b_dout,
b_dout_en,
// IO Cell
io_din,
io_dout,
io_dout_en,
// Function selection (0=A, 1=B)
sel
);
// PARAMETERs
//============
parameter WIDTH = 8;
// Function A (typically GPIO)
//===============================
output [WIDTH-1:0] a_din;
input [WIDTH-1:0] a_dout;
input [WIDTH-1:0] a_dout_en;
// Function B (Timer A, ...)
//===============================
output [WIDTH-1:0] b_din;
input [WIDTH-1:0] b_dout;
input [WIDTH-1:0] b_dout_en;
// IO Cell
//===============================
input [WIDTH-1:0] io_din;
output [WIDTH-1:0] io_dout;
output [WIDTH-1:0] io_dout_en;
// Function selection (0=A, 1=B)
//===============================
input [WIDTH-1:0] sel;
//=============================================================================
// 1) I/O FUNCTION SELECTION MUX
//=============================================================================
function [WIDTH-1:0] mux (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input [WIDTH-1:0] SEL
);
integer i;
begin
mux = {WIDTH{1'b0}};
for (i = 0; i < WIDTH; i = i + 1)
mux[i] = sel[i] ? B[i] : A[i];
end
endfunction
assign a_din = mux( io_din, {WIDTH{1'b0}}, sel);
assign b_din = mux({WIDTH{1'b0}}, io_din, sel);
assign io_dout = mux( a_dout, b_dout, sel);
assign io_dout_en = mux( a_dout_en, b_dout_en, sel);
endmodule // io_mux
|
/* Verilog netlist generated by SCUBA Diamond_1.4_Production (87) */
/* Module Version: 5.4 */
/* C:\lscc\diamond\1.4\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16 -width 9 -depth 16 -rdata_width 9 -no_enable -pe -1 -pf -1 -e */
/* Fri Jun 08 19:14:04 2012 */
`timescale 1 ns / 1 ps
module asfifo9_4 (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q,
Empty, Full);
input wire [8:0] Data;
input wire WrClock;
input wire RdClock;
input wire WrEn;
input wire RdEn;
input wire Reset;
input wire RPReset;
output wire [8:0] Q;
output wire Empty;
output wire Full;
wire invout_1;
wire invout_0;
wire w_gdata_0;
wire w_gdata_1;
wire w_gdata_2;
wire w_gdata_3;
wire wptr_0;
wire wptr_1;
wire wptr_2;
wire wptr_3;
wire wptr_4;
wire r_gdata_0;
wire r_gdata_1;
wire r_gdata_2;
wire r_gdata_3;
wire rptr_0;
wire rptr_1;
wire rptr_2;
wire rptr_3;
wire rptr_4;
wire w_gcount_0;
wire w_gcount_1;
wire w_gcount_2;
wire w_gcount_3;
wire w_gcount_4;
wire r_gcount_0;
wire r_gcount_1;
wire r_gcount_2;
wire r_gcount_3;
wire r_gcount_4;
wire w_gcount_r20;
wire w_gcount_r0;
wire w_gcount_r21;
wire w_gcount_r1;
wire w_gcount_r22;
wire w_gcount_r2;
wire w_gcount_r23;
wire w_gcount_r3;
wire w_gcount_r24;
wire w_gcount_r4;
wire r_gcount_w20;
wire r_gcount_w0;
wire r_gcount_w21;
wire r_gcount_w1;
wire r_gcount_w22;
wire r_gcount_w2;
wire r_gcount_w23;
wire r_gcount_w3;
wire r_gcount_w24;
wire r_gcount_w4;
wire empty_i;
wire rRst;
wire full_i;
wire iwcount_0;
wire iwcount_1;
wire w_gctr_ci;
wire iwcount_2;
wire iwcount_3;
wire co0;
wire iwcount_4;
wire co2;
wire wcount_4;
wire co1;
wire scuba_vhi;
wire ircount_0;
wire ircount_1;
wire r_gctr_ci;
wire ircount_2;
wire ircount_3;
wire co0_1;
wire ircount_4;
wire co2_1;
wire rcount_4;
wire co1_1;
wire rden_i;
wire cmp_ci;
wire wcount_r0;
wire w_g2b_xor_cluster_0;
wire rcount_0;
wire rcount_1;
wire co0_2;
wire wcount_r2;
wire wcount_r3;
wire rcount_2;
wire rcount_3;
wire co1_2;
wire empty_cmp_clr;
wire empty_cmp_set;
wire empty_d;
wire empty_d_c;
wire wren_i;
wire cmp_ci_1;
wire rcount_w0;
wire r_g2b_xor_cluster_0;
wire wcount_0;
wire wcount_1;
wire co0_3;
wire rcount_w2;
wire rcount_w3;
wire wcount_2;
wire wcount_3;
wire co1_3;
wire full_cmp_clr;
wire full_cmp_set;
wire full_d;
wire full_d_c;
wire scuba_vlo;
AND2 AND2_t10 (.A(WrEn), .B(invout_1), .Z(wren_i));
INV INV_1 (.A(full_i), .Z(invout_1));
AND2 AND2_t9 (.A(RdEn), .B(invout_0), .Z(rden_i));
INV INV_0 (.A(empty_i), .Z(invout_0));
OR2 OR2_t8 (.A(Reset), .B(RPReset), .Z(rRst));
XOR2 XOR2_t7 (.A(wcount_0), .B(wcount_1), .Z(w_gdata_0));
XOR2 XOR2_t6 (.A(wcount_1), .B(wcount_2), .Z(w_gdata_1));
XOR2 XOR2_t5 (.A(wcount_2), .B(wcount_3), .Z(w_gdata_2));
XOR2 XOR2_t4 (.A(wcount_3), .B(wcount_4), .Z(w_gdata_3));
XOR2 XOR2_t3 (.A(rcount_0), .B(rcount_1), .Z(r_gdata_0));
XOR2 XOR2_t2 (.A(rcount_1), .B(rcount_2), .Z(r_gdata_1));
XOR2 XOR2_t1 (.A(rcount_2), .B(rcount_3), .Z(r_gdata_2));
XOR2 XOR2_t0 (.A(rcount_3), .B(rcount_4), .Z(r_gdata_3));
defparam LUT4_11.initval = 16'h6996 ;
ROM16X1A LUT4_11 (.AD3(w_gcount_r21), .AD2(w_gcount_r22), .AD1(w_gcount_r23),
.AD0(w_gcount_r24), .DO0(w_g2b_xor_cluster_0));
defparam LUT4_10.initval = 16'h6996 ;
ROM16X1A LUT4_10 (.AD3(w_gcount_r23), .AD2(w_gcount_r24), .AD1(scuba_vlo),
.AD0(scuba_vlo), .DO0(wcount_r3));
defparam LUT4_9.initval = 16'h6996 ;
ROM16X1A LUT4_9 (.AD3(w_gcount_r22), .AD2(w_gcount_r23), .AD1(w_gcount_r24),
.AD0(scuba_vlo), .DO0(wcount_r2));
defparam LUT4_8.initval = 16'h6996 ;
ROM16X1A LUT4_8 (.AD3(w_gcount_r20), .AD2(w_gcount_r21), .AD1(w_gcount_r22),
.AD0(wcount_r3), .DO0(wcount_r0));
defparam LUT4_7.initval = 16'h6996 ;
ROM16X1A LUT4_7 (.AD3(r_gcount_w21), .AD2(r_gcount_w22), .AD1(r_gcount_w23),
.AD0(r_gcount_w24), .DO0(r_g2b_xor_cluster_0));
defparam LUT4_6.initval = 16'h6996 ;
ROM16X1A LUT4_6 (.AD3(r_gcount_w23), .AD2(r_gcount_w24), .AD1(scuba_vlo),
.AD0(scuba_vlo), .DO0(rcount_w3));
defparam LUT4_5.initval = 16'h6996 ;
ROM16X1A LUT4_5 (.AD3(r_gcount_w22), .AD2(r_gcount_w23), .AD1(r_gcount_w24),
.AD0(scuba_vlo), .DO0(rcount_w2));
defparam LUT4_4.initval = 16'h6996 ;
ROM16X1A LUT4_4 (.AD3(r_gcount_w20), .AD2(r_gcount_w21), .AD1(r_gcount_w22),
.AD0(rcount_w3), .DO0(rcount_w0));
defparam LUT4_3.initval = 16'h0410 ;
ROM16X1A LUT4_3 (.AD3(rptr_4), .AD2(rcount_4), .AD1(w_gcount_r24), .AD0(scuba_vlo),
.DO0(empty_cmp_set));
defparam LUT4_2.initval = 16'h1004 ;
ROM16X1A LUT4_2 (.AD3(rptr_4), .AD2(rcount_4), .AD1(w_gcount_r24), .AD0(scuba_vlo),
.DO0(empty_cmp_clr));
defparam LUT4_1.initval = 16'h0140 ;
ROM16X1A LUT4_1 (.AD3(wptr_4), .AD2(wcount_4), .AD1(r_gcount_w24), .AD0(scuba_vlo),
.DO0(full_cmp_set));
defparam LUT4_0.initval = 16'h4001 ;
ROM16X1A LUT4_0 (.AD3(wptr_4), .AD2(wcount_4), .AD1(r_gcount_w24), .AD0(scuba_vlo),
.DO0(full_cmp_clr));
defparam pdp_ram_0_0_0.CSDECODE_B = "0b000" ;
defparam pdp_ram_0_0_0.CSDECODE_A = "0b000" ;
defparam pdp_ram_0_0_0.WRITEMODE_B = "NORMAL" ;
defparam pdp_ram_0_0_0.WRITEMODE_A = "NORMAL" ;
defparam pdp_ram_0_0_0.GSR = "DISABLED" ;
defparam pdp_ram_0_0_0.REGMODE_B = "NOREG" ;
defparam pdp_ram_0_0_0.REGMODE_A = "NOREG" ;
defparam pdp_ram_0_0_0.DATA_WIDTH_B = 9 ;
defparam pdp_ram_0_0_0.DATA_WIDTH_A = 9 ;
DP16KC pdp_ram_0_0_0 (.DIA0(Data[0]), .DIA1(Data[1]), .DIA2(Data[2]),
.DIA3(Data[3]), .DIA4(Data[4]), .DIA5(Data[5]), .DIA6(Data[6]),
.DIA7(Data[7]), .DIA8(Data[8]), .DIA9(scuba_vlo), .DIA10(scuba_vlo),
.DIA11(scuba_vlo), .DIA12(scuba_vlo), .DIA13(scuba_vlo), .DIA14(scuba_vlo),
.DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), .ADA0(scuba_vlo),
.ADA1(scuba_vlo), .ADA2(scuba_vlo), .ADA3(wptr_0), .ADA4(wptr_1),
.ADA5(wptr_2), .ADA6(wptr_3), .ADA7(scuba_vlo), .ADA8(scuba_vlo),
.ADA9(scuba_vlo), .ADA10(scuba_vlo), .ADA11(scuba_vlo), .ADA12(scuba_vlo),
.ADA13(scuba_vlo), .CEA(wren_i), .CLKA(WrClock), .OCEA(wren_i),
.WEA(scuba_vhi), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
.RSTA(Reset), .DIB0(scuba_vlo), .DIB1(scuba_vlo), .DIB2(scuba_vlo),
.DIB3(scuba_vlo), .DIB4(scuba_vlo), .DIB5(scuba_vlo), .DIB6(scuba_vlo),
.DIB7(scuba_vlo), .DIB8(scuba_vlo), .DIB9(scuba_vlo), .DIB10(scuba_vlo),
.DIB11(scuba_vlo), .DIB12(scuba_vlo), .DIB13(scuba_vlo), .DIB14(scuba_vlo),
.DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vlo),
.ADB1(scuba_vlo), .ADB2(scuba_vlo), .ADB3(rptr_0), .ADB4(rptr_1),
.ADB5(rptr_2), .ADB6(rptr_3), .ADB7(scuba_vlo), .ADB8(scuba_vlo),
.ADB9(scuba_vlo), .ADB10(scuba_vlo), .ADB11(scuba_vlo), .ADB12(scuba_vlo),
.ADB13(scuba_vlo), .CEB(rden_i), .CLKB(RdClock), .OCEB(rden_i),
.WEB(scuba_vlo), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo),
.RSTB(Reset), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(),
.DOA6(), .DOA7(), .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(),
.DOA13(), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(Q[0]), .DOB1(Q[1]),
.DOB2(Q[2]), .DOB3(Q[3]), .DOB4(Q[4]), .DOB5(Q[5]), .DOB6(Q[6]),
.DOB7(Q[7]), .DOB8(Q[8]), .DOB9(), .DOB10(), .DOB11(), .DOB12(),
.DOB13(), .DOB14(), .DOB15(), .DOB16(), .DOB17())
/* synthesis MEM_LPC_FILE="asfifo9_4.lpc" */
/* synthesis MEM_INIT_FILE="" */
/* synthesis RESETMODE="SYNC" */;
FD1P3BX FF_51 (.D(iwcount_0), .SP(wren_i), .CK(WrClock), .PD(Reset),
.Q(wcount_0))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_50 (.D(iwcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wcount_1))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_49 (.D(iwcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wcount_2))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_48 (.D(iwcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wcount_3))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_47 (.D(iwcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wcount_4))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_46 (.D(w_gdata_0), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(w_gcount_0))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_45 (.D(w_gdata_1), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(w_gcount_1))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_44 (.D(w_gdata_2), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(w_gcount_2))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_43 (.D(w_gdata_3), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(w_gcount_3))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_42 (.D(wcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(w_gcount_4))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_41 (.D(wcount_0), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wptr_0))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_40 (.D(wcount_1), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wptr_1))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_39 (.D(wcount_2), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wptr_2))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_38 (.D(wcount_3), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wptr_3))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_37 (.D(wcount_4), .SP(wren_i), .CK(WrClock), .CD(Reset),
.Q(wptr_4))
/* synthesis GSR="ENABLED" */;
FD1P3BX FF_36 (.D(ircount_0), .SP(rden_i), .CK(RdClock), .PD(rRst),
.Q(rcount_0))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_35 (.D(ircount_1), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(rcount_1))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_34 (.D(ircount_2), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(rcount_2))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_33 (.D(ircount_3), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(rcount_3))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_32 (.D(ircount_4), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(rcount_4))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_31 (.D(r_gdata_0), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(r_gcount_0))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_30 (.D(r_gdata_1), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(r_gcount_1))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_29 (.D(r_gdata_2), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(r_gcount_2))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_28 (.D(r_gdata_3), .SP(rden_i), .CK(RdClock), .CD(rRst),
.Q(r_gcount_3))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_27 (.D(rcount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(r_gcount_4))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_26 (.D(rcount_0), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_0))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_25 (.D(rcount_1), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_1))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_24 (.D(rcount_2), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_2))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_23 (.D(rcount_3), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_3))
/* synthesis GSR="ENABLED" */;
FD1P3DX FF_22 (.D(rcount_4), .SP(rden_i), .CK(RdClock), .CD(rRst), .Q(rptr_4))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_21 (.D(w_gcount_0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r0))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_20 (.D(w_gcount_1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r1))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_19 (.D(w_gcount_2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r2))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_18 (.D(w_gcount_3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r3))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_17 (.D(w_gcount_4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r4))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_16 (.D(r_gcount_0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w0))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_15 (.D(r_gcount_1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w1))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_14 (.D(r_gcount_2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w2))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_13 (.D(r_gcount_3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w3))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_12 (.D(r_gcount_4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w4))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_11 (.D(w_gcount_r0), .CK(RdClock), .CD(Reset), .Q(w_gcount_r20))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_10 (.D(w_gcount_r1), .CK(RdClock), .CD(Reset), .Q(w_gcount_r21))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_9 (.D(w_gcount_r2), .CK(RdClock), .CD(Reset), .Q(w_gcount_r22))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_8 (.D(w_gcount_r3), .CK(RdClock), .CD(Reset), .Q(w_gcount_r23))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_7 (.D(w_gcount_r4), .CK(RdClock), .CD(Reset), .Q(w_gcount_r24))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_6 (.D(r_gcount_w0), .CK(WrClock), .CD(rRst), .Q(r_gcount_w20))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_5 (.D(r_gcount_w1), .CK(WrClock), .CD(rRst), .Q(r_gcount_w21))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_4 (.D(r_gcount_w2), .CK(WrClock), .CD(rRst), .Q(r_gcount_w22))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_3 (.D(r_gcount_w3), .CK(WrClock), .CD(rRst), .Q(r_gcount_w23))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_2 (.D(r_gcount_w4), .CK(WrClock), .CD(rRst), .Q(r_gcount_w24))
/* synthesis GSR="ENABLED" */;
FD1S3BX FF_1 (.D(empty_d), .CK(RdClock), .PD(rRst), .Q(empty_i))
/* synthesis GSR="ENABLED" */;
FD1S3DX FF_0 (.D(full_d), .CK(WrClock), .CD(Reset), .Q(full_i))
/* synthesis GSR="ENABLED" */;
FADD2B w_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi),
.CI(scuba_vlo), .COUT(w_gctr_ci), .S0(), .S1());
CU2 w_gctr_0 (.CI(w_gctr_ci), .PC0(wcount_0), .PC1(wcount_1), .CO(co0),
.NC0(iwcount_0), .NC1(iwcount_1));
CU2 w_gctr_1 (.CI(co0), .PC0(wcount_2), .PC1(wcount_3), .CO(co1), .NC0(iwcount_2),
.NC1(iwcount_3));
CU2 w_gctr_2 (.CI(co1), .PC0(wcount_4), .PC1(scuba_vlo), .CO(co2), .NC0(iwcount_4),
.NC1());
VHI scuba_vhi_inst (.Z(scuba_vhi));
FADD2B r_gctr_cia (.A0(scuba_vlo), .A1(scuba_vhi), .B0(scuba_vlo), .B1(scuba_vhi),
.CI(scuba_vlo), .COUT(r_gctr_ci), .S0(), .S1());
CU2 r_gctr_0 (.CI(r_gctr_ci), .PC0(rcount_0), .PC1(rcount_1), .CO(co0_1),
.NC0(ircount_0), .NC1(ircount_1));
CU2 r_gctr_1 (.CI(co0_1), .PC0(rcount_2), .PC1(rcount_3), .CO(co1_1),
.NC0(ircount_2), .NC1(ircount_3));
CU2 r_gctr_2 (.CI(co1_1), .PC0(rcount_4), .PC1(scuba_vlo), .CO(co2_1),
.NC0(ircount_4), .NC1());
FADD2B empty_cmp_ci_a (.A0(scuba_vlo), .A1(rden_i), .B0(scuba_vlo),
.B1(rden_i), .CI(scuba_vlo), .COUT(cmp_ci), .S0(), .S1());
AGEB2 empty_cmp_0 (.A0(rcount_0), .A1(rcount_1), .B0(wcount_r0), .B1(w_g2b_xor_cluster_0),
.CI(cmp_ci), .GE(co0_2));
AGEB2 empty_cmp_1 (.A0(rcount_2), .A1(rcount_3), .B0(wcount_r2), .B1(wcount_r3),
.CI(co0_2), .GE(co1_2));
AGEB2 empty_cmp_2 (.A0(empty_cmp_set), .A1(scuba_vlo), .B0(empty_cmp_clr),
.B1(scuba_vlo), .CI(co1_2), .GE(empty_d_c));
FADD2B a0 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo),
.CI(empty_d_c), .COUT(), .S0(empty_d), .S1());
FADD2B full_cmp_ci_a (.A0(scuba_vlo), .A1(wren_i), .B0(scuba_vlo), .B1(wren_i),
.CI(scuba_vlo), .COUT(cmp_ci_1), .S0(), .S1());
AGEB2 full_cmp_0 (.A0(wcount_0), .A1(wcount_1), .B0(rcount_w0), .B1(r_g2b_xor_cluster_0),
.CI(cmp_ci_1), .GE(co0_3));
AGEB2 full_cmp_1 (.A0(wcount_2), .A1(wcount_3), .B0(rcount_w2), .B1(rcount_w3),
.CI(co0_3), .GE(co1_3));
AGEB2 full_cmp_2 (.A0(full_cmp_set), .A1(scuba_vlo), .B0(full_cmp_clr),
.B1(scuba_vlo), .CI(co1_3), .GE(full_d_c));
VLO scuba_vlo_inst (.Z(scuba_vlo));
FADD2B a1 (.A0(scuba_vlo), .A1(scuba_vlo), .B0(scuba_vlo), .B1(scuba_vlo),
.CI(full_d_c), .COUT(), .S0(full_d), .S1());
assign Empty = empty_i;
assign Full = full_i;
// exemplar begin
// exemplar attribute pdp_ram_0_0_0 MEM_LPC_FILE asfifo9_4.lpc
// exemplar attribute pdp_ram_0_0_0 MEM_INIT_FILE
// exemplar attribute pdp_ram_0_0_0 RESETMODE SYNC
// exemplar attribute FF_51 GSR ENABLED
// exemplar attribute FF_50 GSR ENABLED
// exemplar attribute FF_49 GSR ENABLED
// exemplar attribute FF_48 GSR ENABLED
// exemplar attribute FF_47 GSR ENABLED
// exemplar attribute FF_46 GSR ENABLED
// exemplar attribute FF_45 GSR ENABLED
// exemplar attribute FF_44 GSR ENABLED
// exemplar attribute FF_43 GSR ENABLED
// exemplar attribute FF_42 GSR ENABLED
// exemplar attribute FF_41 GSR ENABLED
// exemplar attribute FF_40 GSR ENABLED
// exemplar attribute FF_39 GSR ENABLED
// exemplar attribute FF_38 GSR ENABLED
// exemplar attribute FF_37 GSR ENABLED
// exemplar attribute FF_36 GSR ENABLED
// exemplar attribute FF_35 GSR ENABLED
// exemplar attribute FF_34 GSR ENABLED
// exemplar attribute FF_33 GSR ENABLED
// exemplar attribute FF_32 GSR ENABLED
// exemplar attribute FF_31 GSR ENABLED
// exemplar attribute FF_30 GSR ENABLED
// exemplar attribute FF_29 GSR ENABLED
// exemplar attribute FF_28 GSR ENABLED
// exemplar attribute FF_27 GSR ENABLED
// exemplar attribute FF_26 GSR ENABLED
// exemplar attribute FF_25 GSR ENABLED
// exemplar attribute FF_24 GSR ENABLED
// exemplar attribute FF_23 GSR ENABLED
// exemplar attribute FF_22 GSR ENABLED
// exemplar attribute FF_21 GSR ENABLED
// exemplar attribute FF_20 GSR ENABLED
// exemplar attribute FF_19 GSR ENABLED
// exemplar attribute FF_18 GSR ENABLED
// exemplar attribute FF_17 GSR ENABLED
// exemplar attribute FF_16 GSR ENABLED
// exemplar attribute FF_15 GSR ENABLED
// exemplar attribute FF_14 GSR ENABLED
// exemplar attribute FF_13 GSR ENABLED
// exemplar attribute FF_12 GSR ENABLED
// exemplar attribute FF_11 GSR ENABLED
// exemplar attribute FF_10 GSR ENABLED
// exemplar attribute FF_9 GSR ENABLED
// exemplar attribute FF_8 GSR ENABLED
// exemplar attribute FF_7 GSR ENABLED
// exemplar attribute FF_6 GSR ENABLED
// exemplar attribute FF_5 GSR ENABLED
// exemplar attribute FF_4 GSR ENABLED
// exemplar attribute FF_3 GSR ENABLED
// exemplar attribute FF_2 GSR ENABLED
// exemplar attribute FF_1 GSR ENABLED
// exemplar attribute FF_0 GSR ENABLED
// exemplar end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_aluaddsub.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_aluaddsub
// Description: This block implements addition and subtraction.
// It takes two operands, a carry_in, plus two control signals
// (subtract and use_cin). If subtract is high, then rs2_data
// is subtracted from rs1_data. If use_cin is high, then
// carry_in is added to the sum (addition) or subtracted from
// the result (subtraction). It outputs the result of the
// specified operation. To keep the cin calculation from
// being in the critical path, it is moved into the d-stage.
// All other calculations are in the e-stage.
*/
module sparc_exu_aluaddsub
(/*AUTOARG*/
// Outputs
adder_out, spr_out, alu_ecl_cout64_e_l, alu_ecl_cout32_e,
alu_ecl_adderin2_63_e, alu_ecl_adderin2_31_e,
// Inputs
clk, se, byp_alu_rs1_data_e, byp_alu_rs2_data_e, ecl_alu_cin_e,
ifu_exu_invert_d
);
input clk;
input se;
input [63:0] byp_alu_rs1_data_e; // 1st input operand
input [63:0] byp_alu_rs2_data_e; // 2nd input operand
input ecl_alu_cin_e; // carry in
input ifu_exu_invert_d; // subtract used by adder
output [63:0] adder_out; // result of adder
output [63:0] spr_out; // result of sum predict
output alu_ecl_cout64_e_l;
output alu_ecl_cout32_e;
output alu_ecl_adderin2_63_e;
output alu_ecl_adderin2_31_e;
wire [63:0] rs2_data; // 2nd input to adder
wire [63:0] rs1_data; // 1st input to adder
wire [63:0] subtract_d;
wire [63:0] subtract_e;
wire cout64_e;
////////////////////////////////////////////
// Module implementation
////////////////////////////////////////////
assign subtract_d[63:0] = {64{ifu_exu_invert_d}};
dff_s #(64) sub_dff(.din(subtract_d[63:0]), .clk(clk), .q(subtract_e[63:0]), .se(se),
.si(), .so());
assign rs1_data[63:0] = byp_alu_rs1_data_e[63:0];
assign rs2_data[63:0] = byp_alu_rs2_data_e[63:0] ^ subtract_e[63:0];
assign alu_ecl_adderin2_63_e = rs2_data[63];
assign alu_ecl_adderin2_31_e = rs2_data[31];
sparc_exu_aluadder64 adder(.rs1_data(rs1_data[63:0]), .rs2_data(rs2_data[63:0]),
.cin(ecl_alu_cin_e), .adder_out(adder_out[63:0]),
.cout32(alu_ecl_cout32_e), .cout64(cout64_e));
assign alu_ecl_cout64_e_l = ~cout64_e;
// sum predict
sparc_exu_aluspr spr(.rs1_data(rs1_data[63:0]), .rs2_data(rs2_data[63:0]), .cin(ecl_alu_cin_e),
.spr_out(spr_out[63:0]));
endmodule // sparc_exu_aluaddsub
|
(** * Extraction: Extracting ML from Coq *)
(* $Date: 2013-01-16 22:29:57 -0500 (Wed, 16 Jan 2013) $ *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign ledu = 0;
assign ledl = 0;
assign ledd = 0;
assign ledr = 0;
assign ledc = 0;
assign led = led_reg;
assign phy_reset_n = !rst_125mhz;
assign uart_rxd = 0;
assign uart_cts = 0;
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk_125mhz),
.gtx_rst(rst_125mhz),
.logic_clk(clk_125mhz),
.logic_rst(rst_125mhz),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/* this file automatically generated by make_wp.py script
* for file l2tlb.v
* for module l2tlb
* with the instance name top
*/
// This module is instantiated inside the l2cache
//
// The l1TLB has to track at least 4 SPBTRs at once, but no need to have
// unlimited. This means that just 4 flops translating SBPTR to valid indexes
// are enough. If a new SBPTR checkpoint create arrives, the TLB can
// invalidate all the associated TLB entries (and notify the L1 accordingly)
//
`include "scmem.vh"
`define L2TLB_PASSTHROUGH
module l2tlb_wp(
/* verilator lint_off UNUSED */
input logic clk
,input logic reset
// L2TLB listens the same L1 request (but no ack). Response sent to L2
,input logic l1tol2tlb_req_valid
,output logic l1tol2tlb_req_retry
,input L1_reqid_type l1tol2tlb_req_l1id // 5 bits
,input logic l1tol2tlb_req_prefetch
,input TLB_hpaddr_type l1tol2tlb_req_hpaddr // 11 bits
,output logic l2tlbtol2_fwd_valid
,input logic l2tlbtol2_fwd_retry
,output L1_reqid_type l2tlbtol2_fwd_l1id // 5 bits
,output logic l2tlbtol2_fwd_prefetch
,output SC_fault_type l2tlbtol2_fwd_fault // 3 bits
,output TLB_hpaddr_type l2tlbtol2_fwd_hpaddr // 11 bits
,output SC_paddr_type l2tlbtol2_fwd_paddr // 50 bits
// l1TLB and L2TLB interface
,output logic l2tlbtol1tlb_snoop_valid
,input logic l2tlbtol1tlb_snoop_retry
,output TLB_reqid_type l2tlbtol1tlb_snoop_rid // 2 bits
,output TLB_hpaddr_type l2tlbtol1tlb_snoop_hpaddr // 11 bits
,output logic l2tlbtol1tlb_ack_valid
,input logic l2tlbtol1tlb_ack_retry
,output TLB_reqid_type l2tlbtol1tlb_ack_rid // 2 bits
,output TLB_hpaddr_type l2tlbtol1tlb_ack_hpaddr // 11 bits
,output SC_ppaddr_type l2tlbtol1tlb_ack_ppaddr // 3 bits
,output SC_dctlbe_type l2tlbtol1tlb_ack_dctlbe // 13 bits
,input logic l1tlbtol2tlb_req_valid
,output logic l1tlbtol2tlb_req_retry
,input TLB_reqid_type l1tlbtol2tlb_req_rid // 2 bits
,input logic l1tlbtol2tlb_req_disp_req
,input logic l1tlbtol2tlb_req_disp_A
,input logic l1tlbtol2tlb_req_disp_D
,input TLB_hpaddr_type l1tlbtol2tlb_req_disp_hpaddr // 11 bits
,input SC_laddr_type l1tlbtol2tlb_req_laddr // 39 bits
,input SC_sptbr_type l1tlbtol2tlb_req_sptbr // 38 bits
,input logic l1tlbtol2tlb_sack_valid
,output logic l1tlbtol2tlb_sack_retry
,input TLB_reqid_type l1tlbtol2tlb_sack_rid // 2 bits
//---------------------------
// Directory interface (l2 has to arbitrate between L2 and L2TLB
// messages based on nodeid. Even nodeid is L2, odd is L2TLB)
,output logic l2todr_req_valid
,input logic l2todr_req_retry
,output SC_nodeid_type l2todr_req_nid // 5 bits
,output L2_reqid_type l2todr_req_l2id // 6 bits
,output SC_cmd_type l2todr_req_cmd // 3 bits
,output SC_paddr_type l2todr_req_paddr // 50 bits
,input logic drtol2_snack_valid
,output logic drtol2_snack_retry
,input SC_nodeid_type drtol2_snack_nid // 5 bits
,input L2_reqid_type drtol2_snack_l2id // 6 bits
,input DR_reqid_type drtol2_snack_drid // 6 bits
,input DR_ndirs_type drtol2_snack_directory_id // 2 bits
,input SC_snack_type drtol2_snack_snack // 5 bits
,input SC_line_type drtol2_snack_line // 512 bits
,input DR_hpaddr_base_type drtol2_snack_hpaddr_base // 17 bits
,input DR_hpaddr_hash_type drtol2_snack_hpaddr_hash // 8 bits
,input SC_paddr_type drtol2_snack_paddr // 50 bits
,output logic l2todr_snoop_ack_valid
,input logic l2todr_snoop_ack_retry
,output L2_reqid_type l2todr_snoop_ack_l2id // 6 bits
,output DR_ndirs_type l2todr_snoop_ack_directory_id // 2 bits
,output logic l2todr_disp_valid
,input logic l2todr_disp_retry
,output SC_nodeid_type l2todr_disp_nid // 5 bits
,output L2_reqid_type l2todr_disp_l2id // 6 bits
,output DR_reqid_type l2todr_disp_drid // 6 bits
,output SC_disp_mask_type l2todr_disp_mask // 64 bits
,output SC_dcmd_type l2todr_disp_dcmd // 3 bits
,output SC_line_type l2todr_disp_line // 512 bits
,output SC_paddr_type l2todr_disp_paddr // 50 bits
,input logic drtol2_dack_valid
,output logic drtol2_dack_retry
,input SC_nodeid_type drtol2_dack_nid // 5 bits
,input L2_reqid_type drtol2_dack_l2id // 6 bits
/* verilator lint_on UNUSED */
);
I_l1tol2tlb_req_type l1tol2tlb_req;
assign l1tol2tlb_req.l1id = l1tol2tlb_req_l1id;
assign l1tol2tlb_req.prefetch = l1tol2tlb_req_prefetch;
assign l1tol2tlb_req.hpaddr = l1tol2tlb_req_hpaddr;
I_l2tlbtol2_fwd_type l2tlbtol2_fwd;
assign l2tlbtol2_fwd_l1id = l2tlbtol2_fwd.l1id;
assign l2tlbtol2_fwd_prefetch = l2tlbtol2_fwd.prefetch;
assign l2tlbtol2_fwd_fault = l2tlbtol2_fwd.fault;
assign l2tlbtol2_fwd_hpaddr = l2tlbtol2_fwd.hpaddr;
assign l2tlbtol2_fwd_paddr = l2tlbtol2_fwd.paddr;
I_l2tlbtol1tlb_snoop_type l2tlbtol1tlb_snoop;
assign l2tlbtol1tlb_snoop_rid = l2tlbtol1tlb_snoop.rid;
assign l2tlbtol1tlb_snoop_hpaddr = l2tlbtol1tlb_snoop.hpaddr;
I_l2tlbtol1tlb_ack_type l2tlbtol1tlb_ack;
assign l2tlbtol1tlb_ack_rid = l2tlbtol1tlb_ack.rid;
assign l2tlbtol1tlb_ack_hpaddr = l2tlbtol1tlb_ack.hpaddr;
assign l2tlbtol1tlb_ack_ppaddr = l2tlbtol1tlb_ack.ppaddr;
assign l2tlbtol1tlb_ack_dctlbe = l2tlbtol1tlb_ack.dctlbe;
I_l1tlbtol2tlb_req_type l1tlbtol2tlb_req;
assign l1tlbtol2tlb_req.rid = l1tlbtol2tlb_req_rid;
assign l1tlbtol2tlb_req.disp_req = l1tlbtol2tlb_req_disp_req;
assign l1tlbtol2tlb_req.disp_A = l1tlbtol2tlb_req_disp_A;
assign l1tlbtol2tlb_req.disp_D = l1tlbtol2tlb_req_disp_D;
assign l1tlbtol2tlb_req.disp_hpaddr = l1tlbtol2tlb_req_disp_hpaddr;
assign l1tlbtol2tlb_req.laddr = l1tlbtol2tlb_req_laddr;
assign l1tlbtol2tlb_req.sptbr = l1tlbtol2tlb_req_sptbr;
I_l1tlbtol2tlb_sack_type l1tlbtol2tlb_sack;
assign l1tlbtol2tlb_sack.rid = l1tlbtol2tlb_sack_rid;
I_l2todr_req_type l2todr_req;
assign l2todr_req_nid = l2todr_req.nid;
assign l2todr_req_l2id = l2todr_req.l2id;
assign l2todr_req_cmd = l2todr_req.cmd;
assign l2todr_req_paddr = l2todr_req.paddr;
I_drtol2_snack_type drtol2_snack;
assign drtol2_snack.nid = drtol2_snack_nid;
assign drtol2_snack.l2id = drtol2_snack_l2id;
assign drtol2_snack.drid = drtol2_snack_drid;
assign drtol2_snack.directory_id = drtol2_snack_directory_id;
assign drtol2_snack.snack = drtol2_snack_snack;
assign drtol2_snack.line = drtol2_snack_line;
assign drtol2_snack.hpaddr_base = drtol2_snack_hpaddr_base;
assign drtol2_snack.hpaddr_hash = drtol2_snack_hpaddr_hash;
assign drtol2_snack.paddr = drtol2_snack_paddr;
I_l2snoop_ack_type l2todr_snoop_ack;
assign l2todr_snoop_ack_l2id = l2todr_snoop_ack.l2id;
assign l2todr_snoop_ack_directory_id = l2todr_snoop_ack.directory_id;
I_l2todr_disp_type l2todr_disp;
assign l2todr_disp_nid = l2todr_disp.nid;
assign l2todr_disp_l2id = l2todr_disp.l2id;
assign l2todr_disp_drid = l2todr_disp.drid;
assign l2todr_disp_mask = l2todr_disp.mask;
assign l2todr_disp_dcmd = l2todr_disp.dcmd;
assign l2todr_disp_line = l2todr_disp.line;
assign l2todr_disp_paddr = l2todr_disp.paddr;
I_drtol2_dack_type drtol2_dack;
assign drtol2_dack.nid = drtol2_dack_nid;
assign drtol2_dack.l2id = drtol2_dack_l2id;
l2tlb top(.*);
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY TX
*/
module eth_phy_10g_tx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* Status
*/
output wire tx_bad_block,
/*
* Configuration
*/
input wire tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
xgmii_baser_enc_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_enc_inst (
.clk(clk),
.rst(rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.tx_bad_block(tx_bad_block)
);
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_V |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Finite set library *)
(** Set interfaces, inspired by the one of Ocaml. When compared with
Ocaml, the main differences are:
- the lack of [iter] function, useless since Coq is purely functional
- the use of [option] types instead of [Not_found] exceptions
- the use of [nat] instead of [int] for the [cardinal] function
Several variants of the set interfaces are available:
- [WSetsOn] : functorial signature for weak sets
- [WSets] : self-contained version of [WSets]
- [SetsOn] : functorial signature for ordered sets
- [Sets] : self-contained version of [Sets]
- [WRawSets] : a signature for weak sets that may be ill-formed
- [RawSets] : same for ordered sets
If unsure, [S = Sets] is probably what you're looking for: most other
signatures are subsets of it, while [Sets] can be obtained from
[RawSets] via the use of a subset type (see (W)Raw2Sets below).
*)
Require Export Bool SetoidList RelationClasses Morphisms
RelationPairs Equalities Orders OrdersFacts.
Set Implicit Arguments.
Unset Strict Implicit.
Module Type TypElt.
Parameters t elt : Type.
End TypElt.
Module Type HasWOps (Import T:TypElt).
Parameter empty : t.
(** The empty set. *)
Parameter is_empty : t -> bool.
(** Test whether a set is empty or not. *)
Parameter mem : elt -> t -> bool.
(** [mem x s] tests whether [x] belongs to the set [s]. *)
Parameter add : elt -> t -> t.
(** [add x s] returns a set containing all elements of [s],
plus [x]. If [x] was already in [s], [s] is returned unchanged. *)
Parameter singleton : elt -> t.
(** [singleton x] returns the one-element set containing only [x]. *)
Parameter remove : elt -> t -> t.
(** [remove x s] returns a set containing all elements of [s],
except [x]. If [x] was not in [s], [s] is returned unchanged. *)
Parameter union : t -> t -> t.
(** Set union. *)
Parameter inter : t -> t -> t.
(** Set intersection. *)
Parameter diff : t -> t -> t.
(** Set difference. *)
Parameter equal : t -> t -> bool.
(** [equal s1 s2] tests whether the sets [s1] and [s2] are
equal, that is, contain equal elements. *)
Parameter subset : t -> t -> bool.
(** [subset s1 s2] tests whether the set [s1] is a subset of
the set [s2]. *)
Parameter fold : forall A : Type, (elt -> A -> A) -> t -> A -> A.
(** [fold f s a] computes [(f xN ... (f x2 (f x1 a))...)],
where [x1 ... xN] are the elements of [s].
The order in which elements of [s] are presented to [f] is
unspecified. *)
Parameter for_all : (elt -> bool) -> t -> bool.
(** [for_all p s] checks if all elements of the set
satisfy the predicate [p]. *)
Parameter exists_ : (elt -> bool) -> t -> bool.
(** [exists p s] checks if at least one element of
the set satisfies the predicate [p]. *)
Parameter filter : (elt -> bool) -> t -> t.
(** [filter p s] returns the set of all elements in [s]
that satisfy predicate [p]. *)
Parameter partition : (elt -> bool) -> t -> t * t.
(** [partition p s] returns a pair of sets [(s1, s2)], where
[s1] is the set of all the elements of [s] that satisfy the
predicate [p], and [s2] is the set of all the elements of
[s] that do not satisfy [p]. *)
Parameter cardinal : t -> nat.
(** Return the number of elements of a set. *)
Parameter elements : t -> list elt.
(** Return the list of all elements of the given set, in any order. *)
Parameter choose : t -> option elt.
(** Return one element of the given set, or [None] if
the set is empty. Which element is chosen is unspecified.
Equal sets could return different elements. *)
End HasWOps.
Module Type WOps (E : DecidableType).
Definition elt := E.t.
Parameter t : Type. (** the abstract type of sets *)
Include HasWOps.
End WOps.
(** ** Functorial signature for weak sets
Weak sets are sets without ordering on base elements, only
a decidable equality. *)
Module Type WSetsOn (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Include IsEq. (** [eq] is obviously an equivalence, for subtyping only *)
Include HasEqDec.
(** Specifications of set operators *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : mem x s = true <-> In x s.
Parameter equal_spec : equal s s' = true <-> s[=]s'.
Parameter subset_spec : subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
(** When compared with ordered sets, here comes the only
property that is really weaker: *)
Parameter elements_spec2w : NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WSetsOn.
(** ** Static signature for weak sets
Similar to the functorial signature [WSetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type WSets.
Declare Module E : DecidableType.
Include WSetsOn E.
End WSets.
(** ** Functorial signature for sets on ordered elements
Based on [WSetsOn], plus ordering on sets and [min_elt] and [max_elt]
and some stronger specifications for other functions. *)
Module Type HasOrdOps (Import T:TypElt).
Parameter compare : t -> t -> comparison.
(** Total ordering between sets. Can be used as the ordering function
for doing sets of sets. *)
Parameter min_elt : t -> option elt.
(** Return the smallest element of the given set
(with respect to the [E.compare] ordering),
or [None] if the set is empty. *)
Parameter max_elt : t -> option elt.
(** Same as [min_elt], but returns the largest element of the
given set. *)
End HasOrdOps.
Module Type Ops (E : OrderedType) := WOps E <+ HasOrdOps.
Module Type SetsOn (E : OrderedType).
Include WSetsOn E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
Parameter compare_spec : CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : sort E.lt (elements s).
(** Remark: since [fold] is specified via [elements], this stronger
specification of [elements] has an indirect impact on [fold],
which can now be proved to receive elements in increasing order.
*)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : choose s = Some x -> choose s' = Some y ->
Equal s s' -> E.eq x y.
End Spec.
End SetsOn.
(** ** Static signature for sets on ordered elements
Similar to the functorial signature [SetsOn], except that the
module [E] of base elements is incorporated in the signature. *)
Module Type Sets.
Declare Module E : OrderedType.
Include SetsOn E.
End Sets.
Module Type S := Sets.
(** ** Some subtyping tests
<<
WSetsOn ---> WSets
| |
| |
V V
SetsOn ---> Sets
Module S_WS (M : Sets) <: WSets := M.
Module Sfun_WSfun (E:OrderedType)(M : SetsOn E) <: WSetsOn E := M.
Module S_Sfun (M : Sets) <: SetsOn M.E := M.
Module WS_WSfun (M : WSets) <: WSetsOn M.E := M.
>>
*)
(** ** Signatures for set representations with ill-formed values.
Motivation:
For many implementation of finite sets (AVL trees, sorted
lists, lists without duplicates), we use the same two-layer
approach:
- A first module deals with the datatype (eg. list or tree) without
any restriction on the values we consider. In this module (named
"Raw" in the past), some results are stated under the assumption
that some invariant (e.g. sortedness) holds for the input sets. We
also prove that this invariant is preserved by set operators.
- A second module implements the exact Sets interface by
using a subtype, for instance [{ l : list A | sorted l }].
This module is a mere wrapper around the first Raw module.
With the interfaces below, we give some respectability to
the "Raw" modules. This allows the interested users to directly
access them via the interfaces. Even better, we can build once
and for all a functor doing the transition between Raw and usual Sets.
Description:
The type [t] of sets may contain ill-formed values on which our
set operators may give wrong answers. In particular, [mem]
may not see a element in a ill-formed set (think for instance of a
unsorted list being given to an optimized [mem] that stops
its search as soon as a strictly larger element is encountered).
Unlike optimized operators, the [In] predicate is supposed to
always be correct, even on ill-formed sets. Same for [Equal] and
other logical predicates.
A predicate parameter [Ok] is used to discriminate between
well-formed and ill-formed values. Some lemmas hold only on sets
validating [Ok]. This predicate [Ok] is required to be
preserved by set operators. Moreover, a boolean function [isok]
should exist for identifying (at least some of) the well-formed sets.
*)
Module Type WRawSets (E : DecidableType).
(** First, we ask for all the functions *)
Include WOps E.
(** Is a set well-formed or ill-formed ? *)
Parameter IsOk : t -> Prop.
Class Ok (s:t) : Prop := ok : IsOk s.
(** In order to be able to validate (at least some) particular sets as
well-formed, we ask for a boolean function for (semi-)deciding
predicate [Ok]. If [Ok] isn't decidable, [isok] may be the
always-false function. *)
Parameter isok : t -> bool.
(** MS:
Dangerous instance, the [isok s = true] hypothesis cannot be discharged
with typeclass resolution. Is it really an instance? *)
Declare Instance isok_Ok s `(isok s = true) : Ok s | 10.
(** Logical predicates *)
Parameter In : elt -> t -> Prop.
Declare Instance In_compat : Proper (E.eq==>eq==>iff) In.
Definition Equal s s' := forall a : elt, In a s <-> In a s'.
Definition Subset s s' := forall a : elt, In a s -> In a s'.
Definition Empty s := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop) s := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop) s := exists x, In x s /\ P x.
Notation "s [=] t" := (Equal s t) (at level 70, no associativity).
Notation "s [<=] t" := (Subset s t) (at level 70, no associativity).
Definition eq : t -> t -> Prop := Equal.
Declare Instance eq_equiv : Equivalence eq.
(** First, all operations are compatible with the well-formed predicate. *)
Declare Instance empty_ok : Ok empty.
Declare Instance add_ok s x `(Ok s) : Ok (add x s).
Declare Instance remove_ok s x `(Ok s) : Ok (remove x s).
Declare Instance singleton_ok x : Ok (singleton x).
Declare Instance union_ok s s' `(Ok s, Ok s') : Ok (union s s').
Declare Instance inter_ok s s' `(Ok s, Ok s') : Ok (inter s s').
Declare Instance diff_ok s s' `(Ok s, Ok s') : Ok (diff s s').
Declare Instance filter_ok s f `(Ok s) : Ok (filter f s).
Declare Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Declare Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
(** Now, the specifications, with constraints on the input sets. *)
Section Spec.
Variable s s': t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Parameter mem_spec : forall `{Ok s}, mem x s = true <-> In x s.
Parameter equal_spec : forall `{Ok s, Ok s'},
equal s s' = true <-> s[=]s'.
Parameter subset_spec : forall `{Ok s, Ok s'},
subset s s' = true <-> s[<=]s'.
Parameter empty_spec : Empty empty.
Parameter is_empty_spec : is_empty s = true <-> Empty s.
Parameter add_spec : forall `{Ok s},
In y (add x s) <-> E.eq y x \/ In y s.
Parameter remove_spec : forall `{Ok s},
In y (remove x s) <-> In y s /\ ~E.eq y x.
Parameter singleton_spec : In y (singleton x) <-> E.eq y x.
Parameter union_spec : forall `{Ok s, Ok s'},
In x (union s s') <-> In x s \/ In x s'.
Parameter inter_spec : forall `{Ok s, Ok s'},
In x (inter s s') <-> In x s /\ In x s'.
Parameter diff_spec : forall `{Ok s, Ok s'},
In x (diff s s') <-> In x s /\ ~In x s'.
Parameter fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (flip f) (elements s) i.
Parameter cardinal_spec : forall `{Ok s},
cardinal s = length (elements s).
Parameter filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Parameter for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Parameter exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Parameter partition_spec1 : compatb f ->
fst (partition f s) [=] filter f s.
Parameter partition_spec2 : compatb f ->
snd (partition f s) [=] filter (fun x => negb (f x)) s.
Parameter elements_spec1 : InA E.eq x (elements s) <-> In x s.
Parameter elements_spec2w : forall `{Ok s}, NoDupA E.eq (elements s).
Parameter choose_spec1 : choose s = Some x -> In x s.
Parameter choose_spec2 : choose s = None -> Empty s.
End Spec.
End WRawSets.
(** From weak raw sets to weak usual sets *)
Module WRaw2SetsOn (E:DecidableType)(M:WRawSets E) <: WSetsOn E.
(** We avoid creating induction principles for the Record *)
Local Unset Elimination Schemes.
Definition elt := E.t.
Record t_ := Mkt {this :> M.t; is_ok : M.Ok this}.
Definition t := t_.
Arguments Mkt this {is_ok}.
Hint Resolve is_ok : typeclass_instances.
Definition In (x : elt)(s : t) := M.In x (this s).
Definition Equal (s s' : t) := forall a : elt, In a s <-> In a s'.
Definition Subset (s s' : t) := forall a : elt, In a s -> In a s'.
Definition Empty (s : t) := forall a : elt, ~ In a s.
Definition For_all (P : elt -> Prop)(s : t) := forall x, In x s -> P x.
Definition Exists (P : elt -> Prop)(s : t) := exists x, In x s /\ P x.
Definition mem (x : elt)(s : t) := M.mem x s.
Definition add (x : elt)(s : t) : t := Mkt (M.add x s).
Definition remove (x : elt)(s : t) : t := Mkt (M.remove x s).
Definition singleton (x : elt) : t := Mkt (M.singleton x).
Definition union (s s' : t) : t := Mkt (M.union s s').
Definition inter (s s' : t) : t := Mkt (M.inter s s').
Definition diff (s s' : t) : t := Mkt (M.diff s s').
Definition equal (s s' : t) := M.equal s s'.
Definition subset (s s' : t) := M.subset s s'.
Definition empty : t := Mkt M.empty.
Definition is_empty (s : t) := M.is_empty s.
Definition elements (s : t) : list elt := M.elements s.
Definition choose (s : t) : option elt := M.choose s.
Definition fold (A : Type)(f : elt -> A -> A)(s : t) : A -> A := M.fold f s.
Definition cardinal (s : t) := M.cardinal s.
Definition filter (f : elt -> bool)(s : t) : t := Mkt (M.filter f s).
Definition for_all (f : elt -> bool)(s : t) := M.for_all f s.
Definition exists_ (f : elt -> bool)(s : t) := M.exists_ f s.
Definition partition (f : elt -> bool)(s : t) : t * t :=
let p := M.partition f s in (Mkt (fst p), Mkt (snd p)).
Instance In_compat : Proper (E.eq==>eq==>iff) In.
Proof. repeat red. intros; apply M.In_compat; congruence. Qed.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Definition eq_dec : forall (s s':t), { eq s s' }+{ ~eq s s' }.
Proof.
intros (s,Hs) (s',Hs').
change ({M.Equal s s'}+{~M.Equal s s'}).
destruct (M.equal s s') eqn:H; [left|right];
rewrite <- M.equal_spec; congruence.
Defined.
Section Spec.
Variable s s' : t.
Variable x y : elt.
Variable f : elt -> bool.
Notation compatb := (Proper (E.eq==>Logic.eq)) (only parsing).
Lemma mem_spec : mem x s = true <-> In x s.
Proof. exact (@M.mem_spec _ _ _). Qed.
Lemma equal_spec : equal s s' = true <-> Equal s s'.
Proof. exact (@M.equal_spec _ _ _ _). Qed.
Lemma subset_spec : subset s s' = true <-> Subset s s'.
Proof. exact (@M.subset_spec _ _ _ _). Qed.
Lemma empty_spec : Empty empty.
Proof. exact M.empty_spec. Qed.
Lemma is_empty_spec : is_empty s = true <-> Empty s.
Proof. exact (@M.is_empty_spec _). Qed.
Lemma add_spec : In y (add x s) <-> E.eq y x \/ In y s.
Proof. exact (@M.add_spec _ _ _ _). Qed.
Lemma remove_spec : In y (remove x s) <-> In y s /\ ~E.eq y x.
Proof. exact (@M.remove_spec _ _ _ _). Qed.
Lemma singleton_spec : In y (singleton x) <-> E.eq y x.
Proof. exact (@M.singleton_spec _ _). Qed.
Lemma union_spec : In x (union s s') <-> In x s \/ In x s'.
Proof. exact (@M.union_spec _ _ _ _ _). Qed.
Lemma inter_spec : In x (inter s s') <-> In x s /\ In x s'.
Proof. exact (@M.inter_spec _ _ _ _ _). Qed.
Lemma diff_spec : In x (diff s s') <-> In x s /\ ~In x s'.
Proof. exact (@M.diff_spec _ _ _ _ _). Qed.
Lemma fold_spec : forall (A : Type) (i : A) (f : elt -> A -> A),
fold f s i = fold_left (fun a e => f e a) (elements s) i.
Proof. exact (@M.fold_spec _). Qed.
Lemma cardinal_spec : cardinal s = length (elements s).
Proof. exact (@M.cardinal_spec s _). Qed.
Lemma filter_spec : compatb f ->
(In x (filter f s) <-> In x s /\ f x = true).
Proof. exact (@M.filter_spec _ _ _). Qed.
Lemma for_all_spec : compatb f ->
(for_all f s = true <-> For_all (fun x => f x = true) s).
Proof. exact (@M.for_all_spec _ _). Qed.
Lemma exists_spec : compatb f ->
(exists_ f s = true <-> Exists (fun x => f x = true) s).
Proof. exact (@M.exists_spec _ _). Qed.
Lemma partition_spec1 : compatb f -> Equal (fst (partition f s)) (filter f s).
Proof. exact (@M.partition_spec1 _ _). Qed.
Lemma partition_spec2 : compatb f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. exact (@M.partition_spec2 _ _). Qed.
Lemma elements_spec1 : InA E.eq x (elements s) <-> In x s.
Proof. exact (@M.elements_spec1 _ _). Qed.
Lemma elements_spec2w : NoDupA E.eq (elements s).
Proof. exact (@M.elements_spec2w _ _). Qed.
Lemma choose_spec1 : choose s = Some x -> In x s.
Proof. exact (@M.choose_spec1 _ _). Qed.
Lemma choose_spec2 : choose s = None -> Empty s.
Proof. exact (@M.choose_spec2 _). Qed.
End Spec.
End WRaw2SetsOn.
Module WRaw2Sets (D:DecidableType)(M:WRawSets D) <: WSets with Module E := D.
Module E := D.
Include WRaw2SetsOn D M.
End WRaw2Sets.
(** Same approach for ordered sets *)
Module Type RawSets (E : OrderedType).
Include WRawSets E <+ HasOrdOps <+ HasLt <+ IsStrOrder.
Section Spec.
Variable s s': t.
Variable x y : elt.
(** Specification of [compare] *)
Parameter compare_spec : forall `{Ok s, Ok s'}, CompSpec eq lt s s' (compare s s').
(** Additional specification of [elements] *)
Parameter elements_spec2 : forall `{Ok s}, sort E.lt (elements s).
(** Specification of [min_elt] *)
Parameter min_elt_spec1 : min_elt s = Some x -> In x s.
Parameter min_elt_spec2 : forall `{Ok s}, min_elt s = Some x -> In y s -> ~ E.lt y x.
Parameter min_elt_spec3 : min_elt s = None -> Empty s.
(** Specification of [max_elt] *)
Parameter max_elt_spec1 : max_elt s = Some x -> In x s.
Parameter max_elt_spec2 : forall `{Ok s}, max_elt s = Some x -> In y s -> ~ E.lt x y.
Parameter max_elt_spec3 : max_elt s = None -> Empty s.
(** Additional specification of [choose] *)
Parameter choose_spec3 : forall `{Ok s, Ok s'},
choose s = Some x -> choose s' = Some y -> Equal s s' -> E.eq x y.
End Spec.
End RawSets.
(** From Raw to usual sets *)
Module Raw2SetsOn (O:OrderedType)(M:RawSets O) <: SetsOn O.
Include WRaw2SetsOn O M.
Definition compare (s s':t) := M.compare s s'.
Definition min_elt (s:t) : option elt := M.min_elt s.
Definition max_elt (s:t) : option elt := M.max_elt s.
Definition lt (s s':t) := M.lt s s'.
(** Specification of [lt] *)
Instance lt_strorder : StrictOrder lt.
Proof. constructor ; unfold lt; red.
unfold complement. red. intros. apply (irreflexivity H).
intros. transitivity y; auto.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
repeat red. unfold eq, lt.
intros (s1,p1) (s2,p2) E (s1',p1') (s2',p2') E'; simpl.
change (M.eq s1 s2) in E.
change (M.eq s1' s2') in E'.
rewrite E,E'; intuition.
Qed.
Section Spec.
Variable s s' s'' : t.
Variable x y : elt.
Lemma compare_spec : CompSpec eq lt s s' (compare s s').
Proof. unfold compare; destruct (@M.compare_spec s s' _ _); auto. Qed.
(** Additional specification of [elements] *)
Lemma elements_spec2 : sort O.lt (elements s).
Proof. exact (@M.elements_spec2 _ _). Qed.
(** Specification of [min_elt] *)
Lemma min_elt_spec1 : min_elt s = Some x -> In x s.
Proof. exact (@M.min_elt_spec1 _ _). Qed.
Lemma min_elt_spec2 : min_elt s = Some x -> In y s -> ~ O.lt y x.
Proof. exact (@M.min_elt_spec2 _ _ _ _). Qed.
Lemma min_elt_spec3 : min_elt s = None -> Empty s.
Proof. exact (@M.min_elt_spec3 _). Qed.
(** Specification of [max_elt] *)
Lemma max_elt_spec1 : max_elt s = Some x -> In x s.
Proof. exact (@M.max_elt_spec1 _ _). Qed.
Lemma max_elt_spec2 : max_elt s = Some x -> In y s -> ~ O.lt x y.
Proof. exact (@M.max_elt_spec2 _ _ _ _). Qed.
Lemma max_elt_spec3 : max_elt s = None -> Empty s.
Proof. exact (@M.max_elt_spec3 _). Qed.
(** Additional specification of [choose] *)
Lemma choose_spec3 :
choose s = Some x -> choose s' = Some y -> Equal s s' -> O.eq x y.
Proof. exact (@M.choose_spec3 _ _ _ _ _ _). Qed.
End Spec.
End Raw2SetsOn.
Module Raw2Sets (O:OrderedType)(M:RawSets O) <: Sets with Module E := O.
Module E := O.
Include Raw2SetsOn O M.
End Raw2Sets.
(** It is in fact possible to provide an ordering on sets with
very little information on them (more or less only the [In]
predicate). This generic build of ordering is in fact not
used for the moment, we rather use a simpler version
dedicated to sets-as-sorted-lists, see [MakeListOrdering].
*)
Module Type IN (O:OrderedType).
Parameter Inline t : Type.
Parameter Inline In : O.t -> t -> Prop.
Declare Instance In_compat : Proper (O.eq==>eq==>iff) In.
Definition Equal s s' := forall x, In x s <-> In x s'.
Definition Empty s := forall x, ~In x s.
End IN.
Module MakeSetOrdering (O:OrderedType)(Import M:IN O).
Module Import MO := OrderedTypeFacts O.
Definition eq : t -> t -> Prop := Equal.
Instance eq_equiv : Equivalence eq.
Proof. firstorder. Qed.
Instance : Proper (O.eq==>eq==>iff) In.
Proof.
intros x x' Ex s s' Es. rewrite Ex. apply Es.
Qed.
Definition Below x s := forall y, In y s -> O.lt y x.
Definition Above x s := forall y, In y s -> O.lt x y.
Definition EquivBefore x s s' :=
forall y, O.lt y x -> (In y s <-> In y s').
Definition EmptyBetween x y s :=
forall z, In z s -> O.lt z y -> O.lt z x.
Definition lt s s' := exists x, EquivBefore x s s' /\
((In x s' /\ Below x s) \/
(In x s /\ exists y, In y s' /\ O.lt x y /\ EmptyBetween x y s')).
Instance : Proper (O.eq==>eq==>eq==>iff) EquivBefore.
Proof.
unfold EquivBefore. intros x x' E s1 s1' E1 s2 s2' E2.
setoid_rewrite E; setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Below.
Proof.
unfold Below. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>eq==>iff) Above.
Proof.
unfold Above. intros x x' Ex s s' Es.
setoid_rewrite Ex; setoid_rewrite Es; intuition.
Qed.
Instance : Proper (O.eq==>O.eq==>eq==>iff) EmptyBetween.
Proof.
unfold EmptyBetween. intros x x' Ex y y' Ey s s' Es.
setoid_rewrite Ex; setoid_rewrite Ey; setoid_rewrite Es; intuition.
Qed.
Instance lt_compat : Proper (eq==>eq==>iff) lt.
Proof.
unfold lt. intros s1 s1' E1 s2 s2' E2.
setoid_rewrite E1; setoid_rewrite E2; intuition.
Qed.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
intros s (x & _ & [(IN,Em)|(IN & y & IN' & LT & Be)]).
specialize (Em x IN); order.
specialize (Be x IN LT); order.
(* transitive *)
intros s1 s2 s3 (x & EQ & [(IN,Pre)|(IN,Lex)])
(x' & EQ' & [(IN',Pre')|(IN',Lex')]).
(* 1) Pre / Pre --> Pre *)
assert (O.lt x x') by (specialize (Pre' x IN); auto).
exists x; split.
intros y Hy; rewrite <- (EQ' y); auto; order.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2) Pre / Lex *)
elim_compare x x'.
(* 2a) x=x' --> Pre *)
destruct Lex' as (y & INy & LT & Be).
exists y; split.
intros z Hz. split; intros INz.
specialize (Pre z INz). rewrite <- (EQ' z), <- (EQ z); auto; order.
specialize (Be z INz Hz). rewrite (EQ z), (EQ' z); auto; order.
left; split; auto.
intros z Hz. transitivity x; auto; order.
(* 2b) x<x' --> Pre *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
left; split; auto.
rewrite <- (EQ' x); auto.
(* 2c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
(* 3) Lex / Pre --> Lex *)
destruct Lex as (y & INy & LT & Be).
specialize (Pre' y INy).
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz; apply Be; auto. rewrite (EQ' z); auto; order.
(* 4) Lex / Lex *)
elim_compare x x'.
(* 4a) x=x' --> impossible *)
destruct Lex as (y & INy & LT & Be).
setoid_replace x with x' in LT; auto.
specialize (Be x' IN' LT); order.
(* 4b) x<x' --> Lex *)
exists x; split.
intros z Hz. rewrite <- (EQ' z) by order; auto.
right; split; auto.
destruct Lex as (y & INy & LT & Be).
elim_compare y x'.
(* 4ba *)
destruct Lex' as (y' & Iny' & LT' & Be').
exists y'; repeat split; auto. order.
intros z Hz LTz. specialize (Be' z Hz LTz).
rewrite <- (EQ' z) in Hz by order.
apply Be; auto. order.
(* 4bb *)
exists y; repeat split; auto.
rewrite <- (EQ' y); auto.
intros z Hz LTz. apply Be; auto. rewrite (EQ' z); auto; order.
(* 4bc*)
assert (O.lt x' x) by auto. order.
(* 4c) x>x' --> Lex *)
exists x'; split.
intros z Hz. rewrite (EQ z) by order; auto.
right; split; auto.
rewrite (EQ x'); auto.
Qed.
Lemma lt_empty_r : forall s s', Empty s' -> ~ lt s s'.
Proof.
intros s s' Hs' (x & _ & [(IN,_)|(_ & y & IN & _)]).
elim (Hs' x IN).
elim (Hs' y IN).
Qed.
Definition Add x s s' := forall y, In y s' <-> O.eq x y \/ In y s.
Lemma lt_empty_l : forall x s1 s2 s2',
Empty s1 -> Above x s2 -> Add x s2 s2' -> lt s1 s2'.
Proof.
intros x s1 s2 s2' Em Ab Ad.
exists x; split.
intros y Hy; split; intros IN.
elim (Em y IN).
rewrite (Ad y) in IN; destruct IN as [EQ|IN]. order.
specialize (Ab y IN). order.
left; split.
rewrite (Ad x). now left.
intros y Hy. elim (Em y Hy).
Qed.
Lemma lt_add_lt : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.lt x1 x2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 LT.
exists x1; split; [ | right; split]; auto.
intros y Hy. rewrite (Ad1 y), (Ad2 y).
split; intros [U|U]; try order.
specialize (Ab1 y U). order.
specialize (Ab2 y U). order.
rewrite (Ad1 x1); auto with *.
exists x2; repeat split; auto.
rewrite (Ad2 x2); now left.
intros y. rewrite (Ad2 y). intros [U|U]. order.
specialize (Ab2 y U). order.
Qed.
Lemma lt_add_eq : forall x1 x2 s1 s1' s2 s2',
Above x1 s1 -> Above x2 s2 -> Add x1 s1 s1' -> Add x2 s2 s2' ->
O.eq x1 x2 -> lt s1 s2 -> lt s1' s2'.
Proof.
intros x1 x2 s1 s1' s2 s2' Ab1 Ab2 Ad1 Ad2 Hx (x & EQ & Disj).
assert (O.lt x1 x).
destruct Disj as [(IN,_)|(IN,_)]; auto. rewrite Hx; auto.
exists x; split.
intros z Hz. rewrite (Ad1 z), (Ad2 z).
split; intros [U|U]; try (left; order); right.
rewrite <- (EQ z); auto.
rewrite (EQ z); auto.
destruct Disj as [(IN,Em)|(IN & y & INy & LTy & Be)].
left; split; auto.
rewrite (Ad2 x); auto.
intros z. rewrite (Ad1 z); intros [U|U]; try specialize (Ab1 z U); auto; order.
right; split; auto.
rewrite (Ad1 x); auto.
exists y; repeat split; auto.
rewrite (Ad2 y); auto.
intros z. rewrite (Ad2 z). intros [U|U]; try specialize (Ab2 z U); auto; order.
Qed.
End MakeSetOrdering.
Module MakeListOrdering (O:OrderedType).
Module MO:=OrderedTypeFacts O.
Local Notation t := (list O.t).
Local Notation In := (InA O.eq).
Definition eq s s' := forall x, In x s <-> In x s'.
Instance eq_equiv : Equivalence eq := _.
Inductive lt_list : t -> t -> Prop :=
| lt_nil : forall x s, lt_list nil (x :: s)
| lt_cons_lt : forall x y s s',
O.lt x y -> lt_list (x :: s) (y :: s')
| lt_cons_eq : forall x y s s',
O.eq x y -> lt_list s s' -> lt_list (x :: s) (y :: s').
Hint Constructors lt_list : core.
Definition lt := lt_list.
Hint Unfold lt : core.
Instance lt_strorder : StrictOrder lt.
Proof.
split.
(* irreflexive *)
assert (forall s s', s=s' -> ~lt s s').
red; induction 2.
discriminate.
inversion H; subst.
apply (StrictOrder_Irreflexive y); auto.
inversion H; subst; auto.
intros s Hs; exact (H s s (eq_refl s) Hs).
(* transitive *)
intros s s' s'' H; generalize s''; clear s''; elim H.
intros x l s'' H'; inversion_clear H'; auto.
intros x x' l l' E s'' H'; inversion_clear H'; auto.
constructor 2. transitivity x'; auto.
constructor 2. rewrite <- H0; auto.
intros.
inversion_clear H3.
constructor 2. rewrite H0; auto.
constructor 3; auto. transitivity y; auto. unfold lt in *; auto.
Qed.
Instance lt_compat' :
Proper (eqlistA O.eq==>eqlistA O.eq==>iff) lt.
Proof.
apply proper_sym_impl_iff_2; auto with *.
intros s1 s1' E1 s2 s2' E2 H.
revert s1' E1 s2' E2.
induction H; intros; inversion_clear E1; inversion_clear E2.
constructor 1.
constructor 2. MO.order.
constructor 3. MO.order. unfold lt in *; auto.
Qed.
Lemma eq_cons :
forall l1 l2 x y,
O.eq x y -> eq l1 l2 -> eq (x :: l1) (y :: l2).
Proof.
unfold eq; intros l1 l2 x y Exy E12 z.
split; inversion_clear 1.
left; MO.order. right; rewrite <- E12; auto.
left; MO.order. right; rewrite E12; auto.
Qed.
Hint Resolve eq_cons : core.
Lemma cons_CompSpec : forall c x1 x2 l1 l2, O.eq x1 x2 ->
CompSpec eq lt l1 l2 c -> CompSpec eq lt (x1::l1) (x2::l2) c.
Proof.
destruct c; simpl; inversion_clear 2; auto with relations.
Qed.
Hint Resolve cons_CompSpec : core.
End MakeListOrdering.
|
//-----------------------------------------------------------------------------
// File : test_setup.v
// Creation date : 28.11.2017
// Creation time : 16:01:32
// Description : Test arrangement for verifying the wishbone slave template.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:communication.template.test:wb_slave.setup:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.template.test/wb_slave.setup/1.0/wb_slave.setup.1.0.xml
//-----------------------------------------------------------------------------
module test_setup();
// wb_slave_0_wb_system_to_clock_generator_0_wb_system wires:
wire wb_slave_0_wb_system_to_clock_generator_0_wb_systemclk;
wire wb_slave_0_wb_system_to_clock_generator_0_wb_systemrst;
// wb_master_0_wb_master_to_wb_slave_0_wb_slave wires:
wire wb_master_0_wb_master_to_wb_slave_0_wb_slaveack;
wire [15:0] wb_master_0_wb_master_to_wb_slave_0_wb_slaveadr;
wire wb_master_0_wb_master_to_wb_slave_0_wb_slavecyc;
wire [31:0] wb_master_0_wb_master_to_wb_slave_0_wb_slavedat_ms;
wire [31:0] wb_master_0_wb_master_to_wb_slave_0_wb_slavedat_sm;
wire wb_master_0_wb_master_to_wb_slave_0_wb_slaveerr;
wire wb_master_0_wb_master_to_wb_slave_0_wb_slavestb;
wire wb_master_0_wb_master_to_wb_slave_0_wb_slavewe;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// wb_master_0 port wires:
wire wb_master_0_ack_i;
wire [15:0] wb_master_0_adr_o;
wire wb_master_0_clk_i;
wire wb_master_0_cyc_o;
wire [31:0] wb_master_0_dat_i;
wire [31:0] wb_master_0_dat_o;
wire wb_master_0_err_i;
wire wb_master_0_rst_i;
wire wb_master_0_stb_o;
wire wb_master_0_we_o;
// wb_slave_0 port wires:
wire wb_slave_0_ack_o;
wire [15:0] wb_slave_0_adr_i;
wire wb_slave_0_clk_i;
wire wb_slave_0_cyc_i;
wire [31:0] wb_slave_0_dat_i;
wire [31:0] wb_slave_0_dat_o;
wire wb_slave_0_err_o;
wire wb_slave_0_rst_i;
wire wb_slave_0_stb_i;
wire wb_slave_0_we_i;
// clock_generator_0 assignments:
assign wb_slave_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_slave_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
// wb_master_0 assignments:
assign wb_master_0_ack_i = wb_master_0_wb_master_to_wb_slave_0_wb_slaveack;
assign wb_master_0_wb_master_to_wb_slave_0_wb_slaveadr[15:0] = wb_master_0_adr_o[15:0];
assign wb_master_0_clk_i = wb_slave_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_master_0_wb_master_to_wb_slave_0_wb_slavecyc = wb_master_0_cyc_o;
assign wb_master_0_dat_i[31:0] = wb_master_0_wb_master_to_wb_slave_0_wb_slavedat_sm[31:0];
assign wb_master_0_wb_master_to_wb_slave_0_wb_slavedat_ms[31:0] = wb_master_0_dat_o[31:0];
assign wb_master_0_err_i = wb_master_0_wb_master_to_wb_slave_0_wb_slaveerr;
assign wb_master_0_rst_i = wb_slave_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_master_0_wb_master_to_wb_slave_0_wb_slavestb = wb_master_0_stb_o;
assign wb_master_0_wb_master_to_wb_slave_0_wb_slavewe = wb_master_0_we_o;
// wb_slave_0 assignments:
assign wb_master_0_wb_master_to_wb_slave_0_wb_slaveack = wb_slave_0_ack_o;
assign wb_slave_0_adr_i[15:0] = wb_master_0_wb_master_to_wb_slave_0_wb_slaveadr[15:0];
assign wb_slave_0_clk_i = wb_slave_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_slave_0_cyc_i = wb_master_0_wb_master_to_wb_slave_0_wb_slavecyc;
assign wb_slave_0_dat_i[31:0] = wb_master_0_wb_master_to_wb_slave_0_wb_slavedat_ms[31:0];
assign wb_master_0_wb_master_to_wb_slave_0_wb_slavedat_sm[31:0] = wb_slave_0_dat_o[31:0];
assign wb_master_0_wb_master_to_wb_slave_0_wb_slaveerr = wb_slave_0_err_o;
assign wb_slave_0_rst_i = wb_slave_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_slave_0_stb_i = wb_master_0_wb_master_to_wb_slave_0_wb_slavestb;
assign wb_slave_0_we_i = wb_master_0_wb_master_to_wb_slave_0_wb_slavewe;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:communication.template:wb_master:1.0
wb_master #(
.ADDR_WIDTH (16),
.DATA_COUNT (8),
.DATA_WIDTH (32),
.BASE_ADDRESS (3840),
.SEND_ERR_ADDR (1))
wb_master_0(
// Interface: wb_master
.ack_i (wb_master_0_ack_i),
.dat_i (wb_master_0_dat_i),
.err_i (wb_master_0_err_i),
.adr_o (wb_master_0_adr_o),
.cyc_o (wb_master_0_cyc_o),
.dat_o (wb_master_0_dat_o),
.stb_o (wb_master_0_stb_o),
.we_o (wb_master_0_we_o),
// Interface: wb_system
.clk_i (wb_master_0_clk_i),
.rst_i (wb_master_0_rst_i),
// These ports are not in any interface
.start (0),
.done ());
// IP-XACT VLNV: tut.fi:communication.template:wb_slave:1.0
wb_slave #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.DATA_COUNT (8),
.BASE_ADDRESS (3840))
wb_slave_0(
// Interface: wb_slave
.adr_i (wb_slave_0_adr_i),
.cyc_i (wb_slave_0_cyc_i),
.dat_i (wb_slave_0_dat_i),
.stb_i (wb_slave_0_stb_i),
.we_i (wb_slave_0_we_i),
.ack_o (wb_slave_0_ack_o),
.dat_o (wb_slave_0_dat_o),
.err_o (wb_slave_0_err_o),
// Interface: wb_system
.clk_i (wb_slave_0_clk_i),
.rst_i (wb_slave_0_rst_i));
endmodule
|
// v6_mig33.v
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.3
// \ \ Application : MIG
// / / Filename : mig_33.v
// /___/ /\ Date Last Modified : $Date: 2009/10/19 15:58:09 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : Virtex-6
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level module. This module serves both as an example,
// and allows the user to synthesize a self-contained design,
// which they can use to test their hardware. In addition to
// the memory controller.
// instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Synthesizable testbench - used to model user's backend
// logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
(* X_CORE_INFO = "mig_v3_3_ddr3_V6, Coregen 11.4" , CORE_GENERATION_INFO = "ddr3_V6,mig_v3_3,{component_name=mig_33, DRAM_TYPE=DDR3, nCS_PER_RANK=1, DQ_CNT_WIDTH=6, DQS_CNT_WIDTH=3, RANK_WIDTH=1, BANK_WIDTH=3, CK_WIDTH=1, COL_WIDTH=10, CS_WIDTH=1, DM_WIDTH=8, USE_DM_PORT=1, DQ_WIDTH=64, DRAM_WIDTH=8, DQS_WIDTH=8, ROW_WIDTH=13, AL=0, BURST_MODE=8, BURST_TYPE=SEQ, IODELAY_HP_MODE=ON, CL=6, CWL=5, RANKS=1, WRLVL=ON, PHASE_DETECT=ON, RTT_NOM=DISABLED, RTT_WR=OFF, OUTPUT_DRV=HIGH, REG_CTRL=OFF, nDQS_COL0=6, nDQS_COL1=2, nDQS_COL2=0, nDQS_COL3=0, DQS_LOC_COL0=48'h050403020100, DQS_LOC_COL1=48'h050403020100, DQS_LOC_COL2=48'h050403020100, DQS_LOC_COL3=48'h050403020100, tFAW=45000, tRRD=7500, tRAS=37500, tRCD=13130, tREFI=7800000, tRFC=110000, tRP=13130, tRTP=7500, tWTR=7500, DEBUG_PORT=ON, ADDR_WIDTH=27, ECC=OFF, DATA_WIDTH=64, ECC_TEST=OFF, CLKFBOUT_MULT_F=3, CLKOUT_DIVIDE=3, tCK=2500, REFCLK_FREQ=200, IODELAY_GRP=IODELAY_MIG, INTERFACE_TYPE=DDR3_SDRAM, RST_ACT_LOW=1, INPUT_CLK_TYPE=DIFFERENTIAL, LANGUAGE=Verilog, SYNTHESIS_TOOL=XST, NO_OF_CONTROLLERS=1}" *)
module v6_mig33 #
(
parameter REFCLK_FREQ = 200,
// # = 200 when design frequency <= 533 MHz,
// = 300 when design frequency > 533 MHz.
parameter IODELAY_GRP = "IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter CLKFBOUT_MULT_F = 6, // ML605 (was 3 with MIG 3.3)
// write PLL VCO multiplier.
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor.
parameter CLKOUT_DIVIDE = 3,
// VCO output divisor for fast (memory) clocks.
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric clock.
// # = 2, 1.
parameter tCK = 2500,
// memory tCK paramter.
// # = Clock Period.
parameter DEBUG_PORT = "ON",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter SIM_INIT_OPTION = "NONE",
// # = "SKIP_PU_DLY" - Skip the memory
// initilization sequence,
// = "NONE" - Complete the memory
// initilization sequence.
parameter SIM_CAL_OPTION = "NONE",
// # = "FAST_CAL" - Skip the delay
// Calibration process,
// = "NONE" - Complete the delay
// Calibration process.
parameter PERFCLK_DIFF = 0,
// Performance clock delay difference
// between inner and outer columns in ps.
// Should be 0 in only inner column is used.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per Rank for
// phy.
parameter DQS_CNT_WIDTH = 3,
// # = ceil(log2(DQS_WIDTH)).
parameter RANK_WIDTH = 1,
// # = ceil(log2(RANKS)).
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter DM_WIDTH = 8,
// # of Data Mask bits.
parameter DQ_WIDTH = 64,
// # of Data (DQ) bits.
parameter DQS_WIDTH = 8,
// # of DQS/DQS# bits.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter BURST_MODE = "8",
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
parameter BM_CNT_WIDTH = 2,
// # = ceil(log2(nBANK_MACHS)).
parameter ADDR_CMD_MODE = "UNBUF",
// # = "UNBUF", "REG".
parameter ORDERING = "STRICT",
// # = "NORM", "STRICT", "RELAXED".
parameter WRLVL = "ON",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter PHASE_DETECT = "ON",
// # = "ON", "OFF".
parameter RTT_NOM = "40", // ML605 "40" or "60" acceptable parameter value
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF",
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter OUTPUT_DRV = "HIGH",
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/6,
// = "LOW" - RZQ/7.
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter nDQS_COL0 = 3,
// Number of DQS groups in I/O column #1. // ML605
parameter nDQS_COL1 = 5,
// Number of DQS groups in I/O column #2. // ML605
parameter nDQS_COL2 = 0,
// Number of DQS groups in I/O column #3.
parameter nDQS_COL3 = 0,
// Number of DQS groups in I/O column #4.
parameter DQS_LOC_COL0 = 24'h020100,
// DQS groups in column #1. // ML605
parameter DQS_LOC_COL1 = 40'h0706050403,
// DQS groups in column #2. // ML605
parameter DQS_LOC_COL2 = 0,
// DQS groups in column #3.
parameter DQS_LOC_COL3 = 0,
// DQS groups in column #4.
parameter OCB_MONITOR = "ON",
// # = "ON",
// = "OFF".
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter ECC_TEST = "OFF",
parameter TCQ = 100,
parameter RST_ACT_LOW = 0,
// =1 for active low reset,
// =0 for active high.
//parameter INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter INPUT_CLK_TYPE = "SINGLE_ENDED",
// input clock type DIFFERNTIAL or SINGLE_ENDED
parameter STARVE_LIMIT = 2
// # = 2,3,4.
)
(
input clk_sys,
input clk_ref, // 200 MHz for the IODELAY control
input sys_rst, // System reset, active Hi
inout [DQ_WIDTH-1:0] ddr3_dq,
output [ROW_WIDTH-1:0] ddr3_addr,
output [BANK_WIDTH-1:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt,
output [CS_WIDTH-1:0] ddr3_cke,
output [DM_WIDTH-1:0] ddr3_dm,
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
output [CK_WIDTH-1:0] ddr3_ck_p,
output [CK_WIDTH-1:0] ddr3_ck_n,
output ddr3_reset_n,
inout sda,
output scl,
input app_wdf_wren,
input [(4*PAYLOAD_WIDTH)-1:0] app_wdf_data,
input [(4*PAYLOAD_WIDTH)/8-1:0] app_wdf_mask,
input app_wdf_end,
input [ADDR_WIDTH-1:0] tg_addr,
input [2:0] app_cmd,
input app_en,
output app_full,
output app_wdf_full,
output [(4*PAYLOAD_WIDTH)-1:0] app_rd_data,
output app_rd_data_valid,
output app_rd_data_end, // added
output phy_init_done,
output tb_rst_n,
output tb_clk,
// added 25 debug signals debug..
output [DQS_WIDTH-1:0] dbg_wl_dqs_inverted,
output [2*DQS_WIDTH-1:0] dbg_wr_calib_clk_delay,
output [5*DQS_WIDTH-1:0] dbg_wl_odelay_dqs_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_wl_odelay_dq_tap_cnt,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [5*DQS_WIDTH-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
output [3*DQS_WIDTH-1:0] dbg_rd_bitslip_cnt,
output [2*DQS_WIDTH-1:0] dbg_rd_clkdly_cnt,
output [4:0] dbg_rd_active_dly,
input dbg_pd_off,
input dbg_pd_maintain_off,
input dbg_pd_maintain_0_only,
input dbg_ocb_mon_off,
input dbg_inc_cpt,
input dbg_dec_cpt,
input dbg_inc_rd_dqs,
input dbg_dec_rd_dqs,
input [DQS_CNT_WIDTH-1:0] dbg_inc_dec_sel,
output [5*DQS_WIDTH-1:0] dbg_dqs_p_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_dqs_n_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_dq_tap_cnt,
output [4*DQ_WIDTH-1:0] dbg_rddata
);
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam SYSCLK_PERIOD = tCK * nCK_PER_CLK;
localparam DATA_WIDTH = 64;
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
localparam APP_DATA_WIDTH = PAYLOAD_WIDTH * 4;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
wire mmcm_clk;
wire iodelay_ctrl_rdy;
// (* KEEP = "TRUE" *) wire sda_i; //ML605 comment out used IIC ports
// (* KEEP = "TRUE" *) wire scl_i; //ML606 comment out used IIC ports
wire rst;
wire rst_pll_ck_fb;
wire pll_lock_ck_fb;
wire clk;
wire clk_mem;
wire clk_wr_i;
wire clk_wr_o;
wire ocb_mon_PSDONE;
wire ocb_mon_PSEN;
wire ocb_mon_PSINCDEC;
wire [(BM_CNT_WIDTH)-1:0] bank_mach_next;
wire ddr3_parity;
wire [ADDR_WIDTH-1:0] app_addr;
wire app_hi_pri;
wire dfi_init_complete;
wire [3:0] app_ecc_multiple_err_i;
wire [47:0] traffic_wr_data_counts;
wire [47:0] traffic_rd_data_counts;
wire ddr3_cs0_clk;
wire [35:0] ddr3_cs0_control;
wire [383:0] ddr3_cs0_data;
wire [7:0] ddr3_cs0_trig;
wire [255:0] ddr3_cs1_async_in;
wire [35:0] ddr3_cs1_control;
wire [255:0] ddr3_cs2_async_in;
wire [35:0] ddr3_cs2_control;
wire [255:0] ddr3_cs3_async_in;
wire [35:0] ddr3_cs3_control;
wire ddr3_cs4_clk;
wire [35:0] ddr3_cs4_control;
wire [31:0] ddr3_cs4_sync_out;
assign phy_init_done = dfi_init_complete;
assign app_addr = tg_addr;
assign app_hi_pri = 1'b0;
assign tb_clk = clk;
assign tb_rst_n = !rst;
MUXCY scl_inst
(
.O (scl),
.CI (scl_i),
.DI (1'b0),
.S (1'b1)
);
MUXCY sda_inst
(
.O (sda),
.CI (sda_i),
.DI (1'b0),
.S (1'b1)
);
assign clk_ref_p = 1'b0;
assign clk_ref_n = 1'b0;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
//***************************************************************************
iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_iodelay_ctrl
(
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref (clk_ref),
.sys_rst (sys_rst),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy)
);
assign mmcm_clk = clk_sys; // The DRAM clock
/*
clk_ibuf #
( .INPUT_CLK_TYPE (INPUT_CLK_TYPE)) u_clk_ibuf
( .sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk (clk_sys),
.mmcm_clk (mmcm_clk)
);
*/
infrastructure #
(
.TCQ (TCQ),
.CLK_PERIOD (SYSCLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.PERFCLK_DIFF (PERFCLK_DIFF),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_infrastructure
(
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.pll_lock_ck_fb (pll_lock_ck_fb),
.clk_mem (clk_mem),
.clk (clk),
.clk_wr_i (clk_wr_i),
.clk_wr_o (clk_wr_o),
.rst_pll_ck_fb (rst_pll_ck_fb),
.rstdiv0 (rst),
.PSDONE (ocb_mon_PSDONE),
.PSEN (ocb_mon_PSEN),
.PSINCDEC (ocb_mon_PSINCDEC)
);
memc_ui_top #
(
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DM_WIDTH (DM_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DEBUG_PORT (DEBUG_PORT),
.IODELAY_GRP (IODELAY_GRP),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.OCB_MONITOR (OCB_MONITOR),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.PHASE_DETECT (PHASE_DETECT),
.RANK_WIDTH (RANK_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.WRLVL (WRLVL),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3),
.BURST_MODE (BURST_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.tCK (tCK),
.ADDR_WIDTH (ADDR_WIDTH),
.TCQ (TCQ),
.ECC_TEST (ECC_TEST),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH)
)
u_memc_ui_top
(
.ddr_addr (ddr3_addr),
.ddr_ba (ddr3_ba),
.ddr_cas_n (ddr3_cas_n),
.ddr_ck_n (ddr3_ck_n),
.ddr_ck (ddr3_ck_p),
.ddr_cke (ddr3_cke),
.ddr_cs_n (ddr3_cs_n),
.ddr_dm (ddr3_dm),
.ddr_odt (ddr3_odt),
.ddr_ras_n (ddr3_ras_n),
.ddr_reset_n (ddr3_reset_n),
.ddr_parity (ddr3_parity),
.ddr_we_n (ddr3_we_n),
.ddr_dq (ddr3_dq),
.ddr_dqs_n (ddr3_dqs_n),
.ddr_dqs (ddr3_dqs_p),
.pll_lock_ck_fb (pll_lock_ck_fb),
.bank_mach_next (bank_mach_next),
.ocb_mon_PSEN (ocb_mon_PSEN),
.ocb_mon_PSINCDEC (ocb_mon_PSINCDEC),
.dfi_init_complete (dfi_init_complete),
.app_ecc_multiple_err (app_ecc_multiple_err_i),
.clk (clk),
.clk_mem (clk_mem),
.clk_wr_i (clk_wr_i),
.clk_wr_o (clk_wr_o),
.ocb_mon_PSDONE (ocb_mon_PSDONE),
.rst (rst),
.rst_pll_ck_fb (rst_pll_ck_fb),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_full (app_full),
.app_wdf_full (app_wdf_full),
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_hi_pri (app_hi_pri),
.app_sz (1'b1),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.dbg_wl_dqs_inverted (dbg_wl_dqs_inverted),
.dbg_wr_calib_clk_delay (dbg_wr_calib_clk_delay),
.dbg_wl_odelay_dqs_tap_cnt (dbg_wl_odelay_dqs_tap_cnt),
.dbg_wl_odelay_dq_tap_cnt (dbg_wl_odelay_dq_tap_cnt),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_bitslip_cnt (dbg_rd_bitslip_cnt),
.dbg_rd_clkdly_cnt (dbg_rd_clkdly_cnt),
.dbg_rd_active_dly (dbg_rd_active_dly),
.dbg_dqs_p_tap_cnt (dbg_dqs_p_tap_cnt),
.dbg_dqs_n_tap_cnt (dbg_dqs_n_tap_cnt),
.dbg_dq_tap_cnt (dbg_dq_tap_cnt),
.dbg_rddata (dbg_rddata),
.dbg_pd_off (dbg_pd_off),
.dbg_pd_maintain_off (dbg_pd_maintain_off),
.dbg_pd_maintain_0_only (dbg_pd_maintain_0_only),
.dbg_ocb_mon_off (dbg_ocb_mon_off),
.dbg_inc_cpt (dbg_inc_cpt),
.dbg_dec_cpt (dbg_dec_cpt),
.dbg_inc_rd_dqs (dbg_inc_rd_dqs),
.dbg_dec_rd_dqs (dbg_dec_rd_dqs),
.dbg_inc_dec_sel (dbg_inc_dec_sel)
);
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_data_receive(
input posedge_clk,
input rx_resetn,
input ready_control_p_r,
input ready_data_p_r,
input ready_control,
input ready_data,
input parity_rec_c,
input parity_rec_d,
input parity_rec_c_gen,
input parity_rec_d_gen,
input [2:0] control_p_r,
input [2:0] control_l_r,
input [8:0] dta_timec_p,
output reg [1:0] state_data_process,
output reg last_is_control,
output reg last_is_data,
output reg last_is_timec,
output reg rx_error_c,
output reg rx_error_d,
output reg rx_got_fct,
output reg [8:0] rx_data_flag/* synthesis dont_replicate */,
output reg [7:0] timecode/* synthesis dont_replicate */
);
reg [1:0] next_state_data_process/* synthesis dont_replicate */;
always@(*)
begin
next_state_data_process = state_data_process;
case(state_data_process)
2'd0:
begin
if(ready_control_p_r || ready_data_p_r)
begin
next_state_data_process = 2'd1;
end
else
begin
next_state_data_process = 2'd0;
end
end
2'd1:
begin
if(ready_control || ready_data)
begin
next_state_data_process = 2'd0;
end
else
begin
next_state_data_process = 2'd1;
end
end
default:
begin
next_state_data_process = 2'd0;
end
endcase
end
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
rx_data_flag <= 9'd0;
timecode <= 8'd0;
state_data_process <= 2'd0;
rx_error_c <= 1'b0;
rx_error_d <= 1'b0;
rx_got_fct <= 1'b0;
end
else
begin
state_data_process <= next_state_data_process;
case(state_data_process)
2'd0:
begin
rx_error_c <= rx_error_c;
rx_error_d <= rx_error_d;
if(ready_control_p_r)
begin
if(control_l_r[2:0] != 3'd7 && control_p_r[2:0] == 3'd4)
begin
rx_got_fct <= 1'b1;
end
else
begin
rx_got_fct <= 1'b0;
end
if(control_p_r[2:0] == 3'd6)
begin
rx_data_flag <= 9'b100000001;
end
else if(control_p_r[2:0] == 3'd5)
begin
rx_data_flag <= 9'b100000000;
end
else
begin
rx_data_flag <= rx_data_flag;
end
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
end
else if(ready_data_p_r)
begin
rx_got_fct <= 1'b0;
if(control_p_r[2:0] == 3'd7)
begin
timecode <= {dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
end
else
begin
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
end
end
else
begin
rx_got_fct <= 1'b0;
timecode <= timecode;
end
end
2'd1:
begin
if(ready_control_p_r)
begin
if(parity_rec_c_gen != parity_rec_c)
begin
rx_error_c <= 1'b1;
end
else
rx_error_c <= rx_error_c;
rx_got_fct <= rx_got_fct;
end
else if(ready_data_p_r)
begin
if(parity_rec_d_gen != parity_rec_d)
begin
rx_error_d <= 1'b1;
end
else
rx_error_d <= rx_error_d;
rx_got_fct <= 1'b0;
end
else
begin
rx_error_c <= rx_error_c;
rx_error_d <= rx_error_d;
rx_got_fct <= 1'b0;
end
rx_data_flag <= rx_data_flag;
timecode <= timecode;
end
default:
begin
rx_data_flag <= rx_data_flag;
timecode <= timecode;
rx_got_fct <= rx_got_fct;
end
endcase
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_2_0/system_inverter_2_0_stub.v
// Design : system_inverter_2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_2_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_2_V
`define SKY130_FD_SC_MS__O22A_2_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22a_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_BLACKBOX_V
`define SKY130_FD_SC_HS__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_BLACKBOX_V
|
/**
* testbench.v
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p + 1;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_li;
logic [width_p-1:0] a_li;
logic signed_li;
logic ready_lo;
logic v_lo;
logic [width_p-1:0] z_lo;
logic yumi_li;
bsg_fpu_i2f #(
.e_p(8)
,.m_p(23)
) dut (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_li)
,.a_i(a_li)
,.signed_i(signed_li)
,.ready_o(ready_lo)
,.v_o(v_lo)
,.z_o(z_lo)
,.yumi_i(yumi_li)
);
logic tr_v_li;
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(tr_v_li)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
assign {signed_li, a_li} = tr_data_lo;
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign tr_data_li = {
1'b0
, z_lo
};
assign v_li = tr_v_lo;
assign tr_yumi_li = tr_v_lo & ready_lo;
assign tr_v_li = v_lo;
assign yumi_li = v_lo & tr_ready_lo;
initial begin
wait(done_lo);
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
// that should not work.
//
// The given generate loops should attempt to access invalid bits of mask and
// trigger errors.
// is defined by SIZE. However since the loop range is larger, this only works
// if short-circuited evaluation of the generate loop is in place.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
`define MAX_SIZE 3
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (2'b11))
i_test_gen (.clk (clk));
// This is only a compilation test, so we can immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that all have errors in applying short-circuting to
// generate "if" conditionals.
// Attempt to access invalid bits of MASK in different ways
generate
genvar g;
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE + 1)) && MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < SIZE) && MASK[g + 1]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise AND
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE)) & MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise OR
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g >= SIZE) | ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_FUNCTIONAL_PP_V |
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof.
split; red; unfold relation_equivalence, iffT.
- firstorder.
- firstorder.
- intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : Antisymmetric eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof.
unfold flip; constructor; unfold flip.
- intros. apply H. apply symmetry. apply X.
- unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption.
Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:15:45 06/08/2013
// Design Name:
// Module Name: Control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control(input [3:0] opcode,output [2:0]ALUControl,output RegWrite,RegDst,ALUSrc,Branch,
MemWrite,MemtoReg
);
reg [8:0] combin;
assign {RegWrite,RegDst,ALUSrc,ALUControl,Branch,MemWrite,MemtoReg} = combin ;
always @(opcode)
case(opcode)
4'b0000: combin=9'b0_0000_0000; //NOP
4'b0001: combin=9'b1_1000_1000; //ADD
4'b0010: combin=9'b1_1001_0000; //SUB
4'b0011: combin=9'b1_1001_1000; //AND
4'b0100: combin=9'b1_1001_0000; //OR
4'b0101: combin=9'b1_0110_1000; //LFT SHift
4'b0110: combin=9'b1_0111_0000; //RT Shift
4'b0111: combin=9'b1_0100_1000; //ADDI
4'b1000: combin=9'b1_0101_0000; //SUBI
4'b1001: combin=9'b1_0100_1001; //LD REG
4'b1010: combin=9'b0_0100_1010; //Store Reg
4'b1011: combin=9'b1_0100_1001; //LD I
4'b1100: combin=9'b0_0100_1010; //Store I
4'b1101: combin=9'b0_0001_0100; //Jump
default: combin=9'b0_0000_0000; //NOP
endcase
endmodule
|
// File: MUX4_1_MS_TBV.v
// Generated by MyHDL 0.10
// Date: Sun Sep 23 18:20:41 2018
`timescale 1ns/10ps
module MUX4_1_MS_TBV (
);
// myHDL -> Verilog testbench for module `MUX4_1_MS`
reg x0 = 0;
reg x1 = 0;
wire y;
reg x2 = 0;
reg x3 = 0;
reg s0 = 0;
reg s1 = 0;
wire [68:0] x0TV;
wire [68:0] x1TV;
wire [68:0] x2TV;
wire [68:0] x3TV;
wire [68:0] s0TV;
wire [68:0] s1TV;
wire MUX4_1_MS0_0_x0x1_yWire;
wire MUX4_1_MS0_0_MUX2_1_Combo1_0_1_y;
assign x0TV = 69'd2296870857426870268;
assign x1TV = 69'd34723282962276803050;
assign x2TV = 69'd118059162071741130356;
assign x3TV = 69'd196765270119568550582;
assign s0TV = 69'd137438953451;
assign s1TV = 69'd9007061817884663;
always @(x0, x3, s0, x2, y, x1, s1) begin: MUX4_1_MS_TBV_PRINT_DATA
$write("%h", x0);
$write(" ");
$write("%h", x1);
$write(" ");
$write("%h", x2);
$write(" ");
$write("%h", x3);
$write(" ");
$write("%h", s0);
$write(" ");
$write("%h", s1);
$write(" ");
$write("%h", y);
$write("\n");
end
assign MUX4_1_MS0_0_x0x1_yWire = (((!s0) && x0) | (s0 && x1));
assign MUX4_1_MS0_0_MUX2_1_Combo1_0_1_y = (((!s0) && x2) | (s0 && x3));
assign y = (((!s1) && MUX4_1_MS0_0_x0x1_yWire) | (s1 && MUX4_1_MS0_0_MUX2_1_Combo1_0_1_y));
initial begin: MUX4_1_MS_TBV_STIMULES
integer i;
for (i=0; i<69; i=i+1) begin
x0 <= x0TV[i];
x1 <= x1TV[i];
x2 <= x2TV[i];
x3 <= x3TV[i];
s0 <= s0TV[i];
s1 <= s1TV[i];
# 1;
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O22AI_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module nco_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 5,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
input wire [15:0] sine_sample_V,
input wire sine_sample_V_ap_vld,
output wire [15:0] step_size_V
);
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of sine_sample_V
// bit 15~0 - sine_sample_V[15:0] (Read)
// others - reserved
// 0x14 : Control signal of sine_sample_V
// bit 0 - sine_sample_V_ap_vld (Read/COR)
// others - reserved
// 0x18 : Data signal of step_size_V
// bit 15~0 - step_size_V[15:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
// address bits
localparam
ADDR_BITS = 5;
// address
localparam
ADDR_SINE_SAMPLE_V_DATA_0 = 5'h10,
ADDR_SINE_SAMPLE_V_CTRL = 5'h14,
ADDR_STEP_SIZE_V_DATA_0 = 5'h18,
ADDR_STEP_SIZE_V_CTRL = 5'h1c;
// axi write fsm
localparam
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2;
// axi read fsm
localparam
RDIDLE = 2'd0,
RDDATA = 2'd1;
//------------------------Local signal-------------------
// axi write
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
// axi read
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg [15:0] int_sine_sample_V;
reg int_sine_sample_V_ap_vld;
reg [15:0] int_step_size_V;
//------------------------Body---------------------------
//++++++++++++++++++++++++axi write++++++++++++++++++++++
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi read+++++++++++++++++++++++
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_SINE_SAMPLE_V_DATA_0: begin
rdata <= int_sine_sample_V[15:0];
end
ADDR_SINE_SAMPLE_V_CTRL: begin
rdata[0] <= int_sine_sample_V_ap_vld;
end
ADDR_STEP_SIZE_V_DATA_0: begin
rdata <= int_step_size_V[15:0];
end
endcase
end
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++internal registers+++++++++++++
assign step_size_V = int_step_size_V;
// int_sine_sample_V
always @(posedge ACLK) begin
if (ARESET)
int_sine_sample_V <= 0;
else if (ACLK_EN) begin
if (sine_sample_V_ap_vld)
int_sine_sample_V <= sine_sample_V;
end
end
// int_sine_sample_V_ap_vld
always @(posedge ACLK) begin
if (ARESET)
int_sine_sample_V_ap_vld <= 1'b0;
else if (ACLK_EN) begin
if (sine_sample_V_ap_vld)
int_sine_sample_V_ap_vld <= 1'b1;
else if (ar_hs && raddr == ADDR_SINE_SAMPLE_V_CTRL)
int_sine_sample_V_ap_vld <= 1'b0; // clear on read
end
end
// int_step_size_V[15:0]
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (w_hs && waddr == ADDR_STEP_SIZE_V_DATA_0)
int_step_size_V[15:0] <= (WDATA[31:0] & wmask) | (int_step_size_V[15:0] & ~wmask);
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_efa.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//****************************************************************
//
// Module: bw_r_efa
//
// Description: RTL model for EFA (EFuse Array)
//
//****************************************************************
`include "sys.h"
module bw_r_efa (
vpp,
pi_efa_prog_en,
sbc_efa_read_en,
sbc_efa_word_addr,
sbc_efa_bit_addr,
sbc_efa_margin0_rd,
sbc_efa_margin1_rd,
efa_sbc_data,
pwr_ok,
por_n,
sbc_efa_sup_det_rd,
sbc_efa_power_down,
so,
si,
se,
vddo,
clk
);
input vpp; // VPP input from I/O
output [31:0] efa_sbc_data; // Data from e-fuse array to SBC
input pi_efa_prog_en; // e-fuse array program enable
input sbc_efa_read_en; // e-fuse array read enable
input [5:0] sbc_efa_word_addr; // e-fuse array word addr
input [4:0] sbc_efa_bit_addr; // e-fuse array bit addr
input sbc_efa_margin0_rd; // e-fuse array margin0 read
input sbc_efa_margin1_rd; // e-fuse array margin1 read
input pwr_ok; // power_ok reset
input por_n; // por_n reset
input sbc_efa_sup_det_rd; // e-fuse array supply detect read
input sbc_efa_power_down; // e-fuse power down signal from SBC
output so; // Scan ports
input si;
input se;
input vddo;
input clk; // cpu clk
/*--------------------------------------------------------------------------*/
//** Parameters and define **//
parameter MAXFILENAME=200;
//parameter EFA_READ_LAT = 5670 ; // 7 system cycles (150Mhz) - 1/4(sys clk); about 45ns
// 840 ticks = 1 system cycle
parameter EFA_READ_LAT = 45000 ; // about 45ns (timescale is 1 ps)
/* The access time has been specified to be 45ns for a worst case read */
//** Wire and Reg declarations **//
reg [MAXFILENAME*8-1:0] efuse_data_filename;
reg [31:0] efuse_array[0:63],efuse_row,efa_read_data; //EFUSE ARRAY
integer file_get_status,i;
reg [31:0] fpInVec;
wire [31:0] efa_sbc_data;
wire l1clk;
wire lvl_det_l; // level detect ok
wire vddc_ok_l; // vddc ok
wire vddo_ok_l; // vddo ok
wire vpp_ok_l; // vpp ok
reg efuse_rd_progress;
reg efuse_enable_write_check;
/*--------------------------------------------------------------------------*/
// Process data file
// synopsys translate_off
initial
begin
efuse_enable_write_check = 1;
// Get Efuse data file from plusarg.
if ($value$plusargs("efuse_data_file=%s", efuse_data_filename))
begin
// Read Efuse data file if present
$display("INFO: efuse data file is being read--filename=%0s",
efuse_data_filename);
$readmemh(efuse_data_filename, efuse_array);
$display("INFO: completed reading efuse data file");
end
else
begin
//if file not present, initialize efuse_array with default value
$display("INFO: Using default efuse data for the efuse array");
for (i=0;i<=63;i=i+1) begin
efuse_array[i] = 32'b0;
end
end
end
// Process power down signal
assign l1clk = clk & ~sbc_efa_power_down;
// Scan logic not in RTL
assign so = se ? si : 1'bx;
//assign supply detect signals to valid values (circuit cannot be impl in model)
assign vddc_ok_l = 1'b0;
assign vddo_ok_l = 1'b0;
assign vpp_ok_l = 1'b0;
assign lvl_det_l = 1'b0;
always @(posedge l1clk) begin
// Write operation , one bit at a time
if ((pi_efa_prog_en === 1'b1) && (pwr_ok === 1'b1) && (por_n === 1'b1)) begin
efuse_row = efuse_array[sbc_efa_word_addr];
efuse_row[sbc_efa_bit_addr] = 1'b1;
efuse_array[sbc_efa_word_addr] <= efuse_row;
end
end
// efa_read_data is from the VPP_CORE which is reset to 0 in ckt when read is de-asserted
// However in RTL it is reset to X because I want to simulate the wait time where
// efa_read_data is indeed X till the latency period
// margin reads are not modelled in the RTL
always @(posedge l1clk) begin
// Read operation , 32 bits at a time
if ((sbc_efa_read_en) & ~efuse_rd_progress) begin
// About 45ns
efa_read_data[31:0] <= #EFA_READ_LAT efuse_array[sbc_efa_word_addr];
efuse_rd_progress = 1'b1;
end
if (~(sbc_efa_read_en)) begin
efuse_rd_progress = 1'b0;
end
if (~efuse_rd_progress) begin
efa_read_data[31:0] <= 32'bx;
end
end
// synopsys translate_on
// In ckt, when sbc_efa_read_en is low, output remains the same.
assign efa_sbc_data[31:0] = por_n ? ((pwr_ok & sbc_efa_read_en) ? (sbc_efa_sup_det_rd ?
{28'bx,~lvl_det_l,~vddc_ok_l,~vddo_ok_l,~vpp_ok_l}
: efa_read_data[31:0] ) : efa_sbc_data[31:0]) : 32'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
reg notifier ;
wire buf_Q ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_BEHAVIORAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:21:30 05/20/2014
// Design Name: alu
// Module Name: C:/Users/Deus/Windows Sync/Xilinx Workspace/Single/test_alu.v
// Project Name: Single
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_alu;
// Inputs
reg [3:0] alu_ctl;
reg [31:0] A;
reg [31:0] B;
// Outputs
wire zero;
wire [31:0] result;
// Instantiate the Unit Under Test (UUT)
alu uut (
.alu_ctl(alu_ctl),
.A(A),
.B(B),
.zero(zero),
.result(result)
);
initial begin
// Initialize Inputs
alu_ctl = 0;
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 32'h01234567;
B = 32'h3456789A;
# 100;
alu_ctl = 4'b0001;
# 100;
alu_ctl = 4'b0010;
# 100;
alu_ctl = 4'b0011;
# 100;
alu_ctl = 4'b0100;
# 100;
alu_ctl = 4'b0101;
# 100;
alu_ctl = 4'b0110;
# 100;
alu_ctl = 4'b0111;
# 100;
alu_ctl = 4'b1000;
# 100;
alu_ctl = 4'b1001;
# 100;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_FUNCTIONAL_PP_V |
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: dpth_regfile.v
// Version: 1.0
// Description:
// Register file.
//----------------------------------------------------------------------------------------
`include "defines.vh"
module dpth_regfile (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
//------------------------------
// Input data
//------------------------------
input wire [2:0] rd_at,
input wire [2:0] wr_at,
input wire wr_en,
input wire [`REG_BITS] din,
//------------------------------
// Output data
//------------------------------
output wire [`REG_BITS] dout
);
reg [`REG_BITS] data [2:0];
always @(posedge clk)
begin
if (wr_en == 1'b1)
data[wr_at] <= din;
end
assign dout = data[rd_at];
endmodule
//----------------------------------------------------------------------------------------
// Trivia:
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The Subsystem-TOP module to implement CPU and some closely coupled devices
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_top(
// This clock should comes from the crystal pad generated high speed clock (16MHz)
input hfextclk,
output hfxoscen,// The signal to enable the crystal pad generated clock
// This clock should comes from the crystal pad generated low speed clock (32.768KHz)
input lfextclk,
output lfxoscen,// The signal to enable the crystal pad generated clock
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
input io_pads_bootrom_n_i_ival,
output io_pads_bootrom_n_o_oval,
output io_pads_bootrom_n_o_oe,
output io_pads_bootrom_n_o_ie,
output io_pads_bootrom_n_o_pue,
output io_pads_bootrom_n_o_ds,
input io_pads_aon_erst_n_i_ival,
output io_pads_aon_erst_n_o_oval,
output io_pads_aon_erst_n_o_oe,
output io_pads_aon_erst_n_o_ie,
output io_pads_aon_erst_n_o_pue,
output io_pads_aon_erst_n_o_ds,
input io_pads_aon_pmu_dwakeup_n_i_ival,
output io_pads_aon_pmu_dwakeup_n_o_oval,
output io_pads_aon_pmu_dwakeup_n_o_oe,
output io_pads_aon_pmu_dwakeup_n_o_ie,
output io_pads_aon_pmu_dwakeup_n_o_pue,
output io_pads_aon_pmu_dwakeup_n_o_ds,
input io_pads_aon_pmu_vddpaden_i_ival,
output io_pads_aon_pmu_vddpaden_o_oval,
output io_pads_aon_pmu_vddpaden_o_oe,
output io_pads_aon_pmu_vddpaden_o_ie,
output io_pads_aon_pmu_vddpaden_o_pue,
output io_pads_aon_pmu_vddpaden_o_ds,
input io_pads_aon_pmu_padrst_i_ival,
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_padrst_o_oe,
output io_pads_aon_pmu_padrst_o_ie,
output io_pads_aon_pmu_padrst_o_pue,
output io_pads_aon_pmu_padrst_o_ds,
input [`E203_HART_ID_W-1:0] core_mhartid,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
//
// * Bus cmd channel
output sysper_icb_cmd_valid,
input sysper_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysper_icb_cmd_addr,
output sysper_icb_cmd_read,
output [`E203_XLEN-1:0] sysper_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysper_icb_cmd_wmask,
//
// * Bus RSP channel
input sysper_icb_rsp_valid,
output sysper_icb_rsp_ready,
input sysper_icb_rsp_err ,
input [`E203_XLEN-1:0] sysper_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
//
// * Bus cmd channel
output sysfio_icb_cmd_valid,
input sysfio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysfio_icb_cmd_addr,
output sysfio_icb_cmd_read,
output [`E203_XLEN-1:0] sysfio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysfio_icb_cmd_wmask,
//
// * Bus RSP channel
input sysfio_icb_rsp_valid,
output sysfio_icb_rsp_ready,
input sysfio_icb_rsp_err ,
input [`E203_XLEN-1:0] sysfio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
// * Bus cmd channel
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
// * Bus RSP channel
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err ,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
`endif//}
input io_pads_gpio_0_i_ival,
output io_pads_gpio_0_o_oval,
output io_pads_gpio_0_o_oe,
output io_pads_gpio_0_o_ie,
output io_pads_gpio_0_o_pue,
output io_pads_gpio_0_o_ds,
input io_pads_gpio_1_i_ival,
output io_pads_gpio_1_o_oval,
output io_pads_gpio_1_o_oe,
output io_pads_gpio_1_o_ie,
output io_pads_gpio_1_o_pue,
output io_pads_gpio_1_o_ds,
input io_pads_gpio_2_i_ival,
output io_pads_gpio_2_o_oval,
output io_pads_gpio_2_o_oe,
output io_pads_gpio_2_o_ie,
output io_pads_gpio_2_o_pue,
output io_pads_gpio_2_o_ds,
input io_pads_gpio_3_i_ival,
output io_pads_gpio_3_o_oval,
output io_pads_gpio_3_o_oe,
output io_pads_gpio_3_o_ie,
output io_pads_gpio_3_o_pue,
output io_pads_gpio_3_o_ds,
input io_pads_gpio_4_i_ival,
output io_pads_gpio_4_o_oval,
output io_pads_gpio_4_o_oe,
output io_pads_gpio_4_o_ie,
output io_pads_gpio_4_o_pue,
output io_pads_gpio_4_o_ds,
input io_pads_gpio_5_i_ival,
output io_pads_gpio_5_o_oval,
output io_pads_gpio_5_o_oe,
output io_pads_gpio_5_o_ie,
output io_pads_gpio_5_o_pue,
output io_pads_gpio_5_o_ds,
input io_pads_gpio_6_i_ival,
output io_pads_gpio_6_o_oval,
output io_pads_gpio_6_o_oe,
output io_pads_gpio_6_o_ie,
output io_pads_gpio_6_o_pue,
output io_pads_gpio_6_o_ds,
input io_pads_gpio_7_i_ival,
output io_pads_gpio_7_o_oval,
output io_pads_gpio_7_o_oe,
output io_pads_gpio_7_o_ie,
output io_pads_gpio_7_o_pue,
output io_pads_gpio_7_o_ds,
input io_pads_gpio_8_i_ival,
output io_pads_gpio_8_o_oval,
output io_pads_gpio_8_o_oe,
output io_pads_gpio_8_o_ie,
output io_pads_gpio_8_o_pue,
output io_pads_gpio_8_o_ds,
input io_pads_gpio_9_i_ival,
output io_pads_gpio_9_o_oval,
output io_pads_gpio_9_o_oe,
output io_pads_gpio_9_o_ie,
output io_pads_gpio_9_o_pue,
output io_pads_gpio_9_o_ds,
input io_pads_gpio_10_i_ival,
output io_pads_gpio_10_o_oval,
output io_pads_gpio_10_o_oe,
output io_pads_gpio_10_o_ie,
output io_pads_gpio_10_o_pue,
output io_pads_gpio_10_o_ds,
input io_pads_gpio_11_i_ival,
output io_pads_gpio_11_o_oval,
output io_pads_gpio_11_o_oe,
output io_pads_gpio_11_o_ie,
output io_pads_gpio_11_o_pue,
output io_pads_gpio_11_o_ds,
input io_pads_gpio_12_i_ival,
output io_pads_gpio_12_o_oval,
output io_pads_gpio_12_o_oe,
output io_pads_gpio_12_o_ie,
output io_pads_gpio_12_o_pue,
output io_pads_gpio_12_o_ds,
input io_pads_gpio_13_i_ival,
output io_pads_gpio_13_o_oval,
output io_pads_gpio_13_o_oe,
output io_pads_gpio_13_o_ie,
output io_pads_gpio_13_o_pue,
output io_pads_gpio_13_o_ds,
input io_pads_gpio_14_i_ival,
output io_pads_gpio_14_o_oval,
output io_pads_gpio_14_o_oe,
output io_pads_gpio_14_o_ie,
output io_pads_gpio_14_o_pue,
output io_pads_gpio_14_o_ds,
input io_pads_gpio_15_i_ival,
output io_pads_gpio_15_o_oval,
output io_pads_gpio_15_o_oe,
output io_pads_gpio_15_o_ie,
output io_pads_gpio_15_o_pue,
output io_pads_gpio_15_o_ds,
input io_pads_gpio_16_i_ival,
output io_pads_gpio_16_o_oval,
output io_pads_gpio_16_o_oe,
output io_pads_gpio_16_o_ie,
output io_pads_gpio_16_o_pue,
output io_pads_gpio_16_o_ds,
input io_pads_gpio_17_i_ival,
output io_pads_gpio_17_o_oval,
output io_pads_gpio_17_o_oe,
output io_pads_gpio_17_o_ie,
output io_pads_gpio_17_o_pue,
output io_pads_gpio_17_o_ds,
input io_pads_gpio_18_i_ival,
output io_pads_gpio_18_o_oval,
output io_pads_gpio_18_o_oe,
output io_pads_gpio_18_o_ie,
output io_pads_gpio_18_o_pue,
output io_pads_gpio_18_o_ds,
input io_pads_gpio_19_i_ival,
output io_pads_gpio_19_o_oval,
output io_pads_gpio_19_o_oe,
output io_pads_gpio_19_o_ie,
output io_pads_gpio_19_o_pue,
output io_pads_gpio_19_o_ds,
input io_pads_gpio_20_i_ival,
output io_pads_gpio_20_o_oval,
output io_pads_gpio_20_o_oe,
output io_pads_gpio_20_o_ie,
output io_pads_gpio_20_o_pue,
output io_pads_gpio_20_o_ds,
input io_pads_gpio_21_i_ival,
output io_pads_gpio_21_o_oval,
output io_pads_gpio_21_o_oe,
output io_pads_gpio_21_o_ie,
output io_pads_gpio_21_o_pue,
output io_pads_gpio_21_o_ds,
input io_pads_gpio_22_i_ival,
output io_pads_gpio_22_o_oval,
output io_pads_gpio_22_o_oe,
output io_pads_gpio_22_o_ie,
output io_pads_gpio_22_o_pue,
output io_pads_gpio_22_o_ds,
input io_pads_gpio_23_i_ival,
output io_pads_gpio_23_o_oval,
output io_pads_gpio_23_o_oe,
output io_pads_gpio_23_o_ie,
output io_pads_gpio_23_o_pue,
output io_pads_gpio_23_o_ds,
input io_pads_gpio_24_i_ival,
output io_pads_gpio_24_o_oval,
output io_pads_gpio_24_o_oe,
output io_pads_gpio_24_o_ie,
output io_pads_gpio_24_o_pue,
output io_pads_gpio_24_o_ds,
input io_pads_gpio_25_i_ival,
output io_pads_gpio_25_o_oval,
output io_pads_gpio_25_o_oe,
output io_pads_gpio_25_o_ie,
output io_pads_gpio_25_o_pue,
output io_pads_gpio_25_o_ds,
input io_pads_gpio_26_i_ival,
output io_pads_gpio_26_o_oval,
output io_pads_gpio_26_o_oe,
output io_pads_gpio_26_o_ie,
output io_pads_gpio_26_o_pue,
output io_pads_gpio_26_o_ds,
input io_pads_gpio_27_i_ival,
output io_pads_gpio_27_o_oval,
output io_pads_gpio_27_o_oe,
output io_pads_gpio_27_o_ie,
output io_pads_gpio_27_o_pue,
output io_pads_gpio_27_o_ds,
input io_pads_gpio_28_i_ival,
output io_pads_gpio_28_o_oval,
output io_pads_gpio_28_o_oe,
output io_pads_gpio_28_o_ie,
output io_pads_gpio_28_o_pue,
output io_pads_gpio_28_o_ds,
input io_pads_gpio_29_i_ival,
output io_pads_gpio_29_o_oval,
output io_pads_gpio_29_o_oe,
output io_pads_gpio_29_o_ie,
output io_pads_gpio_29_o_pue,
output io_pads_gpio_29_o_ds,
input io_pads_gpio_30_i_ival,
output io_pads_gpio_30_o_oval,
output io_pads_gpio_30_o_oe,
output io_pads_gpio_30_o_ie,
output io_pads_gpio_30_o_pue,
output io_pads_gpio_30_o_ds,
input io_pads_gpio_31_i_ival,
output io_pads_gpio_31_o_oval,
output io_pads_gpio_31_o_oe,
output io_pads_gpio_31_o_ie,
output io_pads_gpio_31_o_pue,
output io_pads_gpio_31_o_ds,
input io_pads_qspi_sck_i_ival,
output io_pads_qspi_sck_o_oval,
output io_pads_qspi_sck_o_oe,
output io_pads_qspi_sck_o_ie,
output io_pads_qspi_sck_o_pue,
output io_pads_qspi_sck_o_ds,
input io_pads_qspi_dq_0_i_ival,
output io_pads_qspi_dq_0_o_oval,
output io_pads_qspi_dq_0_o_oe,
output io_pads_qspi_dq_0_o_ie,
output io_pads_qspi_dq_0_o_pue,
output io_pads_qspi_dq_0_o_ds,
input io_pads_qspi_dq_1_i_ival,
output io_pads_qspi_dq_1_o_oval,
output io_pads_qspi_dq_1_o_oe,
output io_pads_qspi_dq_1_o_ie,
output io_pads_qspi_dq_1_o_pue,
output io_pads_qspi_dq_1_o_ds,
input io_pads_qspi_dq_2_i_ival,
output io_pads_qspi_dq_2_o_oval,
output io_pads_qspi_dq_2_o_oe,
output io_pads_qspi_dq_2_o_ie,
output io_pads_qspi_dq_2_o_pue,
output io_pads_qspi_dq_2_o_ds,
input io_pads_qspi_dq_3_i_ival,
output io_pads_qspi_dq_3_o_oval,
output io_pads_qspi_dq_3_o_oe,
output io_pads_qspi_dq_3_o_ie,
output io_pads_qspi_dq_3_o_pue,
output io_pads_qspi_dq_3_o_ds,
input io_pads_qspi_cs_0_i_ival,
output io_pads_qspi_cs_0_o_oval,
output io_pads_qspi_cs_0_o_oe,
output io_pads_qspi_cs_0_o_ie,
output io_pads_qspi_cs_0_o_pue,
output io_pads_qspi_cs_0_o_ds,
input io_pads_jtag_TCK_i_ival,
output io_pads_jtag_TCK_o_oval,
output io_pads_jtag_TCK_o_oe,
output io_pads_jtag_TCK_o_ie,
output io_pads_jtag_TCK_o_pue,
output io_pads_jtag_TCK_o_ds,
input io_pads_jtag_TMS_i_ival,
output io_pads_jtag_TMS_o_oval,
output io_pads_jtag_TMS_o_oe,
output io_pads_jtag_TMS_o_ie,
output io_pads_jtag_TMS_o_pue,
output io_pads_jtag_TMS_o_ds,
input io_pads_jtag_TDI_i_ival,
output io_pads_jtag_TDI_o_oval,
output io_pads_jtag_TDI_o_oe,
output io_pads_jtag_TDI_o_ie,
output io_pads_jtag_TDI_o_pue,
output io_pads_jtag_TDI_o_ds,
input io_pads_jtag_TDO_i_ival,
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
output io_pads_jtag_TDO_o_ie,
output io_pads_jtag_TDO_o_pue,
output io_pads_jtag_TDO_o_ds,
input io_pads_jtag_TRST_n_i_ival,
output io_pads_jtag_TRST_n_o_oval,
output io_pads_jtag_TRST_n_o_oe,
output io_pads_jtag_TRST_n_o_ie,
output io_pads_jtag_TRST_n_o_pue,
output io_pads_jtag_TRST_n_o_ds,
input test_iso_override,
input test_mode
);
wire hfclk;// The PLL generated high-speed clock
wire hfclkrst;// The reset signal to disable PLL
wire corerst;
///////////////////////////////////////
wire [`E203_HART_NUM-1:0] dbg_irq;
wire [`E203_PC_SIZE-1:0] cmt_dpc;
wire cmt_dpc_ena;
wire [3-1:0] cmt_dcause;
wire cmt_dcause_ena;
wire dbg_irq_r;
wire wr_dcsr_ena;
wire wr_dpc_ena ;
wire wr_dscratch_ena;
wire [32-1:0] wr_csr_nxt;
wire [32-1:0] dcsr_r ;
wire [`E203_PC_SIZE-1:0] dpc_r ;
wire [32-1:0] dscratch_r;
wire dbg_mode;
wire dbg_halt_r;
wire dbg_step_r;
wire dbg_ebreakm_r;
wire dbg_stopcycle;
wire inspect_mode;
wire inspect_por_rst;
wire inspect_32k_clk;
wire inspect_pc_29b;
wire inspect_dbg_irq;
wire inspect_jtag_clk;
wire core_csr_clk;
wire dm_icb_cmd_valid;
wire dm_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr;
wire dm_icb_cmd_read;
wire [`E203_XLEN-1:0] dm_icb_cmd_wdata;
//
wire dm_icb_rsp_valid;
wire dm_icb_rsp_ready;
wire [`E203_XLEN-1:0] dm_icb_rsp_rdata;
wire aon_wdg_irq_a ;
wire aon_rtc_irq_a ;
wire aon_rtcToggle_a ;
wire aon_icb_cmd_valid;
wire aon_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] aon_icb_cmd_addr;
wire aon_icb_cmd_read;
wire [`E203_XLEN-1:0] aon_icb_cmd_wdata;
//
wire aon_icb_rsp_valid;
wire aon_icb_rsp_ready;
wire [`E203_XLEN-1:0] aon_icb_rsp_rdata;
wire [`E203_PC_SIZE-1:0] pc_rtvec;
e203_subsys_main u_e203_subsys_main(
.pc_rtvec (pc_rtvec),
.inspect_mode (inspect_mode ),
.inspect_por_rst (inspect_por_rst),
.inspect_32k_clk (inspect_32k_clk),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_dbg_irq (inspect_dbg_irq ),
.inspect_jtag_clk(inspect_jtag_clk),
.core_csr_clk (core_csr_clk ),
.hfextclk (hfextclk),
.hfxoscen (hfxoscen),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.core_mhartid (core_mhartid),
.dbg_irq_a (dbg_irq[0]),
.aon_wdg_irq_a (aon_wdg_irq_a ),
.aon_rtc_irq_a (aon_rtc_irq_a ),
.aon_rtcToggle_a (aon_rtcToggle_a ),
.aon_icb_cmd_valid (aon_icb_cmd_valid ),
.aon_icb_cmd_ready (aon_icb_cmd_ready ),
.aon_icb_cmd_addr (aon_icb_cmd_addr ),
.aon_icb_cmd_read (aon_icb_cmd_read ),
.aon_icb_cmd_wdata (aon_icb_cmd_wdata ),
.aon_icb_rsp_valid (aon_icb_rsp_valid ),
.aon_icb_rsp_ready (aon_icb_rsp_ready ),
.aon_icb_rsp_err (1'b0 ),
.aon_icb_rsp_rdata (aon_icb_rsp_rdata ),
.dm_icb_cmd_valid (dm_icb_cmd_valid),
.dm_icb_cmd_ready (dm_icb_cmd_ready),
.dm_icb_cmd_addr (dm_icb_cmd_addr ),
.dm_icb_cmd_read (dm_icb_cmd_read ),
.dm_icb_cmd_wdata (dm_icb_cmd_wdata),
.dm_icb_rsp_valid (dm_icb_rsp_valid),
.dm_icb_rsp_ready (dm_icb_rsp_ready),
.dm_icb_rsp_rdata (dm_icb_rsp_rdata),
.io_pads_gpio_0_i_ival (io_pads_gpio_0_i_ival),
.io_pads_gpio_0_o_oval (io_pads_gpio_0_o_oval),
.io_pads_gpio_0_o_oe (io_pads_gpio_0_o_oe),
.io_pads_gpio_0_o_ie (io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_pue (io_pads_gpio_0_o_pue),
.io_pads_gpio_0_o_ds (io_pads_gpio_0_o_ds),
.io_pads_gpio_1_i_ival (io_pads_gpio_1_i_ival),
.io_pads_gpio_1_o_oval (io_pads_gpio_1_o_oval),
.io_pads_gpio_1_o_oe (io_pads_gpio_1_o_oe),
.io_pads_gpio_1_o_ie (io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_pue (io_pads_gpio_1_o_pue),
.io_pads_gpio_1_o_ds (io_pads_gpio_1_o_ds),
.io_pads_gpio_2_i_ival (io_pads_gpio_2_i_ival),
.io_pads_gpio_2_o_oval (io_pads_gpio_2_o_oval),
.io_pads_gpio_2_o_oe (io_pads_gpio_2_o_oe),
.io_pads_gpio_2_o_ie (io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_pue (io_pads_gpio_2_o_pue),
.io_pads_gpio_2_o_ds (io_pads_gpio_2_o_ds),
.io_pads_gpio_3_i_ival (io_pads_gpio_3_i_ival),
.io_pads_gpio_3_o_oval (io_pads_gpio_3_o_oval),
.io_pads_gpio_3_o_oe (io_pads_gpio_3_o_oe),
.io_pads_gpio_3_o_ie (io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_pue (io_pads_gpio_3_o_pue),
.io_pads_gpio_3_o_ds (io_pads_gpio_3_o_ds),
.io_pads_gpio_4_i_ival (io_pads_gpio_4_i_ival),
.io_pads_gpio_4_o_oval (io_pads_gpio_4_o_oval),
.io_pads_gpio_4_o_oe (io_pads_gpio_4_o_oe),
.io_pads_gpio_4_o_ie (io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_pue (io_pads_gpio_4_o_pue),
.io_pads_gpio_4_o_ds (io_pads_gpio_4_o_ds),
.io_pads_gpio_5_i_ival (io_pads_gpio_5_i_ival),
.io_pads_gpio_5_o_oval (io_pads_gpio_5_o_oval),
.io_pads_gpio_5_o_oe (io_pads_gpio_5_o_oe),
.io_pads_gpio_5_o_ie (io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_pue (io_pads_gpio_5_o_pue),
.io_pads_gpio_5_o_ds (io_pads_gpio_5_o_ds),
.io_pads_gpio_6_i_ival (io_pads_gpio_6_i_ival),
.io_pads_gpio_6_o_oval (io_pads_gpio_6_o_oval),
.io_pads_gpio_6_o_oe (io_pads_gpio_6_o_oe),
.io_pads_gpio_6_o_ie (io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_pue (io_pads_gpio_6_o_pue),
.io_pads_gpio_6_o_ds (io_pads_gpio_6_o_ds),
.io_pads_gpio_7_i_ival (io_pads_gpio_7_i_ival),
.io_pads_gpio_7_o_oval (io_pads_gpio_7_o_oval),
.io_pads_gpio_7_o_oe (io_pads_gpio_7_o_oe),
.io_pads_gpio_7_o_ie (io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_pue (io_pads_gpio_7_o_pue),
.io_pads_gpio_7_o_ds (io_pads_gpio_7_o_ds),
.io_pads_gpio_8_i_ival (io_pads_gpio_8_i_ival),
.io_pads_gpio_8_o_oval (io_pads_gpio_8_o_oval),
.io_pads_gpio_8_o_oe (io_pads_gpio_8_o_oe),
.io_pads_gpio_8_o_ie (io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_pue (io_pads_gpio_8_o_pue),
.io_pads_gpio_8_o_ds (io_pads_gpio_8_o_ds),
.io_pads_gpio_9_i_ival (io_pads_gpio_9_i_ival),
.io_pads_gpio_9_o_oval (io_pads_gpio_9_o_oval),
.io_pads_gpio_9_o_oe (io_pads_gpio_9_o_oe),
.io_pads_gpio_9_o_ie (io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_pue (io_pads_gpio_9_o_pue),
.io_pads_gpio_9_o_ds (io_pads_gpio_9_o_ds),
.io_pads_gpio_10_i_ival (io_pads_gpio_10_i_ival),
.io_pads_gpio_10_o_oval (io_pads_gpio_10_o_oval),
.io_pads_gpio_10_o_oe (io_pads_gpio_10_o_oe),
.io_pads_gpio_10_o_ie (io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_pue (io_pads_gpio_10_o_pue),
.io_pads_gpio_10_o_ds (io_pads_gpio_10_o_ds),
.io_pads_gpio_11_i_ival (io_pads_gpio_11_i_ival),
.io_pads_gpio_11_o_oval (io_pads_gpio_11_o_oval),
.io_pads_gpio_11_o_oe (io_pads_gpio_11_o_oe),
.io_pads_gpio_11_o_ie (io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_pue (io_pads_gpio_11_o_pue),
.io_pads_gpio_11_o_ds (io_pads_gpio_11_o_ds),
.io_pads_gpio_12_i_ival (io_pads_gpio_12_i_ival),
.io_pads_gpio_12_o_oval (io_pads_gpio_12_o_oval),
.io_pads_gpio_12_o_oe (io_pads_gpio_12_o_oe),
.io_pads_gpio_12_o_ie (io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_pue (io_pads_gpio_12_o_pue),
.io_pads_gpio_12_o_ds (io_pads_gpio_12_o_ds),
.io_pads_gpio_13_i_ival (io_pads_gpio_13_i_ival),
.io_pads_gpio_13_o_oval (io_pads_gpio_13_o_oval),
.io_pads_gpio_13_o_oe (io_pads_gpio_13_o_oe),
.io_pads_gpio_13_o_ie (io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_pue (io_pads_gpio_13_o_pue),
.io_pads_gpio_13_o_ds (io_pads_gpio_13_o_ds),
.io_pads_gpio_14_i_ival (io_pads_gpio_14_i_ival),
.io_pads_gpio_14_o_oval (io_pads_gpio_14_o_oval),
.io_pads_gpio_14_o_oe (io_pads_gpio_14_o_oe),
.io_pads_gpio_14_o_ie (io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_pue (io_pads_gpio_14_o_pue),
.io_pads_gpio_14_o_ds (io_pads_gpio_14_o_ds),
.io_pads_gpio_15_i_ival (io_pads_gpio_15_i_ival),
.io_pads_gpio_15_o_oval (io_pads_gpio_15_o_oval),
.io_pads_gpio_15_o_oe (io_pads_gpio_15_o_oe),
.io_pads_gpio_15_o_ie (io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_pue (io_pads_gpio_15_o_pue),
.io_pads_gpio_15_o_ds (io_pads_gpio_15_o_ds),
.io_pads_gpio_16_i_ival (io_pads_gpio_16_i_ival),
.io_pads_gpio_16_o_oval (io_pads_gpio_16_o_oval),
.io_pads_gpio_16_o_oe (io_pads_gpio_16_o_oe),
.io_pads_gpio_16_o_ie (io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_pue (io_pads_gpio_16_o_pue),
.io_pads_gpio_16_o_ds (io_pads_gpio_16_o_ds),
.io_pads_gpio_17_i_ival (io_pads_gpio_17_i_ival),
.io_pads_gpio_17_o_oval (io_pads_gpio_17_o_oval),
.io_pads_gpio_17_o_oe (io_pads_gpio_17_o_oe),
.io_pads_gpio_17_o_ie (io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_pue (io_pads_gpio_17_o_pue),
.io_pads_gpio_17_o_ds (io_pads_gpio_17_o_ds),
.io_pads_gpio_18_i_ival (io_pads_gpio_18_i_ival),
.io_pads_gpio_18_o_oval (io_pads_gpio_18_o_oval),
.io_pads_gpio_18_o_oe (io_pads_gpio_18_o_oe),
.io_pads_gpio_18_o_ie (io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_pue (io_pads_gpio_18_o_pue),
.io_pads_gpio_18_o_ds (io_pads_gpio_18_o_ds),
.io_pads_gpio_19_i_ival (io_pads_gpio_19_i_ival),
.io_pads_gpio_19_o_oval (io_pads_gpio_19_o_oval),
.io_pads_gpio_19_o_oe (io_pads_gpio_19_o_oe),
.io_pads_gpio_19_o_ie (io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_pue (io_pads_gpio_19_o_pue),
.io_pads_gpio_19_o_ds (io_pads_gpio_19_o_ds),
.io_pads_gpio_20_i_ival (io_pads_gpio_20_i_ival),
.io_pads_gpio_20_o_oval (io_pads_gpio_20_o_oval),
.io_pads_gpio_20_o_oe (io_pads_gpio_20_o_oe),
.io_pads_gpio_20_o_ie (io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_pue (io_pads_gpio_20_o_pue),
.io_pads_gpio_20_o_ds (io_pads_gpio_20_o_ds),
.io_pads_gpio_21_i_ival (io_pads_gpio_21_i_ival),
.io_pads_gpio_21_o_oval (io_pads_gpio_21_o_oval),
.io_pads_gpio_21_o_oe (io_pads_gpio_21_o_oe),
.io_pads_gpio_21_o_ie (io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_pue (io_pads_gpio_21_o_pue),
.io_pads_gpio_21_o_ds (io_pads_gpio_21_o_ds),
.io_pads_gpio_22_i_ival (io_pads_gpio_22_i_ival),
.io_pads_gpio_22_o_oval (io_pads_gpio_22_o_oval),
.io_pads_gpio_22_o_oe (io_pads_gpio_22_o_oe),
.io_pads_gpio_22_o_ie (io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_pue (io_pads_gpio_22_o_pue),
.io_pads_gpio_22_o_ds (io_pads_gpio_22_o_ds),
.io_pads_gpio_23_i_ival (io_pads_gpio_23_i_ival),
.io_pads_gpio_23_o_oval (io_pads_gpio_23_o_oval),
.io_pads_gpio_23_o_oe (io_pads_gpio_23_o_oe),
.io_pads_gpio_23_o_ie (io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_pue (io_pads_gpio_23_o_pue),
.io_pads_gpio_23_o_ds (io_pads_gpio_23_o_ds),
.io_pads_gpio_24_i_ival (io_pads_gpio_24_i_ival),
.io_pads_gpio_24_o_oval (io_pads_gpio_24_o_oval),
.io_pads_gpio_24_o_oe (io_pads_gpio_24_o_oe),
.io_pads_gpio_24_o_ie (io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_pue (io_pads_gpio_24_o_pue),
.io_pads_gpio_24_o_ds (io_pads_gpio_24_o_ds),
.io_pads_gpio_25_i_ival (io_pads_gpio_25_i_ival),
.io_pads_gpio_25_o_oval (io_pads_gpio_25_o_oval),
.io_pads_gpio_25_o_oe (io_pads_gpio_25_o_oe),
.io_pads_gpio_25_o_ie (io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_pue (io_pads_gpio_25_o_pue),
.io_pads_gpio_25_o_ds (io_pads_gpio_25_o_ds),
.io_pads_gpio_26_i_ival (io_pads_gpio_26_i_ival),
.io_pads_gpio_26_o_oval (io_pads_gpio_26_o_oval),
.io_pads_gpio_26_o_oe (io_pads_gpio_26_o_oe),
.io_pads_gpio_26_o_ie (io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_pue (io_pads_gpio_26_o_pue),
.io_pads_gpio_26_o_ds (io_pads_gpio_26_o_ds),
.io_pads_gpio_27_i_ival (io_pads_gpio_27_i_ival),
.io_pads_gpio_27_o_oval (io_pads_gpio_27_o_oval),
.io_pads_gpio_27_o_oe (io_pads_gpio_27_o_oe),
.io_pads_gpio_27_o_ie (io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_pue (io_pads_gpio_27_o_pue),
.io_pads_gpio_27_o_ds (io_pads_gpio_27_o_ds),
.io_pads_gpio_28_i_ival (io_pads_gpio_28_i_ival),
.io_pads_gpio_28_o_oval (io_pads_gpio_28_o_oval),
.io_pads_gpio_28_o_oe (io_pads_gpio_28_o_oe),
.io_pads_gpio_28_o_ie (io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_pue (io_pads_gpio_28_o_pue),
.io_pads_gpio_28_o_ds (io_pads_gpio_28_o_ds),
.io_pads_gpio_29_i_ival (io_pads_gpio_29_i_ival),
.io_pads_gpio_29_o_oval (io_pads_gpio_29_o_oval),
.io_pads_gpio_29_o_oe (io_pads_gpio_29_o_oe),
.io_pads_gpio_29_o_ie (io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_pue (io_pads_gpio_29_o_pue),
.io_pads_gpio_29_o_ds (io_pads_gpio_29_o_ds),
.io_pads_gpio_30_i_ival (io_pads_gpio_30_i_ival),
.io_pads_gpio_30_o_oval (io_pads_gpio_30_o_oval),
.io_pads_gpio_30_o_oe (io_pads_gpio_30_o_oe),
.io_pads_gpio_30_o_ie (io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_pue (io_pads_gpio_30_o_pue),
.io_pads_gpio_30_o_ds (io_pads_gpio_30_o_ds),
.io_pads_gpio_31_i_ival (io_pads_gpio_31_i_ival),
.io_pads_gpio_31_o_oval (io_pads_gpio_31_o_oval),
.io_pads_gpio_31_o_oe (io_pads_gpio_31_o_oe),
.io_pads_gpio_31_o_ie (io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_pue (io_pads_gpio_31_o_pue),
.io_pads_gpio_31_o_ds (io_pads_gpio_31_o_ds),
.io_pads_qspi_sck_i_ival (io_pads_qspi_sck_i_ival ),
.io_pads_qspi_sck_o_oval (io_pads_qspi_sck_o_oval ),
.io_pads_qspi_sck_o_oe (io_pads_qspi_sck_o_oe ),
.io_pads_qspi_sck_o_ie (io_pads_qspi_sck_o_ie ),
.io_pads_qspi_sck_o_pue (io_pads_qspi_sck_o_pue ),
.io_pads_qspi_sck_o_ds (io_pads_qspi_sck_o_ds ),
.io_pads_qspi_dq_0_i_ival (io_pads_qspi_dq_0_i_ival ),
.io_pads_qspi_dq_0_o_oval (io_pads_qspi_dq_0_o_oval ),
.io_pads_qspi_dq_0_o_oe (io_pads_qspi_dq_0_o_oe ),
.io_pads_qspi_dq_0_o_ie (io_pads_qspi_dq_0_o_ie ),
.io_pads_qspi_dq_0_o_pue (io_pads_qspi_dq_0_o_pue ),
.io_pads_qspi_dq_0_o_ds (io_pads_qspi_dq_0_o_ds ),
.io_pads_qspi_dq_1_i_ival (io_pads_qspi_dq_1_i_ival ),
.io_pads_qspi_dq_1_o_oval (io_pads_qspi_dq_1_o_oval ),
.io_pads_qspi_dq_1_o_oe (io_pads_qspi_dq_1_o_oe ),
.io_pads_qspi_dq_1_o_ie (io_pads_qspi_dq_1_o_ie ),
.io_pads_qspi_dq_1_o_pue (io_pads_qspi_dq_1_o_pue ),
.io_pads_qspi_dq_1_o_ds (io_pads_qspi_dq_1_o_ds ),
.io_pads_qspi_dq_2_i_ival (io_pads_qspi_dq_2_i_ival ),
.io_pads_qspi_dq_2_o_oval (io_pads_qspi_dq_2_o_oval ),
.io_pads_qspi_dq_2_o_oe (io_pads_qspi_dq_2_o_oe ),
.io_pads_qspi_dq_2_o_ie (io_pads_qspi_dq_2_o_ie ),
.io_pads_qspi_dq_2_o_pue (io_pads_qspi_dq_2_o_pue ),
.io_pads_qspi_dq_2_o_ds (io_pads_qspi_dq_2_o_ds ),
.io_pads_qspi_dq_3_i_ival (io_pads_qspi_dq_3_i_ival ),
.io_pads_qspi_dq_3_o_oval (io_pads_qspi_dq_3_o_oval ),
.io_pads_qspi_dq_3_o_oe (io_pads_qspi_dq_3_o_oe ),
.io_pads_qspi_dq_3_o_ie (io_pads_qspi_dq_3_o_ie ),
.io_pads_qspi_dq_3_o_pue (io_pads_qspi_dq_3_o_pue ),
.io_pads_qspi_dq_3_o_ds (io_pads_qspi_dq_3_o_ds ),
.io_pads_qspi_cs_0_i_ival (io_pads_qspi_cs_0_i_ival ),
.io_pads_qspi_cs_0_o_oval (io_pads_qspi_cs_0_o_oval ),
.io_pads_qspi_cs_0_o_oe (io_pads_qspi_cs_0_o_oe ),
.io_pads_qspi_cs_0_o_ie (io_pads_qspi_cs_0_o_ie ),
.io_pads_qspi_cs_0_o_pue (io_pads_qspi_cs_0_o_pue ),
.io_pads_qspi_cs_0_o_ds (io_pads_qspi_cs_0_o_ds ),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_addr (sysper_icb_cmd_addr ),
.sysper_icb_cmd_read (sysper_icb_cmd_read ),
.sysper_icb_cmd_wdata (sysper_icb_cmd_wdata),
.sysper_icb_cmd_wmask (sysper_icb_cmd_wmask),
.sysper_icb_rsp_valid (sysper_icb_rsp_valid),
.sysper_icb_rsp_ready (sysper_icb_rsp_ready),
.sysper_icb_rsp_err (sysper_icb_rsp_err ),
.sysper_icb_rsp_rdata (sysper_icb_rsp_rdata),
.sysfio_icb_cmd_valid (sysfio_icb_cmd_valid),
.sysfio_icb_cmd_ready (sysfio_icb_cmd_ready),
.sysfio_icb_cmd_addr (sysfio_icb_cmd_addr ),
.sysfio_icb_cmd_read (sysfio_icb_cmd_read ),
.sysfio_icb_cmd_wdata (sysfio_icb_cmd_wdata),
.sysfio_icb_cmd_wmask (sysfio_icb_cmd_wmask),
.sysfio_icb_rsp_valid (sysfio_icb_rsp_valid),
.sysfio_icb_rsp_ready (sysfio_icb_rsp_ready),
.sysfio_icb_rsp_err (sysfio_icb_rsp_err ),
.sysfio_icb_rsp_rdata (sysfio_icb_rsp_rdata),
.sysmem_icb_cmd_valid (sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready (sysmem_icb_cmd_ready),
.sysmem_icb_cmd_addr (sysmem_icb_cmd_addr ),
.sysmem_icb_cmd_read (sysmem_icb_cmd_read ),
.sysmem_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.sysmem_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.sysmem_icb_rsp_valid (sysmem_icb_rsp_valid),
.sysmem_icb_rsp_ready (sysmem_icb_rsp_ready),
.sysmem_icb_rsp_err (sysmem_icb_rsp_err ),
.sysmem_icb_rsp_rdata (sysmem_icb_rsp_rdata),
.test_mode (test_mode),
.hfclk (hfclk ),
.hfclkrst (hfclkrst),
.corerst (corerst)
);
sirv_debug_module # (
`ifdef E203_DEBUG_HAS_JTAG //{
.SUPPORT_JTAG_DTM (1),
`else//}{
.SUPPORT_JTAG_DTM (0),
`endif//}
.ASYNC_FF_LEVELS (`E203_ASYNC_FF_LEVELS),
.HART_NUM (`E203_HART_NUM),
.PC_SIZE (`E203_PC_SIZE),
.HART_ID_W(`E203_HART_ID_W)
) u_sirv_debug_module(
.inspect_jtag_clk (inspect_jtag_clk),
.test_mode (test_mode ),
.core_csr_clk (core_csr_clk),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.io_pads_jtag_TCK_i_ival (io_pads_jtag_TCK_i_ival ),
.io_pads_jtag_TCK_o_oval (io_pads_jtag_TCK_o_oval ),
.io_pads_jtag_TCK_o_oe (io_pads_jtag_TCK_o_oe ),
.io_pads_jtag_TCK_o_ie (io_pads_jtag_TCK_o_ie ),
.io_pads_jtag_TCK_o_pue (io_pads_jtag_TCK_o_pue ),
.io_pads_jtag_TCK_o_ds (io_pads_jtag_TCK_o_ds ),
.io_pads_jtag_TMS_i_ival (io_pads_jtag_TMS_i_ival ),
.io_pads_jtag_TMS_o_oval (io_pads_jtag_TMS_o_oval ),
.io_pads_jtag_TMS_o_oe (io_pads_jtag_TMS_o_oe ),
.io_pads_jtag_TMS_o_ie (io_pads_jtag_TMS_o_ie ),
.io_pads_jtag_TMS_o_pue (io_pads_jtag_TMS_o_pue ),
.io_pads_jtag_TMS_o_ds (io_pads_jtag_TMS_o_ds ),
.io_pads_jtag_TDI_i_ival (io_pads_jtag_TDI_i_ival ),
.io_pads_jtag_TDI_o_oval (io_pads_jtag_TDI_o_oval ),
.io_pads_jtag_TDI_o_oe (io_pads_jtag_TDI_o_oe ),
.io_pads_jtag_TDI_o_ie (io_pads_jtag_TDI_o_ie ),
.io_pads_jtag_TDI_o_pue (io_pads_jtag_TDI_o_pue ),
.io_pads_jtag_TDI_o_ds (io_pads_jtag_TDI_o_ds ),
.io_pads_jtag_TDO_i_ival (io_pads_jtag_TDO_i_ival ),
.io_pads_jtag_TDO_o_oval (io_pads_jtag_TDO_o_oval ),
.io_pads_jtag_TDO_o_oe (io_pads_jtag_TDO_o_oe ),
.io_pads_jtag_TDO_o_ie (io_pads_jtag_TDO_o_ie ),
.io_pads_jtag_TDO_o_pue (io_pads_jtag_TDO_o_pue ),
.io_pads_jtag_TDO_o_ds (io_pads_jtag_TDO_o_ds ),
.io_pads_jtag_TRST_n_i_ival (io_pads_jtag_TRST_n_i_ival ),
.io_pads_jtag_TRST_n_o_oval (io_pads_jtag_TRST_n_o_oval ),
.io_pads_jtag_TRST_n_o_oe (io_pads_jtag_TRST_n_o_oe ),
.io_pads_jtag_TRST_n_o_ie (io_pads_jtag_TRST_n_o_ie ),
.io_pads_jtag_TRST_n_o_pue (io_pads_jtag_TRST_n_o_pue ),
.io_pads_jtag_TRST_n_o_ds (io_pads_jtag_TRST_n_o_ds ),
.i_icb_cmd_valid (dm_icb_cmd_valid),
.i_icb_cmd_ready (dm_icb_cmd_ready),
.i_icb_cmd_addr (dm_icb_cmd_addr[11:0] ),
.i_icb_cmd_read (dm_icb_cmd_read ),
.i_icb_cmd_wdata (dm_icb_cmd_wdata),
.i_icb_rsp_valid (dm_icb_rsp_valid),
.i_icb_rsp_ready (dm_icb_rsp_ready),
.i_icb_rsp_rdata (dm_icb_rsp_rdata),
.o_dbg_irq (dbg_irq),
.o_ndreset (),
.o_fullreset (),
.hfclk (hfclk),
.corerst (corerst)
);
sirv_aon_top u_sirv_aon_top(
.pc_rtvec (pc_rtvec),
.jtagpwd_iso (),// Currently not used
.inspect_mode (inspect_mode ),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_por_rst (inspect_por_rst ),
.inspect_32k_clk (inspect_32k_clk ),
.inspect_dbg_irq (inspect_dbg_irq ),
.i_icb_cmd_valid (aon_icb_cmd_valid),
.i_icb_cmd_ready (aon_icb_cmd_ready),
.i_icb_cmd_addr (aon_icb_cmd_addr ),
.i_icb_cmd_read (aon_icb_cmd_read ),
.i_icb_cmd_wdata (aon_icb_cmd_wdata),
.i_icb_rsp_valid (aon_icb_rsp_valid),
.i_icb_rsp_ready (aon_icb_rsp_ready),
.i_icb_rsp_rdata (aon_icb_rsp_rdata),
.aon_wdg_irq (aon_wdg_irq_a ),
.aon_rtc_irq (aon_rtc_irq_a ),
.aon_rtcToggle (aon_rtcToggle_a ),
.test_mode (test_mode ),
.test_iso_override (test_iso_override ),
.lfextclk (lfextclk),
.lfxoscen (lfxoscen),
.io_pads_aon_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_aon_erst_n_o_oval (io_pads_aon_erst_n_o_oval ),
.io_pads_aon_erst_n_o_oe (io_pads_aon_erst_n_o_oe ),
.io_pads_aon_erst_n_o_ie (io_pads_aon_erst_n_o_ie ),
.io_pads_aon_erst_n_o_pue (io_pads_aon_erst_n_o_pue ),
.io_pads_aon_erst_n_o_ds (io_pads_aon_erst_n_o_ds ),
.io_pads_aon_pmu_vddpaden_i_ival (io_pads_aon_pmu_vddpaden_i_ival ),
.io_pads_aon_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_vddpaden_o_oe (io_pads_aon_pmu_vddpaden_o_oe ),
.io_pads_aon_pmu_vddpaden_o_ie (io_pads_aon_pmu_vddpaden_o_ie ),
.io_pads_aon_pmu_vddpaden_o_pue (io_pads_aon_pmu_vddpaden_o_pue ),
.io_pads_aon_pmu_vddpaden_o_ds (io_pads_aon_pmu_vddpaden_o_ds ),
.io_pads_aon_pmu_dwakeup_n_i_ival (io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval (io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_aon_pmu_dwakeup_n_o_oe (io_pads_aon_pmu_dwakeup_n_o_oe ),
.io_pads_aon_pmu_dwakeup_n_o_ie (io_pads_aon_pmu_dwakeup_n_o_ie ),
.io_pads_aon_pmu_dwakeup_n_o_pue (io_pads_aon_pmu_dwakeup_n_o_pue ),
.io_pads_aon_pmu_dwakeup_n_o_ds (io_pads_aon_pmu_dwakeup_n_o_ds ),
.io_pads_aon_pmu_padrst_i_ival (io_pads_aon_pmu_padrst_i_ival ),
.io_pads_aon_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_aon_pmu_padrst_o_oe (io_pads_aon_pmu_padrst_o_oe ),
.io_pads_aon_pmu_padrst_o_ie (io_pads_aon_pmu_padrst_o_ie ),
.io_pads_aon_pmu_padrst_o_pue (io_pads_aon_pmu_padrst_o_pue ),
.io_pads_aon_pmu_padrst_o_ds (io_pads_aon_pmu_padrst_o_ds ),
.io_pads_jtagpwd_n_i_ival (1'b1),// Currently not used
.io_pads_jtagpwd_n_o_oval (),
.io_pads_jtagpwd_n_o_oe (),
.io_pads_jtagpwd_n_o_ie (),
.io_pads_jtagpwd_n_o_pue (),
.io_pads_jtagpwd_n_o_ds (),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (io_pads_bootrom_n_o_oval),
.io_pads_bootrom_n_o_oe (io_pads_bootrom_n_o_oe ),
.io_pads_bootrom_n_o_ie (io_pads_bootrom_n_o_ie ),
.io_pads_bootrom_n_o_pue (io_pads_bootrom_n_o_pue ),
.io_pads_bootrom_n_o_ds (io_pads_bootrom_n_o_ds ),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival),
.hfclkrst (hfclkrst),
.corerst (corerst)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_V |
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module u1plus_core
#(
parameter NUM_RX_DSPS = 2,
parameter CTRL_ACK_SID = 20, //needed for reply
parameter DSP_TX_FIFOSIZE = 10, //4K MTU
parameter DSP_RX_FIFOSIZE = 10, //4K MTU
parameter DSP_RX_XTRA_FIFOSIZE = 11,
parameter DSP_TX_XTRA_FIFOSIZE = 11,
parameter USE_PACKET_PADDER = 0
)
(input clk, input reset,
output [31:0] debug, output [1:0] debug_clk,
// Host Interface
input [35:0] tx_data, input tx_src_rdy, output tx_dst_rdy,
output [35:0] rx_data, output rx_src_rdy, input rx_dst_rdy,
input [35:0] ctrl_data, input ctrl_src_rdy, output ctrl_dst_rdy,
output [35:0] resp_data, output resp_src_rdy, input resp_dst_rdy,
output dsp_rx_run, output dsp_tx_run, output clock_sync,
inout db_sda, inout db_scl,
output sclk, output [7:0] sen, output mosi, input miso,
inout [15:0] io_tx, inout [15:0] io_rx,
output [13:0] tx_i, output [13:0] tx_q,
input [11:0] rx_i, input [11:0] rx_q,
input pps_in
);
localparam SR_MISC = 0; // 5
localparam SR_USER_REGS = 5; // 2
localparam SR_PADDER = 10; // 2
localparam SR_TX_CTRL = 32; // 6
localparam SR_TX_DSP = 40; // 5
localparam SR_TX_FE = 48; // 5
localparam SR_RX_CTRL0 = 96; // 9
localparam SR_RX_DSP0 = 106; // 7
localparam SR_RX_FE = 114; // 5
localparam SR_RX_CTRL1 = 128; // 9
localparam SR_RX_DSP1 = 138; // 7
localparam SR_TIME64 = 192; // 6
localparam SR_SPI = 208; // 3
localparam SR_I2C = 216; // 1
localparam SR_GPIO = 224; // 5
//compatibility number -> increment when the fpga has been sufficiently altered
localparam compat_num = {16'd11, 16'd1}; //major, minor
//assign run signals used for ATR logic
wire [NUM_RX_DSPS-1:0] run_rx_n;
wire run_tx;
wire run_rx = |(run_rx_n);
assign dsp_rx_run = run_rx;
assign dsp_tx_run = run_tx;
//shared time core signals
wire [63:0] vita_time, vita_time_pps;
//shared settings bus signals
wire set_stb, set_stb_user;
wire [31:0] set_data, set_data_user;
wire [7:0] set_addr, set_addr_user;
//shared SPI core signals
wire [31:0] spi_readback;
wire spi_ready;
//shared I2C core signals
wire [31:0] i2c_readback;
wire i2c_ready;
//shared GPIO core signals
wire [31:0] gpio_readback;
///////////////////////////////////////////////////////////////////////////
// Misc Registers - persistent across resets
///////////////////////////////////////////////////////////////////////////
wire [31:0] config_word0;
setting_reg #(.my_addr(SR_MISC+0), .width(32)) sr_misc_config0
(.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word0));
wire [31:0] config_word1;
setting_reg #(.my_addr(SR_MISC+1), .width(32)) sr_misc_config1
(.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word1));
wire clock_sync_inv, clock_sync_enb;
setting_reg #(.my_addr(SR_MISC+2), .width(2)) sr_misc_clock_sync
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out({clock_sync_inv, clock_sync_enb}));
///////////////////////////////////////////////////////////////////////////
// Settings Bus and Readback
///////////////////////////////////////////////////////////////////////////
user_settings #(.BASE(SR_USER_REGS)) user_settings
(.clk(clk),.rst(reset),
.set_stb(set_stb), .set_addr(set_addr),.set_data(set_data),
.set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) );
wire [35:0] ctrl_out_data, ctrl_int_data;
wire ctrl_out_src_rdy, ctrl_out_dst_rdy;
wire ctrl_int_src_rdy, ctrl_int_dst_rdy;
fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_fifo
(.clk(clk), .reset(reset), .clear(1'b0),
.datain(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .space(),
.dataout(ctrl_int_data), .src_rdy_o(ctrl_int_src_rdy), .dst_rdy_i(ctrl_int_dst_rdy), .occupied());
wire [31:0] num_rx_dsps_rb = NUM_RX_DSPS;
wire [31:0] sfc_debug;
settings_fifo_ctrl #(.PROT_HDR(0), .ACK_SID(CTRL_ACK_SID), .XPORT_HDR(0)) sfc
(
.clock(clk), .reset(reset), .clear(1'b0),
.vita_time(vita_time), .perfs_ready(spi_ready & i2c_ready),
.in_data(ctrl_int_data), .in_valid(ctrl_int_src_rdy), .in_ready(ctrl_int_dst_rdy),
.out_data(ctrl_out_data), .out_valid(ctrl_out_src_rdy), .out_ready(ctrl_out_dst_rdy),
.strobe(set_stb), .addr(set_addr), .data(set_data),
.word00(spi_readback),.word01(compat_num),.word02(i2c_readback),.word03(gpio_readback),
.word04(config_word0),.word05(config_word1),.word06(num_rx_dsps_rb),.word07(32'hffff_ffff),
.word08(32'hffff_ffff),.word09(32'hffff_ffff),.word10(vita_time[63:32]),
.word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(32'hffff_ffff),
.word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
.debug(sfc_debug)
);
///////////////////////////////////////////////////////////////////////////
// Time Core
///////////////////////////////////////////////////////////////////////////
time_64bit #(.BASE(SR_TIME64)) time_64bit
(.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps),
.exp_time_in(0));
assign clock_sync = (clock_sync_enb)? (pps_in ^ clock_sync_inv) : 1'b0;
///////////////////////////////////////////////////////////////////////////
// SPI Core
///////////////////////////////////////////////////////////////////////////
simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hff))
simple_spi_core (.clock(clk), .reset(reset),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.readback(spi_readback), .ready(spi_ready),
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso));
///////////////////////////////////////////////////////////////////////////
// I2C Core
///////////////////////////////////////////////////////////////////////////
wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
simple_i2c_core #(.BASE(SR_I2C)) i2c_core
(.clock(clk),.reset(reset),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.readback(i2c_readback), .ready(i2c_ready),
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
// I2C -- Don't use external transistors for open drain, the FPGA implements this
IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
///////////////////////////////////////////////////////////////////////////
// GPIO Core
///////////////////////////////////////////////////////////////////////////
gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
gpio_atr(.clk(clk),.reset(reset),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.rx(run_rx), .tx(run_tx), .gpio({io_tx, io_rx}), .gpio_readback(gpio_readback) );
// /////////////////////////////////////////////////////////////////////////
// DSP RX *
wire [35:0] rx_int2_data [NUM_RX_DSPS-1:0];
wire rx_int2_src_rdy [NUM_RX_DSPS-1:0];
wire rx_int2_dst_rdy [NUM_RX_DSPS-1:0];
wire [31:0] sample_tx;
reg strobe_tx;
reg delayed_strobe_tx;
wire clear_tx;
genvar dspno;
generate
for(dspno = 0; dspno < NUM_RX_DSPS; dspno = dspno + 1) begin:gen_rx_dsps
wire [31:0] sample_rx;
// The length of this register determines how often we process an entry.
// It would be nice to have this adjustable.
reg [`LOG_SENDNTH-1:0] strobe_counter;
wire strobe_rx;
wire clear_rx;
wire [35:0] vita_rx_data;
wire vita_rx_src_rdy, vita_rx_dst_rdy;
wire [35:0] int_rx_data;
wire int_rx_src_rdy, int_rx_dst_rdy;
if (dspno == 0) begin
qa_wrapper qa_0
(.clk(clk), .reset(reset),
.in_data(sample_tx), .in_nd(delayed_strobe_tx),
.out_data(sample_rx), .out_nd(strobe_rx));
initial
strobe_counter <= 0;
always @ (posedge clk)
begin
strobe_counter <= strobe_counter + 1;
if (!(|strobe_counter))
begin
strobe_tx <= 1'b1;
end
if (strobe_tx)
begin
strobe_tx <= 1'b0;
delayed_strobe_tx <= 1'b1;
end
if (delayed_strobe_tx)
begin
delayed_strobe_tx <= 1'b0;
end
end
end
vita_rx_chain #(.BASE(SR_RX_CTRL0+dspno*32), .UNIT(dspno), .FIFOSIZE(DSP_RX_FIFOSIZE), .PROT_ENG_FLAGS(0), .DSP_NUMBER(dspno)) vita_rx_chain
(.clk(clk),.reset(reset),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time), .overrun(),
.sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), .clear_o(clear_rx),
.rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy),
.debug() );
fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE+1)) rx_data_fifo
(.clk(clk), .reset(reset), .clear(1'b0),
.datain(vita_rx_data), .src_rdy_i(vita_rx_src_rdy), .dst_rdy_o(vita_rx_dst_rdy), .space(),
.dataout(int_rx_data), .src_rdy_o(int_rx_src_rdy), .dst_rdy_i(int_rx_dst_rdy), .occupied());
if (dspno == 0) begin
assign rx_int2_data[dspno] = int_rx_data;
assign rx_int2_src_rdy[dspno] = int_rx_src_rdy;
assign int_rx_dst_rdy = rx_int2_dst_rdy[dspno];
end
else begin
fifo36_mux #(.prio(0)) // No priority, fair sharing
combine_rx_dsps (
.clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
.data0_i(rx_int2_data[dspno-1]), .src0_rdy_i(rx_int2_src_rdy[dspno-1]), .dst0_rdy_o(rx_int2_dst_rdy[dspno-1]),
.data1_i(int_rx_data), .src1_rdy_i(int_rx_src_rdy), .dst1_rdy_o(int_rx_dst_rdy),
.data_o(rx_int2_data[dspno]), .src_rdy_o(rx_int2_src_rdy[dspno]), .dst_rdy_i(rx_int2_dst_rdy[dspno])
);
end
end
endgenerate
// /////////////////////////////////////////////////////////////////////////
// RX Stream muxing
wire [35:0] rx_int3_data;
wire rx_int3_src_rdy, rx_int3_dst_rdy;
fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_XTRA_FIFOSIZE)) rx_data_fifo_combined
(.clk(clk), .reset(reset), .clear(1'b0),
.datain(rx_int2_data[NUM_RX_DSPS-1]), .src_rdy_i(rx_int2_src_rdy[NUM_RX_DSPS-1]), .dst_rdy_o(rx_int2_dst_rdy[NUM_RX_DSPS-1]), .space(),
.dataout(rx_int3_data), .src_rdy_o(rx_int3_src_rdy), .dst_rdy_i(rx_int3_dst_rdy), .occupied());
generate
if (USE_PACKET_PADDER) begin
packet_padder36 #(.BASE(SR_PADDER)) packet_padder_rx_data36(
.clk(clk), .reset(reset),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.data_i(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
.data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy),
.always_flush(~dsp_rx_run));
end
else begin
assign rx_data = rx_int3_data;
assign rx_src_rdy = rx_int3_src_rdy;
assign rx_int3_dst_rdy = rx_dst_rdy;
end
endgenerate
///////////////////////////////////////////////////////////////////////////
// MUX for TX async and resp data
///////////////////////////////////////////////////////////////////////////
wire [35:0] tx_err_data, resp_data_int;
wire tx_err_src_rdy, resp_src_rdy_int;
wire tx_err_dst_rdy, resp_dst_rdy_int;
fifo36_mux #(.prio(0)) // No priority, fair sharing
combine_async_and_resp (
.clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
.data0_i(ctrl_out_data), .src0_rdy_i(ctrl_out_src_rdy), .dst0_rdy_o(ctrl_out_dst_rdy),
.data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
.data_o(resp_data_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int)
);
fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_fifo
(.clk(clk), .reset(reset), .clear(1'b0),
.datain(resp_data_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .space(),
.dataout(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), .occupied());
// ///////////////////////////////////////////////////////////////////////////////////
// DSP TX
`ifdef DISABLE_TX_DSP
assign tx_dst_rdy = 1; //null sink
assign run_tx = 0;
assign tx_i = 0;
assign tx_q = 0;
`else
vita_tx_chain #(.BASE(SR_TX_CTRL),
.FIFOSIZE(DSP_TX_FIFOSIZE),
.POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE),
.REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
.PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
.DSP_NUMBER(0))
vita_tx_chain
(.clk(clk), .reset(reset),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.vita_time(vita_time),
.tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
.err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.sample(sample_tx), .strobe(strobe_tx),
.underrun(), .run(run_tx), .clear_o(clear_tx),
.debug());
`endif
// /////////////////////////////////////////////////////////////////////////////////////
// Debug circuitry
assign debug_clk = 2'b11;
assign debug = 32'hffffffff;
endmodule // u1plus_core
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_PP_BLACKBOX_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_PP_BLACKBOX_V
|
/*!
* <b>Module:</b>ahci_dma
* @file ahci_dma.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief DMA R/W over 64-AXI channel for AHCI implementation
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_dma.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module ahci_dma (
// input rst,
input mrst, // @posedge mclk - sync reset
input hrst, // @posedge hclk - sync reset
input mclk, // for command/status
input hclk, // global clock to run axi_hp @ 150MHz
// Control interface (@mclk)
// Documentation insists 6 LSBs should be 0, but AHCI driver seems to ignore it. Will align to just 128 bits.
// input [31:7] ctba, // command table base address
input [31:4] ctba, // command table base address
input ctba_ld, // load command table base address
input [15:0] prdtl, // number of entries in PRD table (valid at cmd_start)
input dev_wr, // write to device (valid at start)
input cmd_start, // start processing command table, reset prdbc
input prd_start, // at or after cmd_start - enable reading PRD/data (if any)
input cmd_abort, // try to abort a command: Will keep afi_rready on until RD FIFO is empty and
// afi_awvalid (slowly one by one?) until afi_wacount is empty, keeping afi_wlast on
// Optional control of the AXI cache mode, default will be set to 4'h3, 4'h3 at mrst
input [3:0] axi_wr_cache_mode,
input [3:0] axi_rd_cache_mode,
input set_axi_wr_cache_mode,
input set_axi_rd_cache_mode,
// Some data from the command table will be used internally, data will be available on the general
// sys_out[31:0] port and should be consumed
output reg ct_busy, // cleared after 0x20 DWORDs are read out
// reading out command table data
input [ 4:0] ct_addr, // DWORD address
input [ 1:0] ct_re, // [0] - re, [1]-regen
output reg [31:0] ct_data, //
// After the first 0x80 bytes of the Command Table are read out, this module will read/process PRDs,
// not forwarding them to the output
output prd_done, // @mclk prd done (regardless of the interrupt) - data transfer of one PRD is finished (any direction)
input prd_irq_clear, // reset pending prd_irq
output reg prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
output reg cmd_busy, // all commands
output cmd_done, // @ mclk
output abort_busy,
output abort_done,
output axi_mismatch, // axi hp counters where empty when calculated counters were not (handled, but seems to be a bug - catch it)
// Data System memory -> HBA interface @ mclk
output [31:0] sys_out, // 32-bit data from the system memory to HBA (dma data)
output sys_dav, // at least one dword is ready to be read
// output sys_dav_many, // several DWORDs are in the FIFO (TODO: decide how many)
input sys_re, // sys_out data read, advance internal FIFO
output last_h2d_data,// when active and no new data for 2 clocks - that was the last one
// Data HBA -> System memory interface @ mclk
input [31:0] sys_in, // HBA -> system memory
output sys_nfull, // internal FIFO has room for more data (will decide - how big reserved space to keep)
input sys_we,
output extra_din, // all DRDs are transferred to memory, but FIFO has some data. Valid when transfer is stopped
// axi_hp signals write channel
// write address
output [31:0] afi_awaddr,
output afi_awvalid,
input afi_awready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi_awid,
output [ 1:0] afi_awlock,
output reg [ 3:0] afi_awcache,
output [ 2:0] afi_awprot,
output [ 3:0] afi_awlen,
output [ 1:0] afi_awsize,
output [ 1:0] afi_awburst,
output [ 3:0] afi_awqos,
// write data
output [63:0] afi_wdata,
output afi_wvalid,
input afi_wready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi_wid,
output afi_wlast,
output [ 7:0] afi_wstrb,
// write response
input afi_bvalid, // @SuppressThisWarning VEditor unused
output afi_bready,
input [ 5:0] afi_bid, // @SuppressThisWarning VEditor unused
input [ 1:0] afi_bresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi_wcount,
input [ 5:0] afi_wacount,
output afi_wrissuecap1en,
// AXI_HP signals - read channel
// read address
output [31:0] afi_araddr,
output afi_arvalid,
input afi_arready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi_arid,
output [ 1:0] afi_arlock,
output reg [ 3:0] afi_arcache,
output [ 2:0] afi_arprot,
output [ 3:0] afi_arlen,
output [ 1:0] afi_arsize,
output [ 1:0] afi_arburst,
output [ 3:0] afi_arqos,
// read data
input [63:0] afi_rdata,
input afi_rvalid,
output afi_rready,
input [ 5:0] afi_rid, // @SuppressThisWarning VEditor unused
input afi_rlast, // @SuppressThisWarning VEditor unused
input [ 1:0] afi_rresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi_rcount,
input [ 2:0] afi_racount,
output afi_rdissuecap1en,
output [31:0] debug_out,
output [31:0] debug_out1
,output [31:0] debug_dma_h2d
);
// Read command table
// localparam AFI_FIFO_LAT = 2; // >=2
localparam SAFE_RD_BITS = 3; //2; // 3;
reg [31:0] ct_data_ram [0:31];
reg [3:0] int_data_addr; // internal (ct,prd) data address
// reg [31:7] ctba_r;
reg [31:4] ctba_r; // Seems that AHCI driver ignores requirement to have 6 LSB==0
reg [15:0] prdtl_mclk;
wire cmd_start_hclk;
reg prd_start_r;
wire prd_start_hclk;
reg prd_start_hclk_r; // to make sure it is with/after prd_start_hclk if in mclk they are in the same cycle
wire cmd_abort_hclk; // TODO: Implement as graceful as possible command abort
reg prd_enabled;
reg [1:0] ct_over_prd_enabled; // prd read and data r/w enabled, command table fetch done
reg [31:4] ct_maddr; // granularity matches PRDT entry - 4xDWORD, 2xQWORD
wire ct_done;
wire first_prd_fetch; // CT read done, prd enabled
reg [31:0] afi_addr; // common for afi_araddr and afi_awaddr
wire axi_set_raddr_ready = !(|afi_racount[2:1]) && (!axi_set_raddr_r || !afi_racount[0]); // What is the size of ra fifo - just 4? Latency?
// wire axi_set_raddr_ready = !(|afi_racount) && !axi_set_raddr_r); // Most pessimistic
wire axi_set_waddr_ready = !afi_wacount[5] && !afi_wacount[4]; // What is the size of wa fifo - just 32? Using just half - safe
wire axi_set_raddr_w;
wire axi_set_waddr_w;
wire axi_set_addr_data_w;
reg axi_set_raddr_r; // [0] - actual write address to fifo
reg axi_set_waddr_r; // [0] - actual write address to fifo
reg is_ct_addr; // current address is ct address
reg is_prd_addr; // current address is prd address
reg is_data_addr; // current address is data address (r or w)
reg [31:1] data_addr; // 2 lower addresses will be used in in/out fifo modules
reg [3:0] data_len; //
reg data_irq; // interrupt at the end of this PRD
reg [21:1] wcount; // Word count
reg wcount_set;
reg [22:1] qwcount; // only [21:3] are used ([22] - carry from subtraction )
reg qwcount_done;
reg [21:3] qw_datawr_left;
reg [ 3:0] qw_datawr_burst;
reg qw_datawr_last;
wire data_afi_re;
reg [15:0] prds_left;
reg last_prd;
reg [1:0] afi_rd_ctl; // read non-data (CT or PRD)
reg [1:0] ct_busy_r;
reg prd_rd_busy; // reading PRD
reg dev_wr_mclk;
reg dev_wr_hclk;
reg prd_wr; // write PRD data to memory
reg prd_rd; // read PRD data from memory
wire [3:0] afi_wstb4;
wire done_dev_wr; // finished PRD mem -> device
wire done_dev_rd; // finished PRD device -> mem
wire prd_done_hclk = done_dev_wr || done_dev_rd;
wire done_flush; // done flushing last partial dword
wire cmd_done_hclk;
wire ct_done_mclk;
reg [3:0] afi_alen;
wire afi_wcount_many = !afi_wcount[7] && !(&afi_wcount[6:4]);
reg data_next_burst;
// wire raddr_prd_rq = (|prds_left) && (ct_done || prd_done);
wire raddr_prd_rq = (|prds_left) && (first_prd_fetch || prd_done_hclk);
reg raddr_prd_pend;
wire raddr_ct_rq = cmd_start_hclk;
reg raddr_ct_pend;
/*
wire addr_data_rq = (wcount_set || data_next_burst);
wire waddr_data_rq = !dev_wr_hclk && addr_data_rq;
wire raddr_data_rq = dev_wr_hclk && addr_data_rq;
*/
wire addr_data_rq_w = (wcount_set || data_next_burst);
reg addr_data_rq_r;
wire waddr_data_rq = !dev_wr_hclk && addr_data_rq_r;
wire raddr_data_rq = dev_wr_hclk && addr_data_rq_r;
reg waddr_data_pend;
reg raddr_data_pend;
// count different types of AXI ID separately - just for debugging
reg [3:0] ct_id;
reg [3:0] prd_id;
reg [3:0] dev_wr_id;
reg [3:0] dev_rd_id;
reg [5:0] afi_id; // common for 3 channels
wire fifo_nempty_mclk;
reg en_extra_din_r;
reg [31:0] ct_data_reg;
// reg abort_busy_hclk;
reg hrst_r;
wire abort_or_reset = cmd_abort_hclk || (hrst_r && !hrst);
// reg axi_dirty_r; // afi_wacount of afi_rcount are non-zero (assuming afi_wcount should be zero as addresses are posted first
wire afi_dirty;
reg afi_dirty_mclk;
wire abort_done_hclk;
wire abort_done_mclk;
reg abort_done_unneeded;
wire aborting;
wire afi_wvalid_data;
wire afi_wvalid_abort;
wire [5:0] afi_wid_abort;
wire afi_rready_abort;
wire afi_wlast_abort;
// wire abort_done;
reg abort_rq_mclk;
reg abort_busy_mclk;
wire [21:0] abort_debug;
reg rwaddr_rq_r; // next cycle after requesting waddr_data_rq, raddr_data_rq, raddr_ct_rq and raddr_prd_rq (*-pend is valid)
assign afi_wvalid = aborting ? afi_wvalid_abort: afi_wvalid_data;
assign afi_wid = aborting ? afi_wid_abort: afi_id;
assign afi_rready = aborting ? afi_rready_abort : (afi_rd_ctl[0] || data_afi_re);
assign afi_wlast = aborting ? afi_wlast_abort: qw_datawr_last;
assign abort_done = abort_done_mclk || abort_done_unneeded;
assign abort_busy = abort_busy_mclk;
// assign prd_done = done_dev_wr || done_dev_rd;
assign cmd_done_hclk = ((ct_busy_r==2'b10) && (prdtl_mclk == 0)) || ((done_flush || done_dev_rd) && last_prd);
assign ct_done = (ct_busy_r == 2'b10);
assign first_prd_fetch = ct_over_prd_enabled == 2'b01;
assign axi_set_raddr_w = axi_set_raddr_ready && (raddr_ct_pend || raddr_prd_pend || raddr_data_pend);
/// assign axi_set_waddr_w = axi_set_raddr_ready && raddr_data_pend;
assign axi_set_waddr_w = axi_set_waddr_ready && waddr_data_pend;
assign axi_set_addr_data_w = (axi_set_raddr_ready && raddr_data_pend) || (axi_set_waddr_ready && waddr_data_pend);
assign afi_awaddr = afi_addr;
assign afi_araddr = afi_addr;
assign afi_arlen = afi_alen;
assign afi_awlen = afi_alen;
assign afi_arvalid = axi_set_raddr_r;
assign afi_awvalid = axi_set_waddr_r;
/// assign afi_rready = afi_rd_ctl[0] || data_afi_re;
assign afi_wstrb = {{2{afi_wstb4[3]}},{2{afi_wstb4[2]}},{2{afi_wstb4[1]}},{2{afi_wstb4[0]}}};
/// assign afi_wlast = qw_datawr_last;
assign afi_awid = afi_id;
// assign afi_wid = afi_id;
assign afi_arid = afi_id;
// Unused or static output signals
assign afi_bready = 1'b1;
assign afi_awlock = 2'h0;
// assign afi_awcache = 4'h3;
assign afi_awprot = 3'h0;
assign afi_awsize = 2'h3;
assign afi_awburst = 2'h1;
assign afi_awqos = 4'h0;
assign afi_wrissuecap1en = 1'b0;
assign afi_arlock = 2'h0;
// assign afi_arcache = 4'h3;
assign afi_arprot = 3'h0;
assign afi_arsize = 2'h3;
assign afi_arburst = 2'h1;
assign afi_arqos = 4'h0;
assign afi_rdissuecap1en = 1'b0;
assign extra_din = en_extra_din_r && fifo_nempty_mclk;
// reg [31:0] ct_data_reg;
always @ (posedge mclk) begin
if (mrst) afi_dirty_mclk <= 0;
afi_dirty_mclk <=afi_dirty;
abort_rq_mclk <= cmd_abort && afi_dirty_mclk;
abort_done_unneeded <= cmd_abort && !afi_dirty_mclk;
if (mrst || abort_done) abort_busy_mclk <= 0;
else if (cmd_abort) abort_busy_mclk <= 1;
if (ct_re[0]) ct_data_reg <= ct_data_ram[ct_addr];
if (ct_re[1]) ct_data <= ct_data_reg;
// if (ctba_ld) ctba_r <= ctba[31:7];
if (ctba_ld) ctba_r <= ctba[31:4];
if (cmd_start) prdtl_mclk <= prdtl;
if (cmd_start) dev_wr_mclk <= dev_wr;
if (mrst || cmd_abort) cmd_busy <= 0;
else if (cmd_start) cmd_busy <= 1;
else if (cmd_done) cmd_busy <= 0;
if (mrst || cmd_abort) ct_busy <= 0;
else if (cmd_start) ct_busy <= 1;
else if (ct_done_mclk) ct_busy <= 0;
if (mrst) afi_arcache <= 4'h3;
else if (set_axi_rd_cache_mode) afi_arcache <= axi_rd_cache_mode;
if (mrst) afi_awcache <= 4'h3;
else if (set_axi_wr_cache_mode) afi_awcache <= axi_wr_cache_mode;
prd_start_r <= prd_start;
if (mrst || prd_irq_clear ||cmd_start || cmd_abort) prd_irq_pend <= 0;
else if (data_irq && prd_done) prd_irq_pend <= 1;
if (mrst || cmd_start || cmd_abort) en_extra_din_r <= 0;
else if (cmd_done) en_extra_din_r <= 1;
end
// afi_rd_ctl <= { afi_rd_ctl[0],(ct_busy_r[0] || prd_rd_busy) && ((|afi_rcount[7:SAFE_RD_BITS]) || (afi_rvalid && !(|afi_rd_ctl)))};
wire debug_01 = ct_busy_r[0] || prd_rd_busy ;
wire debug_02 =|afi_rcount[7:SAFE_RD_BITS];
wire debug_03 = (afi_rvalid && !(|afi_rd_ctl));
wire [21:1] wcount_plus_data_addr = wcount[21:1] + data_addr[2:1];
always @ (posedge hclk) begin
hrst_r <= hrst;
if (hrst) rwaddr_rq_r <= 0;
else rwaddr_rq_r <= raddr_ct_rq || raddr_prd_rq || raddr_data_rq || waddr_data_rq;
addr_data_rq_r <= addr_data_rq_w;
prd_start_hclk_r <= prd_start_hclk;
if (hrst || abort_or_reset) prd_enabled <= 0;
else if (prd_start_hclk_r) prd_enabled <= 1; // precedence over cmd_start_hclk
else if (cmd_start_hclk) prd_enabled <= 0;
// if (cmd_start_hclk) ct_maddr[31:4] <= {ctba_r[31:7],3'b0};
if (cmd_start_hclk) ct_maddr[31:4] <= ctba_r[31:4];
else if (ct_done) ct_maddr[31:4] <= ct_maddr[31:4] + 8; // 16;
else if (wcount_set) ct_maddr[31:4] <= ct_maddr[31:4] + 1;
// overall sequencing makes sure that there will be no new requests until older served
// additionally they are mutuially exclusive - only one may be pending at a time
if (hrst || cmd_abort_hclk) raddr_ct_pend <= 0;
else if (raddr_ct_rq) raddr_ct_pend <= 1;
else if (axi_set_raddr_ready) raddr_ct_pend <= 0;
if (hrst || cmd_abort_hclk) raddr_prd_pend <= 0;
else if (raddr_prd_rq) raddr_prd_pend <= 1;
else if (axi_set_raddr_ready) raddr_prd_pend <= 0;
if (hrst || cmd_abort_hclk) raddr_data_pend <= 0;
else if (raddr_data_rq) raddr_data_pend <= 1;
else if (axi_set_raddr_ready) raddr_data_pend <= 0;
if (hrst || cmd_abort_hclk) waddr_data_pend <= 0;
else if (waddr_data_rq) waddr_data_pend <= 1;
else if (axi_set_waddr_ready) waddr_data_pend <= 0;
if (hrst) {is_ct_addr, is_prd_addr, is_data_addr} <= 0;
else if (raddr_ct_rq || raddr_prd_rq || wcount_set) {is_ct_addr, is_prd_addr, is_data_addr} <= {raddr_ct_rq, raddr_prd_rq, wcount_set};
/// if (axi_set_raddr_w || axi_set_waddr_w) begin
if (rwaddr_rq_r) begin // first cycle one of the *_pend is set
if (raddr_data_pend || waddr_data_pend) afi_addr <= {data_addr[31:3], 3'b0};
else afi_addr <= {ct_maddr[31:4], 4'b0};
if (raddr_data_pend || waddr_data_pend) afi_alen <= data_len;
else if (raddr_ct_pend) afi_alen <= 4'hf; // 16 QWORDS (128 bytes)
else afi_alen <= 4'h1; // 2 QWORDS
if (raddr_data_pend || waddr_data_pend) afi_id <= raddr_data_pend ? {2'h2, dev_rd_id} : {2'h3, dev_wr_id};
else afi_id <= raddr_ct_pend ? {2'h0, ct_id} : {2'h1, prd_id};
end
if (hrst) axi_set_raddr_r <= 0;
else axi_set_raddr_r <= axi_set_raddr_w;
if (hrst) axi_set_waddr_r <= 0;
else axi_set_waddr_r <= axi_set_waddr_w;
/// if (addr_data_rq) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3]; // early calculate
if (addr_data_rq_r) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3]; // early calculate
if (wcount_set) qwcount[22:7] <= {1'b0,wcount_plus_data_addr[21:7]}; // wcount[21:1] + data_addr[2:1]; //minus 1
else if (axi_set_addr_data_w) qwcount[22:7] <= qwcount[22:7] - 1; // may get negative
if (wcount_set) qwcount[ 6:1] <= wcount_plus_data_addr[6:1]; // wcount[21:1] + data_addr[2:1]; //minus 1
if (wcount_set) qwcount_done <= 0;
else if (axi_set_addr_data_w && (qwcount[21:7]==0)) qwcount_done <= 1;
//wcount_plus_data_addr
/// data_next_burst <= !qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid
data_next_burst <= !qwcount_done && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid
// Get PRD data
// store data address from PRD, increment when needed
if (afi_rd_ctl[0] && is_prd_addr && (!int_data_addr[0])) data_addr[31:1] <= afi_rdata[31:1];
if (axi_set_addr_data_w) data_addr[31:7] <= data_addr[31:7] + 1;
if (afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0])) data_irq <= afi_rdata[63];
if (afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0])) wcount[21:1] <= afi_rdata[53:33];
wcount_set <= afi_rd_ctl[0] && is_prd_addr && (int_data_addr[0]);
if (cmd_start_hclk) prds_left <= prdtl_mclk;
else if (raddr_prd_rq) prds_left <= prds_left - 1;
if (raddr_prd_rq) last_prd <= prds_left[15:1] == 0;
// Set/increment address to store (internally) CT and PRD data
if (axi_set_raddr_r) int_data_addr <= 0;
else if (afi_rd_ctl[0] && !is_data_addr) int_data_addr <= int_data_addr + 1;
if (afi_rd_ctl[0] && is_ct_addr) {ct_data_ram[{int_data_addr,1'b1}],ct_data_ram[{int_data_addr,1'b0}]} <= afi_rdata; // make sure it is synthesized correctly
// generate busy for command table (CT) read
if (hrst) ct_busy_r[0] <= 0;
else if (cmd_start_hclk) ct_busy_r[0] <= 1;
else if (afi_rd_ctl[0] && is_ct_addr && (&int_data_addr)) ct_busy_r[0] <= 0;
ct_busy_r[1] <= ct_busy_r[0]; // delayed version to detect end of command
if (hrst || ct_busy_r[0]) ct_over_prd_enabled[0] <= 0;
else if (prd_enabled) ct_over_prd_enabled[0] <= 1;
ct_over_prd_enabled[1] <= ct_over_prd_enabled[0]; // detecting 0->1 transition
// generate busy for PRD table entry read
if (hrst) prd_rd_busy <= 0;
// else if (prd_rd_busy) prd_rd_busy <= 1;
else if (raddr_prd_rq && axi_set_raddr_ready) prd_rd_busy <= 1;
else if (wcount_set) prd_rd_busy <= 0;
if (cmd_start_hclk) dev_wr_hclk <= dev_wr_mclk; // 1: memory -> device, 0: device -> memory
prd_wr <= wcount_set && !dev_wr_hclk;
prd_rd <= wcount_set && dev_wr_hclk;
afi_rd_ctl <= { afi_rd_ctl[0],(ct_busy_r[0] || prd_rd_busy) && ((|afi_rcount[7:SAFE_RD_BITS]) || (afi_rvalid && !(|afi_rd_ctl)))};
// calculate afi_wlast - it is (qw_datawr_burst == 0), just use register qw_datawr_last
if (prd_wr) qw_datawr_last <= (qwcount[21:3] == 0);
else if (afi_wvalid_data) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && (qw_datawr_left[21:3] == 16)); // last case - n*16 + 1 (last burst single)
if (prd_wr) qw_datawr_burst <= (|qwcount[21:7])? 4'hf: qwcount[6:3];
else if (afi_wvalid_data && qw_datawr_last && (qw_datawr_left[21:7] == 1)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf
else if (afi_wvalid_data) qw_datawr_burst <= qw_datawr_burst - 1;
if (prd_wr) qw_datawr_left[21:3] <= qwcount[21:3];
else if (afi_wvalid_data && qw_datawr_last) qw_datawr_left[21:7] <= qw_datawr_left[21:7] - 1; // can go negative - OK?
// Count AXI IDs
if (hrst) ct_id <= 0;
else if (ct_busy_r==2'b10) ct_id <= ct_id + 1;
if (hrst) prd_id <= 0;
else if (wcount_set) prd_id <= prd_id + 1;
if (hrst) dev_wr_id <= 0;
else if (done_dev_wr) dev_wr_id <= dev_wr_id + 1;
if (hrst) dev_rd_id <= 0;
else if (done_dev_rd) dev_rd_id <= dev_rd_id + 1;
end
// Flushing AXI HP - there is no easy way to reset it, so if there was an error in SATA communication we need to read any data
// that was already requested (over AXI read adderss channel) and send junk data (with appropriate afi_wlast bit) to the write
// channel. THis module is not reset and even bitsteram relaod will not work, so hrst input is used just as disable paying attention
// to other inputs, doe s not reset anything inside.
// FPGA should not be reset /reloaded if there are any outstanding transactions not aborted
// Current implementation counts all transactions and relies on it - not on afi_*count. TODO: Implement recovering from mismatch
axi_hp_abort axi_hp_abort_i (
.hclk (hclk), // input
.hrst (hrst), // input
.abort (abort_or_reset), // input
.busy (aborting), // output
.done (abort_done_hclk), // output reg
.afi_awvalid (afi_awvalid), // input
.afi_awready (afi_awready), // input
.afi_awid (afi_awid), // input[5:0]
.afi_awlen (afi_awlen), // input[3:0]
.afi_wvalid_in (afi_wvalid), // input
.afi_wready (afi_wready), // input
.afi_wvalid (afi_wvalid_abort), // output
.afi_wid (afi_wid_abort), // output[5:0] reg
.afi_arvalid (afi_arvalid), // input
.afi_arready (afi_arready), // input
.afi_arlen (afi_arlen), // input[3:0]
.afi_rready_in (afi_rready), // input
.afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready_abort), // output
.afi_wlast (afi_wlast_abort), // output
.afi_racount (afi_racount), // input[2:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0]
.afi_wcount (afi_wcount), // input[7:0]
.dirty (afi_dirty), // output reg
.axi_mismatch (axi_mismatch), // output_reg
.debug (abort_debug) // output[21:0]
);
ahci_dma_rd_fifo #( // memory to device
.WCNT_BITS (21),
.ADDRESS_BITS (3)
) ahci_dma_rd_fifo_i (
.mrst (mrst || abort_busy_mclk), // input
.hrst (hrst || cmd_abort_hclk), // input
.mclk (mclk), // input
.hclk (hclk), // input
.wcnt (wcount[21:1]), // input[20:0]
.woffs (data_addr[2:1]), // input[1:0]
.start (prd_rd), // input
.din (afi_rdata), // input[63:0]
.din_av (afi_rvalid), // input
.din_av_many (|afi_rcount[7:SAFE_RD_BITS]), // input
.last_prd (last_prd), // input
.din_re (data_afi_re), // output
.done (done_dev_wr), // output reg // @ hclk
.done_flush (done_flush), // output // @ hclk
.dout (sys_out), // output[31:0]
.dout_vld (sys_dav), // output
.dout_re (sys_re), // input
.last_DW (last_h2d_data) // output
,.debug_dma_h2d(debug_dma_h2d) // output[31:0]
);
ahci_dma_wr_fifo #( // device to memory
.WCNT_BITS (21),
.ADDRESS_BITS (3)
) ahci_dma_wr_fifo_i (
.mrst (mrst || abort_busy_mclk), // input
.hrst (hrst ||cmd_abort_hclk), // input
.mclk (mclk), // input
.hclk (hclk), // input
.wcnt (wcount[21:1]), // input[20:0]
.woffs (data_addr[2:1]), // input[1:0]
.init (cmd_start_hclk), // input
.start (prd_wr), // input
.dout (afi_wdata), // output[63:0] reg
// .dout_av (), // input
.dout_av_many (afi_wcount_many), // input
.last_prd (last_prd), // input
.dout_we (afi_wvalid_data), // output
.dout_wstb (afi_wstb4), // output[3:0] reg
.done (done_dev_rd), // output reg
.busy (), // output
.fifo_nempty_mclk (fifo_nempty_mclk), // output reg
.din (sys_in), // input[31:0]
.din_rdy (sys_nfull), // output
.din_avail (sys_we) // input
);
// mclk -> hclk cross-clock synchronization
pulse_cross_clock #(
.EXTRA_DLY(0)
) cmd_start_hclk_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (hclk), // input
.in_pulse (cmd_start), // input
.out_pulse (cmd_start_hclk), // output
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) cmd_abort_hclk_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (hclk), // input
.in_pulse (abort_rq_mclk), // input
.out_pulse (cmd_abort_hclk), // output
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) prd_start_hclk_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (hclk), // input
.in_pulse (prd_start_r), // input
.out_pulse (prd_start_hclk), // output
.busy() // output
);
// hclk -> mclk;
pulse_cross_clock #(
.EXTRA_DLY(0)
) cmd_done_i (
.rst (hrst), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (cmd_done_hclk), // input
.out_pulse (cmd_done), // output
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) ct_done_mclk_i (
.rst (hrst), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (ct_done), // input
.out_pulse (ct_done_mclk), // output
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) prd_done_mclk_i (
.rst (hrst), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (prd_done_hclk), // input
.out_pulse (prd_done), // output
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) abort_done_i (
.rst (hrst), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (abort_done_hclk), // input
.out_pulse (abort_done_mclk), // output
.busy() // output
);
//abort_done_hclk
reg [7:0] dbg_afi_awvalid_cntr;
reg [7:0] dbg_qwcount;
reg [7:0] dbg_qwcount_cntr;
reg [7:0] dbg_set_raddr_count;
reg [7:0] dbg_set_waddr_count;
reg dbg_was_mismatch;
// if (axi_set_raddr_w || axi_set_waddr_w) begin
//data_next_burst
always @ (posedge hclk) begin
if (hrst) dbg_afi_awvalid_cntr <= 0;
else if (axi_set_waddr_r) dbg_afi_awvalid_cntr <= dbg_afi_awvalid_cntr + 1;
// if (hrst) dbg_last_afi_len <= 0;
if (axi_set_raddr_w || axi_set_waddr_w) begin
end
if (wcount_set) dbg_qwcount <= wcount_plus_data_addr[14:7];
// if (wcount_set) qwcount[22:7] <= {1'b0,wcount_plus_data_addr[21:7]}; // wcount[21:1] + data_addr[2:1]; //minus 1
if (hrst) dbg_qwcount_cntr <= 0;
// else if (wcount_set) dbg_qwcount_cntr <= dbg_qwcount_cntr + 1;
// else if (data_next_burst) dbg_qwcount_cntr <= dbg_qwcount_cntr + 1;
else if (!qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7])) dbg_qwcount_cntr <= dbg_qwcount_cntr + 1;
if (hrst) dbg_set_raddr_count <= 0;
// else if (axi_set_raddr_w) dbg_set_raddr_count <= dbg_set_raddr_count + 1;
else if (axi_set_raddr_ready && raddr_data_pend) dbg_set_raddr_count <= dbg_set_raddr_count + 1;
if (hrst) dbg_set_waddr_count <= 0;
// else if (axi_set_waddr_w) dbg_set_waddr_count <= dbg_set_waddr_count + 1;
// else if (axi_set_waddr_ready && waddr_data_pend) dbg_set_waddr_count <= dbg_set_waddr_count + 1; //0x14
else if (addr_data_rq_w) dbg_set_waddr_count <= dbg_set_waddr_count + 1; //0x14
if (hrst) dbg_was_mismatch <= 0;
else if (axi_mismatch) dbg_was_mismatch <= 1;
end
assign debug_out = {int_data_addr [3:0],
qwcount_done, // prd_rd_busy,
afi_racount [2:0],
//--
afi_rcount [7:0],
//--
ct_busy,
cmd_busy,
afi_wacount [5:0],
//--
afi_wcount [7:0]};
/*
assign debug_out = {
qwcount[22:7],
dev_rd_id,
dev_wr_id,
prd_id,
ct_id
};
assign debug_out = {qwcount_done,
2'b0,
dev_wr_id,
prd_id,
wcount[21:1]
};
assign debug_out1 = { //dbg_set_raddr_count[7:0],
qwcount_done,
afi_rcount[6:0],
//{qwcount[22], qwcount[13:7]},
dbg_set_waddr_count[7:0],
dbg_qwcount[3:0],
afi_alen[3:0],
dbg_qwcount_cntr[7:0]};
*/
assign debug_out1 = { //dbg_set_raddr_count[7:0]
8'b0 ,
dbg_was_mismatch,
1'b0,
abort_debug[21:0]}; // {aw_count[5:0], w_count[7:0], r_count[7:0]};
//
endmodule
|
/*main function
1)parsing packet header
2)fetch the keys from packet header include l3_protocol ,tos,l4_protocol,source ip,derection ip,source port derection port ,tcp_flag icmp layer_type and icmp code
3)combine keys to prepad
*/
/******************************* the prepad format********************************************/
/*
four pats prepad format:
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
ipv4_uc|ipv4_mc|umknown|arp|rarp|mpls_uc|ttl 0or1|option|ppp_ctrl|ipv6_mc|fragment|subsequent|isis|ipv6_link_local|drop|out_vlan|in_vlan|L3infhandle|local__port_port_index|l2_stake|pad2|l3_stake|net_diagnosis|pad|timestamp_2B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
timestamp_6B|L3_protocol|Tos|L4_protocol|source ip|derection ip_2B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
derection ip_2B|source port|derection port|tcp_flag|pad_9B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
pad_16B
*/
//*********************the structure of packet parsing******************************************/
/*
|--->TCP
| --->IP----
| |----ICMP
ethernet----
|
| --->unknown
*/
`timescale 1 ps / 1 ps
module CLASSIFY(
input clk,
input reset,
input in_ingress_key_wr,// the key write request of inputctrl to classfy
input [133:0] in_ingress_key,// the key of inputctrl to classfy
input in_ingress_valid_wr,//the valid flag write request of inputctrl to classfy
input in_ingress_valid,//the valid flag of inputctrl to classfy
output out_ingress_key_almostfull,//the valid fifo almostfull signal of classfy to inputctrl
output reg out_offset_key_wr,// the key write request of classfy to inputctrl
output reg [133:0] out_offset_key,// the key of classfy to inputctrl
output reg out_offset_valid,// the valid flag of classfy to inputctrl
output reg out_offset_valid_wr,//the valid flag write request of classfy to inputctrl
input in_offset_key_almostfull//the valid fifo almostfull signal of inputctrl to classfy
);
reg [2:0] state;
wire in_ingress_valid_q; //the output valid flag from the valid flag fifo
wire in_ingress_valid_empty;//the empty signal of the valid flag fifo
reg out_ingress_valid_rd; //the read request of the valid flag fifo
wire [7:0] out_ingress_key_usedw;//the usedw signal of the key fifo
assign out_ingress_key_almostfull = out_ingress_key_usedw[7];
reg out_ingress_key_rd;//the read request of the key fifo
wire [133:0]in_ingress_key_q;//the output key from the valid flag fifo
reg is_unknown;
reg [7:0]tos;
reg [15:0]l3_protocol;
reg [7:0]l4_protocol;
reg [31:0]sip;
reg [31:0]dip;
reg [15:0]sport;
reg [15:0]dport;
reg [7:0]tcp_flag;
reg [7:0]layer_type;
reg [7:0]code;
reg tcp_icmp;
parameter idle=3'd0,
l2=3'd1,
l3=3'd2,
l4=3'd3,
prepad1=3'd4,
prepad2=3'd5,
prepad3=3'd6,
prepad4=3'd7;
always @(posedge clk or negedge reset) begin
if(!reset)begin
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
state<=idle;
end
else begin
case(state)
idle:begin// according to the in_offset_key_almostfull and in_ingress_valid_empty signals to judge whether or not the classfy module can receive packet from inputctrl
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
if(in_offset_key_almostfull==1'b0 && in_ingress_valid_empty==1'b0 )begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
state<=l2;
end
else begin
state<=idle;
end
end
l2: begin//according to the layer_type field of the ethrnet hearder to parsing packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
state<=l3;
if(in_ingress_key_q[31:16]==16'h0800 &&in_ingress_key_q[11:8] ==4'd5)//judge the packet whether or not a IP packet and its header length equal the 20bytes
begin
l3_protocol<=in_ingress_key_q[31:16];
tos<=in_ingress_key_q[7:0];
end
else
begin
is_unknown<=1'b1;
end
end
l3:begin//according to the protocol field of the IP hearder to judge the packet whether or not a TCP packet or ICMP packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=l4;
end
else if(in_ingress_key_q[71:64]==8'd6|| in_ingress_key_q[71:64]==8'd1)//judge the packet whether or not a TCP packet or ICMP packet
begin
l4_protocol<=in_ingress_key_q[71:64];
sip<=in_ingress_key_q[47:16];
dip[31:16]<=in_ingress_key_q[15:0];
end
else
begin
is_unknown<=1'b1;
end
state<=l4;
end
l4:begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=prepad1;
end
else if(l4_protocol==8'd6)
begin
dip[15:0]<=in_ingress_key_q[127:112];
sport<=in_ingress_key_q[111:96];
dport<=in_ingress_key_q[95:80];
tcp_flag<=in_ingress_key_q[7:0];
state<=prepad1;
end
else if(l4_protocol==8'd1)
begin
dip[15:0]<=in_ingress_key_q[127:112];
layer_type<=in_ingress_key_q[111:104];
code<=in_ingress_key_q[103:96];
tcp_flag<=8'b0;
end
else
begin
is_unknown<=1'b1;
end
state<=prepad1;
end
prepad1:begin//to structure the first pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b010000,3'b001,125'b0};
state<=prepad2;
end
prepad2:begin//to structure the second pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b110000,48'b0,l3_protocol,tos,l4_protocol,sip,dip[31:16]};
state<=prepad3;
end
prepad3:begin//to structure the third pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
if(tcp_icmp==1'b0)
begin
out_offset_key<={6'b110000,dip[15:0],sport,dport,tcp_flag,72'b0};
end
else
begin
out_offset_key<={6'b110000,dip[15:0],layer_type,code,96'b0};
end
state<=prepad4;
end
prepad4:begin//to structure the fourth pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b100000,128'b0};
out_offset_valid<=1'b1;
out_offset_valid_wr<=1'b1;
state<=idle;
end
endcase
end
end
fifo_64_1 FIFO_VALID_input (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_key_input (
.aclr(!reset),
.data(in_ingress_key),
.clock(clk),
.rdreq(out_ingress_key_rd),
.wrreq(in_ingress_key_wr),
.q(in_ingress_key_q),
.usedw(out_ingress_key_usedw)
);
endmodule |
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division *)
(** Initial Contribution by Claude Marché and Xavier Urbain *)
Require Export ZArith_base.
Require Import Zbool Omega ZArithRing Zcomplements Setoid Morphisms.
Require Import Zdiv_def.
Local Open Scope Z_scope.
(** The definition and initial properties are now in file [Zdiv_def] *)
(** * Main division theorems *)
(** NB: many things are stated twice for compatibility reasons *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Zdiv_eucl_POS a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
intros b Hb a. apply Zgt_lt in Hb.
generalize (Zdiv_eucl_POS_eq a b Hb) (Zmod_POS_bound a b Hb).
destruct Zdiv_eucl_POS. auto.
Qed.
Theorem Z_div_mod :
forall a b:Z,
b > 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
intros a b Hb. apply Zgt_lt in Hb.
assert (Hb' : b<>0) by (now destruct b).
generalize (Zdiv_eucl_eq a b Hb') (Zmod_pos_bound a b Hb).
unfold Zmod. destruct Zdiv_eucl. auto.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Zabs r < Zabs b /\ Zsgn r <> - Zsgn b.
(* In the last formulation, [ Zsgn r <> - Zsgn b ] is less nice than saying
[ Zsgn r = Zsgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full :
forall a b:Z,
b <> 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
intros a b Hb.
generalize (Zdiv_eucl_eq a b Hb)
(Zmod_pos_bound a b) (Zmod_neg_bound a b).
unfold Zmod. destruct Zdiv_eucl as (q,r).
intros EQ POS NEG.
split; auto.
red; destruct b.
now destruct Hb. left; now apply POS. right; now apply NEG.
Qed.
(** The same results as before, stated separately in terms of Zdiv and Zmod *)
Lemma Z_mod_remainder : forall a b:Z, b<>0 -> Remainder (a mod b) b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Zdiv_eucl; tauto.
Qed.
Definition Z_mod_lt : forall a b:Z, b > 0 -> 0 <= a mod b < b
:= fun a b Hb => Zmod_pos_bound a b (Zgt_lt _ _ Hb).
Definition Z_mod_neg : forall a b:Z, b < 0 -> b < a mod b <= 0
:= Zmod_neg_bound.
Notation Z_div_mod_eq_full := Z_div_mod_eq_full (only parsing).
Lemma Z_div_mod_eq : forall a b:Z, b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros; apply Z_div_mod_eq_full; auto with zarith.
Qed.
Lemma Zmod_eq_full : forall a b:Z, b<>0 -> a mod b = a - (a/b)*b.
Proof. intros. rewrite Zmult_comm. now apply Z.mod_eq. Qed.
Lemma Zmod_eq : forall a b:Z, b>0 -> a mod b = a - (a/b)*b.
Proof. intros. apply Zmod_eq_full. now destruct b. Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Zdiv_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Implicit Arguments Zdiv_eucl_exist.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique :
forall b q1 q2 r1 r2:Z,
0 <= r1 < Zabs b -> 0 <= r2 < Zabs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof. exact Z.div_mod_unique. Qed.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof. exact Z.div_unique. Qed.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof. exact Z.mod_unique. Qed.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z_eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros. zero_or_not a. apply Z.div_1_r. Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof. exact Z.div_1_l. Qed.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof. exact Z.mod_1_l. Qed.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof. exact Z.div_same. Qed.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_mul. auto. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof. exact Z.div_mul. Qed.
(** * Order results about Zmod and Zdiv *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto with zarith. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof. intros. apply Z.div_lt; auto with zarith. Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof. exact Z.div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof. exact Z.mod_small. Qed.
(** [Zge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Zle_ge. apply Z.div_le_mono; auto with zarith. Qed.
(** Same, with [Zle]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto with zarith. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Zle_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Zmult_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; auto with zarith. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Zsgn (a/b) * Zsgn a * Zsgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z_div_pos (Zpos a) (Zpos b)); unfold Zdiv, Zdiv_eucl;
destruct Zdiv_eucl_POS as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros. zero_or_not c. apply Z.mod_add; auto. Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof. exact Z.div_add. Qed.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof. exact Z.div_add_l. Qed.
(** [Zopp] and [Zdiv], [Zmod].
Due to the choice of convention for our Euclidean division,
some of the relations about [Zopp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_l_z; auto. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_nz; auto. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros. rewrite (Zmult_comm c b); zero_or_not b.
rewrite (Zmult_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros. zero_or_not c. rewrite (Zmult_comm c b); zero_or_not b.
rewrite (Zmult_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros. zero_or_not b. rewrite (Zmult_comm b c); zero_or_not c.
rewrite (Zmult_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Section EqualityModulo.
Variable N:Z.
Definition eqm a b := (a mod N = b mod N).
Infix "==" := eqm (at level 70).
Lemma eqm_refl : forall a, a == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym : forall a b, a == b -> b == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans : forall a b c,
a == b -> b == c -> a == c.
Proof. unfold eqm; eauto with *. Qed.
Instance eqm_setoid : Equivalence eqm.
Proof.
constructor; [exact eqm_refl | exact eqm_sym | exact eqm_trans].
Qed.
Instance Zplus_eqm : Proper (eqm ==> eqm ==> eqm) Zplus.
Proof.
unfold eqm; repeat red; intros. rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Instance Zminus_eqm : Proper (eqm ==> eqm ==> eqm) Zminus.
Proof.
unfold eqm; repeat red; intros. rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Instance Zmult_eqm : Proper (eqm ==> eqm ==> eqm) Zmult.
Proof.
unfold eqm; repeat red; intros. rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Instance Zopp_eqm : Proper (eqm ==> eqm) Zopp.
Proof.
intros x y H. change ((-x)==(-y)) with ((0-x)==(0-y)). now rewrite H.
Qed.
Lemma Zmod_eqm : forall a, (a mod N) == a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Zmod and Zdiv are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
End EqualityModulo.
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros. zero_or_not b. rewrite Zmult_comm. zero_or_not c.
rewrite Zmult_comm. apply Z.div_div; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros. zero_or_not b. apply Z.div_mul_le; auto with zarith. Qed.
(** Zmod is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
intros. rewrite Z.mod_divide; trivial.
split; intros (c,Hc); exists c; auto.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zdiv2_div : forall a, Zdiv2 a = a/2.
Proof.
apply Z.div2_div.
Qed.
Lemma Zmod_odd : forall a, a mod 2 = if Zodd_bool a then 1 else 0.
Proof.
intros a. now rewrite <- Z.bit0_odd, <- Z.bit0_mod.
Qed.
Lemma Zmod_even : forall a, a mod 2 = if Zeven_bool a then 0 else 1.
Proof.
intros a. rewrite Zmod_odd, Zodd_even_bool. now destruct Zeven_bool.
Qed.
Lemma Zodd_mod : forall a, Zodd_bool a = Zeq_bool (a mod 2) 1.
Proof.
intros a. rewrite Zmod_odd. now destruct Zodd_bool.
Qed.
Lemma Zeven_mod : forall a, Zeven_bool a = Zeq_bool (a mod 2) 0.
Proof.
intros a. rewrite Zmod_even. now destruct Zeven_bool.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Zmod *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if Zgt_bool b r' then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if Zgt_bool b r' then r' else (r' - b)
| xH => if Zge_bool b 2 then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct: forall a b, Zmod_POS a b = (snd (Zdiv_eucl_POS a b)).
Proof.
intros a b; elim a; simpl; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
case (Zge_bool b 2); auto.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = Zmod a b.
Proof.
intros a b; unfold Zmod; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Zdiv_eucl_POS p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Zabs b}.
Proof.
intros b Hb a.
elim (Z_le_gt_dec 0 b); intro Hb'.
cut (b > 0); [ intro Hb'' | omega ].
rewrite Zabs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
cut (- b > 0); [ intro Hb'' | omega ].
elim (Zdiv_eucl_exist Hb'' a); intros qr.
elim qr; intros q r Hqr.
exists (- q, r).
elim Hqr; intros.
split.
rewrite <- Zmult_opp_comm; assumption.
rewrite Zabs_non_eq; [ assumption | omega ].
Qed.
Implicit Arguments Zdiv_eucl_extended.
(** * Division and modulo in Z agree with same in nat: *)
Require Import NPeano.
Lemma div_Zdiv (n m: nat): m <> O ->
Z_of_nat (n / m) = Z_of_nat n / Z_of_nat m.
Proof.
intros.
apply (Zdiv_unique _ _ _ (Z_of_nat (n mod m)%nat)).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- inj_mult, <- inj_plus.
now apply inj_eq, Nat.div_mod.
Qed.
Lemma mod_Zmod (n m: nat): m <> O ->
Z_of_nat (n mod m)%nat = (Z_of_nat n mod Z_of_nat m).
Proof.
intros.
apply (Zmod_unique _ _ (Z_of_nat n / Z_of_nat m)).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- div_Zdiv, <- inj_mult, <- inj_plus by trivial.
now apply inj_eq, Nat.div_mod.
Qed.
(** For compatibility *)
Notation Zdiv_eucl := Zdiv_eucl (only parsing).
Notation Zdiv := Zdiv (only parsing).
Notation Zmod := Zmod (only parsing).
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam and Mohammad
// Create Date: 20:22:39 10/24/2015
// Design Name: I2C Shift Register
// Module Name: ShiftRegisterI2C2015fall
// Summary: This module is used to both write data to I2C and read data from I2c
//////////////////////////////////////////////////////////////////////////////////
module ShiftRegisterI2C2015fall(SentData,Clock,Reset,ShiftIn,ShiftOrHold,WriteLoad,ReceivedData,ShiftOut,ClockI2C);
input [7:0] SentData;
input Clock;
input ClockI2C;
input Reset;
input ShiftIn;
input ShiftOrHold;
input WriteLoad;
output reg [7:0] ReceivedData;
output reg ShiftOut;
wire OneShotClockI2C;
NegClockedOneShot OneShotUnit1(ClockI2C, OneShotClockI2C, Reset, Clock) ;
always @ (posedge Clock)
if (Reset == 1) begin ShiftOut <= 0; ReceivedData <= 8'b0; end
else if (WriteLoad) begin
ReceivedData <= SentData;
ShiftOut <= SentData[7];
end
else case ({OneShotClockI2C, ShiftOrHold})
2'b01: begin
ReceivedData <={ReceivedData[6:0],ShiftIn};
ShiftOut <= ReceivedData[6];
end
endcase
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_never_unknown (clock, reset, enable, qualifier, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input qualifier;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NEVER_UNKNOWN";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_never_unknown_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_never_unknown_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_never_unknown_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_never_unknown
`endif
|
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