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////////////////////////////////////////////////////////////////////////////////
//
// Filename: axiluart
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: A basic AXI-Lite serial port controller. It has the same
// interface as the WBUART core in the same directory.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2020-2021, Gisselquist Technology, LLC
// {{{
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
// }}}
//
`default_nettype none
//
module axiluart #(
// {{{
// 4MB 8N1, when using 100MHz clock
parameter [30:0] INITIAL_SETUP = 31'd25,
//
// LGFLEN: The log (based two) of our FIFOs size. Maxes out
// at 10, representing a FIFO length of 1024.
parameter [3:0] LGFLEN = 4,
//
// HARDWARE_FLOW_CONTROL_PRESET controls whether or not we
// ignore the RTS/CTS signaling. If present, we only start
// transmitting if
parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1,
// Perform a simple/quick bounds check on the log FIFO length,
// to make sure its within the bounds we can support with our
// current interface.
localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN),
//
// Size of the AXI-lite bus. These are fixed, since 1) AXI-lite
// is fixed at a width of 32-bits by Xilinx def'n, and 2) since
// we only ever have 4 configuration words.
parameter C_AXI_ADDR_WIDTH = 4,
localparam C_AXI_DATA_WIDTH = 32,
parameter [0:0] OPT_SKIDBUFFER = 1'b0,
parameter [0:0] OPT_LOWPOWER = 0,
localparam ADDRLSB = $clog2(C_AXI_DATA_WIDTH)-3
// }}}
) (
// AXI-lite signaling
// {{{
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [2:0] S_AXI_AWPROT,
//
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
//
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
output wire [1:0] S_AXI_BRESP,
//
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [2:0] S_AXI_ARPROT,
//
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
// }}}
// UART signals
// {{{
input wire i_uart_rx,
output wire o_uart_tx,
//
// CTS is the "Clear-to-send" hardware flow control signal. We
// set it anytime our FIFO isn't full. Feel free to ignore
// this output if you do not wish to use flow control.
input wire i_cts_n,
//
// RTS is used for hardware flow control. According to
// Wikipedia, it should probably be renamed RTR for "ready to
// receive". It tell us whether or not the receiving hardware
// is ready to accept another byte. If low, the transmitter
// will pause.
//
// If you don't wish to use hardware flow control, just set
// HARDWARE_FLOW_CONTROL_PRESENT to 1'b0 and let the optimizer
// simply remove this logic.
output reg o_rts_n,
// }}}
// A series of outgoing interrupts to select from among
// {{{
output wire o_uart_rx_int,
output wire o_uart_tx_int,
output wire o_uart_rxfifo_int,
output wire o_uart_txfifo_int
// }}}
);
////////////////////////////////////////////////////////////////////////
//
// Register/wire signal declarations
//
////////////////////////////////////////////////////////////////////////
//
// {{{
wire i_reset = !S_AXI_ARESETN;
wire axil_write_ready;
wire [C_AXI_ADDR_WIDTH-ADDRLSB-1:0] awskd_addr;
//
wire [C_AXI_DATA_WIDTH-1:0] wskd_data;
wire [C_AXI_DATA_WIDTH/8-1:0] wskd_strb;
reg axil_bvalid;
//
wire axil_read_ready;
wire [C_AXI_ADDR_WIDTH-ADDRLSB-1:0] arskd_addr;
reg [C_AXI_DATA_WIDTH-1:0] axil_read_data;
reg axil_read_valid;
//
//
wire tx_busy;
//
reg [30:0] uart_setup;
//
wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
wire [7:0] rx_uart_data;
reg rx_uart_reset;
//
wire rx_empty_n, rx_fifo_err;
wire [7:0] rxf_axil_data;
wire [15:0] rxf_status;
reg rxf_axil_read;
reg r_rx_perr, r_rx_ferr;
//
wire [(LCLLGFLEN-1):0] check_cutoff;
wire [31:0] axil_rx_data;
//
wire tx_empty_n, txf_err, tx_break;
wire [7:0] tx_data;
wire [15:0] txf_status;
reg txf_axil_write, tx_uart_reset;
reg [7:0] txf_axil_data;
wire [31:0] axil_tx_data;
wire [31:0] axil_fifo_data;
//
reg [1:0] r_axil_addr;
reg r_preread;
reg [31:0] new_setup;
// }}}
////////////////////////////////////////////////////////////////////////
//
// AXI-lite signaling
//
////////////////////////////////////////////////////////////////////////
//
// {{{
//
// Write signaling
//
// {{{
generate if (OPT_SKIDBUFFER)
begin : SKIDBUFFER_WRITE
wire awskd_valid, wskd_valid;
skidbuffer #(.OPT_OUTREG(0),
.OPT_LOWPOWER(OPT_LOWPOWER),
.DW(C_AXI_ADDR_WIDTH-ADDRLSB))
axilawskid(//
.i_clk(S_AXI_ACLK), .i_reset(i_reset),
.i_valid(S_AXI_AWVALID), .o_ready(S_AXI_AWREADY),
.i_data(S_AXI_AWADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]),
.o_valid(awskd_valid), .i_ready(axil_write_ready),
.o_data(awskd_addr));
skidbuffer #(.OPT_OUTREG(0),
.OPT_LOWPOWER(OPT_LOWPOWER),
.DW(C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8))
axilwskid(//
.i_clk(S_AXI_ACLK), .i_reset(i_reset),
.i_valid(S_AXI_WVALID), .o_ready(S_AXI_WREADY),
.i_data({ S_AXI_WDATA, S_AXI_WSTRB }),
.o_valid(wskd_valid), .i_ready(axil_write_ready),
.o_data({ wskd_data, wskd_strb }));
assign axil_write_ready = awskd_valid && wskd_valid
&& (!S_AXI_BVALID || S_AXI_BREADY);
end else begin : SIMPLE_WRITES
reg axil_awready;
initial axil_awready = 1'b0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axil_awready <= 1'b0;
else
axil_awready <= !axil_awready
&& (S_AXI_AWVALID && S_AXI_WVALID)
&& (!S_AXI_BVALID || S_AXI_BREADY);
assign S_AXI_AWREADY = axil_awready;
assign S_AXI_WREADY = axil_awready;
assign awskd_addr = S_AXI_AWADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB];
assign wskd_data = S_AXI_WDATA;
assign wskd_strb = S_AXI_WSTRB;
assign axil_write_ready = axil_awready;
end endgenerate
initial axil_bvalid = 0;
always @(posedge S_AXI_ACLK)
if (i_reset)
axil_bvalid <= 0;
else if (axil_write_ready)
axil_bvalid <= 1;
else if (S_AXI_BREADY)
axil_bvalid <= 0;
assign S_AXI_BVALID = axil_bvalid;
assign S_AXI_BRESP = 2'b00;
// }}}
//
// Read signaling
//
// {{{
generate if (OPT_SKIDBUFFER)
begin : SKIDBUFFER_READ
wire arskd_valid;
skidbuffer #(.OPT_OUTREG(0),
.OPT_LOWPOWER(OPT_LOWPOWER),
.DW(C_AXI_ADDR_WIDTH-ADDRLSB))
axilarskid(//
.i_clk(S_AXI_ACLK), .i_reset(i_reset),
.i_valid(S_AXI_ARVALID), .o_ready(S_AXI_ARREADY),
.i_data(S_AXI_ARADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]),
.o_valid(arskd_valid), .i_ready(axil_read_ready),
.o_data(arskd_addr));
// High bandwidth reads
assign axil_read_ready = arskd_valid
&& (!r_preread || !axil_read_valid
|| S_AXI_RREADY);
end else begin : SIMPLE_READS
reg axil_arready;
initial axil_arready = 1;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axil_arready <= 1;
else if (S_AXI_ARVALID && S_AXI_ARREADY)
axil_arready <= 0;
else if (S_AXI_RVALID && S_AXI_RREADY)
axil_arready <= 1;
assign arskd_addr = S_AXI_ARADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB];
assign S_AXI_ARREADY = axil_arready;
assign axil_read_ready = (S_AXI_ARVALID && S_AXI_ARREADY);
end endgenerate
initial axil_read_valid = 1'b0;
always @(posedge S_AXI_ACLK)
if (i_reset)
axil_read_valid <= 1'b0;
else if (r_preread)
axil_read_valid <= 1'b1;
else if (S_AXI_RREADY)
axil_read_valid <= 1'b0;
assign S_AXI_RVALID = axil_read_valid;
assign S_AXI_RDATA = axil_read_data;
assign S_AXI_RRESP = 2'b00;
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// AXI-lite register logic
//
////////////////////////////////////////////////////////////////////////
//
// {{{
localparam [1:0] UART_SETUP = 2'b00,
UART_FIFO = 2'b01,
UART_RXREG = 2'b10,
UART_TXREG = 2'b11;
always @(*)
new_setup = apply_wstrb({1'b0,uart_setup},wskd_data,wskd_strb);
//
// The UART setup parameters: bits per byte, stop bits, parity, and
// baud rate are all captured within this uart_setup register.
//
initial uart_setup = INITIAL_SETUP
| ((HARDWARE_FLOW_CONTROL_PRESENT==1'b0)? 31'h40000000 : 0);
always @(posedge S_AXI_ACLK)
if ((axil_write_ready)&&(awskd_addr == UART_SETUP))
begin
uart_setup <= new_setup[30:0];
if (!HARDWARE_FLOW_CONTROL_PRESENT)
uart_setup[30] <= 1'b1;
end
/////////////////////////////////////////
//
// First, the UART receiver
// {{{
/////////////////////////////////////////
//
//
// Here's our UART receiver. Basically, it accepts our setup wires,
// the UART input, a clock, and a reset line, and produces outputs:
// a stb (true when new data is ready), and an 8-bit data out value
// valid when stb is high.
`ifdef FORMAL
(* anyseq *) reg w_rx_break, w_rx_perr, w_rx_ferr, w_ck_uart;
assign rx_break = w_rx_break;
assign w_rx_perr = w_rx_perr;
assign w_rx_ferr = w_rx_ferr;
assign ck_uart = w_ck_uart;
`else
`ifdef USE_LITE_UART
rxuartlite #(.CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]))
rx(S_AXI_ACLK, i_uart_rx, rx_stb, rx_uart_data);
assign rx_break = 1'b0;
assign rx_perr = 1'b0;
assign rx_ferr = 1'b0;
assign ck_uart = 1'b0;
`else
// The full receiver also produces a break value (true during a break
// cond.), and parity/framing error flags--also valid when stb is true.
rxuart #(.INITIAL_SETUP(INITIAL_SETUP)) rx(S_AXI_ACLK, (!S_AXI_ARESETN)||(rx_uart_reset),
uart_setup, i_uart_rx,
rx_stb, rx_uart_data, rx_break,
rx_perr, rx_ferr, ck_uart);
// The real trick is ... now that we have this extra data, what do we do
// with it?
`endif
`endif // FORMAL
// We place it into a receiver FIFO.
//
// Note that the FIFO will be cleared upon any reset: either if there's
// a UART break condition on the line, the receiver is in reset, or an
// external reset is issued.
//
// The FIFO accepts strobe and data from the receiver.
// We issue another wire to it (rxf_axil_read), true when we wish to
// read from the FIFO, and we get our data in rxf_axil_data. The FIFO
// outputs four status-type values: 1) is it non-empty, 2) is the FIFO
// over half full, 3) a 16-bit status register, containing info
// regarding how full the FIFO truly is, and 4) an error indicator.
ufifo #(.LGFLEN(LCLLGFLEN), .RXFIFO(1))
rxfifo(S_AXI_ACLK, (!S_AXI_ARESETN)||(rx_break)||(rx_uart_reset),
rx_stb, rx_uart_data,
rx_empty_n,
rxf_axil_read, rxf_axil_data,
rxf_status, rx_fifo_err);
assign o_uart_rxfifo_int = rxf_status[1];
// We produce four interrupts. One of the receive interrupts indicates
// whether or not the receive FIFO is non-empty. This should wake up
// the CPU.
assign o_uart_rx_int = rxf_status[0];
// The clear to send line, which may be ignored, but which we set here
// to be true any time the FIFO has fewer than N-2 items in it.
// Why not N-1? Because at N-1 we are totally full, but already so full
// that if the transmit end starts sending we won't have a location to
// receive it. (Transmit might've started on the next character by the
// time we set this--thus we need to set it to one, one character before
// necessary).
assign check_cutoff = -3;
always @(posedge S_AXI_ACLK)
o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT)
&&(!uart_setup[30])
&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff));
// If the bus requests that we read from the receive FIFO, we need to
// tell this to the receive FIFO. Note that because we are using a
// clock here, the output from the receive FIFO will necessarily be
// delayed by an extra clock.
initial rxf_axil_read = 1'b0;
always @(posedge S_AXI_ACLK)
rxf_axil_read<=(axil_read_ready)&&(arskd_addr[1:0]==UART_RXREG);
// Now, let's deal with those RX UART errors: both the parity and frame
// errors. As you may recall, these are valid only when rx_stb is
// valid, so we need to hold on to them until the user reads them via
// a UART read request..
initial r_rx_perr = 1'b0;
initial r_rx_ferr = 1'b0;
always @(posedge S_AXI_ACLK)
if ((rx_uart_reset)||(rx_break))
begin
// Clear the error
r_rx_perr <= 1'b0;
r_rx_ferr <= 1'b0;
end else if (axil_write_ready&&awskd_addr == UART_RXREG && wskd_strb[1])
begin
// Reset the error lines if a '1' is ever written to
// them, otherwise leave them alone.
//
r_rx_perr <= (r_rx_perr)&&(!wskd_data[9]);
r_rx_ferr <= (r_rx_ferr)&&(!wskd_data[10]);
end else if (rx_stb)
begin
// On an rx_stb, capture any parity or framing error
// indications. These aren't kept with the data rcvd,
// but rather kept external to the FIFO. As a result,
// if you get a parity or framing error, you will never
// know which data byte it was associated with.
// For now ... that'll work.
r_rx_perr <= (r_rx_perr)||(rx_perr);
r_rx_ferr <= (r_rx_ferr)||(rx_ferr);
end
initial rx_uart_reset = 1'b1;
always @(posedge S_AXI_ACLK)
if ((!S_AXI_ARESETN)||((axil_write_ready)&&(awskd_addr[1:0]== UART_SETUP) && (&wskd_strb)))
// The receiver reset, always set on a master reset
// request.
rx_uart_reset <= 1'b1;
else if (axil_write_ready&&(awskd_addr[1:0]==UART_RXREG)&&wskd_strb[1])
// Writes to the receive register will command a receive
// reset anytime bit[12] is set.
rx_uart_reset <= wskd_data[12];
else
rx_uart_reset <= 1'b0;
// Finally, we'll construct a 32-bit value from these various wires,
// to be returned over the bus on any read. These include the data
// that would be read from the FIFO, an error indicator set upon
// reading from an empty FIFO, a break indicator, and the frame and
// parity error signals.
assign axil_rx_data = { 16'h00,
3'h0, rx_fifo_err,
rx_break, rx_ferr, r_rx_perr, !rx_empty_n,
rxf_axil_data};
// }}}
/////////////////////////////////////////
//
// Then the UART transmitter
// {{{
/////////////////////////////////////////
//
// Unlike the receiver which goes from RXUART -> UFIFO -> WB, the
// transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build
// support for the transmitter, we start with the command to write data
// into the FIFO. In this case, we use the act of writing to the
// UART_TXREG address as our indication that we wish to write to the
// FIFO. Here, we create a write command line, and latch the data for
// the extra clock that it'll take so that the command and data can be
// both true on the same clock.
initial txf_axil_write = 1'b0;
always @(posedge S_AXI_ACLK)
begin
txf_axil_write <= (axil_write_ready)&&(awskd_addr == UART_TXREG)
&& wskd_strb[0];
txf_axil_data <= wskd_data[7:0];
end
// Transmit FIFO
//
// Most of this is just wire management. The TX FIFO is identical in
// implementation to the RX FIFO (theyre both UFIFOs), but the TX
// FIFO is fed from the WB and read by the transmitter. Some key
// differences to note: we reset the transmitter on any request for a
// break. We read from the FIFO any time the UART transmitter is idle.
// and ... we just set the values (above) for controlling writing into
// this.
ufifo #(.LGFLEN(LGFLEN), .RXFIFO(0))
txfifo(S_AXI_ACLK, (tx_break)||(tx_uart_reset),
txf_axil_write, txf_axil_data,
tx_empty_n,
(!tx_busy)&&(tx_empty_n), tx_data,
txf_status, txf_err);
// Let's create two transmit based interrupts from the FIFO for the CPU.
// The first will be true any time the FIFO has at least one open
// position within it.
assign o_uart_tx_int = txf_status[0];
// The second will be true any time the FIFO is less than half
// full, allowing us a change to always keep it (near) fully
// charged.
assign o_uart_txfifo_int = txf_status[1];
`ifndef USE_LITE_UART
// Break logic
//
// A break in a UART controller is any time the UART holds the line
// low for an extended period of time. Here, we capture the
// wskd_data[9] wire, on writes, as an indication we wish to break.
// As long as you write unsigned characters to the interface, this
// will never be true unless you wish it to be true. Be aware, though,
// writing a valid value to the interface will bring it out of the
// break condition.
reg r_tx_break;
initial r_tx_break = 1'b0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
r_tx_break <= 1'b0;
else if (axil_write_ready &&(awskd_addr[1:0]== UART_TXREG) &&
wskd_strb[1])
r_tx_break <= wskd_data[9];
assign tx_break = r_tx_break;
`else
assign tx_break = 1'b0;
`endif
// TX-Reset logic
//
// This is nearly identical to the RX reset logic above. Basically,
// any time someone writes to bit [12] the transmitter will go through
// a reset cycle. Keep bit [12] low, and everything will proceed as
// normal.
initial tx_uart_reset = 1'b1;
always @(posedge S_AXI_ACLK)
if ((!S_AXI_ARESETN)||((axil_write_ready)&&(awskd_addr == UART_SETUP)))
tx_uart_reset <= 1'b1;
else if ((axil_write_ready)&&(awskd_addr[1:0]== UART_TXREG) && wskd_strb[1])
tx_uart_reset <= wskd_data[12];
else
tx_uart_reset <= 1'b0;
`ifdef FORMAL
(* anyseq *) reg w_uart_tx, w_tx_busy;
assign tx_busy = w_uart_tx;
assign o_uart_tx = w_uart_tx;
`else
`ifdef USE_LITE_UART
txuartlite #(.CLOCKS_PER_BAUD(INITIAL_SETUP[23:0])) tx(S_AXI_ACLK, (tx_empty_n), tx_data,
o_uart_tx, tx_busy);
`else
wire cts_n;
assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n);
// Finally, the UART transmitter module itself. Note that we haven't
// connected the reset wire. Transmitting is as simple as setting
// the stb value (here set to tx_empty_n) and the data. When these
// are both set on the same clock that tx_busy is low, the transmitter
// will move on to the next data byte. Really, the only thing magical
// here is that tx_empty_n wire--thus, if there's anything in the FIFO,
// we read it here. (You might notice above, we register a read any
// time (tx_empty_n) and (!tx_busy) are both true---the condition for
// starting to transmit a new byte.)
txuart #(.INITIAL_SETUP(INITIAL_SETUP)) tx(S_AXI_ACLK, 1'b0, uart_setup,
r_tx_break, (tx_empty_n), tx_data,
cts_n, o_uart_tx, tx_busy);
`endif
`endif // FORMAL
// Now that we are done with the chain, pick some wires for the user
// to read on any read of the transmit port.
//
// This port is different from reading from the receive port, since
// there are no side effects. (Reading from the receive port advances
// the receive FIFO, here only writing to the transmit port advances the
// transmit FIFO--hence the read values are free for ... whatever.)
// We choose here to provide information about the transmit FIFO
// (txf_err, txf_half_full, txf_full_n), information about the current
// voltage on the line (o_uart_tx)--and even the voltage on the receive
// line (ck_uart), as well as our current setting of the break and
// whether or not we are actively transmitting.
assign axil_tx_data = { 16'h00,
i_cts_n, txf_status[1:0], txf_err,
ck_uart, o_uart_tx, tx_break, (tx_busy|txf_status[0]),
(tx_busy|txf_status[0])?txf_axil_data:8'b00};
// }}}
/////////////////////////////////////////
//
// FIFO return
// {{{
/////////////////////////////////////////
//
// Each of the FIFO's returns a 16 bit status value. This value tells
// us both how big the FIFO is, as well as how much of the FIFO is in
// use. Let's merge those two status words together into a word we
// can use when reading about the FIFO.
assign axil_fifo_data = { txf_status, rxf_status };
// }}}
/////////////////////////////////////////
//
// Final read register
// {{{
/////////////////////////////////////////
//
// You may recall from above that reads take two clocks. Hence, we
// need to delay the address decoding for a clock until the data is
// ready. We do that here.
initial r_preread = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
r_preread <= 0;
else if (axil_read_ready)
r_preread <= 1;
else if (!S_AXI_RVALID || S_AXI_RREADY)
r_preread <= 0;
always @(posedge S_AXI_ACLK)
if (axil_read_ready)
r_axil_addr <= arskd_addr;
// Finally, set the return data. This data must be valid on the same
// clock S_AXI_RVALID is high. On all other clocks, it is
// irrelelant--since no one cares, no one is reading it, it gets lost
// in the mux in the interconnect, etc. For this reason, we can just
// simplify our logic.
always @(posedge S_AXI_ACLK)
if (!S_AXI_RVALID || S_AXI_RREADY)
begin
casez(r_axil_addr)
UART_SETUP: axil_read_data <= { 1'b0, uart_setup };
UART_FIFO: axil_read_data <= axil_fifo_data;
UART_RXREG: axil_read_data <= axil_rx_data;
UART_TXREG: axil_read_data <= axil_tx_data;
endcase
if (OPT_LOWPOWER && !r_preread)
axil_read_data <= 0;
end
// }}}
function [C_AXI_DATA_WIDTH-1:0] apply_wstrb;
input [C_AXI_DATA_WIDTH-1:0] prior_data;
input [C_AXI_DATA_WIDTH-1:0] new_data;
input [C_AXI_DATA_WIDTH/8-1:0] wstrb;
integer k;
for(k=0; k<C_AXI_DATA_WIDTH/8; k=k+1)
begin
apply_wstrb[k*8 +: 8]
= wstrb[k] ? new_data[k*8 +: 8] : prior_data[k*8 +: 8];
end
endfunction
// }}}
////////////////////////////////////////////////////////////////////////
//
// Veri1ator lint-check
// {{{
// Verilator lint_off UNUSED
wire unused;
assign unused = &{ 1'b0, S_AXI_AWPROT, S_AXI_ARPROT,
S_AXI_ARADDR[ADDRLSB-1:0],
S_AXI_AWADDR[ADDRLSB-1:0], new_setup[31] };
// Verilator lint_on UNUSED
// }}}
`ifdef FORMAL
////////////////////////////////////////////////////////////////////////
//
// Formal properties used in verfiying this core
//
////////////////////////////////////////////////////////////////////////
//
// {{{
reg f_past_valid;
initial f_past_valid = 0;
always @(posedge S_AXI_ACLK)
f_past_valid <= 1;
////////////////////////////////////////////////////////////////////////
//
// The AXI-lite control interface
//
////////////////////////////////////////////////////////////////////////
//
// {{{
localparam F_AXIL_LGDEPTH = 4;
wire [F_AXIL_LGDEPTH-1:0] faxil_rd_outstanding,
faxil_wr_outstanding,
faxil_awr_outstanding;
faxil_slave #(
// {{{
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.F_LGDEPTH(F_AXIL_LGDEPTH),
.F_AXI_MAXWAIT(4),
.F_AXI_MAXDELAY(4),
.F_AXI_MAXRSTALL(3),
.F_OPT_COVER_BURST(4)
// }}}
) faxil(
// {{{
.i_clk(S_AXI_ACLK), .i_axi_reset_n(S_AXI_ARESETN),
//
.i_axi_awvalid(S_AXI_AWVALID),
.i_axi_awready(S_AXI_AWREADY),
.i_axi_awaddr( S_AXI_AWADDR),
.i_axi_awcache(4'h0),
.i_axi_awprot( S_AXI_AWPROT),
//
.i_axi_wvalid(S_AXI_WVALID),
.i_axi_wready(S_AXI_WREADY),
.i_axi_wdata( S_AXI_WDATA),
.i_axi_wstrb( S_AXI_WSTRB),
//
.i_axi_bvalid(S_AXI_BVALID),
.i_axi_bready(S_AXI_BREADY),
.i_axi_bresp( S_AXI_BRESP),
//
.i_axi_arvalid(S_AXI_ARVALID),
.i_axi_arready(S_AXI_ARREADY),
.i_axi_araddr( S_AXI_ARADDR),
.i_axi_arcache(4'h0),
.i_axi_arprot( S_AXI_ARPROT),
//
.i_axi_rvalid(S_AXI_RVALID),
.i_axi_rready(S_AXI_RREADY),
.i_axi_rdata( S_AXI_RDATA),
.i_axi_rresp( S_AXI_RRESP),
//
.f_axi_rd_outstanding(faxil_rd_outstanding),
.f_axi_wr_outstanding(faxil_wr_outstanding),
.f_axi_awr_outstanding(faxil_awr_outstanding)
// }}}
);
always @(*)
if (OPT_SKIDBUFFER)
begin
assert(faxil_awr_outstanding== (S_AXI_BVALID ? 1:0)
+(S_AXI_AWREADY ? 0:1));
assert(faxil_wr_outstanding == (S_AXI_BVALID ? 1:0)
+(S_AXI_WREADY ? 0:1));
assert(faxil_rd_outstanding == (S_AXI_RVALID ? 1:0)
+ (r_preread ? 1:0) +(S_AXI_ARREADY ? 0:1));
end else begin
assert(faxil_wr_outstanding == (S_AXI_BVALID ? 1:0));
assert(faxil_awr_outstanding == faxil_wr_outstanding);
assert(faxil_rd_outstanding == (S_AXI_RVALID ? 1:0)
+ (r_preread ? 1:0));
assert(S_AXI_ARREADY == (!S_AXI_RVALID && !r_preread));
end
`ifdef VERIFIC
assert property (@(posedge S_AXI_ACLK)
disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY))
S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_SETUP
|=> r_preread && r_axil_addr == UART_SETUP
##1 S_AXI_RVALID && axil_read_data
== { 1'b0, $past(uart_setup) });
assert property (@(posedge S_AXI_ACLK)
disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY))
S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2] == UART_FIFO
|=> r_preread && r_axil_addr == UART_FIFO
##1 S_AXI_RVALID && axil_read_data == $past(axil_fifo_data));
assert property (@(posedge S_AXI_ACLK)
disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY))
S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_RXREG
|=> r_preread && r_axil_addr == UART_RXREG
##1 S_AXI_RVALID && axil_read_data == $past(axil_rx_data));
assert property (@(posedge S_AXI_ACLK)
disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY))
S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_TXREG
|=> r_preread && r_axil_addr == UART_TXREG
##1 S_AXI_RVALID && axil_read_data == $past(axil_tx_data));
`endif
//
// Check that our low-power only logic works by verifying that anytime
// S_AXI_RVALID is inactive, then the outgoing data is also zero.
//
always @(*)
if (OPT_LOWPOWER && !S_AXI_RVALID)
assert(S_AXI_RDATA == 0);
// }}}
////////////////////////////////////////////////////////////////////////
//
// Cover checks
//
////////////////////////////////////////////////////////////////////////
//
// {{{
// While there are already cover properties in the formal property
// set above, you'll probably still want to cover something
// application specific here
// }}}
// }}}
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD1_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD1_PP_SYMBOL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD1_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_FUNCTIONAL_PP_V |
`include "../rtl/button_debounce.v"
`default_nettype none
`timescale 1ms/1us
module tb_button_debounce;
parameter CLK_FREQ = 1_000;
parameter DEBOUNCE_HZ = 40;
reg clk;
reg rst_n;
reg btn_in;
wire btn_out;
button_debounce
#(
.CLK_FREQ(CLK_FREQ),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
) _button_debounce
(
.clk ( clk ),
.rst_n ( rst_n ),
.btn_in ( btn_in ),
.btn_out ( btn_out )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_button_debounce.vcd");
$dumpvars(0, tb_button_debounce);
#1 rst_n=1'bx;clk=1'bx;btn_in=1'bx;
#(CLK_PERIOD) rst_n=1;
#(CLK_PERIOD) rst_n=0;clk=0;
#(CLK_PERIOD) rst_n=1;
#(CLK_PERIOD) btn_in=0;
#(CLK_PERIOD*50);
$finish(2);
end
always begin
#(CLK_PERIOD*10) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
#(CLK_PERIOD/100) btn_in=~btn_in;
end
endmodule
`default_nettype wire
|
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.61
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
* - Duty Cycle Corrector is not modeled
* - Temperature Compensated Self Refresh is not modeled
* - DLL off mode is not modeled.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
* TDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* Improved checking of DQS during writes.
* Added true BL4 operation.
* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
* Added ODTS Readout.
* Replaced tZQCL with tZQinit and tZQoper
* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
* Added tRFC checking for Refresh to Power-Down Re-Entry.
* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
* Added Clock Frequency Change during Precharge Power-Down.
* Added -125x speed grades.
* Fixed tRCD checking during Write.
* 1.00 JMK 05/11/07 Initial release
* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
* Removed temp sensor readout from MPR
* Updated initialization sequence
* Updated timing parameters
* 1.20 JMK 09/05/07 Updated clock frequency change
* Added ddr3_dimm module
* 1.30 JMK 01/23/08 Updated timing parameters
* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
* Added multi-chip package model support in ddr3_mcp.v
* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW
*****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
// model flags
// `define MODEL_PASR
module ddr3_model (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`include "ddr3_model_parameters.vh"
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS#
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_jbusr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_jbusr(bscan_hiz_l_out ,bscan_update_dr_out ,
bscan_clock_dr_out ,bscan_shift_dr_out ,bscan_clock_dr_in ,
jbus_n_ref_res ,jbi_io_j_ad ,j_adp ,bscan_mode_ctl_out ,
j_req1_out_l ,j_pack5 ,j_pack4 ,j_pack1 ,j_pack0 ,j_req4_in_l ,
dtl_r_vref ,jbus_p_ref_res ,jbi_io_j_req1_out_en ,j_adtype ,
jbi_io_j_req1_out_l ,serial_in ,j_ad ,spare_jbusr_pin ,
jbi_io_config_dtl ,io_jbi_j_ad ,ps_select ,bypass_enable ,
ps_select_out ,bypass_enable_out ,clk_jbusr_cken ,jbus_gclk ,
jbus_grst_l ,jbus_arst_l ,jbus_gdbginit_l ,jbus_adbginit_l ,
pad_jbusr_se ,j_req0_out_l ,bscan_shift_dr_in ,j_par ,
pad_jbusr_sscan_out ,jbi_io_j_err ,tclk ,serial_out ,pad_jbusr_so ,
pad_jbusr_si ,pad_jbusr_bsi ,vddo ,jbi_io_j_adtype ,rst_val_up ,
bscan_hiz_l_in ,jbi_io_j_ad_en ,sel_bypass ,bscan_mode_ctl_in ,
bscan_update_dr_in ,rst_val_dn ,rst_io_l ,por_l ,jbi_io_j_adp_en ,
jbi_io_j_pack0 ,jbi_io_j_pack1 ,jbi_io_j_pack0_en ,
jbi_io_j_pack1_en ,spare_jbusr_data ,jbi_io_j_adtype_en ,hard_rst_l
,jbi_io_j_par_en ,jbi_io_j_adp ,jbi_io_j_req0_out_en ,
ctu_io_sscan_update ,jbi_io_j_req0_out_l ,jbi_io_j_par ,
pad_jbusr_sscan_in ,ctu_io_sscan_se ,j_req5_in_l ,spare_jbusr_oe ,
spare_jbusr_to_core ,j_rst_l ,pad_jbusr_bso ,j_err ,io_jbi_j_adtype
,io_jbi_j_pack4 ,io_jbi_j_adp ,io_jbi_j_pack5 ,io_jbi_j_req5_in_l
,io_jbi_j_req4_in_l ,io_jbi_j_par ,io_jbi_j_rst_l ,jbusr_jbusl_cbu
,jbusr_jbusl_cbd ,ctu_global_snap );
output [2:0] j_pack1 ;
output [2:0] j_pack0 ;
output [56:0] io_jbi_j_ad ;
output [56:0] serial_out ;
output [0:0] spare_jbusr_to_core ;
output [7:0] io_jbi_j_adtype ;
output [2:0] io_jbi_j_pack4 ;
output [3:0] io_jbi_j_adp ;
output [2:0] io_jbi_j_pack5 ;
output [8:1] jbusr_jbusl_cbu ;
output [8:1] jbusr_jbusl_cbd ;
input [56:0] jbi_io_j_ad ;
input [2:0] j_pack5 ;
input [2:0] j_pack4 ;
input [56:0] serial_in ;
input [1:0] jbi_io_config_dtl ;
input [7:0] jbi_io_j_adtype ;
input [1:0] jbi_io_j_ad_en ;
input [2:0] jbi_io_j_pack0 ;
input [2:0] jbi_io_j_pack1 ;
input [0:0] spare_jbusr_data ;
input [3:0] jbi_io_j_adp ;
input [0:0] spare_jbusr_oe ;
inout [3:0] j_adp ;
inout [7:0] j_adtype ;
inout [56:0] j_ad ;
inout [0:0] spare_jbusr_pin ;
output bscan_hiz_l_out ;
output bscan_update_dr_out ;
output bscan_clock_dr_out ;
output bscan_shift_dr_out ;
output bscan_mode_ctl_out ;
output j_req1_out_l ;
output ps_select_out ;
output bypass_enable_out ;
output j_req0_out_l ;
output pad_jbusr_sscan_out ;
output pad_jbusr_so ;
output pad_jbusr_bso ;
output j_err ;
output io_jbi_j_req5_in_l ;
output io_jbi_j_req4_in_l ;
output io_jbi_j_par ;
output io_jbi_j_rst_l ;
input bscan_clock_dr_in ;
input jbus_n_ref_res ;
input j_req4_in_l ;
input jbus_p_ref_res ;
input jbi_io_j_req1_out_en ;
input jbi_io_j_req1_out_l ;
input ps_select ;
input bypass_enable ;
input clk_jbusr_cken ;
input jbus_gclk ;
input jbus_grst_l ;
input jbus_arst_l ;
input jbus_gdbginit_l ;
input jbus_adbginit_l ;
input pad_jbusr_se ;
input bscan_shift_dr_in ;
input jbi_io_j_err ;
input tclk ;
input pad_jbusr_si ;
input pad_jbusr_bsi ;
input vddo ;
input rst_val_up ;
input bscan_hiz_l_in ;
input sel_bypass ;
input bscan_mode_ctl_in ;
input bscan_update_dr_in ;
input rst_val_dn ;
input rst_io_l ;
input por_l ;
input jbi_io_j_adp_en ;
input jbi_io_j_pack0_en ;
input jbi_io_j_pack1_en ;
input jbi_io_j_adtype_en ;
input hard_rst_l ;
input jbi_io_j_par_en ;
input jbi_io_j_req0_out_en ;
input ctu_io_sscan_update ;
input jbi_io_j_req0_out_l ;
input jbi_io_j_par ;
input pad_jbusr_sscan_in ;
input ctu_io_sscan_se ;
input j_req5_in_l ;
input j_rst_l ;
input ctu_global_snap ;
inout dtl_r_vref ;
inout j_par ;
supply1 vdd ;
supply0 vss ;
wire [1:0] _spare_jbusr_to_core ;
wire [1:0] config_dtl ;
wire [1:0] scan_mode0 ;
wire [1:0] net743 ;
wire [7:0] net710 ;
wire [1:0] net697 ;
wire [1:0] hiz_l3 ;
wire [1:0] net657 ;
wire [7:0] net593 ;
wire [7:0] net595 ;
wire [7:0] net596 ;
wire [1:0] clock_dr3 ;
wire [1:0] net693 ;
wire [7:0] net594 ;
wire [1:0] scan_mode4 ;
wire [1:0] clock_dr_end ;
wire [8:2] bscan ;
wire [7:0] net669 ;
wire [7:0] net0478 ;
wire [8:1] cbd0 ;
wire [8:1] cbd1 ;
wire [1:0] upd_dr3 ;
wire [1:0] net667 ;
wire [1:0] shift_dr_end ;
wire [7:0] net672 ;
wire [7:0] net670 ;
wire [7:0] net671 ;
wire [7:0] net0480 ;
wire [1:0] net663 ;
wire [1:0] net867 ;
wire [8:1] mid2 ;
wire [8:1] cbu0 ;
wire [7:0] net872 ;
wire [1:0] hiz_l_end ;
wire [8:1] mid0 ;
wire [1:0] bypass_en_mid ;
wire [1:0] net863 ;
wire [1:0] mid5 ;
wire [8:1] mid1 ;
wire [8:1] cbu1 ;
wire [8:1] cbd ;
wire [8:2] scan ;
wire [1:0] mid9 ;
wire [1:0] net579 ;
wire [8:1] mid3 ;
wire [1:0] shift_dr4 ;
wire [7:0] net874 ;
wire [1:0] net738 ;
wire [8:1] l1 ;
wire [8:1] l0 ;
wire [1:0] net581 ;
wire [1:0] mid15 ;
wire [1:0] shift_dr0 ;
wire [1:0] net734 ;
wire [1:0] ps_select_end ;
wire [1:0] l5 ;
wire [8:1] l3 ;
wire [8:1] l2 ;
wire [1:0] l9 ;
wire [7:0] dnr ;
wire [1:0] net740 ;
wire [7:0] net709 ;
wire [8:1] cbu ;
wire [1:0] l13 ;
wire [1:0] net700 ;
wire [7:0] net707 ;
wire [1:0] mode_ctl_end ;
wire [1:0] net585 ;
wire [7:0] upr ;
wire [1:0] mid11 ;
wire [1:0] l17 ;
wire [7:0] net748 ;
wire [1:0] hiz_l1 ;
wire [7:0] net746 ;
wire [1:0] net591 ;
wire [7:0] net708 ;
wire [7:0] net747 ;
wire [7:0] net745 ;
wire [1:0] clock_dr1 ;
wire [1:0] scan_mode2 ;
wire [1:0] net658 ;
wire [1:0] hiz_l5 ;
wire [1:0] net858 ;
wire [1:0] clock_dr5 ;
wire [1:0] net660 ;
wire [1:0] net860 ;
wire [1:0] upd_dr5 ;
wire [1:0] net470 ;
wire [1:0] upd_dr1 ;
wire [1:0] net664 ;
wire [1:0] net864 ;
wire [1:0] net870 ;
wire [1:0] bypass_en_end ;
wire [1:0] shift_dr2 ;
wire [1:0] mid16 ;
wire [1:0] net582 ;
wire [1:0] l10 ;
wire [1:0] l6 ;
wire [1:0] net701 ;
wire [1:0] net488 ;
wire [1:0] net484 ;
wire [1:0] l18 ;
wire [1:0] net586 ;
wire [1:0] mid12 ;
wire [1:0] net705 ;
wire [1:0] net490 ;
wire [1:0] hiz_l2 ;
wire [1:0] scan_mode1 ;
wire [1:0] clock_dr2 ;
wire [1:0] net498 ;
wire [1:0] net698 ;
wire [1:0] scan_mode5 ;
wire [1:0] update_dr_end ;
wire [1:0] upd_dr4 ;
wire [1:0] upd_dr0 ;
wire [1:0] net731 ;
wire [1:0] net739 ;
wire [1:0] shift_dr3 ;
wire [1:0] net735 ;
wire [1:0] hiz_l0 ;
wire [1:0] clock_dr0 ;
wire [1:0] net659 ;
wire [1:0] hiz_l4 ;
wire [1:0] clock_dr4 ;
wire [1:0] net655 ;
wire [1:0] scan_mode3 ;
wire [1:0] net661 ;
wire [1:0] net861 ;
wire [1:0] upd_dr2 ;
wire [1:0] net865 ;
wire [1:0] shift_dr5 ;
wire [1:0] bypass_en_m ;
wire [1:0] mid13 ;
wire [1:0] shift_dr1 ;
wire [1:0] net502 ;
wire [1:0] l7 ;
wire [1:0] net702 ;
wire [1:0] l11 ;
wire [1:0] net587 ;
wire [1:0] l15 ;
wire [1:0] l19 ;
wire [1:0] net583 ;
wire [1:0] net699 ;
wire [1:0] net695 ;
wire [1:0] tout ;
wire [1:0] ps_select_m ;
wire [1:0] net736 ;
wire [1:0] net662 ;
wire [1:0] net862 ;
wire [1:0] net472 ;
wire [1:0] net866 ;
wire [1:0] net482 ;
wire [1:0] l4 ;
wire [1:0] mid18 ;
wire [1:0] l12 ;
wire [1:0] l8 ;
wire [1:0] mid10 ;
wire [1:0] l16 ;
wire [1:0] net486 ;
wire [1:0] net588 ;
wire [1:0] net492 ;
wire [1:0] net584 ;
wire [1:0] net696 ;
wire [1:0] net737 ;
wire [1:0] ps_select_mid ;
wire [1:0] net733 ;
wire clk ;
wire net402 ;
wire net0384 ;
wire deltabitd ;
wire net396 ;
wire net0387 ;
wire net398 ;
wire sscan ;
wire deltabitu ;
wire jbusrsebuf ;
wire rstiolbuf ;
wire dbginit_l ;
wire reset_l ;
wire pad_jbusr_header_si ;
wire pad_jbusr_header_so ;
wire net439 ;
wire por_l_buf ;
wire rstvaldnbuf ;
wire rstvalupbuf ;
wire net0433 ;
wire net01028 ;
wire net01029 ;
wire se_buf_imp ;
wire net0390 ;
wire scan_imp ;
wire sscan_updatebuf ;
wire selbypassbuf ;
assign spare_jbusr_to_core[0] = _spare_jbusr_to_core[0] ;
bw_u1_buf_15x I225_1_ (
.z (shift_dr0[1] ),
.a (bscan_shift_dr_in ) );
bw_u1_buf_15x I228 (
.z (bscan_mode_ctl_out ),
.a (mode_ctl_end[0] ) );
bw_u1_buf_40x I165_6_ (
.z (cbu1[6] ),
.a (cbu[6] ) );
bw_u1_buf_15x I229 (
.z (bscan_update_dr_out ),
.a (update_dr_end[0] ) );
bw_u1_buf_40x I166_8_ (
.z (cbu0[8] ),
.a (cbu[8] ) );
bw_u1_buf_15x I201_0_ (
.z (net486[1] ),
.a (net484[1] ) );
bw_io_dtl_padx12 I2 (
.ps_select_buf ({ps_select_end } ),
.bypass_en_buf ({bypass_en_end } ),
.serial_out ({serial_out[56:45] } ),
.serial_in ({serial_in[56:45] } ),
.to_core ({io_jbi_j_ad[56:45] } ),
.pad ({j_ad[56:45] } ),
.por_l_buf ({net866[0] ,net866[1] } ),
.oe_buf ({net867[0] ,net867[1] } ),
.reset_l_buf ({net865[0] ,net865[1] } ),
.update_dr_buf ({update_dr_end } ),
.cbu1 ({net872[0] ,net872[1] ,net872[2] ,net872[3] ,
net872[4] ,net872[5] ,net872[6] ,net872[7] } ),
.cbd1 ({net874[0] ,net874[1] ,net874[2] ,net874[3] ,
net874[4] ,net874[5] ,net874[6] ,net874[7] } ),
.up_open_buf ({net858[0] ,net858[1] } ),
.mode_ctl_buf ({mode_ctl_end } ),
.se_buf ({net861[0] ,net861[1] } ),
.shift_dr_buf ({shift_dr_end } ),
.hiz_l_buf ({hiz_l_end } ),
.rst_val_dn_buf ({net863[0] ,net863[1] } ),
.down_25_buf ({net870[0] ,net870[1] } ),
.data ({jbi_io_j_ad[56:45] } ),
.clock_dr_buf ({clock_dr_end } ),
.rst_val_up_buf ({net862[0] ,net862[1] } ),
.sel_bypass_buf ({net860[0] ,net860[1] } ),
.cbu0 ({net0480[0] ,net0480[1] ,net0480[2] ,net0480[3] ,
net0480[4] ,net0480[5] ,net0480[6] ,net0480[7] } ),
.cbd0 ({net0478[0] ,net0478[1] ,net0478[2] ,net0478[3] ,
net0478[4] ,net0478[5] ,net0478[6] ,net0478[7] } ),
.rst_io_l_buf ({net864[0] ,net864[1] } ),
.bso (bscan[8] ),
.so (scan[8] ),
.bsr_si (pad_jbusr_bsi ),
.si (pad_jbusr_header_so ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_r_vref ) );
bw_io_dtl_padx12 I61 (
.ps_select_buf ({net482[0] ,net482[1] } ),
.bypass_en_buf ({net484[0] ,net484[1] } ),
.serial_out ({serial_out[19:8] } ),
.serial_in ({serial_in[19:8] } ),
.to_core ({io_jbi_j_ad[19:8] } ),
.pad ({j_ad[19:8] } ),
.por_l_buf ({net587[0] ,net587[1] } ),
.oe_buf ({net588[0] ,net588[1] } ),
.reset_l_buf ({net586[0] ,net586[1] } ),
.update_dr_buf ({upd_dr2 } ),
.cbu1 ({net593[0] ,net593[1] ,net593[2] ,net593[3] ,
net593[4] ,net593[5] ,net593[6] ,net593[7] } ),
.cbd1 ({net595[0] ,net595[1] ,net595[2] ,net595[3] ,
net595[4] ,net595[5] ,net595[6] ,net595[7] } ),
.up_open_buf ({net579[0] ,net579[1] } ),
.mode_ctl_buf ({scan_mode2 } ),
.se_buf ({net582[0] ,net582[1] } ),
.shift_dr_buf ({shift_dr2 } ),
.hiz_l_buf ({hiz_l2 } ),
.rst_val_dn_buf ({net584[0] ,net584[1] } ),
.down_25_buf ({net591[0] ,net591[1] } ),
.data ({jbi_io_j_ad[19:8] } ),
.clock_dr_buf ({clock_dr2 } ),
.rst_val_up_buf ({net583[0] ,net583[1] } ),
.sel_bypass_buf ({net581[0] ,net581[1] } ),
.cbu0 ({net594[0] ,net594[1] ,net594[2] ,net594[3] ,
net594[4] ,net594[5] ,net594[6] ,net594[7] } ),
.cbd0 ({net596[0] ,net596[1] ,net596[2] ,net596[3] ,
net596[4] ,net596[5] ,net596[6] ,net596[7] } ),
.rst_io_l_buf ({net585[0] ,net585[1] } ),
.bso (bscan[3] ),
.so (scan[3] ),
.bsr_si (bscan[4] ),
.si (scan[4] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_r_vref ) );
bw_u1_buf_15x I205_0_ (
.z (bypass_en_end[0] ),
.a (net492[1] ) );
bw_u1_buf_15x I230 (
.z (bscan_clock_dr_out ),
.a (clock_dr_end[0] ) );
bw_io_dtl_rpt I3 (
.out18 ({net858[0] ,net858[1] } ),
.in7 ({l7 } ),
.in0 ({l0 } ),
.out16 ({net860[0] ,net860[1] } ),
.in3 ({l3 } ),
.in2 ({l2 } ),
.in6 ({l6 } ),
.out19 ({update_dr_end } ),
.in8 ({l8 } ),
.in9 ({l9 } ),
.out15 ({net861[0] ,net861[1] } ),
.out17 ({shift_dr_end } ),
.in1 ({l1 } ),
.in4 ({l4 } ),
.in5 ({l5 } ),
.out13 ({net862[0] ,net862[1] } ),
.in10 ({l10 } ),
.in11 ({l11 } ),
.in12 ({l12 } ),
.in13 ({l13 } ),
.in19 ({l19 } ),
.in18 ({l18 } ),
.in17 ({l17 } ),
.in16 ({l16 } ),
.in15 ({l15 } ),
.out6 ({hiz_l_end } ),
.out7 ({mode_ctl_end } ),
.out8 ({net867[0] ,net867[1] } ),
.out9 ({net866[0] ,net866[1] } ),
.out10 ({net865[0] ,net865[1] } ),
.out11 ({net864[0] ,net864[1] } ),
.out12 ({net863[0] ,net863[1] } ),
.out0 ({net0478[0] ,net0478[1] ,net0478[2] ,net0478[3] ,
net0478[4] ,net0478[5] ,net0478[6] ,net0478[7] } ),
.out1 ({net874[0] ,net874[1] ,net874[2] ,net874[3] ,
net874[4] ,net874[5] ,net874[6] ,net874[7] } ),
.out2 ({net0480[0] ,net0480[1] ,net0480[2] ,net0480[3] ,
net0480[4] ,net0480[5] ,net0480[6] ,net0480[7] } ),
.out3 ({net872[0] ,net872[1] ,net872[2] ,net872[3] ,
net872[4] ,net872[5] ,net872[6] ,net872[7] } ),
.out4 ({clock_dr_end } ),
.out5 ({net870[0] ,net870[1] } ) );
bw_u1_buf_15x I209_0_ (
.z (net490[1] ),
.a (ps_select_m[0] ) );
bw_u1_buf_15x I231 (
.z (bscan_shift_dr_out ),
.a (shift_dr_end[0] ) );
bw_u1_buf_30x I149_5_ (
.z (cbd1[5] ),
.a (cbd[5] ) );
bw_u1_buf_30x I148_3_ (
.z (cbd0[3] ),
.a (cbd[3] ) );
bw_io_dtl_rpt I63 (
.out18 ({net655[0] ,net655[1] } ),
.in7 ({scan_mode1 } ),
.in0 ({net596[0] ,net596[1] ,net596[2] ,net596[3] ,
net596[4] ,net596[5] ,net596[6] ,net596[7] } ),
.out16 ({net657[0] ,net657[1] } ),
.in3 ({net593[0] ,net593[1] ,net593[2] ,net593[3] ,
net593[4] ,net593[5] ,net593[6] ,net593[7] } ),
.in2 ({net594[0] ,net594[1] ,net594[2] ,net594[3] ,
net594[4] ,net594[5] ,net594[6] ,net594[7] } ),
.in6 ({hiz_l1 } ),
.out19 ({upd_dr2 } ),
.in8 ({net588[0] ,net588[1] } ),
.in9 ({net587[0] ,net587[1] } ),
.out15 ({net658[0] ,net658[1] } ),
.out17 ({shift_dr2 } ),
.in1 ({net595[0] ,net595[1] ,net595[2] ,net595[3] ,
net595[4] ,net595[5] ,net595[6] ,net595[7] } ),
.in4 ({clock_dr1 } ),
.in5 ({net591[0] ,net591[1] } ),
.out13 ({net659[0] ,net659[1] } ),
.in10 ({net586[0] ,net586[1] } ),
.in11 ({net585[0] ,net585[1] } ),
.in12 ({net584[0] ,net584[1] } ),
.in13 ({net583[0] ,net583[1] } ),
.in19 ({upd_dr1 } ),
.in18 ({net579[0] ,net579[1] } ),
.in17 ({shift_dr1 } ),
.in16 ({net581[0] ,net581[1] } ),
.in15 ({net582[0] ,net582[1] } ),
.out6 ({hiz_l2 } ),
.out7 ({scan_mode2 } ),
.out8 ({net664[0] ,net664[1] } ),
.out9 ({net663[0] ,net663[1] } ),
.out10 ({net662[0] ,net662[1] } ),
.out11 ({net661[0] ,net661[1] } ),
.out12 ({net660[0] ,net660[1] } ),
.out0 ({net672[0] ,net672[1] ,net672[2] ,net672[3] ,
net672[4] ,net672[5] ,net672[6] ,net672[7] } ),
.out1 ({net671[0] ,net671[1] ,net671[2] ,net671[3] ,
net671[4] ,net671[5] ,net671[6] ,net671[7] } ),
.out2 ({net670[0] ,net670[1] ,net670[2] ,net670[3] ,
net670[4] ,net670[5] ,net670[6] ,net670[7] } ),
.out3 ({net669[0] ,net669[1] ,net669[2] ,net669[3] ,
net669[4] ,net669[5] ,net669[6] ,net669[7] } ),
.out4 ({clock_dr2 } ),
.out5 ({net667[0] ,net667[1] } ) );
bw_io_dtl_rpt I4 (
.out18 ({l18 } ),
.in7 ({scan_mode5 } ),
.in0 ({cbd0 } ),
.out16 ({l16 } ),
.in3 ({cbu1 } ),
.in2 ({cbu0 } ),
.in6 ({hiz_l5 } ),
.out19 ({l19 } ),
.in8 ({jbi_io_j_ad_en[1] ,jbi_io_j_ad_en[1] } ),
.in9 ({{2 {por_l_buf }} } ),
.out15 ({l15 } ),
.out17 ({l17 } ),
.in1 ({cbd1 } ),
.in4 ({clock_dr5 } ),
.in5 ({config_dtl[1] ,config_dtl[1] } ),
.out13 ({l13 } ),
.in10 ({{2 {reset_l }} } ),
.in11 ({{2 {rstiolbuf }} } ),
.in12 ({{2 {rstvaldnbuf }} } ),
.in13 ({{2 {rstvalupbuf }} } ),
.in19 ({upd_dr5 } ),
.in18 ({config_dtl[0] ,config_dtl[0] } ),
.in17 ({shift_dr5 } ),
.in16 ({{2 {selbypassbuf }} } ),
.in15 ({{2 {jbusrsebuf }} } ),
.out6 ({l6 } ),
.out7 ({l7 } ),
.out8 ({l8 } ),
.out9 ({l9 } ),
.out10 ({l10 } ),
.out11 ({l11 } ),
.out12 ({l12 } ),
.out0 ({l0 } ),
.out1 ({l1 } ),
.out2 ({l2 } ),
.out3 ({l3 } ),
.out4 ({l4 } ),
.out5 ({l5 } ) );
bw_io_dtl_padx12 I5 (
.ps_select_buf ({net490[0] ,net490[1] } ),
.bypass_en_buf ({net492[0] ,net492[1] } ),
.serial_out ({serial_out[44:33] } ),
.serial_in ({serial_in[44:33] } ),
.to_core ({io_jbi_j_ad[44:33] } ),
.pad ({j_ad[44:33] } ),
.por_l_buf ({l9 } ),
.oe_buf ({l8 } ),
.reset_l_buf ({l10 } ),
.update_dr_buf ({l19 } ),
.cbu1 ({l3 } ),
.cbd1 ({l1 } ),
.up_open_buf ({l18 } ),
.mode_ctl_buf ({l7 } ),
.se_buf ({l15 } ),
.shift_dr_buf ({l17 } ),
.hiz_l_buf ({l6 } ),
.rst_val_dn_buf ({l12 } ),
.down_25_buf ({l5 } ),
.data ({jbi_io_j_ad[44:33] } ),
.clock_dr_buf ({l4 } ),
.rst_val_up_buf ({l13 } ),
.sel_bypass_buf ({l16 } ),
.cbu0 ({l2 } ),
.cbd0 ({l0 } ),
.rst_io_l_buf ({l11 } ),
.bso (bscan[7] ),
.so (scan[7] ),
.bsr_si (bscan[8] ),
.si (scan[8] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_r_vref ) );
bw_io_dtl_rpt I64 (
.out18 ({net693[0] ,net693[1] } ),
.in7 ({scan_mode0 } ),
.in0 ({net672[0] ,net672[1] ,net672[2] ,net672[3] ,
net672[4] ,net672[5] ,net672[6] ,net672[7] } ),
.out16 ({net695[0] ,net695[1] } ),
.in3 ({net669[0] ,net669[1] ,net669[2] ,net669[3] ,
net669[4] ,net669[5] ,net669[6] ,net669[7] } ),
.in2 ({net670[0] ,net670[1] ,net670[2] ,net670[3] ,
net670[4] ,net670[5] ,net670[6] ,net670[7] } ),
.in6 ({hiz_l0 } ),
.out19 ({upd_dr1 } ),
.in8 ({{2 {jbi_io_j_adtype_en }} } ),
.in9 ({net663[0] ,net663[1] } ),
.out15 ({net696[0] ,net696[1] } ),
.out17 ({shift_dr1 } ),
.in1 ({net671[0] ,net671[1] ,net671[2] ,net671[3] ,
net671[4] ,net671[5] ,net671[6] ,net671[7] } ),
.in4 ({clock_dr0 } ),
.in5 ({net667[0] ,net667[1] } ),
.out13 ({net697[0] ,net697[1] } ),
.in10 ({net662[0] ,net662[1] } ),
.in11 ({net661[0] ,net661[1] } ),
.in12 ({net660[0] ,net660[1] } ),
.in13 ({net659[0] ,net659[1] } ),
.in19 ({upd_dr0 } ),
.in18 ({net655[0] ,net655[1] } ),
.in17 ({shift_dr0 } ),
.in16 ({net657[0] ,net657[1] } ),
.in15 ({net658[0] ,net658[1] } ),
.out6 ({hiz_l1 } ),
.out7 ({scan_mode1 } ),
.out8 ({net702[0] ,net702[1] } ),
.out9 ({net701[0] ,net701[1] } ),
.out10 ({net700[0] ,net700[1] } ),
.out11 ({net699[0] ,net699[1] } ),
.out12 ({net698[0] ,net698[1] } ),
.out0 ({net710[0] ,net710[1] ,net710[2] ,net710[3] ,
net710[4] ,net710[5] ,net710[6] ,net710[7] } ),
.out1 ({net709[0] ,net709[1] ,net709[2] ,net709[3] ,
net709[4] ,net709[5] ,net709[6] ,net709[7] } ),
.out2 ({net708[0] ,net708[1] ,net708[2] ,net708[3] ,
net708[4] ,net708[5] ,net708[6] ,net708[7] } ),
.out3 ({net707[0] ,net707[1] ,net707[2] ,net707[3] ,
net707[4] ,net707[5] ,net707[6] ,net707[7] } ),
.out4 ({clock_dr1 } ),
.out5 ({net705[0] ,net705[1] } ) );
bw_u1_buf_15x I211_0_ (
.z (ps_select_m[0] ),
.a (ps_select_mid[0] ) );
bw_u1_buf_15x I251_1_ (
.z (jbusr_jbusl_cbu[1] ),
.a (net0480[7] ) );
bw_u1_buf_15x I250_7_ (
.z (jbusr_jbusl_cbd[7] ),
.a (net0478[1] ) );
bw_u1_buf_15x I225_0_ (
.z (shift_dr0[0] ),
.a (bscan_shift_dr_in ) );
bw_u1_buf_40x I165_5_ (
.z (cbu1[5] ),
.a (cbu[5] ) );
bw_clk_cl_jbusr_jbus I69 (
.cluster_grst_l (reset_l ),
.so (net0433 ),
.dbginit_l (dbginit_l ),
.rclk (clk ),
.si (pad_jbusr_header_si ),
.se (jbusrsebuf ),
.adbginit_l (jbus_adbginit_l ),
.gdbginit_l (jbus_gdbginit_l ),
.arst_l (jbus_arst_l ),
.grst_l (jbus_grst_l ),
.cluster_cken (clk_jbusr_cken ),
.gclk (jbus_gclk ) );
bw_u1_buf_40x I166_7_ (
.z (cbu0[7] ),
.a (cbu[7] ) );
bw_io_dtl_drv I140 (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.pad (dtl_r_vref ),
.sel_data_n (vss ),
.pad_up (vss ),
.pad_dn_l (vdd ),
.pad_dn25_l (vdd ),
.por (vss ),
.bsr_up (vss ),
.bsr_dn_l (vdd ),
.bsr_dn25_l (vdd ),
.vddo (vddo ) );
bw_u1_buf_15x I202_1_ (
.z (bypass_en_mid[1] ),
.a (net486[0] ) );
bw_u1_buf_30x I148_2_ (
.z (cbd0[2] ),
.a (cbd[2] ) );
bw_u1_buf_30x I149_4_ (
.z (cbd1[4] ),
.a (cbd[4] ) );
bw_u1_buf_30x I144 (
.z (pad_jbusr_bso ),
.a (net0390 ) );
bw_u1_buf_15x I212_1_ (
.z (net498[0] ),
.a (net470[0] ) );
bw_u1_buf_15x I250_6_ (
.z (jbusr_jbusl_cbd[6] ),
.a (net0478[2] ) );
bw_u1_buf_30x I243 (
.z (pad_jbusr_sscan_out ),
.a (net398 ) );
bw_dtl_impctl_pulldown I145 (
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.z ({cbd } ),
.to_csr ({dnr } ),
.rclk (clk ),
.se (se_buf_imp ),
.hard_reset_n (hard_rst_l ),
.we_csr (vss ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.ctu_io_sscan_in (pad_jbusr_sscan_in ),
.tclk (tclk ),
.ctu_global_snap (ctu_global_snap ),
.so (net402 ),
.si (scan[7] ),
.io_ctu_sscan_out (sscan ),
.ctu_io_sscan_update (sscan_updatebuf ),
.deltabit (deltabitd ),
.clk_dis_l (vdd ),
.vddo (vddo ),
.pad (jbus_n_ref_res ) );
bw_u1_buf_15x I197_1_ (
.z (net482[0] ),
.a (net502[0] ) );
bw_u1_buf_15x I216_1_ (
.z (net472[0] ),
.a (ps_select ) );
bw_u1_buf_15x I251_8_ (
.z (jbusr_jbusl_cbu[8] ),
.a (net0480[0] ) );
bw_u1_buf_15x I147 (
.z (pad_jbusr_header_si ),
.a (pad_jbusr_si ) );
bw_u1_buf_15x I226_1_ (
.z (upd_dr0[1] ),
.a (bscan_update_dr_in ) );
bw_u1_buf_40x I166_6_ (
.z (cbu0[6] ),
.a (cbu[6] ) );
bw_u1_buf_40x I165_4_ (
.z (cbu1[4] ),
.a (cbu[4] ) );
bw_u1_buf_20x I249 (
.z (pad_jbusr_header_so ),
.a (net0433 ) );
bw_u1_buf_15x I202_0_ (
.z (bypass_en_mid[0] ),
.a (net486[1] ) );
bw_u1_buf_30x I148_1_ (
.z (cbd0[1] ),
.a (cbd[1] ) );
bw_u1_scanl_2x I152 (
.so (net0387 ),
.sd (net01028 ),
.ck (net0384 ) );
bw_u1_buf_30x I149_3_ (
.z (cbd1[3] ),
.a (cbd[3] ) );
bw_u1_scanl_2x I153 (
.so (net0390 ),
.sd (net01029 ),
.ck (bscan_clock_dr_in ) );
bw_u1_buf_15x I212_0_ (
.z (net498[1] ),
.a (net470[1] ) );
bw_u1_buf_15x I253 (
.z (por_l_buf ),
.a (por_l ) );
bw_u1_buf_15x I252_1_ (
.z (config_dtl[1] ),
.a (jbi_io_config_dtl[1] ) );
bw_u1_buf_15x I250_5_ (
.z (jbusr_jbusl_cbd[5] ),
.a (net0478[3] ) );
bw_u1_buf_30x I155 (
.z (pad_jbusr_so ),
.a (net0387 ) );
bw_u1_buf_15x I197_0_ (
.z (net482[1] ),
.a (net502[1] ) );
bw_u1_buf_15x I216_0_ (
.z (net472[1] ),
.a (ps_select ) );
bw_u1_buf_15x I254 (
.z (selbypassbuf ),
.a (sel_bypass ) );
bw_u1_buf_15x I251_7_ (
.z (jbusr_jbusl_cbu[7] ),
.a (net0480[1] ) );
bw_u1_buf_15x I255 (
.z (rstvalupbuf ),
.a (rst_val_up ) );
bw_u1_buf_15x I256 (
.z (rstvaldnbuf ),
.a (rst_val_dn ) );
bw_u1_buf_15x I88 (
.z (bscan_hiz_l_out ),
.a (hiz_l_end[0] ) );
bw_u1_buf_15x I257 (
.z (rstiolbuf ),
.a (rst_io_l ) );
bw_u1_buf_15x I226_0_ (
.z (upd_dr0[0] ),
.a (bscan_update_dr_in ) );
bw_u1_buf_15x I258 (
.z (sscan_updatebuf ),
.a (ctu_io_sscan_update ) );
bw_u1_buf_40x I166_5_ (
.z (cbu0[5] ),
.a (cbu[5] ) );
bw_u1_buf_40x I165_3_ (
.z (cbu1[3] ),
.a (cbu[3] ) );
bw_u1_buf_15x I259 (
.z (jbusrsebuf ),
.a (pad_jbusr_se ) );
bw_u1_buf_15x I203_1_ (
.z (ps_select_mid[1] ),
.a (net488[0] ) );
bw_u1_buf_30x I149_2_ (
.z (cbd1[2] ),
.a (cbd[2] ) );
bw_dtl_impctl_pullup I162 (
.from_csr ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.z ({cbu } ),
.to_csr ({upr } ),
.rclk (clk ),
.ctu_io_sscan_update (sscan_updatebuf ),
.ctu_global_snap (ctu_global_snap ),
.tclk (tclk ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.si (net439 ),
.we_csr (vss ),
.se (se_buf_imp ),
.ctu_io_sscan_in (sscan ),
.hard_reset_n (hard_rst_l ),
.clk_dis_l (vdd ),
.vddo (vddo ),
.so_l (net396 ),
.imped_shadow_so (net398 ),
.deltabit (deltabitu ),
.pad (jbus_p_ref_res ) );
bw_u1_ckbuf_1p5x I260 (
.clk (net0384 ),
.rclk (clk ) );
bw_u1_buf_30x I148_8_ (
.z (cbd0[8] ),
.a (cbd[8] ) );
bw_u1_buf_15x I213_1_ (
.z (net502[0] ),
.a (net472[0] ) );
bw_u1_buf_15x I252_0_ (
.z (config_dtl[0] ),
.a (jbi_io_config_dtl[0] ) );
bw_u1_buf_15x I251_6_ (
.z (jbusr_jbusl_cbu[6] ),
.a (net0480[2] ) );
bw_u1_buf_15x I250_4_ (
.z (jbusr_jbusl_cbd[4] ),
.a (net0478[4] ) );
bw_u1_buf_15x I198_1_ (
.z (net484[0] ),
.a (net498[0] ) );
bw_u1_buf_15x I217_1_ (
.z (net470[0] ),
.a (bypass_enable ) );
bw_io_dtl_rpt I17 (
.out18 ({mid18 } ),
.in7 ({scan_mode4 } ),
.in0 ({cbd0 } ),
.out16 ({mid16 } ),
.in3 ({cbu1 } ),
.in2 ({cbu0 } ),
.in6 ({hiz_l4 } ),
.out19 ({upd_dr5 } ),
.in8 ({vss ,vss } ),
.in9 ({{2 {por_l_buf }} } ),
.out15 ({mid15 } ),
.out17 ({shift_dr5 } ),
.in1 ({cbd1 } ),
.in4 ({clock_dr4 } ),
.in5 ({config_dtl[1] ,config_dtl[1] } ),
.out13 ({mid13 } ),
.in10 ({{2 {reset_l }} } ),
.in11 ({{2 {rstiolbuf }} } ),
.in12 ({{2 {rstvaldnbuf }} } ),
.in13 ({{2 {rstvalupbuf }} } ),
.in19 ({upd_dr4 } ),
.in18 ({config_dtl[0] ,config_dtl[0] } ),
.in17 ({shift_dr4 } ),
.in16 ({{2 {selbypassbuf }} } ),
.in15 ({{2 {jbusrsebuf }} } ),
.out6 ({hiz_l5 } ),
.out7 ({scan_mode5 } ),
.out8 ({tout } ),
.out9 ({mid9 } ),
.out10 ({mid10 } ),
.out11 ({mid11 } ),
.out12 ({mid12 } ),
.out0 ({mid0 } ),
.out1 ({mid1 } ),
.out2 ({mid2 } ),
.out3 ({mid3 } ),
.out4 ({clock_dr5 } ),
.out5 ({mid5 } ) );
bw_u1_buf_15x I223_1_ (
.z (clock_dr0[1] ),
.a (bscan_clock_dr_in ) );
bw_u1_buf_40x I165_2_ (
.z (cbu1[2] ),
.a (cbu[2] ) );
bw_u1_buf_15x I227_1_ (
.z (scan_mode0[1] ),
.a (bscan_mode_ctl_in ) );
bw_u1_buf_40x I166_4_ (
.z (cbu0[4] ),
.a (cbu[4] ) );
bw_u1_buf_15x I203_0_ (
.z (ps_select_mid[0] ),
.a (net488[1] ) );
bw_u1_buf_30x I171 (
.z (se_buf_imp ),
.a (jbusrsebuf ) );
bw_io_dtl_rpt I20 (
.out18 ({net731[0] ,net731[1] } ),
.in7 ({scan_mode3 } ),
.in0 ({mid0 } ),
.out16 ({net733[0] ,net733[1] } ),
.in3 ({mid3 } ),
.in2 ({mid2 } ),
.in6 ({hiz_l3 } ),
.out19 ({upd_dr4 } ),
.in8 ({jbi_io_j_ad_en[0] ,jbi_io_j_ad_en[0] } ),
.in9 ({mid9 } ),
.out15 ({net734[0] ,net734[1] } ),
.out17 ({shift_dr4 } ),
.in1 ({mid1 } ),
.in4 ({clock_dr3 } ),
.in5 ({mid5 } ),
.out13 ({net735[0] ,net735[1] } ),
.in10 ({mid10 } ),
.in11 ({mid11 } ),
.in12 ({mid12 } ),
.in13 ({mid13 } ),
.in19 ({upd_dr3 } ),
.in18 ({mid18 } ),
.in17 ({shift_dr3 } ),
.in16 ({mid16 } ),
.in15 ({mid15 } ),
.out6 ({hiz_l4 } ),
.out7 ({scan_mode4 } ),
.out8 ({net740[0] ,net740[1] } ),
.out9 ({net739[0] ,net739[1] } ),
.out10 ({net738[0] ,net738[1] } ),
.out11 ({net737[0] ,net737[1] } ),
.out12 ({net736[0] ,net736[1] } ),
.out0 ({net748[0] ,net748[1] ,net748[2] ,net748[3] ,
net748[4] ,net748[5] ,net748[6] ,net748[7] } ),
.out1 ({net747[0] ,net747[1] ,net747[2] ,net747[3] ,
net747[4] ,net747[5] ,net747[6] ,net747[7] } ),
.out2 ({net746[0] ,net746[1] ,net746[2] ,net746[3] ,
net746[4] ,net746[5] ,net746[6] ,net746[7] } ),
.out3 ({net745[0] ,net745[1] ,net745[2] ,net745[3] ,
net745[4] ,net745[5] ,net745[6] ,net745[7] } ),
.out4 ({clock_dr4 } ),
.out5 ({net743[0] ,net743[1] } ) );
bw_u1_buf_30x I149_1_ (
.z (cbd1[1] ),
.a (cbd[1] ) );
bw_u1_buf_30x I148_7_ (
.z (cbd0[7] ),
.a (cbd[7] ) );
bw_u1_buf_10x I173 (
.z (net439 ),
.a (net402 ) );
bw_u1_inv_8x I174 (
.z (scan_imp ),
.a (net396 ) );
bw_u1_buf_15x I213_0_ (
.z (net502[1] ),
.a (net472[1] ) );
bw_u1_buf_15x I251_5_ (
.z (jbusr_jbusl_cbu[5] ),
.a (net0480[3] ) );
bw_u1_buf_15x I250_3_ (
.z (jbusr_jbusl_cbd[3] ),
.a (net0478[5] ) );
bw_u1_buf_15x I198_0_ (
.z (net484[1] ),
.a (net498[1] ) );
bw_u1_buf_15x I217_0_ (
.z (net470[1] ),
.a (bypass_enable ) );
bw_u1_buf_15x I223_0_ (
.z (clock_dr0[0] ),
.a (bscan_clock_dr_in ) );
bw_u1_buf_40x I165_1_ (
.z (cbu1[1] ),
.a (cbu[1] ) );
bw_u1_buf_15x I227_0_ (
.z (scan_mode0[0] ),
.a (bscan_mode_ctl_in ) );
bw_u1_buf_40x I166_3_ (
.z (cbu0[3] ),
.a (cbu[3] ) );
bw_u1_buf_15x I200_1_ (
.z (net488[0] ),
.a (net482[0] ) );
bw_u1_buf_15x I204_1_ (
.z (ps_select_end[1] ),
.a (net490[0] ) );
bw_u1_buf_15x I208_1_ (
.z (net492[0] ),
.a (bypass_en_m[1] ) );
bw_u1_buf_30x I148_6_ (
.z (cbd0[6] ),
.a (cbd[6] ) );
bw_u1_buf_30x I149_8_ (
.z (cbd1[8] ),
.a (cbd[8] ) );
bw_u1_buf_15x I210_1_ (
.z (bypass_en_m[1] ),
.a (bypass_en_mid[1] ) );
bw_u1_buf_15x I250_2_ (
.z (jbusr_jbusl_cbd[2] ),
.a (net0478[6] ) );
bw_u1_buf_15x I251_4_ (
.z (jbusr_jbusl_cbu[4] ),
.a (net0480[4] ) );
bw_zckgatedcap_h I156_2_ (
.ld (net0384 ) );
bw_u1_buf_15x I206 (
.z (ps_select_out ),
.a (ps_select_end[0] ) );
bw_io_dtl_padx12 I37 (
.ps_select_buf ({net488[0] ,net488[1] } ),
.bypass_en_buf ({net486[0] ,net486[1] } ),
.serial_out ({serial_out[31:20] } ),
.serial_in ({serial_in[31:20] } ),
.to_core ({io_jbi_j_ad[31:20] } ),
.pad ({j_ad[31:20] } ),
.por_l_buf ({net739[0] ,net739[1] } ),
.oe_buf ({net740[0] ,net740[1] } ),
.reset_l_buf ({net738[0] ,net738[1] } ),
.update_dr_buf ({upd_dr3 } ),
.cbu1 ({net745[0] ,net745[1] ,net745[2] ,net745[3] ,
net745[4] ,net745[5] ,net745[6] ,net745[7] } ),
.cbd1 ({net747[0] ,net747[1] ,net747[2] ,net747[3] ,
net747[4] ,net747[5] ,net747[6] ,net747[7] } ),
.up_open_buf ({net731[0] ,net731[1] } ),
.mode_ctl_buf ({scan_mode3 } ),
.se_buf ({net734[0] ,net734[1] } ),
.shift_dr_buf ({shift_dr3 } ),
.hiz_l_buf ({hiz_l3 } ),
.rst_val_dn_buf ({net736[0] ,net736[1] } ),
.down_25_buf ({net743[0] ,net743[1] } ),
.data ({jbi_io_j_ad[31:20] } ),
.clock_dr_buf ({clock_dr3 } ),
.rst_val_up_buf ({net735[0] ,net735[1] } ),
.sel_bypass_buf ({net733[0] ,net733[1] } ),
.cbu0 ({net746[0] ,net746[1] ,net746[2] ,net746[3] ,
net746[4] ,net746[5] ,net746[6] ,net746[7] } ),
.cbd0 ({net748[0] ,net748[1] ,net748[2] ,net748[3] ,
net748[4] ,net748[5] ,net748[6] ,net748[7] } ),
.rst_io_l_buf ({net737[0] ,net737[1] } ),
.bso (bscan[4] ),
.so (scan[4] ),
.bsr_si (bscan[5] ),
.si (scan[5] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_r_vref ) );
bw_u1_buf_15x I224_1_ (
.z (hiz_l0[1] ),
.a (bscan_hiz_l_in ) );
bw_u1_buf_40x I166_2_ (
.z (cbu0[2] ),
.a (cbu[2] ) );
bw_io_dtl_pad_r3 I38 (
.cbu0 ({cbu0 } ),
.cbu1 ({cbu1 } ),
.spare_out ({_spare_jbusr_to_core } ),
.down_25_buf ({config_dtl[1] ,config_dtl[1] } ),
.cbd0 ({cbd0 } ),
.cbd1 ({cbd1 } ),
.spare_in ({spare_jbusr_data[0] } ),
.por_l_buf ({{2 {por_l_buf }} } ),
.rst_io_l_buf ({{2 {rstiolbuf }} } ),
.shift_dr_buf ({shift_dr5 } ),
.hiz_l_buf ({hiz_l5 } ),
.rst_val_dn_buf ({{2 {rstvaldnbuf }} } ),
.update_dr_buf ({upd_dr5 } ),
.spare_en ({spare_jbusr_oe[0] } ),
.se_buf ({{2 {jbusrsebuf }} } ),
.up_open_buf ({config_dtl[0] ,config_dtl[0] } ),
.mode_ctl_buf ({scan_mode5 } ),
.rst_val_up_buf ({{2 {rstvalupbuf }} } ),
.reset_l_buf ({{2 {reset_l }} } ),
.clock_dr_buf ({clock_dr5 } ),
.spare ({j_req1_out_l ,spare_jbusr_pin[0] } ),
.sel_bypass_buf ({{2 {selbypassbuf }} } ),
.j_ad (j_ad[32] ),
.req1_oe (jbi_io_j_req1_out_en ),
.j_rst_l (j_rst_l ),
.j_req1_i (jbi_io_j_req1_out_l ),
.j_par_data (jbi_io_j_par ),
.serial_in (serial_in[32] ),
.j_par_en (jbi_io_j_par_en ),
.serial_out (serial_out[32] ),
.ps_select (ps_select_m[0] ),
.bypass_enable (bypass_en_m[0] ),
.bso (bscan[6] ),
.j_err_i (jbi_io_j_err ),
.jad32 (io_jbi_j_ad[32] ),
.jpar_o (io_jbi_j_par ),
.j_rst_l_o (io_jbi_j_rst_l ),
.so (scan[6] ),
.j_req5 (j_req5_in_l ),
.req5_l (io_jbi_j_req5_in_l ),
.j_req0 (j_req0_out_l ),
.j_err (j_err ),
.j_req4 (j_req4_in_l ),
.jpar (j_par ),
.j_req0_i (jbi_io_j_req0_out_l ),
.j_req0_en (jbi_io_j_req0_out_en ),
.vddo (vddo ),
.bsr_si (bscan[7] ),
.ref (dtl_r_vref ),
.req4_l (io_jbi_j_req4_in_l ),
.jad32_en (jbi_io_j_ad_en[1] ),
.jad32_data (jbi_io_j_ad[32] ),
.si (scan_imp ),
.clk (clk ) );
bw_u1_buf_40x I165_8_ (
.z (cbu1[8] ),
.a (cbu[8] ) );
bw_io_dtl_pad_pack12 I39 (
.se_buf ({mid15 } ),
.up_open_buf ({mid18 } ),
.down_25_buf ({mid5 } ),
.cbu1 ({mid3 } ),
.cbu0 ({mid2 } ),
.cbd0 ({mid0 } ),
.j_pack1 ({jbi_io_j_pack1 } ),
.rst_val_up_buf ({mid13 } ),
.j_pack0 ({jbi_io_j_pack0 } ),
.jpack5 ({j_pack5 } ),
.rst_val_dn_buf ({mid12 } ),
.pack5 ({io_jbi_j_pack5 } ),
.pack4 ({io_jbi_j_pack4 } ),
.update_dr_buf ({upd_dr4 } ),
.por_l_buf ({mid9 } ),
.rst_io_l_buf ({mid11 } ),
.hiz_l_buf ({hiz_l4 } ),
.reset_l_buf ({mid10 } ),
.sel_bypass_buf ({mid16 } ),
.clock_dr_buf ({clock_dr4 } ),
.cbd1 ({mid1 } ),
.mode_ctl_buf ({scan_mode4 } ),
.jpack4 ({j_pack4 } ),
.jpack1 ({j_pack1 } ),
.jpack0 ({j_pack0 } ),
.shift_dr_buf ({shift_dr4 } ),
.ref (dtl_r_vref ),
.si (scan[6] ),
.clk (clk ),
.vddo (vddo ),
.pack0_en (jbi_io_j_pack0_en ),
.pack1_en (jbi_io_j_pack1_en ),
.bsr_si (bscan[6] ),
.so (scan[5] ),
.bso (bscan[5] ) );
bw_u1_buf_15x I200_0_ (
.z (net488[1] ),
.a (net482[1] ) );
bw_u1_buf_15x I204_0_ (
.z (ps_select_end[0] ),
.a (net490[1] ) );
bw_io_dtl_padx8 I40 (
.update_dr_buf ({upd_dr0 } ),
.por_l_buf ({net701[0] ,net701[1] } ),
.shift_dr_buf ({shift_dr0 } ),
.rst_io_l_buf ({net699[0] ,net699[1] } ),
.reset_l_buf ({net700[0] ,net700[1] } ),
.mode_ctl_buf ({scan_mode0 } ),
.sel_bypass_buf ({net695[0] ,net695[1] } ),
.clock_dr_buf ({clock_dr0 } ),
.rst_val_up_buf ({net697[0] ,net697[1] } ),
.se_buf ({net696[0] ,net696[1] } ),
.oe_buf ({net702[0] ,net702[1] } ),
.up_open_buf ({net693[0] ,net693[1] } ),
.down_25_buf ({net705[0] ,net705[1] } ),
.cbu0 ({net708[0] ,net708[1] ,net708[2] ,net708[3] ,
net708[4] ,net708[5] ,net708[6] ,net708[7] } ),
.cbd0 ({net710[0] ,net710[1] ,net710[2] ,net710[3] ,
net710[4] ,net710[5] ,net710[6] ,net710[7] } ),
.data ({jbi_io_j_adtype } ),
.cbd1 ({net709[0] ,net709[1] ,net709[2] ,net709[3] ,
net709[4] ,net709[5] ,net709[6] ,net709[7] } ),
.cbu1 ({net707[0] ,net707[1] ,net707[2] ,net707[3] ,
net707[4] ,net707[5] ,net707[6] ,net707[7] } ),
.hiz_l_buf ({hiz_l0 } ),
.rst_val_dn_buf ({net698[0] ,net698[1] } ),
.pad ({j_adtype } ),
.to_core ({io_jbi_j_adtype } ),
.clk (clk ),
.vddo (vddo ),
.si (scan[2] ),
.bsr_si (bscan[2] ),
.ref (dtl_r_vref ),
.bso (net01029 ),
.so (net01028 ) );
bw_u1_buf_15x I208_0_ (
.z (net492[1] ),
.a (bypass_en_m[0] ) );
bw_u1_buf_30x I148_5_ (
.z (cbd0[5] ),
.a (cbd[5] ) );
bw_io_dtl_pad_adp I41 (
.serial_in ({serial_in[7:0] } ),
.serial_out ({serial_out[7:0] } ),
.ps_select_buf ({net502[0] ,net502[1] } ),
.bypass_en_buf ({net498[0] ,net498[1] } ),
.cbd0 ({net672[0] ,net672[1] ,net672[2] ,net672[3] ,
net672[4] ,net672[5] ,net672[6] ,net672[7] } ),
.cbu0 ({net670[0] ,net670[1] ,net670[2] ,net670[3] ,
net670[4] ,net670[5] ,net670[6] ,net670[7] } ),
.cbd1 ({net671[0] ,net671[1] ,net671[2] ,net671[3] ,
net671[4] ,net671[5] ,net671[6] ,net671[7] } ),
.cbu1 ({net669[0] ,net669[1] ,net669[2] ,net669[3] ,
net669[4] ,net669[5] ,net669[6] ,net669[7] } ),
.por_l_buf ({net663[0] ,net663[1] } ),
.rst_io_l_buf ({net661[0] ,net661[1] } ),
.shift_dr_buf ({shift_dr1 } ),
.hiz_l_buf ({hiz_l1 } ),
.rst_val_dn_buf ({net660[0] ,net660[1] } ),
.update_dr_buf ({upd_dr1 } ),
.reset_l_buf ({net662[0] ,net662[1] } ),
.mode_ctl_buf ({scan_mode1 } ),
.sel_bypass_buf ({net657[0] ,net657[1] } ),
.clock_dr_buf ({clock_dr1 } ),
.rst_val_up_buf ({net659[0] ,net659[1] } ),
.se_buf ({net658[0] ,net658[1] } ),
.up_open_buf ({net655[0] ,net655[1] } ),
.down_25_buf ({net667[0] ,net667[1] } ),
.data ({jbi_io_j_ad[7:0] } ),
.oe_buf ({net664[0] ,net664[1] } ),
.j_adp ({jbi_io_j_adp } ),
.to_core ({io_jbi_j_ad[7:0] } ),
.jadpout ({io_jbi_j_adp } ),
.pad ({j_ad[7:0] } ),
.jadp ({j_adp } ),
.vddo (vddo ),
.clk (clk ),
.ref (dtl_r_vref ),
.j_adp_en (jbi_io_j_adp_en ),
.si (scan[3] ),
.bsr_si (bscan[3] ),
.bso (bscan[2] ),
.so (scan[2] ) );
bw_u1_buf_30x I149_7_ (
.z (cbd1[7] ),
.a (cbd[7] ) );
bw_u1_buf_15x I210_0_ (
.z (bypass_en_m[0] ),
.a (bypass_en_mid[0] ) );
bw_u1_buf_15x I115 (
.z (bypass_enable_out ),
.a (bypass_en_end[0] ) );
bw_u1_buf_15x I250_1_ (
.z (jbusr_jbusl_cbd[1] ),
.a (net0478[7] ) );
bw_u1_buf_15x I251_3_ (
.z (jbusr_jbusl_cbu[3] ),
.a (net0480[5] ) );
bw_zckgatedcap_h I156_1_ (
.ld (net0384 ) );
bw_u1_buf_15x I224_0_ (
.z (hiz_l0[0] ),
.a (bscan_hiz_l_in ) );
bw_u1_buf_40x I166_1_ (
.z (cbu0[1] ),
.a (cbu[1] ) );
bw_u1_buf_40x I165_7_ (
.z (cbu1[7] ),
.a (cbu[7] ) );
bw_u1_buf_15x I201_1_ (
.z (net486[0] ),
.a (net484[0] ) );
bw_u1_buf_15x I205_1_ (
.z (bypass_en_end[1] ),
.a (net492[0] ) );
bw_u1_buf_15x I209_1_ (
.z (net490[0] ),
.a (ps_select_m[1] ) );
bw_u1_buf_30x I149_6_ (
.z (cbd1[6] ),
.a (cbd[6] ) );
bw_u1_buf_30x I148_4_ (
.z (cbd0[4] ),
.a (cbd[4] ) );
bw_u1_buf_15x I211_1_ (
.z (ps_select_m[1] ),
.a (ps_select_mid[1] ) );
bw_u1_buf_15x I251_2_ (
.z (jbusr_jbusl_cbu[2] ),
.a (net0480[6] ) );
bw_u1_buf_15x I250_8_ (
.z (jbusr_jbusl_cbd[8] ),
.a (net0478[0] ) );
bw_zckgatedcap_h I156_0_ (
.ld (net0384 ) );
bw_io_dtl_rpt I56 (
.out18 ({net579[0] ,net579[1] } ),
.in7 ({scan_mode2 } ),
.in0 ({net748[0] ,net748[1] ,net748[2] ,net748[3] ,
net748[4] ,net748[5] ,net748[6] ,net748[7] } ),
.out16 ({net581[0] ,net581[1] } ),
.in3 ({net745[0] ,net745[1] ,net745[2] ,net745[3] ,
net745[4] ,net745[5] ,net745[6] ,net745[7] } ),
.in2 ({net746[0] ,net746[1] ,net746[2] ,net746[3] ,
net746[4] ,net746[5] ,net746[6] ,net746[7] } ),
.in6 ({hiz_l2 } ),
.out19 ({upd_dr3 } ),
.in8 ({net740[0] ,net740[1] } ),
.in9 ({net739[0] ,net739[1] } ),
.out15 ({net582[0] ,net582[1] } ),
.out17 ({shift_dr3 } ),
.in1 ({net747[0] ,net747[1] ,net747[2] ,net747[3] ,
net747[4] ,net747[5] ,net747[6] ,net747[7] } ),
.in4 ({clock_dr2 } ),
.in5 ({net743[0] ,net743[1] } ),
.out13 ({net583[0] ,net583[1] } ),
.in10 ({net738[0] ,net738[1] } ),
.in11 ({net737[0] ,net737[1] } ),
.in12 ({net736[0] ,net736[1] } ),
.in13 ({net735[0] ,net735[1] } ),
.in19 ({upd_dr2 } ),
.in18 ({net731[0] ,net731[1] } ),
.in17 ({shift_dr2 } ),
.in16 ({net733[0] ,net733[1] } ),
.in15 ({net734[0] ,net734[1] } ),
.out6 ({hiz_l3 } ),
.out7 ({scan_mode3 } ),
.out8 ({net588[0] ,net588[1] } ),
.out9 ({net587[0] ,net587[1] } ),
.out10 ({net586[0] ,net586[1] } ),
.out11 ({net585[0] ,net585[1] } ),
.out12 ({net584[0] ,net584[1] } ),
.out0 ({net596[0] ,net596[1] ,net596[2] ,net596[3] ,
net596[4] ,net596[5] ,net596[6] ,net596[7] } ),
.out1 ({net595[0] ,net595[1] ,net595[2] ,net595[3] ,
net595[4] ,net595[5] ,net595[6] ,net595[7] } ),
.out2 ({net594[0] ,net594[1] ,net594[2] ,net594[3] ,
net594[4] ,net594[5] ,net594[6] ,net594[7] } ),
.out3 ({net593[0] ,net593[1] ,net593[2] ,net593[3] ,
net593[4] ,net593[5] ,net593[6] ,net593[7] } ),
.out4 ({clock_dr3 } ),
.out5 ({net591[0] ,net591[1] } ) );
endmodule
|
/*
IOBUF
Not a primitive?
Looks like it has an OBUFT
Output buffer family:
OBUF
OBUFDS
OBUFT
OBUFTDS
*/
`ifndef ROI
ERROR: must set ROI
`endif
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
`ROI
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi_io_a(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
IOBUF_INTERMDISABLE #(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW"),
.USE_IBUFDISABLE("TRUE")
) IOBUF_INTERMDISABLE_inst (
.O(1'b0),
.IO(1'bz),
.I(dout[8]),
.IBUFDISABLE(1'b0),
.INTERMDISABLE(1'b0),
.T(1'b1));
endmodule
module roi_io_b(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
wire onet;
IOBUF_INTERMDISABLE #(
.DRIVE(12),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW"),
.USE_IBUFDISABLE("FALSE")
) IOBUF_INTERMDISABLE_inst (
.O(onet),
.IO(1'bz),
.I(dout[8]),
.IBUFDISABLE(1'b0),
.INTERMDISABLE(1'b0),
.T(1'b1));
PULLUP PULLUP_inst (
.O(onet)
);
IOBUF_INTERMDISABLE #(
.DRIVE(12),
.IBUF_LOW_PWR("FALSE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW"),
.USE_IBUFDISABLE("FALSE")
) i2 (
.O(),
.IO(1'bz),
.I(dout[8]),
.IBUFDISABLE(1'b0),
.INTERMDISABLE(1'b0),
.T(1'b1));
endmodule
/*
For some reason this doesn't diff
Was this optimized out?
ERROR: [Place 30-69] Instance roi/dut/OBUFT (OBUFT) is unplaced after IO placer
ERROR: [Place 30-68] Instance roi/dut/OBUFT (OBUFT) is not placed
*/
/*
module roi_prop_a(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
//(* LOC="D19", KEEP, DONT_TOUCH *)
(* KEEP, DONT_TOUCH *)
IOBUF #(
.DRIVE(8),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
.O(dout[1]),
.I(din[0]),
.T(din[1]));
endmodule
module roi_prop_b(input clk, input [255:0] din, output [255:0] dout);
assign dout[0] = din[0] & din[1];
//(* LOC="D19", KEEP, DONT_TOUCH *)
(* KEEP, DONT_TOUCH *)
IOBUF #(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
.O(dout[1]),
.I(din[0]),
.T(din[1]));
endmodule
*/
/*
ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1
ERROR: [Place 30-69] Instance roi/dut (OBUFT) is unplaced after IO placer
hmm
Abandoning verilog approach
tcl seems to work well, just use it directly
*/
module roi_prop_a(input clk, input [255:0] din, output [255:0] dout);
(* LOC="D19", KEEP, DONT_TOUCH *)
//(* KEEP, DONT_TOUCH *)
OBUFT #(
.DRIVE(8),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
//.O(dout[1]),
.O(),
.I(din[0]),
.T(din[1]));
endmodule
module roi_prop_b(input clk, input [255:0] din, output [255:0] dout);
(* LOC="D19", KEEP, DONT_TOUCH *)
//(* KEEP, DONT_TOUCH *)
(* KEEP, DONT_TOUCH *)
OBUFT #(
.DRIVE(12),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) dut (
//.O(dout[1]),
.O(),
.I(din[0]),
.T(din[1]));
endmodule
|
// ************************Declaration*************************************** //
// File name: decoders38.v //
// Author: firedom //
// //
// Abstract: //
// dedocder38 for verilog. //
// [0:2]in is 3-port select input. //
// [0:7]out is 7-port select output. //
// [0:2]en is enable port. //
// Send 3'b100 to enable port and send 3'bxxx(000~111 3-bit binary code) //
// to select input can be accessed by the corresponding select output. //
// //
// Reference: //
// http://www.ti.com/lit/ds/symlink/sn74ls138.pdf //
// https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/Decoder //
// //
// Modification history:(including time, version, author and abstract) //
// 2016-08-30 22:14 version 1.0 //
// 2016-08-31 10:23 change wire name. //
// ************************Declaration*************************************** //
module decoders38(in, out, en);
input [0:2]in;
input [0:2]en;
output [0:7]out;
wire enableWire;
and
andGateEnable(enableWire, en[0], ~en[1], ~en[2]);
nand
nandGate0(out[0], ~in[2], ~in[1], ~in[0], enableWire),
nandGate1(out[1], ~in[2], ~in[1], in[0], enableWire),
nandGate2(out[2], ~in[2], in[1], ~in[0], enableWire),
nandGate3(out[3], ~in[2], in[1], in[0], enableWire),
nandGate4(out[4], in[2], ~in[1], ~in[0], enableWire),
nandGate5(out[5], in[2], ~in[1], in[0], enableWire),
nandGate6(out[6], in[2], in[1], ~in[0], enableWire),
nandGate7(out[7], in[2], in[1], in[0], enableWire);
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| BNot b' => BNot (optimize_0plus_b b')
| BAnd b1 b2 => BAnd (optimize_0plus_b b1) (optimize_0plus_b b2)
end.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq" | Case_aux c "BLe" |
Case_aux c "BNot" | Case_aux c "BAnd" ].
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros. bexp_cases (induction b as [| | | |b IHb1|b1 IHb1 b2 IHb2]) Case;
simpl;
try (repeat (rewrite optimize_0plus_sound));
try (rewrite IHb1); try (rewrite IHb2);
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Liebniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(*
Inductive bevalR:
(* FILL IN HERE *)
*)
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** *** Adding nondeterminism *)
(* /TERSE *)
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
intros.
destruct (eq_id_dec x y).
destruct H.
apply e.
reflexivity.
Qed.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
intros.
unfold update.
apply eq_id.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
intros.
unfold update.
apply neq_id.
apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
intros.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
intros. unfold update. destruct (eq_id_dec x2 x1); reflexivity.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
intros. unfold update. destruct (eq_id_dec x1 x2).
- symmetry. rewrite <- e. apply H.
- reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
intros. unfold update. destruct (eq_id_dec x1 x3).
- symmetry. apply neq_id. unfold not. intros. apply H. rewrite e. apply H0.
- reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
(*
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;
Y ::= 1;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;
X ::= 1;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
(* FILL IN HERE *)
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-02-22 09:43:41 -0500 (Sat, 22 Feb 2014) $ *)
|
// soc_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 188 at 2015.01.20.10:18:04
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0 (
input wire [11:0] hps_0_h2f_axi_master_awid, // hps_0_h2f_axi_master.awid
input wire [29:0] hps_0_h2f_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_axi_master_awprot, // .awprot
input wire hps_0_h2f_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_axi_master_wid, // .wid
input wire [63:0] hps_0_h2f_axi_master_wdata, // .wdata
input wire [7:0] hps_0_h2f_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_axi_master_wlast, // .wlast
input wire hps_0_h2f_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_axi_master_bresp, // .bresp
output wire hps_0_h2f_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_axi_master_arid, // .arid
input wire [29:0] hps_0_h2f_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_axi_master_arprot, // .arprot
input wire hps_0_h2f_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_axi_master_rid, // .rid
output wire [63:0] hps_0_h2f_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_axi_master_rresp, // .rresp
output wire hps_0_h2f_axi_master_rlast, // .rlast
output wire hps_0_h2f_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_axi_master_rready, // .rready
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire fpga_only_master_clk_reset_reset_bridge_in_reset_reset, // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
input wire hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire onchip_memory2_0_reset1_reset_bridge_in_reset_reset, // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
input wire [31:0] fpga_only_master_master_address, // fpga_only_master_master.address
output wire fpga_only_master_master_waitrequest, // .waitrequest
input wire [3:0] fpga_only_master_master_byteenable, // .byteenable
input wire fpga_only_master_master_read, // .read
output wire [31:0] fpga_only_master_master_readdata, // .readdata
output wire fpga_only_master_master_readdatavalid, // .readdatavalid
input wire fpga_only_master_master_write, // .write
input wire [31:0] fpga_only_master_master_writedata, // .writedata
output wire [1:0] button_pio_s1_address, // button_pio_s1.address
output wire button_pio_s1_write, // .write
input wire [31:0] button_pio_s1_readdata, // .readdata
output wire [31:0] button_pio_s1_writedata, // .writedata
output wire button_pio_s1_chipselect, // .chipselect
output wire [1:0] dipsw_pio_s1_address, // dipsw_pio_s1.address
output wire dipsw_pio_s1_write, // .write
input wire [31:0] dipsw_pio_s1_readdata, // .readdata
output wire [31:0] dipsw_pio_s1_writedata, // .writedata
output wire dipsw_pio_s1_chipselect, // .chipselect
output wire [0:0] intr_capturer_0_avalon_slave_0_address, // intr_capturer_0_avalon_slave_0.address
output wire intr_capturer_0_avalon_slave_0_read, // .read
input wire [31:0] intr_capturer_0_avalon_slave_0_readdata, // .readdata
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] led_pio_s1_address, // led_pio_s1.address
output wire led_pio_s1_write, // .write
input wire [31:0] led_pio_s1_readdata, // .readdata
output wire [31:0] led_pio_s1_writedata, // .writedata
output wire led_pio_s1_chipselect, // .chipselect
output wire [12:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [63:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [63:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [7:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [0:0] sysid_qsys_control_slave_address, // sysid_qsys_control_slave.address
input wire [31:0] sysid_qsys_control_slave_readdata // .readdata
);
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_0_h2f_axi_master_agent:write_rp_valid
wire [164:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_0_h2f_axi_master_agent:write_rp_data
wire rsp_mux_src_ready; // hps_0_h2f_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_0_h2f_axi_master_agent:write_rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_0_h2f_axi_master_agent:write_rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_0_h2f_axi_master_agent:write_rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_0_h2f_axi_master_agent:read_rp_valid
wire [164:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_0_h2f_axi_master_agent:read_rp_data
wire rsp_mux_001_src_ready; // hps_0_h2f_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
wire [6:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_0_h2f_axi_master_agent:read_rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_0_h2f_axi_master_agent:read_rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_0_h2f_axi_master_agent:read_rp_endofpacket
wire fpga_only_master_master_translator_avalon_universal_master_0_waitrequest; // fpga_only_master_master_agent:av_waitrequest -> fpga_only_master_master_translator:uav_waitrequest
wire [31:0] fpga_only_master_master_translator_avalon_universal_master_0_readdata; // fpga_only_master_master_agent:av_readdata -> fpga_only_master_master_translator:uav_readdata
wire fpga_only_master_master_translator_avalon_universal_master_0_debugaccess; // fpga_only_master_master_translator:uav_debugaccess -> fpga_only_master_master_agent:av_debugaccess
wire [31:0] fpga_only_master_master_translator_avalon_universal_master_0_address; // fpga_only_master_master_translator:uav_address -> fpga_only_master_master_agent:av_address
wire fpga_only_master_master_translator_avalon_universal_master_0_read; // fpga_only_master_master_translator:uav_read -> fpga_only_master_master_agent:av_read
wire [3:0] fpga_only_master_master_translator_avalon_universal_master_0_byteenable; // fpga_only_master_master_translator:uav_byteenable -> fpga_only_master_master_agent:av_byteenable
wire fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid; // fpga_only_master_master_agent:av_readdatavalid -> fpga_only_master_master_translator:uav_readdatavalid
wire fpga_only_master_master_translator_avalon_universal_master_0_lock; // fpga_only_master_master_translator:uav_lock -> fpga_only_master_master_agent:av_lock
wire fpga_only_master_master_translator_avalon_universal_master_0_write; // fpga_only_master_master_translator:uav_write -> fpga_only_master_master_agent:av_write
wire [31:0] fpga_only_master_master_translator_avalon_universal_master_0_writedata; // fpga_only_master_master_translator:uav_writedata -> fpga_only_master_master_agent:av_writedata
wire [2:0] fpga_only_master_master_translator_avalon_universal_master_0_burstcount; // fpga_only_master_master_translator:uav_burstcount -> fpga_only_master_master_agent:av_burstcount
wire [63:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [31:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [7:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [63:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [3:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [165:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [165:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_agent_rdata_fifo:in_valid
wire [65:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_agent_rdata_fifo:in_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_agent_rdata_fifo:in_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire onchip_memory2_0_s1_agent_rdata_fifo_out_valid; // onchip_memory2_0_s1_agent_rdata_fifo:out_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [65:0] onchip_memory2_0_s1_agent_rdata_fifo_out_data; // onchip_memory2_0_s1_agent_rdata_fifo:out_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire onchip_memory2_0_s1_agent_rdata_fifo_out_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_agent_rdata_fifo:out_ready
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [129:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire [129:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_ready
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_readdata; // intr_capturer_0_avalon_slave_0_translator:uav_readdata -> intr_capturer_0_avalon_slave_0_agent:m0_readdata
wire intr_capturer_0_avalon_slave_0_agent_m0_waitrequest; // intr_capturer_0_avalon_slave_0_translator:uav_waitrequest -> intr_capturer_0_avalon_slave_0_agent:m0_waitrequest
wire intr_capturer_0_avalon_slave_0_agent_m0_debugaccess; // intr_capturer_0_avalon_slave_0_agent:m0_debugaccess -> intr_capturer_0_avalon_slave_0_translator:uav_debugaccess
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_address; // intr_capturer_0_avalon_slave_0_agent:m0_address -> intr_capturer_0_avalon_slave_0_translator:uav_address
wire [3:0] intr_capturer_0_avalon_slave_0_agent_m0_byteenable; // intr_capturer_0_avalon_slave_0_agent:m0_byteenable -> intr_capturer_0_avalon_slave_0_translator:uav_byteenable
wire intr_capturer_0_avalon_slave_0_agent_m0_read; // intr_capturer_0_avalon_slave_0_agent:m0_read -> intr_capturer_0_avalon_slave_0_translator:uav_read
wire intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid; // intr_capturer_0_avalon_slave_0_translator:uav_readdatavalid -> intr_capturer_0_avalon_slave_0_agent:m0_readdatavalid
wire intr_capturer_0_avalon_slave_0_agent_m0_lock; // intr_capturer_0_avalon_slave_0_agent:m0_lock -> intr_capturer_0_avalon_slave_0_translator:uav_lock
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_writedata; // intr_capturer_0_avalon_slave_0_agent:m0_writedata -> intr_capturer_0_avalon_slave_0_translator:uav_writedata
wire intr_capturer_0_avalon_slave_0_agent_m0_write; // intr_capturer_0_avalon_slave_0_agent:m0_write -> intr_capturer_0_avalon_slave_0_translator:uav_write
wire [2:0] intr_capturer_0_avalon_slave_0_agent_m0_burstcount; // intr_capturer_0_avalon_slave_0_agent:m0_burstcount -> intr_capturer_0_avalon_slave_0_translator:uav_burstcount
wire intr_capturer_0_avalon_slave_0_agent_rf_source_valid; // intr_capturer_0_avalon_slave_0_agent:rf_source_valid -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [129:0] intr_capturer_0_avalon_slave_0_agent_rf_source_data; // intr_capturer_0_avalon_slave_0_agent:rf_source_data -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_data
wire intr_capturer_0_avalon_slave_0_agent_rf_source_ready; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rf_source_ready
wire intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket; // intr_capturer_0_avalon_slave_0_agent:rf_source_startofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket; // intr_capturer_0_avalon_slave_0_agent:rf_source_endofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_valid -> intr_capturer_0_avalon_slave_0_agent:rf_sink_valid
wire [129:0] intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_data -> intr_capturer_0_avalon_slave_0_agent:rf_sink_data
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready; // intr_capturer_0_avalon_slave_0_agent:rf_sink_ready -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_valid -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_valid
wire [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_data -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_data
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_valid -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_data -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> intr_capturer_0_avalon_slave_0_agent:cp_valid
wire [128:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> intr_capturer_0_avalon_slave_0_agent:cp_data
wire cmd_mux_002_src_ready; // intr_capturer_0_avalon_slave_0_agent:cp_ready -> cmd_mux_002:src_ready
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> intr_capturer_0_avalon_slave_0_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_endofpacket
wire [31:0] sysid_qsys_control_slave_agent_m0_readdata; // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
wire sysid_qsys_control_slave_agent_m0_waitrequest; // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
wire sysid_qsys_control_slave_agent_m0_debugaccess; // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
wire [31:0] sysid_qsys_control_slave_agent_m0_address; // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
wire [3:0] sysid_qsys_control_slave_agent_m0_byteenable; // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
wire sysid_qsys_control_slave_agent_m0_read; // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
wire sysid_qsys_control_slave_agent_m0_readdatavalid; // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
wire sysid_qsys_control_slave_agent_m0_lock; // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
wire [31:0] sysid_qsys_control_slave_agent_m0_writedata; // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
wire sysid_qsys_control_slave_agent_m0_write; // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
wire [2:0] sysid_qsys_control_slave_agent_m0_burstcount; // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
wire sysid_qsys_control_slave_agent_rf_source_valid; // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
wire [129:0] sysid_qsys_control_slave_agent_rf_source_data; // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
wire sysid_qsys_control_slave_agent_rf_source_ready; // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
wire sysid_qsys_control_slave_agent_rf_source_startofpacket; // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
wire sysid_qsys_control_slave_agent_rf_source_endofpacket; // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_valid; // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
wire [129:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data; // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
wire sysid_qsys_control_slave_agent_rsp_fifo_out_ready; // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
wire sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
wire sysid_qsys_control_slave_agent_rdata_fifo_src_valid; // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent_rdata_fifo:in_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data; // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent_rdata_fifo:in_data
wire sysid_qsys_control_slave_agent_rdata_fifo_src_ready; // sysid_qsys_control_slave_agent_rdata_fifo:in_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
wire sysid_qsys_control_slave_agent_rdata_fifo_out_valid; // sysid_qsys_control_slave_agent_rdata_fifo:out_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_out_data; // sysid_qsys_control_slave_agent_rdata_fifo:out_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
wire sysid_qsys_control_slave_agent_rdata_fifo_out_ready; // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> sysid_qsys_control_slave_agent_rdata_fifo:out_ready
wire [31:0] led_pio_s1_agent_m0_readdata; // led_pio_s1_translator:uav_readdata -> led_pio_s1_agent:m0_readdata
wire led_pio_s1_agent_m0_waitrequest; // led_pio_s1_translator:uav_waitrequest -> led_pio_s1_agent:m0_waitrequest
wire led_pio_s1_agent_m0_debugaccess; // led_pio_s1_agent:m0_debugaccess -> led_pio_s1_translator:uav_debugaccess
wire [31:0] led_pio_s1_agent_m0_address; // led_pio_s1_agent:m0_address -> led_pio_s1_translator:uav_address
wire [3:0] led_pio_s1_agent_m0_byteenable; // led_pio_s1_agent:m0_byteenable -> led_pio_s1_translator:uav_byteenable
wire led_pio_s1_agent_m0_read; // led_pio_s1_agent:m0_read -> led_pio_s1_translator:uav_read
wire led_pio_s1_agent_m0_readdatavalid; // led_pio_s1_translator:uav_readdatavalid -> led_pio_s1_agent:m0_readdatavalid
wire led_pio_s1_agent_m0_lock; // led_pio_s1_agent:m0_lock -> led_pio_s1_translator:uav_lock
wire [31:0] led_pio_s1_agent_m0_writedata; // led_pio_s1_agent:m0_writedata -> led_pio_s1_translator:uav_writedata
wire led_pio_s1_agent_m0_write; // led_pio_s1_agent:m0_write -> led_pio_s1_translator:uav_write
wire [2:0] led_pio_s1_agent_m0_burstcount; // led_pio_s1_agent:m0_burstcount -> led_pio_s1_translator:uav_burstcount
wire led_pio_s1_agent_rf_source_valid; // led_pio_s1_agent:rf_source_valid -> led_pio_s1_agent_rsp_fifo:in_valid
wire [129:0] led_pio_s1_agent_rf_source_data; // led_pio_s1_agent:rf_source_data -> led_pio_s1_agent_rsp_fifo:in_data
wire led_pio_s1_agent_rf_source_ready; // led_pio_s1_agent_rsp_fifo:in_ready -> led_pio_s1_agent:rf_source_ready
wire led_pio_s1_agent_rf_source_startofpacket; // led_pio_s1_agent:rf_source_startofpacket -> led_pio_s1_agent_rsp_fifo:in_startofpacket
wire led_pio_s1_agent_rf_source_endofpacket; // led_pio_s1_agent:rf_source_endofpacket -> led_pio_s1_agent_rsp_fifo:in_endofpacket
wire led_pio_s1_agent_rsp_fifo_out_valid; // led_pio_s1_agent_rsp_fifo:out_valid -> led_pio_s1_agent:rf_sink_valid
wire [129:0] led_pio_s1_agent_rsp_fifo_out_data; // led_pio_s1_agent_rsp_fifo:out_data -> led_pio_s1_agent:rf_sink_data
wire led_pio_s1_agent_rsp_fifo_out_ready; // led_pio_s1_agent:rf_sink_ready -> led_pio_s1_agent_rsp_fifo:out_ready
wire led_pio_s1_agent_rsp_fifo_out_startofpacket; // led_pio_s1_agent_rsp_fifo:out_startofpacket -> led_pio_s1_agent:rf_sink_startofpacket
wire led_pio_s1_agent_rsp_fifo_out_endofpacket; // led_pio_s1_agent_rsp_fifo:out_endofpacket -> led_pio_s1_agent:rf_sink_endofpacket
wire led_pio_s1_agent_rdata_fifo_src_valid; // led_pio_s1_agent:rdata_fifo_src_valid -> led_pio_s1_agent_rdata_fifo:in_valid
wire [33:0] led_pio_s1_agent_rdata_fifo_src_data; // led_pio_s1_agent:rdata_fifo_src_data -> led_pio_s1_agent_rdata_fifo:in_data
wire led_pio_s1_agent_rdata_fifo_src_ready; // led_pio_s1_agent_rdata_fifo:in_ready -> led_pio_s1_agent:rdata_fifo_src_ready
wire led_pio_s1_agent_rdata_fifo_out_valid; // led_pio_s1_agent_rdata_fifo:out_valid -> led_pio_s1_agent:rdata_fifo_sink_valid
wire [33:0] led_pio_s1_agent_rdata_fifo_out_data; // led_pio_s1_agent_rdata_fifo:out_data -> led_pio_s1_agent:rdata_fifo_sink_data
wire led_pio_s1_agent_rdata_fifo_out_ready; // led_pio_s1_agent:rdata_fifo_sink_ready -> led_pio_s1_agent_rdata_fifo:out_ready
wire [31:0] dipsw_pio_s1_agent_m0_readdata; // dipsw_pio_s1_translator:uav_readdata -> dipsw_pio_s1_agent:m0_readdata
wire dipsw_pio_s1_agent_m0_waitrequest; // dipsw_pio_s1_translator:uav_waitrequest -> dipsw_pio_s1_agent:m0_waitrequest
wire dipsw_pio_s1_agent_m0_debugaccess; // dipsw_pio_s1_agent:m0_debugaccess -> dipsw_pio_s1_translator:uav_debugaccess
wire [31:0] dipsw_pio_s1_agent_m0_address; // dipsw_pio_s1_agent:m0_address -> dipsw_pio_s1_translator:uav_address
wire [3:0] dipsw_pio_s1_agent_m0_byteenable; // dipsw_pio_s1_agent:m0_byteenable -> dipsw_pio_s1_translator:uav_byteenable
wire dipsw_pio_s1_agent_m0_read; // dipsw_pio_s1_agent:m0_read -> dipsw_pio_s1_translator:uav_read
wire dipsw_pio_s1_agent_m0_readdatavalid; // dipsw_pio_s1_translator:uav_readdatavalid -> dipsw_pio_s1_agent:m0_readdatavalid
wire dipsw_pio_s1_agent_m0_lock; // dipsw_pio_s1_agent:m0_lock -> dipsw_pio_s1_translator:uav_lock
wire [31:0] dipsw_pio_s1_agent_m0_writedata; // dipsw_pio_s1_agent:m0_writedata -> dipsw_pio_s1_translator:uav_writedata
wire dipsw_pio_s1_agent_m0_write; // dipsw_pio_s1_agent:m0_write -> dipsw_pio_s1_translator:uav_write
wire [2:0] dipsw_pio_s1_agent_m0_burstcount; // dipsw_pio_s1_agent:m0_burstcount -> dipsw_pio_s1_translator:uav_burstcount
wire dipsw_pio_s1_agent_rf_source_valid; // dipsw_pio_s1_agent:rf_source_valid -> dipsw_pio_s1_agent_rsp_fifo:in_valid
wire [129:0] dipsw_pio_s1_agent_rf_source_data; // dipsw_pio_s1_agent:rf_source_data -> dipsw_pio_s1_agent_rsp_fifo:in_data
wire dipsw_pio_s1_agent_rf_source_ready; // dipsw_pio_s1_agent_rsp_fifo:in_ready -> dipsw_pio_s1_agent:rf_source_ready
wire dipsw_pio_s1_agent_rf_source_startofpacket; // dipsw_pio_s1_agent:rf_source_startofpacket -> dipsw_pio_s1_agent_rsp_fifo:in_startofpacket
wire dipsw_pio_s1_agent_rf_source_endofpacket; // dipsw_pio_s1_agent:rf_source_endofpacket -> dipsw_pio_s1_agent_rsp_fifo:in_endofpacket
wire dipsw_pio_s1_agent_rsp_fifo_out_valid; // dipsw_pio_s1_agent_rsp_fifo:out_valid -> dipsw_pio_s1_agent:rf_sink_valid
wire [129:0] dipsw_pio_s1_agent_rsp_fifo_out_data; // dipsw_pio_s1_agent_rsp_fifo:out_data -> dipsw_pio_s1_agent:rf_sink_data
wire dipsw_pio_s1_agent_rsp_fifo_out_ready; // dipsw_pio_s1_agent:rf_sink_ready -> dipsw_pio_s1_agent_rsp_fifo:out_ready
wire dipsw_pio_s1_agent_rsp_fifo_out_startofpacket; // dipsw_pio_s1_agent_rsp_fifo:out_startofpacket -> dipsw_pio_s1_agent:rf_sink_startofpacket
wire dipsw_pio_s1_agent_rsp_fifo_out_endofpacket; // dipsw_pio_s1_agent_rsp_fifo:out_endofpacket -> dipsw_pio_s1_agent:rf_sink_endofpacket
wire dipsw_pio_s1_agent_rdata_fifo_src_valid; // dipsw_pio_s1_agent:rdata_fifo_src_valid -> dipsw_pio_s1_agent_rdata_fifo:in_valid
wire [33:0] dipsw_pio_s1_agent_rdata_fifo_src_data; // dipsw_pio_s1_agent:rdata_fifo_src_data -> dipsw_pio_s1_agent_rdata_fifo:in_data
wire dipsw_pio_s1_agent_rdata_fifo_src_ready; // dipsw_pio_s1_agent_rdata_fifo:in_ready -> dipsw_pio_s1_agent:rdata_fifo_src_ready
wire dipsw_pio_s1_agent_rdata_fifo_out_valid; // dipsw_pio_s1_agent_rdata_fifo:out_valid -> dipsw_pio_s1_agent:rdata_fifo_sink_valid
wire [33:0] dipsw_pio_s1_agent_rdata_fifo_out_data; // dipsw_pio_s1_agent_rdata_fifo:out_data -> dipsw_pio_s1_agent:rdata_fifo_sink_data
wire dipsw_pio_s1_agent_rdata_fifo_out_ready; // dipsw_pio_s1_agent:rdata_fifo_sink_ready -> dipsw_pio_s1_agent_rdata_fifo:out_ready
wire [31:0] button_pio_s1_agent_m0_readdata; // button_pio_s1_translator:uav_readdata -> button_pio_s1_agent:m0_readdata
wire button_pio_s1_agent_m0_waitrequest; // button_pio_s1_translator:uav_waitrequest -> button_pio_s1_agent:m0_waitrequest
wire button_pio_s1_agent_m0_debugaccess; // button_pio_s1_agent:m0_debugaccess -> button_pio_s1_translator:uav_debugaccess
wire [31:0] button_pio_s1_agent_m0_address; // button_pio_s1_agent:m0_address -> button_pio_s1_translator:uav_address
wire [3:0] button_pio_s1_agent_m0_byteenable; // button_pio_s1_agent:m0_byteenable -> button_pio_s1_translator:uav_byteenable
wire button_pio_s1_agent_m0_read; // button_pio_s1_agent:m0_read -> button_pio_s1_translator:uav_read
wire button_pio_s1_agent_m0_readdatavalid; // button_pio_s1_translator:uav_readdatavalid -> button_pio_s1_agent:m0_readdatavalid
wire button_pio_s1_agent_m0_lock; // button_pio_s1_agent:m0_lock -> button_pio_s1_translator:uav_lock
wire [31:0] button_pio_s1_agent_m0_writedata; // button_pio_s1_agent:m0_writedata -> button_pio_s1_translator:uav_writedata
wire button_pio_s1_agent_m0_write; // button_pio_s1_agent:m0_write -> button_pio_s1_translator:uav_write
wire [2:0] button_pio_s1_agent_m0_burstcount; // button_pio_s1_agent:m0_burstcount -> button_pio_s1_translator:uav_burstcount
wire button_pio_s1_agent_rf_source_valid; // button_pio_s1_agent:rf_source_valid -> button_pio_s1_agent_rsp_fifo:in_valid
wire [129:0] button_pio_s1_agent_rf_source_data; // button_pio_s1_agent:rf_source_data -> button_pio_s1_agent_rsp_fifo:in_data
wire button_pio_s1_agent_rf_source_ready; // button_pio_s1_agent_rsp_fifo:in_ready -> button_pio_s1_agent:rf_source_ready
wire button_pio_s1_agent_rf_source_startofpacket; // button_pio_s1_agent:rf_source_startofpacket -> button_pio_s1_agent_rsp_fifo:in_startofpacket
wire button_pio_s1_agent_rf_source_endofpacket; // button_pio_s1_agent:rf_source_endofpacket -> button_pio_s1_agent_rsp_fifo:in_endofpacket
wire button_pio_s1_agent_rsp_fifo_out_valid; // button_pio_s1_agent_rsp_fifo:out_valid -> button_pio_s1_agent:rf_sink_valid
wire [129:0] button_pio_s1_agent_rsp_fifo_out_data; // button_pio_s1_agent_rsp_fifo:out_data -> button_pio_s1_agent:rf_sink_data
wire button_pio_s1_agent_rsp_fifo_out_ready; // button_pio_s1_agent:rf_sink_ready -> button_pio_s1_agent_rsp_fifo:out_ready
wire button_pio_s1_agent_rsp_fifo_out_startofpacket; // button_pio_s1_agent_rsp_fifo:out_startofpacket -> button_pio_s1_agent:rf_sink_startofpacket
wire button_pio_s1_agent_rsp_fifo_out_endofpacket; // button_pio_s1_agent_rsp_fifo:out_endofpacket -> button_pio_s1_agent:rf_sink_endofpacket
wire button_pio_s1_agent_rdata_fifo_src_valid; // button_pio_s1_agent:rdata_fifo_src_valid -> button_pio_s1_agent_rdata_fifo:in_valid
wire [33:0] button_pio_s1_agent_rdata_fifo_src_data; // button_pio_s1_agent:rdata_fifo_src_data -> button_pio_s1_agent_rdata_fifo:in_data
wire button_pio_s1_agent_rdata_fifo_src_ready; // button_pio_s1_agent_rdata_fifo:in_ready -> button_pio_s1_agent:rdata_fifo_src_ready
wire button_pio_s1_agent_rdata_fifo_out_valid; // button_pio_s1_agent_rdata_fifo:out_valid -> button_pio_s1_agent:rdata_fifo_sink_valid
wire [33:0] button_pio_s1_agent_rdata_fifo_out_data; // button_pio_s1_agent_rdata_fifo:out_data -> button_pio_s1_agent:rdata_fifo_sink_data
wire button_pio_s1_agent_rdata_fifo_out_ready; // button_pio_s1_agent:rdata_fifo_sink_ready -> button_pio_s1_agent_rdata_fifo:out_ready
wire hps_0_h2f_axi_master_agent_write_cp_valid; // hps_0_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
wire [164:0] hps_0_h2f_axi_master_agent_write_cp_data; // hps_0_h2f_axi_master_agent:write_cp_data -> router:sink_data
wire hps_0_h2f_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_0_h2f_axi_master_agent:write_cp_ready
wire hps_0_h2f_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire hps_0_h2f_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [164:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [6:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire hps_0_h2f_axi_master_agent_read_cp_valid; // hps_0_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire [164:0] hps_0_h2f_axi_master_agent_read_cp_data; // hps_0_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_0_h2f_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_0_h2f_axi_master_agent:read_cp_ready
wire hps_0_h2f_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire hps_0_h2f_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [164:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [6:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire fpga_only_master_master_agent_cp_valid; // fpga_only_master_master_agent:cp_valid -> router_002:sink_valid
wire [128:0] fpga_only_master_master_agent_cp_data; // fpga_only_master_master_agent:cp_data -> router_002:sink_data
wire fpga_only_master_master_agent_cp_ready; // router_002:sink_ready -> fpga_only_master_master_agent:cp_ready
wire fpga_only_master_master_agent_cp_startofpacket; // fpga_only_master_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire fpga_only_master_master_agent_cp_endofpacket; // fpga_only_master_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> router_003:sink_valid
wire [128:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> router_003:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // router_003:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> router_003:sink_startofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> router_003:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> router_004:sink_valid
wire [128:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> router_004:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // router_004:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_004:sink_startofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_004:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_005:sink_valid
wire [164:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_005:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_005:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux:sink_valid
wire [164:0] router_005_src_data; // router_005:src_data -> rsp_demux:sink_data
wire router_005_src_ready; // rsp_demux:sink_ready -> router_005:src_ready
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_006:sink_valid
wire [128:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_006:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_006:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_001:sink_valid
wire [128:0] router_006_src_data; // router_006:src_data -> rsp_demux_001:sink_data
wire router_006_src_ready; // rsp_demux_001:sink_ready -> router_006:src_ready
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_001:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rp_valid; // intr_capturer_0_avalon_slave_0_agent:rp_valid -> router_007:sink_valid
wire [128:0] intr_capturer_0_avalon_slave_0_agent_rp_data; // intr_capturer_0_avalon_slave_0_agent:rp_data -> router_007:sink_data
wire intr_capturer_0_avalon_slave_0_agent_rp_ready; // router_007:sink_ready -> intr_capturer_0_avalon_slave_0_agent:rp_ready
wire intr_capturer_0_avalon_slave_0_agent_rp_startofpacket; // intr_capturer_0_avalon_slave_0_agent:rp_startofpacket -> router_007:sink_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rp_endofpacket; // intr_capturer_0_avalon_slave_0_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_002:sink_valid
wire [128:0] router_007_src_data; // router_007:src_data -> rsp_demux_002:sink_data
wire router_007_src_ready; // rsp_demux_002:sink_ready -> router_007:src_ready
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_002:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sysid_qsys_control_slave_agent_rp_valid; // sysid_qsys_control_slave_agent:rp_valid -> router_008:sink_valid
wire [128:0] sysid_qsys_control_slave_agent_rp_data; // sysid_qsys_control_slave_agent:rp_data -> router_008:sink_data
wire sysid_qsys_control_slave_agent_rp_ready; // router_008:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
wire sysid_qsys_control_slave_agent_rp_startofpacket; // sysid_qsys_control_slave_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sysid_qsys_control_slave_agent_rp_endofpacket; // sysid_qsys_control_slave_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_003:sink_valid
wire [128:0] router_008_src_data; // router_008:src_data -> rsp_demux_003:sink_data
wire router_008_src_ready; // rsp_demux_003:sink_ready -> router_008:src_ready
wire [6:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_003:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire led_pio_s1_agent_rp_valid; // led_pio_s1_agent:rp_valid -> router_009:sink_valid
wire [128:0] led_pio_s1_agent_rp_data; // led_pio_s1_agent:rp_data -> router_009:sink_data
wire led_pio_s1_agent_rp_ready; // router_009:sink_ready -> led_pio_s1_agent:rp_ready
wire led_pio_s1_agent_rp_startofpacket; // led_pio_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire led_pio_s1_agent_rp_endofpacket; // led_pio_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_004:sink_valid
wire [128:0] router_009_src_data; // router_009:src_data -> rsp_demux_004:sink_data
wire router_009_src_ready; // rsp_demux_004:sink_ready -> router_009:src_ready
wire [6:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_004:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire dipsw_pio_s1_agent_rp_valid; // dipsw_pio_s1_agent:rp_valid -> router_010:sink_valid
wire [128:0] dipsw_pio_s1_agent_rp_data; // dipsw_pio_s1_agent:rp_data -> router_010:sink_data
wire dipsw_pio_s1_agent_rp_ready; // router_010:sink_ready -> dipsw_pio_s1_agent:rp_ready
wire dipsw_pio_s1_agent_rp_startofpacket; // dipsw_pio_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire dipsw_pio_s1_agent_rp_endofpacket; // dipsw_pio_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_005:sink_valid
wire [128:0] router_010_src_data; // router_010:src_data -> rsp_demux_005:sink_data
wire router_010_src_ready; // rsp_demux_005:sink_ready -> router_010:src_ready
wire [6:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_005:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire button_pio_s1_agent_rp_valid; // button_pio_s1_agent:rp_valid -> router_011:sink_valid
wire [128:0] button_pio_s1_agent_rp_data; // button_pio_s1_agent:rp_data -> router_011:sink_data
wire button_pio_s1_agent_rp_ready; // router_011:sink_ready -> button_pio_s1_agent:rp_ready
wire button_pio_s1_agent_rp_startofpacket; // button_pio_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire button_pio_s1_agent_rp_endofpacket; // button_pio_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_006:sink_valid
wire [128:0] router_011_src_data; // router_011:src_data -> rsp_demux_006:sink_data
wire router_011_src_ready; // rsp_demux_006:sink_ready -> router_011:src_ready
wire [6:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_006:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> fpga_only_master_master_limiter:cmd_sink_valid
wire [128:0] router_002_src_data; // router_002:src_data -> fpga_only_master_master_limiter:cmd_sink_data
wire router_002_src_ready; // fpga_only_master_master_limiter:cmd_sink_ready -> router_002:src_ready
wire [6:0] router_002_src_channel; // router_002:src_channel -> fpga_only_master_master_limiter:cmd_sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> fpga_only_master_master_limiter:cmd_sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> fpga_only_master_master_limiter:cmd_sink_endofpacket
wire [128:0] fpga_only_master_master_limiter_cmd_src_data; // fpga_only_master_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
wire fpga_only_master_master_limiter_cmd_src_ready; // cmd_demux_002:sink_ready -> fpga_only_master_master_limiter:cmd_src_ready
wire [6:0] fpga_only_master_master_limiter_cmd_src_channel; // fpga_only_master_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
wire fpga_only_master_master_limiter_cmd_src_startofpacket; // fpga_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
wire fpga_only_master_master_limiter_cmd_src_endofpacket; // fpga_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> fpga_only_master_master_limiter:rsp_sink_valid
wire [128:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> fpga_only_master_master_limiter:rsp_sink_data
wire rsp_mux_002_src_ready; // fpga_only_master_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
wire [6:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> fpga_only_master_master_limiter:rsp_sink_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> fpga_only_master_master_limiter:rsp_sink_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> fpga_only_master_master_limiter:rsp_sink_endofpacket
wire fpga_only_master_master_limiter_rsp_src_valid; // fpga_only_master_master_limiter:rsp_src_valid -> fpga_only_master_master_agent:rp_valid
wire [128:0] fpga_only_master_master_limiter_rsp_src_data; // fpga_only_master_master_limiter:rsp_src_data -> fpga_only_master_master_agent:rp_data
wire fpga_only_master_master_limiter_rsp_src_ready; // fpga_only_master_master_agent:rp_ready -> fpga_only_master_master_limiter:rsp_src_ready
wire [6:0] fpga_only_master_master_limiter_rsp_src_channel; // fpga_only_master_master_limiter:rsp_src_channel -> fpga_only_master_master_agent:rp_channel
wire fpga_only_master_master_limiter_rsp_src_startofpacket; // fpga_only_master_master_limiter:rsp_src_startofpacket -> fpga_only_master_master_agent:rp_startofpacket
wire fpga_only_master_master_limiter_rsp_src_endofpacket; // fpga_only_master_master_limiter:rsp_src_endofpacket -> fpga_only_master_master_agent:rp_endofpacket
wire router_003_src_valid; // router_003:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire [128:0] router_003_src_data; // router_003:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire router_003_src_ready; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router_003:src_ready
wire [6:0] router_003_src_channel; // router_003:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire [128:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux_003:sink_data
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux_003:sink_ready -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire [6:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux_003:sink_channel
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux_003:sink_startofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux_003:sink_endofpacket
wire rsp_mux_003_src_valid; // rsp_mux_003:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire [128:0] rsp_mux_003_src_data; // rsp_mux_003:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire rsp_mux_003_src_ready; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux_003:src_ready
wire [6:0] rsp_mux_003_src_channel; // rsp_mux_003:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_003_src_startofpacket; // rsp_mux_003:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire rsp_mux_003_src_endofpacket; // rsp_mux_003:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire [128:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire [6:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire router_004_src_valid; // router_004:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire [128:0] router_004_src_data; // router_004:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire router_004_src_ready; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_004:src_ready
wire [6:0] router_004_src_channel; // router_004:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire [128:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_004:sink_data
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_004:sink_ready -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire [6:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_004:sink_channel
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_004:sink_startofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_004:sink_endofpacket
wire rsp_mux_004_src_valid; // rsp_mux_004:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire [128:0] rsp_mux_004_src_data; // rsp_mux_004:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire rsp_mux_004_src_ready; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_004:src_ready
wire [6:0] rsp_mux_004_src_channel; // rsp_mux_004:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_004_src_startofpacket; // rsp_mux_004:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire rsp_mux_004_src_endofpacket; // rsp_mux_004:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire [128:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire [6:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> onchip_memory2_0_s1_burst_adapter:sink0_valid
wire [164:0] cmd_mux_src_data; // cmd_mux:src_data -> onchip_memory2_0_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // onchip_memory2_0_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> onchip_memory2_0_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> onchip_memory2_0_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> onchip_memory2_0_s1_burst_adapter:sink0_endofpacket
wire onchip_memory2_0_s1_burst_adapter_source0_valid; // onchip_memory2_0_s1_burst_adapter:source0_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [164:0] onchip_memory2_0_s1_burst_adapter_source0_data; // onchip_memory2_0_s1_burst_adapter:source0_data -> onchip_memory2_0_s1_agent:cp_data
wire onchip_memory2_0_s1_burst_adapter_source0_ready; // onchip_memory2_0_s1_agent:cp_ready -> onchip_memory2_0_s1_burst_adapter:source0_ready
wire [6:0] onchip_memory2_0_s1_burst_adapter_source0_channel; // onchip_memory2_0_s1_burst_adapter:source0_channel -> onchip_memory2_0_s1_agent:cp_channel
wire onchip_memory2_0_s1_burst_adapter_source0_startofpacket; // onchip_memory2_0_s1_burst_adapter:source0_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire onchip_memory2_0_s1_burst_adapter_source0_endofpacket; // onchip_memory2_0_s1_burst_adapter:source0_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_valid
wire [128:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // jtag_uart_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_endofpacket
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire [128:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_data; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> jtag_uart_avalon_jtag_slave_burst_adapter:source0_ready
wire [6:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sysid_qsys_control_slave_burst_adapter:sink0_valid
wire [128:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sysid_qsys_control_slave_burst_adapter:sink0_data
wire cmd_mux_003_src_ready; // sysid_qsys_control_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sysid_qsys_control_slave_burst_adapter:sink0_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_endofpacket
wire sysid_qsys_control_slave_burst_adapter_source0_valid; // sysid_qsys_control_slave_burst_adapter:source0_valid -> sysid_qsys_control_slave_agent:cp_valid
wire [128:0] sysid_qsys_control_slave_burst_adapter_source0_data; // sysid_qsys_control_slave_burst_adapter:source0_data -> sysid_qsys_control_slave_agent:cp_data
wire sysid_qsys_control_slave_burst_adapter_source0_ready; // sysid_qsys_control_slave_agent:cp_ready -> sysid_qsys_control_slave_burst_adapter:source0_ready
wire [6:0] sysid_qsys_control_slave_burst_adapter_source0_channel; // sysid_qsys_control_slave_burst_adapter:source0_channel -> sysid_qsys_control_slave_agent:cp_channel
wire sysid_qsys_control_slave_burst_adapter_source0_startofpacket; // sysid_qsys_control_slave_burst_adapter:source0_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
wire sysid_qsys_control_slave_burst_adapter_source0_endofpacket; // sysid_qsys_control_slave_burst_adapter:source0_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> led_pio_s1_burst_adapter:sink0_valid
wire [128:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> led_pio_s1_burst_adapter:sink0_data
wire cmd_mux_004_src_ready; // led_pio_s1_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> led_pio_s1_burst_adapter:sink0_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> led_pio_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> led_pio_s1_burst_adapter:sink0_endofpacket
wire led_pio_s1_burst_adapter_source0_valid; // led_pio_s1_burst_adapter:source0_valid -> led_pio_s1_agent:cp_valid
wire [128:0] led_pio_s1_burst_adapter_source0_data; // led_pio_s1_burst_adapter:source0_data -> led_pio_s1_agent:cp_data
wire led_pio_s1_burst_adapter_source0_ready; // led_pio_s1_agent:cp_ready -> led_pio_s1_burst_adapter:source0_ready
wire [6:0] led_pio_s1_burst_adapter_source0_channel; // led_pio_s1_burst_adapter:source0_channel -> led_pio_s1_agent:cp_channel
wire led_pio_s1_burst_adapter_source0_startofpacket; // led_pio_s1_burst_adapter:source0_startofpacket -> led_pio_s1_agent:cp_startofpacket
wire led_pio_s1_burst_adapter_source0_endofpacket; // led_pio_s1_burst_adapter:source0_endofpacket -> led_pio_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> dipsw_pio_s1_burst_adapter:sink0_valid
wire [128:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> dipsw_pio_s1_burst_adapter:sink0_data
wire cmd_mux_005_src_ready; // dipsw_pio_s1_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> dipsw_pio_s1_burst_adapter:sink0_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> dipsw_pio_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> dipsw_pio_s1_burst_adapter:sink0_endofpacket
wire dipsw_pio_s1_burst_adapter_source0_valid; // dipsw_pio_s1_burst_adapter:source0_valid -> dipsw_pio_s1_agent:cp_valid
wire [128:0] dipsw_pio_s1_burst_adapter_source0_data; // dipsw_pio_s1_burst_adapter:source0_data -> dipsw_pio_s1_agent:cp_data
wire dipsw_pio_s1_burst_adapter_source0_ready; // dipsw_pio_s1_agent:cp_ready -> dipsw_pio_s1_burst_adapter:source0_ready
wire [6:0] dipsw_pio_s1_burst_adapter_source0_channel; // dipsw_pio_s1_burst_adapter:source0_channel -> dipsw_pio_s1_agent:cp_channel
wire dipsw_pio_s1_burst_adapter_source0_startofpacket; // dipsw_pio_s1_burst_adapter:source0_startofpacket -> dipsw_pio_s1_agent:cp_startofpacket
wire dipsw_pio_s1_burst_adapter_source0_endofpacket; // dipsw_pio_s1_burst_adapter:source0_endofpacket -> dipsw_pio_s1_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> button_pio_s1_burst_adapter:sink0_valid
wire [128:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> button_pio_s1_burst_adapter:sink0_data
wire cmd_mux_006_src_ready; // button_pio_s1_burst_adapter:sink0_ready -> cmd_mux_006:src_ready
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> button_pio_s1_burst_adapter:sink0_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> button_pio_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> button_pio_s1_burst_adapter:sink0_endofpacket
wire button_pio_s1_burst_adapter_source0_valid; // button_pio_s1_burst_adapter:source0_valid -> button_pio_s1_agent:cp_valid
wire [128:0] button_pio_s1_burst_adapter_source0_data; // button_pio_s1_burst_adapter:source0_data -> button_pio_s1_agent:cp_data
wire button_pio_s1_burst_adapter_source0_ready; // button_pio_s1_agent:cp_ready -> button_pio_s1_burst_adapter:source0_ready
wire [6:0] button_pio_s1_burst_adapter_source0_channel; // button_pio_s1_burst_adapter:source0_channel -> button_pio_s1_agent:cp_channel
wire button_pio_s1_burst_adapter_source0_startofpacket; // button_pio_s1_burst_adapter:source0_startofpacket -> button_pio_s1_agent:cp_startofpacket
wire button_pio_s1_burst_adapter_source0_endofpacket; // button_pio_s1_burst_adapter:source0_endofpacket -> button_pio_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [164:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [164:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [6:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink0_valid
wire [128:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_002:src1_ready
wire [6:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_002:sink0_valid
wire [128:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_002_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_002:src2_ready
wire [6:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_002_src3_valid; // cmd_demux_002:src3_valid -> cmd_mux_003:sink0_valid
wire [128:0] cmd_demux_002_src3_data; // cmd_demux_002:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_002_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_002:src3_ready
wire [6:0] cmd_demux_002_src3_channel; // cmd_demux_002:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_002_src3_startofpacket; // cmd_demux_002:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_002_src3_endofpacket; // cmd_demux_002:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_002_src4_valid; // cmd_demux_002:src4_valid -> cmd_mux_004:sink0_valid
wire [128:0] cmd_demux_002_src4_data; // cmd_demux_002:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_002_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_002:src4_ready
wire [6:0] cmd_demux_002_src4_channel; // cmd_demux_002:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_002_src4_startofpacket; // cmd_demux_002:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_002_src4_endofpacket; // cmd_demux_002:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_002_src5_valid; // cmd_demux_002:src5_valid -> cmd_mux_005:sink0_valid
wire [128:0] cmd_demux_002_src5_data; // cmd_demux_002:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_002_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux_002:src5_ready
wire [6:0] cmd_demux_002_src5_channel; // cmd_demux_002:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_002_src5_startofpacket; // cmd_demux_002:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_002_src5_endofpacket; // cmd_demux_002:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_002_src6_valid; // cmd_demux_002:src6_valid -> cmd_mux_006:sink0_valid
wire [128:0] cmd_demux_002_src6_data; // cmd_demux_002:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_002_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux_002:src6_ready
wire [6:0] cmd_demux_002_src6_channel; // cmd_demux_002:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_002_src6_startofpacket; // cmd_demux_002:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_002_src6_endofpacket; // cmd_demux_002:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_003_src0_valid; // cmd_demux_003:src0_valid -> cmd_mux_001:sink1_valid
wire [128:0] cmd_demux_003_src0_data; // cmd_demux_003:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_003_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_003:src0_ready
wire [6:0] cmd_demux_003_src0_channel; // cmd_demux_003:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_003_src0_startofpacket; // cmd_demux_003:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_003_src0_endofpacket; // cmd_demux_003:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_003_src1_valid; // cmd_demux_003:src1_valid -> cmd_mux_003:sink1_valid
wire [128:0] cmd_demux_003_src1_data; // cmd_demux_003:src1_data -> cmd_mux_003:sink1_data
wire cmd_demux_003_src1_ready; // cmd_mux_003:sink1_ready -> cmd_demux_003:src1_ready
wire [6:0] cmd_demux_003_src1_channel; // cmd_demux_003:src1_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_003_src1_startofpacket; // cmd_demux_003:src1_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_003_src1_endofpacket; // cmd_demux_003:src1_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_003_src2_valid; // cmd_demux_003:src2_valid -> cmd_mux_004:sink1_valid
wire [128:0] cmd_demux_003_src2_data; // cmd_demux_003:src2_data -> cmd_mux_004:sink1_data
wire cmd_demux_003_src2_ready; // cmd_mux_004:sink1_ready -> cmd_demux_003:src2_ready
wire [6:0] cmd_demux_003_src2_channel; // cmd_demux_003:src2_channel -> cmd_mux_004:sink1_channel
wire cmd_demux_003_src2_startofpacket; // cmd_demux_003:src2_startofpacket -> cmd_mux_004:sink1_startofpacket
wire cmd_demux_003_src2_endofpacket; // cmd_demux_003:src2_endofpacket -> cmd_mux_004:sink1_endofpacket
wire cmd_demux_003_src3_valid; // cmd_demux_003:src3_valid -> cmd_mux_005:sink1_valid
wire [128:0] cmd_demux_003_src3_data; // cmd_demux_003:src3_data -> cmd_mux_005:sink1_data
wire cmd_demux_003_src3_ready; // cmd_mux_005:sink1_ready -> cmd_demux_003:src3_ready
wire [6:0] cmd_demux_003_src3_channel; // cmd_demux_003:src3_channel -> cmd_mux_005:sink1_channel
wire cmd_demux_003_src3_startofpacket; // cmd_demux_003:src3_startofpacket -> cmd_mux_005:sink1_startofpacket
wire cmd_demux_003_src3_endofpacket; // cmd_demux_003:src3_endofpacket -> cmd_mux_005:sink1_endofpacket
wire cmd_demux_003_src4_valid; // cmd_demux_003:src4_valid -> cmd_mux_006:sink1_valid
wire [128:0] cmd_demux_003_src4_data; // cmd_demux_003:src4_data -> cmd_mux_006:sink1_data
wire cmd_demux_003_src4_ready; // cmd_mux_006:sink1_ready -> cmd_demux_003:src4_ready
wire [6:0] cmd_demux_003_src4_channel; // cmd_demux_003:src4_channel -> cmd_mux_006:sink1_channel
wire cmd_demux_003_src4_startofpacket; // cmd_demux_003:src4_startofpacket -> cmd_mux_006:sink1_startofpacket
wire cmd_demux_003_src4_endofpacket; // cmd_demux_003:src4_endofpacket -> cmd_mux_006:sink1_endofpacket
wire cmd_demux_004_src0_valid; // cmd_demux_004:src0_valid -> cmd_mux_001:sink2_valid
wire [128:0] cmd_demux_004_src0_data; // cmd_demux_004:src0_data -> cmd_mux_001:sink2_data
wire cmd_demux_004_src0_ready; // cmd_mux_001:sink2_ready -> cmd_demux_004:src0_ready
wire [6:0] cmd_demux_004_src0_channel; // cmd_demux_004:src0_channel -> cmd_mux_001:sink2_channel
wire cmd_demux_004_src0_startofpacket; // cmd_demux_004:src0_startofpacket -> cmd_mux_001:sink2_startofpacket
wire cmd_demux_004_src0_endofpacket; // cmd_demux_004:src0_endofpacket -> cmd_mux_001:sink2_endofpacket
wire cmd_demux_004_src1_valid; // cmd_demux_004:src1_valid -> cmd_mux_003:sink2_valid
wire [128:0] cmd_demux_004_src1_data; // cmd_demux_004:src1_data -> cmd_mux_003:sink2_data
wire cmd_demux_004_src1_ready; // cmd_mux_003:sink2_ready -> cmd_demux_004:src1_ready
wire [6:0] cmd_demux_004_src1_channel; // cmd_demux_004:src1_channel -> cmd_mux_003:sink2_channel
wire cmd_demux_004_src1_startofpacket; // cmd_demux_004:src1_startofpacket -> cmd_mux_003:sink2_startofpacket
wire cmd_demux_004_src1_endofpacket; // cmd_demux_004:src1_endofpacket -> cmd_mux_003:sink2_endofpacket
wire cmd_demux_004_src2_valid; // cmd_demux_004:src2_valid -> cmd_mux_004:sink2_valid
wire [128:0] cmd_demux_004_src2_data; // cmd_demux_004:src2_data -> cmd_mux_004:sink2_data
wire cmd_demux_004_src2_ready; // cmd_mux_004:sink2_ready -> cmd_demux_004:src2_ready
wire [6:0] cmd_demux_004_src2_channel; // cmd_demux_004:src2_channel -> cmd_mux_004:sink2_channel
wire cmd_demux_004_src2_startofpacket; // cmd_demux_004:src2_startofpacket -> cmd_mux_004:sink2_startofpacket
wire cmd_demux_004_src2_endofpacket; // cmd_demux_004:src2_endofpacket -> cmd_mux_004:sink2_endofpacket
wire cmd_demux_004_src3_valid; // cmd_demux_004:src3_valid -> cmd_mux_005:sink2_valid
wire [128:0] cmd_demux_004_src3_data; // cmd_demux_004:src3_data -> cmd_mux_005:sink2_data
wire cmd_demux_004_src3_ready; // cmd_mux_005:sink2_ready -> cmd_demux_004:src3_ready
wire [6:0] cmd_demux_004_src3_channel; // cmd_demux_004:src3_channel -> cmd_mux_005:sink2_channel
wire cmd_demux_004_src3_startofpacket; // cmd_demux_004:src3_startofpacket -> cmd_mux_005:sink2_startofpacket
wire cmd_demux_004_src3_endofpacket; // cmd_demux_004:src3_endofpacket -> cmd_mux_005:sink2_endofpacket
wire cmd_demux_004_src4_valid; // cmd_demux_004:src4_valid -> cmd_mux_006:sink2_valid
wire [128:0] cmd_demux_004_src4_data; // cmd_demux_004:src4_data -> cmd_mux_006:sink2_data
wire cmd_demux_004_src4_ready; // cmd_mux_006:sink2_ready -> cmd_demux_004:src4_ready
wire [6:0] cmd_demux_004_src4_channel; // cmd_demux_004:src4_channel -> cmd_mux_006:sink2_channel
wire cmd_demux_004_src4_startofpacket; // cmd_demux_004:src4_startofpacket -> cmd_mux_006:sink2_startofpacket
wire cmd_demux_004_src4_endofpacket; // cmd_demux_004:src4_endofpacket -> cmd_mux_006:sink2_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [164:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [164:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [6:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_002:sink1_valid
wire [128:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src0_ready
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_003:sink0_valid
wire [128:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_003:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_003:sink0_ready -> rsp_demux_001:src1_ready
wire [6:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_003:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_003:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_003:sink0_endofpacket
wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> rsp_mux_004:sink0_valid
wire [128:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> rsp_mux_004:sink0_data
wire rsp_demux_001_src2_ready; // rsp_mux_004:sink0_ready -> rsp_demux_001:src2_ready
wire [6:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> rsp_mux_004:sink0_channel
wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> rsp_mux_004:sink0_startofpacket
wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> rsp_mux_004:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_002:sink2_valid
wire [128:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_002:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_002:sink2_ready -> rsp_demux_002:src0_ready
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_002:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_002:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_002:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_002:sink3_valid
wire [128:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_002:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_002:sink3_ready -> rsp_demux_003:src0_ready
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_002:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_002:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_002:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_003:sink1_valid
wire [128:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_003:sink1_data
wire rsp_demux_003_src1_ready; // rsp_mux_003:sink1_ready -> rsp_demux_003:src1_ready
wire [6:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_003:sink1_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_003:sink1_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_003:sink1_endofpacket
wire rsp_demux_003_src2_valid; // rsp_demux_003:src2_valid -> rsp_mux_004:sink1_valid
wire [128:0] rsp_demux_003_src2_data; // rsp_demux_003:src2_data -> rsp_mux_004:sink1_data
wire rsp_demux_003_src2_ready; // rsp_mux_004:sink1_ready -> rsp_demux_003:src2_ready
wire [6:0] rsp_demux_003_src2_channel; // rsp_demux_003:src2_channel -> rsp_mux_004:sink1_channel
wire rsp_demux_003_src2_startofpacket; // rsp_demux_003:src2_startofpacket -> rsp_mux_004:sink1_startofpacket
wire rsp_demux_003_src2_endofpacket; // rsp_demux_003:src2_endofpacket -> rsp_mux_004:sink1_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_002:sink4_valid
wire [128:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_002:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux_002:sink4_ready -> rsp_demux_004:src0_ready
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_002:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_002:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_002:sink4_endofpacket
wire rsp_demux_004_src1_valid; // rsp_demux_004:src1_valid -> rsp_mux_003:sink2_valid
wire [128:0] rsp_demux_004_src1_data; // rsp_demux_004:src1_data -> rsp_mux_003:sink2_data
wire rsp_demux_004_src1_ready; // rsp_mux_003:sink2_ready -> rsp_demux_004:src1_ready
wire [6:0] rsp_demux_004_src1_channel; // rsp_demux_004:src1_channel -> rsp_mux_003:sink2_channel
wire rsp_demux_004_src1_startofpacket; // rsp_demux_004:src1_startofpacket -> rsp_mux_003:sink2_startofpacket
wire rsp_demux_004_src1_endofpacket; // rsp_demux_004:src1_endofpacket -> rsp_mux_003:sink2_endofpacket
wire rsp_demux_004_src2_valid; // rsp_demux_004:src2_valid -> rsp_mux_004:sink2_valid
wire [128:0] rsp_demux_004_src2_data; // rsp_demux_004:src2_data -> rsp_mux_004:sink2_data
wire rsp_demux_004_src2_ready; // rsp_mux_004:sink2_ready -> rsp_demux_004:src2_ready
wire [6:0] rsp_demux_004_src2_channel; // rsp_demux_004:src2_channel -> rsp_mux_004:sink2_channel
wire rsp_demux_004_src2_startofpacket; // rsp_demux_004:src2_startofpacket -> rsp_mux_004:sink2_startofpacket
wire rsp_demux_004_src2_endofpacket; // rsp_demux_004:src2_endofpacket -> rsp_mux_004:sink2_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_002:sink5_valid
wire [128:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_002:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux_002:sink5_ready -> rsp_demux_005:src0_ready
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_002:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_002:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_002:sink5_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_003:sink3_valid
wire [128:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_003:sink3_data
wire rsp_demux_005_src1_ready; // rsp_mux_003:sink3_ready -> rsp_demux_005:src1_ready
wire [6:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_003:sink3_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_003:sink3_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_003:sink3_endofpacket
wire rsp_demux_005_src2_valid; // rsp_demux_005:src2_valid -> rsp_mux_004:sink3_valid
wire [128:0] rsp_demux_005_src2_data; // rsp_demux_005:src2_data -> rsp_mux_004:sink3_data
wire rsp_demux_005_src2_ready; // rsp_mux_004:sink3_ready -> rsp_demux_005:src2_ready
wire [6:0] rsp_demux_005_src2_channel; // rsp_demux_005:src2_channel -> rsp_mux_004:sink3_channel
wire rsp_demux_005_src2_startofpacket; // rsp_demux_005:src2_startofpacket -> rsp_mux_004:sink3_startofpacket
wire rsp_demux_005_src2_endofpacket; // rsp_demux_005:src2_endofpacket -> rsp_mux_004:sink3_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux_002:sink6_valid
wire [128:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux_002:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux_002:sink6_ready -> rsp_demux_006:src0_ready
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux_002:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux_002:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux_002:sink6_endofpacket
wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_003:sink4_valid
wire [128:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_003:sink4_data
wire rsp_demux_006_src1_ready; // rsp_mux_003:sink4_ready -> rsp_demux_006:src1_ready
wire [6:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_003:sink4_channel
wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_003:sink4_startofpacket
wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_003:sink4_endofpacket
wire rsp_demux_006_src2_valid; // rsp_demux_006:src2_valid -> rsp_mux_004:sink4_valid
wire [128:0] rsp_demux_006_src2_data; // rsp_demux_006:src2_data -> rsp_mux_004:sink4_data
wire rsp_demux_006_src2_ready; // rsp_mux_004:sink4_ready -> rsp_demux_006:src2_ready
wire [6:0] rsp_demux_006_src2_channel; // rsp_demux_006:src2_channel -> rsp_mux_004:sink4_channel
wire rsp_demux_006_src2_startofpacket; // rsp_demux_006:src2_startofpacket -> rsp_mux_004:sink4_startofpacket
wire rsp_demux_006_src2_endofpacket; // rsp_demux_006:src2_endofpacket -> rsp_mux_004:sink4_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_valid
wire [128:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_data
wire cmd_demux_002_src0_ready; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_ready -> cmd_demux_002:src0_ready
wire [6:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:in_endofpacket
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_valid -> cmd_mux:sink2_valid
wire [164:0] fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_data -> cmd_mux:sink2_data
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready; // cmd_mux:sink2_ready -> fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_ready
wire [6:0] fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_channel -> cmd_mux:sink2_channel
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink2_startofpacket
wire fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket; // fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink2_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_valid
wire [164:0] rsp_demux_src2_data; // rsp_demux:src2_data -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_data
wire rsp_demux_src2_ready; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_ready -> rsp_demux:src2_ready
wire [6:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:in_endofpacket
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_valid -> rsp_mux_002:sink0_valid
wire [128:0] onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_data -> rsp_mux_002:sink0_data
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready; // rsp_mux_002:sink0_ready -> onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_ready
wire [6:0] onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_channel -> rsp_mux_002:sink0_channel
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_startofpacket -> rsp_mux_002:sink0_startofpacket
wire onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket; // onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter:out_endofpacket -> rsp_mux_002:sink0_endofpacket
wire [6:0] fpga_only_master_master_limiter_cmd_valid_data; // fpga_only_master_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
wire [6:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux_003:sink_valid
wire [6:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_004:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) fpga_only_master_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (fpga_only_master_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (fpga_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (fpga_only_master_master_translator_avalon_universal_master_0_read), // .read
.uav_write (fpga_only_master_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (fpga_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (fpga_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (fpga_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (fpga_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (fpga_only_master_master_address), // avalon_anti_master_0.address
.av_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.av_byteenable (fpga_only_master_master_byteenable), // .byteenable
.av_read (fpga_only_master_master_read), // .read
.av_readdata (fpga_only_master_master_readdata), // .readdata
.av_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.av_write (fpga_only_master_master_write), // .write
.av_writedata (fpga_only_master_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) intr_capturer_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (intr_capturer_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (intr_capturer_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (intr_capturer_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (intr_capturer_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (intr_capturer_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (intr_capturer_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (intr_capturer_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (intr_capturer_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (intr_capturer_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_read (intr_capturer_0_avalon_slave_0_read), // .read
.av_readdata (intr_capturer_0_avalon_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_control_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_qsys_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_control_slave_agent_m0_read), // .read
.uav_write (sysid_qsys_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_pio_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (led_pio_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_pio_s1_agent_m0_burstcount), // .burstcount
.uav_read (led_pio_s1_agent_m0_read), // .read
.uav_write (led_pio_s1_agent_m0_write), // .write
.uav_waitrequest (led_pio_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_pio_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_pio_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (led_pio_s1_agent_m0_readdata), // .readdata
.uav_writedata (led_pio_s1_agent_m0_writedata), // .writedata
.uav_lock (led_pio_s1_agent_m0_lock), // .lock
.uav_debugaccess (led_pio_s1_agent_m0_debugaccess), // .debugaccess
.av_address (led_pio_s1_address), // avalon_anti_slave_0.address
.av_write (led_pio_s1_write), // .write
.av_readdata (led_pio_s1_readdata), // .readdata
.av_writedata (led_pio_s1_writedata), // .writedata
.av_chipselect (led_pio_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) dipsw_pio_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (dipsw_pio_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (dipsw_pio_s1_agent_m0_burstcount), // .burstcount
.uav_read (dipsw_pio_s1_agent_m0_read), // .read
.uav_write (dipsw_pio_s1_agent_m0_write), // .write
.uav_waitrequest (dipsw_pio_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (dipsw_pio_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (dipsw_pio_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (dipsw_pio_s1_agent_m0_readdata), // .readdata
.uav_writedata (dipsw_pio_s1_agent_m0_writedata), // .writedata
.uav_lock (dipsw_pio_s1_agent_m0_lock), // .lock
.uav_debugaccess (dipsw_pio_s1_agent_m0_debugaccess), // .debugaccess
.av_address (dipsw_pio_s1_address), // avalon_anti_slave_0.address
.av_write (dipsw_pio_s1_write), // .write
.av_readdata (dipsw_pio_s1_readdata), // .readdata
.av_writedata (dipsw_pio_s1_writedata), // .writedata
.av_chipselect (dipsw_pio_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) button_pio_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (button_pio_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (button_pio_s1_agent_m0_burstcount), // .burstcount
.uav_read (button_pio_s1_agent_m0_read), // .read
.uav_write (button_pio_s1_agent_m0_write), // .write
.uav_waitrequest (button_pio_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (button_pio_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (button_pio_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (button_pio_s1_agent_m0_readdata), // .readdata
.uav_writedata (button_pio_s1_agent_m0_writedata), // .writedata
.uav_lock (button_pio_s1_agent_m0_lock), // .lock
.uav_debugaccess (button_pio_s1_agent_m0_debugaccess), // .debugaccess
.av_address (button_pio_s1_address), // avalon_anti_slave_0.address
.av_write (button_pio_s1_write), // .write
.av_readdata (button_pio_s1_readdata), // .readdata
.av_writedata (button_pio_s1_writedata), // .writedata
.av_chipselect (button_pio_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (30),
.RDATA_WIDTH (64),
.WDATA_WIDTH (64),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (133),
.PKT_CACHE_H (159),
.PKT_CACHE_L (156),
.PKT_ADDR_SIDEBAND_H (131),
.PKT_ADDR_SIDEBAND_L (131),
.PKT_PROTECTION_H (155),
.PKT_PROTECTION_L (153),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_BURST_TYPE_H (130),
.PKT_BURST_TYPE_L (129),
.PKT_RESPONSE_STATUS_L (160),
.PKT_RESPONSE_STATUS_H (161),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_EXCLUSIVE (109),
.PKT_TRANS_LOCK (108),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (137),
.PKT_SRC_ID_L (135),
.PKT_DEST_ID_H (140),
.PKT_DEST_ID_L (138),
.PKT_THREAD_ID_H (152),
.PKT_THREAD_ID_L (141),
.PKT_QOS_L (134),
.PKT_QOS_H (134),
.PKT_ORI_BURST_SIZE_L (162),
.PKT_ORI_BURST_SIZE_H (164),
.PKT_DATA_SIDEBAND_H (132),
.PKT_DATA_SIDEBAND_L (132),
.ST_DATA_W (165),
.ST_CHANNEL_W (7),
.ID (1)
) hps_0_h2f_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (rsp_mux_src_valid), // write_rp.valid
.write_rp_data (rsp_mux_src_data), // .data
.write_rp_channel (rsp_mux_src_channel), // .channel
.write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.write_rp_ready (rsp_mux_src_ready), // .ready
.read_cp_valid (hps_0_h2f_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
.read_rp_data (rsp_mux_001_src_data), // .data
.read_rp_channel (rsp_mux_001_src_channel), // .channel
.read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.read_rp_ready (rsp_mux_001_src_ready), // .ready
.awid (hps_0_h2f_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_axi_master_awready), // .awready
.wid (hps_0_h2f_axi_master_wid), // .wid
.wdata (hps_0_h2f_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_axi_master_wready), // .wready
.bid (hps_0_h2f_axi_master_bid), // .bid
.bresp (hps_0_h2f_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_axi_master_bready), // .bready
.arid (hps_0_h2f_axi_master_arid), // .arid
.araddr (hps_0_h2f_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_axi_master_arready), // .arready
.rid (hps_0_h2f_axi_master_rid), // .rid
.rdata (hps_0_h2f_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_QOS_H (98),
.PKT_QOS_L (98),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_CACHE_H (123),
.PKT_CACHE_L (120),
.PKT_THREAD_ID_H (116),
.PKT_THREAD_ID_L (105),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (255),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) fpga_only_master_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (fpga_only_master_master_translator_avalon_universal_master_0_address), // av.address
.av_write (fpga_only_master_master_translator_avalon_universal_master_0_write), // .write
.av_read (fpga_only_master_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (fpga_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (fpga_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (fpga_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (fpga_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (fpga_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (fpga_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (fpga_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (fpga_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (fpga_only_master_master_agent_cp_valid), // cp.valid
.cp_data (fpga_only_master_master_agent_cp_data), // .data
.cp_startofpacket (fpga_only_master_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (fpga_only_master_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (fpga_only_master_master_agent_cp_ready), // .ready
.rp_valid (fpga_only_master_master_limiter_rsp_src_valid), // rp.valid
.rp_data (fpga_only_master_master_limiter_rsp_src_data), // .data
.rp_channel (fpga_only_master_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (fpga_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (fpga_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (fpga_only_master_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (97),
.PKT_CACHE_H (123),
.PKT_CACHE_L (120),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_RESPONSE_STATUS_L (124),
.PKT_RESPONSE_STATUS_H (125),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_THREAD_ID_H (116),
.PKT_THREAD_ID_L (105),
.PKT_QOS_L (98),
.PKT_QOS_H (98),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_ORI_BURST_SIZE_H (128),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.ID (2)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (164),
.PKT_ORI_BURST_SIZE_L (162),
.PKT_RESPONSE_STATUS_H (161),
.PKT_RESPONSE_STATUS_L (160),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_TRANS_LOCK (108),
.PKT_BEGIN_BURST (133),
.PKT_PROTECTION_H (155),
.PKT_PROTECTION_L (153),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (137),
.PKT_SRC_ID_L (135),
.PKT_DEST_ID_H (140),
.PKT_DEST_ID_L (138),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (165),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (onchip_memory2_0_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (onchip_memory2_0_s1_burst_adapter_source0_valid), // .valid
.cp_data (onchip_memory2_0_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (onchip_memory2_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (onchip_memory2_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (onchip_memory2_0_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_0_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_0_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_0_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (166),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (onchip_memory2_0_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid), // .valid
.cp_data (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) intr_capturer_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (intr_capturer_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (intr_capturer_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (intr_capturer_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (intr_capturer_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (intr_capturer_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (intr_capturer_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (intr_capturer_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (intr_capturer_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (intr_capturer_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (intr_capturer_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (intr_capturer_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (intr_capturer_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (intr_capturer_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (intr_capturer_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) intr_capturer_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (intr_capturer_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (intr_capturer_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (intr_capturer_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) intr_capturer_0_avalon_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_qsys_control_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_qsys_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_qsys_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (sysid_qsys_control_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (sysid_qsys_control_slave_burst_adapter_source0_valid), // .valid
.cp_data (sysid_qsys_control_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sysid_qsys_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sysid_qsys_control_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_control_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (sysid_qsys_control_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) led_pio_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (led_pio_s1_agent_m0_address), // m0.address
.m0_burstcount (led_pio_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_pio_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_pio_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_pio_s1_agent_m0_lock), // .lock
.m0_readdata (led_pio_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_pio_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_pio_s1_agent_m0_read), // .read
.m0_waitrequest (led_pio_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_pio_s1_agent_m0_writedata), // .writedata
.m0_write (led_pio_s1_agent_m0_write), // .write
.rp_endofpacket (led_pio_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_pio_s1_agent_rp_ready), // .ready
.rp_valid (led_pio_s1_agent_rp_valid), // .valid
.rp_data (led_pio_s1_agent_rp_data), // .data
.rp_startofpacket (led_pio_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (led_pio_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (led_pio_s1_burst_adapter_source0_valid), // .valid
.cp_data (led_pio_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (led_pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (led_pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (led_pio_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (led_pio_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_pio_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_pio_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_pio_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_pio_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_pio_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_pio_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_pio_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (led_pio_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (led_pio_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (led_pio_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (led_pio_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_pio_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_pio_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_pio_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_pio_s1_agent_rf_source_data), // in.data
.in_valid (led_pio_s1_agent_rf_source_valid), // .valid
.in_ready (led_pio_s1_agent_rf_source_ready), // .ready
.in_startofpacket (led_pio_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_pio_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_pio_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (led_pio_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_pio_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_pio_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (led_pio_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (led_pio_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (led_pio_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (led_pio_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (led_pio_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (led_pio_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) dipsw_pio_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (dipsw_pio_s1_agent_m0_address), // m0.address
.m0_burstcount (dipsw_pio_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (dipsw_pio_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (dipsw_pio_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (dipsw_pio_s1_agent_m0_lock), // .lock
.m0_readdata (dipsw_pio_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (dipsw_pio_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (dipsw_pio_s1_agent_m0_read), // .read
.m0_waitrequest (dipsw_pio_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (dipsw_pio_s1_agent_m0_writedata), // .writedata
.m0_write (dipsw_pio_s1_agent_m0_write), // .write
.rp_endofpacket (dipsw_pio_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (dipsw_pio_s1_agent_rp_ready), // .ready
.rp_valid (dipsw_pio_s1_agent_rp_valid), // .valid
.rp_data (dipsw_pio_s1_agent_rp_data), // .data
.rp_startofpacket (dipsw_pio_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (dipsw_pio_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (dipsw_pio_s1_burst_adapter_source0_valid), // .valid
.cp_data (dipsw_pio_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (dipsw_pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (dipsw_pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (dipsw_pio_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (dipsw_pio_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (dipsw_pio_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (dipsw_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (dipsw_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (dipsw_pio_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (dipsw_pio_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (dipsw_pio_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (dipsw_pio_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (dipsw_pio_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (dipsw_pio_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (dipsw_pio_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (dipsw_pio_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (dipsw_pio_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (dipsw_pio_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (dipsw_pio_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (dipsw_pio_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) dipsw_pio_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (dipsw_pio_s1_agent_rf_source_data), // in.data
.in_valid (dipsw_pio_s1_agent_rf_source_valid), // .valid
.in_ready (dipsw_pio_s1_agent_rf_source_ready), // .ready
.in_startofpacket (dipsw_pio_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (dipsw_pio_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (dipsw_pio_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (dipsw_pio_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (dipsw_pio_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (dipsw_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (dipsw_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) dipsw_pio_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (dipsw_pio_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (dipsw_pio_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (dipsw_pio_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (dipsw_pio_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (dipsw_pio_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (dipsw_pio_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (128),
.PKT_ORI_BURST_SIZE_L (126),
.PKT_RESPONSE_STATUS_H (125),
.PKT_RESPONSE_STATUS_L (124),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (119),
.PKT_PROTECTION_L (117),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (129),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) button_pio_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (button_pio_s1_agent_m0_address), // m0.address
.m0_burstcount (button_pio_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (button_pio_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (button_pio_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (button_pio_s1_agent_m0_lock), // .lock
.m0_readdata (button_pio_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (button_pio_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (button_pio_s1_agent_m0_read), // .read
.m0_waitrequest (button_pio_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (button_pio_s1_agent_m0_writedata), // .writedata
.m0_write (button_pio_s1_agent_m0_write), // .write
.rp_endofpacket (button_pio_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (button_pio_s1_agent_rp_ready), // .ready
.rp_valid (button_pio_s1_agent_rp_valid), // .valid
.rp_data (button_pio_s1_agent_rp_data), // .data
.rp_startofpacket (button_pio_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (button_pio_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (button_pio_s1_burst_adapter_source0_valid), // .valid
.cp_data (button_pio_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (button_pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (button_pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (button_pio_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (button_pio_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (button_pio_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (button_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (button_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (button_pio_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (button_pio_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (button_pio_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (button_pio_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (button_pio_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (button_pio_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (button_pio_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (button_pio_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (button_pio_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (button_pio_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (button_pio_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (button_pio_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (130),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) button_pio_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (button_pio_s1_agent_rf_source_data), // in.data
.in_valid (button_pio_s1_agent_rf_source_valid), // .valid
.in_ready (button_pio_s1_agent_rf_source_ready), // .ready
.in_startofpacket (button_pio_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (button_pio_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (button_pio_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (button_pio_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (button_pio_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (button_pio_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (button_pio_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) button_pio_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (button_pio_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (button_pio_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (button_pio_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (button_pio_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (button_pio_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (button_pio_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_system_mm_interconnect_0_router router (
.sink_ready (hps_0_h2f_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router router_001 (
.sink_ready (hps_0_h2f_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (fpga_only_master_master_agent_cp_ready), // sink.ready
.sink_valid (fpga_only_master_master_agent_cp_valid), // .valid
.sink_data (fpga_only_master_master_agent_cp_data), // .data
.sink_startofpacket (fpga_only_master_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (fpga_only_master_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_005 router_005 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_006 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_007 router_007 (
.sink_ready (intr_capturer_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (intr_capturer_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (intr_capturer_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_008 (
.sink_ready (sysid_qsys_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_qsys_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_009 (
.sink_ready (led_pio_s1_agent_rp_ready), // sink.ready
.sink_valid (led_pio_s1_agent_rp_valid), // .valid
.sink_data (led_pio_s1_agent_rp_data), // .data
.sink_startofpacket (led_pio_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_pio_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_010 (
.sink_ready (dipsw_pio_s1_agent_rp_ready), // sink.ready
.sink_valid (dipsw_pio_s1_agent_rp_valid), // .valid
.sink_data (dipsw_pio_s1_agent_rp_data), // .data
.sink_startofpacket (dipsw_pio_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (dipsw_pio_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_router_006 router_011 (
.sink_ready (button_pio_s1_agent_rp_ready), // sink.ready
.sink_valid (button_pio_s1_agent_rp_valid), // .valid
.sink_data (button_pio_s1_agent_rp_data), // .data
.sink_startofpacket (button_pio_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (button_pio_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.REORDER (0)
) fpga_only_master_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_002_src_valid), // .valid
.cmd_sink_data (router_002_src_data), // .data
.cmd_sink_channel (router_002_src_channel), // .channel
.cmd_sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (fpga_only_master_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (fpga_only_master_master_limiter_cmd_src_data), // .data
.cmd_src_channel (fpga_only_master_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (fpga_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (fpga_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (fpga_only_master_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (fpga_only_master_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (fpga_only_master_master_limiter_rsp_src_data), // .data
.rsp_src_channel (fpga_only_master_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (fpga_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (fpga_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (fpga_only_master_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.REORDER (0)
) hps_0_h2f_lw_axi_master_wr_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_003_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_003_src_valid), // .valid
.cmd_sink_data (router_003_src_data), // .data
.cmd_sink_channel (router_003_src_channel), // .channel
.cmd_sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_003_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_003_src_valid), // .valid
.rsp_sink_channel (rsp_mux_003_src_channel), // .channel
.rsp_sink_data (rsp_mux_003_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (102),
.PKT_SRC_ID_H (101),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (3),
.PIPELINED (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.REORDER (0)
) hps_0_h2f_lw_axi_master_rd_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_004_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_004_src_valid), // .valid
.cmd_sink_data (router_004_src_data), // .data
.cmd_sink_channel (router_004_src_channel), // .channel
.cmd_sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_004_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_004_src_valid), // .valid
.rsp_sink_channel (rsp_mux_004_src_channel), // .channel
.rsp_sink_data (rsp_mux_004_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_BEGIN_BURST (133),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_BURST_TYPE_H (130),
.PKT_BURST_TYPE_L (129),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (165),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (113),
.OUT_BURSTWRAP_H (125),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) onchip_memory2_0_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (onchip_memory2_0_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (onchip_memory2_0_s1_burst_adapter_source0_data), // .data
.source0_channel (onchip_memory2_0_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (onchip_memory2_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (onchip_memory2_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (onchip_memory2_0_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) jtag_uart_avalon_jtag_slave_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data), // .data
.source0_channel (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) sysid_qsys_control_slave_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_003_src_valid), // sink0.valid
.sink0_data (cmd_mux_003_src_data), // .data
.sink0_channel (cmd_mux_003_src_channel), // .channel
.sink0_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_003_src_ready), // .ready
.source0_valid (sysid_qsys_control_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (sysid_qsys_control_slave_burst_adapter_source0_data), // .data
.source0_channel (sysid_qsys_control_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sysid_qsys_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sysid_qsys_control_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) led_pio_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_004_src_valid), // sink0.valid
.sink0_data (cmd_mux_004_src_data), // .data
.sink0_channel (cmd_mux_004_src_channel), // .channel
.sink0_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_004_src_ready), // .ready
.source0_valid (led_pio_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (led_pio_s1_burst_adapter_source0_data), // .data
.source0_channel (led_pio_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (led_pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (led_pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (led_pio_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) dipsw_pio_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_005_src_valid), // sink0.valid
.sink0_data (cmd_mux_005_src_data), // .data
.sink0_channel (cmd_mux_005_src_channel), // .channel
.sink0_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_005_src_ready), // .ready
.source0_valid (dipsw_pio_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (dipsw_pio_s1_burst_adapter_source0_data), // .data
.source0_channel (dipsw_pio_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (dipsw_pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (dipsw_pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (dipsw_pio_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (129),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) button_pio_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_006_src_valid), // sink0.valid
.sink0_data (cmd_mux_006_src_data), // .data
.sink0_channel (cmd_mux_006_src_channel), // .channel
.sink0_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_006_src_ready), // .ready
.source0_valid (button_pio_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (button_pio_s1_burst_adapter_source0_data), // .data
.source0_channel (button_pio_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (button_pio_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (button_pio_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (button_pio_s1_burst_adapter_source0_ready) // .ready
);
soc_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (fpga_only_master_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (fpga_only_master_master_limiter_cmd_src_channel), // .channel
.sink_data (fpga_only_master_master_limiter_cmd_src_data), // .data
.sink_startofpacket (fpga_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (fpga_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (fpga_only_master_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
.src2_valid (cmd_demux_002_src2_valid), // .valid
.src2_data (cmd_demux_002_src2_data), // .data
.src2_channel (cmd_demux_002_src2_channel), // .channel
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_002_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_002_src3_ready), // src3.ready
.src3_valid (cmd_demux_002_src3_valid), // .valid
.src3_data (cmd_demux_002_src3_data), // .data
.src3_channel (cmd_demux_002_src3_channel), // .channel
.src3_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_002_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_002_src4_ready), // src4.ready
.src4_valid (cmd_demux_002_src4_valid), // .valid
.src4_data (cmd_demux_002_src4_data), // .data
.src4_channel (cmd_demux_002_src4_channel), // .channel
.src4_startofpacket (cmd_demux_002_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_002_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_002_src5_ready), // src5.ready
.src5_valid (cmd_demux_002_src5_valid), // .valid
.src5_data (cmd_demux_002_src5_data), // .data
.src5_channel (cmd_demux_002_src5_channel), // .channel
.src5_startofpacket (cmd_demux_002_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_002_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_002_src6_ready), // src6.ready
.src6_valid (cmd_demux_002_src6_valid), // .valid
.src6_data (cmd_demux_002_src6_data), // .data
.src6_channel (cmd_demux_002_src6_channel), // .channel
.src6_startofpacket (cmd_demux_002_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_002_src6_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_003 cmd_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_003_src0_ready), // src0.ready
.src0_valid (cmd_demux_003_src0_valid), // .valid
.src0_data (cmd_demux_003_src0_data), // .data
.src0_channel (cmd_demux_003_src0_channel), // .channel
.src0_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_003_src1_ready), // src1.ready
.src1_valid (cmd_demux_003_src1_valid), // .valid
.src1_data (cmd_demux_003_src1_data), // .data
.src1_channel (cmd_demux_003_src1_channel), // .channel
.src1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_003_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_003_src2_ready), // src2.ready
.src2_valid (cmd_demux_003_src2_valid), // .valid
.src2_data (cmd_demux_003_src2_data), // .data
.src2_channel (cmd_demux_003_src2_channel), // .channel
.src2_startofpacket (cmd_demux_003_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_003_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_003_src3_ready), // src3.ready
.src3_valid (cmd_demux_003_src3_valid), // .valid
.src3_data (cmd_demux_003_src3_data), // .data
.src3_channel (cmd_demux_003_src3_channel), // .channel
.src3_startofpacket (cmd_demux_003_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_003_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_003_src4_ready), // src4.ready
.src4_valid (cmd_demux_003_src4_valid), // .valid
.src4_data (cmd_demux_003_src4_data), // .data
.src4_channel (cmd_demux_003_src4_channel), // .channel
.src4_startofpacket (cmd_demux_003_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_003_src4_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_demux_003 cmd_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_004_src0_ready), // src0.ready
.src0_valid (cmd_demux_004_src0_valid), // .valid
.src0_data (cmd_demux_004_src0_data), // .data
.src0_channel (cmd_demux_004_src0_channel), // .channel
.src0_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_004_src1_ready), // src1.ready
.src1_valid (cmd_demux_004_src1_valid), // .valid
.src1_data (cmd_demux_004_src1_data), // .data
.src1_channel (cmd_demux_004_src1_channel), // .channel
.src1_startofpacket (cmd_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_004_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_004_src2_ready), // src2.ready
.src2_valid (cmd_demux_004_src2_valid), // .valid
.src2_data (cmd_demux_004_src2_data), // .data
.src2_channel (cmd_demux_004_src2_channel), // .channel
.src2_startofpacket (cmd_demux_004_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_004_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_004_src3_ready), // src3.ready
.src3_valid (cmd_demux_004_src3_valid), // .valid
.src3_data (cmd_demux_004_src3_data), // .data
.src3_channel (cmd_demux_004_src3_channel), // .channel
.src3_startofpacket (cmd_demux_004_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_004_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_004_src4_ready), // src4.ready
.src4_valid (cmd_demux_004_src4_valid), // .valid
.src4_data (cmd_demux_004_src4_data), // .data
.src4_channel (cmd_demux_004_src4_channel), // .channel
.src4_startofpacket (cmd_demux_004_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_004_src4_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready), // sink2.ready
.sink2_valid (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid), // .valid
.sink2_channel (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel), // .channel
.sink2_data (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data), // .data
.sink2_startofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink2_endofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src1_valid), // .valid
.sink0_channel (cmd_demux_002_src1_channel), // .channel
.sink0_data (cmd_demux_002_src1_data), // .data
.sink0_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src0_valid), // .valid
.sink1_channel (cmd_demux_003_src0_channel), // .channel
.sink1_data (cmd_demux_003_src0_data), // .data
.sink1_startofpacket (cmd_demux_003_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src0_valid), // .valid
.sink2_channel (cmd_demux_004_src0_channel), // .channel
.sink2_data (cmd_demux_004_src0_data), // .data
.sink2_startofpacket (cmd_demux_004_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src2_valid), // .valid
.sink0_channel (cmd_demux_002_src2_channel), // .channel
.sink0_data (cmd_demux_002_src2_data), // .data
.sink0_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src3_valid), // .valid
.sink0_channel (cmd_demux_002_src3_channel), // .channel
.sink0_data (cmd_demux_002_src3_data), // .data
.sink0_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src1_valid), // .valid
.sink1_channel (cmd_demux_003_src1_channel), // .channel
.sink1_data (cmd_demux_003_src1_data), // .data
.sink1_startofpacket (cmd_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src1_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src1_valid), // .valid
.sink2_channel (cmd_demux_004_src1_channel), // .channel
.sink2_data (cmd_demux_004_src1_data), // .data
.sink2_startofpacket (cmd_demux_004_src1_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src4_valid), // .valid
.sink0_channel (cmd_demux_002_src4_channel), // .channel
.sink0_data (cmd_demux_002_src4_data), // .data
.sink0_startofpacket (cmd_demux_002_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src2_valid), // .valid
.sink1_channel (cmd_demux_003_src2_channel), // .channel
.sink1_data (cmd_demux_003_src2_data), // .data
.sink1_startofpacket (cmd_demux_003_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src2_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src2_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src2_valid), // .valid
.sink2_channel (cmd_demux_004_src2_channel), // .channel
.sink2_data (cmd_demux_004_src2_data), // .data
.sink2_startofpacket (cmd_demux_004_src2_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src5_valid), // .valid
.sink0_channel (cmd_demux_002_src5_channel), // .channel
.sink0_data (cmd_demux_002_src5_data), // .data
.sink0_startofpacket (cmd_demux_002_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src3_valid), // .valid
.sink1_channel (cmd_demux_003_src3_channel), // .channel
.sink1_data (cmd_demux_003_src3_data), // .data
.sink1_startofpacket (cmd_demux_003_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src3_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src3_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src3_valid), // .valid
.sink2_channel (cmd_demux_004_src3_channel), // .channel
.sink2_data (cmd_demux_004_src3_data), // .data
.sink2_startofpacket (cmd_demux_004_src3_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_cmd_mux_001 cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src6_valid), // .valid
.sink0_channel (cmd_demux_002_src6_channel), // .channel
.sink0_data (cmd_demux_002_src6_data), // .data
.sink0_startofpacket (cmd_demux_002_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_003_src4_ready), // sink1.ready
.sink1_valid (cmd_demux_003_src4_valid), // .valid
.sink1_channel (cmd_demux_003_src4_channel), // .channel
.sink1_data (cmd_demux_003_src4_data), // .data
.sink1_startofpacket (cmd_demux_003_src4_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_003_src4_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_004_src4_ready), // sink2.ready
.sink2_valid (cmd_demux_004_src4_valid), // .valid
.sink2_channel (cmd_demux_004_src4_channel), // .channel
.sink2_data (cmd_demux_004_src4_data), // .data
.sink2_startofpacket (cmd_demux_004_src4_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_004_src4_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_demux_001_src2_valid), // .valid
.src2_data (rsp_demux_001_src2_data), // .data
.src2_channel (rsp_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_003_src2_ready), // src2.ready
.src2_valid (rsp_demux_003_src2_valid), // .valid
.src2_data (rsp_demux_003_src2_data), // .data
.src2_channel (rsp_demux_003_src2_channel), // .channel
.src2_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_003_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_demux_004_src1_valid), // .valid
.src1_data (rsp_demux_004_src1_data), // .data
.src1_channel (rsp_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_004_src2_ready), // src2.ready
.src2_valid (rsp_demux_004_src2_valid), // .valid
.src2_data (rsp_demux_004_src2_data), // .data
.src2_channel (rsp_demux_004_src2_channel), // .channel
.src2_startofpacket (rsp_demux_004_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_004_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_005_src2_ready), // src2.ready
.src2_valid (rsp_demux_005_src2_valid), // .valid
.src2_data (rsp_demux_005_src2_data), // .data
.src2_channel (rsp_demux_005_src2_channel), // .channel
.src2_startofpacket (rsp_demux_005_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_005_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_demux_001 rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_demux_006_src1_valid), // .valid
.src1_data (rsp_demux_006_src1_data), // .data
.src1_channel (rsp_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_006_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_006_src2_ready), // src2.ready
.src2_valid (rsp_demux_006_src2_valid), // .valid
.src2_data (rsp_demux_006_src2_data), // .data
.src2_channel (rsp_demux_006_src2_channel), // .channel
.src2_startofpacket (rsp_demux_006_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_006_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid), // .valid
.sink0_channel (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel), // .channel
.sink0_data (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux_003 rsp_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_003_src_ready), // src.ready
.src_valid (rsp_mux_003_src_valid), // .valid
.src_data (rsp_mux_003_src_data), // .data
.src_channel (rsp_mux_003_src_channel), // .channel
.src_startofpacket (rsp_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src1_valid), // .valid
.sink1_channel (rsp_demux_003_src1_channel), // .channel
.sink1_data (rsp_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_004_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_004_src1_valid), // .valid
.sink2_channel (rsp_demux_004_src1_channel), // .channel
.sink2_data (rsp_demux_004_src1_data), // .data
.sink2_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_005_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_005_src1_valid), // .valid
.sink3_channel (rsp_demux_005_src1_channel), // .channel
.sink3_data (rsp_demux_005_src1_data), // .data
.sink3_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_006_src1_ready), // sink4.ready
.sink4_valid (rsp_demux_006_src1_valid), // .valid
.sink4_channel (rsp_demux_006_src1_channel), // .channel
.sink4_data (rsp_demux_006_src1_data), // .data
.sink4_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_0_rsp_mux_003 rsp_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_004_src_ready), // src.ready
.src_valid (rsp_mux_004_src_valid), // .valid
.src_data (rsp_mux_004_src_data), // .data
.src_channel (rsp_mux_004_src_channel), // .channel
.src_startofpacket (rsp_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src2_valid), // .valid
.sink0_channel (rsp_demux_001_src2_channel), // .channel
.sink0_data (rsp_demux_001_src2_data), // .data
.sink0_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src2_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src2_valid), // .valid
.sink1_channel (rsp_demux_003_src2_channel), // .channel
.sink1_data (rsp_demux_003_src2_data), // .data
.sink1_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src2_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_004_src2_ready), // sink2.ready
.sink2_valid (rsp_demux_004_src2_valid), // .valid
.sink2_channel (rsp_demux_004_src2_channel), // .channel
.sink2_data (rsp_demux_004_src2_data), // .data
.sink2_startofpacket (rsp_demux_004_src2_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_004_src2_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_005_src2_ready), // sink3.ready
.sink3_valid (rsp_demux_005_src2_valid), // .valid
.sink3_channel (rsp_demux_005_src2_channel), // .channel
.sink3_data (rsp_demux_005_src2_data), // .data
.sink3_startofpacket (rsp_demux_005_src2_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_005_src2_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_006_src2_ready), // sink4.ready
.sink4_valid (rsp_demux_006_src2_valid), // .valid
.sink4_channel (rsp_demux_006_src2_channel), // .channel
.sink4_data (rsp_demux_006_src2_data), // .data
.sink4_startofpacket (rsp_demux_006_src2_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_006_src2_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (81),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (89),
.IN_PKT_BURSTWRAP_L (82),
.IN_PKT_BURST_SIZE_H (92),
.IN_PKT_BURST_SIZE_L (90),
.IN_PKT_RESPONSE_STATUS_H (125),
.IN_PKT_RESPONSE_STATUS_L (124),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (94),
.IN_PKT_BURST_TYPE_L (93),
.IN_PKT_ORI_BURST_SIZE_L (126),
.IN_PKT_ORI_BURST_SIZE_H (128),
.IN_ST_DATA_W (129),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (117),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (128),
.OUT_PKT_BURST_SIZE_L (126),
.OUT_PKT_RESPONSE_STATUS_H (161),
.OUT_PKT_RESPONSE_STATUS_L (160),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (130),
.OUT_PKT_BURST_TYPE_L (129),
.OUT_PKT_ORI_BURST_SIZE_L (162),
.OUT_PKT_ORI_BURST_SIZE_H (164),
.OUT_ST_DATA_W (165),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (1)
) fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_002_src0_valid), // sink.valid
.in_channel (cmd_demux_002_src0_channel), // .channel
.in_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_002_src0_ready), // .ready
.in_data (cmd_demux_002_src0_data), // .data
.out_endofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_data), // .data
.out_channel (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (117),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_BURSTWRAP_H (125),
.IN_PKT_BURSTWRAP_L (118),
.IN_PKT_BURST_SIZE_H (128),
.IN_PKT_BURST_SIZE_L (126),
.IN_PKT_RESPONSE_STATUS_H (161),
.IN_PKT_RESPONSE_STATUS_L (160),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (130),
.IN_PKT_BURST_TYPE_L (129),
.IN_PKT_ORI_BURST_SIZE_L (162),
.IN_PKT_ORI_BURST_SIZE_H (164),
.IN_ST_DATA_W (165),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (81),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (92),
.OUT_PKT_BURST_SIZE_L (90),
.OUT_PKT_RESPONSE_STATUS_H (125),
.OUT_PKT_RESPONSE_STATUS_L (124),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (94),
.OUT_PKT_BURST_TYPE_L (93),
.OUT_PKT_ORI_BURST_SIZE_L (126),
.OUT_PKT_ORI_BURST_SIZE_H (128),
.OUT_ST_DATA_W (129),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (1)
) onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (onchip_memory2_0_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src2_valid), // sink.valid
.in_channel (rsp_demux_src2_channel), // .channel
.in_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.in_ready (rsp_demux_src2_ready), // .ready
.in_data (rsp_demux_src2_data), // .data
.out_endofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_data), // .data
.out_channel (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_channel), // .channel
.out_valid (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_valid), // .valid
.out_ready (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFRTP_PP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:20 11/10/2016
// Design Name:
// Module Name: ceespu_execute
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ceespu_execute(
input I_clk,
input I_rst,
input [3:0] I_aluop,
input I_we,
input [1:0] I_selWb,
input I_prediction,
input I_isBranch,
input [2:0] I_branchop,
input [31:0] I_storeData,
input [31:0] I_dataA,
input [31:0] I_dataB,
input [1:0] I_selCin,
input [4:0] I_regD,
input I_memE,
input I_memWe,
input [2:0] I_selMem,
input [13:0] I_PC,
input [13:0] I_branchTarget,
output reg [13:0] O_branchTarget,
output [31:0] O_memAddress,
output reg O_we = 0,
output reg [31:0] O_aluResult = 0,
output reg [31:0] O_StoreData = 0,
output reg [1:0] O_selWb = 0,
output reg [2:0] O_selMem = 0,
output reg O_memE = 0,
output reg [3:0] O_memWe = 0,
output reg [13:0] O_PC = 0,
output reg [4:0] O_regD = 0,
output reg O_busy = 0,
output O_branch_mispredict,
output O_branch_taken
);
reg Cin;
reg Carry;
wire [31:0] aluResult;
wire [31:0] adderResult;
wire multiCycle;
wire Cout;
wire ready;
wire doBranch;
ceespu_alu alu(I_clk, I_rst, I_dataA, I_dataB, Cin, I_aluop, multiCycle, adderResult, aluResult, Cout, ready);
ceespu_compare compare(I_dataA, I_dataB, I_branchop, Carry, doBranch);
assign O_memAddress = adderResult;
assign O_branch_mispredict = I_isBranch && (doBranch != I_prediction);
assign O_branch_taken = doBranch;
always @* begin
O_busy = (!ready) && multiCycle;
O_memE = I_memE;
if (I_selMem[1:0] == 2) begin
O_StoreData = {I_storeData[7:0], I_storeData[7:0], I_storeData[7:0], I_storeData[7:0]};
end
else if (I_selMem[1:0] == 1) begin
O_StoreData = {I_storeData[15:0], I_storeData[15:0]};
end
else begin
O_StoreData = I_storeData;
end
O_memWe = 4'b0000;
if (I_memE && I_memWe) begin
if (I_selMem[1:0] == 2) begin
case (adderResult[1:0])
0: O_memWe = 4'b0001;
1: O_memWe = 4'b0010;
2: O_memWe = 4'b0100;
3: O_memWe = 4'b1000;
endcase
end
else if (I_selMem[1:0] == 1) begin
O_memWe = (adderResult[0]) ? 4'b1100 : 4'b0011;
end
else begin
O_memWe = 4'b1111;
end
end
else if(I_memE) begin
O_memWe = 4'b0000;
end
case (I_selCin)
2'd0: Cin = 0;
2'd1: Cin = Carry;
2'd2: Cin = !Carry;
2'd3: Cin = 1;
endcase
if(I_prediction) begin
O_branchTarget = I_PC; // PC is already the PC of the next instruction
end
else begin //FIXME: writeback data hazards are not handled yet for bx instructions
O_branchTarget = I_branchTarget;
end
end
always @(posedge I_clk) begin
Carry <= Cout;
O_we <= I_we & ! O_busy;
O_regD <= I_regD;
O_PC <= I_PC;
O_aluResult <= aluResult;
O_selWb <= I_selWb;
O_selMem <= I_selMem;
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND4B_PP_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_PP_SYMBOL_V
|
//Legal Notice: (C)2021 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "onchip_mem.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/14/2014 05:34:33 PM
// Design Name:
// Module Name: delta_sigma
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delta_sigma(
input [15:0] din,
input clk_i,
output reg dout
);
// PWM module to take in PWM data and play it out on a one line speaker
// mainly taken from:
// http://www.fpga4fun.com/PWM_DAC.html
// sigma delta PWM
reg [16:0] PWM_accumulator;
always @(posedge clk_i) begin
PWM_accumulator[16:0] = PWM_accumulator[15:0] + {~din[15], din[14:0]}; // plus sigma
dout = PWM_accumulator[16];
//PWM_accumulator[16] = 0; // delta : subtract 256
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: oq_regs.v
// Project: NF2.1
// Description: Demultiplexes, stores and serves register requests
//
///////////////////////////////////////////////////////////////////////////////
module oq_regs
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH)
)
(
// --- interface to udp_reg_grp
reg_req_in,
reg_ack_in,
reg_rd_wr_L_in,
reg_addr_in,
reg_data_in,
reg_src_in,
reg_req_out,
reg_ack_out,
reg_rd_wr_L_out,
reg_addr_out,
reg_data_out,
reg_src_out,
// --- interface to remove_pkt
src_oq_rd_addr,
src_oq_high_addr,
src_oq_low_addr,
src_oq_empty,
src_oq_rd_addr_new,
pkt_removed,
removed_pkt_data_length,
removed_pkt_overhead_length,
removed_pkt_total_word_length,
src_oq,
removed_oq,
rd_src_addr,
enable_send_pkt,
// --- interface to store_pkt
dst_oq_wr_addr_new,
pkt_stored,
stored_pkt_data_length,
stored_pkt_overhead_length,
stored_pkt_total_word_length,
pkt_dropped,
dst_oq,
rd_dst_addr,
dst_oq_high_addr,
dst_oq_low_addr,
dst_oq_wr_addr,
dst_oq_full,
// --- Misc
clk,
reset
);
// --- interface to udp_reg_grp
input reg_req_in;
input reg_ack_in;
input reg_rd_wr_L_in;
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in;
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in;
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in;
output reg_req_out;
output reg_ack_out;
output reg_rd_wr_L_out;
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out;
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out;
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out;
// --- interface to remove_pkt
output [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr;
output [SRAM_ADDR_WIDTH-1:0] src_oq_high_addr;
output [SRAM_ADDR_WIDTH-1:0] src_oq_low_addr;
output [NUM_OUTPUT_QUEUES-1:0] src_oq_empty;
input [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr_new;
input pkt_removed;
input [PKT_LEN_WIDTH-1:0] removed_pkt_data_length;
input [CTRL_WIDTH-1:0] removed_pkt_overhead_length;
input [PKT_WORDS_WIDTH-1:0] removed_pkt_total_word_length;
input [NUM_OQ_WIDTH-1:0] src_oq;
input [NUM_OQ_WIDTH-1:0] removed_oq;
input rd_src_addr;
output [NUM_OUTPUT_QUEUES-1:0] enable_send_pkt;
// --- interface to store_pkt
input [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
input pkt_stored;
input [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
input [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
input [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
input pkt_dropped;
input [NUM_OQ_WIDTH-1:0] dst_oq;
input rd_dst_addr;
output [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
output [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
output [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
output [NUM_OUTPUT_QUEUES-1:0] dst_oq_full;
// --- Misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 17;
localparam MAX_PKT = 2048/CTRL_WIDTH; // allow for 2K bytes
localparam MIN_PKT = 60/CTRL_WIDTH + 1; // allow for 2K bytes
localparam PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT);
localparam ADDR_WIDTH = log2(NUM_REGS_USED);
// ------------- Wires/reg ------------------
// Register interfaces
wire [NUM_OQ_WIDTH-1:0] reg_addr;
wire num_pkt_bytes_stored_reg_req;
wire num_pkt_bytes_stored_reg_ack;
wire num_pkt_bytes_stored_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_stored_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_stored_reg_rd_data;
wire num_overhead_bytes_stored_reg_req;
wire num_overhead_bytes_stored_reg_ack;
wire num_overhead_bytes_stored_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_stored_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_stored_reg_rd_data;
wire num_pkts_stored_reg_req;
wire num_pkts_stored_reg_ack;
wire num_pkts_stored_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_stored_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_stored_reg_rd_data;
wire num_pkts_dropped_reg_req;
wire num_pkts_dropped_reg_ack;
wire num_pkts_dropped_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_dropped_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_dropped_reg_rd_data;
wire num_pkt_bytes_removed_reg_req;
wire num_pkt_bytes_removed_reg_ack;
wire num_pkt_bytes_removed_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_removed_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_removed_reg_rd_data;
wire num_overhead_bytes_removed_reg_req;
wire num_overhead_bytes_removed_reg_ack;
wire num_overhead_bytes_removed_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_removed_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_removed_reg_rd_data;
wire num_pkts_removed_reg_req;
wire num_pkts_removed_reg_ack;
wire num_pkts_removed_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_removed_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_removed_reg_rd_data;
wire oq_addr_hi_reg_req;
wire oq_addr_hi_reg_ack;
wire oq_addr_hi_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_rd_data;
wire oq_addr_lo_reg_req;
wire oq_addr_lo_reg_ack;
wire oq_addr_lo_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_rd_data;
wire oq_wr_addr_reg_req;
wire oq_wr_addr_reg_ack;
wire oq_wr_addr_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_wr_addr_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_wr_addr_reg_rd_data;
wire oq_rd_addr_reg_req;
wire oq_rd_addr_reg_ack;
wire oq_rd_addr_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_rd_addr_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_rd_addr_reg_rd_data;
wire max_pkts_in_q_reg_req;
wire max_pkts_in_q_reg_ack;
wire max_pkts_in_q_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] max_pkts_in_q_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] max_pkts_in_q_reg_rd_data;
wire num_pkts_in_q_reg_req;
wire num_pkts_in_q_reg_ack;
wire num_pkts_in_q_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_in_q_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_in_q_reg_rd_data;
wire num_words_left_reg_req;
wire num_words_left_reg_ack;
wire num_words_left_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_left_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_left_reg_rd_data;
wire num_words_in_q_reg_req;
wire num_words_in_q_reg_ack;
wire num_words_in_q_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_in_q_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] num_words_in_q_reg_rd_data;
wire oq_full_thresh_reg_req;
wire oq_full_thresh_reg_ack;
wire oq_full_thresh_reg_wr;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_full_thresh_reg_wr_data;
wire [`CPCI_NF2_DATA_WIDTH-1:0] oq_full_thresh_reg_rd_data;
// Values used to calculate full/emtpy state
wire [PKTS_IN_RAM_WIDTH-1:0] max_pkts_in_q_dst;
wire [PKTS_IN_RAM_WIDTH-1:0] num_pkts_in_q_dst;
wire num_pkts_in_q_dst_wr_done;
wire [PKTS_IN_RAM_WIDTH-1:0] max_pkts_in_q_src;
wire [PKTS_IN_RAM_WIDTH-1:0] num_pkts_in_q_src;
wire num_pkts_in_q_src_wr_done;
wire [SRAM_ADDR_WIDTH-1:0] oq_full_thresh_dst;
wire [SRAM_ADDR_WIDTH-1:0] num_words_left_dst;
wire num_words_left_dst_wr_done;
wire [SRAM_ADDR_WIDTH-1:0] oq_full_thresh_src;
wire [SRAM_ADDR_WIDTH-1:0] num_words_left_src;
wire num_words_left_src_wr_done;
// --- interface to oq_regs_host_iface
wire reg_req;
wire reg_rd_wr_L_held;
wire [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_held;
wire [ADDR_WIDTH-1:0] addr;
wire [NUM_OQ_WIDTH-1:0] q_addr;
wire result_ready;
wire [`CPCI_NF2_DATA_WIDTH-1:0] reg_result;
wire [NUM_OUTPUT_QUEUES-1:0] empty;
wire [NUM_OUTPUT_QUEUES-1:0] full;
wire initialize;
wire [NUM_OQ_WIDTH-1:0] initialize_oq;
// --------- logic ---------------------------
assign src_oq_empty = empty;
assign dst_oq_full = full;
// -------------------------------------------
// Control module
// -- Contains logic for resetting the queues, initalizing the queues on
// writes to the control register and logic to process register requests
// from the host
// -------------------------------------------
oq_regs_ctrl
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.NUM_REGS_USED (NUM_REGS_USED),
.MAX_PKT (MAX_PKT), // allow for 2K bytes
.PKT_LEN_WIDTH (PKT_LEN_WIDTH)
) oq_regs_ctrl (
// --- interface to store/remove pkt
.enable (enable_send_pkt),
// --- interface to oq_regs_host_iface
.reg_req (req_in_progress),
.reg_rd_wr_L_held (reg_rd_wr_L_held),
.reg_data_held (reg_data_held),
.addr (addr),
.q_addr (q_addr),
.result_ready (result_ready),
.reg_result (reg_result),
// --- Interface to full/empty generation logic
.initialize (initialize),
.initialize_oq (initialize_oq),
// Register interfaces
.reg_addr (reg_addr),
.num_pkt_bytes_stored_reg_req (num_pkt_bytes_stored_reg_req),
.num_pkt_bytes_stored_reg_ack (num_pkt_bytes_stored_reg_ack),
.num_pkt_bytes_stored_reg_wr (num_pkt_bytes_stored_reg_wr),
.num_pkt_bytes_stored_reg_wr_data (num_pkt_bytes_stored_reg_wr_data),
.num_pkt_bytes_stored_reg_rd_data (num_pkt_bytes_stored_reg_rd_data),
.num_overhead_bytes_stored_reg_req (num_overhead_bytes_stored_reg_req),
.num_overhead_bytes_stored_reg_ack (num_overhead_bytes_stored_reg_ack),
.num_overhead_bytes_stored_reg_wr (num_overhead_bytes_stored_reg_wr),
.num_overhead_bytes_stored_reg_wr_data (num_overhead_bytes_stored_reg_wr_data),
.num_overhead_bytes_stored_reg_rd_data (num_overhead_bytes_stored_reg_rd_data),
.num_pkts_stored_reg_req (num_pkts_stored_reg_req),
.num_pkts_stored_reg_ack (num_pkts_stored_reg_ack),
.num_pkts_stored_reg_wr (num_pkts_stored_reg_wr),
.num_pkts_stored_reg_wr_data (num_pkts_stored_reg_wr_data),
.num_pkts_stored_reg_rd_data (num_pkts_stored_reg_rd_data),
.num_pkts_dropped_reg_req (num_pkts_dropped_reg_req),
.num_pkts_dropped_reg_ack (num_pkts_dropped_reg_ack),
.num_pkts_dropped_reg_wr (num_pkts_dropped_reg_wr),
.num_pkts_dropped_reg_wr_data (num_pkts_dropped_reg_wr_data),
.num_pkts_dropped_reg_rd_data (num_pkts_dropped_reg_rd_data),
.num_pkt_bytes_removed_reg_req (num_pkt_bytes_removed_reg_req),
.num_pkt_bytes_removed_reg_ack (num_pkt_bytes_removed_reg_ack),
.num_pkt_bytes_removed_reg_wr (num_pkt_bytes_removed_reg_wr),
.num_pkt_bytes_removed_reg_wr_data (num_pkt_bytes_removed_reg_wr_data),
.num_pkt_bytes_removed_reg_rd_data (num_pkt_bytes_removed_reg_rd_data),
.num_overhead_bytes_removed_reg_req (num_overhead_bytes_removed_reg_req),
.num_overhead_bytes_removed_reg_ack (num_overhead_bytes_removed_reg_ack),
.num_overhead_bytes_removed_reg_wr (num_overhead_bytes_removed_reg_wr),
.num_overhead_bytes_removed_reg_wr_data(num_overhead_bytes_removed_reg_wr_data),
.num_overhead_bytes_removed_reg_rd_data(num_overhead_bytes_removed_reg_rd_data),
.num_pkts_removed_reg_req (num_pkts_removed_reg_req),
.num_pkts_removed_reg_ack (num_pkts_removed_reg_ack),
.num_pkts_removed_reg_wr (num_pkts_removed_reg_wr),
.num_pkts_removed_reg_wr_data (num_pkts_removed_reg_wr_data),
.num_pkts_removed_reg_rd_data (num_pkts_removed_reg_rd_data),
.oq_addr_hi_reg_req (oq_addr_hi_reg_req),
.oq_addr_hi_reg_ack (oq_addr_hi_reg_ack),
.oq_addr_hi_reg_wr (oq_addr_hi_reg_wr),
.oq_addr_hi_reg_wr_data (oq_addr_hi_reg_wr_data),
.oq_addr_hi_reg_rd_data (oq_addr_hi_reg_rd_data),
.oq_addr_lo_reg_req (oq_addr_lo_reg_req),
.oq_addr_lo_reg_ack (oq_addr_lo_reg_ack),
.oq_addr_lo_reg_wr (oq_addr_lo_reg_wr),
.oq_addr_lo_reg_wr_data (oq_addr_lo_reg_wr_data),
.oq_addr_lo_reg_rd_data (oq_addr_lo_reg_rd_data),
.oq_wr_addr_reg_req (oq_wr_addr_reg_req),
.oq_wr_addr_reg_ack (oq_wr_addr_reg_ack),
.oq_wr_addr_reg_wr (oq_wr_addr_reg_wr),
.oq_wr_addr_reg_wr_data (oq_wr_addr_reg_wr_data),
.oq_wr_addr_reg_rd_data (oq_wr_addr_reg_rd_data),
.oq_rd_addr_reg_req (oq_rd_addr_reg_req),
.oq_rd_addr_reg_ack (oq_rd_addr_reg_ack),
.oq_rd_addr_reg_wr (oq_rd_addr_reg_wr),
.oq_rd_addr_reg_wr_data (oq_rd_addr_reg_wr_data),
.oq_rd_addr_reg_rd_data (oq_rd_addr_reg_rd_data),
.max_pkts_in_q_reg_req (max_pkts_in_q_reg_req),
.max_pkts_in_q_reg_ack (max_pkts_in_q_reg_ack),
.max_pkts_in_q_reg_wr (max_pkts_in_q_reg_wr),
.max_pkts_in_q_reg_wr_data (max_pkts_in_q_reg_wr_data),
.max_pkts_in_q_reg_rd_data (max_pkts_in_q_reg_rd_data),
.num_pkts_in_q_reg_req (num_pkts_in_q_reg_req),
.num_pkts_in_q_reg_ack (num_pkts_in_q_reg_ack),
.num_pkts_in_q_reg_wr (num_pkts_in_q_reg_wr),
.num_pkts_in_q_reg_wr_data (num_pkts_in_q_reg_wr_data),
.num_pkts_in_q_reg_rd_data (num_pkts_in_q_reg_rd_data),
.num_words_left_reg_req (num_words_left_reg_req),
.num_words_left_reg_ack (num_words_left_reg_ack),
.num_words_left_reg_wr (num_words_left_reg_wr),
.num_words_left_reg_wr_data (num_words_left_reg_wr_data),
.num_words_left_reg_rd_data (num_words_left_reg_rd_data),
.num_words_in_q_reg_req (num_words_in_q_reg_req),
.num_words_in_q_reg_ack (num_words_in_q_reg_ack),
.num_words_in_q_reg_wr (num_words_in_q_reg_wr),
.num_words_in_q_reg_wr_data (num_words_in_q_reg_wr_data),
.num_words_in_q_reg_rd_data (num_words_in_q_reg_rd_data),
.oq_full_thresh_reg_req (oq_full_thresh_reg_req),
.oq_full_thresh_reg_ack (oq_full_thresh_reg_ack),
.oq_full_thresh_reg_wr (oq_full_thresh_reg_wr),
.oq_full_thresh_reg_wr_data (oq_full_thresh_reg_wr_data),
.oq_full_thresh_reg_rd_data (oq_full_thresh_reg_rd_data),
// --- Misc
.clk (clk),
.reset (reset)
);
// -------------------------------------------
// Empty/full signal generation logic
// -- Analyzes the number of packets/number of words in each queue on
// updates
// -------------------------------------------
oq_regs_eval_empty
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH (PKT_LEN_WIDTH),
.MAX_PKT (MAX_PKT)
) oq_regs_eval_empty (
// --- Inputs from dst update ---
.dst_update (pkt_stored),
.dst_oq (dst_oq),
.dst_num_pkts_in_q (num_pkts_in_q_dst),
.dst_num_pkts_in_q_done (num_pkts_in_q_dst_wr_done),
// --- Inputs from src update ---
.src_update (pkt_removed),
.src_oq (removed_oq),
.src_num_pkts_in_q (num_pkts_in_q_src),
.src_num_pkts_in_q_done (num_pkts_in_q_src_wr_done),
// --- Clear the flag ---
.initialize (initialize),
.initialize_oq (initialize_oq),
.empty (empty),
// --- Misc
.clk (clk),
.reset (reset)
);
oq_regs_eval_full
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH (PKT_LEN_WIDTH),
.MAX_PKT (MAX_PKT)
) oq_regs_eval_full (
// --- Inputs from dst update ---
.dst_update (pkt_stored),
.dst_oq (dst_oq),
.dst_max_pkts_in_q (max_pkts_in_q_dst),
.dst_num_pkts_in_q (num_pkts_in_q_dst),
.dst_num_pkts_in_q_done (num_pkts_in_q_dst_wr_done),
.dst_oq_full_thresh (oq_full_thresh_dst),
.dst_num_words_left (num_words_left_dst),
.dst_num_words_left_done (num_words_left_dst_wr_done),
// --- Inputs from src update ---
.src_update (pkt_removed),
.src_oq (removed_oq),
.src_max_pkts_in_q (max_pkts_in_q_src),
.src_num_pkts_in_q (num_pkts_in_q_src),
.src_num_pkts_in_q_done (num_pkts_in_q_src_wr_done),
.src_oq_full_thresh (oq_full_thresh_src),
.src_num_words_left (num_words_left_src),
.src_num_words_left_done (num_words_left_src_wr_done),
// --- Clear the flag ---
.initialize (initialize),
.initialize_oq (initialize_oq),
.full (full),
// --- Misc
.clk (clk),
.reset (reset)
);
// -------------------------------------------
// Host interface module
// -- initial processing of incoming register
// requests
// -- most of the register processing is handed
// off to oq_regs_host_ctrl
// -------------------------------------------
oq_regs_host_iface
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.NUM_REGS_USED (NUM_REGS_USED)
) oq_regs_host_iface (
// --- interface to udp_reg_grp
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- interface to oq_regs_process_sm
.req_in_progress (req_in_progress),
.reg_rd_wr_L_held (reg_rd_wr_L_held),
.reg_data_held (reg_data_held),
.addr (addr),
.q_addr (q_addr),
.result_ready (result_ready),
.reg_result (reg_result),
// --- Misc
.clk (clk),
.reset (reset)
);
// -------------------------------------------
// Register instances module
// -- Holds the memory instances for all registers except the control
// register
// -------------------------------------------
oq_reg_instances
#(
.SRAM_ADDR_WIDTH (SRAM_ADDR_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_OUTPUT_QUEUES (NUM_OUTPUT_QUEUES),
.PKT_LEN_WIDTH (PKT_LEN_WIDTH),
.MAX_PKT (MAX_PKT)
) oq_reg_instances (
// --- interface to remove_pkt
.src_oq_rd_addr (src_oq_rd_addr),
.src_oq_high_addr (src_oq_high_addr),
.src_oq_low_addr (src_oq_low_addr),
.src_oq_rd_addr_new (src_oq_rd_addr_new),
.pkt_removed (pkt_removed),
.removed_pkt_data_length (removed_pkt_data_length),
.removed_pkt_overhead_length (removed_pkt_overhead_length),
.removed_pkt_total_word_length (removed_pkt_total_word_length),
.src_oq (src_oq),
.removed_oq (removed_oq),
.rd_src_addr (rd_src_addr),
// --- interface to store_pkt
.dst_oq_wr_addr_new (dst_oq_wr_addr_new),
.pkt_stored (pkt_stored),
.stored_pkt_data_length (stored_pkt_data_length),
.stored_pkt_overhead_length (stored_pkt_overhead_length),
.stored_pkt_total_word_length (stored_pkt_total_word_length),
.pkt_dropped (pkt_dropped),
.dst_oq (dst_oq),
.rd_dst_addr (rd_dst_addr),
.dst_oq_high_addr (dst_oq_high_addr),
.dst_oq_low_addr (dst_oq_low_addr),
.dst_oq_wr_addr (dst_oq_wr_addr),
// Register interfaces
.reg_addr (reg_addr),
.num_pkt_bytes_stored_reg_req (num_pkt_bytes_stored_reg_req),
.num_pkt_bytes_stored_reg_ack (num_pkt_bytes_stored_reg_ack),
.num_pkt_bytes_stored_reg_wr (num_pkt_bytes_stored_reg_wr),
.num_pkt_bytes_stored_reg_wr_data (num_pkt_bytes_stored_reg_wr_data),
.num_pkt_bytes_stored_reg_rd_data (num_pkt_bytes_stored_reg_rd_data),
.num_overhead_bytes_stored_reg_req (num_overhead_bytes_stored_reg_req),
.num_overhead_bytes_stored_reg_ack (num_overhead_bytes_stored_reg_ack),
.num_overhead_bytes_stored_reg_wr (num_overhead_bytes_stored_reg_wr),
.num_overhead_bytes_stored_reg_wr_data(num_overhead_bytes_stored_reg_wr_data),
.num_overhead_bytes_stored_reg_rd_data(num_overhead_bytes_stored_reg_rd_data),
.num_pkts_stored_reg_req (num_pkts_stored_reg_req),
.num_pkts_stored_reg_ack (num_pkts_stored_reg_ack),
.num_pkts_stored_reg_wr (num_pkts_stored_reg_wr),
.num_pkts_stored_reg_wr_data (num_pkts_stored_reg_wr_data),
.num_pkts_stored_reg_rd_data (num_pkts_stored_reg_rd_data),
.num_pkts_dropped_reg_req (num_pkts_dropped_reg_req),
.num_pkts_dropped_reg_ack (num_pkts_dropped_reg_ack),
.num_pkts_dropped_reg_wr (num_pkts_dropped_reg_wr),
.num_pkts_dropped_reg_wr_data (num_pkts_dropped_reg_wr_data),
.num_pkts_dropped_reg_rd_data (num_pkts_dropped_reg_rd_data),
.num_pkt_bytes_removed_reg_req (num_pkt_bytes_removed_reg_req),
.num_pkt_bytes_removed_reg_ack (num_pkt_bytes_removed_reg_ack),
.num_pkt_bytes_removed_reg_wr (num_pkt_bytes_removed_reg_wr),
.num_pkt_bytes_removed_reg_wr_data (num_pkt_bytes_removed_reg_wr_data),
.num_pkt_bytes_removed_reg_rd_data (num_pkt_bytes_removed_reg_rd_data),
.num_overhead_bytes_removed_reg_req (num_overhead_bytes_removed_reg_req),
.num_overhead_bytes_removed_reg_ack (num_overhead_bytes_removed_reg_ack),
.num_overhead_bytes_removed_reg_wr (num_overhead_bytes_removed_reg_wr),
.num_overhead_bytes_removed_reg_wr_data(num_overhead_bytes_removed_reg_wr_data),
.num_overhead_bytes_removed_reg_rd_data(num_overhead_bytes_removed_reg_rd_data),
.num_pkts_removed_reg_req (num_pkts_removed_reg_req),
.num_pkts_removed_reg_ack (num_pkts_removed_reg_ack),
.num_pkts_removed_reg_wr (num_pkts_removed_reg_wr),
.num_pkts_removed_reg_wr_data (num_pkts_removed_reg_wr_data),
.num_pkts_removed_reg_rd_data (num_pkts_removed_reg_rd_data),
.oq_addr_hi_reg_req (oq_addr_hi_reg_req),
.oq_addr_hi_reg_ack (oq_addr_hi_reg_ack),
.oq_addr_hi_reg_wr (oq_addr_hi_reg_wr),
.oq_addr_hi_reg_wr_data (oq_addr_hi_reg_wr_data),
.oq_addr_hi_reg_rd_data (oq_addr_hi_reg_rd_data),
.oq_addr_lo_reg_req (oq_addr_lo_reg_req),
.oq_addr_lo_reg_ack (oq_addr_lo_reg_ack),
.oq_addr_lo_reg_wr (oq_addr_lo_reg_wr),
.oq_addr_lo_reg_wr_data (oq_addr_lo_reg_wr_data),
.oq_addr_lo_reg_rd_data (oq_addr_lo_reg_rd_data),
.oq_wr_addr_reg_req (oq_wr_addr_reg_req),
.oq_wr_addr_reg_ack (oq_wr_addr_reg_ack),
.oq_wr_addr_reg_wr (oq_wr_addr_reg_wr),
.oq_wr_addr_reg_wr_data (oq_wr_addr_reg_wr_data),
.oq_wr_addr_reg_rd_data (oq_wr_addr_reg_rd_data),
.oq_rd_addr_reg_req (oq_rd_addr_reg_req),
.oq_rd_addr_reg_ack (oq_rd_addr_reg_ack),
.oq_rd_addr_reg_wr (oq_rd_addr_reg_wr),
.oq_rd_addr_reg_wr_data (oq_rd_addr_reg_wr_data),
.oq_rd_addr_reg_rd_data (oq_rd_addr_reg_rd_data),
.max_pkts_in_q_reg_req (max_pkts_in_q_reg_req),
.max_pkts_in_q_reg_ack (max_pkts_in_q_reg_ack),
.max_pkts_in_q_reg_wr (max_pkts_in_q_reg_wr),
.max_pkts_in_q_reg_wr_data (max_pkts_in_q_reg_wr_data),
.max_pkts_in_q_reg_rd_data (max_pkts_in_q_reg_rd_data),
.num_pkts_in_q_reg_req (num_pkts_in_q_reg_req),
.num_pkts_in_q_reg_ack (num_pkts_in_q_reg_ack),
.num_pkts_in_q_reg_wr (num_pkts_in_q_reg_wr),
.num_pkts_in_q_reg_wr_data (num_pkts_in_q_reg_wr_data),
.num_pkts_in_q_reg_rd_data (num_pkts_in_q_reg_rd_data),
.num_words_left_reg_req (num_words_left_reg_req),
.num_words_left_reg_ack (num_words_left_reg_ack),
.num_words_left_reg_wr (num_words_left_reg_wr),
.num_words_left_reg_wr_data (num_words_left_reg_wr_data),
.num_words_left_reg_rd_data (num_words_left_reg_rd_data),
.num_words_in_q_reg_req (num_words_in_q_reg_req),
.num_words_in_q_reg_ack (num_words_in_q_reg_ack),
.num_words_in_q_reg_wr (num_words_in_q_reg_wr),
.num_words_in_q_reg_wr_data (num_words_in_q_reg_wr_data),
.num_words_in_q_reg_rd_data (num_words_in_q_reg_rd_data),
.oq_full_thresh_reg_req (oq_full_thresh_reg_req),
.oq_full_thresh_reg_ack (oq_full_thresh_reg_ack),
.oq_full_thresh_reg_wr (oq_full_thresh_reg_wr),
.oq_full_thresh_reg_wr_data (oq_full_thresh_reg_wr_data),
.oq_full_thresh_reg_rd_data (oq_full_thresh_reg_rd_data),
// Values used to calculate full/emtpy state
.max_pkts_in_q_dst (max_pkts_in_q_dst),
.num_pkts_in_q_dst (num_pkts_in_q_dst),
.num_pkts_in_q_dst_wr_done (num_pkts_in_q_dst_wr_done),
.max_pkts_in_q_src (max_pkts_in_q_src),
.num_pkts_in_q_src (num_pkts_in_q_src),
.num_pkts_in_q_src_wr_done (num_pkts_in_q_src_wr_done),
.oq_full_thresh_dst (oq_full_thresh_dst),
.num_words_left_dst (num_words_left_dst),
.num_words_left_dst_wr_done (num_words_left_dst_wr_done),
.oq_full_thresh_src (oq_full_thresh_src),
.num_words_left_src (num_words_left_src),
.num_words_left_src_wr_done (num_words_left_src_wr_done),
// --- Misc
.clk (clk),
.reset (reset)
);
endmodule // oq_regs
|
`include "project_include.v"
module master(
input clk,
input rst,
output reg o_master_ready, //Goes high until enough data for an
//entire command is read.
// For Ping, this is just the command
// For Read, just the command
// For Config, (Read) just the command
// For Config, (Write) command + the
// amount of data to read from host
// For Write, command + the amount of
// data to read from the host
//Master Interface
input [7:0] i_command,
input [7:0] i_flag,
input [31:0] i_rw_count,
input [31:0] i_address,
input i_command_rdy_stb,
output reg [7:0] o_status,
output [7:0] o_status_flags,
output reg [31:0] o_read_size,
output reg o_status_rdy_stb,
output reg [31:0] o_address, //Calculated end address, this can be
//used to verify that the mem was
//calculated correctly
//Write side FIFO interface
input i_wpath_ready,
output reg o_wpath_activate,
input [23:0] i_wpath_packet_size,
input [31:0] i_wpath_data,
output reg o_wpath_strobe,
//Read side FIFO interface
input [1:0] i_rpath_ready,
output reg [1:0] o_rpath_activate,
input [23:0] i_rpath_size,
output reg [31:0] o_rpath_data,
output reg o_rpath_strobe
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PING = 4'h1;
localparam WRITE = 4'h2;
localparam READ = 4'h3;
localparam CONFIG = 4'h4;
//Registers/Wires
reg [3:0] state;
reg [3:0] next_state;
reg [23:0] r_wdata_count;
reg [23:0] r_rdata_count;
reg [31:0] r_write_count;
reg [31:0] r_read_count;
reg [23:0] r_status_index;
reg r_status_strobe;
reg r_process_command;
reg [31:0] r_status;
wire [7:0] w_status_flags;
wire w_error; //Indicate that some error occured
wire w_error_bus_timeout; //Timeout with axi bus
wire w_error_comm_timeout; //Timeout with communication
wire w_interrupt;
reg r_send_status;
reg r_status_sent;
wire w_status_send_finished;
reg [23:0] r_rpath_fifo_count;
wire w_out_path_ready;
//Trigger Declaration
reg r_trig_send_status;
reg r_trig_send_finished;
//Submodules
//Asynchronous Logic
//assign o_master_ready = (state == IDLE);
assign w_out_path_ready = ((o_rpath_activate > 0) && (r_rpath_fifo_count < i_rpath_size));
assign w_status_send_finished = (!r_send_status && !r_status_sent);
assign w_error_bus_timeout = 0;
assign w_error_comm_timeout= 0;
assign w_error = (w_error_bus_timeout ||
w_error_comm_timeout);
assign w_interrupt = 0;
assign o_status_flags = 8'h0;
//Triggers
//Send Status Trigger
always @ (posedge clk) begin
if (rst) begin
r_trig_send_status <= 0;
r_trig_send_finished <= 0;
o_master_ready <= 0;
end
else begin
r_trig_send_status <= 0;
o_master_ready <= 0;
case (state)
IDLE: begin
r_trig_send_finished <= 0;
o_master_ready <= 1;
end
PING: begin
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
WRITE: begin
o_master_ready <= 1;
if (r_write_count >= i_rw_count) begin
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
end
READ: begin
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
CONFIG: begin
if (i_rw_count > 0) begin
o_master_ready <= 1;
end
if (!r_trig_send_finished) begin
r_trig_send_status <= 1;
end
r_trig_send_finished <= 1;
end
endcase
end
end
always @ (*) begin
if (rst) begin
r_status = 0;
end
else begin
if (w_error) begin
//Error Occured :(
r_status = {`IDENTIFICATION_ERR,
o_status_flags,
~i_command};
end
else if (w_interrupt) begin
//Send OH HI!
r_status = {`IDENTIFICATION_INT,
o_status_flags,
`INTERRUPT_STATUS};
end
else begin
//Normal Response
//Check if there is an error condition here
r_status = {`IDENTIFICATION_RESP,
o_status_flags,
~i_command};
end
end
end
//strobe (i_command_rdy_stb) to enable (r_process_command)
always @ (*) begin
if (rst) begin
r_process_command = 0;
end
else begin
if (i_command_rdy_stb && (state == IDLE)) begin
r_process_command = 1;
end
else if (state != IDLE) begin
r_process_command = 0;
end
else begin
r_process_command = r_process_command;
end
end
end
//State Machine
always @ (*) begin
if (rst) begin
next_state = IDLE;
end
else begin
next_state = state;
case (state)
IDLE: begin
if (r_process_command) begin
case (i_command)
`PING_COMMAND: begin
next_state = PING;
end
`WRITE_COMMAND: begin
next_state = WRITE;
end
`READ_COMMAND: begin
$display ("Detected Read Request");
next_state = READ;
end
`CONFIG_COMMAND: begin
next_state = CONFIG;
end
endcase
end
else begin
next_state = IDLE;
end
end
PING: begin
//Just Send a response
if (!r_trig_send_finished) begin
next_state = IDLE;
end
else begin
next_state = PING;
end
end
WRITE: begin
//Data comes in from the host and writes to the FPGA
if (!r_trig_send_finished && (r_write_count >= i_rw_count)) begin
next_state = IDLE;
end
else begin
next_state = WRITE;
end
end
READ: begin
//Read Data from the i_address
if (r_read_count >= o_read_size) begin
next_state = IDLE;
end
else begin
next_state = READ;
end
end
CONFIG: begin
//Write and read configuration data
if (r_write_count >= i_rw_count) begin
next_state = IDLE;
end
end
endcase
end
end
//Synchronous Logic
//Synchronize state
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
end
else begin
state <= next_state;
end
end
//Set up the out read size and the out address
always @ (posedge clk) begin
if (rst) begin
o_read_size <= 0;
o_address <= 0;
end
else begin
if (i_command_rdy_stb) begin
case (i_command)
`PING_COMMAND: begin
o_read_size <= 0;
o_address <= i_address;
end
`WRITE_COMMAND: begin
o_read_size <= 0;
o_address <= i_address;
end
`READ_COMMAND: begin
o_read_size <= i_rw_count;
o_address <= i_address;
end
`CONFIG_COMMAND: begin
o_read_size <= `CONFIG_LENGTH;
o_address <= i_address;
end
endcase
end
end
end
//Input Path (All incomming data goes through here)
always @ (posedge clk) begin
if (rst) begin
o_wpath_activate <= 0;
o_wpath_strobe <= 0;
r_wdata_count <= 0; //Count for packet
r_write_count <= 0; //Count for the total data (independent of packet size)
end
else begin
o_wpath_strobe <= 0;
//Write Path (Incomming)
if (i_wpath_ready && !o_wpath_activate) begin
r_wdata_count <= 0;
o_wpath_activate <= 1;
end
else if (o_wpath_activate) begin
if (r_wdata_count >= i_wpath_packet_size) begin
o_wpath_activate <= 0;
end
end
if (o_wpath_strobe) begin
r_write_count <= r_write_count + 1;
end
if (state == WRITE) begin
if ((o_wpath_activate > 0) && (r_wdata_count < i_wpath_packet_size)) begin
o_wpath_strobe <= 1;
r_wdata_count <= r_wdata_count + 1;
end
//for now just suck all the data out of the incomming ping pong FIFO
//whenever it's available. In the future this will interface with the
//Axi Out Path
end
else if (state == IDLE) begin
r_write_count <= 0;
end
end
end
//Output Path (All outgoing data goes through here)
always @ (posedge clk) begin
if (rst) begin
o_status <= 0;
o_status_rdy_stb <= 0;
r_status_index <= 0;
r_status_strobe <= 0;
r_send_status <= 0;
r_status_sent <= 0;
o_rpath_activate <= 0;
o_rpath_data <= 0;
o_rpath_strobe <= 0;
r_rpath_fifo_count <= 0;
end
else begin
//Strobe
o_rpath_strobe <= 0;
o_status_rdy_stb <= 0;
r_status_strobe <= 0;
//Ping Pong FIFO Read Path (Outgoing)
if ((i_rpath_ready > 0) && (o_rpath_activate == 0)) begin
r_rpath_fifo_count <= 0;
if (i_rpath_ready[0]) begin
o_rpath_activate[0] <= 1;
end
else begin
o_rpath_activate[1] <= 1;
end
end
// else if (o_rpath_activate > 0)begin
// if (r_rpath_fifo_count < i_rpath_size) begin
// if (o_rpath_strobe) begin
// r_rpath_fifo_count <= r_rpath_fifo_count + 1;
// end
// end
// else begin
// o_rpath_activate <= 0;
// end
// end
//Take care of the send status trigger setup so we don't send multiple
//status packets
if (r_trig_send_status) begin
r_send_status <= 1;
end
else if (r_status_sent) begin
r_send_status <= 0;
r_status_sent <= 0;
end
//Conditions to disable the current Ping Pong FIFO
if ((state == IDLE) && (r_rpath_fifo_count > 0) && !o_rpath_strobe) begin
//Condition to flush the FIFO
o_rpath_activate <= 0;
end
//Condition to reset the read count
if (state == IDLE) begin
r_read_count <= 0;
r_status_index <= 0;
end
//Send Status
if (o_rpath_activate && r_send_status) begin
case (r_status_index)
`STATUS_DATA_0: begin
o_status <= r_status;
o_rpath_data <= r_status;
r_status_index <= r_status_index + 1;
o_rpath_strobe <= 1;
r_rpath_fifo_count <= r_rpath_fifo_count + 1;
end
`STATUS_DATA_1: begin
o_rpath_data <= o_read_size;
r_status_index <= r_status_index + 1;
o_rpath_strobe <= 1;
r_rpath_fifo_count <= r_rpath_fifo_count + 1;
end
`STATUS_DATA_2: begin
o_rpath_data <= o_address;
o_status_rdy_stb <= 1;
o_rpath_strobe <= 1;
r_status_index <= r_status_index + 1;
r_rpath_fifo_count <= r_rpath_fifo_count + 1;
if (i_command != `READ_COMMAND) begin
r_status_sent <= 1;
end
end
default: begin
if (r_read_count < o_read_size ) begin
if (o_rpath_activate > 0) begin
if (r_rpath_fifo_count < i_rpath_size) begin
o_rpath_strobe <= 1;
o_rpath_data <= r_read_count;
r_read_count <= r_read_count + 1;
r_rpath_fifo_count<= r_rpath_fifo_count + 1;
end
else begin
o_rpath_activate <= 0;
end
end
end
else begin
r_status_sent <= 1;
end
end
endcase
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_TB_V
`define SKY130_FD_SC_MS__O22AI_TB_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_PP_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:12:07 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_sim_netlist.v
// Design : zqynq_lab_1_design_auto_pc_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
s_axi_awvalid,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input s_axi_awvalid;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [11:4]C;
wire [22:0]Q;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_50 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_2 ;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_150;
wire SI_REG_n_151;
wire SI_REG_n_158;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_171;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_183;
wire SI_REG_n_184;
wire SI_REG_n_185;
wire SI_REG_n_186;
wire SI_REG_n_187;
wire SI_REG_n_188;
wire SI_REG_n_189;
wire SI_REG_n_190;
wire SI_REG_n_191;
wire SI_REG_n_192;
wire SI_REG_n_193;
wire SI_REG_n_194;
wire SI_REG_n_195;
wire SI_REG_n_196;
wire SI_REG_n_20;
wire SI_REG_n_21;
wire SI_REG_n_22;
wire SI_REG_n_23;
wire SI_REG_n_29;
wire SI_REG_n_79;
wire SI_REG_n_80;
wire SI_REG_n_81;
wire SI_REG_n_82;
wire SI_REG_n_88;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_54 ;
wire \WR.aw_channel_0_n_55 ;
wire \WR.aw_channel_0_n_56 ;
wire \WR.aw_channel_0_n_57 ;
wire \WR.aw_channel_0_n_7 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire [1:0]\ar_cmd_fsm_0/state ;
wire \ar_pipe/p_1_in ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire \aw_pipe/p_1_in ;
wire [11:0]b_awid;
wire [7:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
wire \cmd_translator_0/incr_cmd_0/sel_first ;
wire \cmd_translator_0/incr_cmd_0/sel_first_4 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel \RD.ar_channel_0
(.CO(SI_REG_n_147),
.D({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.E(\ar_pipe/p_1_in ),
.O({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.Q(\ar_cmd_fsm_0/state ),
.S({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_0 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_10 ),
.\m_payload_i_reg[11] ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\m_payload_i_reg[38] (SI_REG_n_196),
.\m_payload_i_reg[3] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\m_payload_i_reg[44] (SI_REG_n_171),
.\m_payload_i_reg[46] (SI_REG_n_177),
.\m_payload_i_reg[47] (SI_REG_n_175),
.\m_payload_i_reg[51] (SI_REG_n_176),
.\m_payload_i_reg[64] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,si_rs_araddr}),
.\m_payload_i_reg[6] (SI_REG_n_187),
.\m_payload_i_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_11 ),
.r_rlast(r_rlast),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_8 ),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_2 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_178),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_11 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice SI_REG
(.CO(SI_REG_n_134),
.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr_reg(\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_incr_reg[11] (C),
.\axaddr_incr_reg[11]_0 ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\axaddr_incr_reg[3] ({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.\axaddr_incr_reg[3]_0 (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_incr_reg[7] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\axaddr_incr_reg[7]_0 (SI_REG_n_147),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (SI_REG_n_179),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_187),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.\axaddr_offset_r_reg[3]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_4 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_162),
.\axlen_cnt_reg[3]_0 (SI_REG_n_175),
.b_push(b_push),
.\cnt_read_reg[3]_rep__0 (SI_REG_n_178),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_2 ),
.\m_axi_araddr[10] (SI_REG_n_196),
.\m_axi_awaddr[10] (SI_REG_n_195),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.m_valid_i_reg(\ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_163),
.next_pending_r_reg_0(SI_REG_n_164),
.next_pending_r_reg_1(SI_REG_n_176),
.next_pending_r_reg_2(SI_REG_n_177),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.sel_first_2(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_10 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\ar_cmd_fsm_0/state ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_7 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_8 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\wrap_cnt_r_reg[3] (SI_REG_n_158),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_171),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.wrap_second_len_1(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_2 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel \WR.aw_channel_0
(.CO(SI_REG_n_134),
.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[11] (C),
.\m_payload_i_reg[35] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.\m_payload_i_reg[38] (SI_REG_n_195),
.\m_payload_i_reg[44] (SI_REG_n_158),
.\m_payload_i_reg[46] (SI_REG_n_164),
.\m_payload_i_reg[47] (SI_REG_n_162),
.\m_payload_i_reg[48] (SI_REG_n_163),
.\m_payload_i_reg[64] ({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] (SI_REG_n_179),
.\m_payload_i_reg[6]_0 ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_7 ),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],wrap_cnt[0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
wrap_second_len,
\wrap_boundary_axaddr_r_reg[11] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
r_push_r_reg,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
m_axi_arvalid,
r_rlast,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_arvalid,
\m_payload_i_reg[44] ,
\m_payload_i_reg[64] ,
m_axi_arready,
CO,
\cnt_read_reg[2]_rep__0 ,
axaddr_offset,
\m_payload_i_reg[46] ,
\m_payload_i_reg[51] ,
areset_d1,
\m_payload_i_reg[6] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output [0:0]wrap_second_len;
output \wrap_boundary_axaddr_r_reg[11] ;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output r_push_r_reg;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output m_axi_arvalid;
output r_rlast;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_arvalid;
input \m_payload_i_reg[44] ;
input [35:0]\m_payload_i_reg[64] ;
input m_axi_arready;
input [0:0]CO;
input \cnt_read_reg[2]_rep__0 ;
input [2:0]axaddr_offset;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[51] ;
input areset_d1;
input \m_payload_i_reg[6] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]D;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_12;
wire ar_cmd_fsm_0_n_15;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_20;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [3:0]\axaddr_incr_reg[3] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_8;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire sel_first;
wire sel_first_i;
wire si_rs_arvalid;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_17),
.axaddr_offset(axaddr_offset),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[11] (ar_cmd_fsm_0_n_16),
.\axlen_cnt_reg[1] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[1]_0 ({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.\axlen_cnt_reg[1]_1 ({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.\axlen_cnt_reg[4] (cmd_translator_0_n_11),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[64] [19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[51] (\m_payload_i_reg[51] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_12),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_15),
.s_axburst_eq1_reg_0(cmd_translator_0_n_13),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_20),
.sel_first_reg_0(ar_cmd_fsm_0_n_21),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.sel_first_reg_3(cmd_translator_0_n_8),
.si_rs_arvalid(si_rs_arvalid),
.wrap_next_pending(wrap_next_pending),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[1] (\wrap_cmd_0/wrap_second_len_r ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 cmd_translator_0
(.CO(CO),
.D({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,axaddr_offset}),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_12),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_15),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] (\m_payload_i_reg[64] [23:0]),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(ar_cmd_fsm_0_n_16),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_11),
.r_rlast(r_rlast),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_8),
.sel_first_reg_2(ar_cmd_fsm_0_n_17),
.sel_first_reg_3(ar_cmd_fsm_0_n_20),
.sel_first_reg_4(ar_cmd_fsm_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0] (ar_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_13),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0] ),
.\state_reg[1] (Q),
.\state_reg[1]_rep (\m_payload_i_reg[0]_0 ),
.\state_reg[1]_rep_0 (r_push_r_reg),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({D[2:1],wrap_second_len,D[0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 [2:1],ar_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_0 [0]}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
\wrap_boundary_axaddr_r_reg[11] ,
D,
\state_reg[1]_rep ,
\state_reg[1]_rep_0 ,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
b_push,
\axaddr_offset_r_reg[3]_0 ,
E,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_awvalid,
\m_payload_i_reg[64] ,
\m_payload_i_reg[44] ,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
CO,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[46] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[11] ;
output [0:0]D;
output \state_reg[1]_rep ;
output \state_reg[1]_rep_0 ;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output b_push;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [0:0]E;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [19:0]in;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_awvalid;
input [35:0]\m_payload_i_reg[64] ;
input \m_payload_i_reg[44] ;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [0:0]CO;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[6] ;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_13;
wire aw_cmd_fsm_0_n_17;
wire aw_cmd_fsm_0_n_20;
wire aw_cmd_fsm_0_n_21;
wire aw_cmd_fsm_0_n_24;
wire aw_cmd_fsm_0_n_25;
wire aw_cmd_fsm_0_n_3;
wire [3:0]\axaddr_incr_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_14;
wire cmd_translator_0_n_15;
wire cmd_translator_0_n_16;
wire cmd_translator_0_n_17;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire [7:0]\m_payload_i_reg[11] ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire next;
wire [5:0]p_1_in;
wire sel_first;
wire sel_first__0;
wire sel_first_i;
wire si_rs_awvalid;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(aw_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_21),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_20),
.\axlen_cnt_reg[2] (cmd_translator_0_n_16),
.\axlen_cnt_reg[3] (cmd_translator_0_n_15),
.\axlen_cnt_reg[3]_0 (cmd_translator_0_n_17),
.\axlen_cnt_reg[4] (aw_cmd_fsm_0_n_0),
.\axlen_cnt_reg[4]_0 (cmd_translator_0_n_13),
.\axlen_cnt_reg[5] ({p_1_in[5:4],p_1_in[1:0]}),
.\axlen_cnt_reg[5]_0 ({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1 (\cnt_read_reg[1]_rep__1 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (b_push),
.\m_payload_i_reg[0]_0 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[49] ({\m_payload_i_reg[64] [21:19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_13),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_17),
.s_axburst_eq1_reg_0(cmd_translator_0_n_14),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_24),
.sel_first_reg_0(aw_cmd_fsm_0_n_25),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep_0 (\state_reg[1]_rep ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[1] (D),
.\wrap_second_len_r_reg[1]_0 (\wrap_cmd_0/wrap_second_len_r ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator cmd_translator_0
(.CO(CO),
.D({p_1_in[5:4],p_1_in[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,\m_payload_i_reg[35] }),
.\axlen_cnt_reg[4] (cmd_translator_0_n_17),
.\axlen_cnt_reg[7] (cmd_translator_0_n_13),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_13),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_17),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[64] [23:22],\m_payload_i_reg[64] [19:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(aw_cmd_fsm_0_n_20),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_15),
.next_pending_r_reg_2(cmd_translator_0_n_16),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_21),
.sel_first_reg_2(aw_cmd_fsm_0_n_24),
.sel_first_reg_3(aw_cmd_fsm_0_n_25),
.\state_reg[0] (aw_cmd_fsm_0_n_0),
.\state_reg[0]_rep (b_push),
.\state_reg[1] (Q),
.\state_reg[1]_rep (cmd_translator_0_n_14),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_second_len_r_reg[3]_0 [2:1],D,\wrap_second_len_r_reg[3]_0 [0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_1 [2:1],aw_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_1 [0]}));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(in[18]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(in[19]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(in[16]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(in[17]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [19]),
.Q(in[3]),
.R(1'b0));
FDRE \s_awlen_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awlen_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awlen_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awlen_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [23]),
.Q(in[7]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__1 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__1 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [19:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_2;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_6;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bvalid_i_reg(bid_fifo_0_n_6),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_0 (bid_fifo_0_n_3),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1_0 (\cnt_read_reg[1]_rep__1 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.\bresp_cnt_reg[3] (bid_fifo_0_n_3),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_6),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first__0,
Q,
\axlen_cnt_reg[7] ,
\state_reg[1]_rep ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\axlen_cnt_reg[4] ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
O,
sel_first_reg_2,
sel_first_reg_3,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
CO,
D,
next,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first__0;
output [3:0]Q;
output \axlen_cnt_reg[7] ;
output \state_reg[1]_rep ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \axlen_cnt_reg[4] ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input [3:0]O;
input sel_first_reg_2;
input sel_first_reg_3;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [21:0]\m_payload_i_reg[51] ;
input [0:0]CO;
input [3:0]D;
input next;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[7] ;
wire incr_cmd_0_n_21;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [21:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[4]_0 (\axlen_cnt_reg[4] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[1] (incr_cmd_0_n_21),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [21:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_2),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd wrap_cmd_0
(.E(E),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3:2],\axaddr_incr_reg[3] [0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_2),
.sel_first_reg_0(sel_first__0),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_21),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first_reg_1,
Q,
next_pending_r_reg_0,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
O,
sel_first_reg_3,
sel_first_reg_4,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\state_reg[0]_rep_0 ,
si_rs_arvalid,
\state_reg[1]_rep ,
CO,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
D,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first_reg_1;
output [1:0]Q;
output next_pending_r_reg_0;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input [3:0]O;
input sel_first_reg_3;
input sel_first_reg_4;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [23:0]\m_payload_i_reg[51] ;
input \state_reg[0]_rep_0 ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input [0:0]CO;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_17;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [23:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11]_0 ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[11]_1 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[2] (incr_cmd_0_n_17),
.\m_axi_araddr[5] (incr_cmd_0_n_16),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [23:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [5],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_0),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_3),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3],\axaddr_incr_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_4),
.sel_first_reg_2(incr_cmd_0_n_16),
.sel_first_reg_3(incr_cmd_0_n_17),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
Q,
\axlen_cnt_reg[7]_0 ,
next_pending_r_reg_1,
\axlen_cnt_reg[4]_0 ,
\m_axi_awaddr[1] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output [3:0]Q;
output \axlen_cnt_reg[7]_0 ;
output next_pending_r_reg_1;
output \axlen_cnt_reg[4]_0 ;
output \m_axi_awaddr[1] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [9:0]\m_payload_i_reg[51] ;
input [7:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2_n_0 ;
wire \axaddr_incr[4]_i_3_n_0 ;
wire \axaddr_incr[4]_i_4_n_0 ;
wire \axaddr_incr[4]_i_5_n_0 ;
wire \axaddr_incr[8]_i_2_n_0 ;
wire \axaddr_incr[8]_i_3_n_0 ;
wire \axaddr_incr[8]_i_4_n_0 ;
wire \axaddr_incr[8]_i_5_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1_n_0 ;
wire \axaddr_incr_reg[4]_i_1_n_1 ;
wire \axaddr_incr_reg[4]_i_1_n_2 ;
wire \axaddr_incr_reg[4]_i_1_n_3 ;
wire \axaddr_incr_reg[4]_i_1_n_4 ;
wire \axaddr_incr_reg[4]_i_1_n_5 ;
wire \axaddr_incr_reg[4]_i_1_n_6 ;
wire \axaddr_incr_reg[4]_i_1_n_7 ;
wire \axaddr_incr_reg[8]_i_1_n_1 ;
wire \axaddr_incr_reg[8]_i_1_n_2 ;
wire \axaddr_incr_reg[8]_i_1_n_3 ;
wire \axaddr_incr_reg[8]_i_1_n_4 ;
wire \axaddr_incr_reg[8]_i_1_n_5 ;
wire \axaddr_incr_reg[8]_i_1_n_6 ;
wire \axaddr_incr_reg[8]_i_1_n_7 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt[7]_i_4_n_0 ;
wire \axlen_cnt_reg[4]_0 ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[1] ;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[47] ;
wire [9:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire [7:2]p_1_in;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'h559AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[3]));
LUT6 #(
.INIT(64'h0000AAAA559AAAAA))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[2]));
LUT6 #(
.INIT(64'h00000000559AAAAA))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [4]),
.I5(\m_payload_i_reg[51] [5]),
.O(S[1]));
LUT6 #(
.INIT(64'h000000000000559A))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2
(.I0(\m_payload_i_reg[11] [7]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3
(.I0(\m_payload_i_reg[11] [6]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4
(.I0(\m_payload_i_reg[11] [5]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5
(.I0(\m_payload_i_reg[11] [4]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1_n_0 ,\axaddr_incr_reg[4]_i_1_n_1 ,\axaddr_incr_reg[4]_i_1_n_2 ,\axaddr_incr_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1_n_4 ,\axaddr_incr_reg[4]_i_1_n_5 ,\axaddr_incr_reg[4]_i_1_n_6 ,\axaddr_incr_reg[4]_i_1_n_7 }),
.S({\axaddr_incr[4]_i_2_n_0 ,\axaddr_incr[4]_i_3_n_0 ,\axaddr_incr[4]_i_4_n_0 ,\axaddr_incr[4]_i_5_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1
(.CI(\axaddr_incr_reg[4]_i_1_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1_n_1 ,\axaddr_incr_reg[8]_i_1_n_2 ,\axaddr_incr_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1_n_4 ,\axaddr_incr_reg[8]_i_1_n_5 ,\axaddr_incr_reg[8]_i_1_n_6 ,\axaddr_incr_reg[8]_i_1_n_7 }),
.S({\axaddr_incr[8]_i_2_n_0 ,\axaddr_incr[8]_i_3_n_0 ,\axaddr_incr[8]_i_4_n_0 ,\axaddr_incr[8]_i_5_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(p_1_in[2]));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt_reg[4]_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(Q[3]),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [8]),
.O(p_1_in[6]));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(\axlen_cnt[7]_i_4_n_0 ),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [9]),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[7]_i_3
(.I0(Q[2]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt_reg[7]_0 ));
LUT2 #(
.INIT(4'hE))
\axlen_cnt[7]_i_4
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(Q[3]),
.O(\axlen_cnt[7]_i_4_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[2]),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[6]),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[7]),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(\axaddr_incr_reg[3]_0 [1]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\m_payload_i_reg[51] [1]),
.O(\m_axi_awaddr[1] ));
LUT6 #(
.INIT(64'h0000000000000001))
next_pending_r_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(Q[2]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(Q[1]),
.I5(\axlen_cnt[7]_i_4_n_0 ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[11]_1 ,
Q,
next_pending_r_reg_1,
\m_axi_araddr[5] ,
\m_axi_araddr[2] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [6:0]\axaddr_incr_reg[11]_0 ;
output \axaddr_incr_reg[11]_1 ;
output [1:0]Q;
output next_pending_r_reg_1;
output \m_axi_araddr[5] ;
output \m_axi_araddr[2] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [12:0]\m_payload_i_reg[51] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2__0_n_0 ;
wire \axaddr_incr[4]_i_3__0_n_0 ;
wire \axaddr_incr[4]_i_4__0_n_0 ;
wire \axaddr_incr[4]_i_5__0_n_0 ;
wire \axaddr_incr[8]_i_2__0_n_0 ;
wire \axaddr_incr[8]_i_3__0_n_0 ;
wire \axaddr_incr[8]_i_4__0_n_0 ;
wire \axaddr_incr[8]_i_5__0_n_0 ;
wire [5:5]axaddr_incr_reg;
wire [6:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_1 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_1 ;
wire \axaddr_incr_reg[4]_i_1__0_n_2 ;
wire \axaddr_incr_reg[4]_i_1__0_n_3 ;
wire \axaddr_incr_reg[4]_i_1__0_n_4 ;
wire \axaddr_incr_reg[4]_i_1__0_n_5 ;
wire \axaddr_incr_reg[4]_i_1__0_n_6 ;
wire \axaddr_incr_reg[4]_i_1__0_n_7 ;
wire \axaddr_incr_reg[8]_i_1__0_n_1 ;
wire \axaddr_incr_reg[8]_i_1__0_n_2 ;
wire \axaddr_incr_reg[8]_i_1__0_n_3 ;
wire \axaddr_incr_reg[8]_i_1__0_n_4 ;
wire \axaddr_incr_reg[8]_i_1__0_n_5 ;
wire \axaddr_incr_reg[8]_i_1__0_n_6 ;
wire \axaddr_incr_reg[8]_i_1__0_n_7 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_2_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire [12:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[1]));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [2]),
.O(\axaddr_incr[4]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [1]),
.O(\axaddr_incr[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(axaddr_incr_reg),
.O(\axaddr_incr[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [0]),
.O(\axaddr_incr[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2__0
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [6]),
.O(\axaddr_incr[8]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3__0
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [5]),
.O(\axaddr_incr[8]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4__0
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [4]),
.O(\axaddr_incr[8]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5__0
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [3]),
.O(\axaddr_incr[8]_i_5__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1__0
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1__0_n_0 ,\axaddr_incr_reg[4]_i_1__0_n_1 ,\axaddr_incr_reg[4]_i_1__0_n_2 ,\axaddr_incr_reg[4]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1__0_n_4 ,\axaddr_incr_reg[4]_i_1__0_n_5 ,\axaddr_incr_reg[4]_i_1__0_n_6 ,\axaddr_incr_reg[4]_i_1__0_n_7 }),
.S({\axaddr_incr[4]_i_2__0_n_0 ,\axaddr_incr[4]_i_3__0_n_0 ,\axaddr_incr[4]_i_4__0_n_0 ,\axaddr_incr[4]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_6 ),
.Q(axaddr_incr_reg),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1__0
(.CI(\axaddr_incr_reg[4]_i_1__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1__0_n_1 ,\axaddr_incr_reg[8]_i_1__0_n_2 ,\axaddr_incr_reg[8]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1__0_n_4 ,\axaddr_incr_reg[8]_i_1__0_n_5 ,\axaddr_incr_reg[8]_i_1__0_n_6 ,\axaddr_incr_reg[8]_i_1__0_n_7 }),
.S({\axaddr_incr[8]_i_2__0_n_0 ,\axaddr_incr[8]_i_3__0_n_0 ,\axaddr_incr[8]_i_4__0_n_0 ,\axaddr_incr[8]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_6 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt[4]_i_2__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [9]),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt[5]_i_2_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [10]),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[5]_i_2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [11]),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[7]_i_2__0
(.I0(E),
.I1(\m_payload_i_reg[51] [12]),
.I2(\axlen_cnt_reg_n_0_[7] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.I4(\axlen_cnt_reg_n_0_[6] ),
.I5(\state_reg[0] ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(\axaddr_incr_reg[3]_0 [2]),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(axaddr_incr_reg),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [4]),
.O(\m_axi_araddr[5] ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_3__1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(next_pending_r_i_4__0_n_0),
.O(next_pending_r_reg_1));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_4__0
(.I0(Q[1]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_1 ),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
(\state_reg[1]_rep ,
m_axi_rready,
m_valid_i_reg,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output \state_reg[1]_rep ;
output m_axi_rready;
output m_valid_i_reg;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_1;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_1),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[0]_rep__2_0 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
(\axlen_cnt_reg[1] ,
Q,
D,
wrap_second_len,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axlen_cnt_reg[1]_0 ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
\axaddr_wrap_reg[11] ,
\axaddr_incr_reg[11] ,
m_axi_arvalid,
\m_payload_i_reg[0]_1 ,
sel_first_reg,
sel_first_reg_0,
si_rs_arvalid,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[44] ,
m_axi_arready,
s_axburst_eq1_reg_0,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axlen_cnt_reg[1]_1 ,
\wrap_second_len_r_reg[1] ,
axaddr_offset,
wrap_next_pending,
\m_payload_i_reg[51] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first_reg_3,
aclk);
output \axlen_cnt_reg[1] ;
output [1:0]Q;
output [0:0]D;
output [0:0]wrap_second_len;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [1:0]\axlen_cnt_reg[1]_0 ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output [0:0]\axaddr_wrap_reg[11] ;
output \axaddr_incr_reg[11] ;
output m_axi_arvalid;
output [0:0]\m_payload_i_reg[0]_1 ;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_arvalid;
input \axlen_cnt_reg[4] ;
input \m_payload_i_reg[44] ;
input m_axi_arready;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[2]_rep__0 ;
input [3:0]\m_payload_i_reg[47] ;
input [1:0]\axlen_cnt_reg[1]_1 ;
input [0:0]\wrap_second_len_r_reg[1] ;
input [2:0]axaddr_offset;
input wrap_next_pending;
input \m_payload_i_reg[51] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first_reg_3;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire \axlen_cnt_reg[1] ;
wire [1:0]\axlen_cnt_reg[1]_0 ;
wire [1:0]\axlen_cnt_reg[1]_1 ;
wire \axlen_cnt_reg[4] ;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[44] ;
wire [3:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire \m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [0:0]\wrap_second_len_r_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[0]_i_1__0
(.I0(sel_first_reg_2),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[47] [3]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__1
(.I0(Q[1]),
.I1(si_rs_arvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[47] [1]),
.I4(\axlen_cnt_reg[1]_1 [0]),
.I5(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[47] [2]),
.I2(\axlen_cnt_reg[1]_1 [1]),
.I3(\axlen_cnt_reg[1]_1 [0]),
.I4(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[7]_i_1__0
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_wrap_reg[11] ));
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_4__0
(.I0(Q[0]),
.I1(si_rs_arvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[1] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__2
(.I0(\m_payload_i_reg[51] ),
.I1(E),
.I2(\axlen_cnt_reg[4] ),
.I3(r_push_r_reg),
.I4(next_pending_r_reg),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__0
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg_0),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg_0),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(wrap_second_len),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(axaddr_offset[2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(axaddr_offset[0]),
.I4(axaddr_offset[1]),
.I5(E),
.O(wrap_second_len));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__1_0 ,
D,
\cnt_read_reg[0]_0 ,
sel,
SR,
bvalid_i_reg,
out,
b_push,
shandshake_r,
Q,
areset_d1,
\bresp_cnt_reg[7] ,
mhandshake_r,
bvalid_i_reg_0,
si_rs_bready,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__1_0 ;
output [0:0]D;
output \cnt_read_reg[0]_0 ;
output sel;
output [0:0]SR;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input [1:0]Q;
input areset_d1;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input bvalid_i_reg_0;
input si_rs_bready;
input [19:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire [7:0]\bresp_cnt_reg[7] ;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [19:0]in;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_i_5_n_0 ;
wire \memory_reg[3][0]_srl4_i_6_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire \memory_reg[3][4]_srl4_n_0 ;
wire \memory_reg[3][5]_srl4_n_0 ;
wire \memory_reg[3][6]_srl4_n_0 ;
wire \memory_reg[3][7]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire sel;
wire shandshake_r;
wire si_rs_bready;
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT2 #(
.INIT(4'hB))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\cnt_read_reg[0]_0 ),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h002A))
bvalid_i_i_1
(.I0(bvalid_i_i_2_n_0),
.I1(bvalid_i_reg_0),
.I2(si_rs_bready),
.I3(areset_d1),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__1_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1
(.I0(\cnt_read_reg[0]_0 ),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__1_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT1 #(
.INIT(2'h1))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\cnt_read_reg[0]_0 ),
.O(sel));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFE))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I1(\memory_reg[3][0]_srl4_i_4_n_0 ),
.I2(\memory_reg[3][0]_srl4_i_5_n_0 ),
.I3(\memory_reg[3][0]_srl4_i_6_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\cnt_read_reg[0]_0 ));
LUT6 #(
.INIT(64'h22F2FFFFFFFF22F2))
\memory_reg[3][0]_srl4_i_3
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\memory_reg[3][2]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [2]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT6 #(
.INIT(64'hF222FFFFFFFFF222))
\memory_reg[3][0]_srl4_i_4
(.I0(\bresp_cnt_reg[7] [5]),
.I1(\memory_reg[3][5]_srl4_n_0 ),
.I2(\cnt_read_reg[1]_rep__1_0 ),
.I3(\cnt_read_reg[0]_rep__0_0 ),
.I4(\bresp_cnt_reg[7] [7]),
.I5(\memory_reg[3][7]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
LUT6 #(
.INIT(64'h2FF22FF2FFFF2FF2))
\memory_reg[3][0]_srl4_i_5
(.I0(\bresp_cnt_reg[7] [2]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\memory_reg[3][4]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\bresp_cnt_reg[7] [0]),
.I5(\memory_reg[3][0]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_5_n_0 ));
LUT5 #(
.INIT(32'h6F6FFF6F))
\memory_reg[3][0]_srl4_i_6
(.I0(\memory_reg[3][6]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [6]),
.I2(mhandshake_r),
.I3(\memory_reg[3][5]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [5]),
.O(\memory_reg[3][0]_srl4_i_6_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[16]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[17]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[18]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[19]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][4]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(\memory_reg[3][4]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][5]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(\memory_reg[3][5]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][6]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(\memory_reg[3][6]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][7]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(\memory_reg[3][7]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[1]));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0
(mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
\bresp_cnt_reg[3] ,
sel,
in,
aclk,
areset_d1,
D);
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input \bresp_cnt_reg[3] ;
input sel;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \bresp_cnt_reg[3] ;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(shandshake_r),
.I2(Q[0]),
.I3(\bresp_cnt_reg[3] ),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
s_ready_i_reg_0,
si_rs_rready,
\cnt_read_reg[4]_rep__0_0 ,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input s_ready_i_reg_0;
input si_rs_rready;
input \cnt_read_reg[4]_rep__0_0 ;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hA96A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(wr_en0),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[4]_rep__0_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2
(\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
m_valid_i_reg,
\skid_buffer_reg[46] ,
r_push_r,
s_ready_i_reg,
\cnt_read_reg[0]_rep__2 ,
si_rs_rready,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[0]_rep__2_0 ,
in,
aclk,
areset_d1);
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output m_valid_i_reg;
output [12:0]\skid_buffer_reg[46] ;
input r_push_r;
input s_ready_i_reg;
input \cnt_read_reg[0]_rep__2 ;
input si_rs_rready;
input wr_en0;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[0]_rep__2_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_4__0_n_0 ;
wire \cnt_read[4]_i_5__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep__2_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(s_ready_i_reg),
.I3(r_push_r),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hAA6AA9AA))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA6AAAAAA9AAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(r_push_r),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h6A666A6AAA99AAAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read[4]_i_4__0_n_0 ),
.I4(\cnt_read[4]_i_5__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h8A))
\cnt_read[4]_i_2__0
(.I0(r_push_r),
.I1(m_valid_i_reg),
.I2(si_rs_rready),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_4__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.O(\cnt_read[4]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_5__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[4]_i_5__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF80808080808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__2_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEFEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
(\axlen_cnt_reg[4] ,
Q,
D,
\wrap_second_len_r_reg[1] ,
\state_reg[1]_rep_0 ,
\state_reg[1]_rep_1 ,
\axlen_cnt_reg[5] ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
next,
\m_payload_i_reg[0] ,
\axaddr_wrap_reg[0] ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[0]_0 ,
m_axi_awvalid,
sel_first_reg,
sel_first_reg_0,
si_rs_awvalid,
\axlen_cnt_reg[3] ,
\m_payload_i_reg[44] ,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
\m_payload_i_reg[49] ,
\axlen_cnt_reg[5]_0 ,
\axlen_cnt_reg[3]_0 ,
\axlen_cnt_reg[4]_0 ,
\wrap_second_len_r_reg[1]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[2] ,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first__0,
aclk);
output \axlen_cnt_reg[4] ;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[1] ;
output \state_reg[1]_rep_0 ;
output \state_reg[1]_rep_1 ;
output [3:0]\axlen_cnt_reg[5] ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output next;
output \m_payload_i_reg[0] ;
output [0:0]\axaddr_wrap_reg[0] ;
output \axaddr_incr_reg[11] ;
output [0:0]\m_payload_i_reg[0]_0 ;
output m_axi_awvalid;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_awvalid;
input \axlen_cnt_reg[3] ;
input \m_payload_i_reg[44] ;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [5:0]\m_payload_i_reg[49] ;
input [3:0]\axlen_cnt_reg[5]_0 ;
input \axlen_cnt_reg[3]_0 ;
input \axlen_cnt_reg[4]_0 ;
input [0:0]\wrap_second_len_r_reg[1]_0 ;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input \m_payload_i_reg[46] ;
input \axlen_cnt_reg[2] ;
input next_pending_r_reg_0;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first__0;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[0] ;
wire \axlen_cnt_reg[2] ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[4]_0 ;
wire [3:0]\axlen_cnt_reg[5] ;
wire [3:0]\axlen_cnt_reg[5]_0 ;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[48] ;
wire [5:0]\m_payload_i_reg[49] ;
wire \m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [0:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[1] ;
wire [0:0]\wrap_second_len_r_reg[1]_0 ;
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hEEFE))
\axaddr_incr[0]_i_1
(.I0(sel_first_reg_2),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[49] [3]),
.I2(\state_reg[1]_rep_1 ),
.I3(si_rs_awvalid),
.I4(\state_reg[1]_rep_0 ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[49] [1]),
.I4(\axlen_cnt_reg[5]_0 [0]),
.I5(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [2]),
.I2(\axlen_cnt_reg[5]_0 [1]),
.I3(\axlen_cnt_reg[5]_0 [0]),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [1]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[4]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [4]),
.I2(\axlen_cnt_reg[5]_0 [2]),
.I3(\axlen_cnt_reg[3]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [2]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[5]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [5]),
.I2(\axlen_cnt_reg[5]_0 [3]),
.I3(\axlen_cnt_reg[4]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [3]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hCCFE))
\axlen_cnt[7]_i_1
(.I0(si_rs_awvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_wrap_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_5
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[3] ),
.O(\axlen_cnt_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(s_axburst_eq1_reg_0),
.O(\m_payload_i_reg[0] ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1
(.I0(\m_payload_i_reg[48] ),
.I1(E),
.I2(\axlen_cnt_reg[3] ),
.I3(next),
.I4(next_pending_r_reg),
.O(incr_next_pending));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(E),
.I2(\axlen_cnt_reg[2] ),
.I3(next),
.I4(next_pending_r_reg_0),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hF3F35100FFFF0000))
next_pending_r_i_4
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hCCCEFCFFCCCECCCE))
sel_first_i_1
(.I0(si_rs_awvalid),
.I1(areset_d1),
.I2(\state_reg[1]_rep_1 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[0] ),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__2
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first__0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h2F))
\state[0]_i_1
(.I0(si_rs_awvalid),
.I1(Q[0]),
.I2(\state[0]_i_2_n_0 ),
.O(next_state));
LUT6 #(
.INIT(64'hFA08FAFA0F0F0F0F))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\state_reg[1]_rep_0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(\state_reg[1]_rep_1 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\state_reg[1]_rep_0 ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[1]_rep_1 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1]_0 ),
.I1(\m_payload_i_reg[35] [2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\m_payload_i_reg[35] [0]),
.I4(\m_payload_i_reg[35] [1]),
.I5(E),
.O(\wrap_second_len_r_reg[1] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
next,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input next;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[11]_i_5_n_0 ;
wire \axaddr_wrap[11]_i_6_n_0 ;
wire \axaddr_wrap[11]_i_7_n_0 ;
wire \axaddr_wrap[11]_i_8_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_3_n_0 ;
wire \axaddr_wrap[7]_i_4_n_0 ;
wire \axaddr_wrap[7]_i_5_n_0 ;
wire \axaddr_wrap[7]_i_6_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__0_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(wrap_cnt_r[2]),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(wrap_cnt_r[1]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5
(.I0(axaddr_wrap[11]),
.O(\axaddr_wrap[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6
(.I0(axaddr_wrap[10]),
.O(\axaddr_wrap[11]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7
(.I0(axaddr_wrap[9]),
.O(\axaddr_wrap[11]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8
(.I0(axaddr_wrap[8]),
.O(\axaddr_wrap[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3
(.I0(axaddr_wrap[7]),
.O(\axaddr_wrap[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4
(.I0(axaddr_wrap[6]),
.O(\axaddr_wrap[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5
(.I0(axaddr_wrap[5]),
.O(\axaddr_wrap[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6
(.I0(axaddr_wrap[4]),
.O(\axaddr_wrap[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S({\axaddr_wrap[11]_i_5_n_0 ,\axaddr_wrap[11]_i_6_n_0 ,\axaddr_wrap[11]_i_7_n_0 ,\axaddr_wrap[11]_i_8_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S({\axaddr_wrap[7]_i_3_n_0 ,\axaddr_wrap[7]_i_4_n_0 ,\axaddr_wrap[7]_i_5_n_0 ,\axaddr_wrap[7]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__0
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_awaddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[1]_INST_0
(.I0(\m_payload_i_reg[47] [1]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[1]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_3__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
(wrap_next_pending,
sel_first_reg_0,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[0]_rep ,
si_rs_arvalid,
\state_reg[1]_rep ,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input \state_reg[0]_rep ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [6:0]\axaddr_incr_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input sel_first_reg_3;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [6:0]\axaddr_incr_reg[11] ;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[11]_i_5__0_n_0 ;
wire \axaddr_wrap[11]_i_6__0_n_0 ;
wire \axaddr_wrap[11]_i_7__0_n_0 ;
wire \axaddr_wrap[11]_i_8__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_3__0_n_0 ;
wire \axaddr_wrap[7]_i_4__0_n_0 ;
wire \axaddr_wrap[7]_i_5__0_n_0 ;
wire \axaddr_wrap[7]_i_6__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[46] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_3__2_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\wrap_cnt_r_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\wrap_cnt_r_reg_n_0_[2] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[11] ),
.O(\axaddr_wrap[11]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[10] ),
.O(\axaddr_wrap[11]_i_6__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7__0
(.I0(\axaddr_wrap_reg_n_0_[9] ),
.O(\axaddr_wrap[11]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8__0
(.I0(\axaddr_wrap_reg_n_0_[8] ),
.O(\axaddr_wrap[11]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3__0
(.I0(\axaddr_wrap_reg_n_0_[7] ),
.O(\axaddr_wrap[7]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[6] ),
.O(\axaddr_wrap[7]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[5] ),
.O(\axaddr_wrap[7]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[4] ),
.O(\axaddr_wrap[7]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap[11]_i_5__0_n_0 ,\axaddr_wrap[11]_i_6__0_n_0 ,\axaddr_wrap[11]_i_7__0_n_0 ,\axaddr_wrap[11]_i_8__0_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap[7]_i_3__0_n_0 ,\axaddr_wrap[7]_i_4__0_n_0 ,\axaddr_wrap[7]_i_5__0_n_0 ,\axaddr_wrap[7]_i_6__0_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__2
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(\m_payload_i_reg[47] [2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFD55FC0C))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[46] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep_0 ),
.I3(next_pending_r_i_3__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_3__2
(.I0(\state_reg[0]_rep ),
.I1(si_rs_arvalid),
.I2(\state_reg[1]_rep ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_3__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
Q,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[11] ,
CO,
O,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[3]_1 ,
axaddr_offset_0,
\axlen_cnt_reg[3]_0 ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\cnt_read_reg[3]_rep__0 ,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\m_axi_awaddr[10] ,
\m_axi_araddr[10] ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
\state_reg[1] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
b_push,
s_axi_awvalid,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_0 ,
wrap_second_len,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_2 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_3 ,
\state_reg[1]_rep_1 ,
\axaddr_offset_r_reg[3]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
sel_first,
sel_first_2,
si_rs_bvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
axaddr_incr_reg,
\axaddr_incr_reg[3]_0 ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [58:0]Q;
output [58:0]\s_arid_r_reg[11] ;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11]_0 ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output [2:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output [2:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[3]_1 ;
output [2:0]axaddr_offset_0;
output \axlen_cnt_reg[3]_0 ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \cnt_read_reg[3]_rep__0 ;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \m_axi_awaddr[10] ;
output \m_axi_araddr[10] ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input [1:0]\state_reg[1] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [1:0]\state_reg[1]_0 ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_3 ;
input \state_reg[1]_rep_1 ;
input [3:0]\axaddr_offset_r_reg[3]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input sel_first;
input sel_first_2;
input si_rs_bvalid;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [3:0]axaddr_incr_reg;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire ar_pipe_n_2;
wire aresetn;
wire aw_pipe_n_1;
wire aw_pipe_n_97;
wire [3:0]axaddr_incr_reg;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire [0:0]\axaddr_offset_r_reg[3]_3 ;
wire [3:0]\axaddr_offset_r_reg[3]_4 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_axi_araddr[10] ;
wire \m_axi_awaddr[10] ;
wire [3:0]\m_payload_i_reg[3] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [58:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire sel_first;
wire sel_first_2;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [2:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [0:0]wrap_second_len;
wire [0:0]wrap_second_len_1;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice ar_pipe
(.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[0]_0 (aw_pipe_n_97),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11]_0 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7]_0 ),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset_0[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset_0[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_3 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_4 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_axi_araddr[10] (\m_axi_araddr[10] ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i_reg_0(ar_pipe_n_2),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_1),
.next_pending_r_reg_0(next_pending_r_reg_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.sel_first_2(sel_first_2),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_second_len_1(wrap_second_len_1),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 aw_pipe
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (aw_pipe_n_97),
.\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.\m_axi_awaddr[10] (\m_axi_awaddr[10] ),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.next_pending_r_reg_0(next_pending_r_reg_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(aw_pipe_n_1),
.sel_first(sel_first),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.\cnt_read_reg[3]_rep__0 (\cnt_read_reg[3]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11] ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_araddr[10] ,
\aresetn_d_reg[0] ,
aclk,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
sel_first_2,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\axaddr_incr_reg[3]_0 ,
m_valid_i_reg_1);
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11] ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_araddr[10] ;
input \aresetn_d_reg[0] ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input sel_first_2;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]m_valid_i_reg_1;
wire [58:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[0]_i_10__0_n_0 ;
wire \axaddr_incr[0]_i_12__0_n_0 ;
wire \axaddr_incr[0]_i_13__0_n_0 ;
wire \axaddr_incr[0]_i_14__0_n_0 ;
wire \axaddr_incr[0]_i_3__0_n_0 ;
wire \axaddr_incr[0]_i_4__0_n_0 ;
wire \axaddr_incr[0]_i_5__0_n_0 ;
wire \axaddr_incr[0]_i_6__0_n_0 ;
wire \axaddr_incr[0]_i_7__0_n_0 ;
wire \axaddr_incr[0]_i_8__0_n_0 ;
wire \axaddr_incr[0]_i_9__0_n_0 ;
wire \axaddr_incr[4]_i_10__0_n_0 ;
wire \axaddr_incr[4]_i_7__0_n_0 ;
wire \axaddr_incr[4]_i_8__0_n_0 ;
wire \axaddr_incr[4]_i_9__0_n_0 ;
wire \axaddr_incr[8]_i_10__0_n_0 ;
wire \axaddr_incr[8]_i_7__0_n_0 ;
wire \axaddr_incr[8]_i_8__0_n_0 ;
wire \axaddr_incr[8]_i_9__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_1 ;
wire \axaddr_incr_reg[0]_i_11__0_n_2 ;
wire \axaddr_incr_reg[0]_i_11__0_n_3 ;
wire \axaddr_incr_reg[0]_i_11__0_n_4 ;
wire \axaddr_incr_reg[0]_i_11__0_n_5 ;
wire \axaddr_incr_reg[0]_i_11__0_n_6 ;
wire \axaddr_incr_reg[0]_i_11__0_n_7 ;
wire \axaddr_incr_reg[0]_i_2__0_n_1 ;
wire \axaddr_incr_reg[0]_i_2__0_n_2 ;
wire \axaddr_incr_reg[0]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_1 ;
wire \axaddr_incr_reg[4]_i_6__0_n_2 ;
wire \axaddr_incr_reg[4]_i_6__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_incr_reg[8]_i_6__0_n_1 ;
wire \axaddr_incr_reg[8]_i_6__0_n_2 ;
wire \axaddr_incr_reg[8]_i_6__0_n_3 ;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_axi_araddr[10] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[48]_i_1__0_n_0 ;
wire \m_payload_i[49]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[62]_i_1__0_n_0 ;
wire \m_payload_i[63]_i_1__0_n_0 ;
wire \m_payload_i[64]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first_2;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3__0_n_0 ;
wire [2:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]wrap_second_len_1;
wire \wrap_second_len_r[0]_i_2__0_n_0 ;
wire \wrap_second_len_r[0]_i_3__0_n_0 ;
wire \wrap_second_len_r[0]_i_4__0_n_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [0]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_7 ),
.O(\axaddr_incr[0]_i_10__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14__0_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [3]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_4 ),
.O(\axaddr_incr[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [2]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_5 ),
.O(\axaddr_incr[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [1]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_6 ),
.O(\axaddr_incr[0]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10__0
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7__0
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8__0
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9__0
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10__0
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7__0
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8__0
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9__0
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9__0_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11__0_n_0 ,\axaddr_incr_reg[0]_i_11__0_n_1 ,\axaddr_incr_reg[0]_i_11__0_n_2 ,\axaddr_incr_reg[0]_i_11__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12__0_n_0 ,\axaddr_incr[0]_i_13__0_n_0 ,\axaddr_incr[0]_i_14__0_n_0 }),
.O({\axaddr_incr_reg[0]_i_11__0_n_4 ,\axaddr_incr_reg[0]_i_11__0_n_5 ,\axaddr_incr_reg[0]_i_11__0_n_6 ,\axaddr_incr_reg[0]_i_11__0_n_7 }),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[0]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[7]_0 ,\axaddr_incr_reg[0]_i_2__0_n_1 ,\axaddr_incr_reg[0]_i_2__0_n_2 ,\axaddr_incr_reg[0]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3__0_n_0 ,\axaddr_incr[0]_i_4__0_n_0 ,\axaddr_incr[0]_i_5__0_n_0 ,\axaddr_incr[0]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S({\axaddr_incr[0]_i_7__0_n_0 ,\axaddr_incr[0]_i_8__0_n_0 ,\axaddr_incr[0]_i_9__0_n_0 ,\axaddr_incr[0]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6__0
(.CI(\axaddr_incr_reg[0]_i_11__0_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6__0_n_0 ,\axaddr_incr_reg[4]_i_6__0_n_1 ,\axaddr_incr_reg[4]_i_6__0_n_2 ,\axaddr_incr_reg[4]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S({\axaddr_incr[4]_i_7__0_n_0 ,\axaddr_incr[4]_i_8__0_n_0 ,\axaddr_incr[4]_i_9__0_n_0 ,\axaddr_incr[4]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6__0
(.CI(\axaddr_incr_reg[4]_i_6__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6__0_n_1 ,\axaddr_incr_reg[8]_i_6__0_n_2 ,\axaddr_incr_reg[8]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] ),
.S({\axaddr_incr[8]_i_7__0_n_0 ,\axaddr_incr[8]_i_8__0_n_0 ,\axaddr_incr[8]_i_9__0_n_0 ,\axaddr_incr[8]_i_10__0_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2__0
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_araddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first_2),
.O(\m_axi_araddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1__0
(.I0(s_axi_arlen[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(\m_payload_i[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1__0
(.I0(s_axi_arlen[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(\m_payload_i[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arlen[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arlen[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(\m_payload_i[62]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(\m_payload_i[63]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(\m_payload_i[64]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[48]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[49]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[62]_i_1__0_n_0 ),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[63]_i_1__0_n_0 ),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[64]_i_1__0_n_0 ),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFFBBBB))
m_valid_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hFFFFFFFD))
next_pending_r_i_2__1
(.I0(next_pending_r_reg_0),
.I1(Q[46]),
.I2(Q[44]),
.I3(Q[45]),
.I4(Q[43]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__2
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_cnt_r_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3]_0 ),
.I2(wrap_second_len_1),
.O(\wrap_cnt_r_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len_1),
.I2(\wrap_cnt_r_reg[3]_0 ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_cnt_r[3]_i_3__0_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2__0
(.I0(\wrap_second_len_r[0]_i_4__0_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2__0_n_0 ),
.O(\wrap_second_len_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3__0
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4__0
(.I0(Q[39]),
.I1(\state_reg[1] [0]),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\wrap_second_len_r[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1__0
(.I0(\state_reg[1]_rep ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[11] ,
CO,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_awaddr[10] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
b_push,
s_axi_awvalid,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1] ,
wrap_second_len,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
sel_first,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
axaddr_incr_reg,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_awaddr[10] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1] ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input sel_first;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [3:0]axaddr_incr_reg;
input [0:0]E;
wire [3:0]C;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire \axaddr_incr[0]_i_10_n_0 ;
wire \axaddr_incr[0]_i_12_n_0 ;
wire \axaddr_incr[0]_i_13_n_0 ;
wire \axaddr_incr[0]_i_14_n_0 ;
wire \axaddr_incr[0]_i_3_n_0 ;
wire \axaddr_incr[0]_i_4_n_0 ;
wire \axaddr_incr[0]_i_5_n_0 ;
wire \axaddr_incr[0]_i_6_n_0 ;
wire \axaddr_incr[0]_i_7_n_0 ;
wire \axaddr_incr[0]_i_8_n_0 ;
wire \axaddr_incr[0]_i_9_n_0 ;
wire \axaddr_incr[4]_i_10_n_0 ;
wire \axaddr_incr[4]_i_7_n_0 ;
wire \axaddr_incr[4]_i_8_n_0 ;
wire \axaddr_incr[4]_i_9_n_0 ;
wire \axaddr_incr[8]_i_10_n_0 ;
wire \axaddr_incr[8]_i_7_n_0 ;
wire \axaddr_incr[8]_i_8_n_0 ;
wire \axaddr_incr[8]_i_9_n_0 ;
wire [3:0]axaddr_incr_reg;
wire \axaddr_incr_reg[0]_i_11_n_0 ;
wire \axaddr_incr_reg[0]_i_11_n_1 ;
wire \axaddr_incr_reg[0]_i_11_n_2 ;
wire \axaddr_incr_reg[0]_i_11_n_3 ;
wire \axaddr_incr_reg[0]_i_2_n_1 ;
wire \axaddr_incr_reg[0]_i_2_n_2 ;
wire \axaddr_incr_reg[0]_i_2_n_3 ;
wire [7:0]\axaddr_incr_reg[11] ;
wire \axaddr_incr_reg[4]_i_6_n_0 ;
wire \axaddr_incr_reg[4]_i_6_n_1 ;
wire \axaddr_incr_reg[4]_i_6_n_2 ;
wire \axaddr_incr_reg[4]_i_6_n_3 ;
wire \axaddr_incr_reg[8]_i_6_n_1 ;
wire \axaddr_incr_reg[8]_i_6_n_2 ;
wire \axaddr_incr_reg[8]_i_6_n_3 ;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \m_axi_awaddr[10] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first;
wire [64:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [0:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[0]),
.I3(sel_first),
.I4(C[0]),
.O(\axaddr_incr[0]_i_10_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[3]),
.I3(sel_first),
.I4(C[3]),
.O(\axaddr_incr[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[2]),
.I3(sel_first),
.I4(C[2]),
.O(\axaddr_incr[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[1]),
.I3(sel_first),
.I4(C[1]),
.O(\axaddr_incr[0]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11_n_0 ,\axaddr_incr_reg[0]_i_11_n_1 ,\axaddr_incr_reg[0]_i_11_n_2 ,\axaddr_incr_reg[0]_i_11_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12_n_0 ,\axaddr_incr[0]_i_13_n_0 ,\axaddr_incr[0]_i_14_n_0 }),
.O(C),
.S(S));
CARRY4 \axaddr_incr_reg[0]_i_2
(.CI(1'b0),
.CO({CO,\axaddr_incr_reg[0]_i_2_n_1 ,\axaddr_incr_reg[0]_i_2_n_2 ,\axaddr_incr_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3_n_0 ,\axaddr_incr[0]_i_4_n_0 ,\axaddr_incr[0]_i_5_n_0 ,\axaddr_incr[0]_i_6_n_0 }),
.O(O),
.S({\axaddr_incr[0]_i_7_n_0 ,\axaddr_incr[0]_i_8_n_0 ,\axaddr_incr[0]_i_9_n_0 ,\axaddr_incr[0]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6
(.CI(\axaddr_incr_reg[0]_i_11_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6_n_0 ,\axaddr_incr_reg[4]_i_6_n_1 ,\axaddr_incr_reg[4]_i_6_n_2 ,\axaddr_incr_reg[4]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [3:0]),
.S({\axaddr_incr[4]_i_7_n_0 ,\axaddr_incr[4]_i_8_n_0 ,\axaddr_incr[4]_i_9_n_0 ,\axaddr_incr[4]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6
(.CI(\axaddr_incr_reg[4]_i_6_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6_n_1 ,\axaddr_incr_reg[8]_i_6_n_2 ,\axaddr_incr_reg[8]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [7:4]),
.S({\axaddr_incr[8]_i_7_n_0 ,\axaddr_incr[8]_i_8_n_0 ,\axaddr_incr[8]_i_9_n_0 ,\axaddr_incr[8]_i_10_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[2]_i_3_n_0 ),
.I1(\axaddr_offset_r[1]_i_2_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first),
.O(\m_axi_awaddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(s_axi_awlen[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(s_axi_awlen[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awlen[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awlen[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(skid_buffer[62]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(skid_buffer[63]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(skid_buffer[64]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(E),
.D(skid_buffer[62]),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(E),
.D(skid_buffer[63]),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(E),
.D(skid_buffer[64]),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
next_pending_r_i_2
(.I0(next_pending_r_reg_0),
.I1(Q[43]),
.I2(Q[44]),
.I3(Q[46]),
.I4(Q[45]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2__0
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hBFBB))
s_ready_i_i_2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3] ),
.I2(wrap_second_len),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len),
.I2(\wrap_cnt_r_reg[3] ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3] ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2
(.I0(\wrap_second_len_r[0]_i_4_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2_n_0 ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep_0 ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4
(.I0(Q[39]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep_0 ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[3]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[3]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__1_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[3]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(* $Id: SetoidList.v 11800 2009-01-18 18:34:15Z msozeau $ *)
Require Export List.
Require Export Sorting.
Require Export Setoid.
Set Implicit Arguments.
Unset Strict Implicit.
(** * Logical relations over lists with respect to a setoid equality
or ordering. *)
(** This can be seen as a complement of predicate [lelistA] and [sort]
found in [Sorting]. *)
Section Type_with_equality.
Variable A : Type.
Variable eqA : A -> A -> Prop.
(** Being in a list modulo an equality relation over type [A]. *)
Inductive InA (x : A) : list A -> Prop :=
| InA_cons_hd : forall y l, eqA x y -> InA x (y :: l)
| InA_cons_tl : forall y l, InA x l -> InA x (y :: l).
Hint Constructors InA.
Lemma InA_cons : forall x y l, InA x (y::l) <-> eqA x y \/ InA x l.
Proof.
intuition.
inversion H; auto.
Qed.
Lemma InA_nil : forall x, InA x nil <-> False.
Proof.
intuition.
inversion H.
Qed.
(** An alternative definition of [InA]. *)
Lemma InA_alt : forall x l, InA x l <-> exists y, eqA x y /\ In y l.
Proof.
induction l; intuition.
inversion H.
firstorder.
inversion H1; firstorder.
firstorder; subst; auto.
Qed.
(** A list without redundancy modulo the equality over [A]. *)
Inductive NoDupA : list A -> Prop :=
| NoDupA_nil : NoDupA nil
| NoDupA_cons : forall x l, ~ InA x l -> NoDupA l -> NoDupA (x::l).
Hint Constructors NoDupA.
(** lists with same elements modulo [eqA] *)
Definition equivlistA l l' := forall x, InA x l <-> InA x l'.
(** lists with same elements modulo [eqA] at the same place *)
Inductive eqlistA : list A -> list A -> Prop :=
| eqlistA_nil : eqlistA nil nil
| eqlistA_cons : forall x x' l l',
eqA x x' -> eqlistA l l' -> eqlistA (x::l) (x'::l').
Hint Constructors eqlistA.
(** Compatibility of a boolean function with respect to an equality. *)
Definition compat_bool (f : A->bool) := forall x y, eqA x y -> f x = f y.
(** Compatibility of a function upon natural numbers. *)
Definition compat_nat (f : A->nat) := forall x y, eqA x y -> f x = f y.
(** Compatibility of a predicate with respect to an equality. *)
Definition compat_P (P : A->Prop) := forall x y, eqA x y -> P x -> P y.
(** Results concerning lists modulo [eqA] *)
Hypothesis eqA_refl : forall x, eqA x x.
Hypothesis eqA_sym : forall x y, eqA x y -> eqA y x.
Hypothesis eqA_trans : forall x y z, eqA x y -> eqA y z -> eqA x z.
Hint Resolve eqA_refl eqA_trans.
Hint Immediate eqA_sym.
Lemma InA_eqA : forall l x y, eqA x y -> InA x l -> InA y l.
Proof.
intros s x y.
do 2 rewrite InA_alt.
intros H (z,(U,V)).
exists z; split; eauto.
Qed.
Hint Immediate InA_eqA.
Lemma In_InA : forall l x, In x l -> InA x l.
Proof.
simple induction l; simpl in |- *; intuition.
subst; auto.
Qed.
Hint Resolve In_InA.
Lemma InA_split : forall l x, InA x l ->
exists l1, exists y, exists l2,
eqA x y /\ l = l1++y::l2.
Proof.
induction l; inversion_clear 1.
exists (@nil A); exists a; exists l; auto.
destruct (IHl x H0) as (l1,(y,(l2,(H1,H2)))).
exists (a::l1); exists y; exists l2; auto.
split; simpl; f_equal; auto.
Qed.
Lemma InA_app : forall l1 l2 x,
InA x (l1 ++ l2) -> InA x l1 \/ InA x l2.
Proof.
induction l1; simpl in *; intuition.
inversion_clear H; auto.
elim (IHl1 l2 x H0); auto.
Qed.
Lemma InA_app_iff : forall l1 l2 x,
InA x (l1 ++ l2) <-> InA x l1 \/ InA x l2.
Proof.
split.
apply InA_app.
destruct 1; generalize H; do 2 rewrite InA_alt.
destruct 1 as (y,(H1,H2)); exists y; split; auto.
apply in_or_app; auto.
destruct 1 as (y,(H1,H2)); exists y; split; auto.
apply in_or_app; auto.
Qed.
Lemma InA_rev : forall p m,
InA p (rev m) <-> InA p m.
Proof.
intros; do 2 rewrite InA_alt.
split; intros (y,H); exists y; intuition.
rewrite In_rev; auto.
rewrite <- In_rev; auto.
Qed.
(** Results concerning lists modulo [eqA] and [ltA] *)
Variable ltA : A -> A -> Prop.
Hypothesis ltA_trans : forall x y z, ltA x y -> ltA y z -> ltA x z.
Hypothesis ltA_not_eqA : forall x y, ltA x y -> ~ eqA x y.
Hypothesis ltA_eqA : forall x y z, ltA x y -> eqA y z -> ltA x z.
Hypothesis eqA_ltA : forall x y z, eqA x y -> ltA y z -> ltA x z.
Hint Resolve ltA_trans.
Hint Immediate ltA_eqA eqA_ltA.
Notation InfA:=(lelistA ltA).
Notation SortA:=(sort ltA).
Hint Constructors lelistA sort.
Lemma InfA_ltA :
forall l x y, ltA x y -> InfA y l -> InfA x l.
Proof.
destruct l; constructor; inversion_clear H0;
eapply ltA_trans; eauto.
Qed.
Lemma InfA_eqA :
forall l x y, eqA x y -> InfA y l -> InfA x l.
Proof.
intro s; case s; constructor; inversion_clear H0; eauto.
Qed.
Hint Immediate InfA_ltA InfA_eqA.
Lemma SortA_InfA_InA :
forall l x a, SortA l -> InfA a l -> InA x l -> ltA a x.
Proof.
simple induction l.
intros; inversion H1.
intros.
inversion_clear H0; inversion_clear H1; inversion_clear H2.
eapply ltA_eqA; eauto.
eauto.
Qed.
Lemma In_InfA :
forall l x, (forall y, In y l -> ltA x y) -> InfA x l.
Proof.
simple induction l; simpl in |- *; intros; constructor; auto.
Qed.
Lemma InA_InfA :
forall l x, (forall y, InA y l -> ltA x y) -> InfA x l.
Proof.
simple induction l; simpl in |- *; intros; constructor; auto.
Qed.
(* In fact, this may be used as an alternative definition for InfA: *)
Lemma InfA_alt :
forall l x, SortA l -> (InfA x l <-> (forall y, InA y l -> ltA x y)).
Proof.
split.
intros; eapply SortA_InfA_InA; eauto.
apply InA_InfA.
Qed.
Lemma InfA_app : forall l1 l2 a, InfA a l1 -> InfA a l2 -> InfA a (l1++l2).
Proof.
induction l1; simpl; auto.
inversion_clear 1; auto.
Qed.
Lemma SortA_app :
forall l1 l2, SortA l1 -> SortA l2 ->
(forall x y, InA x l1 -> InA y l2 -> ltA x y) ->
SortA (l1 ++ l2).
Proof.
induction l1; simpl in *; intuition.
inversion_clear H.
constructor; auto.
apply InfA_app; auto.
destruct l2; auto.
Qed.
Section NoDupA.
Lemma SortA_NoDupA : forall l, SortA l -> NoDupA l.
Proof.
simple induction l; auto.
intros x l' H H0.
inversion_clear H0.
constructor; auto.
intro.
assert (ltA x x) by (eapply SortA_InfA_InA; eauto).
elim (ltA_not_eqA H3); auto.
Qed.
Lemma NoDupA_app : forall l l', NoDupA l -> NoDupA l' ->
(forall x, InA x l -> InA x l' -> False) ->
NoDupA (l++l').
Proof.
induction l; simpl; auto; intros.
inversion_clear H.
constructor.
rewrite InA_alt; intros (y,(H4,H5)).
destruct (in_app_or _ _ _ H5).
elim H2.
rewrite InA_alt.
exists y; auto.
apply (H1 a).
auto.
rewrite InA_alt.
exists y; auto.
apply IHl; auto.
intros.
apply (H1 x); auto.
Qed.
Lemma NoDupA_rev : forall l, NoDupA l -> NoDupA (rev l).
Proof.
induction l.
simpl; auto.
simpl; intros.
inversion_clear H.
apply NoDupA_app; auto.
constructor; auto.
intro H2; inversion H2.
intros x.
rewrite InA_alt.
intros (x1,(H2,H3)).
inversion_clear 1.
destruct H0.
apply InA_eqA with x1; eauto.
apply In_InA.
rewrite In_rev; auto.
inversion H4.
Qed.
Lemma NoDupA_split : forall l l' x, NoDupA (l++x::l') -> NoDupA (l++l').
Proof.
induction l; simpl in *; inversion_clear 1; auto.
constructor; eauto.
contradict H0.
rewrite InA_app_iff in *; rewrite InA_cons; intuition.
Qed.
Lemma NoDupA_swap : forall l l' x, NoDupA (l++x::l') -> NoDupA (x::l++l').
Proof.
induction l; simpl in *; inversion_clear 1; auto.
constructor; eauto.
assert (H2:=IHl _ _ H1).
inversion_clear H2.
rewrite InA_cons.
red; destruct 1.
apply H0.
rewrite InA_app_iff in *; rewrite InA_cons; auto.
apply H; auto.
constructor.
contradict H0.
rewrite InA_app_iff in *; rewrite InA_cons; intuition.
eapply NoDupA_split; eauto.
Qed.
End NoDupA.
(** Some results about [eqlistA] *)
Section EqlistA.
Lemma eqlistA_length : forall l l', eqlistA l l' -> length l = length l'.
Proof.
induction 1; auto; simpl; congruence.
Qed.
Lemma eqlistA_app : forall l1 l1' l2 l2',
eqlistA l1 l1' -> eqlistA l2 l2' -> eqlistA (l1++l2) (l1'++l2').
Proof.
intros l1 l1' l2 l2' H; revert l2 l2'; induction H; simpl; auto.
Qed.
Lemma eqlistA_rev_app : forall l1 l1',
eqlistA l1 l1' -> forall l2 l2', eqlistA l2 l2' ->
eqlistA ((rev l1)++l2) ((rev l1')++l2').
Proof.
induction 1; auto.
simpl; intros.
do 2 rewrite app_ass; simpl; auto.
Qed.
Lemma eqlistA_rev : forall l1 l1',
eqlistA l1 l1' -> eqlistA (rev l1) (rev l1').
Proof.
intros.
rewrite (app_nil_end (rev l1)).
rewrite (app_nil_end (rev l1')).
apply eqlistA_rev_app; auto.
Qed.
Lemma SortA_equivlistA_eqlistA : forall l l',
SortA l -> SortA l' -> equivlistA l l' -> eqlistA l l'.
Proof.
induction l; destruct l'; simpl; intros; auto.
destruct (H1 a); assert (H4 : InA a nil) by auto; inversion H4.
destruct (H1 a); assert (H4 : InA a nil) by auto; inversion H4.
inversion_clear H; inversion_clear H0.
assert (forall y, InA y l -> ltA a y).
intros; eapply SortA_InfA_InA with (l:=l); eauto.
assert (forall y, InA y l' -> ltA a0 y).
intros; eapply SortA_InfA_InA with (l:=l'); eauto.
clear H3 H4.
assert (eqA a a0).
destruct (H1 a).
destruct (H1 a0).
assert (InA a (a0::l')) by auto.
inversion_clear H8; auto.
assert (InA a0 (a::l)) by auto.
inversion_clear H8; auto.
elim (@ltA_not_eqA a a); auto.
apply ltA_trans with a0; auto.
constructor; auto.
apply IHl; auto.
split; intros.
destruct (H1 x).
assert (H8 : InA x (a0::l')) by auto; inversion_clear H8; auto.
elim (@ltA_not_eqA a x); eauto.
destruct (H1 x).
assert (H8 : InA x (a::l)) by auto; inversion_clear H8; auto.
elim (@ltA_not_eqA a0 x); eauto.
Qed.
End EqlistA.
(** A few things about [filter] *)
Section Filter.
Lemma filter_sort : forall f l, SortA l -> SortA (List.filter f l).
Proof.
induction l; simpl; auto.
inversion_clear 1; auto.
destruct (f a); auto.
constructor; auto.
apply In_InfA; auto.
intros.
rewrite filter_In in H; destruct H.
eapply SortA_InfA_InA; eauto.
Qed.
Lemma filter_InA : forall f, (compat_bool f) ->
forall l x, InA x (List.filter f l) <-> InA x l /\ f x = true.
Proof.
intros; do 2 rewrite InA_alt; intuition.
destruct H0 as (y,(H0,H1)); rewrite filter_In in H1; exists y; intuition.
destruct H0 as (y,(H0,H1)); rewrite filter_In in H1; intuition.
rewrite (H _ _ H0); auto.
destruct H1 as (y,(H0,H1)); exists y; rewrite filter_In; intuition.
rewrite <- (H _ _ H0); auto.
Qed.
Lemma filter_split :
forall f, (forall x y, f x = true -> f y = false -> ltA x y) ->
forall l, SortA l -> l = filter f l ++ filter (fun x=>negb (f x)) l.
Proof.
induction l; simpl; intros; auto.
inversion_clear H0.
pattern l at 1; rewrite IHl; auto.
case_eq (f a); simpl; intros; auto.
assert (forall e, In e l -> f e = false).
intros.
assert (H4:=SortA_InfA_InA H1 H2 (In_InA H3)).
case_eq (f e); simpl; intros; auto.
elim (@ltA_not_eqA e e); auto.
apply ltA_trans with a; eauto.
replace (List.filter f l) with (@nil A); auto.
generalize H3; clear; induction l; simpl; auto.
case_eq (f a); auto; intros.
rewrite H3 in H; auto; try discriminate.
Qed.
End Filter.
Section Fold.
Variable B:Type.
Variable eqB:B->B->Prop.
(** Compatibility of a two-argument function with respect to two equalities. *)
Definition compat_op (f : A -> B -> B) :=
forall (x x' : A) (y y' : B), eqA x x' -> eqB y y' -> eqB (f x y) (f x' y').
(** Two-argument functions that allow to reorder their arguments. *)
Definition transpose (f : A -> B -> B) :=
forall (x y : A) (z : B), eqB (f x (f y z)) (f y (f x z)).
(** A version of transpose with restriction on where it should hold *)
Definition transpose_restr (R : A -> A -> Prop)(f : A -> B -> B) :=
forall (x y : A) (z : B), R x y -> eqB (f x (f y z)) (f y (f x z)).
Variable st:Equivalence eqB.
Variable f:A->B->B.
Variable i:B.
Variable Comp:compat_op f.
Lemma fold_right_eqlistA :
forall s s', eqlistA s s' ->
eqB (fold_right f i s) (fold_right f i s').
Proof.
induction 1; simpl; auto.
reflexivity.
Qed.
Lemma equivlistA_NoDupA_split : forall l l1 l2 x y, eqA x y ->
NoDupA (x::l) -> NoDupA (l1++y::l2) ->
equivlistA (x::l) (l1++y::l2) -> equivlistA l (l1++l2).
Proof.
intros; intro a.
generalize (H2 a).
repeat rewrite InA_app_iff.
do 2 rewrite InA_cons.
inversion_clear H0.
assert (SW:=NoDupA_swap H1).
inversion_clear SW.
rewrite InA_app_iff in H0.
split; intros.
assert (~eqA a x).
contradict H3; apply InA_eqA with a; auto.
assert (~eqA a y).
contradict H8; eauto.
intuition.
assert (eqA a x \/ InA a l) by intuition.
destruct H8; auto.
elim H0.
destruct H7; [left|right]; eapply InA_eqA; eauto.
Qed.
(** [ForallList2] : specifies that a certain binary predicate should
always hold when inspecting two different elements of the list. *)
Inductive ForallList2 (R : A -> A -> Prop) : list A -> Prop :=
| ForallNil : ForallList2 R nil
| ForallCons : forall a l,
(forall b, In b l -> R a b) ->
ForallList2 R l -> ForallList2 R (a::l).
Hint Constructors ForallList2.
(** [NoDupA] can be written in terms of [ForallList2] *)
Lemma ForallList2_NoDupA : forall l,
ForallList2 (fun a b => ~eqA a b) l <-> NoDupA l.
Proof.
induction l; split; intros; auto.
inversion_clear H. constructor; [ | rewrite <- IHl; auto ].
rewrite InA_alt; intros (a',(Haa',Ha')).
exact (H0 a' Ha' Haa').
inversion_clear H. constructor; [ | rewrite IHl; auto ].
intros b Hb.
contradict H0.
rewrite InA_alt; exists b; auto.
Qed.
Lemma ForallList2_impl : forall (R R':A->A->Prop),
(forall a b, R a b -> R' a b) ->
forall l, ForallList2 R l -> ForallList2 R' l.
Proof.
induction 2; auto.
Qed.
(** The following definition is easier to use than [ForallList2]. *)
Definition ForallList2_alt (R:A->A->Prop) l :=
forall a b, InA a l -> InA b l -> ~eqA a b -> R a b.
Section Restriction.
Variable R : A -> A -> Prop.
(** [ForallList2] and [ForallList2_alt] are related, but no completely
equivalent. For proving one implication, we need to know that the
list has no duplicated elements... *)
Lemma ForallList2_equiv1 : forall l, NoDupA l ->
ForallList2_alt R l -> ForallList2 R l.
Proof.
induction l; auto.
constructor. intros b Hb.
inversion_clear H.
apply H0; auto.
contradict H1.
apply InA_eqA with b; auto.
apply IHl.
inversion_clear H; auto.
intros b c Hb Hc Hneq.
apply H0; auto.
Qed.
(** ... and for proving the other implication, we need to be able
to reverse and adapt relation [R] modulo [eqA]. *)
Hypothesis R_sym : forall a b, R a b -> R b a.
Hypothesis R_compat : forall a, compat_P (R a).
Lemma ForallList2_equiv2 : forall l,
ForallList2 R l -> ForallList2_alt R l.
Proof.
induction l.
intros _. red. intros a b Ha. inversion Ha.
inversion_clear 1 as [|? ? H_R Hl].
intros b c Hb Hc Hneq.
inversion_clear Hb; inversion_clear Hc.
(* b,c = a : impossible *)
elim Hneq; eauto.
(* b = a, c in l *)
rewrite InA_alt in H0; destruct H0 as (d,(Hcd,Hd)).
apply R_compat with d; auto.
apply R_sym; apply R_compat with a; auto.
(* b in l, c = a *)
rewrite InA_alt in H; destruct H as (d,(Hcd,Hd)).
apply R_compat with a; auto.
apply R_sym; apply R_compat with d; auto.
(* b,c in l *)
apply (IHl Hl); auto.
Qed.
Lemma ForallList2_equiv : forall l, NoDupA l ->
(ForallList2 R l <-> ForallList2_alt R l).
Proof.
split; [apply ForallList2_equiv2|apply ForallList2_equiv1]; auto.
Qed.
Lemma ForallList2_equivlistA : forall l l', NoDupA l' ->
equivlistA l l' -> ForallList2 R l -> ForallList2 R l'.
Proof.
intros.
apply ForallList2_equiv1; auto.
intros a b Ha Hb Hneq.
red in H0; rewrite <- H0 in Ha,Hb.
revert a b Ha Hb Hneq.
change (ForallList2_alt R l).
apply ForallList2_equiv2; auto.
Qed.
Variable TraR :transpose_restr R f.
Lemma fold_right_commutes_restr :
forall s1 s2 x, ForallList2 R (s1++x::s2) ->
eqB (fold_right f i (s1++x::s2)) (f x (fold_right f i (s1++s2))).
Proof.
induction s1; simpl; auto; intros.
reflexivity.
transitivity (f a (f x (fold_right f i (s1++s2)))).
apply Comp; auto.
apply IHs1.
inversion_clear H; auto.
apply TraR.
inversion_clear H.
apply H0.
apply in_or_app; simpl; auto.
Qed.
Lemma fold_right_equivlistA_restr :
forall s s', NoDupA s -> NoDupA s' -> ForallList2 R s ->
equivlistA s s' -> eqB (fold_right f i s) (fold_right f i s').
Proof.
simple induction s.
destruct s'; simpl.
intros; reflexivity.
unfold equivlistA; intros.
destruct (H2 a).
assert (X : InA a nil); auto; inversion X.
intros x l Hrec s' N N' F E; simpl in *.
assert (InA x s').
rewrite <- (E x); auto.
destruct (InA_split H) as (s1,(y,(s2,(H1,H2)))).
subst s'.
transitivity (f x (fold_right f i (s1++s2))).
apply Comp; auto.
apply Hrec; auto.
inversion_clear N; auto.
eapply NoDupA_split; eauto.
inversion_clear F; auto.
eapply equivlistA_NoDupA_split; eauto.
transitivity (f y (fold_right f i (s1++s2))).
apply Comp; auto. reflexivity.
symmetry; apply fold_right_commutes_restr.
apply ForallList2_equivlistA with (x::l); auto.
Qed.
Lemma fold_right_add_restr :
forall s' s x, NoDupA s -> NoDupA s' -> ForallList2 R s' -> ~ InA x s ->
equivlistA s' (x::s) -> eqB (fold_right f i s') (f x (fold_right f i s)).
Proof.
intros; apply (@fold_right_equivlistA_restr s' (x::s)); auto.
Qed.
End Restriction.
(** we know state similar results, but without restriction on transpose. *)
Variable Tra :transpose f.
Lemma fold_right_commutes : forall s1 s2 x,
eqB (fold_right f i (s1++x::s2)) (f x (fold_right f i (s1++s2))).
Proof.
induction s1; simpl; auto; intros.
reflexivity.
transitivity (f a (f x (fold_right f i (s1++s2)))); auto.
Qed.
Lemma fold_right_equivlistA :
forall s s', NoDupA s -> NoDupA s' ->
equivlistA s s' -> eqB (fold_right f i s) (fold_right f i s').
Proof.
intros; apply fold_right_equivlistA_restr with (R:=fun _ _ => True);
try red; auto.
apply ForallList2_equiv1; try red; auto.
Qed.
Lemma fold_right_add :
forall s' s x, NoDupA s -> NoDupA s' -> ~ InA x s ->
equivlistA s' (x::s) -> eqB (fold_right f i s') (f x (fold_right f i s)).
Proof.
intros; apply (@fold_right_equivlistA s' (x::s)); auto.
Qed.
Section Remove.
Hypothesis eqA_dec : forall x y : A, {eqA x y}+{~(eqA x y)}.
Lemma InA_dec : forall x l, { InA x l } + { ~ InA x l }.
Proof.
induction l.
right; auto.
red; inversion 1.
destruct (eqA_dec x a).
left; auto.
destruct IHl.
left; auto.
right; red; inversion_clear 1; contradiction.
Qed.
Fixpoint removeA (x : A) (l : list A){struct l} : list A :=
match l with
| nil => nil
| y::tl => if (eqA_dec x y) then removeA x tl else y::(removeA x tl)
end.
Lemma removeA_filter : forall x l,
removeA x l = filter (fun y => if eqA_dec x y then false else true) l.
Proof.
induction l; simpl; auto.
destruct (eqA_dec x a); auto.
rewrite IHl; auto.
Qed.
Lemma removeA_InA : forall l x y, InA y (removeA x l) <-> InA y l /\ ~eqA x y.
Proof.
induction l; simpl; auto.
split.
inversion_clear 1.
destruct 1; inversion_clear H.
intros.
destruct (eqA_dec x a); simpl; auto.
rewrite IHl; split; destruct 1; split; auto.
inversion_clear H; auto.
destruct H0; apply eqA_trans with a; auto.
split.
inversion_clear 1.
split; auto.
contradict n.
apply eqA_trans with y; auto.
rewrite (IHl x y) in H0; destruct H0; auto.
destruct 1; inversion_clear H; auto.
constructor 2; rewrite IHl; auto.
Qed.
Lemma removeA_NoDupA :
forall s x, NoDupA s -> NoDupA (removeA x s).
Proof.
simple induction s; simpl; intros.
auto.
inversion_clear H0.
destruct (eqA_dec x a); simpl; auto.
constructor; auto.
rewrite removeA_InA.
intuition.
Qed.
Lemma removeA_equivlistA : forall l l' x,
~InA x l -> equivlistA (x :: l) l' -> equivlistA l (removeA x l').
Proof.
unfold equivlistA; intros.
rewrite removeA_InA.
split; intros.
rewrite <- H0; split; auto.
contradict H.
apply InA_eqA with x0; auto.
rewrite <- (H0 x0) in H1.
destruct H1.
inversion_clear H1; auto.
elim H2; auto.
Qed.
End Remove.
End Fold.
End Type_with_equality.
Hint Unfold compat_bool compat_nat compat_P.
Hint Constructors InA NoDupA sort lelistA eqlistA.
Section Find.
Variable A B : Type.
Variable eqA : A -> A -> Prop.
Hypothesis eqA_sym : forall x y, eqA x y -> eqA y x.
Hypothesis eqA_trans : forall x y z, eqA x y -> eqA y z -> eqA x z.
Hypothesis eqA_dec : forall x y : A, {eqA x y}+{~(eqA x y)}.
Fixpoint findA (f : A -> bool) (l:list (A*B)) : option B :=
match l with
| nil => None
| (a,b)::l => if f a then Some b else findA f l
end.
Lemma findA_NoDupA :
forall l a b,
NoDupA (fun p p' => eqA (fst p) (fst p')) l ->
(InA (fun p p' => eqA (fst p) (fst p') /\ snd p = snd p') (a,b) l <->
findA (fun a' => if eqA_dec a a' then true else false) l = Some b).
Proof.
induction l; simpl; intros.
split; intros; try discriminate.
inversion H0.
destruct a as (a',b'); rename a0 into a.
inversion_clear H.
split; intros.
inversion_clear H.
simpl in *; destruct H2; subst b'.
destruct (eqA_dec a a'); intuition.
destruct (eqA_dec a a'); simpl.
destruct H0.
generalize e H2 eqA_trans eqA_sym; clear.
induction l.
inversion 2.
inversion_clear 2; intros; auto.
destruct a0.
compute in H; destruct H.
subst b.
constructor 1; auto.
simpl.
apply eqA_trans with a; auto.
rewrite <- IHl; auto.
destruct (eqA_dec a a'); simpl in *.
inversion H; clear H; intros; subst b'; auto.
constructor 2.
rewrite IHl; auto.
Qed.
End Find.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pcie_pipe_misc.v
// Version : 1.11
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcieCore_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
`timescale 1ns / 1ps
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Design File: scores2.v
// Score keeper and character generator.
//
// Pins description:
// clk input master clock
// neglineclk input line clock (hsync)
// realx input x-coordinate
// realy input y-coordinate
// score_addA input left score increment
// score_addB input right score increment
// score_reset input score reset
// scoreA output left score bcd value
// scoreB output right score bcd value
// score_scan output score scan
//
// Contains additional modules:
// module bcdcounterx(reset, c, cout, q);
// module unicounter(c, r, en, q1, q2, q3);
// module mux2x4(sel, d0, d1, d2, d3, q); -- can be used instead of scorecopymux macro
// module textramx(clk, d, a, q);
// module charrom(clk, char, line, q);
// module digit(scanline, pixels);
// module counter_mod4(c, r, q, cout);
// module counter_mod8(c, r, q, cout);
module scores(clk, neglineclk, realx, realy, score_addA, score_addB, score_reset, scoreA, scoreB, score_scan);
input clk;
input neglineclk;
input [9:0] realx, realy;
input score_addA, score_addB, score_reset;
output [7:0]scoreA, scoreB;
output score_scan;
// score counters
wire scout1, scout2, scout3, scout4;
wire [3:0] score0;
wire [3:0] score1;
wire [3:0] score2;
wire [3:0] score3;
bcdcounterx bcdcounter1(score_reset, score_addA, scout1, score1);
bcdcounterx bcdcounter2(score_reset, scout1, scout2, score0);
bcdcounterx bcdcounter3(score_reset, score_addB, scout3, score3);
bcdcounterx bcdcounter4(score_reset, scout3, scout4, score2);
reg [7:0] scoreA, scoreB;
always @(score0 or score1 or score2 or score3) begin
scoreA <= {score0,score1};
scoreB <= {score2,score3};
end
parameter XSTART = 640/2-3*8*4;
parameter YSTART = 6*8;
reg rscxr;
wire scxr = rscxr; //= realx == XSTART; // reset of x counters
always @(negedge clk) begin
if (realx == XSTART) rscxr <= 1;
else rscxr <= 0;
end
wire newline = !neglineclk;//realx == 0;
wire scyr = realy == YSTART; // reset of y counters
reg [7:0] xwide;
always @(posedge clk) begin
if (scxr)
xwide <= 6*8*4;
else
if (xwide > 0) xwide <= xwide - 1;
end
wire display_ax = xwide != 0;
wire display_ay = realy >= YSTART && realy < YSTART+5*8;
wire displayactive = display_ax & display_ay & skippy;
// leap skippy
reg skippy;
always @(posedge clk) begin
if (realx == XSTART + 2*8*4) begin
skippy <= 0;
end else if (realx == XSTART + 4*8*4) begin
skippy <= 1;
end
end
wire [3:0] dummy;
wire [1:0] bitnumber; // this selects the bit from charrom out
wire [1:0] textadr;
unicounter unicounter(clk, scxr, skippy & display_ax, dummy[2:0], bitnumber, textadr);
wire [2:0] y;
unicounter ycounter(newline, scyr, display_ay, dummy[2:0], y[1:0], {dummy[0],y[2]});
// mux score counters
wire [3:0] textd; // this goes into text ram
//mux2x4 muxscorbles(textadr, score[0], score[1], score[2], score[3], textd);
scorecopymux scorecopymux(score0, score1, score2, score3, textadr, textd);
// the character rom and pixels
wire [3:0] pixels;
charrom charrom(clk, charcode, y, pixels);
// where the actual digits are!
wire [3:0] charcode;
textramx displaymem(clk, textd, textadr, charcode);
reg sscan;
always @(posedge clk) begin
sscan <= displayactive & pixels[bitnumber];
end
assign score_scan = sscan;
//assign score_scan = displayactive & pixels[bitnumber];
endmodule
module bcdcounterx(reset, c, cout, q);
input reset, c;
output reg cout;
output reg [3:0]q;
always @(posedge reset or posedge c) begin
if (reset) {cout, q} <= 0;
else begin
if (q == 9)
{cout, q} <= {5'b10000};
else
{cout, q} <= q + 1'b1;
end
end
endmodule
module unicounter(c, r, en, q1, q2, q3);
input c, r, en;
output [2:0] q1;
output [1:0] q2;
output [1:0] q3;
reg [6:0]q;
assign q1 = q[2:0];
assign q2 = q[4:3];
assign q3 = q[6:5];
always @(posedge c)
if (r)
q <= 0;
else if (en)
q <= q + 1'b1;
endmodule
module mux2x4(sel, d0, d1, d2, d3, q);
input [1:0] sel;
input [3:0] d0, d1, d2, d3;
output [3:0] q;
assign q = sel == 2'b00 ? d0 :
2'b01 ? d1 :
2'b10 ? d2 : d3;
endmodule
module textramx(clk, d, a, q);
input clk;
input [3:0] d;
input [1:0] a;
output [3:0] q;
reg [3:0] ram[3:0]; // 4 locations 4-bit wide each
reg [3:0] q;
//assign q = ram[a];
// always @(posedge clk) begin
// q <= ram[a];
// ram[a] <= d;
// end
always @(d or a) begin
q <= ram[a];
ram[a] <= d;
end
endmodule
module charrom(clk, char, line, q);
input clk;
input [3:0] char;
input [2:0] line;
output reg[3:0] q;
always @(char or pixels0 or pixels1 or pixels2 or pixels3 or pixels4 or pixels5 or pixels6 or pixels7 or pixels8 or pixels9)
case (char)
4'd0 : q <= pixels0;
4'd1 : q <= pixels1;
4'd2 : q <= pixels2;
4'd3 : q <= pixels3;
4'd4 : q <= pixels4;
4'd5 : q <= pixels5;
4'd6 : q <= pixels6;
4'd7 : q <= pixels7;
4'd8 : q <= pixels8;
4'd9 : q <= pixels9;
default:
q <= 0;
endcase
wire [3:0] pixels0;
digit #(
4'b1110,
4'b1010,
4'b1010,
4'b1010,
4'b1110
) dzigit0(line, pixels0);
wire [3:0] pixels1;
digit #(
4'b1100,
4'b0100,
4'b0100,
4'b0100,
4'b1110
) dzigit1(line, pixels1);
wire [3:0] pixels2;
digit #(
4'b1110,
4'b0010,
4'b1110,
4'b1000,
4'b1110
) dzigit2(line, pixels2);
wire [3:0] pixels3;
digit #(
4'b1110,
4'b0010,
4'b0110,
4'b0010,
4'b1110
) dzigit3(line, pixels3);
wire [3:0] pixels4;
digit #(
4'b1010,
4'b1010,
4'b1110,
4'b0010,
4'b0010
) dzigit4(line, pixels4);
wire [3:0] pixels5;
digit #(
4'b1110,
4'b1000,
4'b1110,
4'b0010,
4'b1110
) dzigit5(line, pixels5);
wire [3:0] pixels6;
digit #(
4'b1110,
4'b1000,
4'b1110,
4'b1010,
4'b1110
) dzigit6(line, pixels6);
wire [3:0] pixels7;
digit #(
4'b1110,
4'b0010,
4'b0010,
4'b0010,
4'b0010
) dzigit7(line, pixels7);
wire [3:0] pixels8;
digit #(
4'b1110,
4'b1010,
4'b1110,
4'b1010,
4'b1110
) dzigit8(line, pixels8);
wire [3:0] pixels9;
digit #(
4'b1110,
4'b1010,
4'b1110,
4'b0010,
4'b1110
) dzigit9(line, pixels9);
endmodule
module digit(scanline, pixels);
input [2:0] scanline;
output [3:0] pixels;
parameter a=0,b=0,c=0,d=0,e=0;
assign pixels = scanline == 3'd0 ? {a[0],a[1],a[2],a[3]} :
scanline == 3'd1 ? {b[0],b[1],b[2],b[3]} :
scanline == 3'd2 ? {c[0],c[1],c[2],c[3]} :
scanline == 3'd3 ? {d[0],d[1],d[2],d[3]} :
scanline == 3'd4 ? {e[0],e[1],e[2],e[3]} : 4'b0000;
endmodule
module counter_mod8(c, r, q, cout);
input c, r;
output [2:0] q;
output reg cout;
reg[2:0] ctval;
assign q = ctval;
always @(posedge c or posedge r)
if (r)
{cout, ctval} <= 0;
else
{cout,ctval} <= ctval + 1'b1;
endmodule
module counter_mod4(c, r, q, cout);
input c, r;
output reg[1:0] q;
output reg cout;
always @(posedge c)
if (r)
{cout, q} <= 0;
else
{cout, q} <= q + 1'b1;
endmodule
// $Id: scores2.v,v 1.9 2007/08/27 22:14:51 svo Exp $
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V |
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 7921edb2cddbc3b048c85c03554d299ad3111bec
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_WFI 2'b10
`define EnvCtrlEnum_binary_sequential_ECALL 2'b11
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [1:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [1:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [1:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [1:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [1:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [1:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [0:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[23 : 20] = 4'b1000;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 2'b11);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 1'b1));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 3],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 1'b0;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 1'b1);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 1'b0;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [1:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [8:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [8:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [8:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [9:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [0:0] loader_counter_valueNext;
reg [0:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:511];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 9'bxxxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 3];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 9'bxxxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[8:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 3];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 3],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[9]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[9]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[2 : 0] = 3'b000;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = stageB_request_size;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 2'b11;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 1'b1);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + loader_counter_willIncrement);
if(loader_counter_willClear) begin
loader_counter_valueNext = 1'b0;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 10'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 1'b0;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 10'h001);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 10'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [22:0] _zz_ways_0_tags_port1;
wire [22:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:511];
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 7'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
// Top module connecting all the other modules
//`include "verilog/mips_instr_defines.v"
module top
(
input wire clk,
input wire reset
);
wire[31:0] instr_top;
wire wr_en_imem_top;
wire[31:0] curr_pc_top;
wire[31:0] next_pc_top;
wire[31:0] next_seq_pc_top;
wire[31:0] next_beq_pc_top;
wire next_seq_pc_carry_top;
wire next_beq_pc_carry_top;
wire[31:0] next_brn_eq_pc_top;
wire[31:0] next_jmp_pc_top;
wire[31:0] wr_instr_imem_top;
wire[4:0] rt_top;
wire[4:0] rs_top;
wire[4:0] rd_top;
wire[4:0] rs_dec_top;
wire[4:0] rd_dec_top;
wire[5:0] op_top;
wire[5:0] funct_top;
wire[4:0] shamt_top;
wire[25:0] target_top;
wire[31:0] sign_imm_top;
wire is_r_type_top;
wire is_i_type_top;
wire is_j_type_top;
wire use_link_reg_top;
wire reg_src_top;
wire reg_dst_top;
wire jump_top;
wire branch_top;
wire mem_read_top;
wire mem_to_reg_top;
wire[5:0] alu_op_top;
wire mem_wr_top;
wire[2:0] alu_src_top;
wire reg_wr_top;
wire sign_ext_top;
wire[31:0] r_data_p1_top;
wire[31:0] r_data_p2_top;
wire[31:0] r_data_p2_rf_top;
wire[31:0] res_alu_top;
wire z_top;
wire n_top;
wire v_pc_top;
wire v_branch_top;
wire[31:0] read_data_dmem_ram_top;
wire[31:0] wr_data_rf_top;
pc_reg PC (
.clk (clk),
.reset (reset),
.next_pc_pc_reg_i (next_pc_top),
.next_pc_pc_reg_o (curr_pc_top)
);
adder ADD1 (
.op1 (curr_pc_top),
.op2 (32'h4),
.cin (1'b0),
.sum (next_seq_pc_top),
.carry (next_seq_pc_carry_top),
.v_flag (v_pc_top)
);
adder ADD2 (
.op1 (next_seq_pc_top),
.op2 (sign_imm_top << 2),
.cin (1'b0),
.sum (next_beq_pc_top),
.carry (next_beq_pc_carry_top),
.v_flag (v_branch_top)
);
assign next_brn_eq_pc_top = (branch_top & ((op_top == `BEQ)) & z_top) |
(branch_top & ((op_top == `BVAR) & ((rt_top == `BGEZ)|
(rt_top == `BGEZAL))) & (~n_top | z_top)) |
(branch_top & ((op_top == `BLEZ)) & (n_top | z_top)) |
(branch_top & ((op_top == `BGTZ)) & ~(n_top | z_top)) |
(branch_top & ((op_top == `BVAR) & ((rt_top == `BLTZ) |
(rt_top == `BLTZAL))) & (n_top & ~z_top))|
(branch_top & ((op_top == `BNE)) & ~z_top) ? next_beq_pc_top : next_seq_pc_top;
assign next_jmp_pc_top = {next_seq_pc_top[31:28], instr_top[25:0] << 2};
assign next_pc_top = jump_top ? next_jmp_pc_top : next_brn_eq_pc_top;
instr_mem I_MEM1 (
.clk (clk),
.addr_imem_ram_i (curr_pc_top),
.wr_instr_imem_ram_i (wr_instr_imem_top),
.wr_en_imem_ram_i (wr_en_imem_top),
.read_instr_imem_ram_o (instr_top)
);
decode D1 (
.instr_dec_i (instr_top),
.sign_ext_i (sign_ext_top),
.rt_dec_o (rt_top),
.rs_dec_o (rs_dec_top),
.rd_dec_o (rd_dec_top),
.op_dec_o (op_top),
.funct_dec_o (funct_top),
.shamt_dec_o (shamt_top),
.target_dec_o (target_top),
.sign_imm_dec_o (sign_imm_top),
.is_r_type_dec_o (is_r_type_top),
.is_i_type_dec_o (is_i_type_top),
.is_j_type_dec_o (is_j_type_top),
.use_link_reg_dec_o (use_link_reg_top)
);
assign rd_top = (use_link_reg_top) ? 5'h1F :
(reg_dst_top ? rd_dec_top : rt_top);
assign rs_top = reg_src_top ? rt_top : rs_dec_top;
regfile R1 (
.clk (clk),
.reset (reset),
.w_en_rf_i (reg_wr_top | use_link_reg_top),
.w_data_rf_i (wr_data_rf_top),
.w_reg_rf_i (rd_top),
.r_reg_p1_rf_i (rs_top),
.r_reg_p2_rf_i (rt_top),
.r_data_p1_rf_o (r_data_p1_top),
.r_data_p2_rf_o (r_data_p2_rf_top)
);
assign r_data_p2_top = alu_src_top[2] ? 32'h0 :
alu_src_top[1] ? {{27{1'b0}}, shamt_top} :
alu_src_top[0] ? sign_imm_top : r_data_p2_rf_top;
alu A1 (
.opr_a_alu_i (r_data_p1_top),
.opr_b_alu_i (r_data_p2_top),
.op_alu_i (alu_op_top),
.res_alu_o (res_alu_top),
.z_alu_o (z_top),
.n_alu_o (n_top)
);
data_mem D_MEM1 (
.clk (clk),
.addr_dmem_ram_i (res_alu_top),
.wr_data_dmem_ram_i (r_data_p2_rf_top),
.wr_strb_dmem_ram_i (4'hF),
.wr_en_dmem_ram_i (mem_wr_top),
.read_data_dmem_ram_o (read_data_dmem_ram_top)
);
assign wr_data_rf_top = (use_link_reg_top) ? (next_seq_pc_top) :
(|rd_top) ? (mem_to_reg_top ? read_data_dmem_ram_top :
res_alu_top) :
32'h0;
control C1 (
.instr_op_ctl_i (op_top),
.instr_funct_ctl_i (funct_top),
.reg_src_ctl_o (reg_src_top),
.reg_dst_ctl_o (reg_dst_top),
.jump_ctl_o (jump_top),
.branch_ctl_o (branch_top),
.mem_read_ctl_o (mem_read_top),
.mem_to_reg_ctl_o (mem_to_reg_top),
.alu_op_ctl_o (alu_op_top),
.mem_wr_ctl_o (mem_wr_top),
.alu_src_ctl_o (alu_src_top),
.reg_wr_ctl_o (reg_wr_top),
.sign_ext_ctl_o (sign_ext_top)
);
endmodule
|
/**
* bsg_nonsynth_cache_axe_tracer.v
*
* use SystemVerilog 'bind' on bsg_cache.
*
*
* @author tommy
*
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_nonsynth_cache_axe_tracer
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter sbuf_entry_width_lp=`bsg_cache_sbuf_entry_width(addr_width_p,data_width_p,ways_p)
)
(
input clk_i
, input v_o
, input yumi_i
, input bsg_cache_decode_s decode_v_r
, input [addr_width_p-1:0] addr_v_r
, input [sbuf_entry_width_lp-1:0] sbuf_entry_li
, input [data_width_p-1:0] data_o
);
`declare_bsg_cache_sbuf_entry_s(addr_width_p, data_width_p, ways_p);
bsg_cache_sbuf_entry_s sbuf_entry;
assign sbuf_entry = sbuf_entry_li;
// synopsys translate_off
localparam logfile_lp = "bsg_cache.axe";
integer fd;
string header;
initial forever begin
@(negedge clk_i) begin
if (v_o & yumi_i) begin
if (decode_v_r.st_op) begin
fd = $fopen(logfile_lp, "a");
$fwrite(fd, "0: M[%0d] := %0d\n", addr_v_r>>2, sbuf_entry.data);
$fclose(fd);
end
if (decode_v_r.ld_op) begin
fd = $fopen(logfile_lp, "a");
$fwrite(fd, "0: M[%0d] == %0d\n", addr_v_r>>2, data_o);
$fclose(fd);
end
end
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_cache_axe_tracer)
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module LEDSample(
clk,
rst_x,
o_a,
o_b,
o_c,
o_d,
o_e,
o_f,
o_g,
o_dp);
input clk;
input rst_x;
output o_a;
output o_b;
output o_c;
output o_d;
output o_e;
output o_f;
output o_g;
output o_dp;
reg [4:0] r_count;
assign o_dp = r_count[0] & rst_x;
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_count <= 5'h00;
end else begin
r_count <= r_count + 5'h01;
end
end // always
SevenSegmentLED led(
.i_data(r_count[4:1]),
.o_a (o_a ),
.o_b (o_b ),
.o_c (o_c ),
.o_d (o_d ),
.o_e (o_e ),
.o_f (o_f ),
.o_g (o_g ));
endmodule // LEDSample
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_1_V
`define SKY130_FD_SC_LS__TAPVGND2_1_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog wrapper for tapvgnd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgnd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapvgnd2 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_1_V
|
/*
* SuperStack
*
* (c) 2017 - Jesús Leganés-Combarro 'piranna' <[email protected]>
*
* Based on https://github.com/whitequark/bfcpu2/blob/master/verilog/Stack.v
*/
`include "SuperStack.vh"
`default_nettype none
module SuperStack
#(
parameter WIDTH = 8, // bits
parameter DEPTH = 3, // frames (exponential)
parameter ZEROED_SLICES = 0
)
(
input clk,
input reset,
input [ 2:0] op, // none / push / pop / replace /
// index_reset / index_push /
// underflow_get / underflow_set
input [WIDTH-1:0] data, // Data to be inserted on the stack
input [DEPTH :0] offset, // position of getter/setter/new index
input [DEPTH :0] underflow_limit, // Depth of underflow error
input [DEPTH :0] upper_limit, // Underflow get/set upper limit
input [DEPTH :0] lower_limit, // Underflow get/set lower limit
input dropTos,
output reg [DEPTH :0] index = 0, // Current top of stack position
output [WIDTH-1:0] out, // top of stack
output [WIDTH-1:0] out1,
output [WIDTH-1:0] out2,
output reg [WIDTH-1:0] getter, // Output of getter
output reg [1:0] status = `EMPTY, // none / empty / full / underflow
output reg [1:0] error = `NONE // none / underflow / overflow
);
localparam MAX_STACK = (1 << DEPTH+1) - 1;
reg [WIDTH-1:0] stack [0:MAX_STACK-1];
assign out = stack[index-1];
assign out1 = stack[index-2];
assign out2 = stack[index-3];
// Adjust status when index or underflow limit or stack content has¡ve changed
always @* begin
if(index == MAX_STACK)
status <= `FULL;
else if(index == underflow_limit)
status <= `EMPTY;
else if(index < underflow_limit)
status <= `UNDERFLOW;
else
status <= `NONE;
end
/**
* Fill the stack slices with zeroes if new index is greater than current one
*/
task zeroedIndex;
reg [$clog2(DEPTH+1):0] i;
reg [ DEPTH :0] j;
reg [ DEPTH :0] o = 0;
reg [ DEPTH :0] slice;
// By disabling the filling of zeroes we improve performance more than twice
// (25-60 MHz) almost up to the regular stack (70 MHz). Alternatives would
// be to do the zeroed in parallel by preserving someway the base address
// for each group, or using a bitmap of the setted variables on each call
// slice, or do the zeroed in several cycles by using a requests queue.
if(ZEROED_SLICES && index < offset) begin
slice = offset - index;
for(i=0; i < DEPTH+1; i = i + 1)
if(slice[i])
for(j=0; j < 2**i; j = j + 1) begin
stack[index+o] = 0;
o = o + 1;
end
end
endtask
always @(posedge clk) begin
error <= `NONE;
if(reset)
index <= 0;
else
case(op)
`PUSH:
begin
// Stack is full
if (index == MAX_STACK)
error <= `OVERFLOW;
// Push data to ToS
else begin
stack[index] <= data;
index <= index + 1;
end
end
`POP:
begin
if (index-data <= underflow_limit)
error <= `UNDERFLOW;
else
index <= index - (1+data);
end
`REPLACE:
begin
if (index <= underflow_limit)
error <= `UNDERFLOW;
else
stack[index-1] <= data;
end
`INDEX_RESET:
begin
zeroedIndex();
index <= offset;
end
`INDEX_RESET_AND_PUSH:
begin
// New index is equal to MAX_STACK, raise error
if (offset == MAX_STACK)
error <= `OVERFLOW;
else begin
zeroedIndex();
stack[offset] <= data;
index <= offset+1;
end
end
`UNDERFLOW_GET:
begin
if (upper_limit - lower_limit <= offset)
error <= `BAD_OFFSET;
else
getter <= stack[lower_limit + offset];
end
`UNDERFLOW_SET:
begin
if (upper_limit - lower_limit <= offset)
error <= `BAD_OFFSET;
else if(dropTos && index == underflow_limit)
error <= `UNDERFLOW;
else begin
stack[lower_limit + offset] <= data;
if(dropTos) index <= index - 1;
end
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLXTN_BEHAVIORAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_no_pg/sky130_fd_sc_hs__u_dl_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtn (
VPWR ,
VGND ,
Q ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input D ;
input GATE_N;
// Local signals
wire gate buf_Q ;
wire gate GATE_N_delayed;
wire gate D_delayed ;
reg notifier ;
wire GATE ;
wire awake ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hs__u_dl_p_no_pg u_dl_p_no_pg0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_PP_V |
// megafunction wizard: %LPM_RAM_DP+%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_32x32_dp_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ram_32x32_dp_be (
data_a,
wren_a,
address_a,
data_b,
address_b,
wren_b,
byteena_a,
clock_a,
clock_b,
q_a,
q_b);
input [31:0] data_a;
input wren_a;
input [4:0] address_a;
input [31:0] data_b;
input [4:0] address_b;
input wren_b;
input [3:0] byteena_a;
input clock_a;
input clock_b;
output [31:0] q_a;
output [31:0] q_b;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL data_a[31..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL q_a[31..0]
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL q_b[31..0]
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL address_a[4..0]
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL data_b[31..0]
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL address_b[4..0]
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be_bb.v TRUE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:33:33 08/26/2015
// Design Name:
// Module Name: VerificadorSentidoMovimiento
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
*Módulo encargado de decidir el movimiendo y la dirección del ascensor mediante
*lógica combinacional entre el valor del registro de solicitudes y el piso actual.
*Tiene como entradas los 10 bits del registro de solicitudes y los 3 bits del código
*Grey identificador de cada piso y el clock. Tiene como salidas 2 bits que idicarán la
*habilitación del motor (MSB) 0=apagado, 1=activado y la dirección(LSB) 0=subir, 1=bajar .
*/
module VerificadorSentidoMovimiento(
_clk_,
FSM_ready_in,
piso_actual,
solicitud_ps,
solicitud_p1,
solicitud_p2,
solicitud_p3,
solicitud_p4,
accion,
clear_solicitud_ps,
clear_solicitud_p1,
clear_solicitud_p2,
clear_solicitud_p3,
clear_solicitud_p4
);
input [2:0] piso_actual;
input [1:0] solicitud_ps, solicitud_p1, solicitud_p2, solicitud_p3, solicitud_p4;
input _clk_, FSM_ready_in;
output reg [1:0] accion;
always @(posedge _clk_)
begin
//acciones para el sotano
if (piso_actual == 3'b000)
begin
if (solicitud_ps == 2'bx1) //No realiza accion
accion <= 2'b00;
if (solicitud_ps == 2'bx0)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_p1 == 2'bx0 | solicitud_p2 == 2'bx0 | solicitud_p3 == 2'bx0 | solicitud_p4 == 2'bx0)
accion <= 2'b10;
end
//acciones para el piso1
else if (piso_actual == 3'b001)
begin
if (solicitud_p1 == 2'bxx)
accion <= 01;
if (solicitud_ps == 2'bx1)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_p2 == 2'b1x)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_p3 == 2'b1x | solicitud_p4 == 2'b1x)
accion <= 2'b10;
else if (solicitud_p3 == 2'bx1 | solicitud_p4 == 2'bx1)
accion <= 2'b11;
end
//acciones para el piso2
else if (piso_actual == 3'b010)
begin
if (solicitud_p2 == 2'bxx)
accion <= 01;
if (solicitud_p1 == 2'bx1)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_p3 == 2'b1x)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_ps == 2'b1x | solicitud_p3 == 2'b1x)
accion <= 2'b10;
else if (solicitud_ps == 2'bx1 | solicitud_p3 == 2'bx1)
accion <= 2'b11;
end
//acciones para el piso3
else if (piso_actual == 3'b011)
begin
if (solicitud_p3 == 2'bxx)
accion <= 01;
if (solicitud_p2 == 2'bx1)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_p4 == 2'b1x)
begin
accion <= 2'b10;
accion <= 2'b01;
end
if (solicitud_ps == 2'b1x | solicitud_p1 == 2'b1x)
accion <= 2'b10;
else if (solicitud_ps == 2'bx1 | solicitud_p1 == 2'bx1)
accion <= 2'b11;
end
//acciones para el piso 4
else if (piso_actual == 3'b100)
begin
if (solicitud_p4 == 2'b1x) //No realiza accion
accion <= 2'b00;
if (solicitud_p4 == 2'b0x)
begin
accion <= 2'b11;
accion <= 2'b01;
end
if (solicitud_ps == 2'b0x | solicitud_p1 == 2'b0x | solicitud_p2 == 2'b0x | solicitud_p3 == 2'b0x)
accion <= 2'b11;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_TB_V
`define SKY130_FD_SC_MS__DFRTN_TB_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtn.v"
module top();
// Inputs are registered
reg D;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ms__dfrtn dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISO0N_SYMBOL_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_SYMBOL_V
|
/***********************************************************************
Single Port RAM that maps to a Xilinx/Lattice BRAM
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This is a program memory for the AVR. It maps to a Xilinx/Lattice
BRAM.
This version can be modified by the CPU (i. e. SPM instruction)
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the BSD license
------------------------------------------------------------------------------
Design unit: SinglePortPM(Xilinx) (Entity and architecture)
File name: pm_s_rw.in.v (template used)
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
Target FPGA: Spartan 3 (XC3S1500-4-FG456)
iCE40 (iCE40HX4K)
Language: Verilog
Wishbone: No
Synthesis tools: Xilinx Release 9.2.03i - xst J.39
iCEcube2.2016.02
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module lattuino_1_blPM_2
#(
parameter WORD_SIZE=16,// Word Size
parameter FALL_EDGE=0, // Ram clock falling edge
parameter ADDR_W=13 // Address Width
)
(
input clk_i,
input [ADDR_W-1:0] addr_i,
output [WORD_SIZE-1:0] data_o,
input we_i,
input [WORD_SIZE-1:0] data_i
);
localparam ROM_SIZE=2**ADDR_W;
reg [ADDR_W-1:0] addr_r;
reg [WORD_SIZE-1:0] rom[0:ROM_SIZE-1];
initial begin
$readmemh("../../../Work/lattuino_1_bl_2_v.dat",rom,696);
end
generate
if (!FALL_EDGE)
begin : use_rising_edge
always @(posedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_rising_edge
else
begin : use_falling_edge
always @(negedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_falling_edge
endgenerate
assign data_o=rom[addr_r];
endmodule // lattuino_1_blPM_2
|
// file: clk_wiz_v3_6_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_wiz_v3_6_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf
(.O (clk_in1_buf),
.I (CLK_IN1));
// Instantiation of the clocking network
//--------------------------------------
clk_wiz_v3_6 clknetwork
(// Clock in ports
.clk (clk_in1_buf),
// Clock out ports
.clk_20MHz (clk_int));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
/*
* ctu set mudule, implements a mathematical set data structure. it can
* store and retrieve elements in O(1). back 2 back read and write commands
* are allowed.
*
* Authur: Kimi - Sep 2010
*/
`ifndef _ctu
`define _ctu
`timescale 1ns/1ns
`include "../common_defines.v"
module ctu #(parameter data_wd = 11, // single entry width
max_len = 128, // maximal # for entries in CTU
add_wd = 7, // width of max_len field
hi = 10, // significant bits within CTU entry, other bits will not be
lo = 0 // taken into account when soring the entry in CTU
)
(
input wire clk,
input wire rst,
input wire [data_wd-1:0] EV_in, // input entry
output wire [data_wd-1:0] EV_out, // output entry
input wire rd, wr, // read write signals
input wire cs, // chip select signal
output wire full, empty,// ctu output indications
output wire [add_wd-1:0] length
);
wire ram_cs;
wire ram_rd;
wire ram_wr;
wire ram_wr_data;
wire ram_rd_data;
wire ram_rd_data_valid;
wire [`CTU_SET_LENGTH_WD-1:0] ram_rd_add;
wire [`CTU_SET_LENGTH_WD-1:0] ram_wr_add;
wire [data_wd-1:0] fifo_EV_out;
wire [data_wd-1:0] fifo_EV_in;
wire fifo_rd;
wire fifo_wr;
wire continues_write;
wire ctu_write_ena;
wire ctu_read_ena;
wire ctu_enter_new_entry;
wire ctu_continues_write;
wire ctu_first_write;
wire does_cell_exist_in_ram;
wire rd_wd_to_same_add;
wire enrty_is_missing_in_ram;
wire remove_entry_from_ram;
wire stage2_active_only;
reg delayed_wr;
reg sampled_rd_wd_to_same_add;
reg sampled_wr;
reg delayed_ctu_first_write;
reg [data_wd-1:0] delayed_EV_in;
// control logic
assign ctu_read_ena = (cs && rd && !empty);
assign ctu_write_ena = (cs && wr && !full);
assign ctu_first_write = ctu_write_ena && empty;
assign ctu_continues_write = ctu_write_ena && continues_write && !delayed_ctu_first_write;
assign ctu_enter_new_entry = ctu_first_write || stage2_active_only || (ctu_continues_write && enrty_is_missing_in_ram);
assign does_cell_exist_in_ram = ctu_write_ena && !empty;
assign rd_wd_to_same_add = ram_wr && ram_rd && (ram_rd_add == ram_wr_add);
assign enrty_is_missing_in_ram = (ram_rd_data_valid == `FALSE);
assign remove_entry_from_ram = ctu_read_ena;
assign fifo_rd = ctu_read_ena;
assign fifo_wr = ctu_enter_new_entry; // (C)
// when rd & wr data to same address assign TRUE to ram_rd_data_valid (work around)
assign ram_rd_data_valid = sampled_rd_wd_to_same_add ? `TRUE : ram_rd_data;
// ram control signals
assign ram_cs = remove_entry_from_ram || does_cell_exist_in_ram || ctu_enter_new_entry ;
assign ram_rd = does_cell_exist_in_ram;
assign ram_wr = remove_entry_from_ram || ctu_enter_new_entry ;
assign ram_wr_add = remove_entry_from_ram
? EV_out[hi:lo]
: ctu_first_write
? EV_in[hi:lo]
: ctu_enter_new_entry
? delayed_EV_in[hi:lo]
: {data_wd{1'b0}};
assign ram_wr_data = remove_entry_from_ram
? `FALSE
: ctu_enter_new_entry
? `TRUE
: `FALSE;
assign ram_rd_add = does_cell_exist_in_ram
? EV_in[hi:lo]
: {`CTU_SET_LENGTH_WD{1'b0}};
// sample EV_in
always @ (posedge clk) begin
if(rst) begin
delayed_EV_in <= #5 {data_wd{1'b0}};
end
else begin
delayed_EV_in <= #5 EV_in;
end
end
// stage2 control
assign stage2_active_only = sampled_wr && !wr && !delayed_ctu_first_write;
always @ (posedge clk) begin
if(rst)
sampled_wr <= #5 `FALSE;
else
sampled_wr <= #5 wr;
end
// delayed_ctu_first_write signal generation
always @ (posedge clk) begin
if(rst)
delayed_ctu_first_write <= #5 `FALSE;
else
delayed_ctu_first_write <= #5 ctu_first_write;
end
// continues_write control
assign continues_write = delayed_wr && wr;
always @ (posedge clk) begin
if(rst) begin
delayed_wr <= #5 `FALSE;
end
else begin
delayed_wr <= #5 wr;
end
end
// sample rd_wd_to_same_add signal
always @ (posedge clk) begin
if(rst) begin
sampled_rd_wd_to_same_add <= #5 `FALSE;
end
else begin
sampled_rd_wd_to_same_add <= #5 rd_wd_to_same_add;
end
end
// muxing fifo I/O signal
assign fifo_EV_in = ctu_first_write ? EV_in : delayed_EV_in;
assign EV_out = empty ? {data_wd{1'b0}} : fifo_EV_out ;
my_fifo #(.max_len(max_len), .len_wd(add_wd), .entry_wd(data_wd))
fifo(
.clk(clk),
.rst(rst),
.rd(fifo_rd),
.wr(fifo_wr),
.data_in(fifo_EV_in), // input entry
.full(full),
.empty(empty), // fifo status indicators
.data_out(fifo_EV_out), // output entry
.len(length)
);
// ram is used to implement mathematical set
dp_ram #(.add_wd(`CTU_SET_LENGTH_WD), .data_wd(1), .depth(`CTU_SET_LENGTH))
ram(
.clk(clk),
.cs(ram_cs),
.rd(ram_rd),
.wr(ram_wr),
.rd_add(ram_rd_add),
.wr_add(ram_wr_add),
.wr_data(ram_wr_data),
.rd_data(ram_rd_data)
);
endmodule
`endif |
/*------------------------------------------------------------------------------
Purpose
Decode instruction.
------------------------------------------------------------------------------*/
module mips_instr_decoder #(parameter ADDR_EXCEPT=32'h8000_0000)
(
input pl_cause_bd,
output pl_stall_mem,
output pl_stall_branch,
output pl_stall_multdiv,
output pl_stall_eret,
input[5:0] ifield_fstage_opcode,
input[4:0] ifield_fstage_d,
input[4:0] ifield_fstage_t,
input[4:0] ifield_fstage_s,
input[4:0] ifield_fstage_shift,
input[5:0] ifield_fstage_func,
input alu_multdiv_ready,
input[31:0] alu_quotient,
input[31:0] alu_remainder,
input[63:0] alu_product,
input[31:0] alu_result,
output reg[2:0] alu_mode,
output reg alu_mode_acompl,
output reg alu_mode_bcompl,
output reg alu_mode_rinv_l,
output reg alu_mode_div,
output reg alu_mode_mult,
output reg[31:0] alu_a,
output reg[31:0] alu_b,
input signed[31:0] greg_rdata_s,
input[31:0] greg_rdata_t,
output reg[31:0] greg_wdata_dt,
output reg[4:0] greg_waddr_dt,
output reg greg_wen_dt,
input[31:0] hlreg_rdata_h,
input[31:0] hlreg_rdata_l,
output reg[1:0] hlreg_wen,
output reg[31:0] hlreg_wdata_h,
output reg[31:0] hlreg_wdata_l,
input[31:2] pcreg_crntcmd,
input[31:2] pcreg_nextcmd,
output reg pcreg_wen,
output reg[31:2] pcreg_wdata,
input dmem_stall_i,
input dmem_ack_i,
input dmem_rreq_1,
input dmem_rmemdir_0,
input[4:0] dmem_rgregbusy_queued,
input[4:0] dmem_rgregbusy,
input[5:0] dmem_rloadinstr,
input[1:0] dmem_rbytesel,
input[31:0] dmem_rdata,
output reg dmem_wen,
output reg[31:2] dmem_waddr,
output reg[31:0] dmem_wdata,
output reg[3:0] dmem_wbytesel,
output reg dmem_wrw,
output reg exception,
input cop0_exl,
input cop0_int,
input[31:2] cop0_epc,
input[31:0] cop0_rdata,
output reg[4:0] cop0_waddr,
output reg cop0_wen,
output reg[31:0] cop0_wdata,
output reg cop0_cause_wen,
output reg[3:0] cop0_cause_excode,
output reg cop0_exl_set,
output reg cop0_exl_reset,
output reg cop0_badvaddr_wren
);
localparam OP_RTYPE= 6'b000000;
//PC CHANGE
localparam OP_BLTZ_BGEZ= 6'b000001;
localparam OP_J= 6'b000010;
localparam OP_JAL= 6'b000011;
localparam OP_BEQ= 6'b000100;
localparam OP_BNE= 6'b000101;
localparam OP_BLEZ= 6'b000110;
localparam OP_BGTZ= 6'b000111;
localparam FUNC_JR= 6'b001000;
localparam FUNC_JALR= 6'b001001;
//MEMORY R/W
localparam OP_LB= 6'b100000;
localparam OP_LH= 6'b100001;
localparam OP_LW= 6'b100011;
localparam OP_LBU= 6'b100100;
localparam OP_LHU= 6'b100101;
localparam OP_SB= 6'b101000;
localparam OP_SH= 6'b101001;
localparam OP_SW= 6'b101011;
//ALU
localparam FUNC_SLL= 6'b000000;
localparam FUNC_SRL= 6'b000010;
localparam FUNC_SRA= 6'b000011;
localparam FUNC_SLLV= 6'b000100;
localparam FUNC_SRLV= 6'b000110;
localparam FUNC_SRAV= 6'b000111;
localparam FUNC_MULT= 6'b011000;
localparam FUNC_MULTU= 6'b011001;
localparam FUNC_DIV= 6'b011010;
localparam FUNC_DIVU= 6'b011011;
localparam FUNC_MFHI= 6'b010000;
localparam FUNC_MTHI= 6'b010001;
localparam FUNC_MFLO= 6'b010010;
localparam FUNC_MTLO= 6'b010011;
localparam FUNC_ADD= 6'b100000;
localparam FUNC_ADDU= 6'b100001;
localparam FUNC_SUB= 6'b100010;
localparam FUNC_SUBU= 6'b100011;
localparam FUNC_AND= 6'b100100;
localparam FUNC_OR= 6'b100101;
localparam FUNC_XOR= 6'b100110;
localparam FUNC_NOR= 6'b100111;
localparam FUNC_SLT= 6'b101010;
localparam FUNC_SLTU= 6'b101011;
localparam OP_ADDI= 6'b001000;
localparam OP_ADDIU= 6'b001001;
localparam OP_SLTI= 6'b001010;
localparam OP_SLTIU= 6'b001011;
localparam OP_ANDI= 6'b001100;
localparam OP_ORI= 6'b001101;
localparam OP_XORI= 6'b001110;
localparam OP_LUI= 6'b001111;
//COP0
localparam OP_COP0= 6'b010000;
localparam MTC0= 5'b00100;
localparam MFC0= 5'b00000;
localparam ERET= {1'b1,19'd0,6'b011000};
wire[25:0] ifield_fstage_addr;
wire[15:0] ifield_fstage_imm;
wire[31:0] sign_imm;
wire[31:0] bta_offset;
wire instr_en;
wire instr_mem;
wire instr_nop;
wire pl_gregbusy_td;
wire pl_gregbusy_st;
wire pl_gregbusy_std;
wire pl_gregbusy_d;
wire pl_gregbusy_s;
wire pl_change_memdir;
wire pl_dmem_stall;
localparam ALUMODE_ADD= 3'd0;
localparam ALUMODE_SLL= 3'd1;
localparam ALUMODE_SRL= 3'd2;
localparam ALUMODE_SRA= 3'd3;
localparam ALUMODE_AND= 3'd4;
localparam ALUMODE_OR= 3'd5;
localparam ALUMODE_XOR= 3'd6;
localparam EXCODE_INT= 4'd0;
localparam EXCODE_ADEL= 4'd4;
localparam EXCODE_ADES= 4'd5;
localparam EXCODE_RI= 4'd10;
localparam EXCODE_OV= 4'd12;
/*------------------------------------------------------------------------------
MAIN INSTRUCTION DECODER
------------------------------------------------------------------------------*/
assign ifield_fstage_addr= {ifield_fstage_s,
ifield_fstage_t,
ifield_fstage_d,
ifield_fstage_shift,
ifield_fstage_func};
assign ifield_fstage_imm= {ifield_fstage_d,
ifield_fstage_shift,
ifield_fstage_func};
assign sign_imm= ifield_fstage_imm[15] ? {16'hFFFF,ifield_fstage_imm} :
{16'h0000,ifield_fstage_imm};
assign bta_offset= sign_imm<<2;
assign instr_en= !pl_stall_mem & !cop0_int;
assign instr_mem= (ifield_fstage_opcode==OP_LB |
ifield_fstage_opcode==OP_LH |
ifield_fstage_opcode==OP_LW |
ifield_fstage_opcode==OP_LBU |
ifield_fstage_opcode==OP_LHU |
ifield_fstage_opcode==OP_SB |
ifield_fstage_opcode==OP_SH |
ifield_fstage_opcode==OP_SW);
assign instr_nop= ifield_fstage_opcode==OP_RTYPE &
ifield_fstage_func==FUNC_SLL &
ifield_fstage_d==5'd0;
always @*
begin
alu_mode= ALUMODE_ADD;
alu_mode_acompl= 1'b0;
alu_mode_bcompl= 1'b0;
alu_mode_rinv_l= 1'b0;
alu_a= greg_rdata_s;
alu_b= greg_rdata_t;
alu_mode_div= 1'b0;
alu_mode_mult= 1'b0;
greg_waddr_dt= ifield_fstage_d;
greg_wen_dt= 1'b0;
greg_wdata_dt= alu_result[31:0];
hlreg_wen= 2'b00;
hlreg_wdata_h= alu_product[63:32];
hlreg_wdata_l= alu_product[31:0];
pcreg_wen= 1'b0;
pcreg_wdata= alu_result[31:2];
dmem_waddr= 30'd0;
dmem_wdata= 32'd0;
dmem_wbytesel= 4'b1111;
dmem_wrw= 1'b0;
dmem_wen= 1'b0;
exception= 1'b0;
cop0_waddr= ifield_fstage_d;
cop0_wen= 1'b0;
cop0_exl_set= 1'b0;
cop0_exl_reset= 1'b0;
cop0_wdata= greg_rdata_t;
cop0_cause_wen= 1'b0;
cop0_cause_excode= EXCODE_INT;
cop0_badvaddr_wren= 1'b0;
if(cop0_int) task_except_int(cop0_exl, pl_cause_bd, pcreg_crntcmd);
if((!instr_en | instr_mem | instr_nop) &
dmem_ack_i & !dmem_rmemdir_0) task_load_from_mem (dmem_rloadinstr,
dmem_rgregbusy,
dmem_rbytesel,
dmem_rdata);
case(ifield_fstage_opcode)
OP_RTYPE:
begin
case(ifield_fstage_func)
FUNC_SLL:
begin
alu_mode= ALUMODE_SLL;
alu_a[4:0]= ifield_fstage_shift;
if(instr_en & ifield_fstage_d!=5'd0) greg_wen_dt= 1'b1;
end
FUNC_SRL:
begin
alu_mode= ALUMODE_SRL;
alu_a[4:0]= ifield_fstage_shift;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_SRA:
begin
alu_mode= ALUMODE_SRA;
alu_a[4:0]= ifield_fstage_shift;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_SLLV:
begin
alu_mode= ALUMODE_SLL;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_SRLV:
begin
alu_mode= ALUMODE_SRL;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_SRAV:
begin
alu_mode= ALUMODE_SRA;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_JR:
begin
pcreg_wdata= greg_rdata_s[31:2];
if(instr_en) pcreg_wen= 1'b1;
end
FUNC_JALR:
begin
pcreg_wdata= greg_rdata_s[31:2];
if(instr_en)
begin
pcreg_wen= 1'b1;
greg_wen_dt= 1'b1;
greg_wdata_dt= {pcreg_crntcmd,2'd0};
end
end
FUNC_MULT:
begin
alu_mode_acompl= greg_rdata_s[31];
alu_mode_bcompl= greg_rdata_t[31];
if(instr_en)
begin
alu_mode_mult= 1'b1;
if(alu_multdiv_ready) hlreg_wen= 2'b11;
end
end
FUNC_MULTU:
begin
if(instr_en)
begin
alu_mode_mult= 1'b1;
if(alu_multdiv_ready) hlreg_wen= 2'b11;
end
end
FUNC_DIV:
begin
alu_mode_acompl= greg_rdata_s[31];
alu_mode_bcompl= greg_rdata_t[31];
hlreg_wdata_h= alu_remainder;
hlreg_wdata_l= alu_quotient;
if(instr_en)
begin
alu_mode_div= 1'b1;
if(alu_multdiv_ready) hlreg_wen= 2'b11;
end
end
FUNC_DIVU:
begin
hlreg_wdata_h= alu_remainder;
hlreg_wdata_l= alu_quotient;
if(instr_en)
begin
alu_mode_div= 1'b1;
if(alu_multdiv_ready) hlreg_wen= 2'b11;
end
end
FUNC_MFHI:
begin
if(instr_en)
begin
greg_wdata_dt= hlreg_rdata_h;
greg_wen_dt= 1'b1;
end
end
FUNC_MTHI:
begin
hlreg_wdata_h= greg_rdata_s;
if(instr_en) hlreg_wen= 2'b10;
end
FUNC_MFLO:
begin
if(instr_en)
begin
greg_wdata_dt= hlreg_rdata_l;
greg_wen_dt= 1'b1;
end
end
FUNC_MTLO:
begin
hlreg_wdata_l= greg_rdata_s;
if(instr_en) hlreg_wen= 2'b01;
end
FUNC_ADD:
begin
if(instr_en)
begin
if(greg_rdata_s[31]==greg_rdata_t[31] &
alu_result[31]!=greg_rdata_s[31]) task_except_ov(cop0_exl,
pl_cause_bd,
pcreg_crntcmd);
else greg_wen_dt= 1'b1;
end
end
FUNC_ADDU:
begin
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_SUB:
begin
alu_mode_bcompl= 1'b1;
if(instr_en)
begin
if(greg_rdata_s[31]==(~greg_rdata_t[31]) &
alu_result[31]!=greg_rdata_s[31]) task_except_ov(cop0_exl,
pl_cause_bd,
pcreg_crntcmd);
else greg_wen_dt= 1'b1;
end
end
FUNC_SUBU:
begin
alu_mode_bcompl= 1'b1;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_AND:
begin
alu_mode= ALUMODE_AND;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_OR:
begin
alu_mode= ALUMODE_OR;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_XOR:
begin
alu_mode=ALUMODE_XOR;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_NOR:
begin
alu_mode=ALUMODE_OR;
alu_mode_rinv_l= 1'b1;
if(instr_en) greg_wen_dt= 1'b1;
end
FUNC_SLT:
begin
alu_mode_acompl= greg_rdata_s[31];
alu_mode_bcompl= ~greg_rdata_t[31];
if(instr_en)
begin
greg_wdata_dt= (greg_rdata_s[31] & !greg_rdata_t[31]) |
(greg_rdata_s[31] & greg_rdata_t[31] &
!alu_result[31] & alu_result[31:0]!=0) |
(!greg_rdata_s[31] & !greg_rdata_t[31] &
alu_result[31]) ? 32'd1 : 32'd0;
greg_wen_dt= 1'b1;
end
end
FUNC_SLTU:
begin
alu_mode_acompl= greg_rdata_s[31];
alu_mode_bcompl= ~greg_rdata_t[31];
if(instr_en)
begin
greg_wdata_dt= (!greg_rdata_s[31] & greg_rdata_t[31]) |
(greg_rdata_s[31] & greg_rdata_t[31] &
!alu_result[31] & alu_result[31:0]!=0) |
(!greg_rdata_s[31] & !greg_rdata_t[31] &
alu_result[31]) ? 32'd1 : 32'd0;
greg_wen_dt= 1'b1;
end
end
default: if(instr_en) task_except_ri(cop0_exl, pl_cause_bd, pcreg_crntcmd);
endcase
end
OP_BLTZ_BGEZ:
begin
alu_a= {pcreg_nextcmd,2'd0};
alu_b= bta_offset;
if(instr_en &
((ifield_fstage_t==5'd0 & greg_rdata_s<32'sd0) |
(ifield_fstage_t==5'd1 & greg_rdata_s>=32'sd0)))
pcreg_wen= 1'b1;
end
OP_J:
begin
pcreg_wdata= {pcreg_crntcmd[31:28], ifield_fstage_addr};
if(instr_en) pcreg_wen= 1'b1;
end
OP_JAL:
begin
pcreg_wdata= {pcreg_crntcmd[31:28], ifield_fstage_addr};
if(instr_en)
begin
pcreg_wen= 1'b1;
greg_waddr_dt= 5'd31;
greg_wdata_dt= {pcreg_crntcmd,2'd0};
greg_wen_dt= 1'b1;
end
end
OP_BEQ:
begin
alu_a= {pcreg_nextcmd,2'd0};
alu_b= bta_offset;
if(instr_en & greg_rdata_s==greg_rdata_t) pcreg_wen= 1'b1;
end
OP_BNE:
begin
alu_a= {pcreg_nextcmd,2'd0};
alu_b= bta_offset;
if(instr_en & greg_rdata_s!=greg_rdata_t) pcreg_wen= 1'b1;
end
OP_BLEZ:
begin
alu_a= {pcreg_nextcmd,2'd0};
alu_b= bta_offset;
if(instr_en & greg_rdata_s<=32'sd0) pcreg_wen= 1'b1;
end
OP_BGTZ:
begin
alu_a= {pcreg_nextcmd,2'd0};
alu_b= bta_offset;
if(instr_en & greg_rdata_s>32'sd0) pcreg_wen= 1'b1;
end
OP_ADDI:
begin
alu_b= sign_imm;
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
if(greg_rdata_s[31]==sign_imm[31] &
alu_result[31]!=greg_rdata_s[31]) task_except_ov(cop0_exl,
pl_cause_bd,
pcreg_crntcmd);
else greg_wen_dt= 1'b1;
end
end
OP_ADDIU:
begin
alu_b= sign_imm;
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wen_dt= 1'b1;
end
end
OP_SLTI:
begin
alu_b= sign_imm;
alu_mode_acompl= greg_rdata_s[31];
alu_mode_bcompl= ~sign_imm[31];
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wdata_dt= (greg_rdata_s[31] & !sign_imm[31]) |
(greg_rdata_s[31] & sign_imm[31] &
!alu_result[31] & alu_result[31:0]!=32'd0) |
(!greg_rdata_s[31] & !sign_imm[31] &
alu_result[31]) ? 32'd1 : 32'd0;
greg_wen_dt= 1'b1;
end
end
OP_SLTIU:
begin
alu_b= sign_imm;
alu_mode_acompl= greg_rdata_s[31];
alu_mode_bcompl= ~sign_imm[31];
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wdata_dt= (!greg_rdata_s[31] & sign_imm[31]) |
(greg_rdata_s[31] & sign_imm[31] &
!alu_result[31] & alu_result[31:0]!=32'd0) |
(!greg_rdata_s[31] & !sign_imm[31] &
alu_result[31]) ? 32'd1 : 32'd0;
greg_wen_dt= 1'b1;
end
end
OP_ANDI:
begin
alu_mode= ALUMODE_AND;
alu_b= {16'd0,ifield_fstage_imm};
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wen_dt= 1'b1;
end
end
OP_ORI:
begin
alu_mode= ALUMODE_OR;
alu_b= {16'd0,ifield_fstage_imm};
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wen_dt= 1'b1;
end
end
OP_XORI:
begin
alu_mode= ALUMODE_XOR;
alu_b= {16'd0,ifield_fstage_imm};
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wen_dt= 1'b1;
end
end
OP_LUI:
begin
if(instr_en)
begin
greg_waddr_dt= ifield_fstage_t;
greg_wdata_dt= {ifield_fstage_imm,16'd0};
greg_wen_dt= 1'b1;
end
end
OP_COP0:
begin
if(instr_en)
begin
if(ifield_fstage_addr==ERET)
begin
pcreg_wen= 1'b1;
pcreg_wdata= cop0_epc[31:2];
cop0_exl_reset= 1'b1;
end
else case(ifield_fstage_s)
MTC0: cop0_wen= 1'b1;
MFC0:
begin
greg_waddr_dt= ifield_fstage_t;
greg_wen_dt= 1'b1;
greg_wdata_dt= cop0_rdata;
end
default: task_except_ri(cop0_exl, pl_cause_bd, pcreg_crntcmd);
endcase
end
end
OP_LB:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
if(instr_en) dmem_wen= 1'b1;
end
OP_LH:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
if(instr_en)
begin
if(alu_result[0]) task_except_adel(cop0_exl, pl_cause_bd, pcreg_crntcmd);
else dmem_wen= 1'b1;
end
end
OP_LW:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
if(instr_en)
begin
if(alu_result[1:0]!=2'b00) task_except_adel(cop0_exl,
pl_cause_bd,
pcreg_crntcmd);
else dmem_wen= 1'b1;
end
end
OP_LBU:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
if(instr_en) dmem_wen= 1'b1;
end
OP_LHU:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
if(instr_en)
begin
if(alu_result[0]) task_except_adel(cop0_exl, pl_cause_bd, pcreg_crntcmd);
else dmem_wen= 1'b1;
end
end
OP_SB:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
dmem_wrw= 1'b1;
if(instr_en)
begin
dmem_wen= 1'b1;
case(alu_result[1:0])
2'b00:
begin
dmem_wbytesel=4'b0001;
dmem_wdata[7:0]=greg_rdata_t[7:0];
end
2'b01:
begin
dmem_wbytesel=4'b0010;
dmem_wdata[15:8]=greg_rdata_t[7:0];
end
2'b10:
begin
dmem_wbytesel=4'b0100;
dmem_wdata[23:16]=greg_rdata_t[7:0];
end
2'b11:
begin
dmem_wbytesel=4'b1000;
dmem_wdata[31:24]=greg_rdata_t[7:0];
end
endcase
end
end
OP_SH:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
dmem_wrw= 1'b1;
if(instr_en)
begin
if(!alu_result[0])
begin
dmem_wen= 1'b1;
case(alu_result[1])
2'b0:
begin
dmem_wbytesel= 4'b0011;
dmem_wdata[15:0]= greg_rdata_t[15:0];
end
2'b1:
begin
dmem_wbytesel= 4'b1100;
dmem_wdata[31:16]= greg_rdata_t[15:0];
end
endcase
end
else task_except_ades(cop0_exl, pl_cause_bd, pcreg_crntcmd);
end
end
OP_SW:
begin
alu_b= sign_imm;
dmem_waddr= alu_result[31:2];
dmem_wrw= 1'b1;
if(instr_en)
begin
if(alu_result[1:0]==2'b00)
begin
dmem_wen= 1'b1;
dmem_wbytesel= 4'b1111;
dmem_wdata= greg_rdata_t;
end
else task_except_ades(cop0_exl, pl_cause_bd, pcreg_crntcmd);
end
end
default: if(instr_en) task_except_ri(cop0_exl, pl_cause_bd, pcreg_crntcmd);
endcase
end
task task_except_int(input cop0_exl,
input pl_cause_bd,
input[31:0] pcreg_crntcmd);
begin
if(!cop0_exl)
begin
cop0_cause_wen= 1'b1;
cop0_waddr= 5'd14;
cop0_wen= 1'b1;
cop0_exl_set= 1'b1;
if(!pl_cause_bd) cop0_wdata= {pcreg_crntcmd,2'd0};
else cop0_wdata= {pcreg_crntcmd-30'd1,2'd0};
end
exception= 1'b1;
pcreg_wen= 1'b1;
pcreg_wdata= ADDR_EXCEPT[31:2];
end
endtask
task task_except_ov(input cop0_exl,
input pl_cause_bd,
input[31:0] pcreg_crntcmd);
begin
if(!cop0_exl)
begin
cop0_cause_wen= 1'b1;
cop0_cause_excode= EXCODE_OV;
cop0_waddr= 5'd14;
cop0_wen= 1'b1;
cop0_exl_set= 1'b1;
if(!pl_cause_bd) cop0_wdata= {pcreg_crntcmd,2'd0};
else cop0_wdata= {pcreg_crntcmd-30'd1,2'd0};
end
exception= 1'b1;
pcreg_wen= 1'b1;
pcreg_wdata= ADDR_EXCEPT[31:2];
end
endtask
task task_except_ri(input cop0_exl,
input pl_cause_bd,
input[31:0] pcreg_crntcmd);
begin
if(!cop0_exl)
begin
cop0_cause_wen= 1'b1;
cop0_cause_excode= EXCODE_RI;
cop0_waddr= 5'd14;
cop0_wen= 1'b1;
cop0_exl_set= 1'b1;
if(!pl_cause_bd) cop0_wdata= {pcreg_crntcmd,2'd0};
else cop0_wdata= {pcreg_crntcmd-30'd1,2'd0};
end
exception= 1'b1;
pcreg_wen= 1'b1;
pcreg_wdata= ADDR_EXCEPT[31:2];
end
endtask
task task_except_adel(input cop0_exl,
input pl_cause_bd,
input[31:0] pcreg_crntcmd);
begin
if(!cop0_exl)
begin
cop0_cause_wen= 1'b1;
cop0_cause_excode= EXCODE_ADEL;
cop0_waddr= 5'd14;
cop0_wen= 1'b1;
cop0_exl_set= 1'b1;
if(!pl_cause_bd) cop0_wdata= {pcreg_crntcmd,2'd0};
else cop0_wdata= {pcreg_crntcmd-30'd1,2'd0};
cop0_badvaddr_wren= 1'b1;
end
exception= 1'b1;
pcreg_wen= 1'b1;
pcreg_wdata= ADDR_EXCEPT[31:2];
end
endtask
task task_except_ades(input cop0_exl,
input pl_cause_bd,
input[31:0] pcreg_crntcmd);
begin
if(!cop0_exl)
begin
cop0_cause_wen= 1'b1;
cop0_cause_excode= EXCODE_ADES;
cop0_waddr= 5'd14;
cop0_wen= 1'b1;
cop0_exl_set= 1'b1;
if(!pl_cause_bd) cop0_wdata= {pcreg_crntcmd,2'd0};
else cop0_wdata= {pcreg_crntcmd-30'd1,2'd0};
cop0_badvaddr_wren= 1'b1;
end
exception= 1'b1;
pcreg_wen= 1'b1;
pcreg_wdata= ADDR_EXCEPT[31:2];
end
endtask
task task_load_from_mem(input[5:0] dmem_rloadinstr,
input[4:0] dmem_rgregbusy,
input[1:0] dmem_rbytesel,
input[31:0] dmem_rdata);
begin
case(dmem_rloadinstr)
OP_LB:
begin
greg_waddr_dt=dmem_rgregbusy;
greg_wen_dt=1'b1;
case(dmem_rbytesel)
2'b00:greg_wdata_dt={{24{dmem_rdata[7]}},dmem_rdata[7:0]};
2'b01:greg_wdata_dt={{24{dmem_rdata[15]}},dmem_rdata[15:8]};
2'b10:greg_wdata_dt={{24{dmem_rdata[23]}},dmem_rdata[23:16]};
2'b11:greg_wdata_dt={{24{dmem_rdata[31]}},dmem_rdata[31:24]};
endcase
end
OP_LH:
begin
greg_waddr_dt=dmem_rgregbusy;
greg_wen_dt=1'b1;
case(dmem_rbytesel[1])
2'b0:greg_wdata_dt={{16{dmem_rdata[15]}},dmem_rdata[15:0]};
2'b1:greg_wdata_dt={{24{dmem_rdata[31]}},dmem_rdata[31:16]};
endcase
end
OP_LW:
begin
greg_waddr_dt=dmem_rgregbusy;
greg_wen_dt=1'b1;
greg_wdata_dt=dmem_rdata;
end
OP_LBU:
begin
greg_waddr_dt=dmem_rgregbusy;
greg_wen_dt=1'b1;
case(dmem_rbytesel)
2'b00:greg_wdata_dt={{24{1'b0}},dmem_rdata[7:0]};
2'b01:greg_wdata_dt={{24{1'b0}},dmem_rdata[15:8]};
2'b10:greg_wdata_dt={{24{1'b0}},dmem_rdata[23:16]};
2'b11:greg_wdata_dt={{24{1'b0}},dmem_rdata[31:24]};
endcase
end
OP_LHU:
begin
greg_waddr_dt=dmem_rgregbusy;
greg_wen_dt=1'b1;
case(dmem_rbytesel[1])
2'b0:greg_wdata_dt={{16{1'b0}},dmem_rdata[15:0]};
2'b1:greg_wdata_dt={{24{1'b0}},dmem_rdata[31:16]};
endcase
end
endcase
end
endtask
/*------------------------------------------------------------------------------
PIPELINE STALL LOGIC
------------------------------------------------------------------------------*/
assign pl_gregbusy_td= ((dmem_rgregbusy!=5'd0 &
(dmem_rgregbusy==ifield_fstage_t |
dmem_rgregbusy==ifield_fstage_d)) |
(dmem_rgregbusy_queued!=5'd0 &
(dmem_rgregbusy_queued==ifield_fstage_t |
dmem_rgregbusy_queued==ifield_fstage_d))) &
ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_SLL |
ifield_fstage_func==FUNC_SRL |
ifield_fstage_func==FUNC_SRA);
assign pl_gregbusy_std= ((dmem_rgregbusy!=5'd0 &
(dmem_rgregbusy==ifield_fstage_t |
dmem_rgregbusy==ifield_fstage_s |
dmem_rgregbusy==ifield_fstage_d)) |
(dmem_rgregbusy_queued!=5'd0 &
(dmem_rgregbusy_queued==ifield_fstage_t |
dmem_rgregbusy_queued==ifield_fstage_s |
dmem_rgregbusy_queued==ifield_fstage_d))) &
ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_SLLV |
ifield_fstage_func==FUNC_SRLV |
ifield_fstage_func==FUNC_SRAV |
ifield_fstage_func==FUNC_ADD |
ifield_fstage_func==FUNC_ADDU |
ifield_fstage_func==FUNC_SUB |
ifield_fstage_func==FUNC_SUBU |
ifield_fstage_func==FUNC_AND |
ifield_fstage_func==FUNC_OR |
ifield_fstage_func==FUNC_XOR |
ifield_fstage_func==FUNC_NOR |
ifield_fstage_func==FUNC_SLT |
ifield_fstage_func==FUNC_SLTU);
assign pl_gregbusy_st= ((dmem_rgregbusy!=5'd0 &
(dmem_rgregbusy==ifield_fstage_t |
dmem_rgregbusy==ifield_fstage_s)) |
(dmem_rgregbusy_queued!=5'd0 &
(dmem_rgregbusy_queued==ifield_fstage_t |
dmem_rgregbusy_queued==ifield_fstage_s))) &
((ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_MULT |
ifield_fstage_func==FUNC_MULTU |
ifield_fstage_func==FUNC_DIV |
ifield_fstage_func==FUNC_DIVU)) |
ifield_fstage_opcode==OP_ADDI |
ifield_fstage_opcode==OP_ADDIU |
ifield_fstage_opcode==OP_SLTI |
ifield_fstage_opcode==OP_SLTIU |
ifield_fstage_opcode==OP_ANDI |
ifield_fstage_opcode==OP_ORI |
ifield_fstage_opcode==OP_XORI |
ifield_fstage_opcode==OP_LUI |
ifield_fstage_opcode==OP_BEQ |
ifield_fstage_opcode==OP_BNE);
assign pl_gregbusy_d= ((dmem_rgregbusy!=5'd0 &
dmem_rgregbusy==ifield_fstage_d) |
(dmem_rgregbusy_queued!=5'd0 &
dmem_rgregbusy_queued==ifield_fstage_d)) &
ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_MFHI |
ifield_fstage_func==FUNC_MFLO);
assign pl_gregbusy_s= ((dmem_rgregbusy!=5'd0 &
dmem_rgregbusy==ifield_fstage_s) |
(dmem_rgregbusy_queued!=5'd0 &
dmem_rgregbusy_queued==ifield_fstage_s)) &
((ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_MTHI |
ifield_fstage_func==FUNC_MTLO)) |
ifield_fstage_opcode==OP_LB |
ifield_fstage_opcode==OP_LH |
ifield_fstage_opcode==OP_LW |
ifield_fstage_opcode==OP_LBU |
ifield_fstage_opcode==OP_LHU |
ifield_fstage_opcode==OP_BLTZ_BGEZ |
ifield_fstage_opcode==OP_BLEZ |
ifield_fstage_opcode==OP_BGTZ);
assign pl_dmem_stall= instr_mem & ((dmem_stall_i) |
(dmem_rreq_1 & !dmem_ack_i));
assign pl_stall_mem= (dmem_ack_i & !instr_mem & !instr_nop &
(dmem_rloadinstr==OP_LB |
dmem_rloadinstr==OP_LH |
dmem_rloadinstr==OP_LW |
dmem_rloadinstr==OP_LBU |
dmem_rloadinstr==OP_LHU)) |
pl_gregbusy_td |
pl_gregbusy_std |
pl_gregbusy_st |
pl_gregbusy_d |
pl_gregbusy_s |
pl_dmem_stall;
assign pl_stall_branch= (ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_JR |
ifield_fstage_func==FUNC_JALR)) |
(ifield_fstage_opcode==OP_BLTZ_BGEZ &
((ifield_fstage_t==5'd0 & greg_rdata_s<32'sd0) |
(ifield_fstage_t==5'd1 & greg_rdata_s>=32'sd0)))|
ifield_fstage_opcode==OP_J |
ifield_fstage_opcode==OP_JAL |
(ifield_fstage_opcode==OP_BEQ &
greg_rdata_s==greg_rdata_t) |
(ifield_fstage_opcode==OP_BNE &
greg_rdata_s!=greg_rdata_t) |
(ifield_fstage_opcode==OP_BLEZ &
greg_rdata_s<=32'sd0)|
(ifield_fstage_opcode==OP_BGTZ &
greg_rdata_s>32'sd0);
assign pl_stall_eret= ifield_fstage_opcode==OP_COP0 &
ifield_fstage_addr==ERET;
assign pl_stall_multdiv= ifield_fstage_opcode==OP_RTYPE &
(ifield_fstage_func==FUNC_MULT |
ifield_fstage_func==FUNC_MULTU |
ifield_fstage_func==FUNC_DIV |
ifield_fstage_func==FUNC_DIVU);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_PP_SYMBOL_V
`define SKY130_FD_SC_HD__PROBE_P_PP_SYMBOL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probe_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:42:53 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_1/system_auto_cc_1_sim_netlist.v
// Design : system_auto_cc_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_auto_cc_1,axi_clock_converter_v2_1_10_axi_clock_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_auto_cc_1
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [10:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [10:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *) input m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *) input m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [10:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [10:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire m_axi_aclk;
wire [10:0]m_axi_araddr;
wire m_axi_aresetn;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [10:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_axi_aclk;
wire [10:0]s_axi_araddr;
wire s_axi_aresetn;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire NLW_inst_s_axi_rlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_ARADDR_RIGHT = "3" *)
(* C_ARADDR_WIDTH = "11" *)
(* C_ARBURST_RIGHT = "3" *)
(* C_ARBURST_WIDTH = "0" *)
(* C_ARCACHE_RIGHT = "3" *)
(* C_ARCACHE_WIDTH = "0" *)
(* C_ARID_RIGHT = "14" *)
(* C_ARID_WIDTH = "0" *)
(* C_ARLEN_RIGHT = "3" *)
(* C_ARLEN_WIDTH = "0" *)
(* C_ARLOCK_RIGHT = "3" *)
(* C_ARLOCK_WIDTH = "0" *)
(* C_ARPROT_RIGHT = "0" *)
(* C_ARPROT_WIDTH = "3" *)
(* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "0" *)
(* C_ARREGION_RIGHT = "0" *)
(* C_ARREGION_WIDTH = "0" *)
(* C_ARSIZE_RIGHT = "3" *)
(* C_ARSIZE_WIDTH = "0" *)
(* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *)
(* C_AR_WIDTH = "14" *)
(* C_AWADDR_RIGHT = "3" *)
(* C_AWADDR_WIDTH = "11" *)
(* C_AWBURST_RIGHT = "3" *)
(* C_AWBURST_WIDTH = "0" *)
(* C_AWCACHE_RIGHT = "3" *)
(* C_AWCACHE_WIDTH = "0" *)
(* C_AWID_RIGHT = "14" *)
(* C_AWID_WIDTH = "0" *)
(* C_AWLEN_RIGHT = "3" *)
(* C_AWLEN_WIDTH = "0" *)
(* C_AWLOCK_RIGHT = "3" *)
(* C_AWLOCK_WIDTH = "0" *)
(* C_AWPROT_RIGHT = "0" *)
(* C_AWPROT_WIDTH = "3" *)
(* C_AWQOS_RIGHT = "0" *)
(* C_AWQOS_WIDTH = "0" *)
(* C_AWREGION_RIGHT = "0" *)
(* C_AWREGION_WIDTH = "0" *)
(* C_AWSIZE_RIGHT = "3" *)
(* C_AWSIZE_WIDTH = "0" *)
(* C_AWUSER_RIGHT = "0" *)
(* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "14" *)
(* C_AXI_ADDR_WIDTH = "11" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_IS_ACLK_ASYNC = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "0" *)
(* C_BRESP_RIGHT = "0" *)
(* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *)
(* C_BUSER_WIDTH = "0" *)
(* C_B_WIDTH = "2" *)
(* C_FAMILY = "artix7" *)
(* C_FIFO_AR_WIDTH = "14" *)
(* C_FIFO_AW_WIDTH = "14" *)
(* C_FIFO_B_WIDTH = "2" *)
(* C_FIFO_R_WIDTH = "34" *)
(* C_FIFO_W_WIDTH = "36" *)
(* C_M_AXI_ACLK_RATIO = "2" *)
(* C_RDATA_RIGHT = "2" *)
(* C_RDATA_WIDTH = "32" *)
(* C_RID_RIGHT = "34" *)
(* C_RID_WIDTH = "0" *)
(* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "0" *)
(* C_RRESP_RIGHT = "0" *)
(* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *)
(* C_RUSER_WIDTH = "0" *)
(* C_R_WIDTH = "34" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_S_AXI_ACLK_RATIO = "1" *)
(* C_WDATA_RIGHT = "4" *)
(* C_WDATA_WIDTH = "32" *)
(* C_WID_RIGHT = "36" *)
(* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *)
(* C_WLAST_WIDTH = "0" *)
(* C_WSTRB_RIGHT = "0" *)
(* C_WSTRB_WIDTH = "4" *)
(* C_WUSER_RIGHT = "0" *)
(* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "36" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ACLK_RATIO = "2" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_FULLY_REG = "1" *)
(* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *)
(* P_ROUNDING_OFFSET = "0" *)
(* P_SI_LT_MI = "1'b1" *)
system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter inst
(.m_axi_aclk(m_axi_aclk),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(1'b0),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b1}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b1}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_ARADDR_RIGHT = "3" *) (* C_ARADDR_WIDTH = "11" *) (* C_ARBURST_RIGHT = "3" *)
(* C_ARBURST_WIDTH = "0" *) (* C_ARCACHE_RIGHT = "3" *) (* C_ARCACHE_WIDTH = "0" *)
(* C_ARID_RIGHT = "14" *) (* C_ARID_WIDTH = "0" *) (* C_ARLEN_RIGHT = "3" *)
(* C_ARLEN_WIDTH = "0" *) (* C_ARLOCK_RIGHT = "3" *) (* C_ARLOCK_WIDTH = "0" *)
(* C_ARPROT_RIGHT = "0" *) (* C_ARPROT_WIDTH = "3" *) (* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "0" *) (* C_ARREGION_RIGHT = "0" *) (* C_ARREGION_WIDTH = "0" *)
(* C_ARSIZE_RIGHT = "3" *) (* C_ARSIZE_WIDTH = "0" *) (* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *) (* C_AR_WIDTH = "14" *) (* C_AWADDR_RIGHT = "3" *)
(* C_AWADDR_WIDTH = "11" *) (* C_AWBURST_RIGHT = "3" *) (* C_AWBURST_WIDTH = "0" *)
(* C_AWCACHE_RIGHT = "3" *) (* C_AWCACHE_WIDTH = "0" *) (* C_AWID_RIGHT = "14" *)
(* C_AWID_WIDTH = "0" *) (* C_AWLEN_RIGHT = "3" *) (* C_AWLEN_WIDTH = "0" *)
(* C_AWLOCK_RIGHT = "3" *) (* C_AWLOCK_WIDTH = "0" *) (* C_AWPROT_RIGHT = "0" *)
(* C_AWPROT_WIDTH = "3" *) (* C_AWQOS_RIGHT = "0" *) (* C_AWQOS_WIDTH = "0" *)
(* C_AWREGION_RIGHT = "0" *) (* C_AWREGION_WIDTH = "0" *) (* C_AWSIZE_RIGHT = "3" *)
(* C_AWSIZE_WIDTH = "0" *) (* C_AWUSER_RIGHT = "0" *) (* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "14" *) (* C_AXI_ADDR_WIDTH = "11" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_IS_ACLK_ASYNC = "1" *) (* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "0" *) (* C_BRESP_RIGHT = "0" *) (* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *) (* C_BUSER_WIDTH = "0" *) (* C_B_WIDTH = "2" *)
(* C_FAMILY = "artix7" *) (* C_FIFO_AR_WIDTH = "14" *) (* C_FIFO_AW_WIDTH = "14" *)
(* C_FIFO_B_WIDTH = "2" *) (* C_FIFO_R_WIDTH = "34" *) (* C_FIFO_W_WIDTH = "36" *)
(* C_M_AXI_ACLK_RATIO = "2" *) (* C_RDATA_RIGHT = "2" *) (* C_RDATA_WIDTH = "32" *)
(* C_RID_RIGHT = "34" *) (* C_RID_WIDTH = "0" *) (* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "0" *) (* C_RRESP_RIGHT = "0" *) (* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *) (* C_RUSER_WIDTH = "0" *) (* C_R_WIDTH = "34" *)
(* C_SYNCHRONIZER_STAGE = "3" *) (* C_S_AXI_ACLK_RATIO = "1" *) (* C_WDATA_RIGHT = "4" *)
(* C_WDATA_WIDTH = "32" *) (* C_WID_RIGHT = "36" *) (* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *) (* C_WLAST_WIDTH = "0" *) (* C_WSTRB_RIGHT = "0" *)
(* C_WSTRB_WIDTH = "4" *) (* C_WUSER_RIGHT = "0" *) (* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "36" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_axi_clock_converter" *)
(* P_ACLK_RATIO = "2" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *)
(* P_AXILITE = "2" *) (* P_FULLY_REG = "1" *) (* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *) (* P_ROUNDING_OFFSET = "0" *) (* P_SI_LT_MI = "1'b1" *)
module system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
(* keep = "true" *) input s_axi_aclk;
(* keep = "true" *) input s_axi_aresetn;
input [0:0]s_axi_awid;
input [10:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [10:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
(* keep = "true" *) input m_axi_aclk;
(* keep = "true" *) input m_axi_aresetn;
output [0:0]m_axi_awid;
output [10:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [10:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35 ;
wire \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37 ;
(* RTL_KEEP = "true" *) wire m_axi_aclk;
wire [10:0]m_axi_araddr;
(* RTL_KEEP = "true" *) wire m_axi_aresetn;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [10:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
(* RTL_KEEP = "true" *) wire s_axi_aclk;
wire [10:0]s_axi_araddr;
(* RTL_KEEP = "true" *) wire s_axi_aresetn;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire s_axi_arvalid;
wire [10:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1 \gen_clock_conv.gen_async_lite_conv.ar_handshake
(.dest_out({m_axi_arprot,m_axi_araddr}),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_35 ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out(s_axi_aclk),
.s_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_37 ),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.src_in({s_axi_arprot,s_axi_araddr}));
system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async \gen_clock_conv.gen_async_lite_conv.aw_handshake
(.dest_out({m_axi_awprot,m_axi_awaddr}),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_35 ),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out(s_axi_aclk),
.s_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_37 ),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.src_in({s_axi_awprot,s_axi_awaddr}));
system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1 \gen_clock_conv.gen_async_lite_conv.b_handshake
(.m_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_35 ),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(m_axi_aclk),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_37 ),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid));
system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2 \gen_clock_conv.gen_async_lite_conv.r_handshake
(.dest_ack_reg_0(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_37 ),
.dest_out({s_axi_rresp,s_axi_rdata}),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(m_axi_aclk),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.src_in({m_axi_rresp,m_axi_rdata}),
.src_send_reg_0(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_35 ));
system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0 \gen_clock_conv.gen_async_lite_conv.w_handshake
(.dest_out({m_axi_wstrb,m_axi_wdata}),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_35 ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out(s_axi_aclk),
.s_axi_aresetn(\gen_clock_conv.gen_async_lite_conv.r_handshake_n_37 ),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.src_in({s_axi_wstrb,s_axi_wdata}));
endmodule
(* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_lite_async" *)
module system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async
(dest_out,
s_axi_awready,
m_axi_awvalid,
out,
src_in,
m_axi_aclk,
s_axi_aresetn,
m_axi_aresetn,
s_axi_awvalid,
m_axi_awready);
output [13:0]dest_out;
output s_axi_awready;
output m_axi_awvalid;
input out;
input [13:0]src_in;
input m_axi_aclk;
input s_axi_aresetn;
input m_axi_aresetn;
input s_axi_awvalid;
input m_axi_awready;
wire \FSM_sequential_dest_state[0]_i_1_n_0 ;
wire \FSM_sequential_dest_state[1]_i_1_n_0 ;
wire \FSM_sequential_src_state[0]_i_1_n_0 ;
wire \FSM_sequential_src_state[1]_i_1_n_0 ;
wire dest_ack_i_1_n_0;
wire dest_ack_reg_n_0;
wire [13:0]dest_out;
wire dest_req;
(* RTL_KEEP = "yes" *) wire [1:0]dest_state;
wire m_axi_aclk;
wire m_axi_aresetn;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_valid_i_2_n_0;
wire out;
wire s_axi_aresetn;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_ready_i_2_n_0;
wire [13:0]src_in;
wire src_rcv;
wire src_send_i_1_n_0;
wire src_send_reg_n_0;
(* RTL_KEEP = "yes" *) wire [1:0]src_state;
LUT6 #(
.INIT(64'h0D5D5D5D04040404))
\FSM_sequential_dest_state[0]_i_1
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(m_axi_awready),
.I4(m_axi_awvalid),
.I5(dest_state[0]),
.O(\FSM_sequential_dest_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h5959595950000000))
\FSM_sequential_dest_state[1]_i_1
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(m_axi_awready),
.I4(m_axi_awvalid),
.I5(dest_state[1]),
.O(\FSM_sequential_dest_state[1]_i_1_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[0]
(.C(m_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[0]_i_1_n_0 ),
.Q(dest_state[0]),
.R(m_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[1]
(.C(m_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[1]_i_1_n_0 ),
.Q(dest_state[1]),
.R(m_axi_aresetn));
LUT5 #(
.INIT(32'h0F5D040C))
\FSM_sequential_src_state[0]_i_1
(.I0(src_state[1]),
.I1(s_axi_awvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[0]),
.O(\FSM_sequential_src_state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h5B515000))
\FSM_sequential_src_state[1]_i_1
(.I0(src_state[1]),
.I1(s_axi_awvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[1]),
.O(\FSM_sequential_src_state[1]_i_1_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[0]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[0]_i_1_n_0 ),
.Q(src_state[0]),
.R(s_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[1]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[1]_i_1_n_0 ),
.Q(src_state[1]),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h55FF550040004000))
dest_ack_i_1
(.I0(dest_state[1]),
.I1(m_axi_awvalid),
.I2(m_axi_awready),
.I3(dest_state[0]),
.I4(dest_req),
.I5(dest_ack_reg_n_0),
.O(dest_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
dest_ack_reg
(.C(m_axi_aclk),
.CE(1'b1),
.D(dest_ack_i_1_n_0),
.Q(dest_ack_reg_n_0),
.R(m_axi_aresetn));
(* DEST_EXT_HSK = "1" *)
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_SYNC_FF = "2" *)
(* VERSION = "0" *)
(* WIDTH = "14" *)
(* XPM_CDC = "HANDSHAKE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_handshake handshake
(.dest_ack(dest_ack_reg_n_0),
.dest_clk(m_axi_aclk),
.dest_out(dest_out),
.dest_req(dest_req),
.src_clk(out),
.src_in(src_in),
.src_rcv(src_rcv),
.src_send(src_send_reg_n_0));
LUT5 #(
.INIT(32'h0030F0AA))
m_valid_i_2
(.I0(dest_req),
.I1(m_axi_awready),
.I2(m_axi_awvalid),
.I3(dest_state[1]),
.I4(dest_state[0]),
.O(m_valid_i_2_n_0));
FDRE m_valid_reg
(.C(m_axi_aclk),
.CE(1'b1),
.D(m_valid_i_2_n_0),
.Q(m_axi_awvalid),
.R(m_axi_aresetn));
LUT4 #(
.INIT(16'h5540))
s_ready_i_2
(.I0(src_state[1]),
.I1(src_rcv),
.I2(src_state[0]),
.I3(s_axi_awready),
.O(s_ready_i_2_n_0));
FDRE s_ready_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_2_n_0),
.Q(s_axi_awready),
.R(s_axi_aresetn));
LUT5 #(
.INIT(32'h0F5F040C))
src_send_i_1
(.I0(src_state[1]),
.I1(s_axi_awvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_send_reg_n_0),
.O(src_send_i_1_n_0));
FDRE #(
.INIT(1'b0))
src_send_reg
(.C(out),
.CE(1'b1),
.D(src_send_i_1_n_0),
.Q(src_send_reg_n_0),
.R(s_axi_aresetn));
endmodule
(* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_lite_async" *)
module system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0
(dest_out,
s_axi_wready,
m_axi_wvalid,
out,
src_in,
m_axi_aclk,
s_axi_aresetn,
m_axi_aresetn,
s_axi_wvalid,
m_axi_wready);
output [35:0]dest_out;
output s_axi_wready;
output m_axi_wvalid;
input out;
input [35:0]src_in;
input m_axi_aclk;
input s_axi_aresetn;
input m_axi_aresetn;
input s_axi_wvalid;
input m_axi_wready;
wire \FSM_sequential_dest_state[0]_i_1__1_n_0 ;
wire \FSM_sequential_dest_state[1]_i_1__1_n_0 ;
wire \FSM_sequential_src_state[0]_i_1__1_n_0 ;
wire \FSM_sequential_src_state[1]_i_1__1_n_0 ;
wire dest_ack_i_1__1_n_0;
wire dest_ack_reg_n_0;
wire [35:0]dest_out;
wire dest_req;
(* RTL_KEEP = "yes" *) wire [1:0]dest_state;
wire m_axi_aclk;
wire m_axi_aresetn;
wire m_axi_wready;
wire m_axi_wvalid;
wire m_valid_i_1__0_n_0;
wire out;
wire s_axi_aresetn;
wire s_axi_wready;
wire s_axi_wvalid;
wire s_ready_i_1__0_n_0;
wire [35:0]src_in;
wire src_rcv;
wire src_send_i_1__1_n_0;
wire src_send_reg_n_0;
(* RTL_KEEP = "yes" *) wire [1:0]src_state;
LUT6 #(
.INIT(64'h0D5D5D5D04040404))
\FSM_sequential_dest_state[0]_i_1__1
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(dest_state[0]),
.O(\FSM_sequential_dest_state[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h5959595950000000))
\FSM_sequential_dest_state[1]_i_1__1
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(dest_state[1]),
.O(\FSM_sequential_dest_state[1]_i_1__1_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[0]
(.C(m_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[0]_i_1__1_n_0 ),
.Q(dest_state[0]),
.R(m_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[1]
(.C(m_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[1]_i_1__1_n_0 ),
.Q(dest_state[1]),
.R(m_axi_aresetn));
LUT5 #(
.INIT(32'h0F5D040C))
\FSM_sequential_src_state[0]_i_1__1
(.I0(src_state[1]),
.I1(s_axi_wvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[0]),
.O(\FSM_sequential_src_state[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h5B515000))
\FSM_sequential_src_state[1]_i_1__1
(.I0(src_state[1]),
.I1(s_axi_wvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[1]),
.O(\FSM_sequential_src_state[1]_i_1__1_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[0]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[0]_i_1__1_n_0 ),
.Q(src_state[0]),
.R(s_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[1]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[1]_i_1__1_n_0 ),
.Q(src_state[1]),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h55FF550040004000))
dest_ack_i_1__1
(.I0(dest_state[1]),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(dest_state[0]),
.I4(dest_req),
.I5(dest_ack_reg_n_0),
.O(dest_ack_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
dest_ack_reg
(.C(m_axi_aclk),
.CE(1'b1),
.D(dest_ack_i_1__1_n_0),
.Q(dest_ack_reg_n_0),
.R(m_axi_aresetn));
(* DEST_EXT_HSK = "1" *)
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_SYNC_FF = "2" *)
(* VERSION = "0" *)
(* WIDTH = "36" *)
(* XPM_CDC = "HANDSHAKE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_handshake__parameterized0 handshake
(.dest_ack(dest_ack_reg_n_0),
.dest_clk(m_axi_aclk),
.dest_out(dest_out),
.dest_req(dest_req),
.src_clk(out),
.src_in(src_in),
.src_rcv(src_rcv),
.src_send(src_send_reg_n_0));
LUT5 #(
.INIT(32'h0030F0AA))
m_valid_i_1__0
(.I0(dest_req),
.I1(m_axi_wready),
.I2(m_axi_wvalid),
.I3(dest_state[1]),
.I4(dest_state[0]),
.O(m_valid_i_1__0_n_0));
FDRE m_valid_reg
(.C(m_axi_aclk),
.CE(1'b1),
.D(m_valid_i_1__0_n_0),
.Q(m_axi_wvalid),
.R(m_axi_aresetn));
LUT4 #(
.INIT(16'h5540))
s_ready_i_1__0
(.I0(src_state[1]),
.I1(src_rcv),
.I2(src_state[0]),
.I3(s_axi_wready),
.O(s_ready_i_1__0_n_0));
FDRE s_ready_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_1__0_n_0),
.Q(s_axi_wready),
.R(s_axi_aresetn));
LUT5 #(
.INIT(32'h0F5F040C))
src_send_i_1__1
(.I0(src_state[1]),
.I1(s_axi_wvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_send_reg_n_0),
.O(src_send_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
src_send_reg
(.C(out),
.CE(1'b1),
.D(src_send_i_1__1_n_0),
.Q(src_send_reg_n_0),
.R(s_axi_aresetn));
endmodule
(* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_lite_async" *)
module system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1
(s_axi_bresp,
m_axi_bready,
s_axi_bvalid,
out,
m_axi_bresp,
s_axi_aclk,
m_axi_aresetn,
s_axi_aresetn,
m_axi_bvalid,
s_axi_bready);
output [1:0]s_axi_bresp;
output m_axi_bready;
output s_axi_bvalid;
input out;
input [1:0]m_axi_bresp;
input s_axi_aclk;
input m_axi_aresetn;
input s_axi_aresetn;
input m_axi_bvalid;
input s_axi_bready;
wire \FSM_sequential_dest_state[0]_i_1__2_n_0 ;
wire \FSM_sequential_dest_state[1]_i_1__2_n_0 ;
wire \FSM_sequential_src_state[0]_i_1__2_n_0 ;
wire \FSM_sequential_src_state[1]_i_1__2_n_0 ;
wire dest_ack_i_1__2_n_0;
wire dest_ack_reg_n_0;
wire dest_req;
(* RTL_KEEP = "yes" *) wire [1:0]dest_state;
wire m_axi_aresetn;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_valid_i_1__1_n_0;
wire out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire s_ready_i_1__1_n_0;
wire src_rcv;
wire src_send_i_1__2_n_0;
wire src_send_reg_n_0;
(* RTL_KEEP = "yes" *) wire [1:0]src_state;
LUT6 #(
.INIT(64'h0D5D5D5D04040404))
\FSM_sequential_dest_state[0]_i_1__2
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(dest_state[0]),
.O(\FSM_sequential_dest_state[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h5959595950000000))
\FSM_sequential_dest_state[1]_i_1__2
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(dest_state[1]),
.O(\FSM_sequential_dest_state[1]_i_1__2_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[0]_i_1__2_n_0 ),
.Q(dest_state[0]),
.R(s_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[1]_i_1__2_n_0 ),
.Q(dest_state[1]),
.R(s_axi_aresetn));
LUT5 #(
.INIT(32'h0F5D040C))
\FSM_sequential_src_state[0]_i_1__2
(.I0(src_state[1]),
.I1(m_axi_bvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[0]),
.O(\FSM_sequential_src_state[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h5B515000))
\FSM_sequential_src_state[1]_i_1__2
(.I0(src_state[1]),
.I1(m_axi_bvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[1]),
.O(\FSM_sequential_src_state[1]_i_1__2_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[0]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[0]_i_1__2_n_0 ),
.Q(src_state[0]),
.R(m_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[1]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[1]_i_1__2_n_0 ),
.Q(src_state[1]),
.R(m_axi_aresetn));
LUT6 #(
.INIT(64'h55FF550040004000))
dest_ack_i_1__2
(.I0(dest_state[1]),
.I1(s_axi_bvalid),
.I2(s_axi_bready),
.I3(dest_state[0]),
.I4(dest_req),
.I5(dest_ack_reg_n_0),
.O(dest_ack_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
dest_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(dest_ack_i_1__2_n_0),
.Q(dest_ack_reg_n_0),
.R(s_axi_aresetn));
(* DEST_EXT_HSK = "1" *)
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_SYNC_FF = "2" *)
(* VERSION = "0" *)
(* WIDTH = "2" *)
(* XPM_CDC = "HANDSHAKE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_handshake__parameterized1 handshake
(.dest_ack(dest_ack_reg_n_0),
.dest_clk(s_axi_aclk),
.dest_out(s_axi_bresp),
.dest_req(dest_req),
.src_clk(out),
.src_in(m_axi_bresp),
.src_rcv(src_rcv),
.src_send(src_send_reg_n_0));
LUT5 #(
.INIT(32'h0030F0AA))
m_valid_i_1__1
(.I0(dest_req),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(dest_state[1]),
.I4(dest_state[0]),
.O(m_valid_i_1__1_n_0));
FDRE m_valid_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(m_valid_i_1__1_n_0),
.Q(s_axi_bvalid),
.R(s_axi_aresetn));
LUT4 #(
.INIT(16'h5540))
s_ready_i_1__1
(.I0(src_state[1]),
.I1(src_rcv),
.I2(src_state[0]),
.I3(m_axi_bready),
.O(s_ready_i_1__1_n_0));
FDRE s_ready_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_1__1_n_0),
.Q(m_axi_bready),
.R(m_axi_aresetn));
LUT5 #(
.INIT(32'h0F5F040C))
src_send_i_1__2
(.I0(src_state[1]),
.I1(m_axi_bvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_send_reg_n_0),
.O(src_send_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
src_send_reg
(.C(out),
.CE(1'b1),
.D(src_send_i_1__2_n_0),
.Q(src_send_reg_n_0),
.R(m_axi_aresetn));
endmodule
(* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_lite_async" *)
module system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2
(dest_out,
m_axi_rready,
src_send_reg_0,
s_axi_rvalid,
dest_ack_reg_0,
out,
src_in,
s_axi_aclk,
m_axi_rvalid,
s_axi_rready,
s_axi_aresetn,
m_axi_aresetn);
output [33:0]dest_out;
output m_axi_rready;
output src_send_reg_0;
output s_axi_rvalid;
output dest_ack_reg_0;
input out;
input [33:0]src_in;
input s_axi_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_axi_aresetn;
input m_axi_aresetn;
wire \FSM_sequential_dest_state[0]_i_1__3_n_0 ;
wire \FSM_sequential_dest_state[1]_i_1__3_n_0 ;
wire \FSM_sequential_src_state[0]_i_1__3_n_0 ;
wire \FSM_sequential_src_state[1]_i_1__3_n_0 ;
wire dest_ack_i_1__3_n_0;
wire dest_ack_reg_0;
wire dest_ack_reg_n_0;
wire [33:0]dest_out;
wire dest_req;
(* RTL_KEEP = "yes" *) wire [1:0]dest_state;
wire m_axi_aresetn;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_1__2_n_0;
wire out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_1__2_n_0;
wire [33:0]src_in;
wire src_rcv;
wire src_send_i_1__3_n_0;
wire src_send_reg_0;
wire src_send_reg_n_0;
(* RTL_KEEP = "yes" *) wire [1:0]src_state;
LUT6 #(
.INIT(64'h0D5D5D5D04040404))
\FSM_sequential_dest_state[0]_i_1__3
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(dest_state[0]),
.O(\FSM_sequential_dest_state[0]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h5959595950000000))
\FSM_sequential_dest_state[1]_i_1__3
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(dest_state[1]),
.O(\FSM_sequential_dest_state[1]_i_1__3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[0]_i_1__3_n_0 ),
.Q(dest_state[0]),
.R(dest_ack_reg_0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[1]_i_1__3_n_0 ),
.Q(dest_state[1]),
.R(dest_ack_reg_0));
LUT5 #(
.INIT(32'h0F5D040C))
\FSM_sequential_src_state[0]_i_1__3
(.I0(src_state[1]),
.I1(m_axi_rvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[0]),
.O(\FSM_sequential_src_state[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h5B515000))
\FSM_sequential_src_state[1]_i_1__3
(.I0(src_state[1]),
.I1(m_axi_rvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[1]),
.O(\FSM_sequential_src_state[1]_i_1__3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[0]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[0]_i_1__3_n_0 ),
.Q(src_state[0]),
.R(src_send_reg_0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[1]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[1]_i_1__3_n_0 ),
.Q(src_state[1]),
.R(src_send_reg_0));
LUT6 #(
.INIT(64'h55FF550040004000))
dest_ack_i_1__3
(.I0(dest_state[1]),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(dest_state[0]),
.I4(dest_req),
.I5(dest_ack_reg_n_0),
.O(dest_ack_i_1__3_n_0));
FDRE #(
.INIT(1'b0))
dest_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(dest_ack_i_1__3_n_0),
.Q(dest_ack_reg_n_0),
.R(dest_ack_reg_0));
(* DEST_EXT_HSK = "1" *)
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_SYNC_FF = "2" *)
(* VERSION = "0" *)
(* WIDTH = "34" *)
(* XPM_CDC = "HANDSHAKE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_handshake__parameterized2 handshake
(.dest_ack(dest_ack_reg_n_0),
.dest_clk(s_axi_aclk),
.dest_out(dest_out),
.dest_req(dest_req),
.src_clk(out),
.src_in(src_in),
.src_rcv(src_rcv),
.src_send(src_send_reg_n_0));
LUT5 #(
.INIT(32'h0030F0AA))
m_valid_i_1__2
(.I0(dest_req),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(dest_state[1]),
.I4(dest_state[0]),
.O(m_valid_i_1__2_n_0));
LUT1 #(
.INIT(2'h1))
m_valid_i_1__3
(.I0(m_axi_aresetn),
.O(src_send_reg_0));
FDRE m_valid_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(m_valid_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(dest_ack_reg_0));
LUT4 #(
.INIT(16'h5540))
s_ready_i_1__2
(.I0(src_state[1]),
.I1(src_rcv),
.I2(src_state[0]),
.I3(m_axi_rready),
.O(s_ready_i_1__2_n_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_1__3
(.I0(s_axi_aresetn),
.O(dest_ack_reg_0));
FDRE s_ready_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_1__2_n_0),
.Q(m_axi_rready),
.R(src_send_reg_0));
LUT5 #(
.INIT(32'h0F5F040C))
src_send_i_1__3
(.I0(src_state[1]),
.I1(m_axi_rvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_send_reg_n_0),
.O(src_send_i_1__3_n_0));
FDRE #(
.INIT(1'b0))
src_send_reg
(.C(out),
.CE(1'b1),
.D(src_send_i_1__3_n_0),
.Q(src_send_reg_n_0),
.R(src_send_reg_0));
endmodule
(* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_lite_async" *)
module system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1
(dest_out,
s_axi_arready,
m_axi_arvalid,
out,
src_in,
m_axi_aclk,
s_axi_aresetn,
m_axi_aresetn,
s_axi_arvalid,
m_axi_arready);
output [13:0]dest_out;
output s_axi_arready;
output m_axi_arvalid;
input out;
input [13:0]src_in;
input m_axi_aclk;
input s_axi_aresetn;
input m_axi_aresetn;
input s_axi_arvalid;
input m_axi_arready;
wire \FSM_sequential_dest_state[0]_i_1__0_n_0 ;
wire \FSM_sequential_dest_state[1]_i_1__0_n_0 ;
wire \FSM_sequential_src_state[0]_i_1__0_n_0 ;
wire \FSM_sequential_src_state[1]_i_1__0_n_0 ;
wire dest_ack_i_1__0_n_0;
wire dest_ack_reg_n_0;
wire [13:0]dest_out;
wire dest_req;
(* RTL_KEEP = "yes" *) wire [1:0]dest_state;
wire m_axi_aclk;
wire m_axi_aresetn;
wire m_axi_arready;
wire m_axi_arvalid;
wire m_valid_i_1_n_0;
wire out;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_ready_i_1_n_0;
wire [13:0]src_in;
wire src_rcv;
wire src_send_i_1__0_n_0;
wire src_send_reg_n_0;
(* RTL_KEEP = "yes" *) wire [1:0]src_state;
LUT6 #(
.INIT(64'h0D5D5D5D04040404))
\FSM_sequential_dest_state[0]_i_1__0
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(m_axi_arready),
.I4(m_axi_arvalid),
.I5(dest_state[0]),
.O(\FSM_sequential_dest_state[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h5959595950000000))
\FSM_sequential_dest_state[1]_i_1__0
(.I0(dest_state[1]),
.I1(dest_req),
.I2(dest_state[0]),
.I3(m_axi_arready),
.I4(m_axi_arvalid),
.I5(dest_state[1]),
.O(\FSM_sequential_dest_state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[0]
(.C(m_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[0]_i_1__0_n_0 ),
.Q(dest_state[0]),
.R(m_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_dest_state_reg[1]
(.C(m_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_dest_state[1]_i_1__0_n_0 ),
.Q(dest_state[1]),
.R(m_axi_aresetn));
LUT5 #(
.INIT(32'h0F5D040C))
\FSM_sequential_src_state[0]_i_1__0
(.I0(src_state[1]),
.I1(s_axi_arvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[0]),
.O(\FSM_sequential_src_state[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h5B515000))
\FSM_sequential_src_state[1]_i_1__0
(.I0(src_state[1]),
.I1(s_axi_arvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_state[1]),
.O(\FSM_sequential_src_state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[0]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[0]_i_1__0_n_0 ),
.Q(src_state[0]),
.R(s_axi_aresetn));
(* KEEP = "yes" *)
FDRE \FSM_sequential_src_state_reg[1]
(.C(out),
.CE(1'b1),
.D(\FSM_sequential_src_state[1]_i_1__0_n_0 ),
.Q(src_state[1]),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h55FF550040004000))
dest_ack_i_1__0
(.I0(dest_state[1]),
.I1(m_axi_arvalid),
.I2(m_axi_arready),
.I3(dest_state[0]),
.I4(dest_req),
.I5(dest_ack_reg_n_0),
.O(dest_ack_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
dest_ack_reg
(.C(m_axi_aclk),
.CE(1'b1),
.D(dest_ack_i_1__0_n_0),
.Q(dest_ack_reg_n_0),
.R(m_axi_aresetn));
(* DEST_EXT_HSK = "1" *)
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_SYNC_FF = "2" *)
(* VERSION = "0" *)
(* WIDTH = "14" *)
(* XPM_CDC = "HANDSHAKE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_handshake__xdcDup__1 handshake
(.dest_ack(dest_ack_reg_n_0),
.dest_clk(m_axi_aclk),
.dest_out(dest_out),
.dest_req(dest_req),
.src_clk(out),
.src_in(src_in),
.src_rcv(src_rcv),
.src_send(src_send_reg_n_0));
LUT5 #(
.INIT(32'h0030F0AA))
m_valid_i_1
(.I0(dest_req),
.I1(m_axi_arready),
.I2(m_axi_arvalid),
.I3(dest_state[1]),
.I4(dest_state[0]),
.O(m_valid_i_1_n_0));
FDRE m_valid_reg
(.C(m_axi_aclk),
.CE(1'b1),
.D(m_valid_i_1_n_0),
.Q(m_axi_arvalid),
.R(m_axi_aresetn));
LUT4 #(
.INIT(16'h5540))
s_ready_i_1
(.I0(src_state[1]),
.I1(src_rcv),
.I2(src_state[0]),
.I3(s_axi_arready),
.O(s_ready_i_1_n_0));
FDRE s_ready_reg
(.C(out),
.CE(1'b1),
.D(s_ready_i_1_n_0),
.Q(s_axi_arready),
.R(s_axi_aresetn));
LUT5 #(
.INIT(32'h0F5F040C))
src_send_i_1__0
(.I0(src_state[1]),
.I1(s_axi_arvalid),
.I2(src_state[0]),
.I3(src_rcv),
.I4(src_send_reg_n_0),
.O(src_send_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
src_send_reg
(.C(out),
.CE(1'b1),
.D(src_send_i_1__0_n_0),
.Q(src_send_reg_n_0),
.R(s_axi_aresetn));
endmodule
(* DEST_EXT_HSK = "1" *) (* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_handshake" *)
(* SIM_ASSERT_CHK = "0" *) (* SRC_SYNC_FF = "2" *) (* VERSION = "0" *)
(* WIDTH = "14" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "HANDSHAKE" *)
module system_auto_cc_1_xpm_cdc_handshake
(src_clk,
src_in,
src_send,
src_rcv,
dest_clk,
dest_out,
dest_req,
dest_ack);
input src_clk;
input [13:0]src_in;
input src_send;
output src_rcv;
input dest_clk;
output [13:0]dest_out;
output dest_req;
input dest_ack;
wire dest_ack;
wire dest_clk;
(* DIRECT_ENABLE *) wire dest_hsdata_en;
(* RTL_KEEP = "true" *) (* xpm_cdc = "HANDSHAKE" *) wire [13:0]dest_hsdata_ff;
wire dest_req;
wire dest_req_nxt;
wire p_0_in;
wire src_clk;
wire [13:0]src_hsdata_ff;
wire [13:0]src_in;
wire src_rcv;
wire src_send;
wire src_sendd_ff;
assign dest_out[13:0] = dest_hsdata_ff;
LUT2 #(
.INIT(4'h2))
dest_hsdata_en_inferred_i_1
(.I0(dest_req_nxt),
.I1(dest_req),
.O(dest_hsdata_en));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[0]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[0]),
.Q(dest_hsdata_ff[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[10]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[10]),
.Q(dest_hsdata_ff[10]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[11]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[11]),
.Q(dest_hsdata_ff[11]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[12]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[12]),
.Q(dest_hsdata_ff[12]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[13]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[13]),
.Q(dest_hsdata_ff[13]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[1]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[1]),
.Q(dest_hsdata_ff[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[2]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[2]),
.Q(dest_hsdata_ff[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[3]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[3]),
.Q(dest_hsdata_ff[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[4]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[4]),
.Q(dest_hsdata_ff[4]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[5]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[5]),
.Q(dest_hsdata_ff[5]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[6]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[6]),
.Q(dest_hsdata_ff[6]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[7]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[7]),
.Q(dest_hsdata_ff[7]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[8]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[8]),
.Q(dest_hsdata_ff[8]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[9]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[9]),
.Q(dest_hsdata_ff[9]),
.R(1'b0));
FDRE dest_req_ff_reg
(.C(dest_clk),
.CE(1'b1),
.D(dest_req_nxt),
.Q(dest_req),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\src_hsdata_ff[13]_i_1
(.I0(src_sendd_ff),
.O(p_0_in));
FDRE \src_hsdata_ff_reg[0]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[0]),
.Q(src_hsdata_ff[0]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[10]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[10]),
.Q(src_hsdata_ff[10]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[11]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[11]),
.Q(src_hsdata_ff[11]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[12]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[12]),
.Q(src_hsdata_ff[12]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[13]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[13]),
.Q(src_hsdata_ff[13]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[1]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[1]),
.Q(src_hsdata_ff[1]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[2]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[2]),
.Q(src_hsdata_ff[2]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[3]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[3]),
.Q(src_hsdata_ff[3]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[4]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[4]),
.Q(src_hsdata_ff[4]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[5]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[5]),
.Q(src_hsdata_ff[5]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[6]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[6]),
.Q(src_hsdata_ff[6]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[7]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[7]),
.Q(src_hsdata_ff[7]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[8]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[8]),
.Q(src_hsdata_ff[8]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[9]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[9]),
.Q(src_hsdata_ff[9]),
.R(1'b0));
FDRE src_sendd_ff_reg
(.C(src_clk),
.CE(1'b1),
.D(src_send),
.Q(src_sendd_ff),
.R(1'b0));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__11 xpm_cdc_single_dest2src_inst
(.dest_clk(src_clk),
.dest_out(src_rcv),
.src_clk(dest_clk),
.src_in(dest_ack));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__10 xpm_cdc_single_src2dest_inst
(.dest_clk(dest_clk),
.dest_out(dest_req_nxt),
.src_clk(src_clk),
.src_in(src_sendd_ff));
endmodule
(* DEST_EXT_HSK = "1" *) (* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_handshake" *)
(* SIM_ASSERT_CHK = "0" *) (* SRC_SYNC_FF = "2" *) (* VERSION = "0" *)
(* WIDTH = "36" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "HANDSHAKE" *)
module system_auto_cc_1_xpm_cdc_handshake__parameterized0
(src_clk,
src_in,
src_send,
src_rcv,
dest_clk,
dest_out,
dest_req,
dest_ack);
input src_clk;
input [35:0]src_in;
input src_send;
output src_rcv;
input dest_clk;
output [35:0]dest_out;
output dest_req;
input dest_ack;
wire dest_ack;
wire dest_clk;
(* DIRECT_ENABLE *) wire dest_hsdata_en;
(* RTL_KEEP = "true" *) (* xpm_cdc = "HANDSHAKE" *) wire [35:0]dest_hsdata_ff;
wire dest_req;
wire dest_req_nxt;
wire p_0_in;
wire src_clk;
wire [35:0]src_hsdata_ff;
wire [35:0]src_in;
wire src_rcv;
wire src_send;
wire src_sendd_ff;
assign dest_out[35:0] = dest_hsdata_ff;
LUT2 #(
.INIT(4'h2))
dest_hsdata_en_inferred_i_1
(.I0(dest_req_nxt),
.I1(dest_req),
.O(dest_hsdata_en));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[0]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[0]),
.Q(dest_hsdata_ff[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[10]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[10]),
.Q(dest_hsdata_ff[10]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[11]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[11]),
.Q(dest_hsdata_ff[11]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[12]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[12]),
.Q(dest_hsdata_ff[12]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[13]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[13]),
.Q(dest_hsdata_ff[13]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[14]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[14]),
.Q(dest_hsdata_ff[14]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[15]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[15]),
.Q(dest_hsdata_ff[15]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[16]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[16]),
.Q(dest_hsdata_ff[16]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[17]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[17]),
.Q(dest_hsdata_ff[17]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[18]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[18]),
.Q(dest_hsdata_ff[18]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[19]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[19]),
.Q(dest_hsdata_ff[19]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[1]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[1]),
.Q(dest_hsdata_ff[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[20]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[20]),
.Q(dest_hsdata_ff[20]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[21]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[21]),
.Q(dest_hsdata_ff[21]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[22]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[22]),
.Q(dest_hsdata_ff[22]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[23]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[23]),
.Q(dest_hsdata_ff[23]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[24]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[24]),
.Q(dest_hsdata_ff[24]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[25]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[25]),
.Q(dest_hsdata_ff[25]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[26]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[26]),
.Q(dest_hsdata_ff[26]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[27]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[27]),
.Q(dest_hsdata_ff[27]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[28]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[28]),
.Q(dest_hsdata_ff[28]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[29]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[29]),
.Q(dest_hsdata_ff[29]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[2]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[2]),
.Q(dest_hsdata_ff[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[30]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[30]),
.Q(dest_hsdata_ff[30]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[31]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[31]),
.Q(dest_hsdata_ff[31]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[32]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[32]),
.Q(dest_hsdata_ff[32]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[33]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[33]),
.Q(dest_hsdata_ff[33]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[34]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[34]),
.Q(dest_hsdata_ff[34]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[35]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[35]),
.Q(dest_hsdata_ff[35]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[3]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[3]),
.Q(dest_hsdata_ff[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[4]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[4]),
.Q(dest_hsdata_ff[4]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[5]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[5]),
.Q(dest_hsdata_ff[5]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[6]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[6]),
.Q(dest_hsdata_ff[6]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[7]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[7]),
.Q(dest_hsdata_ff[7]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[8]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[8]),
.Q(dest_hsdata_ff[8]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[9]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[9]),
.Q(dest_hsdata_ff[9]),
.R(1'b0));
FDRE dest_req_ff_reg
(.C(dest_clk),
.CE(1'b1),
.D(dest_req_nxt),
.Q(dest_req),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\src_hsdata_ff[35]_i_1
(.I0(src_sendd_ff),
.O(p_0_in));
FDRE \src_hsdata_ff_reg[0]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[0]),
.Q(src_hsdata_ff[0]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[10]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[10]),
.Q(src_hsdata_ff[10]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[11]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[11]),
.Q(src_hsdata_ff[11]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[12]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[12]),
.Q(src_hsdata_ff[12]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[13]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[13]),
.Q(src_hsdata_ff[13]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[14]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[14]),
.Q(src_hsdata_ff[14]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[15]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[15]),
.Q(src_hsdata_ff[15]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[16]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[16]),
.Q(src_hsdata_ff[16]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[17]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[17]),
.Q(src_hsdata_ff[17]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[18]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[18]),
.Q(src_hsdata_ff[18]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[19]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[19]),
.Q(src_hsdata_ff[19]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[1]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[1]),
.Q(src_hsdata_ff[1]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[20]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[20]),
.Q(src_hsdata_ff[20]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[21]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[21]),
.Q(src_hsdata_ff[21]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[22]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[22]),
.Q(src_hsdata_ff[22]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[23]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[23]),
.Q(src_hsdata_ff[23]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[24]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[24]),
.Q(src_hsdata_ff[24]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[25]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[25]),
.Q(src_hsdata_ff[25]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[26]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[26]),
.Q(src_hsdata_ff[26]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[27]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[27]),
.Q(src_hsdata_ff[27]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[28]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[28]),
.Q(src_hsdata_ff[28]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[29]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[29]),
.Q(src_hsdata_ff[29]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[2]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[2]),
.Q(src_hsdata_ff[2]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[30]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[30]),
.Q(src_hsdata_ff[30]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[31]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[31]),
.Q(src_hsdata_ff[31]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[32]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[32]),
.Q(src_hsdata_ff[32]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[33]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[33]),
.Q(src_hsdata_ff[33]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[34]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[34]),
.Q(src_hsdata_ff[34]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[35]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[35]),
.Q(src_hsdata_ff[35]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[3]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[3]),
.Q(src_hsdata_ff[3]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[4]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[4]),
.Q(src_hsdata_ff[4]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[5]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[5]),
.Q(src_hsdata_ff[5]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[6]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[6]),
.Q(src_hsdata_ff[6]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[7]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[7]),
.Q(src_hsdata_ff[7]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[8]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[8]),
.Q(src_hsdata_ff[8]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[9]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[9]),
.Q(src_hsdata_ff[9]),
.R(1'b0));
FDRE src_sendd_ff_reg
(.C(src_clk),
.CE(1'b1),
.D(src_send),
.Q(src_sendd_ff),
.R(1'b0));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__15 xpm_cdc_single_dest2src_inst
(.dest_clk(src_clk),
.dest_out(src_rcv),
.src_clk(dest_clk),
.src_in(dest_ack));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__14 xpm_cdc_single_src2dest_inst
(.dest_clk(dest_clk),
.dest_out(dest_req_nxt),
.src_clk(src_clk),
.src_in(src_sendd_ff));
endmodule
(* DEST_EXT_HSK = "1" *) (* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_handshake" *)
(* SIM_ASSERT_CHK = "0" *) (* SRC_SYNC_FF = "2" *) (* VERSION = "0" *)
(* WIDTH = "2" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "HANDSHAKE" *)
module system_auto_cc_1_xpm_cdc_handshake__parameterized1
(src_clk,
src_in,
src_send,
src_rcv,
dest_clk,
dest_out,
dest_req,
dest_ack);
input src_clk;
input [1:0]src_in;
input src_send;
output src_rcv;
input dest_clk;
output [1:0]dest_out;
output dest_req;
input dest_ack;
wire dest_ack;
wire dest_clk;
(* DIRECT_ENABLE *) wire dest_hsdata_en;
(* RTL_KEEP = "true" *) (* xpm_cdc = "HANDSHAKE" *) wire [1:0]dest_hsdata_ff;
wire dest_req;
wire dest_req_nxt;
wire src_clk;
wire [1:0]src_hsdata_ff;
wire \src_hsdata_ff[0]_i_1_n_0 ;
wire \src_hsdata_ff[1]_i_1_n_0 ;
wire [1:0]src_in;
wire src_rcv;
wire src_send;
wire src_sendd_ff;
assign dest_out[1:0] = dest_hsdata_ff;
LUT2 #(
.INIT(4'h2))
dest_hsdata_en_inferred_i_1
(.I0(dest_req_nxt),
.I1(dest_req),
.O(dest_hsdata_en));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[0]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[0]),
.Q(dest_hsdata_ff[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[1]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[1]),
.Q(dest_hsdata_ff[1]),
.R(1'b0));
FDRE dest_req_ff_reg
(.C(dest_clk),
.CE(1'b1),
.D(dest_req_nxt),
.Q(dest_req),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hE2))
\src_hsdata_ff[0]_i_1
(.I0(src_in[0]),
.I1(src_sendd_ff),
.I2(src_hsdata_ff[0]),
.O(\src_hsdata_ff[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hE2))
\src_hsdata_ff[1]_i_1
(.I0(src_in[1]),
.I1(src_sendd_ff),
.I2(src_hsdata_ff[1]),
.O(\src_hsdata_ff[1]_i_1_n_0 ));
FDRE \src_hsdata_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(\src_hsdata_ff[0]_i_1_n_0 ),
.Q(src_hsdata_ff[0]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(\src_hsdata_ff[1]_i_1_n_0 ),
.Q(src_hsdata_ff[1]),
.R(1'b0));
FDRE src_sendd_ff_reg
(.C(src_clk),
.CE(1'b1),
.D(src_send),
.Q(src_sendd_ff),
.R(1'b0));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__17 xpm_cdc_single_dest2src_inst
(.dest_clk(src_clk),
.dest_out(src_rcv),
.src_clk(dest_clk),
.src_in(dest_ack));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__16 xpm_cdc_single_src2dest_inst
(.dest_clk(dest_clk),
.dest_out(dest_req_nxt),
.src_clk(src_clk),
.src_in(src_sendd_ff));
endmodule
(* DEST_EXT_HSK = "1" *) (* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_handshake" *)
(* SIM_ASSERT_CHK = "0" *) (* SRC_SYNC_FF = "2" *) (* VERSION = "0" *)
(* WIDTH = "34" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "HANDSHAKE" *)
module system_auto_cc_1_xpm_cdc_handshake__parameterized2
(src_clk,
src_in,
src_send,
src_rcv,
dest_clk,
dest_out,
dest_req,
dest_ack);
input src_clk;
input [33:0]src_in;
input src_send;
output src_rcv;
input dest_clk;
output [33:0]dest_out;
output dest_req;
input dest_ack;
wire dest_ack;
wire dest_clk;
(* DIRECT_ENABLE *) wire dest_hsdata_en;
(* RTL_KEEP = "true" *) (* xpm_cdc = "HANDSHAKE" *) wire [33:0]dest_hsdata_ff;
wire dest_req;
wire dest_req_nxt;
wire p_0_in;
wire src_clk;
wire [33:0]src_hsdata_ff;
wire [33:0]src_in;
wire src_rcv;
wire src_send;
wire src_sendd_ff;
assign dest_out[33:0] = dest_hsdata_ff;
LUT2 #(
.INIT(4'h2))
dest_hsdata_en_inferred_i_1
(.I0(dest_req_nxt),
.I1(dest_req),
.O(dest_hsdata_en));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[0]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[0]),
.Q(dest_hsdata_ff[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[10]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[10]),
.Q(dest_hsdata_ff[10]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[11]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[11]),
.Q(dest_hsdata_ff[11]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[12]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[12]),
.Q(dest_hsdata_ff[12]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[13]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[13]),
.Q(dest_hsdata_ff[13]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[14]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[14]),
.Q(dest_hsdata_ff[14]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[15]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[15]),
.Q(dest_hsdata_ff[15]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[16]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[16]),
.Q(dest_hsdata_ff[16]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[17]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[17]),
.Q(dest_hsdata_ff[17]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[18]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[18]),
.Q(dest_hsdata_ff[18]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[19]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[19]),
.Q(dest_hsdata_ff[19]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[1]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[1]),
.Q(dest_hsdata_ff[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[20]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[20]),
.Q(dest_hsdata_ff[20]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[21]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[21]),
.Q(dest_hsdata_ff[21]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[22]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[22]),
.Q(dest_hsdata_ff[22]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[23]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[23]),
.Q(dest_hsdata_ff[23]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[24]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[24]),
.Q(dest_hsdata_ff[24]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[25]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[25]),
.Q(dest_hsdata_ff[25]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[26]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[26]),
.Q(dest_hsdata_ff[26]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[27]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[27]),
.Q(dest_hsdata_ff[27]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[28]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[28]),
.Q(dest_hsdata_ff[28]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[29]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[29]),
.Q(dest_hsdata_ff[29]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[2]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[2]),
.Q(dest_hsdata_ff[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[30]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[30]),
.Q(dest_hsdata_ff[30]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[31]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[31]),
.Q(dest_hsdata_ff[31]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[32]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[32]),
.Q(dest_hsdata_ff[32]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[33]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[33]),
.Q(dest_hsdata_ff[33]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[3]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[3]),
.Q(dest_hsdata_ff[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[4]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[4]),
.Q(dest_hsdata_ff[4]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[5]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[5]),
.Q(dest_hsdata_ff[5]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[6]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[6]),
.Q(dest_hsdata_ff[6]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[7]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[7]),
.Q(dest_hsdata_ff[7]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[8]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[8]),
.Q(dest_hsdata_ff[8]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[9]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[9]),
.Q(dest_hsdata_ff[9]),
.R(1'b0));
FDRE dest_req_ff_reg
(.C(dest_clk),
.CE(1'b1),
.D(dest_req_nxt),
.Q(dest_req),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\src_hsdata_ff[33]_i_1
(.I0(src_sendd_ff),
.O(p_0_in));
FDRE \src_hsdata_ff_reg[0]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[0]),
.Q(src_hsdata_ff[0]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[10]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[10]),
.Q(src_hsdata_ff[10]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[11]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[11]),
.Q(src_hsdata_ff[11]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[12]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[12]),
.Q(src_hsdata_ff[12]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[13]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[13]),
.Q(src_hsdata_ff[13]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[14]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[14]),
.Q(src_hsdata_ff[14]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[15]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[15]),
.Q(src_hsdata_ff[15]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[16]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[16]),
.Q(src_hsdata_ff[16]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[17]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[17]),
.Q(src_hsdata_ff[17]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[18]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[18]),
.Q(src_hsdata_ff[18]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[19]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[19]),
.Q(src_hsdata_ff[19]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[1]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[1]),
.Q(src_hsdata_ff[1]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[20]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[20]),
.Q(src_hsdata_ff[20]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[21]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[21]),
.Q(src_hsdata_ff[21]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[22]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[22]),
.Q(src_hsdata_ff[22]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[23]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[23]),
.Q(src_hsdata_ff[23]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[24]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[24]),
.Q(src_hsdata_ff[24]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[25]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[25]),
.Q(src_hsdata_ff[25]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[26]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[26]),
.Q(src_hsdata_ff[26]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[27]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[27]),
.Q(src_hsdata_ff[27]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[28]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[28]),
.Q(src_hsdata_ff[28]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[29]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[29]),
.Q(src_hsdata_ff[29]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[2]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[2]),
.Q(src_hsdata_ff[2]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[30]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[30]),
.Q(src_hsdata_ff[30]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[31]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[31]),
.Q(src_hsdata_ff[31]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[32]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[32]),
.Q(src_hsdata_ff[32]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[33]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[33]),
.Q(src_hsdata_ff[33]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[3]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[3]),
.Q(src_hsdata_ff[3]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[4]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[4]),
.Q(src_hsdata_ff[4]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[5]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[5]),
.Q(src_hsdata_ff[5]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[6]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[6]),
.Q(src_hsdata_ff[6]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[7]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[7]),
.Q(src_hsdata_ff[7]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[8]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[8]),
.Q(src_hsdata_ff[8]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[9]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[9]),
.Q(src_hsdata_ff[9]),
.R(1'b0));
FDRE src_sendd_ff_reg
(.C(src_clk),
.CE(1'b1),
.D(src_send),
.Q(src_sendd_ff),
.R(1'b0));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single xpm_cdc_single_dest2src_inst
(.dest_clk(src_clk),
.dest_out(src_rcv),
.src_clk(dest_clk),
.src_in(dest_ack));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__18 xpm_cdc_single_src2dest_inst
(.dest_clk(dest_clk),
.dest_out(dest_req_nxt),
.src_clk(src_clk),
.src_in(src_sendd_ff));
endmodule
(* DEST_EXT_HSK = "1" *) (* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_handshake" *)
(* SIM_ASSERT_CHK = "0" *) (* SRC_SYNC_FF = "2" *) (* VERSION = "0" *)
(* WIDTH = "14" *) (* XPM_MODULE = "TRUE" *) (* xpm_cdc = "HANDSHAKE" *)
module system_auto_cc_1_xpm_cdc_handshake__xdcDup__1
(src_clk,
src_in,
src_send,
src_rcv,
dest_clk,
dest_out,
dest_req,
dest_ack);
input src_clk;
input [13:0]src_in;
input src_send;
output src_rcv;
input dest_clk;
output [13:0]dest_out;
output dest_req;
input dest_ack;
wire dest_ack;
wire dest_clk;
(* DIRECT_ENABLE *) wire dest_hsdata_en;
(* RTL_KEEP = "true" *) (* xpm_cdc = "HANDSHAKE" *) wire [13:0]dest_hsdata_ff;
wire dest_req;
wire dest_req_nxt;
wire p_0_in;
wire src_clk;
wire [13:0]src_hsdata_ff;
wire [13:0]src_in;
wire src_rcv;
wire src_send;
wire src_sendd_ff;
assign dest_out[13:0] = dest_hsdata_ff;
LUT2 #(
.INIT(4'h2))
dest_hsdata_en_inferred_i_1
(.I0(dest_req_nxt),
.I1(dest_req),
.O(dest_hsdata_en));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[0]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[0]),
.Q(dest_hsdata_ff[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[10]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[10]),
.Q(dest_hsdata_ff[10]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[11]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[11]),
.Q(dest_hsdata_ff[11]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[12]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[12]),
.Q(dest_hsdata_ff[12]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[13]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[13]),
.Q(dest_hsdata_ff[13]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[1]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[1]),
.Q(dest_hsdata_ff[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[2]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[2]),
.Q(dest_hsdata_ff[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[3]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[3]),
.Q(dest_hsdata_ff[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[4]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[4]),
.Q(dest_hsdata_ff[4]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[5]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[5]),
.Q(dest_hsdata_ff[5]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[6]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[6]),
.Q(dest_hsdata_ff[6]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[7]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[7]),
.Q(dest_hsdata_ff[7]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[8]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[8]),
.Q(dest_hsdata_ff[8]),
.R(1'b0));
(* KEEP = "yes" *)
(* XPM_CDC = "HANDSHAKE" *)
FDRE \dest_hsdata_ff_reg[9]
(.C(dest_clk),
.CE(dest_hsdata_en),
.D(src_hsdata_ff[9]),
.Q(dest_hsdata_ff[9]),
.R(1'b0));
FDRE dest_req_ff_reg
(.C(dest_clk),
.CE(1'b1),
.D(dest_req_nxt),
.Q(dest_req),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\src_hsdata_ff[13]_i_1
(.I0(src_sendd_ff),
.O(p_0_in));
FDRE \src_hsdata_ff_reg[0]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[0]),
.Q(src_hsdata_ff[0]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[10]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[10]),
.Q(src_hsdata_ff[10]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[11]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[11]),
.Q(src_hsdata_ff[11]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[12]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[12]),
.Q(src_hsdata_ff[12]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[13]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[13]),
.Q(src_hsdata_ff[13]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[1]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[1]),
.Q(src_hsdata_ff[1]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[2]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[2]),
.Q(src_hsdata_ff[2]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[3]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[3]),
.Q(src_hsdata_ff[3]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[4]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[4]),
.Q(src_hsdata_ff[4]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[5]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[5]),
.Q(src_hsdata_ff[5]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[6]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[6]),
.Q(src_hsdata_ff[6]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[7]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[7]),
.Q(src_hsdata_ff[7]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[8]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[8]),
.Q(src_hsdata_ff[8]),
.R(1'b0));
FDRE \src_hsdata_ff_reg[9]
(.C(src_clk),
.CE(p_0_in),
.D(src_in[9]),
.Q(src_hsdata_ff[9]),
.R(1'b0));
FDRE src_sendd_ff_reg
(.C(src_clk),
.CE(1'b1),
.D(src_send),
.Q(src_sendd_ff),
.R(1'b0));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__13 xpm_cdc_single_dest2src_inst
(.dest_clk(src_clk),
.dest_out(src_rcv),
.src_clk(dest_clk),
.src_in(dest_ack));
(* DEST_SYNC_FF = "2" *)
(* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SINGLE" *)
(* XPM_MODULE = "TRUE" *)
system_auto_cc_1_xpm_cdc_single__12 xpm_cdc_single_src2dest_inst
(.dest_clk(dest_clk),
.dest_out(dest_req_nxt),
.src_clk(src_clk),
.src_in(src_sendd_ff));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__10
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__11
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__12
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__13
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__14
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__15
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__16
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__17
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* ORIG_REF_NAME = "xpm_cdc_single" *) (* SIM_ASSERT_CHK = "0" *)
(* SRC_INPUT_REG = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *)
(* xpm_cdc = "SINGLE" *)
module system_auto_cc_1_xpm_cdc_single__18
(src_clk,
src_in,
dest_clk,
dest_out);
input src_clk;
input src_in;
input dest_clk;
output dest_out;
wire dest_clk;
wire src_in;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SINGLE" *) wire [1:0]syncstages_ff;
assign dest_out = syncstages_ff[1];
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_in),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XPM_CDC = "SINGLE" *)
FDRE \syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_transmitcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_transmitcontrol.v,v $
// Revision 1.6 2002/11/21 00:16:14 mohor
// When TxUsedData and CtrlMux occur at the same time, byte counter needs
// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
//
// Revision 1.5 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
`include "timescale.v"
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
parameter Tp = 1;
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= #Tp 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= #Tp 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= #Tp 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= #Tp 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= #Tp 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= #Tp 1'b1;
else
TxCtrlEndFrm <= #Tp 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= #Tp 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= #Tp 1'b1;
else
if(TxDoneIn)
CtrlMux <= #Tp 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= #Tp 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= #Tp 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= #Tp 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= #Tp 1'b0;
else
TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= #Tp 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= #Tp 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= #Tp 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= #Tp ControlEnd;
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= #Tp 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= #Tp 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= #Tp 6'h0;
else
if(ResetByteCnt)
ByteCnt <= #Tp 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= #Tp 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
endmodule
|
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_BEHAVIORAL_PP_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_BEHAVIORAL_PP_V |
// debounce debounces signals to prevent oscillation by providing
// a hold time threshold such that if the signal oscillates too quickly
// it will get ignored, the signal has to be stable before the debouncer
// will allow it to transition to a new level
module debounce
(
input wire clk,
input wire sw,
output reg db_level,
output reg db_tick
);
localparam N = 21; // filter of 2^N * 20ns = 40ms
localparam ZERO = 0;
localparam WAIT1 = 1;
localparam ONE = 2;
localparam WAIT0 = 3;
reg [1:0] state_reg, state_next;
reg [N-1:0] q_reg, q_next;
always @ (posedge clk) begin
state_reg <= state_next;
q_reg <= q_next;
end
// state machine outputs level and edge trigger changes
// it outputs the same level as long as the input signal
// changes too quickly or not changing at all. If it changes
// to quickly, it will fail the threshold value for the counter
// and get resetted back to the original level state that it
// was in.
always @ (state_reg, q_reg, sw, q_next) begin
state_next <= state_reg;
q_next <= q_reg;
db_tick <= 0;
case (state_reg)
ZERO: begin
db_level <= 0;
if (sw) begin
state_next <= WAIT1;
q_next <= ~0;
end
end
WAIT1: begin
db_level <= 0;
if (sw) begin
q_next <= q_reg - 1;
if (q_next == 0) begin
state_next <= ONE;
db_tick <= 1;
end
end
else
state_next <= ZERO;
end
ONE: begin
db_level <= 1;
if (!sw) begin
state_next <= WAIT0;
q_next <= ~0;
end
end
WAIT0: begin
db_level <= 1;
if (!sw) begin
q_next <= q_reg - 1;
if (q_next == 0)
state_next <= ZERO;
end
else
state_next <= ONE;
end
endcase
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_SYMBOL_V
`define SKY130_FD_SC_LS__NOR4_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 20:16:32 09/26/2015
// Design Name: DataUnit
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/MultiplicationUnit/DataUnitTest.v
// Project Name: DataUnit
////////////////////////////////////////////////////////////////////////////////
module DataUnitTest;
reg [3:0] Multiplicant;
reg [3:0] Multiplier;
reg [2:0] Shift1;
reg [2:0] Shift0;
reg reset, clock;
wire [7:0] Product;
DataUnit uut(Product, Multiplicant, Multiplier, Shift1, Shift0, reset, clock);
always #5 clock = ~clock;
initial begin
reset = 0; clock = 0;
Multiplicant = 3; Multiplier = 7;
Shift1 = 3'b101; Shift0 = 3'b101; #1;
reset = 1; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 5; Multiplier = 5;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 12; Multiplier = 6;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 0; Multiplier = 15;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 12; Multiplier = 12;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
$stop;
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 6
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "led_controller_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "led_controller_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE\
_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_\
ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg484,C_GP0_EN_\
MODIFIABLE_TXN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module led_controller_design_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg484"),
.C_GP0_EN_MODIFIABLE_TXN(1),
.C_GP1_EN_MODIFIABLE_TXN(1)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_4_V
`define SKY130_FD_SC_HD__O21AI_4_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:10:55 03/06/2016
// Design Name:
// Module Name: mult4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Multiplicador de 4 bits, Practica 1
module mult4(
input x0,
input x1,
input x2,
input x3,
input y0,
input y1,
input y2,
input y3,
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7
);
//productos
//wire p00; -> z0
wire p01;
wire p02;
wire p03;
wire p10;
wire p11;
wire p12;
wire p13;
wire p20;
wire p21;
wire p22;
wire p23;
wire p30;
wire p31;
wire p32;
wire p33;
//acarreos
wire c1;
wire c2;
wire c3;
wire c4;
wire c5;
wire c6;
wire c7;
wire c8;
wire c9;
wire c10;
wire c11;
wire c12;
wire c13;
wire c14;
wire c15;
//sumas
wire s1;
wire s2;
wire s3;
wire s4;
wire s5;
wire s6;
wire s7;
wire s8;
and(z0, x0, y0); //z0
and(p01, x0, y1);
and(p02, x0, y2);
and(p03, x0, y3);
and(p10, x1, y0);
and(p11, x1, y1);
and(p12, x1, y2);
and(p13, x1, y3);
and(p20, x2, y0);
and(p21, x2, y1);
and(p22, x2, y2);
and(p23, x2, y3);
and(p30, x3, y0);
and(p31, x3, y1);
and(p32, x3, y2);
and(p33, x3, y3);
summed HA1(p01, p10, z1, c1); //z1
summed HA2(p11, p20, s1, c2);
sumcomp FA2(p02, s1, c1, z2, c3); //z2
sumcomp FA31(p21, p30, p12, s2, c4);
summed HA3(p03, s2, s3, c5);
sumcomp FA32(c2, s3, c3, z3, c6); //z3
sumcomp FA41(p22, p31, p13, s4, c7);
summed HA4(s4, c4, s5, c8);
sumcomp FA42(c5, s5, c6, z4, c9); //z4
summed HA51(p23, p32, s6, c10);
summed HA52(s6, c7, s7, c11);
sumcomp FA5(c8, s7, c9, z5, c12); //z5
summed HA6(p33, c10, s8, c13);
sumcomp FA6(c11, s8, c12, z6, c14); //z6
summed HA7(c13, c14, z7, c15); //z7
endmodule
|
`timescale 1ns / 1ps
// @module
// control water in/out
// @input
// power: electric power
// start: pause switch
// clk: clock srouce group
// water_in_start: signal for starting watering in
// water_out_start: signal for starting watering out
// max_water_level: maxinum of water level(CONSTANT)
// @output
// water_in_end_sign: mark for watering in finished
// water_out_end_sign: mark for watering out finished
// water_level: display current water level
module water_let_mode
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 2)
(
input power,
input start,
input [31:0]clk,
input water_in_start,
input water_out_start,
input [2:0]max_water_level,
output reg water_in_end_sign,
output reg water_out_end_sign,
output reg [2:0]water_level
);
reg init_flag;
wire [(WIDTH-1):0]water_count;
wire water_sign_mode;
initial begin
init_flag <= 1;
water_in_end_sign = 1'b0;
water_out_end_sign = 1'b0;
water_level = {3{1'b0}};
end
// water in/out timer
timer #(WIDTH, CLK_CH, TIME_SCORE) WATER_IN_TIMER (
.clk_src(clk),
.switch_power(power),
.switch_en(start),
.sum_count({{29{1'b0}}, max_water_level}),
.count_start_flag(water_in_start | water_out_start),
.count_end_flag(water_sign_mode),
.count(water_count)
);
always @(posedge clk[0]) begin
if (power & (water_in_start | water_out_start)) begin
// when first enter this module , start ot initiate
if(init_flag) begin
if (water_in_start) begin
water_level = {3{1'b0}};
end else if (water_out_start) begin
water_level = max_water_level;
init_flag = 0;
end
end
if (start) begin
if (water_in_start) begin
water_level = max_water_level - water_count[0] - water_count[1] * 2 - water_count[2] * 4;
// bind end flag of this module to end flag of timer
water_in_end_sign = water_sign_mode;
end else if (water_out_start) begin
water_level = water_count[0] + water_count[1] * 2 + water_count[2] * 4;
// bind end flag of this module to end flag of timer
water_out_end_sign = water_sign_mode;
end
end
end else begin
// when leave this module, reset init_flag to 1
// making next time enter this module, all var of this module can be initiate
init_flag <= 1;
water_in_end_sign = 1'b0;
water_out_end_sign = 1'b0;
water_level = {3{1'b0}};
end
end
endmodule
|
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** Comparator *****/
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** Sorter cell emitting multiple values at once *****/
/**************************************************************************************************/
module SCELL #(parameter SORTW = 32,
parameter M_LOG = 2)
(input wire CLK,
input wire RST,
input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [(SORTW<<M_LOG)-1:0] din1,
input wire [(SORTW<<M_LOG)-1:0] din2,
input wire full,
output wire [(SORTW<<M_LOG)-1:0] dout,
output wire enq);
function [(SORTW<<M_LOG)-1:0] mux;
input [(SORTW<<M_LOG)-1:0] a;
input [(SORTW<<M_LOG)-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire cmp = (din1[SORTW-1:0] < din2[SORTW-1:0]);
wire [(SORTW<<M_LOG)-1:0] cmp_dout = mux(din2, din1, cmp);
wire F_enq;
wire F_deq;
wire F_emp;
wire F_full;
wire [(SORTW<<M_LOG)-1:0] F_dot;
MRE2 #(1,(SORTW<<M_LOG)) F(.CLK(CLK), .RST(RST), .enq(F_enq), .deq(F_deq),
.din(cmp_dout), .dot(F_dot), .emp(F_emp), .full(F_full));
assign F_enq = &{~F_full,valid1,valid2}; // assign F_enq = (!F_full && valid1 && valid2);
assign F_deq = ~|{full,F_emp}; // assign F_deq = !full && !F_emp;
reg [(SORTW<<M_LOG)-1:0] fbdata;
reg [(SORTW<<M_LOG)-1:0] fbdata_a; // duplicated register
reg [(SORTW<<M_LOG)-1:0] fbdata_b; // duplicated register
reg fbinvoke;
assign enq = (F_deq && fbinvoke);
assign deq1 = (F_enq && cmp);
assign deq2 = (F_enq && !cmp);
localparam P_DATAWIDTH = 32;
wire [P_DATAWIDTH-1:0] a, b, c, d, e, f, g, h;
wire [P_DATAWIDTH-1:0] e_a, f_a, g_a, h_a; // for duplicated register
wire [P_DATAWIDTH-1:0] e_b, f_b, g_b, h_b; // for duplicated register
assign a = F_dot[ 31: 0];
assign b = F_dot[ 63:32];
assign c = F_dot[ 95:64];
assign d = F_dot[127:96];
assign e = fbdata[ 31: 0];
assign f = fbdata[ 63:32];
assign g = fbdata[ 95:64];
assign h = fbdata[127:96];
assign e_a = fbdata_a[ 31: 0];
assign f_a = fbdata_a[ 63:32];
assign g_a = fbdata_a[ 95:64];
assign h_a = fbdata_a[127:96];
assign e_b = fbdata_b[ 31: 0];
assign f_b = fbdata_b[ 63:32];
assign g_b = fbdata_b[ 95:64];
assign h_b = fbdata_b[127:96];
wire t0_c0 = (a < h);
wire t0_c1 = (b < g);
wire t0_c2 = (c < f);
wire t0_c3 = (d < e);
wire t0_x0 = t0_c0 ^ t0_c1;
wire t0_x1 = t0_c2 ^ t0_c3;
wire t0 = t0_x0 ^ t0_x1;
wire s2_c0 = (b < e);
wire s2_c1 = (a < f);
wire s3_c0 = (c < h);
wire s3_c1 = (d < g);
wire s4_c0 = (a < g);
wire s4_c1 = (b < f);
wire s4_c2 = (c < e);
wire s5_c0 = (d < f);
wire s5_c1 = (c < g);
wire s5_c2 = (b < h);
wire s0 = (a < e);
wire s1 = (d < h);
wire [1:0] s2 = {s0, (s2_c0 ^ s2_c1)};
wire [1:0] s3 = {s1, (s3_c0 ^ s3_c1)};
wire [2:0] s4 = {s2, (s4_c0 ^ s4_c1 ^ s4_c2)};
wire [2:0] s5 = {s3, (s5_c0 ^ s5_c1 ^ s5_c2)};
wire [3:0] s6 = {s4, t0};
wire [3:0] s7 = {s5, t0};
wire [P_DATAWIDTH-1:0] m0, m1, m2, m3, m4, m5, m6, m7;
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [32-1:0] mux4in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [1:0] sel;
begin
case (sel)
2'b00: mux4in32 = a;
2'b01: mux4in32 = b;
2'b10: mux4in32 = c;
2'b11: mux4in32 = d;
endcase
end
endfunction
function [32-1:0] mux6in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [2:0] sel;
begin
casex (sel)
3'b000: mux6in32 = a;
3'b001: mux6in32 = b;
3'b100: mux6in32 = c;
3'b101: mux6in32 = d;
3'bx10: mux6in32 = e;
3'bx11: mux6in32 = f;
endcase
end
endfunction
function [32-1:0] mux12in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [32-1:0] g;
input [32-1:0] h;
input [32-1:0] i;
input [32-1:0] j;
input [32-1:0] k;
input [32-1:0] l;
input [3:0] sel;
begin
casex (sel)
4'b0000: mux12in32 = a;
4'b0001: mux12in32 = b;
4'b0010: mux12in32 = c;
4'b0011: mux12in32 = d;
4'b1000: mux12in32 = e;
4'b1001: mux12in32 = f;
4'b1010: mux12in32 = g;
4'b1011: mux12in32 = h;
4'bx100: mux12in32 = i;
4'bx101: mux12in32 = j;
4'bx110: mux12in32 = k;
4'bx111: mux12in32 = l;
endcase
end
endfunction
assign m0 = mux32(e, a, s0);
assign m1 = mux32(d, h, s1);
assign m2 = mux4in32(f, a, b, e, s2);
assign m3 = mux4in32(c, h, g, d, s3);
assign m4 = mux6in32(g, a, e, c, b, f, s4);
assign m5 = mux6in32(b, h, d, f, g, c, s5);
// using duplicated registers
assign m6 = mux12in32(h_a, a, b, g_a, f_a, c, d, e_a, f_a, c, b, g_a, s6);
assign m7 = mux12in32(a, h_b, g_b, b, c, f_b, e_b, d, c, f_b, g_b, b, s7);
// output and feedback
//////////////////////////////////////////////////////////
assign dout = {m6,m4,m2,m0}; // output
always @(posedge CLK) begin // feedback
if (RST) begin
fbdata <= 0;
fbdata_a <= 0;
fbdata_b <= 0;
fbinvoke <= 0;
end else begin
if (F_deq) begin
fbdata <= {m1,m3,m5,m7};
fbdata_a <= {m1,m3,m5,m7};
fbdata_b <= {m1,m3,m5,m7};
fbinvoke <= 1;
end
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire rx_wait,
output wire [`MERGW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
(* mark_debug = "true" *) wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den;
wire im_deq = (req && !im_emp);
assign rx_wait = im_cnt[`IB_SIZE-1];
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/ // todo
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`MERGW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [1:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`MERGW-1:0] mux;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[`MERGW-1:0], dot[`MERGW-1:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==3)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==2)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {`MERGW'b0, dot_t[`DRAMW-1:`MERGW]};
2'b11: dot_t <= {`MERGW'b0, dot[`DRAMW-1:`MERGW]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`MERGW-1:0] din, // data in
output wire [`MERGW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`MERGW-1:0] mux128;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux128 = a;
1'b1: mux128 = b;
endcase
end
endfunction
/*****************************************/
wire [`MERGW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`MERGW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux128(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 4;
if (ecnt==4 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`MERGW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`MERGW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07;
assign {d00, d01, d02, d03, d04, d05, d06, d07} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
wire F08_enq, F08_deq, F08_emp, F08_full; wire [`MERGW-1:0] F08_din, F08_dot; wire [1:0] F08_cnt;
wire F09_enq, F09_deq, F09_emp, F09_full; wire [`MERGW-1:0] F09_din, F09_dot; wire [1:0] F09_cnt;
wire F10_enq, F10_deq, F10_emp, F10_full; wire [`MERGW-1:0] F10_din, F10_dot; wire [1:0] F10_cnt;
wire F11_enq, F11_deq, F11_emp, F11_full; wire [`MERGW-1:0] F11_din, F11_dot; wire [1:0] F11_cnt;
wire F12_enq, F12_deq, F12_emp, F12_full; wire [`MERGW-1:0] F12_din, F12_dot; wire [1:0] F12_cnt;
wire F13_enq, F13_deq, F13_emp, F13_full; wire [`MERGW-1:0] F13_din, F13_dot; wire [1:0] F13_cnt;
wire F14_enq, F14_deq, F14_emp, F14_full; wire [`MERGW-1:0] F14_din, F14_dot; wire [1:0] F14_cnt;
wire F15_enq, F15_deq, F15_emp, F15_full; wire [`MERGW-1:0] F15_din, F15_dot; wire [1:0] F15_cnt;
INBUF IN08(CLK, RST, full[0], F08_full, F08_enq, d00, F08_din, enq[0], phase, irst);
INBUF IN09(CLK, RST, full[1], F09_full, F09_enq, d01, F09_din, enq[1], phase, irst);
INBUF IN10(CLK, RST, full[2], F10_full, F10_enq, d02, F10_din, enq[2], phase, irst);
INBUF IN11(CLK, RST, full[3], F11_full, F11_enq, d03, F11_din, enq[3], phase, irst);
INBUF IN12(CLK, RST, full[4], F12_full, F12_enq, d04, F12_din, enq[4], phase, irst);
INBUF IN13(CLK, RST, full[5], F13_full, F13_enq, d05, F13_din, enq[5], phase, irst);
INBUF IN14(CLK, RST, full[6], F14_full, F14_enq, d06, F14_din, enq[6], phase, irst);
INBUF IN15(CLK, RST, full[7], F15_full, F15_enq, d07, F15_din, enq[7], phase, irst);
MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
MRE2 #(1, `MERGW) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
MRE2 #(1, `MERGW) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
MRE2 #(1, `MERGW) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
MRE2 #(1, `MERGW) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
MRE2 #(1, `MERGW) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
MRE2 #(1, `MERGW) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
MRE2 #(1, `MERGW) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
MRE2 #(1, `MERGW) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
SCELL #(`SORTW, `M_LOG) S04(CLK, frst, !F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
SCELL #(`SORTW, `M_LOG) S05(CLK, frst, !F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
SCELL #(`SORTW, `M_LOG) S06(CLK, frst, !F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
SCELL #(`SORTW, `M_LOG) S07(CLK, frst, !F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`MERGW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [1:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 3);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/***** Sorting Network *****/
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester B for data
reg pcB; // pipeline regester B for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester C for data
reg pcC; // pipeline regester C for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester D for data
reg pcD; // pipeline regester D for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester E for data
reg pcE; // pipeline regester E for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester F for data
reg pcF; // pipeline regester F for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester G for data
reg pcG; // pipeline regester G for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester H for data
reg pcH; // pipeline regester H for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester I for data
reg pcI; // pipeline regester I for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
input wire [`DRAMW-1:0] rx_data,
input wire rx_data_valid,
output wire rx_wait,
input wire chnl_tx_data_ren,
input wire chnl_tx_data_valid,
output wire [`MERGW-1:0] rslt,
output wire rslt_ready);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORT_WAY-1:0] mux_sortway;
input [`SORT_WAY-1:0] a;
input [`SORT_WAY-1:0] b;
input sel;
begin
case (sel)
1'b0: mux_sortway = a;
1'b1: mux_sortway = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
/**********************************************************************************************/
wire [`DRAMW-1:0] OB_dot_a, OB_dot_b;
wire OB_req_a, OB_req_b;
wire OB_full_a, OB_full_b;
reg OB_granted_a, OB_granted_b;
wire OB_deq_a = d_w && OB_granted_a;
wire OB_deq_b = d_w && OB_granted_b;
assign d_din = mux512(OB_dot_b, OB_dot_a, OB_granted_a);
reg [`DRAMW-1:0] dout_ta;
reg [`DRAMW-1:0] dout_tb;
reg [`DRAMW-1:0] dout_tc;
reg [`DRAMW-1:0] dout_td;
reg [`DRAMW-1:0] dout_te;
reg [`DRAMW-1:0] dout_tf;
reg doen_ta;
reg doen_tb; //
reg doen_tc; //
reg doen_td; //
reg doen_te; //
reg doen_tf; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [`SORT_WAY-1:0] req_a, req_b;
reg [`SORT_WAY-1:0] req_ta;
reg [`SORT_WAY-1:0] req_tb;
reg [`SORT_WAY-1:0] req_taa; //
reg [`SORT_WAY-1:0] req_tab; //
reg [`SORT_WAY-1:0] req_tba; //
reg [`SORT_WAY-1:0] req_tbb; //
reg [`SRTP_WAY-1:0] req_pzero;
wire [`SORT_WAY-1:0] im_req_a;
wire [`SORT_WAY-1:0] im_req_b;
wire [`SRTP_WAY-1:0] rxw;
reg [31:0] elem_a, elem_b; // sorted elements in a phase
reg [`PHASE_W] phase_a, phase_b; //
reg pchange_a, pchange_b; // phase_change to reset some registers
reg iter_done_a, iter_done_b; //
reg [31:0] ecnt_a, ecnt_b; // sorted elements in an iteration
reg irst_a, irst_b; // INBUF reset
reg frst_a, frst_b; // sort-tree FIFO reset
reg plast_a, plast_b;
reg phase_zero;
reg last_phase;
reg RSTa, RSTb;
always @(posedge CLK) RSTa <= RST_IN;
always @(posedge CLK) RSTb <= RST_IN;
/**********************************************************************************************/
wire [`MERGW-1:0] d00_a, d01_a, d02_a, d03_a, d04_a, d05_a, d06_a, d07_a;
wire [1:0] ib00_req_a, ib01_req_a, ib02_req_a, ib03_req_a, ib04_req_a, ib05_req_a, ib06_req_a, ib07_req_a;
wire [`MERGW-1:0] d00_b, d01_b, d02_b, d03_b, d04_b, d05_b, d06_b, d07_b;
wire [1:0] ib00_req_b, ib01_req_b, ib02_req_b, ib03_req_b, ib04_req_b, ib05_req_b, ib06_req_b, ib07_req_b;
(* mark_debug = "true" *) wire rsltbuf_enq;
(* mark_debug = "true" *) wire rsltbuf_deq;
wire rsltbuf_emp;
wire rsltbuf_ful;
(* mark_debug = "true" *) wire [4:0] rsltbuf_cnt;
wire F01_emp_a, F01_emp_b;
wire F01_deq_a = mux1((~|{F01_emp_a,OB_full_a}), (~|{F01_emp_a,rsltbuf_ful}), last_phase);
wire F01_deq_b = (~|{F01_emp_b,OB_full_b});
wire [`MERGW-1:0] F01_dot_a, F01_dot_b;
wire [`MERGW*`SORT_WAY-1:0] s_din_a = {d00_a, d01_a, d02_a, d03_a, d04_a, d05_a, d06_a, d07_a};
wire [`MERGW*`SORT_WAY-1:0] s_din_b = {d00_b, d01_b, d02_b, d03_b, d04_b, d05_b, d06_b, d07_b};
wire [`SORT_WAY-1:0] enq_a, enq_b;
wire [`SORT_WAY-1:0] s_ful_a, s_ful_b;
wire [`DRAMW-1:0] stnet_dout;
wire stnet_douten;
SORTINGNETWORK sortingnetwork(CLK, RSTa, rx_data_valid, rx_data, stnet_dout, stnet_douten);
always @(posedge CLK) begin
if (RSTa) req_pzero <= 1;
else if (doen_tc) req_pzero <= {req_pzero[`SRTP_WAY-2:0],req_pzero[`SRTP_WAY-1]};
end
assign im_req_a = mux_sortway(req_tab, req_pzero[`SORT_WAY-1:0], phase_zero);
assign im_req_b = mux_sortway(req_tbb, req_pzero[`SRTP_WAY-1:`SORT_WAY], phase_zero);
INMOD2 im00_a(CLK, RSTa, dout_tc, doen_tc & im_req_a[0], s_ful_a[0], rxw[0], d00_a, enq_a[0], ib00_req_a);
INMOD2 im01_a(CLK, RSTa, dout_tc, doen_tc & im_req_a[1], s_ful_a[1], rxw[1], d01_a, enq_a[1], ib01_req_a);
INMOD2 im02_a(CLK, RSTa, dout_td, doen_td & im_req_a[2], s_ful_a[2], rxw[2], d02_a, enq_a[2], ib02_req_a);
INMOD2 im03_a(CLK, RSTa, dout_td, doen_td & im_req_a[3], s_ful_a[3], rxw[3], d03_a, enq_a[3], ib03_req_a);
INMOD2 im04_a(CLK, RSTa, dout_te, doen_te & im_req_a[4], s_ful_a[4], rxw[4], d04_a, enq_a[4], ib04_req_a);
INMOD2 im05_a(CLK, RSTa, dout_te, doen_te & im_req_a[5], s_ful_a[5], rxw[5], d05_a, enq_a[5], ib05_req_a);
INMOD2 im06_a(CLK, RSTa, dout_tf, doen_tf & im_req_a[6], s_ful_a[6], rxw[6], d06_a, enq_a[6], ib06_req_a);
INMOD2 im07_a(CLK, RSTa, dout_tf, doen_tf & im_req_a[7], s_ful_a[7], rxw[7], d07_a, enq_a[7], ib07_req_a);
INMOD2 im00_b(CLK, RSTb, dout_tc, doen_tc & im_req_b[0], s_ful_b[0], rxw[8], d00_b, enq_b[0], ib00_req_b);
INMOD2 im01_b(CLK, RSTb, dout_tc, doen_tc & im_req_b[1], s_ful_b[1], rxw[9], d01_b, enq_b[1], ib01_req_b);
INMOD2 im02_b(CLK, RSTb, dout_td, doen_td & im_req_b[2], s_ful_b[2], rxw[10], d02_b, enq_b[2], ib02_req_b);
INMOD2 im03_b(CLK, RSTb, dout_td, doen_td & im_req_b[3], s_ful_b[3], rxw[11], d03_b, enq_b[3], ib03_req_b);
INMOD2 im04_b(CLK, RSTb, dout_te, doen_te & im_req_b[4], s_ful_b[4], rxw[12], d04_b, enq_b[4], ib04_req_b);
INMOD2 im05_b(CLK, RSTb, dout_te, doen_te & im_req_b[5], s_ful_b[5], rxw[13], d05_b, enq_b[5], ib05_req_b);
INMOD2 im06_b(CLK, RSTb, dout_tf, doen_tf & im_req_b[6], s_ful_b[6], rxw[14], d06_b, enq_b[6], ib06_req_b);
INMOD2 im07_b(CLK, RSTb, dout_tf, doen_tf & im_req_b[7], s_ful_b[7], rxw[15], d07_b, enq_b[7], ib07_req_b);
assign rx_wait = |rxw;
STREE stree_a(CLK, RSTa, irst_a, frst_a, phase_a, s_din_a, enq_a, s_ful_a, F01_deq_a, F01_dot_a, F01_emp_a);
STREE stree_b(CLK, RSTb, irst_b, frst_b, phase_b, s_din_b, enq_b, s_ful_b, F01_deq_b, F01_dot_b, F01_emp_b);
OTMOD ob_a(CLK, RSTa, (!last_phase && F01_deq_a), F01_dot_a, OB_deq_a, OB_dot_a, OB_full_a, OB_req_a);
OTMOD ob_b(CLK, RSTb, F01_deq_b, F01_dot_b, OB_deq_b, OB_dot_b, OB_full_b, OB_req_b);
assign rsltbuf_enq = last_phase && F01_deq_a;
assign rsltbuf_deq = chnl_tx_data_ren && chnl_tx_data_valid;
SRL_FIFO #(4, `MERGW) rsltbuf(CLK, RSTa, rsltbuf_enq, rsltbuf_deq, F01_dot_a,
rslt, rsltbuf_emp, rsltbuf_ful, rsltbuf_cnt);
assign rslt_ready = !rsltbuf_emp;
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [31:0] w_addr_pzero; //
reg [31:0] w_addr_a, w_addr_b;
reg [3:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h;
reg [31:0] radr_a_a, radr_b_a, radr_c_a, radr_d_a, radr_e_a, radr_f_a, radr_g_a, radr_h_a;
reg [31:0] radr_a_b, radr_b_b, radr_c_b, radr_d_b, radr_e_b, radr_f_b, radr_g_b, radr_h_b;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h;
reg [27:0] cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a, cnt_e_a, cnt_f_a, cnt_g_a, cnt_h_a;
reg [27:0] cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b, cnt_e_b, cnt_f_b, cnt_g_b, cnt_h_b;
reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h; // counter is full ?
reg c_a_a, c_b_a, c_c_a, c_d_a, c_e_a, c_f_a, c_g_a, c_h_a;
reg c_a_b, c_b_b, c_c_b, c_d_b, c_e_b, c_f_b, c_g_b, c_h_b;
always @(posedge CLK) begin
if (RSTa || pchange_a || pchange_b) begin
if (RSTa) state <= 0;
if (RSTa) {d_req, d_initadr, d_blocks} <= 0;
if (RSTa) w_addr_pzero <= (`SORT_ELM>>1);
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
radr_e <= ((`SELM_PER_WAY>>3)*4);
radr_f <= ((`SELM_PER_WAY>>3)*5);
radr_g <= ((`SELM_PER_WAY>>3)*6);
radr_h <= ((`SELM_PER_WAY>>3)*7);
{cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h} <= 0;
{c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h} <= 0;
if ((RSTa || pchange_a) && !plast_a) begin
req_a <= 0;
w_addr_a <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*0);
radr_b_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*1);
radr_c_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*2);
radr_d_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*3);
radr_e_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*4);
radr_f_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*5);
radr_g_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*6);
radr_h_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*7);
{cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a, cnt_e_a, cnt_f_a, cnt_g_a, cnt_h_a} <= 0;
{c_a_a, c_b_a, c_c_a, c_d_a, c_e_a, c_f_a, c_g_a, c_h_a} <= 0;
OB_granted_a <= 0;
end
if ((RSTa || pchange_b) && !plast_b) begin
req_b <= 0;
w_addr_b <= mux32(((`SORT_ELM>>2) | (`SORT_ELM>>1)), (`SORT_ELM>>2), phase_b[0]);
radr_a_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>2);
radr_b_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2);
radr_c_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2);
radr_d_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2);
radr_e_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*4) | (`SORT_ELM>>2);
radr_f_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*5) | (`SORT_ELM>>2);
radr_g_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*6) | (`SORT_ELM>>2);
radr_h_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*7) | (`SORT_ELM>>2);
{cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b, cnt_e_b, cnt_f_b, cnt_g_b, cnt_h_b} <= 0;
{c_a_b, c_b_b, c_c_b, c_d_b, c_e_b, c_f_b, c_g_b, c_h_b} <= 0;
OB_granted_b <= 0;
end
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (!phase_zero) state <= 4;
if (d_req != 0) d_req <= 0;
else if (!d_busy) begin
if (OB_req_a || OB_req_b) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_pzero; //
w_addr_pzero <= w_addr_pzero + (`D_WS); // address for the next write
if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; end
end
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req_a[1] && !c_a) begin req<=8'h01; state<=3; end // first priority
else if (ib01_req_a[1] && !c_b) begin req<=8'h02; state<=3; end //
else if (ib02_req_a[1] && !c_c) begin req<=8'h04; state<=3; end //
else if (ib03_req_a[1] && !c_d) begin req<=8'h08; state<=3; end //
else if (ib04_req_a[1] && !c_e) begin req<=8'h10; state<=3; end //
else if (ib05_req_a[1] && !c_f) begin req<=8'h20; state<=3; end //
else if (ib06_req_a[1] && !c_g) begin req<=8'h40; state<=3; end //
else if (ib07_req_a[1] && !c_h) begin req<=8'h80; state<=3; end //
else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req_a[0] && !c_a) begin req<=8'h01; state<=3; end // second priority
else if (ib01_req_a[0] && !c_b) begin req<=8'h02; state<=3; end //
else if (ib02_req_a[0] && !c_c) begin req<=8'h04; state<=3; end //
else if (ib03_req_a[0] && !c_d) begin req<=8'h08; state<=3; end //
else if (ib04_req_a[0] && !c_e) begin req<=8'h10; state<=3; end //
else if (ib05_req_a[0] && !c_f) begin req<=8'h20; state<=3; end //
else if (ib06_req_a[0] && !c_g) begin req<=8'h40; state<=3; end //
else if (ib07_req_a[0] && !c_h) begin req<=8'h80; state<=3; end //
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
8'h01: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
8'h02: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase_a[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
8'h04: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase_a[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
8'h08: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase_a[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
8'h10: begin
d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase_a[0]);
radr_e <= radr_e+(`D_RS);
cnt_e <= cnt_e+1;
c_e <= (cnt_e>=`WAY_CN_);
end
8'h20: begin
d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase_a[0]);
radr_f <= radr_f+(`D_RS);
cnt_f <= cnt_f+1;
c_f <= (cnt_f>=`WAY_CN_);
end
8'h40: begin
d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase_a[0]);
radr_g <= radr_g+(`D_RS);
cnt_g <= cnt_g+1;
c_g <= (cnt_g>=`WAY_CN_);
end
8'h80: begin
d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase_a[0]);
radr_h <= radr_h+(`D_RS);
cnt_h <= cnt_h+1;
c_h <= (cnt_h>=`WAY_CN_);
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_ta <= req;
req_tb <= 0;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin
if (!d_busy) begin
///////////////// can be parameterized
if (ib00_req_a[1] && !c_a_a) begin req_a<=8'h01; req_b<=0; state<=6; end // first priority
else if (ib01_req_a[1] && !c_b_a) begin req_a<=8'h02; req_b<=0; state<=6; end //
else if (ib02_req_a[1] && !c_c_a) begin req_a<=8'h04; req_b<=0; state<=6; end //
else if (ib03_req_a[1] && !c_d_a) begin req_a<=8'h08; req_b<=0; state<=6; end //
else if (ib04_req_a[1] && !c_e_a) begin req_a<=8'h10; req_b<=0; state<=6; end // first priority
else if (ib05_req_a[1] && !c_f_a) begin req_a<=8'h20; req_b<=0; state<=6; end //
else if (ib06_req_a[1] && !c_g_a) begin req_a<=8'h40; req_b<=0; state<=6; end //
else if (ib07_req_a[1] && !c_h_a) begin req_a<=8'h80; req_b<=0; state<=6; end //
else if (ib00_req_b[1] && !c_a_b) begin req_b<=8'h01; req_a<=0; state<=6; end // first priority
else if (ib01_req_b[1] && !c_b_b) begin req_b<=8'h02; req_a<=0; state<=6; end //
else if (ib02_req_b[1] && !c_c_b) begin req_b<=8'h04; req_a<=0; state<=6; end //
else if (ib03_req_b[1] && !c_d_b) begin req_b<=8'h08; req_a<=0; state<=6; end //
else if (ib04_req_b[1] && !c_e_b) begin req_b<=8'h10; req_a<=0; state<=6; end // first priority
else if (ib05_req_b[1] && !c_f_b) begin req_b<=8'h20; req_a<=0; state<=6; end //
else if (ib06_req_b[1] && !c_g_b) begin req_b<=8'h40; req_a<=0; state<=6; end //
else if (ib07_req_b[1] && !c_h_b) begin req_b<=8'h80; req_a<=0; state<=6; end //
else state<=5;
end
end
5: begin
if (!d_busy) begin
///////////////// can be parameterized
if (ib00_req_a[0] && !c_a_a) begin req_a<=8'h01; req_b<=0; state<=6; end // first priority
else if (ib01_req_a[0] && !c_b_a) begin req_a<=8'h02; req_b<=0; state<=6; end //
else if (ib02_req_a[0] && !c_c_a) begin req_a<=8'h04; req_b<=0; state<=6; end //
else if (ib03_req_a[0] && !c_d_a) begin req_a<=8'h08; req_b<=0; state<=6; end //
else if (ib04_req_a[0] && !c_e_a) begin req_a<=8'h10; req_b<=0; state<=6; end // first priority
else if (ib05_req_a[0] && !c_f_a) begin req_a<=8'h20; req_b<=0; state<=6; end //
else if (ib06_req_a[0] && !c_g_a) begin req_a<=8'h40; req_b<=0; state<=6; end //
else if (ib07_req_a[0] && !c_h_a) begin req_a<=8'h80; req_b<=0; state<=6; end //
else if (ib00_req_b[0] && !c_a_b) begin req_b<=8'h01; req_a<=0; state<=6; end // first priority
else if (ib01_req_b[0] && !c_b_b) begin req_b<=8'h02; req_a<=0; state<=6; end //
else if (ib02_req_b[0] && !c_c_b) begin req_b<=8'h04; req_a<=0; state<=6; end //
else if (ib03_req_b[0] && !c_d_b) begin req_b<=8'h08; req_a<=0; state<=6; end //
else if (ib04_req_b[0] && !c_e_b) begin req_b<=8'h10; req_a<=0; state<=6; end // first priority
else if (ib05_req_b[0] && !c_f_b) begin req_b<=8'h20; req_a<=0; state<=6; end //
else if (ib06_req_b[0] && !c_g_b) begin req_b<=8'h40; req_a<=0; state<=6; end //
else if (ib07_req_b[0] && !c_h_b) begin req_b<=8'h80; req_a<=0; state<=6; end //
else if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; state<=7; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; state<=8; end
else if (last_phase) state<=1;
end
end
////////////////////////////////////////////////////////////////////////////////////////
6: begin
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
case ({req_b,req_a})
16'h0001: begin
d_initadr <= mux32(radr_a_a, (radr_a_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a_a <= radr_a_a+(`D_RS);
cnt_a_a <= cnt_a_a+1;
c_a_a <= (cnt_a_a>=`WAYP_CN_);
end
16'h0002: begin
d_initadr <= mux32(radr_b_a, (radr_b_a | (`SORT_ELM>>1)), phase_a[0]);
radr_b_a <= radr_b_a+(`D_RS);
cnt_b_a <= cnt_b_a+1;
c_b_a <= (cnt_b_a>=`WAYP_CN_);
end
16'h0004: begin
d_initadr <= mux32(radr_c_a, (radr_c_a | (`SORT_ELM>>1)), phase_a[0]);
radr_c_a <= radr_c_a+(`D_RS);
cnt_c_a <= cnt_c_a+1;
c_c_a <= (cnt_c_a>=`WAYP_CN_);
end
16'h0008: begin
d_initadr <= mux32(radr_d_a, (radr_d_a | (`SORT_ELM>>1)), phase_a[0]);
radr_d_a <= radr_d_a+(`D_RS);
cnt_d_a <= cnt_d_a+1;
c_d_a <= (cnt_d_a>=`WAYP_CN_);
end
16'h0010: begin
d_initadr <= mux32(radr_e_a, (radr_e_a | (`SORT_ELM>>1)), phase_a[0]);
radr_e_a <= radr_e_a+(`D_RS);
cnt_e_a <= cnt_e_a+1;
c_e_a <= (cnt_e_a>=`WAYP_CN_);
end
16'h0020: begin
d_initadr <= mux32(radr_f_a, (radr_f_a | (`SORT_ELM>>1)), phase_a[0]);
radr_f_a <= radr_f_a+(`D_RS);
cnt_f_a <= cnt_f_a+1;
c_f_a <= (cnt_f_a>=`WAYP_CN_);
end
16'h0040: begin
d_initadr <= mux32(radr_g_a, (radr_g_a | (`SORT_ELM>>1)), phase_a[0]);
radr_g_a <= radr_g_a+(`D_RS);
cnt_g_a <= cnt_g_a+1;
c_g_a <= (cnt_g_a>=`WAYP_CN_);
end
16'h0080: begin
d_initadr <= mux32(radr_h_a, (radr_h_a | (`SORT_ELM>>1)), phase_a[0]);
radr_h_a <= radr_h_a+(`D_RS);
cnt_h_a <= cnt_h_a+1;
c_h_a <= (cnt_h_a>=`WAYP_CN_);
end
16'h0100: begin
d_initadr <= mux32(radr_a_b, (radr_a_b | (`SORT_ELM>>1)), phase_b[0]);
radr_a_b <= radr_a_b+(`D_RS);
cnt_a_b <= cnt_a_b+1;
c_a_b <= (cnt_a_b>=`WAYP_CN_);
end
16'h0200: begin
d_initadr <= mux32(radr_b_b, (radr_b_b | (`SORT_ELM>>1)), phase_b[0]);
radr_b_b <= radr_b_b+(`D_RS);
cnt_b_b <= cnt_b_b+1;
c_b_b <= (cnt_b_b>=`WAYP_CN_);
end
16'h0400: begin
d_initadr <= mux32(radr_c_b, (radr_c_b | (`SORT_ELM>>1)), phase_b[0]);
radr_c_b <= radr_c_b+(`D_RS);
cnt_c_b <= cnt_c_b+1;
c_c_b <= (cnt_c_b>=`WAYP_CN_);
end
16'h0800: begin
d_initadr <= mux32(radr_d_b, (radr_d_b | (`SORT_ELM>>1)), phase_b[0]);
radr_d_b <= radr_d_b+(`D_RS);
cnt_d_b <= cnt_d_b+1;
c_d_b <= (cnt_d_b>=`WAYP_CN_);
end
16'h1000: begin
d_initadr <= mux32(radr_e_b, (radr_e_b | (`SORT_ELM>>1)), phase_b[0]);
radr_e_b <= radr_e_b+(`D_RS);
cnt_e_b <= cnt_e_b+1;
c_e_b <= (cnt_e_b>=`WAYP_CN_);
end
16'h2000: begin
d_initadr <= mux32(radr_f_b, (radr_f_b | (`SORT_ELM>>1)), phase_b[0]);
radr_f_b <= radr_f_b+(`D_RS);
cnt_f_b <= cnt_f_b+1;
c_f_b <= (cnt_f_b>=`WAYP_CN_);
end
16'h4000: begin
d_initadr <= mux32(radr_g_b, (radr_g_b | (`SORT_ELM>>1)), phase_b[0]);
radr_g_b <= radr_g_b+(`D_RS);
cnt_g_b <= cnt_g_b+1;
c_g_b <= (cnt_g_b>=`WAYP_CN_);
end
16'h8000: begin
d_initadr <= mux32(radr_h_b, (radr_h_b | (`SORT_ELM>>1)), phase_b[0]);
radr_h_b <= radr_h_b+(`D_RS);
cnt_h_b <= cnt_h_b+1;
c_h_b <= (cnt_h_b>=`WAYP_CN_);
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_ta <= req_a;
req_tb <= req_b;
end
end
7: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_a; //
w_addr_a <= w_addr_a + (`D_WS); // address for the next write
end
end
8: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_b; //
w_addr_b <= w_addr_b + (`D_WS); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/**********************************************************************************************/
always @(posedge CLK) begin
// Stage 0
////////////////////////////////////
dout_ta <= mux512(d_dout, stnet_dout, phase_zero);
dout_tb <= mux512(d_dout, stnet_dout, phase_zero);
doen_ta <= mux1(d_douten, stnet_douten, phase_zero);
doen_tb <= mux1(d_douten, stnet_douten, phase_zero);
req_taa <= req_ta;
req_tba <= req_tb;
// Stage 1
////////////////////////////////////
dout_tc <= dout_ta;
dout_td <= dout_ta;
dout_te <= dout_tb;
dout_tf <= dout_tb;
doen_tc <= doen_ta;
doen_td <= doen_ta;
doen_te <= doen_tb;
doen_tf <= doen_tb;
req_tab <= req_taa;
req_tbb <= req_tba;
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
// for plast
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
plast_a <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) plast_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
plast_b <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) plast_b <= 1;
end
end
// for elem
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
elem_a <= 0;
end else begin
case ({OB_deq_a, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= elem_a + 16;
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({OB_deq_b, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= elem_b + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==8);
always @(posedge CLK) iter_done_b <= (ecnt_b==8);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= (ecnt_a==8) || pchange_a;
always @(posedge CLK) irst_b <= (ecnt_b==8) || pchange_b;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= RSTa || (ecnt_a==8) || (elem_a==`SRTP_ELM);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==8) || (elem_b==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq_a) ecnt_a <= ecnt_a - 4;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq_b) ecnt_b <= ecnt_b - 4;
end
end
// for phase zero
// ###########################################################################
always @(posedge CLK) phase_zero <= ((phase_a == 0) || (phase_b == 0));
// for last phase
// ###########################################################################
always @(posedge CLK) last_phase <= ((phase_a == `LAST_PHASE) && (phase_b == `LAST_PHASE));
// for debug
// ###########################################################################
// (* mark_debug = "true" *) reg [31:0] dcnt;
// always @(posedge CLK) begin
// if (RST) begin
// dcnt <= 0;
// end else begin
// case ({F01_deq, (dcnt==`SORT_ELM)})
// 2'b01: dcnt <= 0;
// 2'b10: dcnt <= dcnt + 4;
// endcase
// end
// end
endmodule // CORE
/**************************************************************************************************/
`default_nettype wire
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXC Engine (Ultrascale) takes a single stream of
// AXI packets and provides the completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module rxc_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10,
// Number of data pipeline registers for metadata and data stages
parameter C_RX_META_STAGES = 0,
parameter C_RX_DATA_STAGES = 1
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RC
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP
);
// Width of the Byte Enable Shift register
localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 0;
localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
localparam C_RX_METADW0_CYCLE = (`UPKT_RXC_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`UPKT_RXC_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW2_CYCLE = (`UPKT_RXC_METADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXC_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW2_I%C_PCI_DATA_WIDTH);
localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
// Mask width of the calculated SOF/EOF fields
localparam C_OFFSET_WIDTH = clog2(C_PCI_DATA_WIDTH/32);
wire wMAxisRcSop;
wire wMAxisRcTlast;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire wRxcDataValid;
wire wRxcDataReady; // Pinned High
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataEndFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire wRxcDataStartFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
wire [`SIG_CPLID_W-1:0] wRxcMetaCompleterId;
wire [`UPKT_RXC_MAXHDR_W-1:0] wRxcHdr;
wire [`SIG_TYPE_W-1:0] wRxcType;
wire [`SIG_BARDECODE_W-1:0] wRxcBarDecoded;
wire [`UPKT_RXC_MAXHDR_W-1:0] wHdr;
wire [`SIG_TYPE_W-1:0] wType;
wire wHasPayload;
wire _wEndFlag;
wire wEndFlag;
wire wEndFlagLastCycle;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wStartFlag;
wire wStartFlag;
wire [1:0] wStartFlags;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [C_OFFSET_WIDTH-1:0] wOffsetMask;
reg rValid,_rValid;
assign wMAxisRcSop = M_AXIS_RC_TUSER[`UPKT_RC_TUSER_SOP_I];
assign wMAxisRcTlast = M_AXIS_RC_TLAST;
// We assert the end flag on the last cycle of a packet, however on single
// cycle packets we need to check that there wasn't an end flag last cycle
// (because wStartFlag will take priority when setting rValid) so we can
// deassert rValid if necessary.
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
/* verilator lint_off WIDTH */
assign wStartOffset = 3;
assign wEndOffset = wHdr[`UPKT_RXC_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXC_MAXHDR_W-32)/32);
/* verilator lint_on WIDTH */
// Output assignments. See the header file derived from the user
// guide for indices.
assign RXC_META_LENGTH = wRxcHdr[`UPKT_RXC_LENGTH_I+:`SIG_LEN_W];
//assign RXC_META_ATTR = wRxcHdr[`UPKT_RXC_ATTR_R];
//assign RXC_META_TC = wRxcHdr[`UPKT_RXC_TC_R];
assign RXC_META_TAG = wRxcHdr[`UPKT_RXC_TAG_R];
assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_ADDR = wRxcHdr[(`UPKT_RXC_ADDRLOW_I) +: `SIG_LOWADDR_W];
assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
assign RXC_DATA_START_OFFSET = {C_PCI_DATA_WIDTH > 64, 1'b1};
assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
assign RXC_DATA_VALID = wRxcDataValid;
assign RXC_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXC_META_TYPE = wRxcType;
assign RXC_META_BYTES_REMAINING = wRxcHdr[`UPKT_RXC_BYTECNT_I +: `SIG_BYTECNT_W];
assign RXC_META_COMPLETER_ID = wRxcHdr[`UPKT_RXC_CPLID_R];
assign RXC_META_EP = wRxcHdr[`UPKT_RXC_EP_R];
assign M_AXIS_RC_TREADY = 1'b1;
assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
assign wType = (wHasPayload)? `TRLS_CPL_WD: `TRLS_CPL_ND;
generate
if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[0] = 0;
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1];
//assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end else begin // 256
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(RST_IN) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (1'b0)
/*AUTOINSTPARAM*/)
start_flag_register
(
// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (32))
meta_DW2_register
(
// Outputs
.RD_DATA (wHdr[95:64]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW2_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW2_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (32+1))
meta_DW1_register
(
// Outputs
.RD_DATA ({wHdr[63:32],wHasPayload}),
// Inputs
.WR_DATA ({wRxSrData[C_RX_METADW1_INDEX +: 32],wRxSrData[C_RX_METADW1_INDEX +: `UPKT_LEN_W] != 0}),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (32))
metadata_DW0_register
(
// Outputs
.RD_DATA (wHdr[31:0]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (M_AXIS_RC_TDATA),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (wMAxisRcSop & M_AXIS_RC_TVALID),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// End Flag Shift Register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (wMAxisRcTlast),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Data Valid Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (M_AXIS_RC_TVALID),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wHasPayload}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxcDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wHasPayload),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXC_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxcDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end
endgenerate
// Shift register for input data with output taps for each delayed
// cycle.
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`UPKT_RXC_MAXHDR_W + 2*(1 + clog2(C_PCI_DATA_WIDTH/32))+`SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxcHdr,wRxcDataStartFlag,wRxcDataStartOffset,wRxcDataEndFlag,wRxcDataEndOffset,wRxcType}),
.RD_DATA_VALID (wRxcDataValid),
// Inputs
.WR_DATA ({wHdr,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wType}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_SYMBOL_V
`define SKY130_FD_SC_HD__BUF_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__buf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_SYMBOL_V
|
module branchhistorytable(clk,pcsrcd,pcd,pcbranchd,originalpc,pcnext,clrbp);
input clk;
input [1:0] pcsrcd;
input [31:0] originalpc, pcbranchd, pcd;
output reg [31:0] pcnext;
output reg clrbp;
reg [65:0] branchtargetbuffer[127:0];
reg [31:0] pcstorage;
//66 bits, first 32 bits address, next 32 bits predicted address, 2 bits T/NT
integer i;
reg foundflag;
initial begin
for (i=0; i<128; i=i+1) begin
branchtargetbuffer[i] = 66'b0;
end
end
integer j=0;
integer count=0;
integer recorder;
always @(*) begin
// IF Stage
foundflag = 1'b0;
for (i=0; i<128; i=i+1) begin
if (originalpc==branchtargetbuffer[i][65:34] ) begin
if (!branchtargetbuffer[i][1]) begin
pcstorage = originalpc;
pcnext = branchtargetbuffer[i][33:2];
end
foundflag = 1'b1;
recorder = i;
end
end
// ID and EX Stages
// found? - Yes
if (foundflag) begin
if (pcsrcd[0]) begin//branch taken
clrbp = 1'b0;
// Update the existing buffer to a higher taken
case(branchtargetbuffer[recorder][1:0])
2'b00: branchtargetbuffer[recorder][1:0] = 2'b00;
2'b01: branchtargetbuffer[recorder][1:0] = 2'b00;
2'b10: branchtargetbuffer[recorder][1:0] = 2'b01;
2'b11: branchtargetbuffer[recorder][1:0] = 2'b10;
endcase
end
else begin//branch not taken
// Put back old count and issue a clr signal to pipefd
clrbp = 1'b1;
pcnext = pcstorage;
// Update the existing buffer to a lower taken
case(branchtargetbuffer[recorder][1:0])
2'b00: branchtargetbuffer[recorder][1:0] = 2'b01;
2'b01: branchtargetbuffer[recorder][1:0] = 2'b10;
2'b10: branchtargetbuffer[recorder][1:0] = 2'b11;
2'b11: branchtargetbuffer[recorder][1:0] = 2'b11;
endcase
end
end
// found? - No
else begin
if (pcsrcd[0]) begin//branch taken
// Write into buffer at next available spot
branchtargetbuffer[count][1:0] = 2'b00;
branchtargetbuffer[count][33:2] = pcbranchd;
branchtargetbuffer[count][65:34] = pcd;
pcnext = pcbranchd;
clrbp = 1'b0;
count = count + 1;
if (count > 127)
count = 0;
end
else begin//branch not taken
clrbp = 1'b0;
pcnext = originalpc;
end
end
end
endmodule
|
// file: Clock_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
`timescale 1ns/1ps
`default_nettype none
module test;
localparam NUM_FF = 4;
`include "../../../../library/tbassert.v"
reg clk = 0;
reg rx = 1;
reg [13:0] sw = 0;
reg ce = 0;
reg sr = 0;
wire tx;
wire [15:0] led;
// clock generation
always #1 clk=~clk;
top unt(
.clk(clk),
.rx(rx),
.tx(tx),
.sw({sr, ce, sw}),
.led(led)
);
wire [4*NUM_FF-1:0] D;
wire [NUM_FF-1:0] Q_vcc_gnd;
wire [NUM_FF-1:0] Q_s_gnd;
wire [NUM_FF-1:0] Q_s_s;
wire [NUM_FF-1:0] Q_vcc_s;
assign Q_vcc_gnd[0] = led[0];
assign Q_s_gnd[0] = led[1];
assign Q_s_s[0] = led[2];
assign Q_vcc_s[0] = led[3];
assign Q_vcc_gnd[1] = led[4];
assign Q_vcc_gnd[NUM_FF-1] = led[5];
assign Q_s_gnd[NUM_FF-1] = led[6];
assign Q_s_s[NUM_FF-1] = led[7];
assign Q_vcc_s[NUM_FF-1] = led[8];
wire xorQ = led[9];
wire orQ = led[10];
wire andQ = led[11];
genvar i;
generate for(i = 0; i < NUM_FF; i=i+1) begin:ff
assign D[4*i+0] = sw[(4*i+0) % 14];
assign D[4*i+1] = sw[(4*i+1) % 14];
assign D[4*i+2] = sw[(4*i+2) % 14];
assign D[4*i+3] = sw[(4*i+3) % 14];
end endgenerate
wire xorD = ^D;
wire orD = |D;
wire andD = &D;
always begin
#1
$monitor("1:%d %d %d %d %d %d %d %d %d %d %d %d %d", $time, clk, sw[14], led[0], led[1], led[2], led[3], led[9], xorD, led[10], orD, led[11], andD);
end
initial begin
$dumpfile("testbench_ff_ce_sr_4_tb.vcd");
$dumpvars;
#1.1 // 1
tbassert(clk, "Clock!");
tbassert(!Q_vcc_gnd[0], "!Q_vcc_gnd[0]");
tbassert(!Q_s_gnd[0], "!Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(!xorQ, "^Q == 0");
tbassert(!orQ, "|Q == 0");
tbassert(!andQ, "&Q == 0");
tbassert(xorQ == xorD, "^Q == xorD");
// Test CE
#1 // 2
tbassert(!clk, "Clock!");
sw[0] = 1;
sw[1] = 1;
sw[2] = 1;
sw[3] = 1;
#1 // 3
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(!Q_s_gnd[0], "!Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 4
ce = 1;
#1 // 5
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 6
ce = 0;
sw[0] = 0;
sw[1] = 0;
sw[2] = 0;
sw[3] = 0;
#1 // 7
tbassert(!Q_vcc_gnd[0], "!Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 8
ce = 1;
#1 // 9
tbassert(!Q_vcc_gnd[0], "!Q_vcc_gnd[0]");
tbassert(!Q_s_gnd[0], "!Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(!orQ, "|Q == 0");
tbassert(!andQ, "&Q == 0");
// Test SR
#1 // 10
sw[0] = 1;
sw[1] = 1;
sw[2] = 1;
sw[3] = 1;
#1 // 11
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 12
sr = 1;
#1 // 13
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(!Q_vcc_s[0], "!Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 14
ce = 0;
sr = 0;
#1 // 15
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(!Q_s_s[0], "!Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 16
ce = 1;
#1 // 17
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(!andQ, "&Q == 0");
#1 // 18
sw[13:0] = 14'b11_1111_1111_1111;
#1 // 19
tbassert(Q_vcc_gnd[0], "Q_vcc_gnd[0]");
tbassert(Q_s_gnd[0], "Q_s_gnd[0]");
tbassert(Q_s_s[0], "Q_s_s[0]");
tbassert(Q_vcc_s[0], "Q_vcc_s[0]");
tbassert(Q_vcc_gnd[1], "Q_vcc_gnd[1]");
tbassert(Q_vcc_gnd[NUM_FF-1], "Q_vcc_gnd[-1]");
tbassert(Q_s_gnd[NUM_FF-1], "Q_s_gnd[-1]");
tbassert(Q_s_s[NUM_FF-1], "Q_s_s[-1]");
tbassert(Q_vcc_s[NUM_FF-1], "Q_vcc_s[-1]");
tbassert(xorQ == xorD, "^Q == xorD");
tbassert(orQ, "|Q == 1");
tbassert(andQ, "&Q == 1");
#1 $finish;
end
endmodule
|
`define Rotary_NOP 4'h0
`define Rotary_RDLS 4'h1
`define Rotary_RDRS 4'h2
`define Rotary_State_Reset 2'h0
`define Rotary_State_Ready 2'h1
`define Rotary_State_Error 2'h2
module Rotary(clock,reset,inst,inst_en,rotary,rotary_left_status,rotary_right_status);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
input wire [1:0] rotary;
output wire rotary_left_status;
output wire rotary_right_status;
reg [1:0] s_State;
reg s_IntRotaryLeftStatus;
reg s_OutRotaryLeftStatus;
reg s_IntRotaryRightStatus;
reg s_OutRotaryRightStatus;
wire [3:0] w_InstCode;
wire rotaryint_rotary_left;
wire rotaryint_rotary_right;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign rotary_left_status = s_OutRotaryLeftStatus;
assign rotary_right_status = s_OutRotaryRightStatus;
assign w_InstCode = inst[11:8];
RotaryInterface
rotaryint (.clock(clock),
.reset(reset),
.rotary(rotary),
.rotary_left(rotaryint_rotary_left),
.rotary_right(rotaryint_rotary_right));
always @ (posedge clock) begin
if (reset) begin
s_State <= `Rotary_State_Reset;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
else begin
case (s_State)
`Rotary_State_Reset: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
`Rotary_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`Rotary_NOP: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | s_IntRotaryLeftStatus;
s_OutRotaryLeftStatus <= s_OutRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | s_IntRotaryRightStatus;
s_OutRotaryRightStatus <= s_OutRotaryRightStatus;
end
`Rotary_RDLS: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | 0;
s_OutRotaryLeftStatus <= s_IntRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | s_IntRotaryRightStatus;
s_OutRotaryRightStatus <= s_OutRotaryRightStatus;
end
`Rotary_RDRS: begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | s_IntRotaryLeftStatus;
s_OutRotaryLeftStatus <= s_OutRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | 0;
s_OutRotaryRightStatus <= s_IntRotaryRightStatus;
end
default: begin
s_State <= `Rotary_State_Error;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `Rotary_State_Ready;
s_IntRotaryLeftStatus <= rotaryint_rotary_left | s_IntRotaryLeftStatus;
s_OutRotaryLeftStatus <= s_OutRotaryLeftStatus;
s_IntRotaryRightStatus <= rotaryint_rotary_right | s_IntRotaryRightStatus;
s_OutRotaryRightStatus <= s_OutRotaryRightStatus;
end // else: !if(inst_en)
end // case: `Rotary_State_Ready
`Rotary_State_Error: begin
s_State <= `Rotary_State_Error;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
default: begin
s_State <= `Rotary_State_Error;
s_IntRotaryLeftStatus <= 0;
s_OutRotaryLeftStatus <= 0;
s_IntRotaryRightStatus <= 0;
s_OutRotaryRightStatus <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`Rotary_NOP: begin
$sformat(d_Input,"EN NOP");
end
`Rotary_RDLS: begin
$sformat(d_Input,"EN RDLS");
end
`Rotary_RDRS: begin
$sformat(d_Input,"EN RDRS");
end
default: begin
$sformat(d_Input,"EN (? %2X)",inst[7:0]);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`Rotary_State_Reset: begin
$sformat(d_State,"X");
end
`Rotary_State_Ready: begin
case ({s_IntRotaryLeftStatus,s_OutRotaryLeftStatus,s_IntRotaryRightStatus,s_OutRotaryRightStatus})
4'b0000: begin
$sformat(d_State,"R F F F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0001: begin
$sformat(d_State,"R F F F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0010: begin
$sformat(d_State,"R F F T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0011: begin
$sformat(d_State,"R F F T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0100: begin
$sformat(d_State,"R F T F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0101: begin
$sformat(d_State,"R F T F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0110: begin
$sformat(d_State,"R F T T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b0111: begin
$sformat(d_State,"R F T T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1000: begin
$sformat(d_State,"R T F F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1001: begin
$sformat(d_State,"R T F F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1010: begin
$sformat(d_State,"R T F T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1011: begin
$sformat(d_State,"R T F T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1100: begin
$sformat(d_State,"R T T F F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1101: begin
$sformat(d_State,"R T T F T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1110: begin
$sformat(d_State,"R T T T F %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
4'b1111: begin
$sformat(d_State,"R T T T T %2B %1B %1B",rotary,rotaryint_rotary_left,rotaryint_rotary_right);
end
endcase // case ({s_IntRotaryLeftStatus,s_OutRotaryLeftStatus,s_IntRotaryRightStatus,s_OutRotaryRightStatus})
end // case: `Rotary_State_Ready
`Rotary_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // Rotary
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Tree Matrix Arbiter
*
* - 'multistage' parameter - see description in matrix_arbiter.v
*
* The tree arbiter splits the request vector into groups, performing arbitration
* simultaneously within groups and between groups. Note this has implications
* for fairness.
*
* Only builds one level of a tree
*
*/
module NW_tree_arbiter (request, req_priority, grant, success, clk, rst_n);
parameter multistage=0;
parameter size=20;
parameter groupsize=4;
parameter numgroups=size/groupsize;
parameter priority_support = 0;
//parameter type priority_type = bit unsigned [3:0]; // e.g. 16-levels of priority
input [size-1:0] request;
input priority_type req_priority [numgroups-1:0][groupsize-1:0]; // optional
output [size-1:0] grant;
input success;
input clk, rst_n;
logic [size-1:0] intra_group_grant;
logic [numgroups-1:0] group_grant, any_group_request;
logic [numgroups-1:0] current_group_success, last_group_success;
logic [numgroups-1:0] group_success;
priority_type max_priority [numgroups-1:0];
genvar i;
generate
for (i=0; i<numgroups; i=i+1) begin:arbiters
if (multistage==0) begin
//
// group_arbs need to be multistage=1, as group may not get granted
//
matrix_arb #(.size(groupsize),
.multistage(1),
//.priority_type(priority_type),
.priority_support(priority_support)) arb
(.request(request[(i+1)*groupsize-1:i*groupsize]),
.req_priority(req_priority[i]),
.max_priority(max_priority[i]),
.grant(intra_group_grant[(i+1)*groupsize-1:i*groupsize]),
.success(group_success[i]),
.clk, .rst_n);
end else begin
matrix_arb #(.size(groupsize),
.multistage(multistage),
// .priority_type(priority_type),
.priority_support(priority_support)) arb
(.request(request[(i+1)*groupsize-1:i*groupsize]),
.req_priority(req_priority[i]),
.max_priority(max_priority[i]),
.grant(intra_group_grant[(i+1)*groupsize-1:i*groupsize]),
.success(group_success[i] & success),
// .success('1),
.clk, .rst_n);
end
assign any_group_request[i] = |request[(i+1)*groupsize-1:i*groupsize];
assign grant[(i+1)*groupsize-1:i*groupsize]=
intra_group_grant[(i+1)*groupsize-1:i*groupsize] & {groupsize{group_grant[i]}};
//.success(any_group_request[i] & group_grant[i] & success),
//assign current_group_success[i]=|grant[(i+1)*groupsize-1:i*groupsize];
assign current_group_success[i]= group_grant[i];
end
if (multistage==2) begin
always@(posedge clk) begin
if (!rst_n) begin
last_group_success<='0;
end else begin
last_group_success<=current_group_success;
end
end
assign group_success=last_group_success;
end else begin
assign group_success=current_group_success;
end
endgenerate
matrix_arb #(.size(numgroups),
.multistage(multistage),
//.priority_type(priority_type),
.priority_support(priority_support)) group_arb
(.request(any_group_request),
.req_priority(max_priority),
.grant(group_grant),
.success(success),
.clk, .rst_n);
endmodule // tree_arbiter
|
// Video_System.v
// Generated using ACDS version 12.1sp1 243 at 2015.02.09.16:02:18
`timescale 1 ps / 1 ps
module Video_System (
output wire VGA_CLK_from_the_VGA_Controller, // VGA_Controller_external_interface.CLK
output wire VGA_HS_from_the_VGA_Controller, // .HS
output wire VGA_VS_from_the_VGA_Controller, // .VS
output wire VGA_BLANK_from_the_VGA_Controller, // .BLANK
output wire VGA_SYNC_from_the_VGA_Controller, // .SYNC
output wire [9:0] VGA_R_from_the_VGA_Controller, // .R
output wire [9:0] VGA_G_from_the_VGA_Controller, // .G
output wire [9:0] VGA_B_from_the_VGA_Controller, // .B
input wire clk_0, // clk_0_clk_in.clk
input wire reset_n, // clk_0_clk_in_reset.reset_n
inout wire I2C_SDAT_to_and_from_the_AV_Config, // AV_Config_external_interface.SDAT
output wire I2C_SCLK_from_the_AV_Config, // .SCLK
inout wire [15:0] SRAM_DQ_to_and_from_the_Pixel_Buffer, // Pixel_Buffer_external_interface.DQ
output wire [17:0] SRAM_ADDR_from_the_Pixel_Buffer, // .ADDR
output wire SRAM_LB_N_from_the_Pixel_Buffer, // .LB_N
output wire SRAM_UB_N_from_the_Pixel_Buffer, // .UB_N
output wire SRAM_CE_N_from_the_Pixel_Buffer, // .CE_N
output wire SRAM_OE_N_from_the_Pixel_Buffer, // .OE_N
output wire SRAM_WE_N_from_the_Pixel_Buffer, // .WE_N
input wire TD_CLK27_to_the_Video_In_Decoder, // Video_In_Decoder_external_interface.TD_CLK27
input wire [7:0] TD_DATA_to_the_Video_In_Decoder, // .TD_DATA
input wire TD_HS_to_the_Video_In_Decoder, // .TD_HS
input wire TD_VS_to_the_Video_In_Decoder, // .TD_VS
output wire TD_RESET_from_the_Video_In_Decoder, // .TD_RESET
output wire overflow_flag_from_the_Video_In_Decoder // .overflow_flag
);
wire pixel_scaler_avalon_scaler_source_endofpacket; // Pixel_Scaler:stream_out_endofpacket -> Dual_Clock_FIFO:stream_in_endofpacket
wire pixel_scaler_avalon_scaler_source_valid; // Pixel_Scaler:stream_out_valid -> Dual_Clock_FIFO:stream_in_valid
wire pixel_scaler_avalon_scaler_source_startofpacket; // Pixel_Scaler:stream_out_startofpacket -> Dual_Clock_FIFO:stream_in_startofpacket
wire [29:0] pixel_scaler_avalon_scaler_source_data; // Pixel_Scaler:stream_out_data -> Dual_Clock_FIFO:stream_in_data
wire pixel_scaler_avalon_scaler_source_ready; // Dual_Clock_FIFO:stream_in_ready -> Pixel_Scaler:stream_out_ready
wire pixel_rgb_resampler_avalon_rgb_source_endofpacket; // Pixel_RGB_Resampler:stream_out_endofpacket -> Pixel_Scaler:stream_in_endofpacket
wire pixel_rgb_resampler_avalon_rgb_source_valid; // Pixel_RGB_Resampler:stream_out_valid -> Pixel_Scaler:stream_in_valid
wire pixel_rgb_resampler_avalon_rgb_source_startofpacket; // Pixel_RGB_Resampler:stream_out_startofpacket -> Pixel_Scaler:stream_in_startofpacket
wire [29:0] pixel_rgb_resampler_avalon_rgb_source_data; // Pixel_RGB_Resampler:stream_out_data -> Pixel_Scaler:stream_in_data
wire pixel_rgb_resampler_avalon_rgb_source_ready; // Pixel_Scaler:stream_in_ready -> Pixel_RGB_Resampler:stream_out_ready
wire pixel_buffer_dma_avalon_pixel_source_endofpacket; // Pixel_Buffer_DMA:stream_endofpacket -> Pixel_RGB_Resampler:stream_in_endofpacket
wire pixel_buffer_dma_avalon_pixel_source_valid; // Pixel_Buffer_DMA:stream_valid -> Pixel_RGB_Resampler:stream_in_valid
wire pixel_buffer_dma_avalon_pixel_source_startofpacket; // Pixel_Buffer_DMA:stream_startofpacket -> Pixel_RGB_Resampler:stream_in_startofpacket
wire [15:0] pixel_buffer_dma_avalon_pixel_source_data; // Pixel_Buffer_DMA:stream_data -> Pixel_RGB_Resampler:stream_in_data
wire pixel_buffer_dma_avalon_pixel_source_ready; // Pixel_RGB_Resampler:stream_in_ready -> Pixel_Buffer_DMA:stream_ready
wire dual_clock_fifo_avalon_dc_buffer_source_endofpacket; // Dual_Clock_FIFO:stream_out_endofpacket -> VGA_Controller:endofpacket
wire dual_clock_fifo_avalon_dc_buffer_source_valid; // Dual_Clock_FIFO:stream_out_valid -> VGA_Controller:valid
wire dual_clock_fifo_avalon_dc_buffer_source_startofpacket; // Dual_Clock_FIFO:stream_out_startofpacket -> VGA_Controller:startofpacket
wire [29:0] dual_clock_fifo_avalon_dc_buffer_source_data; // Dual_Clock_FIFO:stream_out_data -> VGA_Controller:data
wire dual_clock_fifo_avalon_dc_buffer_source_ready; // VGA_Controller:ready -> Dual_Clock_FIFO:stream_out_ready
wire video_in_decoder_avalon_decoder_source_endofpacket; // Video_In_Decoder:stream_out_endofpacket -> Chroma_Resampler:stream_in_endofpacket
wire video_in_decoder_avalon_decoder_source_valid; // Video_In_Decoder:stream_out_valid -> Chroma_Resampler:stream_in_valid
wire video_in_decoder_avalon_decoder_source_startofpacket; // Video_In_Decoder:stream_out_startofpacket -> Chroma_Resampler:stream_in_startofpacket
wire [15:0] video_in_decoder_avalon_decoder_source_data; // Video_In_Decoder:stream_out_data -> Chroma_Resampler:stream_in_data
wire video_in_decoder_avalon_decoder_source_ready; // Chroma_Resampler:stream_in_ready -> Video_In_Decoder:stream_out_ready
wire chroma_resampler_avalon_chroma_source_endofpacket; // Chroma_Resampler:stream_out_endofpacket -> Color_Space_Converter:stream_in_endofpacket
wire chroma_resampler_avalon_chroma_source_valid; // Chroma_Resampler:stream_out_valid -> Color_Space_Converter:stream_in_valid
wire chroma_resampler_avalon_chroma_source_startofpacket; // Chroma_Resampler:stream_out_startofpacket -> Color_Space_Converter:stream_in_startofpacket
wire [23:0] chroma_resampler_avalon_chroma_source_data; // Chroma_Resampler:stream_out_data -> Color_Space_Converter:stream_in_data
wire chroma_resampler_avalon_chroma_source_ready; // Color_Space_Converter:stream_in_ready -> Chroma_Resampler:stream_out_ready
wire color_space_converter_avalon_csc_source_endofpacket; // Color_Space_Converter:stream_out_endofpacket -> Video_RGB_Resampler:stream_in_endofpacket
wire color_space_converter_avalon_csc_source_valid; // Color_Space_Converter:stream_out_valid -> Video_RGB_Resampler:stream_in_valid
wire color_space_converter_avalon_csc_source_startofpacket; // Color_Space_Converter:stream_out_startofpacket -> Video_RGB_Resampler:stream_in_startofpacket
wire [23:0] color_space_converter_avalon_csc_source_data; // Color_Space_Converter:stream_out_data -> Video_RGB_Resampler:stream_in_data
wire color_space_converter_avalon_csc_source_ready; // Video_RGB_Resampler:stream_in_ready -> Color_Space_Converter:stream_out_ready
wire video_rgb_resampler_avalon_rgb_source_endofpacket; // Video_RGB_Resampler:stream_out_endofpacket -> Video_Clipper:stream_in_endofpacket
wire video_rgb_resampler_avalon_rgb_source_valid; // Video_RGB_Resampler:stream_out_valid -> Video_Clipper:stream_in_valid
wire video_rgb_resampler_avalon_rgb_source_startofpacket; // Video_RGB_Resampler:stream_out_startofpacket -> Video_Clipper:stream_in_startofpacket
wire [15:0] video_rgb_resampler_avalon_rgb_source_data; // Video_RGB_Resampler:stream_out_data -> Video_Clipper:stream_in_data
wire video_rgb_resampler_avalon_rgb_source_ready; // Video_Clipper:stream_in_ready -> Video_RGB_Resampler:stream_out_ready
wire video_clipper_avalon_clipper_source_endofpacket; // Video_Clipper:stream_out_endofpacket -> Video_Scaler:stream_in_endofpacket
wire video_clipper_avalon_clipper_source_valid; // Video_Clipper:stream_out_valid -> Video_Scaler:stream_in_valid
wire video_clipper_avalon_clipper_source_startofpacket; // Video_Clipper:stream_out_startofpacket -> Video_Scaler:stream_in_startofpacket
wire [15:0] video_clipper_avalon_clipper_source_data; // Video_Clipper:stream_out_data -> Video_Scaler:stream_in_data
wire video_clipper_avalon_clipper_source_ready; // Video_Scaler:stream_in_ready -> Video_Clipper:stream_out_ready
wire video_scaler_avalon_scaler_source_endofpacket; // Video_Scaler:stream_out_endofpacket -> Video_DMA:stream_endofpacket
wire video_scaler_avalon_scaler_source_valid; // Video_Scaler:stream_out_valid -> Video_DMA:stream_valid
wire video_scaler_avalon_scaler_source_startofpacket; // Video_Scaler:stream_out_startofpacket -> Video_DMA:stream_startofpacket
wire [15:0] video_scaler_avalon_scaler_source_data; // Video_Scaler:stream_out_data -> Video_DMA:stream_data
wire video_scaler_avalon_scaler_source_ready; // Video_DMA:stream_ready -> Video_Scaler:stream_out_ready
wire clock_signals_sys_clk_clk; // Clock_Signals:sys_clk -> [AV_Config:clk, AV_Config_avalon_av_config_slave_translator:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, CPU:clk, CPU_data_master_translator:clk, CPU_data_master_translator_avalon_universal_master_0_agent:clk, CPU_instruction_master_translator:clk, CPU_instruction_master_translator_avalon_universal_master_0_agent:clk, CPU_jtag_debug_module_translator:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Chroma_Resampler:clk, Color_Space_Converter:clk, Dual_Clock_FIFO:clk_stream_in, Onchip_Memory:clk, Onchip_Memory_s1_translator:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer:clk, Pixel_Buffer_DMA:clk, Pixel_Buffer_DMA_avalon_control_slave_translator:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_RGB_Resampler:clk, Pixel_Scaler:clk, Video_Clipper:clk, Video_DMA:clk, Video_DMA_avalon_dma_control_slave_translator:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Video_DMA_avalon_dma_master_translator:clk, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:clk, Video_In_Decoder:clk, Video_RGB_Resampler:clk, Video_Scaler:clk, addr_router:clk, addr_router_001:clk, addr_router_002:clk, addr_router_003:clk, burst_adapter:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_demux_002:clk, cmd_xbar_demux_003:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, irq_mapper:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, width_adapter:clk, width_adapter_001:clk]
wire clock_signals_vga_clk_clk; // Clock_Signals:VGA_CLK -> [Dual_Clock_FIFO:clk_stream_out, VGA_Controller:clk, rst_controller_001:clk]
wire cpu_instruction_master_waitrequest; // CPU_instruction_master_translator:av_waitrequest -> CPU:i_waitrequest
wire [19:0] cpu_instruction_master_address; // CPU:i_address -> CPU_instruction_master_translator:av_address
wire cpu_instruction_master_read; // CPU:i_read -> CPU_instruction_master_translator:av_read
wire [31:0] cpu_instruction_master_readdata; // CPU_instruction_master_translator:av_readdata -> CPU:i_readdata
wire cpu_data_master_waitrequest; // CPU_data_master_translator:av_waitrequest -> CPU:d_waitrequest
wire [31:0] cpu_data_master_writedata; // CPU:d_writedata -> CPU_data_master_translator:av_writedata
wire [19:0] cpu_data_master_address; // CPU:d_address -> CPU_data_master_translator:av_address
wire cpu_data_master_write; // CPU:d_write -> CPU_data_master_translator:av_write
wire cpu_data_master_read; // CPU:d_read -> CPU_data_master_translator:av_read
wire [31:0] cpu_data_master_readdata; // CPU_data_master_translator:av_readdata -> CPU:d_readdata
wire cpu_data_master_debugaccess; // CPU:jtag_debug_module_debugaccess_to_roms -> CPU_data_master_translator:av_debugaccess
wire [3:0] cpu_data_master_byteenable; // CPU:d_byteenable -> CPU_data_master_translator:av_byteenable
wire pixel_buffer_dma_avalon_pixel_dma_master_waitrequest; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_waitrequest -> Pixel_Buffer_DMA:master_waitrequest
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_address; // Pixel_Buffer_DMA:master_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_address
wire pixel_buffer_dma_avalon_pixel_dma_master_lock; // Pixel_Buffer_DMA:master_arbiterlock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_lock
wire pixel_buffer_dma_avalon_pixel_dma_master_read; // Pixel_Buffer_DMA:master_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_read
wire [15:0] pixel_buffer_dma_avalon_pixel_dma_master_readdata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdata -> Pixel_Buffer_DMA:master_readdata
wire pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdatavalid -> Pixel_Buffer_DMA:master_readdatavalid
wire video_dma_avalon_dma_master_waitrequest; // Video_DMA_avalon_dma_master_translator:av_waitrequest -> Video_DMA:master_waitrequest
wire [15:0] video_dma_avalon_dma_master_writedata; // Video_DMA:master_writedata -> Video_DMA_avalon_dma_master_translator:av_writedata
wire [31:0] video_dma_avalon_dma_master_address; // Video_DMA:master_address -> Video_DMA_avalon_dma_master_translator:av_address
wire video_dma_avalon_dma_master_write; // Video_DMA:master_write -> Video_DMA_avalon_dma_master_translator:av_write
wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // CPU_jtag_debug_module_translator:av_writedata -> CPU:jtag_debug_module_writedata
wire [8:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_address; // CPU_jtag_debug_module_translator:av_address -> CPU:jtag_debug_module_address
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // CPU_jtag_debug_module_translator:av_chipselect -> CPU:jtag_debug_module_select
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_write; // CPU_jtag_debug_module_translator:av_write -> CPU:jtag_debug_module_write
wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // CPU:jtag_debug_module_readdata -> CPU_jtag_debug_module_translator:av_readdata
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // CPU_jtag_debug_module_translator:av_begintransfer -> CPU:jtag_debug_module_begintransfer
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // CPU_jtag_debug_module_translator:av_debugaccess -> CPU:jtag_debug_module_debugaccess
wire [3:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // CPU_jtag_debug_module_translator:av_byteenable -> CPU:jtag_debug_module_byteenable
wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // Onchip_Memory_s1_translator:av_writedata -> Onchip_Memory:writedata
wire [11:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // Onchip_Memory_s1_translator:av_address -> Onchip_Memory:address
wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // Onchip_Memory_s1_translator:av_chipselect -> Onchip_Memory:chipselect
wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // Onchip_Memory_s1_translator:av_clken -> Onchip_Memory:clken
wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // Onchip_Memory_s1_translator:av_write -> Onchip_Memory:write
wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // Onchip_Memory:readdata -> Onchip_Memory_s1_translator:av_readdata
wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // Onchip_Memory_s1_translator:av_byteenable -> Onchip_Memory:byteenable
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata; // Pixel_Buffer_avalon_sram_slave_translator:av_writedata -> Pixel_Buffer:writedata
wire [17:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address; // Pixel_Buffer_avalon_sram_slave_translator:av_address -> Pixel_Buffer:address
wire pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write; // Pixel_Buffer_avalon_sram_slave_translator:av_write -> Pixel_Buffer:write
wire pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read; // Pixel_Buffer_avalon_sram_slave_translator:av_read -> Pixel_Buffer:read
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata; // Pixel_Buffer:readdata -> Pixel_Buffer_avalon_sram_slave_translator:av_readdata
wire pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid; // Pixel_Buffer:readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator:av_readdatavalid
wire [1:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable; // Pixel_Buffer_avalon_sram_slave_translator:av_byteenable -> Pixel_Buffer:byteenable
wire av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest; // AV_Config:waitrequest -> AV_Config_avalon_av_config_slave_translator:av_waitrequest
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata; // AV_Config_avalon_av_config_slave_translator:av_writedata -> AV_Config:writedata
wire [1:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address; // AV_Config_avalon_av_config_slave_translator:av_address -> AV_Config:address
wire av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write; // AV_Config_avalon_av_config_slave_translator:av_write -> AV_Config:write
wire av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read; // AV_Config_avalon_av_config_slave_translator:av_read -> AV_Config:read
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata; // AV_Config:readdata -> AV_Config_avalon_av_config_slave_translator:av_readdata
wire [3:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable; // AV_Config_avalon_av_config_slave_translator:av_byteenable -> AV_Config:byteenable
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata; // Video_DMA_avalon_dma_control_slave_translator:av_writedata -> Video_DMA:slave_writedata
wire [1:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address; // Video_DMA_avalon_dma_control_slave_translator:av_address -> Video_DMA:slave_address
wire video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write; // Video_DMA_avalon_dma_control_slave_translator:av_write -> Video_DMA:slave_write
wire video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read; // Video_DMA_avalon_dma_control_slave_translator:av_read -> Video_DMA:slave_read
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata; // Video_DMA:slave_readdata -> Video_DMA_avalon_dma_control_slave_translator:av_readdata
wire [3:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable; // Video_DMA_avalon_dma_control_slave_translator:av_byteenable -> Video_DMA:slave_byteenable
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_writedata -> Pixel_Buffer_DMA:slave_writedata
wire [1:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_address -> Pixel_Buffer_DMA:slave_address
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_write -> Pixel_Buffer_DMA:slave_write
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_read -> Pixel_Buffer_DMA:slave_read
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata; // Pixel_Buffer_DMA:slave_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator:av_readdata
wire [3:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_byteenable -> Pixel_Buffer_DMA:slave_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // CPU_instruction_master_translator:uav_burstcount -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // CPU_instruction_master_translator:uav_writedata -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // CPU_instruction_master_translator:uav_address -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // CPU_instruction_master_translator:uav_lock -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // CPU_instruction_master_translator:uav_write -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // CPU_instruction_master_translator:uav_read -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // CPU_instruction_master_translator:uav_debugaccess -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // CPU_instruction_master_translator:uav_byteenable -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_instruction_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // CPU_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_data_master_translator:uav_waitrequest
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // CPU_data_master_translator:uav_burstcount -> CPU_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // CPU_data_master_translator:uav_writedata -> CPU_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_address; // CPU_data_master_translator:uav_address -> CPU_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_lock; // CPU_data_master_translator:uav_lock -> CPU_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // CPU_data_master_translator:uav_write -> CPU_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_data_master_translator_avalon_universal_master_0_read; // CPU_data_master_translator:uav_read -> CPU_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // CPU_data_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // CPU_data_master_translator:uav_debugaccess -> CPU_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // CPU_data_master_translator:uav_byteenable -> CPU_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // CPU_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_data_master_translator:uav_readdatavalid
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_waitrequest
wire [1:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_burstcount -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [15:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_writedata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_address
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_lock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_lock
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_write -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_write
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_read
wire [15:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdata
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_debugaccess -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [1:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_byteenable -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdatavalid
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Video_DMA_avalon_dma_master_translator:uav_waitrequest
wire [1:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount; // Video_DMA_avalon_dma_master_translator:uav_burstcount -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [15:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata; // Video_DMA_avalon_dma_master_translator:uav_writedata -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_address; // Video_DMA_avalon_dma_master_translator:uav_address -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_address
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock; // Video_DMA_avalon_dma_master_translator:uav_lock -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_lock
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_write; // Video_DMA_avalon_dma_master_translator:uav_write -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_write
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_read; // Video_DMA_avalon_dma_master_translator:uav_read -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_read
wire [15:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Video_DMA_avalon_dma_master_translator:uav_readdata
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess; // Video_DMA_avalon_dma_master_translator:uav_debugaccess -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [1:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable; // Video_DMA_avalon_dma_master_translator:uav_byteenable -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Video_DMA_avalon_dma_master_translator:uav_readdatavalid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // CPU_jtag_debug_module_translator:uav_waitrequest -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> CPU_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> CPU_jtag_debug_module_translator:uav_writedata
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> CPU_jtag_debug_module_translator:uav_address
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> CPU_jtag_debug_module_translator:uav_write
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> CPU_jtag_debug_module_translator:uav_lock
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> CPU_jtag_debug_module_translator:uav_read
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // CPU_jtag_debug_module_translator:uav_readdata -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // CPU_jtag_debug_module_translator:uav_readdatavalid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> CPU_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> CPU_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Onchip_Memory_s1_translator:uav_waitrequest -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> Onchip_Memory_s1_translator:uav_burstcount
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> Onchip_Memory_s1_translator:uav_writedata
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> Onchip_Memory_s1_translator:uav_address
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> Onchip_Memory_s1_translator:uav_write
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> Onchip_Memory_s1_translator:uav_lock
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> Onchip_Memory_s1_translator:uav_read
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // Onchip_Memory_s1_translator:uav_readdata -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Onchip_Memory_s1_translator:uav_readdatavalid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Onchip_Memory_s1_translator:uav_debugaccess
wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> Onchip_Memory_s1_translator:uav_byteenable
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Pixel_Buffer_avalon_sram_slave_translator:uav_waitrequest -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_avalon_sram_slave_translator:uav_burstcount
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_avalon_sram_slave_translator:uav_writedata
wire [31:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_avalon_sram_slave_translator:uav_address
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_avalon_sram_slave_translator:uav_write
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_avalon_sram_slave_translator:uav_lock
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_avalon_sram_slave_translator:uav_read
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Pixel_Buffer_avalon_sram_slave_translator:uav_readdata -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Pixel_Buffer_avalon_sram_slave_translator:uav_readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_avalon_sram_slave_translator:uav_debugaccess
wire [1:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_avalon_sram_slave_translator:uav_byteenable
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [87:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [87:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // AV_Config_avalon_av_config_slave_translator:uav_waitrequest -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> AV_Config_avalon_av_config_slave_translator:uav_burstcount
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> AV_Config_avalon_av_config_slave_translator:uav_writedata
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_address -> AV_Config_avalon_av_config_slave_translator:uav_address
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_write -> AV_Config_avalon_av_config_slave_translator:uav_write
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_lock -> AV_Config_avalon_av_config_slave_translator:uav_lock
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_read -> AV_Config_avalon_av_config_slave_translator:uav_read
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // AV_Config_avalon_av_config_slave_translator:uav_readdata -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // AV_Config_avalon_av_config_slave_translator:uav_readdatavalid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> AV_Config_avalon_av_config_slave_translator:uav_debugaccess
wire [3:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> AV_Config_avalon_av_config_slave_translator:uav_byteenable
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Video_DMA_avalon_dma_control_slave_translator:uav_waitrequest -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Video_DMA_avalon_dma_control_slave_translator:uav_burstcount
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Video_DMA_avalon_dma_control_slave_translator:uav_writedata
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Video_DMA_avalon_dma_control_slave_translator:uav_address
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Video_DMA_avalon_dma_control_slave_translator:uav_write
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Video_DMA_avalon_dma_control_slave_translator:uav_lock
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Video_DMA_avalon_dma_control_slave_translator:uav_read
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Video_DMA_avalon_dma_control_slave_translator:uav_readdata -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Video_DMA_avalon_dma_control_slave_translator:uav_readdatavalid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Video_DMA_avalon_dma_control_slave_translator:uav_debugaccess
wire [3:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Video_DMA_avalon_dma_control_slave_translator:uav_byteenable
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_waitrequest -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_burstcount
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_writedata
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_address
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_write
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_lock
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_read
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdatavalid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_debugaccess
wire [3:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_byteenable
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [105:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [105:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [104:0] cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [104:0] cpu_data_master_translator_avalon_universal_master_0_agent_cp_data; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> CPU_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [86:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_ready
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
wire [86:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_003:sink_ready -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [104:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [104:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [86:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [104:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [104:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [104:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [86:0] burst_adapter_source0_data; // burst_adapter:source0_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [5:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [AV_Config:reset, AV_Config_avalon_av_config_slave_translator:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, CPU:reset_n, CPU_data_master_translator:reset, CPU_data_master_translator_avalon_universal_master_0_agent:reset, CPU_instruction_master_translator:reset, CPU_instruction_master_translator_avalon_universal_master_0_agent:reset, CPU_jtag_debug_module_translator:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Chroma_Resampler:reset, Color_Space_Converter:reset, Dual_Clock_FIFO:reset_stream_in, Onchip_Memory:reset, Onchip_Memory_s1_translator:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer:reset, Pixel_Buffer_DMA:reset, Pixel_Buffer_DMA_avalon_control_slave_translator:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_RGB_Resampler:reset, Pixel_Scaler:reset, Video_Clipper:reset, Video_DMA:reset, Video_DMA_avalon_dma_control_slave_translator:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Video_DMA_avalon_dma_master_translator:reset, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:reset, Video_In_Decoder:reset, Video_RGB_Resampler:reset, Video_Scaler:reset, addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, width_adapter:reset, width_adapter_001:reset]
wire cpu_jtag_debug_module_reset_reset; // CPU:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [Dual_Clock_FIFO:reset_stream_out, VGA_Controller:reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> Clock_Signals:reset
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [5:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [104:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [5:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [5:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [104:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [5:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_002:sink1_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
wire [86:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_002:sink1_data
wire [5:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_002:sink1_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_002:src0_ready
wire cmd_xbar_demux_003_src0_endofpacket; // cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_002:sink2_endofpacket
wire cmd_xbar_demux_003_src0_valid; // cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_002:sink2_valid
wire cmd_xbar_demux_003_src0_startofpacket; // cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_002:sink2_startofpacket
wire [86:0] cmd_xbar_demux_003_src0_data; // cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_002:sink2_data
wire [5:0] cmd_xbar_demux_003_src0_channel; // cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_002:sink2_channel
wire cmd_xbar_demux_003_src0_ready; // cmd_xbar_mux_002:sink2_ready -> cmd_xbar_demux_003:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [104:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [5:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [104:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [5:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [104:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [5:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [104:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [5:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_002_src1_endofpacket; // rsp_xbar_demux_002:src1_endofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_002_src1_valid; // rsp_xbar_demux_002:src1_valid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_002_src1_startofpacket; // rsp_xbar_demux_002:src1_startofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [86:0] rsp_xbar_demux_002_src1_data; // rsp_xbar_demux_002:src1_data -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_demux_002_src1_channel; // rsp_xbar_demux_002:src1_channel -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_002_src2_endofpacket; // rsp_xbar_demux_002:src2_endofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_002_src2_valid; // rsp_xbar_demux_002:src2_valid -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_002_src2_startofpacket; // rsp_xbar_demux_002:src2_startofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [86:0] rsp_xbar_demux_002_src2_data; // rsp_xbar_demux_002:src2_data -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_demux_002_src2_channel; // rsp_xbar_demux_002:src2_channel -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [104:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
wire [5:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [104:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
wire [5:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [104:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [5:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [104:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [5:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [104:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [104:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
wire [5:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [104:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_001_src_ready; // CPU_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [86:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
wire [5:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
wire rsp_xbar_demux_002_src1_ready; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_002:src1_ready
wire addr_router_003_src_endofpacket; // addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
wire addr_router_003_src_valid; // addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
wire addr_router_003_src_startofpacket; // addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
wire [86:0] addr_router_003_src_data; // addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
wire [5:0] addr_router_003_src_channel; // addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
wire addr_router_003_src_ready; // cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
wire rsp_xbar_demux_002_src2_ready; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_002:src2_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [104:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [5:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [104:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [104:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [5:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_mux_002_src_endofpacket; // cmd_xbar_mux_002:src_endofpacket -> burst_adapter:sink0_endofpacket
wire cmd_xbar_mux_002_src_valid; // cmd_xbar_mux_002:src_valid -> burst_adapter:sink0_valid
wire cmd_xbar_mux_002_src_startofpacket; // cmd_xbar_mux_002:src_startofpacket -> burst_adapter:sink0_startofpacket
wire [86:0] cmd_xbar_mux_002_src_data; // cmd_xbar_mux_002:src_data -> burst_adapter:sink0_data
wire [5:0] cmd_xbar_mux_002_src_channel; // cmd_xbar_mux_002:src_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_002_src_ready; // burst_adapter:sink0_ready -> cmd_xbar_mux_002:src_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [86:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [5:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_demux_001_src3_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [104:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [5:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_001_src4_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [104:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [5:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [104:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [5:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> width_adapter:in_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> width_adapter:in_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> width_adapter:in_startofpacket
wire [104:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> width_adapter:in_data
wire [5:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> width_adapter:in_channel
wire cmd_xbar_demux_001_src2_ready; // width_adapter:in_ready -> cmd_xbar_demux_001:src2_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> cmd_xbar_mux_002:sink0_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
wire [86:0] width_adapter_src_data; // width_adapter:out_data -> cmd_xbar_mux_002:sink0_data
wire width_adapter_src_ready; // cmd_xbar_mux_002:sink0_ready -> width_adapter:out_ready
wire [5:0] width_adapter_src_channel; // width_adapter:out_channel -> cmd_xbar_mux_002:sink0_channel
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> width_adapter_001:in_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> width_adapter_001:in_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> width_adapter_001:in_startofpacket
wire [86:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> width_adapter_001:in_data
wire [5:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> width_adapter_001:in_channel
wire rsp_xbar_demux_002_src0_ready; // width_adapter_001:in_ready -> rsp_xbar_demux_002:src0_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_mux_001:sink2_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [104:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_mux_001:sink2_data
wire width_adapter_001_src_ready; // rsp_xbar_mux_001:sink2_ready -> width_adapter_001:out_ready
wire [5:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_mux_001:sink2_channel
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> CPU:d_irq
Video_System_Onchip_Memory onchip_memory (
.clk (clock_signals_sys_clk_clk), // clk1.clk
.address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
Video_System_Dual_Clock_FIFO dual_clock_fifo (
.clk_stream_in (clock_signals_sys_clk_clk), // clock_stream_in.clk
.reset_stream_in (rst_controller_reset_out_reset), // clock_stream_in_reset.reset
.clk_stream_out (clock_signals_vga_clk_clk), // clock_stream_out.clk
.reset_stream_out (rst_controller_001_reset_out_reset), // clock_stream_out_reset.reset
.stream_in_ready (pixel_scaler_avalon_scaler_source_ready), // avalon_dc_buffer_sink.ready
.stream_in_startofpacket (pixel_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_in_endofpacket (pixel_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_scaler_avalon_scaler_source_valid), // .valid
.stream_in_data (pixel_scaler_avalon_scaler_source_data), // .data
.stream_out_ready (dual_clock_fifo_avalon_dc_buffer_source_ready), // avalon_dc_buffer_source.ready
.stream_out_startofpacket (dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.stream_out_endofpacket (dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_out_valid (dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.stream_out_data (dual_clock_fifo_avalon_dc_buffer_source_data) // .data
);
Video_System_Pixel_Buffer pixel_buffer (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.SRAM_DQ (SRAM_DQ_to_and_from_the_Pixel_Buffer), // external_interface.export
.SRAM_ADDR (SRAM_ADDR_from_the_Pixel_Buffer), // .export
.SRAM_LB_N (SRAM_LB_N_from_the_Pixel_Buffer), // .export
.SRAM_UB_N (SRAM_UB_N_from_the_Pixel_Buffer), // .export
.SRAM_CE_N (SRAM_CE_N_from_the_Pixel_Buffer), // .export
.SRAM_OE_N (SRAM_OE_N_from_the_Pixel_Buffer), // .export
.SRAM_WE_N (SRAM_WE_N_from_the_Pixel_Buffer), // .export
.address (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_sram_slave.address
.byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.read (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
.write (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid) // .readdatavalid
);
Video_System_Pixel_Buffer_DMA pixel_buffer_dma (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid), // avalon_pixel_dma_master.readdatavalid
.master_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_waitrequest), // .waitrequest
.master_address (pixel_buffer_dma_avalon_pixel_dma_master_address), // .address
.master_arbiterlock (pixel_buffer_dma_avalon_pixel_dma_master_lock), // .lock
.master_read (pixel_buffer_dma_avalon_pixel_dma_master_read), // .read
.master_readdata (pixel_buffer_dma_avalon_pixel_dma_master_readdata), // .readdata
.slave_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address), // avalon_control_slave.address
.slave_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.slave_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read), // .read
.slave_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write), // .write
.slave_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.slave_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.stream_ready (pixel_buffer_dma_avalon_pixel_source_ready), // avalon_pixel_source.ready
.stream_startofpacket (pixel_buffer_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_endofpacket (pixel_buffer_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_valid (pixel_buffer_dma_avalon_pixel_source_valid), // .valid
.stream_data (pixel_buffer_dma_avalon_pixel_source_data) // .data
);
Video_System_Pixel_RGB_Resampler pixel_rgb_resampler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (pixel_buffer_dma_avalon_pixel_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (pixel_buffer_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_buffer_dma_avalon_pixel_source_valid), // .valid
.stream_in_ready (pixel_buffer_dma_avalon_pixel_source_ready), // .ready
.stream_in_data (pixel_buffer_dma_avalon_pixel_source_data), // .data
.stream_out_ready (pixel_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (pixel_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (pixel_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (pixel_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (pixel_rgb_resampler_avalon_rgb_source_data) // .data
);
Video_System_Pixel_Scaler pixel_scaler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (pixel_rgb_resampler_avalon_rgb_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (pixel_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (pixel_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_in_data (pixel_rgb_resampler_avalon_rgb_source_data), // .data
.stream_out_ready (pixel_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (pixel_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (pixel_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (pixel_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (pixel_scaler_avalon_scaler_source_data) // .data
);
Video_System_VGA_Controller vga_controller (
.clk (clock_signals_vga_clk_clk), // clock_reset.clk
.reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
.data (dual_clock_fifo_avalon_dc_buffer_source_data), // avalon_vga_sink.data
.startofpacket (dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.endofpacket (dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.valid (dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.ready (dual_clock_fifo_avalon_dc_buffer_source_ready), // .ready
.VGA_CLK (VGA_CLK_from_the_VGA_Controller), // external_interface.export
.VGA_HS (VGA_HS_from_the_VGA_Controller), // .export
.VGA_VS (VGA_VS_from_the_VGA_Controller), // .export
.VGA_BLANK (VGA_BLANK_from_the_VGA_Controller), // .export
.VGA_SYNC (VGA_SYNC_from_the_VGA_Controller), // .export
.VGA_R (VGA_R_from_the_VGA_Controller), // .export
.VGA_G (VGA_G_from_the_VGA_Controller), // .export
.VGA_B (VGA_B_from_the_VGA_Controller) // .export
);
Video_System_Video_In_Decoder video_in_decoder (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_out_ready (video_in_decoder_avalon_decoder_source_ready), // avalon_decoder_source.ready
.stream_out_startofpacket (video_in_decoder_avalon_decoder_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_decoder_avalon_decoder_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_decoder_avalon_decoder_source_valid), // .valid
.stream_out_data (video_in_decoder_avalon_decoder_source_data), // .data
.TD_CLK27 (TD_CLK27_to_the_Video_In_Decoder), // external_interface.export
.TD_DATA (TD_DATA_to_the_Video_In_Decoder), // .export
.TD_HS (TD_HS_to_the_Video_In_Decoder), // .export
.TD_VS (TD_VS_to_the_Video_In_Decoder), // .export
.TD_RESET (TD_RESET_from_the_Video_In_Decoder), // .export
.overflow_flag (overflow_flag_from_the_Video_In_Decoder) // .export
);
Video_System_Chroma_Resampler chroma_resampler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (video_in_decoder_avalon_decoder_source_startofpacket), // avalon_chroma_sink.startofpacket
.stream_in_endofpacket (video_in_decoder_avalon_decoder_source_endofpacket), // .endofpacket
.stream_in_valid (video_in_decoder_avalon_decoder_source_valid), // .valid
.stream_in_ready (video_in_decoder_avalon_decoder_source_ready), // .ready
.stream_in_data (video_in_decoder_avalon_decoder_source_data), // .data
.stream_out_ready (chroma_resampler_avalon_chroma_source_ready), // avalon_chroma_source.ready
.stream_out_startofpacket (chroma_resampler_avalon_chroma_source_startofpacket), // .startofpacket
.stream_out_endofpacket (chroma_resampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_out_valid (chroma_resampler_avalon_chroma_source_valid), // .valid
.stream_out_data (chroma_resampler_avalon_chroma_source_data) // .data
);
Video_System_Color_Space_Converter color_space_converter (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (chroma_resampler_avalon_chroma_source_startofpacket), // avalon_csc_sink.startofpacket
.stream_in_endofpacket (chroma_resampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_in_valid (chroma_resampler_avalon_chroma_source_valid), // .valid
.stream_in_ready (chroma_resampler_avalon_chroma_source_ready), // .ready
.stream_in_data (chroma_resampler_avalon_chroma_source_data), // .data
.stream_out_ready (color_space_converter_avalon_csc_source_ready), // avalon_csc_source.ready
.stream_out_startofpacket (color_space_converter_avalon_csc_source_startofpacket), // .startofpacket
.stream_out_endofpacket (color_space_converter_avalon_csc_source_endofpacket), // .endofpacket
.stream_out_valid (color_space_converter_avalon_csc_source_valid), // .valid
.stream_out_data (color_space_converter_avalon_csc_source_data) // .data
);
Video_System_Video_RGB_Resampler video_rgb_resampler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (color_space_converter_avalon_csc_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (color_space_converter_avalon_csc_source_endofpacket), // .endofpacket
.stream_in_valid (color_space_converter_avalon_csc_source_valid), // .valid
.stream_in_ready (color_space_converter_avalon_csc_source_ready), // .ready
.stream_in_data (color_space_converter_avalon_csc_source_data), // .data
.stream_out_ready (video_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (video_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (video_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (video_rgb_resampler_avalon_rgb_source_data) // .data
);
Video_System_Video_Clipper video_clipper (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_data (video_rgb_resampler_avalon_rgb_source_data), // avalon_clipper_sink.data
.stream_in_startofpacket (video_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_in_endofpacket (video_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (video_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (video_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_out_ready (video_clipper_avalon_clipper_source_ready), // avalon_clipper_source.ready
.stream_out_data (video_clipper_avalon_clipper_source_data), // .data
.stream_out_startofpacket (video_clipper_avalon_clipper_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_clipper_avalon_clipper_source_endofpacket), // .endofpacket
.stream_out_valid (video_clipper_avalon_clipper_source_valid) // .valid
);
Video_System_Video_Scaler video_scaler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (video_clipper_avalon_clipper_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (video_clipper_avalon_clipper_source_endofpacket), // .endofpacket
.stream_in_valid (video_clipper_avalon_clipper_source_valid), // .valid
.stream_in_ready (video_clipper_avalon_clipper_source_ready), // .ready
.stream_in_data (video_clipper_avalon_clipper_source_data), // .data
.stream_out_ready (video_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (video_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (video_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (video_scaler_avalon_scaler_source_data) // .data
);
Video_System_Video_DMA video_dma (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_data (video_scaler_avalon_scaler_source_data), // avalon_dma_sink.data
.stream_startofpacket (video_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_endofpacket (video_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_valid (video_scaler_avalon_scaler_source_valid), // .valid
.stream_ready (video_scaler_avalon_scaler_source_ready), // .ready
.slave_address (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address), // avalon_dma_control_slave.address
.slave_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.slave_read (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read), // .read
.slave_write (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write), // .write
.slave_writedata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.slave_readdata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.master_address (video_dma_avalon_dma_master_address), // avalon_dma_master.address
.master_waitrequest (video_dma_avalon_dma_master_waitrequest), // .waitrequest
.master_write (video_dma_avalon_dma_master_write), // .write
.master_writedata (video_dma_avalon_dma_master_writedata) // .writedata
);
Video_System_AV_Config av_config (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.address (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address), // avalon_av_config_slave.address
.byteenable (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.read (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read), // .read
.write (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.waitrequest (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.I2C_SDAT (I2C_SDAT_to_and_from_the_AV_Config), // external_interface.export
.I2C_SCLK (I2C_SCLK_from_the_AV_Config) // .export
);
Video_System_CPU cpu (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.jtag_debug_module_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_select (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.jtag_debug_module_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
Video_System_Clock_Signals clock_signals (
.CLOCK_50 (clk_0), // clk_in_primary.clk
.reset (rst_controller_002_reset_out_reset), // clk_in_primary_reset.reset
.sys_clk (clock_signals_sys_clk_clk), // sys_clk.clk
.sys_reset_n (), // sys_clk_reset.reset_n
.VGA_CLK (clock_signals_vga_clk_clk) // vga_clk.clk
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) pixel_buffer_dma_avalon_pixel_dma_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (pixel_buffer_dma_avalon_pixel_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_waitrequest), // .waitrequest
.av_read (pixel_buffer_dma_avalon_pixel_dma_master_read), // .read
.av_readdata (pixel_buffer_dma_avalon_pixel_dma_master_readdata), // .readdata
.av_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid), // .readdatavalid
.av_lock (pixel_buffer_dma_avalon_pixel_dma_master_lock), // .lock
.av_burstcount (1'b1), // (terminated)
.av_byteenable (2'b11), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (16'b0000000000000000), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_dma_avalon_dma_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (video_dma_avalon_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_dma_avalon_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (video_dma_avalon_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (video_dma_avalon_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (video_dma_avalon_dma_master_waitrequest), // .waitrequest
.av_write (video_dma_avalon_dma_master_write), // .write
.av_writedata (video_dma_avalon_dma_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (2'b11), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.av_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (18),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pixel_buffer_avalon_sram_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) av_config_avalon_av_config_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) video_dma_avalon_dma_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pixel_buffer_dma_avalon_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (4'b0000)
) cpu_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) cpu_data_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_001_src_data), // .data
.rp_channel (rsp_xbar_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_001_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BEGIN_BURST (69),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_THREAD_ID_H (77),
.PKT_THREAD_ID_L (77),
.PKT_CACHE_H (84),
.PKT_CACHE_L (81),
.PKT_DATA_SIDEBAND_H (68),
.PKT_DATA_SIDEBAND_L (68),
.PKT_QOS_H (70),
.PKT_QOS_L (70),
.PKT_ADDR_SIDEBAND_H (67),
.PKT_ADDR_SIDEBAND_L (67),
.ST_DATA_W (87),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (2),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_002_src1_valid), // rp.valid
.rp_data (rsp_xbar_demux_002_src1_data), // .data
.rp_channel (rsp_xbar_demux_002_src1_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_002_src1_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_002_src1_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BEGIN_BURST (69),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_THREAD_ID_H (77),
.PKT_THREAD_ID_L (77),
.PKT_CACHE_H (84),
.PKT_CACHE_L (81),
.PKT_DATA_SIDEBAND_H (68),
.PKT_DATA_SIDEBAND_L (68),
.PKT_QOS_H (70),
.PKT_QOS_L (70),
.PKT_ADDR_SIDEBAND_H (67),
.PKT_ADDR_SIDEBAND_L (67),
.ST_DATA_W (87),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (3),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (video_dma_avalon_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (video_dma_avalon_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (video_dma_avalon_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_002_src2_valid), // rp.valid
.rp_data (rsp_xbar_demux_002_src2_data), // .data
.rp_channel (rsp_xbar_demux_002_src2_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_002_src2_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_002_src2_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_002_src2_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) onchip_memory_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_001_src_valid), // .valid
.cp_data (cmd_xbar_mux_001_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_001_src_channel), // .channel
.rf_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (69),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (74),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.ST_CHANNEL_W (6),
.ST_DATA_W (87),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1)
) pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (88),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
.cp_data (cmd_xbar_demux_001_src3_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
.rf_sink_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Video_System_addr_router addr_router (
.sink_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
Video_System_addr_router_001 addr_router_001 (
.sink_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
Video_System_addr_router_002 addr_router_002 (
.sink_ready (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
Video_System_addr_router_002 addr_router_003 (
.sink_ready (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_003_src_ready), // src.ready
.src_valid (addr_router_003_src_valid), // .valid
.src_data (addr_router_003_src_data), // .data
.src_channel (addr_router_003_src_channel), // .channel
.src_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_003_src_endofpacket) // .endofpacket
);
Video_System_id_router id_router (
.sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
Video_System_id_router id_router_001 (
.sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
Video_System_id_router_002 id_router_002 (
.sink_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
Video_System_id_router_003 id_router_003 (
.sink_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
Video_System_id_router_003 id_router_004 (
.sink_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
Video_System_id_router_003 id_router_005 (
.sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (69),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (87),
.ST_CHANNEL_W (6),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (61),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7)
) burst_adapter (
.clk (clock_signals_sys_clk_clk), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_002_src_data), // .data
.sink0_channel (cmd_xbar_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_002_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_001 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clock_signals_vga_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_002 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_0), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
Video_System_cmd_xbar_demux cmd_xbar_demux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_001_src_ready), // sink.ready
.sink_channel (addr_router_001_src_channel), // .channel
.sink_data (addr_router_001_src_data), // .data
.sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.sink_valid (addr_router_001_src_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_demux_002 cmd_xbar_demux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_002_src_ready), // sink.ready
.sink_channel (addr_router_002_src_channel), // .channel
.sink_data (addr_router_002_src_data), // .data
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.sink_valid (addr_router_002_src_valid), // .valid
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_demux_002 cmd_xbar_demux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_003_src_ready), // sink.ready
.sink_channel (addr_router_003_src_channel), // .channel
.sink_data (addr_router_003_src_data), // .data
.sink_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_003_src_endofpacket), // .endofpacket
.sink_valid (addr_router_003_src_valid), // .valid
.src0_ready (cmd_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_003_src0_valid), // .valid
.src0_data (cmd_xbar_demux_003_src0_data), // .data
.src0_channel (cmd_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_mux cmd_xbar_mux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_mux_002 cmd_xbar_mux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_002_src_ready), // src.ready
.src_valid (cmd_xbar_mux_002_src_valid), // .valid
.src_data (cmd_xbar_mux_002_src_data), // .data
.src_channel (cmd_xbar_mux_002_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_src_ready), // sink0.ready
.sink0_valid (width_adapter_src_valid), // .valid
.sink0_channel (width_adapter_src_channel), // .channel
.sink0_data (width_adapter_src_data), // .data
.sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_002_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_002_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_003_src0_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_003_src0_valid), // .valid
.sink2_channel (cmd_xbar_demux_003_src0_channel), // .channel
.sink2_data (cmd_xbar_demux_003_src0_data), // .data
.sink2_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_demux rsp_xbar_demux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
Video_System_cmd_xbar_demux rsp_xbar_demux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
Video_System_rsp_xbar_demux_002 rsp_xbar_demux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_002_src1_valid), // .valid
.src1_data (rsp_xbar_demux_002_src1_data), // .data
.src1_channel (rsp_xbar_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_002_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_002_src2_valid), // .valid
.src2_data (rsp_xbar_demux_002_src2_data), // .data
.src2_channel (rsp_xbar_demux_002_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_002_src2_endofpacket) // .endofpacket
);
Video_System_rsp_xbar_demux_003 rsp_xbar_demux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
Video_System_rsp_xbar_demux_003 rsp_xbar_demux_004 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
Video_System_rsp_xbar_demux_003 rsp_xbar_demux_005 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
Video_System_rsp_xbar_mux rsp_xbar_mux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
Video_System_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (width_adapter_001_src_ready), // sink2.ready
.sink2_valid (width_adapter_001_src_valid), // .valid
.sink2_channel (width_adapter_001_src_channel), // .channel
.sink2_data (width_adapter_001_src_data), // .data
.sink2_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink2_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (76),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (79),
.IN_PKT_BURSTWRAP_L (77),
.IN_PKT_BURST_SIZE_H (82),
.IN_PKT_BURST_SIZE_L (80),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (84),
.IN_PKT_BURST_TYPE_L (83),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (58),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (64),
.OUT_PKT_BURST_SIZE_L (62),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (66),
.OUT_PKT_BURST_TYPE_L (65),
.OUT_ST_DATA_W (87),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (0)
) width_adapter (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_demux_001_src2_valid), // sink.valid
.in_channel (cmd_xbar_demux_001_src2_channel), // .channel
.in_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.in_ready (cmd_xbar_demux_001_src2_ready), // .ready
.in_data (cmd_xbar_demux_001_src2_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (58),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (61),
.IN_PKT_BURSTWRAP_L (59),
.IN_PKT_BURST_SIZE_H (64),
.IN_PKT_BURST_SIZE_L (62),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (66),
.IN_PKT_BURST_TYPE_L (65),
.IN_ST_DATA_W (87),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (76),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (82),
.OUT_PKT_BURST_SIZE_L (80),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (84),
.OUT_PKT_BURST_TYPE_L (83),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (6),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (rsp_xbar_demux_002_src0_valid), // sink.valid
.in_channel (rsp_xbar_demux_002_src0_channel), // .channel
.in_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.in_ready (rsp_xbar_demux_002_src0_ready), // .ready
.in_data (rsp_xbar_demux_002_src0_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
Video_System_irq_mapper irq_mapper (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sender_irq (cpu_d_irq_irq) // sender.irq
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_BEHAVIORAL_V |
Require Export Coq.Program.Tactics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Lists.List.
Import EqNotations.
Import ListNotations.
(***
*** Ordered Types = Types with a PreOrder
***)
(* NOTE: The idea with this approach is that each type uniquely determines its
ordered type, but we keep the types separate from the ordered types to make
type inference work properly... *)
Class OTRelation (A:Type) : Type := ot_R : relation A.
Class OType (A:Type) {R:OTRelation A} : Prop :=
{ ot_PreOrder :> PreOrder ot_R }.
Arguments OTRelation A%type.
Arguments OType A%type {R}.
Instance OType_Reflexive A `{OType A} : Reflexive ot_R.
Proof. typeclasses eauto. Qed.
Instance OType_Transitive A `{OType A} : Transitive ot_R.
Proof. typeclasses eauto. Qed.
(* The equivalence relation for an OrderedType *)
Definition ot_equiv {A} `{OTRelation A} : relation A :=
fun x y => ot_R x y /\ ot_R y x.
Instance ot_equiv_Equivalence A `{OType A} : Equivalence ot_equiv.
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H0; split; assumption. }
{ destruct H0; destruct H1; split; transitivity y; assumption. }
Qed.
Notation "x <o= y" :=
(ot_R x y) (no associativity, at level 70).
Notation "x =o= y" :=
(ot_equiv x y) (no associativity, at level 70).
(* FIXME: replace "ot_R" below with "<o=" notation *)
(***
*** Commonly-Used Ordered Types
***)
(* The ordered type of propositions *)
Instance OTProp_R : OTRelation Prop := Basics.impl.
Instance OTProp : OType Prop.
Proof. repeat constructor; typeclasses eauto. Qed.
(* The discrete ordered type, where things are only related to themselves; we
make this a definition, not an instance, so that it can be instantiated for
particular types. *)
Definition OTdiscrete_R (A:Type) : OTRelation A := eq.
Definition OTdiscrete A : @OType A (OTdiscrete_R A).
repeat constructor. typeclasses eauto.
Qed.
(* The only ordered type over unit is the discrete one *)
Instance OTunit_R : OTRelation unit := OTdiscrete_R unit.
Instance OTunit : OType unit := OTdiscrete unit.
(* The ordered type that flips the ordering of an underlying OType; this becomes
a type itself in Coq *)
Inductive Flip A : Type := flip (a:A).
Definition unflip {A} (f:Flip A) : A := let (x) := f in x.
Instance OTFlip_R A (R:OTRelation A) : OTRelation (Flip A) :=
fun x y => unflip y <o= unflip x.
Instance OTFlip A `{OType A} : OType (Flip A).
Proof.
repeat constructor; intro; intros.
- destruct x; compute; reflexivity.
- destruct x; destruct y; destruct z; compute; transitivity a0; assumption.
Qed.
(* The pointwise relation on pairs *)
Instance OTpair_R A B (RA:OTRelation A) (RB:OTRelation B) : OTRelation (A*B) :=
fun p1 p2 => ot_R (fst p1) (fst p2) /\ ot_R (snd p1) (snd p2).
Instance OTpair A B `(OType A) `(OType B) : OType (A*B).
Proof.
repeat constructor.
- destruct x. reflexivity.
- destruct x. reflexivity.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity a0; assumption.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity b0; assumption.
Qed.
(* The sort-of pointwise relation on sum types *)
Inductive sumR {A B} (RA:OTRelation A) (RB:OTRelation B) : A+B -> A+B -> Prop :=
| sumR_inl a1 a2 : RA a1 a2 -> sumR RA RB (inl a1) (inl a2)
| sumR_inr b1 b2 : RB b1 b2 -> sumR RA RB (inr b1) (inr b2).
Instance OTsum_R A B (RA:OTRelation A) (RB:OTRelation B) : OTRelation (A+B) :=
sumR RA RB.
Instance OTsum A B `(OType A) `(OType B) : OType (A+B).
Proof.
repeat constructor; intro; intros.
{ destruct x; constructor; reflexivity. }
{ destruct H1; inversion H2.
- constructor; transitivity a2; assumption.
- constructor; transitivity b2; assumption. }
Qed.
(* NOTE: the following definition requires everything above to be polymorphic *)
(* NOTE: The definition we choose for OTType is actually deep: instead of
requiring ot_Type A = ot_Type B, we could just require a coercion function from
ot_Type A to ot_Type B, which would yield something more like HoTT... though
maybe it wouldn't work unless we assumed the HoTT axiom? As it is, we might need
UIP to hold if we want to use the definition given here... *)
(*
Program Definition OTType : OType :=
{|
ot_Type := OType;
ot_R := (fun A B =>
exists (e:ot_Type A = ot_Type B),
forall (x y:A),
ot_R A x y ->
ot_R B (rew [fun A => A] e in x)
(rew [fun A => A] e in y));
|}.
*)
(***
*** The Ordered Type for Functions
***)
(* The type of continuous, i.e. Proper, functions between ordered types *)
Record Pfun A B {RA:OTRelation A} {RB:OTRelation B} :=
{
pfun_app : A -> B;
pfun_Proper : Proper (ot_R ==> ot_R) pfun_app
}.
Arguments pfun_app {_ _ _ _} _ _.
Arguments pfun_Proper [_ _ _ _] _ _ _ _.
Notation "A '-o>' B" :=
(Pfun A B) (right associativity, at level 99).
Notation "x @o@ y" :=
(pfun_app x y) (left associativity, at level 20).
(* Infix "@" := pfun_app (at level 50). *)
(* The non-dependent function ordered type *)
Instance OTarrow_R A B {RA:OTRelation A} {RB:OTRelation B} : OTRelation (A -o> B) :=
fun f g =>
forall a1 a2, ot_R a1 a2 -> ot_R (pfun_app f a1) (pfun_app g a2).
Instance OTarrow A B `{OType A} `{OType B} : OType (A -o> B).
Proof.
repeat constructor; intro; intros; intro; intros.
{ apply pfun_Proper; assumption. }
{ transitivity (pfun_app y a1).
- apply H1; reflexivity.
- apply H2; assumption. }
Qed.
(* Curry a Pfun *)
(*
Program Definition pfun_curry {A B C} (pfun : Pfun (OTpair A B) C)
: Pfun A (OTarrow B C) :=
{| pfun_app :=
fun a =>
{| pfun_app := fun b => pfun_app pfun (a,b);
pfun_Proper := _ |};
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros b1 b2 Rb. apply pfun_Proper.
split; [ reflexivity | assumption ].
Qed.
Next Obligation.
Proof.
intros a1 a2 Ra b1 b2 Rb; simpl.
apply pfun_Proper; split; assumption.
Qed.
(* Uncrry a Pfun *)
Program Definition pfun_uncurry {A B C} (pfun : Pfun A (OTarrow B C))
: Pfun (OTpair A B) C :=
{| pfun_app :=
fun ab => pfun_app (pfun_app pfun (fst ab)) (snd ab);
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros ab1 ab2 Rab. destruct Rab as [ Ra Rb ].
exact (pfun_Proper pfun (fst ab1) (fst ab2) Ra (snd ab1) (snd ab2) Rb).
Qed.
*)
(* Currying and uncurrying of pfuns form an adjunction *)
(* FIXME: figure out the simplest way of stating this adjunction *)
(* OTarrow is right adjoint to OTpair, meaning that (OTarrow (OTpair A B) C) is
isomorphic to (OTarrow A (OTarrow B C)). The following is the first part of this
isomorphism, mapping left-to-right. *)
(* FIXME: could also do a forall type, but need the second type argument, B, to
itself be proper, i.e., to be an element of OTarrow A OType. Would also need a
dependent version of OTContext, below. *)
(* pfun_app is always Proper *)
Instance Proper_pfun_app A B `{OType A} `{OType B} :
Proper (ot_R ==> ot_R ==> ot_R) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra. apply Rf; assumption.
Qed.
(* pfun_app is always Proper w.r.t. ot_equiv *)
Instance Proper_pfun_app_equiv A B `{OType A} `{OType B} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra; destruct Rf; destruct Ra.
split; apply Proper_pfun_app; assumption.
Qed.
(***
*** Building Proper Functions
***)
Class ProperPair A `{OTRelation A} (x y:A) : Prop :=
proper_pair_pf : ot_R x y.
Definition ofun {A B} `{OTRelation A} `{OTRelation B} (f: A -> B)
{prp:forall x y, ProperPair A x y -> ProperPair B (f x) (f y)}
: A -o> B :=
{| pfun_app := f; pfun_Proper := prp |}.
Instance ProperPair_refl A `{OType A} (x:A) : ProperPair A x x.
Proof.
unfold ProperPair. reflexivity.
Qed.
Instance ProperPair_pfun_app A B `{OType A} `{OType B}
(fl fr:A -o> B) argl argr
(prpf:ProperPair (A -o> B) fl fr)
(prpa:ProperPair A argl argr)
: ProperPair B (pfun_app fl argl) (pfun_app fr argr).
Proof.
apply prpf; assumption.
Qed.
Instance ProperPair_ofun A B `{OType A} `{OType B} (f g:A -> B) prpl prpr
(pf: forall x y, ProperPair A x y -> ProperPair B (f x) (g y)) :
ProperPair (A -o> B) (@ofun A B _ _ f prpl) (@ofun A B _ _ g prpr).
Proof.
intros xl xr Rx; apply pf; assumption.
Qed.
(***
*** Ordered Terms and ProperPair Instances for Pair Operations
***)
Instance Proper_pair A B `{OType A} `{OType B} :
Proper (ot_R ==> ot_R ==> ot_R) (pair : A -> B -> A*B).
Proof.
repeat intro; split; assumption.
Qed.
Instance ProperPair_fst A B `{OType A} `{OType B} (p1 p2: A*B)
(pf: ProperPair (A*B) p1 p2) :
ProperPair A (fst p1) (fst p2).
Proof.
destruct pf; assumption.
Qed.
Instance ProperPair_snd A B `{OType A} `{OType B} (p1 p2: A*B)
(pf: ProperPair (A*B) p1 p2) :
ProperPair B (snd p1) (snd p2).
Proof.
destruct pf; assumption.
Qed.
Instance ProperPair_pair A B `{OType A} `{OType B}
(x1 x2:A) (y1 y2:B) (pfx: ProperPair A x1 x2) (pfy: ProperPair B y1 y2) :
ProperPair (A*B) (pair x1 y1) (pair x2 y2).
Proof.
split; assumption.
Qed.
(***
*** Notations for Ordered Types
***)
(* FIXME: why don't these work?
Notation "'pfun' ( x : A ) =o> t" :=
(@ot_Lambda A _ (fun x => t))
(at level 100, right associativity, x at level 99) : pterm_scope.
Notation "'pfun' x =o> t" :=
(ot_Lambda (fun x => t))
(at level 100, right associativity, x at level 99) : pterm_scope.
*)
(***
*** Ordered Type Functions
***)
(*
Definition ot_fun_app (TF: forall A `{OType A}, Type) A `{OType A} := TF A.
Notation "F @t@ A" :=
(ot_fun_app F A%type) (left associativity, at level 20).
*)
Class OTRelationF (TF: forall A `{OType A}, Type) : Type :=
ot_rel_app : forall A `{OType A}, OTRelation (TF A).
Instance OTRelation_ot_rel_app TF `(OTRelationF TF) A `(OType A) :
OTRelation (TF A _ _) := ot_rel_app A.
Class OTypeF (TF: forall A `{OType A}, Type) `{OTRelationF TF} : Prop :=
otype_app : forall A `{OType A}, OType (TF A).
Instance OType_otype_app TF `(OTypeF TF) A `(OType A) :
OType (TF A _ _) := otype_app A.
(***
*** Automation for Ordered Terms
***)
Instance Proper_ot_R_ot_R A `{OType A} :
Proper (Basics.flip ot_R ==> ot_R ==> Basics.impl) ot_R.
Proof.
intros x1 x2 Rx y1 y2 Ry Rxy.
transitivity x1; [ assumption | ]; transitivity y1; assumption.
Qed.
Instance Proper_ot_equiv_ot_R A `{OType A} :
Proper (ot_equiv ==> ot_equiv ==> iff) ot_R.
Proof.
intros x1 x2 Rx y1 y2 Ry; destruct Rx; destruct Ry; split; intro Rxy.
transitivity x1; [ assumption | ]; transitivity y1; assumption.
transitivity x2; [ assumption | ]; transitivity y2; assumption.
Qed.
Instance Proper_ot_R_pfun_app A B `{OType A} `{OType B} :
Proper (ot_R ==> ot_R ==> ot_R) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf x1 x2 Rx. apply Rf; apply Rx.
Qed.
Instance Proper_ot_R_pfun_app_partial A B `{OType A} `{OType B} f :
Proper (ot_R ==> ot_R) (@pfun_app A B _ _ f).
Proof.
apply pfun_Proper.
Qed.
Create HintDb OT.
(* Split ot_equiv equalities into the left and right cases *)
Definition split_ot_equiv A `{OTRelation A} (x y : A)
(pf1: x <o= y) (pf2 : y <o= x) : x =o= y :=
conj pf1 pf2.
Hint Resolve split_ot_equiv : OT.
(* Extensionality for ot_R *)
(*
Definition ot_arrow_ext A B `{OTRelation A} `{OTRelation B} (f1 f2 : A -o> B)
(pf:forall x y, x <o= y -> f1 @o@ x <o= f2 @o@ y) : f1 <o= f2 := pf.
Hint Resolve ot_arrow_ext : OT.
*)
(* Add the above rules to the OT rewrite set *)
(* Hint Rewrite @mkOTerm_apply @ot_unlift_iso_OTForType_refl_id : OT. *)
(* Eta-equality for pairs *)
Lemma ot_pair_eta A B `{OType A} `{OType B} (x: A*B) :
(fst x , snd x) =o= x.
split; split; reflexivity.
Qed.
Hint Rewrite ot_pair_eta : OT.
(* Tactic to apply rewrites in the OT rewrite set *)
Ltac rewrite_OT := rewrite_strat (topdown (hints OT)).
(* General tactic to try to prove theorems about ordered terms *)
Ltac prove_OT :=
simpl; try (rewrite_OT; simpl);
lazymatch goal with
| |- @ot_equiv (_ -o> _) _ _ _ =>
split; apply ot_arrow_ext; intro; intro; intro; prove_OT
| |- @ot_R (_ -o> _) _ _ _ =>
apply ot_arrow_ext; intro; intro; intro; prove_OT
| |- _ =>
match goal with
| H : (?x <o= ?y) |- _ => rewrite H; prove_OT
| H : (?x =o= ?y) |- _ => rewrite H; prove_OT
| |- _ => try reflexivity
end
end.
(***
*** Examples of Ordered Terms
***)
Module OTExamples.
Definition ex1 : Prop -o> Prop := ofun (fun p => p).
(* Eval compute in (pfun_app ex1 : Prop -> Prop). *)
Definition ex2 {A} `{OType A} : A -o> A := ofun (fun p => p).
(* Eval simpl in (fun A `{OType A} => pfun_app (@ex2 A _ _) : A -> A). *)
Definition ex3 {A} `{OType A} : A -o> A -o> A :=
ofun (fun p1 => ofun (fun p2 => p1)).
(* Eval simpl in (fun (A:OType) x => pfun_app (pfun_app (@ex3 A) x)). *)
Definition ex4 {A B} `{OType A} `{OType B} : (A * B -o> A) :=
ofun (fun p => fst p).
(* Eval simpl in (fun (A B:OType) => pfun_app ex4 : A * B -> A). *)
Definition ex5 {A B} `{OType A} `{OType B} : A * B -o> B * A :=
ofun (fun p => (snd p , fst p)).
(* Eval simpl in (fun (A B:OType) => pfun_app ex5 : A *o* B -> B *o* A). *)
Definition ex6 {A B C} `{OType A} `{OType B} `{OType C} : A * B * C -o> C * A :=
ofun (fun triple => (snd triple , fst (fst triple))).
Definition ex7 {A B C} `{OType A} `{OType B} `{OType C}
: (A * B -o> C) -o> C -o> A -o> B -o> C :=
ofun (fun f =>
ofun
(fun c =>
ofun
(fun a =>
ofun (fun b => f @o@ (a , b))))).
End OTExamples.
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: store_pkt.v
// Project: NF2.1
// Description: stores incoming packet into the SRAM, sends new wr addres to regs
//
// Note: Assumes that the length header is FIRST!
//
///////////////////////////////////////////////////////////////////////////////
module store_pkt
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter NUM_OUTPUT_QUEUES = 5,
parameter SRAM_ADDR_WIDTH = 13,
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter OQ_STAGE_NUM = 6,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES)
)
( // --- Interface to header_parser
dst_oq_avail,
parsed_dst_oq,
parsed_pkt_byte_len,
parsed_pkt_word_len,
rd_dst_oq,
// --- Interface to registers
dst_oq_wr_addr_new,
pkt_stored,
pkt_dropped,
stored_pkt_data_length,
stored_pkt_overhead_length,
stored_pkt_total_word_length,
dst_oq,
rd_dst_addr,
dst_oq_high_addr,
dst_oq_low_addr,
dst_oq_wr_addr,
dst_oq_full,
// --- Interface to SRAM
wr_0_addr,
wr_0_req,
wr_0_ack,
wr_0_data,
// --- Interface to input fifo
input_fifo_rd_en,
input_fifo_empty,
input_fifo_data_out,
input_fifo_ctrl_out,
// --- misc
clk,
reset
);
input dst_oq_avail;
input [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
input [PKT_LEN_WIDTH-1:0] parsed_pkt_byte_len;
input [PKT_WORDS_WIDTH-1:0] parsed_pkt_word_len;
output reg rd_dst_oq;
// --- Interface to registers
output reg [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr_new;
output reg pkt_stored;
output reg pkt_dropped;
output reg [PKT_LEN_WIDTH-1:0] stored_pkt_data_length;
output reg [CTRL_WIDTH-1:0] stored_pkt_overhead_length;
output reg [PKT_WORDS_WIDTH-1:0] stored_pkt_total_word_length;
output reg [NUM_OQ_WIDTH-1:0] dst_oq;
output reg rd_dst_addr;
input [SRAM_ADDR_WIDTH-1:0] dst_oq_high_addr;
input [SRAM_ADDR_WIDTH-1:0] dst_oq_low_addr;
input [SRAM_ADDR_WIDTH-1:0] dst_oq_wr_addr;
input [NUM_OUTPUT_QUEUES-1:0] dst_oq_full;
// --- Interface to SRAM
output reg [SRAM_ADDR_WIDTH-1:0] wr_0_addr;
output reg wr_0_req;
input wr_0_ack;
output reg [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data;
// --- Interface to input fifo
output reg input_fifo_rd_en;
input input_fifo_empty;
input [DATA_WIDTH-1:0] input_fifo_data_out;
input [CTRL_WIDTH-1:0] input_fifo_ctrl_out;
// --- misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//--------------------- Internal parameters --------------------------
parameter NUM_STORE_STATES = 7;
parameter ST_WAIT_DST_PORT = 1;
parameter ST_READ_ADDR = 2;
parameter ST_LATCH_ADDR = 4;
parameter ST_MOVE_PKT = 8;
parameter ST_WAIT_FOR_DATA = 16;
parameter ST_WAIT_EOP = 32;
parameter ST_DROP_PKT = 64;
parameter COUNT_IDLE = 1;
parameter COUNT_HDRS = 2;
parameter COUNT_DATA = 4;
//------------------------ Wires/regs --------------------------------
reg [NUM_STORE_STATES-1:0] store_state;
reg [NUM_STORE_STATES-1:0] store_state_next;
wire [SRAM_ADDR_WIDTH-1:0] wr_0_addr_plus1;
reg [SRAM_ADDR_WIDTH-1:0] wr_0_addr_next;
reg [DATA_WIDTH+CTRL_WIDTH-1:0] wr_0_data_next;
reg wr_0_req_next;
wire eop;
reg input_fifo_ctrl_out_prev_is_0;
reg [NUM_OQ_WIDTH-1:0] dst_oq_next;
reg [PKT_LEN_WIDTH-1:0] pkt_byte_len;
reg [PKT_LEN_WIDTH-1:0] pkt_byte_len_next;
reg [PKT_WORDS_WIDTH-1:0] pkt_word_len;
reg [PKT_WORDS_WIDTH-1:0] pkt_word_len_next;
reg [SRAM_ADDR_WIDTH-1:0] lo_addr;
reg [SRAM_ADDR_WIDTH-1:0] lo_addr_next;
reg [SRAM_ADDR_WIDTH-1:0] hi_addr;
reg [SRAM_ADDR_WIDTH-1:0] hi_addr_next;
//-------------------------- Logic -----------------------------------
/* wrap around the address */
assign wr_0_addr_plus1 = (wr_0_addr >= hi_addr) ?
lo_addr : wr_0_addr + 1;
assign eop = (input_fifo_ctrl_out_prev_is_0 && input_fifo_ctrl_out!=0);
/*******************************************************
* wait until the dst port fifo has a destination
* then read the dst port, load the addresses to use,
* and start moving data from the input fifo to the
* sram queues. When the eop is reached, write the pkt
* length in the beginning of the pkt
* If the oq is full then drop pkt.
* Also generate pkt_stored and pkt_dropped signals
*******************************************************/
always @(*) begin
rd_dst_oq = 0;
rd_dst_addr = 0;
store_state_next = store_state;
wr_0_req_next = wr_0_req;
input_fifo_rd_en = 0;
pkt_dropped = 0;
wr_0_data_next = wr_0_data;
wr_0_addr_next = wr_0_addr;
dst_oq_wr_addr_new = wr_0_addr_plus1;
pkt_stored = 0;
dst_oq_next = dst_oq;
pkt_byte_len_next = pkt_byte_len;
pkt_word_len_next = pkt_word_len;
lo_addr_next = lo_addr;
hi_addr_next = hi_addr;
case(store_state)
/* wait until we have a destination port */
ST_WAIT_DST_PORT: begin
if(dst_oq_avail) begin
store_state_next = ST_READ_ADDR;
dst_oq_next = parsed_dst_oq;
pkt_byte_len_next = parsed_pkt_byte_len;
pkt_word_len_next = parsed_pkt_word_len;
rd_dst_oq = 1;
end
end
// Request the destination address
ST_READ_ADDR: begin
store_state_next = ST_LATCH_ADDR;
rd_dst_addr = 1;
end
// Latch the destination addresses (write pointer, lo and hi
// addresses)
ST_LATCH_ADDR: begin
if(!dst_oq_full[dst_oq]) begin
store_state_next = ST_MOVE_PKT;
wr_0_req_next = 1;
wr_0_addr_next = dst_oq_wr_addr;
lo_addr_next = dst_oq_low_addr;
hi_addr_next = dst_oq_high_addr;
/* fifos are first-word fallthrough so the data is already available at the output */
wr_0_data_next = {input_fifo_ctrl_out, input_fifo_data_out};
input_fifo_rd_en = 1;
end
else begin
store_state_next = ST_DROP_PKT;
input_fifo_rd_en = !input_fifo_empty;
end
end // case: ST_WAIT_DST_PORT
/* pipeline is full */
ST_MOVE_PKT: begin
if(wr_0_ack & !input_fifo_empty) begin
wr_0_req_next = 1;
wr_0_addr_next = wr_0_addr_plus1;
wr_0_data_next = {input_fifo_ctrl_out, input_fifo_data_out};
input_fifo_rd_en = 1;
if(eop) begin
store_state_next = ST_WAIT_EOP;
end
end
else if (wr_0_ack & input_fifo_empty) begin
store_state_next = ST_WAIT_FOR_DATA;
wr_0_req_next = 0;
end
end // case: ST_MOVE_PKT
/* Wait until the fifo is not empty */
ST_WAIT_FOR_DATA: begin
if(!input_fifo_empty) begin
wr_0_req_next = 1;
wr_0_addr_next = wr_0_addr_plus1;
wr_0_data_next = {input_fifo_ctrl_out, input_fifo_data_out};
input_fifo_rd_en = 1;
if(eop) begin
store_state_next = ST_WAIT_EOP;
end
else begin
store_state_next = ST_MOVE_PKT;
end
end // if (wr_0_ack)
end // case: ST_WAIT_FOR_DATA
ST_WAIT_EOP: begin
if(wr_0_ack) begin
wr_0_req_next = 0;
pkt_stored = 1;
store_state_next = ST_WAIT_DST_PORT;
end // if (wr_0_ack)
end // case: ST_WAIT_LEN
ST_DROP_PKT: begin
if(eop) begin
store_state_next = ST_WAIT_DST_PORT;
pkt_dropped = 1;
end
input_fifo_rd_en = !input_fifo_empty;
end
default: begin end
endcase // case(store_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
store_state <= ST_WAIT_DST_PORT;
input_fifo_ctrl_out_prev_is_0 <= 0;
wr_0_req <= 0;
wr_0_addr <= 0;
wr_0_data <= 0;
dst_oq <= 0;
pkt_byte_len <= 0;
pkt_word_len <= 0;
lo_addr <= 0;
hi_addr <= 0;
end
else begin
store_state <= store_state_next;
wr_0_req <= wr_0_req_next;
wr_0_addr <= wr_0_addr_next;
wr_0_data <= wr_0_data_next;
dst_oq <= dst_oq_next;
pkt_byte_len <= pkt_byte_len_next;
pkt_word_len <= pkt_word_len_next;
lo_addr <= lo_addr_next;
hi_addr <= hi_addr_next;
if(input_fifo_rd_en) begin
input_fifo_ctrl_out_prev_is_0 <= (input_fifo_ctrl_out==0);
end
end // else: !if(reset)
// synthesis translate_off
if(store_state_next == ST_DROP_PKT) begin
$display("%t %m WARNING: output queue %u is full. Pkt is being dropped.", $time, dst_oq);
end
// synthesis translate_on
end // always @ (posedge clk)
always @(posedge clk) begin
stored_pkt_data_length <= pkt_byte_len;
stored_pkt_overhead_length <= CTRL_WIDTH;
// Calculate the total WORD length
stored_pkt_total_word_length <= pkt_word_len + 1;
end
endmodule // store_pkt
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_0_V
`define SKY130_FD_SC_LP__MUX2_0_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_0 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_0 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_0_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RX Engine (Classic) takes a single stream of TLP
// packets and provides the request packets on the RXR Interface, and the
// completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "tlp.vh"
module rx_engine_classic
#(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128,
parameter C_LOG_NUM_TAGS=6)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXR_RST,
output DONE_RXC_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
output RX_TLP_READY,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RXR Engine
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP
);
`include "functions.vh"
localparam C_RX_PIPELINE_DEPTH = 4;
wire [C_PCI_DATA_WIDTH-1:0] _RXC_DATA;
wire [C_PCI_DATA_WIDTH-1:0] _RXR_DATA;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] wRxSrEoff;
wire [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] wRxSrSoff;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
generate
if(C_VENDOR == "XILINX") begin : xilinx_data
if(C_PCI_DATA_WIDTH == 128) begin : x_be_swap128
assign RXC_DATA = {_RXC_DATA[103:96], _RXC_DATA[111:104], _RXC_DATA[119:112], _RXC_DATA[127:120],
_RXC_DATA[71:64], _RXC_DATA[79:72], _RXC_DATA[87:80], _RXC_DATA[95:88],
_RXC_DATA[39:32], _RXC_DATA[47:40], _RXC_DATA[55:48], _RXC_DATA[63:56],
_RXC_DATA[07:00], _RXC_DATA[15:08], _RXC_DATA[23:16], _RXC_DATA[31:24]};
assign RXR_DATA = {_RXR_DATA[103:96], _RXR_DATA[111:104], _RXR_DATA[119:112], _RXR_DATA[127:120],
_RXR_DATA[71:64], _RXR_DATA[79:72], _RXR_DATA[87:80], _RXR_DATA[95:88],
_RXR_DATA[39:32], _RXR_DATA[47:40], _RXR_DATA[55:48], _RXR_DATA[63:56],
_RXR_DATA[07:00], _RXR_DATA[15:08], _RXR_DATA[23:16], _RXR_DATA[31:24]};
end else if(C_PCI_DATA_WIDTH == 64) begin: x_be_swap64
assign RXC_DATA = {_RXC_DATA[39:32], _RXC_DATA[47:40], _RXC_DATA[55:48], _RXC_DATA[63:56],
_RXC_DATA[07:00], _RXC_DATA[15:08], _RXC_DATA[23:16], _RXC_DATA[31:24]};
assign RXR_DATA = {_RXR_DATA[39:32], _RXR_DATA[47:40], _RXR_DATA[55:48], _RXR_DATA[63:56],
_RXR_DATA[07:00], _RXR_DATA[15:08], _RXR_DATA[23:16], _RXR_DATA[31:24]};
end else if(C_PCI_DATA_WIDTH == 32) begin: x_be_swap32
assign RXC_DATA = {_RXC_DATA[07:00], _RXC_DATA[15:08], _RXC_DATA[23:16], _RXC_DATA[31:24]};
assign RXR_DATA = {_RXR_DATA[07:00], _RXR_DATA[15:08], _RXR_DATA[23:16], _RXR_DATA[31:24]};
end
end else begin : altera_data
assign RXC_DATA = _RXC_DATA;
assign RXR_DATA = _RXR_DATA;
end
endgenerate
assign RX_TLP_READY = 1'b1;
// Shift register for input data with output taps for each delayed
// cycle. Shared by RXC and RXR engines.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (RX_TLP),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (RX_TLP_VALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// End Flag Shift Register. Data valid is deasserted based on the
// taps in this register
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (RX_TLP_END_FLAG & RX_TLP_VALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// End Flag Shift Register. Data valid is deasserted based on the
// taps in this register
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (`SIG_OFFSET_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
eoff_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrEoff),
// Inputs
.WR_DATA (RX_TLP_END_OFFSET),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// End Flag Shift Register. Data valid is deasserted based on the
// taps in this register
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (`SIG_OFFSET_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
soff_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrSoff),
// Inputs
.WR_DATA (RX_TLP_START_OFFSET),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
generate
if(C_VENDOR == "XILINX" && C_PCI_DATA_WIDTH == 128) begin
rxr_engine_128
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxr_engine_inst
(
// Inputs
.RX_SR_DATA (wRxSrData),
.RX_SR_EOP (wRxSrEop),
.RX_SR_END_OFFSET (wRxSrEoff),
.RX_SR_SOP (wRxSrSop),
.RX_SR_START_OFFSET (wRxSrSoff),
.RX_SR_VALID (wRxSrDataValid),
// Outputs
.RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RXR_RST (DONE_RXR_RST),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.RXR_META_EP (RXR_META_EP),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
rxc_engine_128
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxc_engine_inst
(
// Inputs
.RX_SR_DATA (wRxSrData),
.RX_SR_EOP (wRxSrEop),
.RX_SR_END_OFFSET (wRxSrEoff),
.RX_SR_SOP (wRxSrSop),
.RX_SR_START_OFFSET (wRxSrSoff),
.RX_SR_VALID (wRxSrDataValid),
// Outputs
.RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RXC_RST (DONE_RXC_RST),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.RXC_META_EP (RXC_META_EP),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
end else begin // if (C_VENDOR != "XILINX" & C_PCI_DATA_WIDTH !=128)
rxr_engine_classic
#(
// Parameters
.C_VENDOR (C_VENDOR),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxr_engine_inst
(
// Inputs
.RX_SR_DATA (wRxSrData),
.RX_SR_EOP (wRxSrEop),
.RX_SR_END_OFFSET (wRxSrEoff),
.RX_SR_SOP (wRxSrSop),
.RX_SR_VALID (wRxSrDataValid),
// Outputs
.RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RXR_RST (DONE_RXR_RST),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.RXR_META_EP (RXR_META_EP),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
rxc_engine_classic
#(
// Parameters
.C_VENDOR (C_VENDOR),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_RX_PIPELINE_DEPTH (C_RX_PIPELINE_DEPTH))
rxc_engine_inst
(
// Inputs
.RX_SR_DATA (wRxSrData),
.RX_SR_EOP (wRxSrEop),
.RX_SR_END_OFFSET (wRxSrEoff),
.RX_SR_SOP (wRxSrSop),
.RX_SR_VALID (wRxSrDataValid),
// Outputs
.RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RXC_RST (DONE_RXC_RST),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.RXC_META_EP (RXC_META_EP),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
end // else: !if(C_VENDOR != "XILINX" & C_PCI_DATA_WIDTH !=128)
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
`include "tx.v"
`include "hardReset.v"
`include "registers.v"
`include "reg_interface.v"
module tcpci(output wire Start_tHardResetComplete_timer,
output wire Request_PHY_to_Send_Hard_Reset,
output wire Request_PHY_to_Send_Cable_Reset,
output wire Stop_PHY_attempting_to_send_Hard_Reset,
output wire Stop_PHY_attempting_to_send_Cable_Reset,
output wire Stop_tHardResetComplete_timer,
output wire Start_CRCReceiveTimer,
output wire Stop_CRCReceiverTimer,
output wire MessageIDCounter,
output wire MessageID,
output wire MessageID_mismatch,
output wire SOP_mismatch,
output wire MessageID_SOP_match,
output wire [7:0] TRANSMIT_BYTE_COUNT,
output wire [7:0] TRANSMIT_HEADER_LOW,
output wire [7:0] TRANSMIT_HEADER_HIGH,
output wire [7:0] TRANSMIT_DATA_OBJECTS,
output wire [7:0] I2C_slave_reg_out,
output wire [7:0] ALERT_LOW,
input wire tHard_Reset_Complete_expires,
input wire Hard_Reset_sent,
input wire Cable_Reset_sent,
input wire tHardResetComplete_expires,
input wire PRL_Rx_Message_Discard,
input wire Hard_Reset_received,
input wire Cable_Reset_received,
input wire RetryCounter,
input wire CRCReceiveTimer_Timeout,
input wire GoodCRC_Response_from_PHY,
input wire Message_discarded_bus_Idle,
input wire [7:0] I2C_slave_reg_in,
input wire [7:0] I2C_slave_reg_addr,
input wire I2C_slave_reg_in_enb,
input wire reset,
input wire clk);
localparam ALERT_ADDR_LOW = 8'h10;
localparam ALERT_ENB_LOW = 1'h1;
reg ir_ri0_enb, ir_ri1_enb, ir_ri2_enb;
wire [7:0] ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data,TRANSMIT, TX_BUF_HEADER_BYTE_1, RX_BUF_HEADER_BYTE_1, RX_BUF_FRAME_TYPE;
reg [7:0] ir_ri1_in_data, ir_ri2_in_data, ir_ri2_address;
wire ALERT_TransmitSuccessful_TX,ALERT_TransmitSuccessful_HR;
wire ALERT_TransmitSOP_MessageFailed_TX,ALERT_TransmitSOP_MessageFailed_HR;
assign ir_ri2_enb=0;
assign ir_ri2_address=8'h00;
REG_INTERFACE reg_interface(I2C_slave_reg_out, ALERT_LOW, ow_ri2_out_data, TRANSMIT, TX_BUF_HEADER_BYTE_1, RX_BUF_HEADER_BYTE_1, RX_BUF_FRAME_TYPE, I2C_slave_reg_addr, ALERT_ADDR_LOW, ir_ri2_address, I2C_slave_reg_in, ir_ri1_in_data, ir_ri2_in_data, I2C_slave_reg_in_enb, ALERT_ENB_LOW, ir_ri2_enb, reset, clk);
tx TX( ALERT_TransmitSOP_MessageFailed_TX, ALERT_TransmitSuccessful_TX, MessageID_mismatch, SOP_mismatch, MessageID_SOP_match, TRANSMIT_BYTE_COUNT, TRANSMIT_HEADER_LOW, TRANSMIT_HEADER_HIGH, TRANSMIT_DATA_OBJECTS, Start_CRCReceiveTimer, Stop_CRCReceiverTimer, MessageIDCounter, MessageID, TRANSMIT [2:0], PRL_Rx_Message_Discard, Hard_Reset_received, Cable_Reset_received, RetryCounter, CRCReceiveTimer_Timeout, GoodCRC_Response_from_PHY, Message_discarded_bus_Idle, TX_BUF_HEADER_BYTE_1, RX_BUF_HEADER_BYTE_1, RX_BUF_FRAME_TYPE, clk, reset);
hardReset me_HR(Start_tHardResetComplete_timer, Request_PHY_to_Send_Hard_Reset, Request_PHY_to_Send_Cable_Reset, Stop_PHY_attempting_to_send_Hard_Reset, Stop_PHY_attempting_to_send_Cable_Reset, Stop_tHardResetComplete_timer, ALERT_TransmitSuccessful_HR, ALERT_TransmitSOP_MessageFailed_HR, TRANSMIT[2:0], tHard_Reset_Complete_expires, Hard_Reset_sent, Cable_Reset_sent, tHardResetComplete_expires, reset, clk);
always @(ALERT_TransmitSuccessful_TX,ALERT_TransmitSuccessful_HR, ALERT_TransmitSOP_MessageFailed_TX, ALERT_TransmitSOP_MessageFailed_HR)
begin
ir_ri1_in_data={ALERT_LOW[7:7],ALERT_TransmitSuccessful_HR+ALERT_TransmitSuccessful_TX,ALERT_LOW[5:5],ALERT_TransmitSOP_MessageFailed_HR
+ALERT_TransmitSOP_MessageFailed_TX,ALERT_LOW[3:0]};
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / System Monitor
// /___/ /\ Filename : SYSMONE1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 01/31/13 - Initial version.
// 03/19/13 - Fixed fatal width problem (CR 707214).
// - Update MUXADDR width (CR 706758).
// 03/20/13 - Fixed output MSB problem (CR 706163).
// - Remove SCL and SDA ports (CR 707646).
// 04/26/13 - Add invertible pin support (PR 683925).
// 05/01/13 - Fixed DRC for IS_*_INVERTED parameters (CR 715818).
// 05/08/13 - Changed Vuser1-4 to Vuser 0-3 (CR 716783).
// 06/04/13 - Added I2CSCLK and I2CSDA ports (CR 721147).
// 06/19/13 - Fixed CHANNEL output (CR 717955).
// 10/15/13 - Added I2C simulation support (CR 707725).
// 10/28/13 - Removed DRC for event mode timing (CR 736315).
// 11/15/13 - Updated I2C support for in and output instead of inout (CR 742395).
// 11/22/13 - Updated VBRAM to VCCBRAM (CR 755165).
// 01/21/14 - Added missing timing (CR 767834).
// 01/21/14 - Fixed Vuser (CR 766501).
// 03/20/14 - Fixed event driven mode in single pass sequence (CR 764936).
// 03/21/14 - Balanced all inputs with xor (CR 778933).
// 04/30/14 - Initialized chan_val and chan_valn (CR 782388).
// 05/27/14 - New simulation library message format.
// 06/17/14 - Fixed default mode sequencer (CR 800173)
// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter.
// 10/22/14 - Added #1 to $finish (CR 808642).
// 12/12/14 - Added missing WIDTH timing check for CONVST (CR 836426).
// Updated new temperature calculation (CR 828651).
// 02/04/15 - Fixed DO output with DCLK division 4 or lower (CR 840852).
// 02/19/15 - Fixed I2C initial sync issue (CR 847938).
// 03/06/15 - Fixed I2C addr when I2C_OR = 0 at initial time.
// 03/17/15 - Fixed sequencer out of bound (CR 850975).
// 04/10/15 - Updated new temperature calculation (CR 828651).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
`celldefine
module SYSMONE1 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT_40 = 16'h0000,
parameter [15:0] INIT_41 = 16'h0000,
parameter [15:0] INIT_42 = 16'h0000,
parameter [15:0] INIT_43 = 16'h0000,
parameter [15:0] INIT_44 = 16'h0000,
parameter [15:0] INIT_45 = 16'h0000,
parameter [15:0] INIT_46 = 16'h0000,
parameter [15:0] INIT_47 = 16'h0000,
parameter [15:0] INIT_48 = 16'h0000,
parameter [15:0] INIT_49 = 16'h0000,
parameter [15:0] INIT_4A = 16'h0000,
parameter [15:0] INIT_4B = 16'h0000,
parameter [15:0] INIT_4C = 16'h0000,
parameter [15:0] INIT_4D = 16'h0000,
parameter [15:0] INIT_4E = 16'h0000,
parameter [15:0] INIT_4F = 16'h0000,
parameter [15:0] INIT_50 = 16'h0000,
parameter [15:0] INIT_51 = 16'h0000,
parameter [15:0] INIT_52 = 16'h0000,
parameter [15:0] INIT_53 = 16'h0000,
parameter [15:0] INIT_54 = 16'h0000,
parameter [15:0] INIT_55 = 16'h0000,
parameter [15:0] INIT_56 = 16'h0000,
parameter [15:0] INIT_57 = 16'h0000,
parameter [15:0] INIT_58 = 16'h0000,
parameter [15:0] INIT_59 = 16'h0000,
parameter [15:0] INIT_5A = 16'h0000,
parameter [15:0] INIT_5B = 16'h0000,
parameter [15:0] INIT_5C = 16'h0000,
parameter [15:0] INIT_5D = 16'h0000,
parameter [15:0] INIT_5E = 16'h0000,
parameter [15:0] INIT_5F = 16'h0000,
parameter [15:0] INIT_60 = 16'h0000,
parameter [15:0] INIT_61 = 16'h0000,
parameter [15:0] INIT_62 = 16'h0000,
parameter [15:0] INIT_63 = 16'h0000,
parameter [15:0] INIT_64 = 16'h0000,
parameter [15:0] INIT_65 = 16'h0000,
parameter [15:0] INIT_66 = 16'h0000,
parameter [15:0] INIT_67 = 16'h0000,
parameter [15:0] INIT_68 = 16'h0000,
parameter [15:0] INIT_69 = 16'h0000,
parameter [15:0] INIT_6A = 16'h0000,
parameter [15:0] INIT_6B = 16'h0000,
parameter [15:0] INIT_6C = 16'h0000,
parameter [15:0] INIT_6D = 16'h0000,
parameter [15:0] INIT_6E = 16'h0000,
parameter [15:0] INIT_6F = 16'h0000,
parameter [15:0] INIT_70 = 16'h0000,
parameter [15:0] INIT_71 = 16'h0000,
parameter [15:0] INIT_72 = 16'h0000,
parameter [15:0] INIT_73 = 16'h0000,
parameter [15:0] INIT_74 = 16'h0000,
parameter [15:0] INIT_75 = 16'h0000,
parameter [15:0] INIT_76 = 16'h0000,
parameter [15:0] INIT_77 = 16'h0000,
parameter [15:0] INIT_78 = 16'h0000,
parameter [15:0] INIT_79 = 16'h0000,
parameter [15:0] INIT_7A = 16'h0000,
parameter [15:0] INIT_7B = 16'h0000,
parameter [15:0] INIT_7C = 16'h0000,
parameter [15:0] INIT_7D = 16'h0000,
parameter [15:0] INIT_7E = 16'h0000,
parameter [15:0] INIT_7F = 16'h0000,
parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0,
parameter [0:0] IS_DCLK_INVERTED = 1'b0,
parameter SIM_MONITOR_FILE = "design.txt",
parameter integer SYSMON_VUSER0_BANK = 0,
parameter SYSMON_VUSER0_MONITOR = "NONE",
parameter integer SYSMON_VUSER1_BANK = 0,
parameter SYSMON_VUSER1_MONITOR = "NONE",
parameter integer SYSMON_VUSER2_BANK = 0,
parameter SYSMON_VUSER2_MONITOR = "NONE",
parameter integer SYSMON_VUSER3_BANK = 0,
parameter SYSMON_VUSER3_MONITOR = "NONE"
)(
output [15:0] ALM,
output BUSY,
output [5:0] CHANNEL,
output [15:0] DO,
output DRDY,
output EOC,
output EOS,
output I2C_SCLK_TS,
output I2C_SDA_TS,
output JTAGBUSY,
output JTAGLOCKED,
output JTAGMODIFIED,
output [4:0] MUXADDR,
output OT,
input CONVST,
input CONVSTCLK,
input [7:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input I2C_SCLK,
input I2C_SDA,
input RESET,
input [15:0] VAUXN,
input [15:0] VAUXP,
input VN,
input VP
);
// define constants
localparam MODULE_NAME = "SYSMONE1";
// Parameter encodings and registers
//localparam SIM_DEVICE_ULTRASCALE_PLUS = 0;
//localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 1;
//localparam SIM_DEVICE_ZYNQ_ULTRASCALE = 2;
//localparam SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 = 3;
//localparam SIM_MONITOR_FILE_design_txt = 0;
//localparam SYSMON_VUSER0_MONITOR_NONE = 0;
//localparam SYSMON_VUSER1_MONITOR_NONE = 0;
//localparam SYSMON_VUSER2_MONITOR_NONE = 0;
//localparam SYSMON_VUSER3_MONITOR_NONE = 0;
reg trig_attr = 1'b0;
reg trig_dep_attr = 1'b0;
reg trig_i2c_addr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "SYSMONE1_dr.v"
`else
localparam [15:0] INIT_40_REG = INIT_40;
localparam [15:0] INIT_41_REG = INIT_41;
localparam [15:0] INIT_42_REG = INIT_42;
localparam [15:0] INIT_43_REG = INIT_43;
localparam [15:0] INIT_44_REG = INIT_44;
localparam [15:0] INIT_45_REG = INIT_45;
localparam [15:0] INIT_46_REG = INIT_46;
localparam [15:0] INIT_47_REG = INIT_47;
localparam [15:0] INIT_48_REG = INIT_48;
localparam [15:0] INIT_49_REG = INIT_49;
localparam [15:0] INIT_4A_REG = INIT_4A;
localparam [15:0] INIT_4B_REG = INIT_4B;
localparam [15:0] INIT_4C_REG = INIT_4C;
localparam [15:0] INIT_4D_REG = INIT_4D;
localparam [15:0] INIT_4E_REG = INIT_4E;
localparam [15:0] INIT_4F_REG = INIT_4F;
localparam [15:0] INIT_50_REG = INIT_50;
localparam [15:0] INIT_51_REG = INIT_51;
localparam [15:0] INIT_52_REG = INIT_52;
localparam [15:0] INIT_53_REG = INIT_53;
localparam [15:0] INIT_54_REG = INIT_54;
localparam [15:0] INIT_55_REG = INIT_55;
localparam [15:0] INIT_56_REG = INIT_56;
localparam [15:0] INIT_57_REG = INIT_57;
localparam [15:0] INIT_58_REG = INIT_58;
localparam [15:0] INIT_59_REG = INIT_59;
localparam [15:0] INIT_5A_REG = INIT_5A;
localparam [15:0] INIT_5B_REG = INIT_5B;
localparam [15:0] INIT_5C_REG = INIT_5C;
localparam [15:0] INIT_5D_REG = INIT_5D;
localparam [15:0] INIT_5E_REG = INIT_5E;
localparam [15:0] INIT_5F_REG = INIT_5F;
localparam [15:0] INIT_60_REG = INIT_60;
localparam [15:0] INIT_61_REG = INIT_61;
localparam [15:0] INIT_62_REG = INIT_62;
localparam [15:0] INIT_63_REG = INIT_63;
localparam [15:0] INIT_64_REG = INIT_64;
localparam [15:0] INIT_65_REG = INIT_65;
localparam [15:0] INIT_66_REG = INIT_66;
localparam [15:0] INIT_67_REG = INIT_67;
localparam [15:0] INIT_68_REG = INIT_68;
localparam [15:0] INIT_69_REG = INIT_69;
localparam [15:0] INIT_6A_REG = INIT_6A;
localparam [15:0] INIT_6B_REG = INIT_6B;
localparam [15:0] INIT_6C_REG = INIT_6C;
localparam [15:0] INIT_6D_REG = INIT_6D;
localparam [15:0] INIT_6E_REG = INIT_6E;
localparam [15:0] INIT_6F_REG = INIT_6F;
localparam [15:0] INIT_70_REG = INIT_70;
localparam [15:0] INIT_71_REG = INIT_71;
localparam [15:0] INIT_72_REG = INIT_72;
localparam [15:0] INIT_73_REG = INIT_73;
localparam [15:0] INIT_74_REG = INIT_74;
localparam [15:0] INIT_75_REG = INIT_75;
localparam [15:0] INIT_76_REG = INIT_76;
localparam [15:0] INIT_77_REG = INIT_77;
localparam [15:0] INIT_78_REG = INIT_78;
localparam [15:0] INIT_79_REG = INIT_79;
localparam [15:0] INIT_7A_REG = INIT_7A;
localparam [15:0] INIT_7B_REG = INIT_7B;
localparam [15:0] INIT_7C_REG = INIT_7C;
localparam [15:0] INIT_7D_REG = INIT_7D;
localparam [15:0] INIT_7E_REG = INIT_7E;
localparam [15:0] INIT_7F_REG = INIT_7F;
localparam [0:0] IS_CONVSTCLK_INVERTED_REG = IS_CONVSTCLK_INVERTED;
localparam [0:0] IS_DCLK_INVERTED_REG = IS_DCLK_INVERTED;
localparam [80:1] SIM_MONITOR_FILE_REG = SIM_MONITOR_FILE;
localparam [9:0] SYSMON_VUSER0_BANK_REG = SYSMON_VUSER0_BANK;
localparam [32:1] SYSMON_VUSER0_MONITOR_REG = SYSMON_VUSER0_MONITOR;
localparam [9:0] SYSMON_VUSER1_BANK_REG = SYSMON_VUSER1_BANK;
localparam [32:1] SYSMON_VUSER1_MONITOR_REG = SYSMON_VUSER1_MONITOR;
localparam [9:0] SYSMON_VUSER2_BANK_REG = SYSMON_VUSER2_BANK;
localparam [32:1] SYSMON_VUSER2_MONITOR_REG = SYSMON_VUSER2_MONITOR;
localparam [9:0] SYSMON_VUSER3_BANK_REG = SYSMON_VUSER3_BANK;
localparam [32:1] SYSMON_VUSER3_MONITOR_REG = SYSMON_VUSER3_MONITOR;
`endif
wire [15:0] INIT_40_BIN;
wire [15:0] INIT_41_BIN;
wire [15:0] INIT_42_BIN;
wire [15:0] INIT_43_BIN;
wire [15:0] INIT_44_BIN;
wire [15:0] INIT_45_BIN;
wire [15:0] INIT_46_BIN;
wire [15:0] INIT_47_BIN;
wire [15:0] INIT_48_BIN;
wire [15:0] INIT_49_BIN;
wire [15:0] INIT_4A_BIN;
wire [15:0] INIT_4B_BIN;
wire [15:0] INIT_4C_BIN;
wire [15:0] INIT_4D_BIN;
wire [15:0] INIT_4E_BIN;
wire [15:0] INIT_4F_BIN;
wire [15:0] INIT_50_BIN;
wire [15:0] INIT_51_BIN;
wire [15:0] INIT_52_BIN;
wire [15:0] INIT_53_BIN;
wire [15:0] INIT_54_BIN;
wire [15:0] INIT_55_BIN;
wire [15:0] INIT_56_BIN;
wire [15:0] INIT_57_BIN;
wire [15:0] INIT_58_BIN;
wire [15:0] INIT_59_BIN;
wire [15:0] INIT_5A_BIN;
wire [15:0] INIT_5B_BIN;
wire [15:0] INIT_5C_BIN;
wire [15:0] INIT_5D_BIN;
wire [15:0] INIT_5E_BIN;
wire [15:0] INIT_5F_BIN;
wire [15:0] INIT_60_BIN;
wire [15:0] INIT_61_BIN;
wire [15:0] INIT_62_BIN;
wire [15:0] INIT_63_BIN;
wire [15:0] INIT_64_BIN;
wire [15:0] INIT_65_BIN;
wire [15:0] INIT_66_BIN;
wire [15:0] INIT_67_BIN;
wire [15:0] INIT_68_BIN;
wire [15:0] INIT_69_BIN;
wire [15:0] INIT_6A_BIN;
wire [15:0] INIT_6B_BIN;
wire [15:0] INIT_6C_BIN;
wire [15:0] INIT_6D_BIN;
wire [15:0] INIT_6E_BIN;
wire [15:0] INIT_6F_BIN;
wire [15:0] INIT_70_BIN;
wire [15:0] INIT_71_BIN;
wire [15:0] INIT_72_BIN;
wire [15:0] INIT_73_BIN;
wire [15:0] INIT_74_BIN;
wire [15:0] INIT_75_BIN;
wire [15:0] INIT_76_BIN;
wire [15:0] INIT_77_BIN;
wire [15:0] INIT_78_BIN;
wire [15:0] INIT_79_BIN;
wire [15:0] INIT_7A_BIN;
wire [15:0] INIT_7B_BIN;
wire [15:0] INIT_7C_BIN;
wire [15:0] INIT_7D_BIN;
wire [15:0] INIT_7E_BIN;
wire [15:0] INIT_7F_BIN;
wire IS_CONVSTCLK_INVERTED_BIN;
wire IS_DCLK_INVERTED_BIN;
wire SIM_MONITOR_FILE_BIN;
wire [9:0] SYSMON_VUSER0_BANK_BIN;
wire SYSMON_VUSER0_MONITOR_BIN;
wire [9:0] SYSMON_VUSER1_BANK_BIN;
wire SYSMON_VUSER1_MONITOR_BIN;
wire [9:0] SYSMON_VUSER2_BANK_BIN;
wire SYSMON_VUSER2_MONITOR_BIN;
wire [9:0] SYSMON_VUSER3_BANK_BIN;
wire SYSMON_VUSER3_MONITOR_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg BUSY_out;
reg DRDY_out;
reg EOC_out;
reg EOS_out;
wire I2C_SCLK_TS_out;
reg I2C_SDA_TS_out;
wire JTAGBUSY_out;
wire JTAGLOCKED_out;
wire JTAGMODIFIED_out;
reg OT_out;
reg [15:0] ALM_out;
reg [15:0] DO_out;
reg [4:0] MUXADDR_out;
reg [5:0] CHANNEL_out;
wire CONVSTCLK_in;
wire CONVST_in;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire I2C_SCLK_in;
wire I2C_SDA_in;
wire RESET_in;
wire VN_in;
wire VP_in;
wire [15:0] DI_in;
wire [15:0] VAUXN_in;
wire [15:0] VAUXP_in;
wire [7:0] DADDR_in;
`ifdef XIL_TIMING
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire [15:0] DI_delay;
wire [7:0] DADDR_delay;
wire RESET_delay;
`endif
assign ALM = ALM_out;
assign BUSY = BUSY_out;
assign CHANNEL = CHANNEL_out;
assign DO = DO_out;
assign DRDY = DRDY_out;
assign EOC = EOC_out;
assign EOS = EOS_out;
assign I2C_SCLK_TS = I2C_SCLK_TS_out;
assign I2C_SDA_TS = I2C_SDA_TS_out;
assign JTAGBUSY = JTAGBUSY_out;
assign JTAGLOCKED = JTAGLOCKED_out;
assign JTAGMODIFIED = JTAGMODIFIED_out;
assign MUXADDR = MUXADDR_out;
assign OT = OT_out;
wire [7:0] DADDR_inv;
wire DCLK_inv;
wire DEN_inv;
wire DWE_inv;
wire RESET_in_inv;
wire [15:0] DI_inv;
wire I2C_SCLK_inv;
wire I2C_SDA_inv;
`ifdef XIL_TIMING
assign DADDR_inv = DADDR_delay;
assign DCLK_inv = DCLK_delay;
assign DEN_inv = DEN_delay;
assign DI_inv = DI_delay;
assign DWE_inv = DWE_delay;
`else
assign DADDR_inv = DADDR;
assign DCLK_inv = DCLK;
assign DEN_inv = DEN;
assign DI_inv = DI;
assign DWE_inv = DWE;
`endif
assign I2C_SCLK_inv = I2C_SCLK;
assign I2C_SDA_inv = I2C_SDA;
assign DADDR_in = DADDR_inv ^ 7'b0000000;
assign DCLK_in = DCLK_inv ^ IS_DCLK_INVERTED_BIN;
assign DEN_in = DEN_inv ^ 1'b0;
assign DI_in = DI_inv ^ 16'h0000;
assign DWE_in = DWE_inv ^ 1'b0;
assign RESET_in = RESET;
assign CONVSTCLK_in = CONVSTCLK ^ IS_CONVSTCLK_INVERTED_BIN;
assign CONVST_in = CONVST ^ 1'b0;
assign I2C_SCLK_in = I2C_SCLK_inv ^ 1'b0;
assign I2C_SDA_in = I2C_SDA_inv ^ 1'b0;
assign VAUXN_in = VAUXN;
assign VAUXP_in = VAUXP;
assign VN_in = VN;
assign VP_in = VP;
assign INIT_40_BIN = INIT_40_REG;
assign INIT_41_BIN = INIT_41_REG;
assign INIT_42_BIN = INIT_42_REG;
assign INIT_43_BIN = INIT_43_REG;
assign INIT_44_BIN = INIT_44_REG;
assign INIT_45_BIN = INIT_45_REG;
assign INIT_46_BIN = INIT_46_REG;
assign INIT_47_BIN = INIT_47_REG;
assign INIT_48_BIN = INIT_48_REG;
assign INIT_49_BIN = INIT_49_REG;
assign INIT_4A_BIN = INIT_4A_REG;
assign INIT_4B_BIN = INIT_4B_REG;
assign INIT_4C_BIN = INIT_4C_REG;
assign INIT_4D_BIN = INIT_4D_REG;
assign INIT_4E_BIN = INIT_4E_REG;
assign INIT_4F_BIN = INIT_4F_REG;
assign INIT_50_BIN = INIT_50_REG;
assign INIT_51_BIN = INIT_51_REG;
assign INIT_52_BIN = INIT_52_REG;
assign INIT_53_BIN = INIT_53_REG;
assign INIT_54_BIN = INIT_54_REG;
assign INIT_55_BIN = INIT_55_REG;
assign INIT_56_BIN = INIT_56_REG;
assign INIT_57_BIN = INIT_57_REG;
assign INIT_58_BIN = INIT_58_REG;
assign INIT_59_BIN = INIT_59_REG;
assign INIT_5A_BIN = INIT_5A_REG;
assign INIT_5B_BIN = INIT_5B_REG;
assign INIT_5C_BIN = INIT_5C_REG;
assign INIT_5D_BIN = INIT_5D_REG;
assign INIT_5E_BIN = INIT_5E_REG;
assign INIT_5F_BIN = INIT_5F_REG;
assign INIT_60_BIN = INIT_60_REG;
assign INIT_61_BIN = INIT_61_REG;
assign INIT_62_BIN = INIT_62_REG;
assign INIT_63_BIN = INIT_63_REG;
assign INIT_64_BIN = INIT_64_REG;
assign INIT_65_BIN = INIT_65_REG;
assign INIT_66_BIN = INIT_66_REG;
assign INIT_67_BIN = INIT_67_REG;
assign INIT_68_BIN = INIT_68_REG;
assign INIT_69_BIN = INIT_69_REG;
assign INIT_6A_BIN = INIT_6A_REG;
assign INIT_6B_BIN = INIT_6B_REG;
assign INIT_6C_BIN = INIT_6C_REG;
assign INIT_6D_BIN = INIT_6D_REG;
assign INIT_6E_BIN = INIT_6E_REG;
assign INIT_6F_BIN = INIT_6F_REG;
assign INIT_70_BIN = INIT_70_REG;
assign INIT_71_BIN = INIT_71_REG;
assign INIT_72_BIN = INIT_72_REG;
assign INIT_73_BIN = INIT_73_REG;
assign INIT_74_BIN = INIT_74_REG;
assign INIT_75_BIN = INIT_75_REG;
assign INIT_76_BIN = INIT_76_REG;
assign INIT_77_BIN = INIT_77_REG;
assign INIT_78_BIN = INIT_78_REG;
assign INIT_79_BIN = INIT_79_REG;
assign INIT_7A_BIN = INIT_7A_REG;
assign INIT_7B_BIN = INIT_7B_REG;
assign INIT_7C_BIN = INIT_7C_REG;
assign INIT_7D_BIN = INIT_7D_REG;
assign INIT_7E_BIN = INIT_7E_REG;
assign INIT_7F_BIN = INIT_7F_REG;
assign IS_CONVSTCLK_INVERTED_BIN = IS_CONVSTCLK_INVERTED_REG;
assign IS_DCLK_INVERTED_BIN = IS_DCLK_INVERTED_REG;
// assign SIM_DEVICE_BIN =
// (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS :
// (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 :
// (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE") ? SIM_DEVICE_ZYNQ_ULTRASCALE :
// (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE_ES1") ? SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 :
// SIM_DEVICE_ULTRASCALE_PLUS;
//
// assign SIM_MONITOR_FILE_BIN =
// (SIM_MONITOR_FILE_REG == "design.txt") ? SIM_MONITOR_FILE_design_txt :
// SIM_MONITOR_FILE_design_txt;
//
assign SYSMON_VUSER0_BANK_BIN = SYSMON_VUSER0_BANK_REG;
// assign SYSMON_VUSER0_MONITOR_BIN =
// (SYSMON_VUSER0_MONITOR_REG == "NONE") ? SYSMON_VUSER0_MONITOR_NONE :
// SYSMON_VUSER0_MONITOR_NONE;
assign SYSMON_VUSER1_BANK_BIN = SYSMON_VUSER1_BANK_REG;
// assign SYSMON_VUSER1_MONITOR_BIN =
// (SYSMON_VUSER1_MONITOR_REG == "NONE") ? SYSMON_VUSER1_MONITOR_NONE :
// SYSMON_VUSER1_MONITOR_NONE;
assign SYSMON_VUSER2_BANK_BIN = SYSMON_VUSER2_BANK_REG;
// assign SYSMON_VUSER2_MONITOR_BIN =
// (SYSMON_VUSER2_MONITOR_REG == "NONE") ? SYSMON_VUSER2_MONITOR_NONE :
// SYSMON_VUSER2_MONITOR_NONE;
assign SYSMON_VUSER3_BANK_BIN = SYSMON_VUSER3_BANK_REG;
// assign SYSMON_VUSER3_MONITOR_BIN =
// (SYSMON_VUSER3_MONITOR_REG == "NONE") ? SYSMON_VUSER3_MONITOR_NONE :
// SYSMON_VUSER3_MONITOR_NONE;
initial begin
trig_attr = 0;
#1;
trig_i2c_addr = 1;
trig_attr = 1;
#2 trig_dep_attr = 1;
end
always @(posedge trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SYSMON_VUSER0_BANK_REG < 0) || (SYSMON_VUSER0_BANK_REG > 999))) begin
$display("Error: [Unisim %s-170] SYSMON_VUSER0_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER0_BANK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER1_BANK_REG < 0) || (SYSMON_VUSER1_BANK_REG > 999))) begin
$display("Error: [Unisim %s-172] SYSMON_VUSER1_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER1_BANK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER2_BANK_REG < 0) || (SYSMON_VUSER2_BANK_REG > 999))) begin
$display("Error: [Unisim %s-174] SYSMON_VUSER2_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER2_BANK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER3_BANK_REG < 0) || (SYSMON_VUSER3_BANK_REG > 999))) begin
$display("Error: [Unisim %s-176] SYSMON_VUSER3_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER3_BANK_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end // always @ (trig_attr)
always @(trig_dep_attr) begin
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[8]==1) && (INIT_40_BIN[5:0] != 6'b000011) && (INIT_40_BIN[5:0] < 6'b010000)))
$display("Warning: [Unisim %s-1] INIT_40 attribute is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_40_BIN);
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]!=4'b0011) && (INIT_4E_BIN[10:0]!=11'd0) && (INIT_4E_BIN[15:12]!=4'd0)))
$display("Warning: [Unisim %s-2] INIT_4E attribute is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_4E_BIN);
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[13:12]!=2'b00) && (INIT_46_BIN != 16'h0000) && (INIT_48_BIN != 16'h0000) && (INIT_49_BIN != 16'h0000)))
$display("Warning: [Unisim %s-3] INIT_46, INIT_48 and INIT_49 attributes are set to %x, %x, and %x respectively. These attributes must be set to 0000h in single channel mode with averaging enabled. Instance: %m", MODULE_NAME, INIT_46_BIN, INIT_48_BIN, INIT_49_BIN);
// CR1004434
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]==4'b0001|| INIT_41_BIN[15:12]==4'b0010) && INIT_46_BIN[3:0]!=4'b0000) || //single pass or cont mode and vuser selected
(INIT_41_BIN[15:12]==4'b0011 && INIT_40_BIN[5:2]==4'b1000) //single channel mode and vuser is selected
)
$display("Warning: [Unisim %s-177] INIT_40 and INIT_41 attributes are set to %x and %x respectively. VUSER is selected. In Kintex devices, SYSMONE1 model has no way of knowing whether VUSER has a 6V range or a 3V range and assumes all channels have 3V range. If HR banks are selected, the value stored in the model's registers will be different than that of the actual hardware; and only for this specific case VUSER simulation checks should be ignored. Instance: %m", MODULE_NAME, INIT_40_BIN, INIT_41_BIN);
end // always @ (trig_dep_attr)
// Total UNISIM %s- warning message next: 59
localparam CONV_CNT_P = 37;
localparam CONV_CNT = 48;
//Convergence periods
localparam CONV_CAL_PER_RST = 6;
localparam CONV_CAL_PER_0 = 2;
localparam CONV_NOTCAL_PER_1 = 18; // //minus 3 ->old comment
localparam CONV_CAL_PER_2 = 96;
localparam CONV_CAL_PER_3 = 96;
localparam CONV_CAL_PER_4 = 44;
localparam CONV_CAL_PER_5 = 21;
//sequencer operation
localparam [3:0] SEQ_DEFAULT_MODE = 4'b0000 ;
localparam [1:0] SEQ_DEFAULT_MODE2 = 2'b11 ;
localparam [3:0] SEQ_SINGLE_PASS = 4'b0001 ;
localparam [3:0] SEQ_CONT_CHAN = 4'b0010 ;
localparam [3:0] SEQ_SINGLE_CHAN = 4'b0011 ;//means sequencer is off
//`define CALIBRATION_ALWAYS_FIRST
//adc_state
localparam S0_ST = 0,
S1_ST = 1,
S2_ST = 2,
S3_ST = 3,
S5_ST = 5,
S6_ST = 6;
time time_out, prev_time_out;
integer temperature_index = -1, time_index = -1, vccaux_index = -1;
integer vccbram_index = -1;
integer vccint_index = -1, vn_index = -1, vp_index = -1;
integer vccpint_index = -1;
integer vccpaux_index = -1;
integer vccpdro_index = -1;
integer vauxp_idx[15:0]; integer vauxn_idx[15:0];
integer vuser0_index = -1, vuser1_index = -1;
integer vuser2_index = -1, vuser3_index = -1;
integer char_1, char_2, fs, fd;
integer num_arg, num_val;
integer clk_count;
reg clk_count_rst = 0;
integer seq_count, seq_count_a;
integer seq_status_avg, acq_count;
integer conv_avg_count [63:0];
wire [7:0] avg_amount;
integer conv_acc [63:0];
integer conv_result_int;
integer conv_count;
integer h, i, j, k, l, m, n, p;
integer file_line;
// string
reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46;
reg [8*600:1] one_line;
reg [8*12:1] label [46:0];
reg [8*12:1] tmp_label;
reg end_of_file;
real tmp_va0, tmp_va1, column_real00, column_real100, column_real101;
real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46;
// array of real numbers
reg [63:0] column_real [CONV_CNT-1 :0];
reg [63:0] chan_val [CONV_CNT_P-1:0];
reg [63:0] chan_val_tmp [CONV_CNT_P-1:0];
reg [63:0] chan_valn [CONV_CNT_P-1:0];
reg [63:0] chan_valn_tmp [CONV_CNT_P-1:0];
reg [63:0] mn_in_diff [CONV_CNT_P-1:0];
reg [63:0] mn_in2_diff [CONV_CNT_P-1:0];
reg [63:0] mn_in_uni [CONV_CNT_P-1:0];
reg [63:0] mn_in2_uni [CONV_CNT_P-1:0];
reg [63:0] mn_comm_in [CONV_CNT_P-1:0];
reg [63:0] mn_comm2_in [CONV_CNT_P-1:0];
real chan_val_p_tmp, chan_val_n_tmp;
real mn_mux_in, mn_in_tmp, mn_comm_in_tmp, mn_in_comm;
real tmp_v, tmp_v1;
real adc_temp_result, adc_intpwr_result;
real adc_ext_result;
reg seq_reset, seq_reset_dly, seq_reset_flag, seq_reset_flag_dly;
reg soft_reset = 0;
reg en_data_flag;
reg first_cal_chan;
reg seq_en;
reg seq_en_dly;
wire [15:0] flag_reg0, flag_reg1;
reg [15:0] ot_limit_reg = 16'hCA30;
reg [15:0] tmp_otv;
reg [23:0] conv_acc_vec;
reg [15:0] conv_result;
reg [15:0] conv_result_reg, conv_acc_result;
wire [7:0] curr_clkdiv_sel;
reg [15:0] alm_out_reg;
reg [5:0] curr_chan, curr_chan_lat;
reg [15:0] data_written;
reg [2:0] adc_state, adc_next_state;
reg conv_start, conv_end;
reg eos_en, eos_tmp_en;
reg DRDY_out_tmp1, DRDY_out_tmp2, DRDY_out_tmp3;
reg ot_out_reg;
reg [15:0] DO_out_rdtmp;
reg [15:0] data_reg [63:0];
reg [15:0] dr_sram [255:64];
reg sysclk;
reg adcclk_tmp;
wire adcclk;
wire sysmone1_en, sysmone12_en;
reg [3:0] curr_seq1_0;
reg [3:0] curr_seq1_0_lat;
reg curr_e_c, curr_b_u, curr_acq;
reg seq_count_en;
reg [5:0] acq_chan;
reg [4:0] acq_chan_m;
wire ext_mux_en;
wire [5:0] ext_mux_chan;
wire default_mode;
wire single_pass_mode;
wire cont_seq_mode;
wire single_chan_mode;
reg acq_b_u;
reg single_pass_finished;
reg acq_acqsel;
wire acq_e_c;
reg acq_e_c_tmp5, acq_e_c_tmp6;
reg [1:0] averaging, averaging_d;
reg eoc_en, eoc_en_delay;
reg EOC_out_tmp, EOS_out_tmp;
reg EOC_out_tmp1, EOS_out_tmp1;
reg EOC_out_pre;
reg EOC_out_pre2;
reg busy_r, busy_r_rst;
reg busy_sync1, busy_sync2;
wire busy_sync_fall, busy_sync_rise;
reg rst_lock, rst_lock_early, rst_lock_late;
reg sim_file_flag;
reg [7:0] DADDR_in_lat;
reg [15:0] curr_seq, curr_seq_m;
reg busy_rst, busy_conv, busy_seq_rst;
wire [3:0] seq1_0;
reg [3:0] seq_bits;
reg ot_en, alm_update, drp_update, cal_chan_update;
reg [13:0] alm_en;
reg [4:0] scon_tmp;
wire [15:0] seq_chan_reg1, seq_chan_reg2, seq_chan_reg3;
wire [15:0] seq_acq_reg1, seq_acq_reg2, seq_acq_reg3;
wire [15:0] seq_avg_reg1, seq_avg_reg2, seq_avg_reg3;
wire [15:0] seq_bu_reg1, seq_bu_reg2, seq_bu_reg3;
reg [15:0] cfg_reg1_init;
reg [5:0] seq_curr_i, seq_curr_ia;
integer busy_rst_cnt;
integer si;
integer hr_tot_chan;
integer seq_mem [37:0];
wire rst_in, adc_convst;
wire [15:0] cfg_reg0;
wire [15:0] cfg_reg1;
wire [15:0] cfg_reg2;
wire [15:0] cfg_reg3;
reg reserved_addr_pre;
reg read_only_pre;
reg RESERVED_ADDR;
reg READ_ONLY;
wire i2c_addr_cap = 0;
wire i2c_addr_cap_ne;
reg i2c_addr_cap_d;
wire convst_in_pre;
reg CONVST_reg;
wire rst_in_not_seq;
wire adcclk_div1;
wire gsr_in;
assign JTAGBUSY_out = 0;
assign JTAGLOCKED_out = 0;
assign JTAGMODIFIED_out = 0;
assign gsr_in = glblGSR;
// initialize chan_val and chan_valn
integer ii, jj;
initial begin
for (ii = 0; ii < CONV_CNT_P; ii = ii + 1)
chan_val[ii] = 64'd0;
for (jj = 0; jj < 36; jj = jj + 1)
chan_valn[jj] = 64'd0;
end
// initialize vauxn_idx and vauxp_idx
integer mm, nn;
initial begin
for (mm = 0; mm < 16; mm = mm + 1)
vauxn_idx[mm] = -1;
for (nn = 0; nn < 16; nn = nn + 1)
vauxp_idx[nn] = -1;
end
//CR 675227
//for single pass mode
integer halt_adc = 0;
reg int_rst;
reg int_rst_halt_adc = 0;
always @(posedge RESET_in)
halt_adc <= 0;
always @(seq1_0) begin
if (halt_adc == 2 && single_pass_mode) begin
halt_adc <= 0;
int_rst_halt_adc <= 1;
@(posedge DCLK_in)
int_rst_halt_adc <= 0;
end
end
real i2c_vpvn_addr_tmp;
integer i2c_conv_result_int;
reg i2c_en;
reg i2c_oride;
reg [6:0] i2c_device_addr;
reg [6:0] i2c_device_addr_vpvn;
reg [15:0] conv_result_i2c_addr;
initial begin
i2c_en = 1;
end
// I2C slave address mapping
always @(*) begin
i2c_en = cfg_reg3[7];
i2c_oride = cfg_reg3[15];
i2c_device_addr = (i2c_oride) ? cfg_reg3[14:8]: i2c_device_addr_vpvn;
end
assign convst_in_pre = (CONVST_in===1 || CONVSTCLK_in===1) ? 1: 0;
always @(posedge convst_in_pre or negedge convst_in_pre or posedge rst_in)
if (rst_in == 1 || rst_lock == 1)
CONVST_reg <= 0;
else if (convst_in_pre == 1)
CONVST_reg <= 1;
else if (convst_in_pre == 0)
CONVST_reg <= 0;
always @(posedge trig_attr) begin
dr_sram[8'h40] = INIT_40_BIN;
dr_sram[8'h41] = INIT_41_BIN;
dr_sram[8'h42] = INIT_42_BIN;
dr_sram[8'h43] = INIT_43_BIN;
dr_sram[8'h44] = INIT_44_BIN;
dr_sram[8'h45] = INIT_45_BIN;
dr_sram[8'h46] = INIT_46_BIN;
dr_sram[8'h47] = INIT_47_BIN;
dr_sram[8'h48] = INIT_48_BIN;
dr_sram[8'h49] = INIT_49_BIN;
dr_sram[8'h4A] = INIT_4A_BIN;
dr_sram[8'h4B] = INIT_4B_BIN;
dr_sram[8'h4C] = INIT_4C_BIN;
dr_sram[8'h4D] = INIT_4D_BIN;
dr_sram[8'h4E] = INIT_4E_BIN;
dr_sram[8'h4F] = INIT_4F_BIN;
dr_sram[8'h50] = INIT_50_BIN;
dr_sram[8'h51] = INIT_51_BIN;
dr_sram[8'h52] = INIT_52_BIN;
tmp_otv = INIT_53_BIN;
if (tmp_otv [3:0] == 4'b0011) begin
dr_sram[8'h53] = INIT_53_BIN;
ot_limit_reg = INIT_53_BIN;
end
else begin
dr_sram[8'h53] = 16'hCA30;
ot_limit_reg = 16'hCA30;
end
dr_sram[8'h54] = INIT_54_BIN;
dr_sram[8'h55] = INIT_55_BIN;
dr_sram[8'h56] = INIT_56_BIN;
dr_sram[8'h57] = INIT_57_BIN;
dr_sram[8'h58] = INIT_58_BIN;
dr_sram[8'h59] = INIT_59_BIN;
dr_sram[8'h5A] = INIT_5A_BIN;
dr_sram[8'h5B] = INIT_5B_BIN;
dr_sram[8'h5C] = INIT_5C_BIN;
dr_sram[8'h5D] = INIT_5D_BIN;
dr_sram[8'h5E] = INIT_5E_BIN;
dr_sram[8'h5F] = INIT_5F_BIN;
dr_sram[8'h60] = INIT_60_BIN;
dr_sram[8'h61] = INIT_61_BIN;
dr_sram[8'h62] = INIT_62_BIN;
dr_sram[8'h63] = INIT_63_BIN;
dr_sram[8'h68] = INIT_68_BIN;
dr_sram[8'h69] = INIT_69_BIN;
dr_sram[8'h6A] = INIT_6A_BIN;
dr_sram[8'h6B] = INIT_6B_BIN;
dr_sram[8'h78] = INIT_78_BIN;
dr_sram[8'h79] = INIT_79_BIN;
dr_sram[8'h7A] = INIT_7A_BIN;
dr_sram[8'h7B] = INIT_7B_BIN;
dr_sram[8'h7C] = INIT_7C_BIN;
end // always @ (trig_attr)
// read input file
initial begin
char_1 = 0;
char_2 = 0;
time_out = 0;
sim_file_flag = 0;
file_line = -1;
end_of_file = 0;
fd = $fopen(SIM_MONITOR_FILE, "r");
if (fd == 0) begin
$display("Error: [Unisim %s-4] The analog data file %s was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt. Instance: %m", MODULE_NAME, SIM_MONITOR_FILE);
sim_file_flag = 1;
#1 $finish;
end
if (sim_file_flag == 0) begin
while (end_of_file==0) begin
file_line = file_line + 1;
char_1 = $fgetc (fd);
char_2 = $fgetc (fd);
//if(char_2==`EOFile)
if(char_2== -1)
end_of_file = 1;
else begin // not end of file
// Ignore Comments
if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
// Getting labels
else if ((char_1 == "T" & char_2 == "I" ) ||
(char_1 == "T" & char_2 == "i" ) ||
(char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s ",
label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46);
label[0] = label0;
label[1] = label1;
label[2] = label2;
label[3] = label3;
label[4] = label4;
label[5] = label5;
label[6] = label6;
label[7] = label7;
label[8] = label8;
label[9] = label9;
label[10] = label10;
label[11] = label11;
label[12] = label12;
label[13] = label13;
label[14] = label14;
label[15] = label15;
label[16] = label16;
label[17] = label17;
label[18] = label18;
label[19] = label19;
label[20] = label20;
label[21] = label21;
label[22] = label22;
label[23] = label23;
label[24] = label24;
label[25] = label25;
label[26] = label26;
label[27] = label27;
label[28] = label28;
label[29] = label29;
label[30] = label30;
label[31] = label31;
label[32] = label32;
label[33] = label33;
label[34] = label34;
label[35] = label35;
label[36] = label36;
label[37] = label37;
label[38] = label38;
label[39] = label39;
label[40] = label40;
label[41] = label41;
label[42] = label42;
label[43] = label43;
label[44] = label44;
label[45] = label45;
label[46] = label46;
for (m = 0; m < num_arg; m = m +1) begin
tmp_label = 96'b0;
tmp_label = to_upcase_label(label[m]);
case (tmp_label)
"TEMP" : temperature_index = m;
"TIME" : time_index = m;
"VCCAUX" : vccaux_index = m;
"VCCINT" : vccint_index = m;
"VCCBRAM" : vccbram_index = m;
"VCCPINT" : vccpint_index = m;
"VCCPAUX" : vccpaux_index = m;
"VCCDDRO" : vccpdro_index = m;
"VN" : vn_index = m;
"VAUXN[0]" : vauxn_idx[0] = m;
"VAUXN[1]" : vauxn_idx[1] = m;
"VAUXN[2]" : vauxn_idx[2] = m;
"VAUXN[3]" : vauxn_idx[3] = m;
"VAUXN[4]" : vauxn_idx[4] = m;
"VAUXN[5]" : vauxn_idx[5] = m;
"VAUXN[6]" : vauxn_idx[6] = m;
"VAUXN[7]" : vauxn_idx[7] = m;
"VAUXN[8]" : vauxn_idx[8] = m;
"VAUXN[9]" : vauxn_idx[9] = m;
"VAUXN[10]" : vauxn_idx[10] = m;
"VAUXN[11]" : vauxn_idx[11] = m;
"VAUXN[12]" : vauxn_idx[12] = m;
"VAUXN[13]" : vauxn_idx[13] = m;
"VAUXN[14]" : vauxn_idx[14] = m;
"VAUXN[15]" : vauxn_idx[15] = m;
"VP" : vp_index = m;
"VAUXP[0]" : vauxp_idx[0] = m;
"VAUXP[1]" : vauxp_idx[1] = m;
"VAUXP[2]" : vauxp_idx[2] = m;
"VAUXP[3]" : vauxp_idx[3] = m;
"VAUXP[4]" : vauxp_idx[4] = m;
"VAUXP[5]" : vauxp_idx[5] = m;
"VAUXP[6]" : vauxp_idx[6] = m;
"VAUXP[7]" : vauxp_idx[7] = m;
"VAUXP[8]" : vauxp_idx[8] = m;
"VAUXP[9]" : vauxp_idx[9] = m;
"VAUXP[10]" : vauxp_idx[10] = m;
"VAUXP[11]" : vauxp_idx[11] = m;
"VAUXP[12]" : vauxp_idx[12] = m;
"VAUXP[13]" : vauxp_idx[13] = m;
"VAUXP[14]" : vauxp_idx[14] = m;
"VAUXP[15]" : vauxp_idx[15] = m;
"VUSER0" : vuser0_index = m;
"VUSER1" : vuser1_index = m;
"VUSER2" : vuser2_index = m;
"VUSER3" : vuser3_index = m;
default : begin
$display("Error: [Unisim %s-5] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label);
infile_format;
end
endcase
end // for (m = 0; m < num_arg; m = m +1)
end // Getting labels
// Getting column values
else if (char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
column_real0 = 0.0;
column_real1 = 0.0;
column_real2 = 0.0;
column_real3 = 0.0;
column_real4 = 0.0;
column_real5 = 0.0;
column_real6 = 0.0;
column_real7 = 0.0;
column_real8 = 0.0;
column_real9 = 0.0;
column_real10 = 0.0;
column_real11 = 0.0;
column_real12 = 0.0;
column_real13 = 0.0;
column_real14 = 0.0;
column_real15 = 0.0;
column_real16 = 0.0;
column_real17 = 0.0;
column_real18 = 0.0;
column_real19 = 0.0;
column_real20 = 0.0;
column_real21 = 0.0;
column_real22 = 0.0;
column_real23 = 0.0;
column_real24 = 0.0;
column_real25 = 0.0;
column_real26 = 0.0;
column_real27 = 0.0;
column_real28 = 0.0;
column_real29 = 0.0;
column_real30 = 0.0;
column_real31 = 0.0;
column_real32 = 0.0;
column_real33 = 0.0;
column_real34 = 0.0;
column_real35 = 0.0;
column_real36 = 0.0;
column_real37 = 0.0;
column_real38 = 0.0;
column_real39 = 0.0;
column_real40 = 0.0;
column_real41 = 0.0;
column_real42 = 0.0;
column_real43 = 0.0;
column_real44 = 0.0;
column_real45 = 0.0;
column_real46 = 0.0;
num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46);
column_real[0] = $realtobits(column_real0);
column_real[1] = $realtobits(column_real1);
column_real[2] = $realtobits(column_real2);
column_real[3] = $realtobits(column_real3);
column_real[4] = $realtobits(column_real4);
column_real[5] = $realtobits(column_real5);
column_real[6] = $realtobits(column_real6);
column_real[7] = $realtobits(column_real7);
column_real[8] = $realtobits(column_real8);
column_real[9] = $realtobits(column_real9);
column_real[10] = $realtobits(column_real10);
column_real[11] = $realtobits(column_real11);
column_real[12] = $realtobits(column_real12);
column_real[13] = $realtobits(column_real13);
column_real[14] = $realtobits(column_real14);
column_real[15] = $realtobits(column_real15);
column_real[16] = $realtobits(column_real16);
column_real[17] = $realtobits(column_real17);
column_real[18] = $realtobits(column_real18);
column_real[19] = $realtobits(column_real19);
column_real[20] = $realtobits(column_real20);
column_real[21] = $realtobits(column_real21);
column_real[22] = $realtobits(column_real22);
column_real[23] = $realtobits(column_real23);
column_real[24] = $realtobits(column_real24);
column_real[25] = $realtobits(column_real25);
column_real[26] = $realtobits(column_real26);
column_real[27] = $realtobits(column_real27);
column_real[28] = $realtobits(column_real28);
column_real[29] = $realtobits(column_real29);
column_real[30] = $realtobits(column_real30);
column_real[31] = $realtobits(column_real31);
column_real[32] = $realtobits(column_real32);
column_real[33] = $realtobits(column_real33);
column_real[34] = $realtobits(column_real34);
column_real[35] = $realtobits(column_real35);
column_real[36] = $realtobits(column_real36);
column_real[37] = $realtobits(column_real37);
column_real[38] = $realtobits(column_real38);
column_real[39] = $realtobits(column_real39);
column_real[40] = $realtobits(column_real40);
column_real[41] = $realtobits(column_real41);
column_real[42] = $realtobits(column_real42);
column_real[43] = $realtobits(column_real43);
column_real[44] = $realtobits(column_real44);
column_real[45] = $realtobits(column_real45);
column_real[46] = $realtobits(column_real46);
chan_val[0] = column_real[temperature_index];
chan_val[1] = column_real[vccint_index];
chan_val[2] = column_real[vccaux_index];
chan_val[3] = column_real[vp_index];
chan_val[6] = column_real[vccbram_index];
chan_val[13] = column_real[vccpint_index];
chan_val[14] = column_real[vccpaux_index];
chan_val[15] = column_real[vccpdro_index];
chan_val[16] = column_real[vauxp_idx[0]];
chan_val[17] = column_real[vauxp_idx[1]];
chan_val[18] = column_real[vauxp_idx[2]];
chan_val[19] = column_real[vauxp_idx[3]];
chan_val[20] = column_real[vauxp_idx[4]];
chan_val[21] = column_real[vauxp_idx[5]];
chan_val[22] = column_real[vauxp_idx[6]];
chan_val[23] = column_real[vauxp_idx[7]];
chan_val[24] = column_real[vauxp_idx[8]];
chan_val[25] = column_real[vauxp_idx[9]];
chan_val[26] = column_real[vauxp_idx[10]];
chan_val[27] = column_real[vauxp_idx[11]];
chan_val[28] = column_real[vauxp_idx[12]];
chan_val[29] = column_real[vauxp_idx[13]];
chan_val[30] = column_real[vauxp_idx[14]];
chan_val[31] = column_real[vauxp_idx[15]];
chan_val[32] = column_real[vuser0_index];
chan_val[33] = column_real[vuser1_index];
chan_val[34] = column_real[vuser2_index];
chan_val[35] = column_real[vuser3_index];
chan_valn[3] = column_real[vn_index];
chan_valn[16] = column_real[vauxn_idx[0]];
chan_valn[17] = column_real[vauxn_idx[1]];
chan_valn[18] = column_real[vauxn_idx[2]];
chan_valn[19] = column_real[vauxn_idx[3]];
chan_valn[20] = column_real[vauxn_idx[4]];
chan_valn[21] = column_real[vauxn_idx[5]];
chan_valn[22] = column_real[vauxn_idx[6]];
chan_valn[23] = column_real[vauxn_idx[7]];
chan_valn[24] = column_real[vauxn_idx[8]];
chan_valn[25] = column_real[vauxn_idx[9]];
chan_valn[26] = column_real[vauxn_idx[10]];
chan_valn[27] = column_real[vauxn_idx[11]];
chan_valn[28] = column_real[vauxn_idx[12]];
chan_valn[29] = column_real[vauxn_idx[13]];
chan_valn[30] = column_real[vauxn_idx[14]];
chan_valn[31] = column_real[vauxn_idx[15]];
// identify columns
if (time_index != -1) begin
prev_time_out = time_out;
time_out = $bitstoreal(column_real[time_index]);
if (prev_time_out > time_out) begin
$display("Error: [Unisim %s-6] Time value %f is invalid in the input file. Time value should be increasing. Instance: %m", MODULE_NAME, time_out);
infile_format;
end
end
else begin
$display("Error: [Unisim %s-7] No TIME label is found in the analog data file. Instance: %m", MODULE_NAME);
infile_format;
#1 $finish;
end
# ((time_out - prev_time_out) * 1000);
for (p = 0; p < CONV_CNT_P; p = p + 1) begin
// assign to real before minus - to work around a bug in modelsim
chan_val_tmp[p] = chan_val[p];
chan_valn_tmp[p] = chan_valn[p];
mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]);
mn_in_diff[p] = $realtobits(mn_in_tmp);
mn_in_uni[p] = chan_val[p];
end
end // if (char_1 == "0" | char_1 == "9")
// Ignore any non-comment, label
else begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
end
end // while (end_file == 0)
end // if (sim_file_flag == 0)
end // initial begin
// Obtain I2C slave address powerup value
always @(posedge trig_i2c_addr) begin
i2c_vpvn_addr_tmp = $bitstoreal(mn_in_uni[3]) * 65536.0;
if (i2c_vpvn_addr_tmp > 65535.0)
i2c_conv_result_int = 65535;
else if (i2c_vpvn_addr_tmp < 0.0)
i2c_conv_result_int = 0;
else begin
i2c_conv_result_int = $rtoi(i2c_vpvn_addr_tmp);
if (i2c_vpvn_addr_tmp - i2c_conv_result_int > 0.9999)
i2c_conv_result_int = i2c_conv_result_int + 1;
end
// I2C address measured and assigned at startup is recorded at address 38h
conv_result_i2c_addr = i2c_conv_result_int;
if(!i2c_oride)
data_reg[56] = i2c_conv_result_int;
// convert i2c address
case (conv_result_i2c_addr[15:12])
4'h0 : i2c_device_addr_vpvn = 7'b0110010;
4'h1 : i2c_device_addr_vpvn = 7'b0001011;
4'h2 : i2c_device_addr_vpvn = 7'b0010011;
4'h3 : i2c_device_addr_vpvn = 7'b0011011;
4'h4 : i2c_device_addr_vpvn = 7'b0100011;
4'h5 : i2c_device_addr_vpvn = 7'b0101011;
4'h6 : i2c_device_addr_vpvn = 7'b0110011;
4'h7 : i2c_device_addr_vpvn = 7'b0111011;
4'h8 : i2c_device_addr_vpvn = 7'b1000011;
4'h9 : i2c_device_addr_vpvn = 7'b1001011;
4'ha : i2c_device_addr_vpvn = 7'b1010011;
4'hb : i2c_device_addr_vpvn = 7'b1011011;
4'hc : i2c_device_addr_vpvn = 7'b1100011;
4'hd : i2c_device_addr_vpvn = 7'b1101011;
4'he : i2c_device_addr_vpvn = 7'b1110011;
4'hf : i2c_device_addr_vpvn = 7'b0111010;
default : begin
i2c_device_addr_vpvn = 7'b0000000;
//$display("Warning: [Unisim %s-25] Invalid I2C address is found. Instance: %m", MODULE_NAME);
end
endcase
end
task infile_format;
begin
$display("\n***** SYSMONE1 Simulation analog Data File Format *****\n");
$display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n");
$display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VCCBRAM VCCPINT VCCPAUX VCCDDRO VP VN VAUXP[0] VAUXN[0] ..... \n");
$display("TIME must be in first column.\n");
$display("Time values need to be integer in ns scale.\n");
$display("Analog values need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n");
$display("Each line including header line can not have extra space after the last character/digit.\n");
$display("Each data line must have the same number of columns as the header line.\n");
$display("Comment line can start with -- or //\n");
$display("Example:\n");
$display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n");
$display("000 125.6 1.0 0.7 0.4 0.3 0.6\n");
$display("200 25.6 0.8 0.5 0.3 0.8 0.2\n");
end
endtask //task infile_format
function [12*8:1] to_upcase_label;
input [12*8:1] in_label;
reg [8:1] tmp_reg;
begin
for (i=0; i< 12; i=i+1) begin
for (j=1; j<=8; j= j+1)
tmp_reg[j] = in_label[i*8+j];
if ((tmp_reg >96) && (tmp_reg<123))
tmp_reg = tmp_reg -32;
for (j=1; j<=8; j= j+1)
to_upcase_label[i*8+j] = tmp_reg[j];
end
end
endfunction
// end read input file
// Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only
always @( posedge busy_r ) begin
if (acq_b_u == 0 && rst_in == 0 && ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31))) begin
chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan]);
chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan]);
if ( chan_val_n_tmp > chan_val_p_tmp)
$display("Warning: [Unisim %s-8] The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, acq_chan, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0);
if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0)
$display("Warning: [Unisim %s-9] The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, acq_chan, chan_val_n_tmp, $time/1000.0);
end
end
reg seq_reset_busy_out = 0;
wire rst_in_out;
always @(posedge DCLK_in or posedge rst_in_out) begin
if (rst_in_out) begin
busy_rst <= 1;
rst_lock <= 1;
rst_lock_early <= 1;
rst_lock_late <= 1;
busy_rst_cnt <= 0;
end
else begin
if (rst_lock == 1) begin
if (busy_rst_cnt < 29) begin
busy_rst_cnt <= busy_rst_cnt + 1;
if ( busy_rst_cnt == 26)
rst_lock_early <= 0;
end
else begin
busy_rst <= 0;
rst_lock = 0;
end
end
if (BUSY_out == 0)
rst_lock_late <= 0;
end
end
initial begin
BUSY_out = 0;
busy_rst = 0;
busy_conv = 0;
busy_seq_rst = 0;
end
always @(busy_rst or busy_conv or rst_lock) begin
if (rst_lock)
BUSY_out = busy_rst;
else
BUSY_out = busy_conv;
end
always @(posedge DCLK_in or posedge rst_in) begin
if (rst_in) begin
busy_conv <= 0;
end
else begin
if (seq_reset_flag == 1 && curr_clkdiv_sel <= 8'h03)
busy_conv <= busy_seq_rst;
else if (busy_sync_fall)
busy_conv <= 0;
else if (busy_sync_rise)
busy_conv <= 1;
end
end
always @(posedge DCLK_in or posedge rst_in) begin
if (rst_in)
cal_chan_update <= 0;
else begin
if (conv_count == CONV_CAL_PER_5 && curr_chan == 6'd8)
cal_chan_update <= 1;
else
cal_chan_update <= 0;
end
end
//always @(posedge adcclk or rst_lock)
always @(posedge DCLK_in or rst_lock) begin
if (rst_lock) begin
busy_sync1 <= 0;
busy_sync2 <= 0;
end
else begin
busy_sync1 <= busy_r;
busy_sync2 <= busy_sync1;
end
end
assign busy_sync_fall = (busy_r == 0 && busy_sync1 == 1) ? 1 : 0;
assign busy_sync_rise = (busy_sync1 == 1 && busy_sync2 == 0 ) ? 1 : 0;
always @(negedge BUSY_out or posedge busy_r)
if (seq_reset_flag == 1 && default_mode && curr_clkdiv_sel <= 8'h03) begin
repeat (5) @(posedge DCLK_in);
busy_seq_rst <= 1;
end
else if (seq_reset_flag == 1 && !default_mode && curr_clkdiv_sel <= 8'h03) begin
repeat (7) @(posedge DCLK_in);
busy_seq_rst <= 1;
end
else
busy_seq_rst <= 0;
//assign muxaddr_o = (rst_lock_early) ? 5'b0 : (curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0 || sysmone12_en == 1) ? acq_chan_m : 5'b0;
always @(posedge adcclk or posedge RESET_in ) begin
if (RESET_in)
MUXADDR_out <= 5'b0;
else begin
if(ext_mux_en &&(curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0 || sysmone12_en == 1))
MUXADDR_out <= acq_chan_m;
else
MUXADDR_out <= 5'b0;
end
end
always @(negedge BUSY_out or posedge BUSY_out or posedge rst_in_out or posedge cal_chan_update )
if (rst_in_out || rst_lock_late)
CHANNEL_out <= 5'd0;
else if (BUSY_out ==1 && (cal_chan_update == 1) )
CHANNEL_out <= 6'd8;
else if (BUSY_out == 0) begin
if ((curr_seq1_0_lat[3:2] != 2'b10 && sysmone12_en == 0) || sysmone12_en == 1)
CHANNEL_out <= curr_chan;
else
CHANNEL_out <= 5'b0;
curr_chan_lat <= curr_chan;
averaging_d <= averaging;
end
// START double latch rst_in
reg rst_in1_tmp6;
reg rst_in2_tmp6;
wire RESET_in_t;
wire rst_in2;
initial begin
int_rst = 1;
repeat (2) @(posedge DCLK_in);
int_rst <= 0;
end
initial begin
rst_in1_tmp6 = 0;
rst_in2_tmp6 = 0;
end
assign #1 RESET_in_t = int_rst_halt_adc | RESET_in | int_rst | soft_reset | gsr_in;
always@(posedge adcclk or posedge RESET_in_t)
if (RESET_in_t) begin
rst_in2_tmp6 <= 1;
rst_in1_tmp6 <= 1;
end
else begin
rst_in2_tmp6 <= rst_in1_tmp6;
rst_in1_tmp6 <= RESET_in_t;
end
assign rst_in2 = rst_in2_tmp6;
assign #10 rst_in_not_seq = rst_in2;
assign rst_in = rst_in_not_seq | seq_reset_dly;
assign rst_in_out = rst_in_not_seq | seq_reset_busy_out;
always @(posedge seq_reset) begin
repeat (2) @(posedge DCLK_in);
seq_reset_dly = 1;
repeat (2) @(negedge DCLK_in);
seq_reset_busy_out = 1;
repeat (3) @(posedge DCLK_in);
seq_reset_dly = 0;
seq_reset_busy_out = 0;
end
always @(posedge seq_reset_dly or posedge busy_r)
if (seq_reset_dly)
seq_reset_flag <= 1;
else
seq_reset_flag <= 0;
always @(posedge seq_reset_flag or posedge BUSY_out)
if (seq_reset_flag)
seq_reset_flag_dly <= 1;
else //if(!CHANNEL_out==6'd8)
seq_reset_flag_dly <= 0;
always @(posedge BUSY_out )
if (seq_reset_flag_dly == 1 && acq_chan == 6'd8 && default_mode )
first_cal_chan <= 1;
else
first_cal_chan <= 0;
initial begin
sysclk = 0;
adcclk_tmp = 0;
seq_count = 1;
seq_count_a = 1;
eos_en = 0;
eos_tmp_en = 0;
clk_count = -1;
acq_acqsel = 0;
acq_e_c_tmp6 = 0;
acq_e_c_tmp5 = 0;
eoc_en = 0;
eoc_en_delay = 0;
rst_lock = 0;
rst_lock_early = 0;
alm_update = 0;
drp_update = 0;
cal_chan_update = 0;
adc_state = S3_ST;
scon_tmp = 0;
busy_r = 0;
busy_r_rst = 0;
busy_sync1 = 0;
busy_sync2 = 0;
conv_count = 0;
conv_end = 0;
seq_status_avg = 0;
for (i = 0; i <=63; i = i +1) begin
conv_avg_count[i] = 0;
conv_acc[i] = 0;
end
single_pass_finished = 0;
for (k = 0; k <= 31; k = k + 1) begin
data_reg[k] = 16'b0;
end
seq_count_en = 0;
EOS_out_tmp = 0;
EOC_out_tmp = 0;
EOS_out_tmp1 = 0;
EOC_out_tmp1 = 0;
EOS_out = 0;
EOC_out = 0;
EOC_out_pre = 0;
EOC_out_pre2 = 0;
averaging = 0;
averaging_d = 0;
curr_e_c = 0;
curr_b_u = 0;
curr_acq = 0;
curr_seq1_0 = 0;
curr_seq1_0_lat = 0;
DADDR_in_lat = 0;
//min and max registers' reset value assignments
data_reg[32] = 16'h0000;
data_reg[33] = 16'h0000;
data_reg[34] = 16'h0000;
data_reg[35] = 16'h0000;
data_reg[36] = 16'hFFFF;
data_reg[37] = 16'hFFFF;
data_reg[38] = 16'hFFFF;
data_reg[39] = 16'hFFFF;
data_reg[40] = 16'h0000;
data_reg[41] = 16'h0000;
data_reg[42] = 16'h0000;
data_reg[43] = 16'h0000; //reserved
data_reg[44] = 16'hFFFF;
data_reg[45] = 16'hFFFF;
data_reg[46] = 16'hFFFF;
data_reg[47] = 16'h0000; //reserved
ot_out_reg = 0;
OT_out = 0;
alm_out_reg = 0;
ALM_out = 0;
curr_chan = 'd0;
acq_chan = 'd0;
acq_chan_m = 'd0;
curr_chan_lat = 'd0;
BUSY_out = 0;
curr_seq = 0;
curr_seq_m = 0;
hr_tot_chan = 0;
seq_reset_flag_dly = 0;
seq_reset_flag = 0;
seq_reset_dly = 0;
ot_en = 1;
alm_en = 13'h1FFF;
DO_out_rdtmp = 0;
acq_b_u = 0;
conv_result_int = 0;
conv_result = 0;
conv_result_reg = 0;
reserved_addr_pre = 0;
end
// state machine
always @(posedge adcclk or posedge rst_in or sim_file_flag) begin
//CR 675227
if (!(halt_adc == 2 && single_chan_mode )) begin
if (sim_file_flag == 1'b1)
adc_state <= S0_ST;
else if (rst_in == 1'b1 || rst_lock_early == 1)
adc_state <= S0_ST;
else if (rst_in == 1'b0)
adc_state <= adc_next_state;
end
end
always @(adc_state or eos_en or conv_start or conv_end or curr_seq1_0_lat) begin
case (adc_state)
S0_ST : adc_next_state = S2_ST;
S2_ST : if (conv_start)
adc_next_state = S3_ST;
else
adc_next_state = S2_ST;
S3_ST : if (conv_end)
adc_next_state = S5_ST;
else
adc_next_state = S3_ST;
S5_ST : if (curr_seq1_0_lat == SEQ_SINGLE_PASS ) begin
//CR 675227 if (eos_en)
if (eos_tmp_en)
adc_next_state = S1_ST;
else
adc_next_state = S2_ST;
end
else
adc_next_state = S2_ST;
S1_ST : adc_next_state = S0_ST;
default :
adc_next_state = S0_ST;
endcase // case(adc_state)
end
// end state machine
// DRPORT - SRAM
initial begin
DRDY_out = 0;
DRDY_out_tmp1 = 0;
DRDY_out_tmp2 = 0;
DRDY_out_tmp3 = 0;
en_data_flag = 0;
DO_out = 16'b0;
seq_reset = 0;
cfg_reg1_init = INIT_41_BIN;
seq_en = 0;
seq_en_dly = 0;
seq_en <= #20 (cfg_reg1_init[15:12] != 4'b0011 ) ? 1 : 0;
seq_en <= #150 0;
end
always @(posedge DRDY_out_tmp3 or posedge gsr_in) begin
if (gsr_in == 1)
DRDY_out <= 0;
else begin
@(posedge DCLK_in)
DRDY_out <= 1;
@(posedge DCLK_in)
DRDY_out <= 0;
end
end
function is_reserved_address;
input [7:0] address_in;
reg is_reserved_address_pre;
begin
is_reserved_address_pre = ((address_in >= 8'h07 && address_in <= 8'h0F) ||
(address_in >= 8'h28 && address_in <= 8'h37) ||
(address_in >= 8'h39 && address_in <= 8'h3D) ||
(address_in >= 8'h44 && address_in <= 8'h45) ||
(address_in >= 8'h58 && address_in <= 8'h5F) ||
(address_in >= 8'h64 && address_in <= 8'h67) ||
(address_in >= 8'h6C && address_in <= 8'h7F) ||
(address_in >= 8'h84 && address_in <= 8'h9F) ||
(address_in >= 8'hA4 && address_in <= 8'hA7) ||
(address_in >= 8'hAC && address_in <= 8'hFF)
);
if(is_reserved_address_pre)
$display("Warning: [Unisim %s-11] The input address=h%x at time %.3f ns is accessing a RESERVED location. The data in this location is invalid. Instance: %m", MODULE_NAME, address_in, $time/1000.0);
is_reserved_address = is_reserved_address_pre;
end
endfunction
function is_readonly_address;
input [7:0] address_in;
reg is_readonly_address_pre;
begin
is_readonly_address_pre = ((address_in <= 8'h3F) ||
(address_in >= 8'h80 && address_in <= 8'hAB)
);
if(is_readonly_address_pre)
$display("Warning: [Unisim %s-19] The input address=h%x at time %.3f ns is accessing a READ ONLY location. The data won't be written. Instance: %m", MODULE_NAME, address_in, $time/1000.0);
is_readonly_address = is_readonly_address_pre;
end
endfunction
always @(posedge DCLK_in or posedge gsr_in) begin
if (gsr_in == 1) begin
DADDR_in_lat <= 8'b0;
DO_out <= 16'b0;
end
else begin
if (DEN_in == 1'b1) begin
if (DRDY_out_tmp1 == 1'b0) begin
DRDY_out_tmp1 <= 1'b1;
en_data_flag = 1;
DADDR_in_lat <= DADDR_in;
end
else if (DADDR_in != DADDR_in_lat)
$display("Warning: [Unisim %s-10] Input pin DEN at time %.3f ns can not be continuously set to high. Please wait for DRDY to be high and then set DEN to high again. Instance: %m", MODULE_NAME, $time/1000.0);
end // if (DEN_in == 1'b1)
else
DRDY_out_tmp1 <= 1'b0;
DRDY_out_tmp2 <= DRDY_out_tmp1;
DRDY_out_tmp3 <= DRDY_out_tmp2;
if (DRDY_out_tmp1 == 1)
en_data_flag = 0;
if (DRDY_out_tmp3 == 1) begin
DO_out <= DO_out_rdtmp;
end
if (DEN_in == 1 && is_reserved_address(DADDR_in) )
reserved_addr_pre <= 1;
else if (DWE_in == 1'b1 && DEN_in == 1'b1 && en_data_flag == 1) begin
//write to all available and writable addresses.
dr_sram[DADDR_in] <= DI_in;
//check write access
if (is_readonly_address(DADDR_in))
read_only_pre <= 1;
else begin
read_only_pre <= 0;
// post processing after DRP write
if (DADDR_in == 8'h03)
soft_reset <= 1;
else if ( DADDR_in == 8'h53 && DI_in[3:0] == 4'b0011)
ot_limit_reg[15:4] <= DI_in[15:4];
else if (DADDR_in == 8'h41 ) begin // && en_data_flag == 1) begin is above
//if (DEN_in == 1'b1 && DWE_in == 1'b1) begin
if (DI_in[15:12] != cfg_reg1[15:12]) // writing with the same seq[3:0] will not restart the sequence, matching with hw
seq_reset <= 1'b1;
else
seq_reset <= 1'b0;
if (DI_in[15:12] != SEQ_SINGLE_CHAN)
seq_en <= 1'b1;
else
seq_en <= 1'b0;
end //DADDR_in == 8'h41
end // not read only
end // dwe ==1
if (seq_en == 1)
seq_en <= 1'b0;
if (seq_reset == 1)
seq_reset <= 1'b0;
if (soft_reset == 1)
soft_reset <= 0;
end // if (gsr == 1)
end //always
reg display_configuration_warnings;
reg [7:0] cfg_check_addr;
always @(posedge DCLK_in or posedge rst_in) begin
if(rst_in) begin
display_configuration_warnings <= 0;
cfg_check_addr <= 0;
end
else begin
if(DEN_in && DWE_in) begin
display_configuration_warnings <= 1;
cfg_check_addr <= DADDR_in;
end
else begin
display_configuration_warnings <= 0;
cfg_check_addr <= 0;
end
end
end
always @(posedge display_configuration_warnings) begin
if(cfg_check_addr == 8'h40)
if (cfg_reg0[5:0] == 6'd7 || (cfg_reg0[5:0] >= 6'd9 && cfg_reg0[5:0] <= 6'd12) || cfg_reg0[5:0] >= 6'd36)
$display("Warning: [Unisim %s-14] Config register 0 bits [5:0] at 40h cannot not be set to an invalid analog channel value as %0b. Instance: %m", MODULE_NAME, cfg_reg0[5:0], $time/1000.0,);
if(cfg_check_addr == 8'h40 || cfg_check_addr==8'h41)
if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (cfg_reg0[8]==1) && (cfg_reg0[5:0] != 6'd3) && (cfg_reg0[5:0] < 6'd16))
$display("Warning: [Unisim %s-15] In single channel mode if the selected channel is not analog, config register 0 bit[8] must be set to 0. Long acqusition mode is only allowed for external channels, not in single channel mode. Instance: %m", MODULE_NAME, DI_in, DADDR_in, $time/1000.0);
if(cfg_check_addr == 8'h40 || cfg_check_addr==8'h41|| cfg_check_addr==8'h46|| cfg_check_addr==8'h48|| cfg_check_addr==8'h49)
if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (cfg_reg0[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000) && (seq_chan_reg3 != 16'h0000))
$display("Warning: [Unisim %s-16] In single channel mode, ADC channel selection registers 46h, 48h and 49h must be set to 0, these are set to %x, %x and %x respectively. Averaging must be enabled. Instance: %m", MODULE_NAME, seq_chan_reg3, seq_chan_reg1, seq_chan_reg2, $time/1000.0);
if(cfg_check_addr == 8'h4E || cfg_check_addr==8'h41)
if ((cfg_reg1[15:12]!=SEQ_SINGLE_CHAN) && ((dr_sram['h4E][10:0]!=11'd0) || (dr_sram['h4E][15:12]!=4'd0)))
$display("Warning: [Unisim %s-18] The Control Register 4Eh value set is to %x. Bits [15:12] and [10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, dr_sram['h4E], $time/1000.0);
if(cfg_check_addr == 8'h42)
if (cfg_reg2[4]==1)
$display("Warning: [Unisim %s-12] The config reg 2 =%x is invalid. Bit [4] must be set to 0. Instance: %m", MODULE_NAME, cfg_reg2, $time/1000.0);
if(cfg_check_addr == 8'h43)
if (cfg_reg3[3:0]!=4'd0)
$display("Warning: [Unisim %s-17] The config reg 3 =%x is invalid. Bits [3:0] must be set to 000. Instance: %m", MODULE_NAME, cfg_reg3, $time/1000.0);
// CR1004434
if (cfg_check_addr == 8'h40 || cfg_check_addr ==8'h41)
if (((cfg_reg1[15:12]==4'b0001|| cfg_reg1[15:12]==4'b0010) && dr_sram['h46][3:0]!=4'b0000) || //single pass or cont mode and vuser selected
(cfg_reg1[15:12]==4'b0011 && cfg_reg0[5:2]==4'b1000) ) //single channel mode and vuser is selected
$display("Warning: [Unisim %s-178] The control registers 40h and 41h are set to %x and %x respectively. VUSER is selected. In Kintex devices, SYSMONE1 model has no way of knowing whether VUSER has a 6V range or a 3V range and assumes all channels have 3V range. If 6V banks are selected, the value stored in the model's registers will be different than that of the actual hardware. Instance: %m",
MODULE_NAME, cfg_reg0, cfg_reg1 );
end
// DO bus data out
assign flag_reg0 = {8'b0, ALM_out[6:3], OT_out, ALM_out[2:0]};
assign flag_reg1 = {10'b0, ALM_out[13:8]};
always @(*) begin
reserved_addr_pre = is_reserved_address(DADDR_in_lat);
if(reserved_addr_pre)
DO_out_rdtmp = 16'b0;
else begin //readable addresses
if ( DADDR_in_lat <= 8'h3D)
DO_out_rdtmp = data_reg[DADDR_in_lat];
else if (DADDR_in_lat == 8'h3E)
DO_out_rdtmp = flag_reg1;
else if (DADDR_in_lat == 8'h3F)
DO_out_rdtmp = flag_reg0;
else
DO_out_rdtmp = dr_sram[DADDR_in_lat];
end
end
// end DRP RAM
assign cfg_reg0 = dr_sram[8'h40];
assign cfg_reg1 = dr_sram[8'h41];
assign cfg_reg2 = dr_sram[8'h42];
assign cfg_reg3 = dr_sram[8'h43];
assign seq_chan_reg1 = dr_sram[8'h48];
assign seq_chan_reg2 = dr_sram[8'h49];
assign seq_chan_reg3 = dr_sram[8'h46];
assign seq_avg_reg1 = dr_sram[8'h4A];
assign seq_avg_reg2 = dr_sram[8'h4B];
assign seq_avg_reg3 = dr_sram[8'h47];
assign seq_bu_reg1 = dr_sram[8'h4C];
assign seq_bu_reg2 = dr_sram[8'h4D];
assign seq_bu_reg3 = dr_sram[8'h78];
assign seq_acq_reg1 = dr_sram[8'h4E];
assign seq_acq_reg2 = dr_sram[8'h4F];
assign seq_acq_reg3 = dr_sram[8'h79];
assign seq1_0 = cfg_reg1[15:12];
assign default_mode = (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11);
assign single_pass_mode = (seq1_0 == 4'b0001);
assign cont_seq_mode = (seq1_0 == 4'b0010);
assign single_chan_mode = (seq1_0 == 4'b0011);
assign ext_mux_chan = cfg_reg0[5:0];
assign ext_mux_en = cfg_reg0[11]; // && (~default_mode) ??
always @(posedge drp_update or posedge rst_in) begin
if (rst_in) begin
repeat (2) @(posedge DCLK_in);
seq_bits = seq1_0;
end
else begin
seq_bits = curr_seq1_0;
if (seq_bits == SEQ_DEFAULT_MODE) begin
alm_en <= 'd0;
ot_en <= 1;
end
else begin
ot_en <= ~cfg_reg1[0];
alm_en[2:0] <= ~cfg_reg1[3:1];
alm_en[6:3] <= ~cfg_reg1[11:8];
alm_en[11:8] <= ~cfg_reg3[3:0]; //TODO check this with UG
end
end
end
//--------------------- end DRPORT - sram
//---- I2C logic start ----------------------------------------------------
parameter ST_I2C_IDLE = 2'd0,
ST_I2C_GET_ADDR = 2'd1,
ST_I2C_GET_CMD = 2'd2,
ST_I2C_READ = 2'd3;
localparam I2C_DRP_RD = 4'b0001; // read
localparam I2C_DRP_WR = 4'b0010; // write
localparam I2C_DRP_NO = 4'b0000; // no operation
reg [1:0] i2c_state;
reg i2c_start;
reg i2c_start_reset;
reg i2c_stop;
reg i2c_stop_reset;
reg [3:0] i2c_bit_counter;
reg [2:0] i2c_byte_counter;
wire i2c_lsb_bit;
wire i2c_ack_bit;
wire [15:0] i2c_drp_data;
wire [9:0] i2c_drp_addr;
wire [3:0] i2c_drp_cmd ;
reg [31:0] i2c_cmd_in;
reg [7:0] i2c_data_in;
wire i2c_addr_match;
wire i2c_addr_match_wop;
wire i2c_rw_bit;
wire i2c_rd_cmd_pre;
reg i2c_rd_cmd;
reg i2c_ack_in; //ack from master to slave, negated.
wire i2c_cmd_end;
wire i2c_rd_end;
reg i2c_cmd_received;
reg [15:0] i2c_data_out;
wire i2c_wr_exec;
assign i2c_addr_match = (i2c_data_in[7:1]==i2c_device_addr[6:0]) ? 1 : 0;
assign i2c_addr_match_wop = i2c_addr_match;
always @(posedge RESET_in or posedge i2c_start_reset or negedge I2C_SDA_in) begin
if(RESET_in || i2c_start_reset)
i2c_start <= 1'b0;
else
i2c_start <= I2C_SCLK_in;
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if(RESET_in)
i2c_start_reset <= 1'b0;
else
i2c_start_reset <= i2c_start;
end
always @(posedge RESET_in or posedge i2c_stop_reset or posedge I2C_SDA_in) begin
if(RESET_in || i2c_stop_reset)
i2c_stop <= 1'b0;
else
i2c_stop <= I2C_SCLK_in;
end
always @(posedge RESET_in or posedge i2c_stop) begin
if(RESET_in)
i2c_stop_reset = 1'b0;
else begin
repeat (16) @(posedge DCLK_in);
i2c_stop_reset = 1;
repeat (16) @(posedge DCLK_in);
i2c_stop_reset = 0;
end
end
assign i2c_lsb_bit = (i2c_bit_counter== 4'd7) && ~i2c_start;
assign i2c_ack_bit = (i2c_bit_counter== 4'd8) && ~i2c_start;
always @(posedge RESET_in or negedge I2C_SCLK_in or posedge i2c_start) begin
if(RESET_in || i2c_start)
i2c_bit_counter <= 'd0;
else begin
if (i2c_ack_bit)
i2c_bit_counter <= 'd0;
else
i2c_bit_counter <= i2c_bit_counter + 'd1;
end
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if(RESET_in)
i2c_data_in <= 'd0;
else if(!i2c_ack_bit)
i2c_data_in <= {i2c_data_in[6:0],I2C_SDA_in} ;
end
assign i2c_drp_data = i2c_cmd_in[15:0];
assign i2c_drp_addr = i2c_cmd_in[25:16];
assign i2c_drp_cmd = i2c_cmd_in[29:26];
always @(posedge I2C_SCLK_in) begin
//if(RESET_in)
// i2c_cmd_in <= 'd0;
//else if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD )
if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD )
i2c_cmd_in <= {i2c_data_in,i2c_cmd_in[31:8]} ;
end
assign i2c_rd_cmd_pre = i2c_rw_bit && I2C_SDA_in;
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)
i2c_rd_cmd <= 1'b0;
else begin
if (i2c_state==ST_I2C_IDLE)
i2c_rd_cmd <= 1'b0;
else if (i2c_rw_bit )
i2c_rd_cmd <= i2c_data_in[0] ;
end
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if(RESET_in)
i2c_ack_in <= 'd0;
else if(i2c_ack_bit)
i2c_ack_in <= ~I2C_SDA_in; //ACK from master to slave, negated.
else if ((i2c_state==ST_I2C_IDLE) || i2c_bit_counter=='d1)
i2c_ack_in <= 0;
end
assign i2c_cmd_end = i2c_ack_bit && (i2c_byte_counter==3'd3);
assign i2c_rd_end = i2c_ack_bit && (i2c_byte_counter==3'd1);
always @(posedge RESET_in or posedge i2c_stop or posedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)
i2c_cmd_received <= 0;
else if (i2c_cmd_end)
i2c_cmd_received <= 1;
else if (i2c_state==ST_I2C_READ)
i2c_cmd_received <= 0;
end
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_start || i2c_stop)
i2c_byte_counter <= 0;
else if(i2c_ack_bit && (i2c_state == ST_I2C_GET_CMD || i2c_state == ST_I2C_READ ))
i2c_byte_counter <= i2c_byte_counter + 1;
end
//I2C state machine.
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)// && ~i2c_en)
i2c_state <= ST_I2C_IDLE;
else if(i2c_start)
i2c_state <= ST_I2C_GET_ADDR;
else if (i2c_ack_bit)
case (i2c_state)
ST_I2C_GET_ADDR : begin
if(!i2c_addr_match) begin
i2c_state <= ST_I2C_IDLE;
$display("Warning: [Unisim %s-54] I2C command address h%0X not matching the device address h%0X @time %0t",
MODULE_NAME, i2c_data_in[7:1], i2c_device_addr, $time);
end
else if (~i2c_cmd_received)
i2c_state <= ST_I2C_GET_CMD;
else if(i2c_drp_cmd==I2C_DRP_RD) //if you received a command earlier, it had to be a drp read command.
i2c_state <= ST_I2C_READ;
else
i2c_state <= ST_I2C_IDLE;
end
ST_I2C_GET_CMD : begin
if (i2c_cmd_end) begin
i2c_state <= ST_I2C_IDLE;
$display("Info: [Unisim %s] I2C command received @time %0t", MODULE_NAME, $time);
end
end
ST_I2C_READ : begin
if(i2c_rd_end)
i2c_state <= ST_I2C_IDLE;
end
default : i2c_state <= ST_I2C_IDLE;
endcase
end
//i2c write command execute
assign i2c_wr_exec = (i2c_cmd_received && i2c_drp_cmd==I2C_DRP_WR);
always @(negedge I2C_SCLK_in) begin
if(!RESET_in) begin
if(i2c_cmd_received && i2c_drp_cmd==I2C_DRP_WR)
if(i2c_drp_addr>='h40)
dr_sram[i2c_drp_addr] <= i2c_drp_data;
//else
// data_reg[i2c_drp_addr] <= i2c_drp_data;
end
end
//i2c read command execute
always @(negedge I2C_SCLK_in) begin
if(!RESET_in) begin
if(i2c_cmd_received && i2c_drp_cmd==I2C_DRP_RD && i2c_state==ST_I2C_GET_ADDR && !i2c_ack_bit) begin //fetch the data
if(i2c_drp_addr>='h40)
i2c_data_out <= dr_sram[i2c_drp_addr];
else
i2c_data_out <= data_reg[i2c_drp_addr];
end
else if(i2c_lsb_bit && i2c_state==ST_I2C_READ)
i2c_data_out <= {8'b0,i2c_data_out[15:8]};// shift the higher byte to lower.
else //shift the data 1 bit at a time for only the lower byte. bit 7 is pushed out.
i2c_data_out <= {i2c_data_out[15:8],i2c_data_out[6:0],1'b0};
end
end
//Pull down SDA to transfer a zero to the master.
always@(posedge RESET_in or negedge I2C_SCLK_in) begin
if (RESET_in)
I2C_SDA_TS_out <= 1;
else begin
if (i2c_start)
I2C_SDA_TS_out <= 1;
else if (i2c_lsb_bit) //acknowledge the end of a 1 byte transfer from master
I2C_SDA_TS_out <= ! (((i2c_state==ST_I2C_GET_ADDR) && i2c_addr_match) ||
((i2c_state==ST_I2C_GET_CMD ) && !(i2c_rd_cmd && i2c_byte_counter=='d3)) //send NACK at the last byte of command, only if read command
);
else if ((i2c_ack_bit && //first bit of next slave to master transfer
((i2c_state==ST_I2C_GET_ADDR) && (i2c_drp_cmd==I2C_DRP_RD) )) ||
(i2c_state==ST_I2C_READ && !i2c_rd_end)) //or read continued
I2C_SDA_TS_out <= i2c_data_out[7];
else
I2C_SDA_TS_out <= 1;
end
end
// clock stretching
assign I2C_SCLK_TS_out = 1'b1;
//---- End of I2C logic ------------------------------------------------
// Clock divider, generate and adcclk
always @(posedge DCLK_in)
sysclk <= ~sysclk;
always @(posedge DCLK_in ) begin
if (curr_clkdiv_sel > 'd2 || clk_count_rst) begin
if ((clk_count >= curr_clkdiv_sel-1) || clk_count_rst)
clk_count <= 0;
else
clk_count <= clk_count + 1;
if(clk_count_rst)
adcclk_tmp <= 1;
//else if(clk_count <= curr_clkdiv_sel/2 -2)
else if(clk_count <= curr_clkdiv_sel/2 -1) //CR-1003761
adcclk_tmp <= 1;
else
adcclk_tmp <= 0;
end
else
adcclk_tmp <= ~adcclk_tmp;
end
wire adcclk_r;
assign curr_clkdiv_sel = cfg_reg2[15:8];
assign sysmone1_en = (cfg_reg2[5]===1 && cfg_reg2[4]===1) ? 0 : 1;
assign sysmone12_en = (cfg_reg2[5]===1 ) ? 0 : 1;
assign adcclk_div1 = (curr_clkdiv_sel > 'd2) ? 0 : 1;
assign adcclk_r = (adcclk_div1) ? ~sysclk : adcclk_tmp;
assign adcclk = (sysmone1_en) ? adcclk_r : 0;
// end clock divider
// latch configuration registers
wire [15:0] cfg_reg0_seq, cfg_reg0_adc;
reg [15:0] cfg_reg0_seq_tmp5, cfg_reg0_adc_tmp5;
reg [15:0] cfg_reg0_seq_tmp6, cfg_reg0_adc_tmp6;
reg [1:0] acq_avg;
//always @( seq1_0 or single_pass_finished or curr_seq_m or cfg_reg0_adc or rst_in) begin
always @(*) begin
if (rst_in == 0) begin
if ( default_mode) //default mode
acq_chan_m = curr_seq_m[4:0];
else if (cont_seq_mode || (single_pass_mode && !single_pass_finished)) //continuous mode or single pass active state
acq_chan_m = curr_seq_m[4:0];
else //single pass mode deactive state or single channel mode
acq_chan_m = cfg_reg0_adc[4:0];
end
end
//CR 675227 always @( seq1_0 or single_pass_finished or curr_seq or cfg_reg0_adc or rst_in) begin
always @(*) begin
if ((single_pass_mode && !single_pass_finished) ||
cont_seq_mode) //|| default_mode ) CR 927318: default mode doesn't support acq adjustability
acq_acqsel = curr_seq[8];
else if (single_chan_mode)
acq_acqsel = cfg_reg0_adc[8];
else
acq_acqsel = 0;
end
always @(single_pass_finished or curr_seq or cfg_reg0_adc or rst_in) begin
if (rst_in == 0) begin
if (default_mode) begin // default mode
acq_avg = 2'b01;
acq_chan = curr_seq[5:0];
acq_b_u = 0;
end
//else if (!single_chan_mode && single_pass_finished == 0) begin // either continuous or single pass mode
else if (cont_seq_mode || (single_pass_mode && !single_pass_finished)) begin // either continuous or active single pass mode
acq_avg = curr_seq[13:12];
acq_chan = curr_seq[5:0];
acq_b_u = curr_seq[10];
end
else begin
acq_avg = cfg_reg0_adc[13:12];
acq_chan = cfg_reg0_adc[5:0];
acq_b_u = cfg_reg0_adc[10];
//CR 675227
// CR 764936 if (seq1_0 == 4'b0001) begin
//when doing one pass when a CONVST BUSY should assert and then an EOC be seen,
//the user can assert a CONVST again without having to write to the sequence register to start the sequence again.
if (single_pass_mode && !acq_e_c) begin // if single pass and not event driven
halt_adc = halt_adc + 1;
if (halt_adc == 2) //need to wait for EOS.
dr_sram[8'h41][15:12] = SEQ_SINGLE_CHAN ;//4'b0011; //from single pass, go to single channel
end
end
end
end
reg single_chan_conv_end;
reg [3:0] conv_end_reg_read;
reg busy_reg_read;
reg first_after_reset_tmp5;
reg first_after_reset_tmp6;
always@(posedge adcclk or posedge rst_in) begin
if(rst_in)
conv_end_reg_read <= 4'b0;
else
conv_end_reg_read <= {conv_end_reg_read[2:0], (single_chan_conv_end | conv_end)};
end
always@(posedge DCLK_in or posedge rst_in) begin
if(rst_in)
busy_reg_read <= 1;
else
busy_reg_read <= ~conv_end_reg_read[2];
end
// i2c write
assign cfg_reg0_adc = (i2c_stop) ? cfg_reg0 : cfg_reg0_adc_tmp6;
// assign cfg_reg0_adc = cfg_reg0_adc_tmp6;
assign cfg_reg0_seq = cfg_reg0_seq_tmp6;
assign acq_e_c = acq_e_c_tmp6;
always @(negedge BUSY_out or rst_in)
if(rst_in) begin
cfg_reg0_seq_tmp6 <= 16'b0;
cfg_reg0_adc_tmp6 <= 16'b0;
acq_e_c_tmp6 <= 0;
first_after_reset_tmp6 <= 1;
end
else begin
repeat(3) @(posedge DCLK);
if(first_after_reset_tmp6) begin
first_after_reset_tmp6<=0;
cfg_reg0_adc_tmp6 <= cfg_reg0;
cfg_reg0_seq_tmp6 <= cfg_reg0;
end
else begin
cfg_reg0_adc_tmp6 <= cfg_reg0_seq;
cfg_reg0_seq_tmp6 <= cfg_reg0;
end
acq_e_c_tmp6 <= cfg_reg0[9];
end
always @(posedge conv_start or posedge busy_r_rst or posedge rst_in)
if (rst_in ==1)
busy_r <= 0;
else if (conv_start && rst_lock == 0)
busy_r <= 1;
else if (busy_r_rst)
busy_r <= 0;
always @(negedge BUSY_out )
if (single_pass_finished == 1) //from single pass, go to single channel
if (curr_seq1_0 == SEQ_SINGLE_PASS || curr_seq1_0 == SEQ_SINGLE_CHAN) // CR 764936
//when doing one pass when a CONVST BUSY should assert and then an EOC be seen,
//the user can assert a CONVST again without having to write to the sequence register to start the sequence again.
curr_seq1_0 <= SEQ_SINGLE_CHAN; //4'b0011;
else
curr_seq1_0 <= SEQ_DEFAULT_MODE; //4'b0000;
else
curr_seq1_0 <= seq1_0;
always @(posedge conv_start or rst_in )
if (rst_in == 1) begin
mn_mux_in <= 0.0;
curr_chan <= 6'b0;
end
else begin
curr_chan <= acq_chan;
curr_seq1_0_lat <= curr_seq1_0;
if ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31)) begin
if (ext_mux_en) begin
tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan]);
mn_mux_in <= tmp_v;
end
else begin
tmp_v = $bitstoreal(mn_in_diff[acq_chan]);
mn_mux_in <= tmp_v;
end
end
else
mn_mux_in <= $bitstoreal(mn_in_uni[acq_chan]);
if ( acq_chan == 7 || (acq_chan >= 9 && acq_chan <= 12) || acq_chan >= 36)
$display("Warning: [Unisim %s-14] The analog channel %x at time %.3f ns is invalid. Check register 40h[5:0]. Instance: %m", MODULE_NAME, acq_chan, $time/1000.0);
if ((single_pass_mode && !single_pass_finished) || cont_seq_mode || default_mode ) begin
averaging <= curr_seq[13:12];
curr_b_u <= curr_seq[10];
curr_e_c <= curr_seq[9];
curr_acq <= curr_seq[8];
end
else begin
averaging <= acq_avg;
curr_b_u <= acq_b_u;
curr_e_c <= cfg_reg0[9];
curr_acq <= cfg_reg0[8];
end
end // if (rst_in == 0)
// end of latch configuration registers
//-----------------------------------------------------------------
// sequence control
always @(seq_en)
seq_en_dly <= #1 seq_en;
always @(posedge seq_en_dly) begin
if (single_pass_mode || cont_seq_mode) begin //single pass or continuous sequence mode
// high rate sequence
hr_tot_chan = 0;
for (si=0; si<= 15; si=si+1) begin
if (seq_chan_reg1[si] ==1) begin
hr_tot_chan = hr_tot_chan + 1;
seq_mem[hr_tot_chan] = si; //seq_mem possible max is 33 - 1 = 32 max channels. Max allowed channels are 31.
end
end
for (si=16; si<= 31; si=si+1) begin
if (seq_chan_reg2[si-16] ==1) begin
hr_tot_chan = hr_tot_chan + 1;
seq_mem[hr_tot_chan] = si;
end
end
for (si=32; si<= 35; si=si+1) begin
if (seq_chan_reg3[si-32] ==1) begin
hr_tot_chan = hr_tot_chan + 1;
seq_mem[hr_tot_chan] = si;
end
end
end
else if (default_mode ) begin //default mode
if(cfg_reg0[11])
$display("Error: [Unisim %s-50] External mux selection will be disregarded as SYSMON is in default mode. Instance: %m", MODULE_NAME);
hr_tot_chan = 5;
seq_mem[1] = 0;
seq_mem[2] = 8;
seq_mem[3] = 9;
seq_mem[4] = 10;
seq_mem[5] = 14;
end
end //always
always @( seq_count or negedge seq_en_dly) begin
seq_curr_i = seq_mem[seq_count];
curr_seq = 16'b0;
if (seq_curr_i >= 0 && seq_curr_i <= 15) begin
curr_seq [2:0] = seq_curr_i[2:0];
curr_seq [4:3] = 2'b01;
curr_seq [8] = seq_acq_reg1[seq_curr_i];
curr_seq [10] = seq_bu_reg1[seq_curr_i];
if (default_mode)
curr_seq [13:12] = 2'b01;
else if (seq_avg_reg1[seq_curr_i])
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
if (seq_curr_i >= 0 && seq_curr_i <=7)
curr_seq [4:3] = 2'b01;
else
curr_seq [4:3] = 2'b00;
end
else if (seq_curr_i >= 16 && seq_curr_i <= 31) begin
curr_seq [4:0] = seq_curr_i;
curr_seq [8] = seq_acq_reg2[seq_curr_i - 16];
curr_seq [10] = seq_bu_reg2[seq_curr_i - 16];
if (seq_avg_reg2[seq_curr_i - 16] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
end // if (seq_curr_i >= 16 && seq_curr_i <= 31)
else if (seq_curr_i > 31 && seq_curr_i <= 35) begin
curr_seq [5:0] = seq_curr_i;
curr_seq [8] = seq_acq_reg3[seq_curr_i - 32];
curr_seq [10] = seq_bu_reg3[seq_curr_i - 32];
if (seq_avg_reg3[seq_curr_i - 32] == 1)
curr_seq [13:12] = cfg_reg0[13:12];
else
curr_seq [13:12] = 2'b00;
end
end
always @( seq_count_a or negedge seq_en_dly) begin
seq_curr_ia = seq_mem[seq_count_a];
curr_seq_m = 16'b0;
if (seq_curr_ia >= 0 && seq_curr_ia <= 15) begin
curr_seq_m [2:0] = seq_curr_ia[2:0];
curr_seq_m [4:3] = 2'b01;
curr_seq_m [8] = seq_acq_reg1[seq_curr_ia];
curr_seq_m [10] = seq_bu_reg1[seq_curr_ia];
if (seq1_0 == 4'b0000 || seq1_0[3:2] == 2'b11)
curr_seq_m [13:12] = 2'b01;
else if (seq_avg_reg1[seq_curr_ia] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
if (seq_curr_ia >= 0 && seq_curr_ia <=7)
curr_seq_m [4:3] = 2'b01;
else
curr_seq_m [4:3] = 2'b00;
end
else if (seq_curr_ia >= 16 && seq_curr_ia <= 31) begin
curr_seq_m [4:0] = seq_curr_ia;
curr_seq_m [8] = seq_acq_reg2[seq_curr_ia - 16];
curr_seq_m [10] = seq_bu_reg2[seq_curr_ia - 16];
if (seq_avg_reg2[seq_curr_ia - 16] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
end
else if (seq_curr_ia > 31 && seq_curr_ia <= 35) begin
curr_seq_m [5:0] = seq_curr_ia;
curr_seq_m [8] = seq_acq_reg3[seq_curr_ia - 32];
curr_seq_m [10] = seq_bu_reg3[seq_curr_ia - 32];
if (seq_avg_reg3[seq_curr_ia - 32] == 1)
curr_seq_m [13:12] = cfg_reg0[13:12];
else
curr_seq_m [13:12] = 2'b00;
end
end // always @ ( seq_count_a or negedge seq_en_dly)
always @(posedge BUSY_out or posedge rst_in ) begin
if (rst_in == 1 || rst_lock == 1 )
seq_count_a <= 1;
else begin
if ( curr_seq1_0_lat == SEQ_SINGLE_CHAN )
seq_count_a <= 1;
else begin
if (seq_count_a >= 37 || seq_count_a >= hr_tot_chan)
seq_count_a <= 1;
else
seq_count_a <= seq_count_a +1;
end
end
end //always
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1 ) begin
seq_count <= 1;
eos_en <= 0;
end
else begin
if ((seq_count == hr_tot_chan) &&
(adc_state == S3_ST && adc_next_state == S5_ST) &&
(curr_seq1_0_lat != SEQ_SINGLE_CHAN) && rst_lock == 0)
eos_tmp_en <= 1;
else
eos_tmp_en <= 0;
if (eos_tmp_en == 1 && seq_status_avg == 0 ) // delay by 1 adcclk
eos_en <= 1;
else
eos_en <= 0;
if (eos_tmp_en == 1 || (curr_seq1_0_lat == SEQ_SINGLE_CHAN)) begin
seq_count <= 1;
end
else if (seq_count_en == 1) begin
if (seq_count >= 37)
seq_count <= 1;
else
seq_count <= seq_count +1;
end
end // else: !if(rst_in == 1 )
// end sequence control
// Acquisition
reg first_acq;
reg shorten_acq;
wire BUSY_out_dly;
assign #10 BUSY_out_dly = BUSY_out;
always @(adc_state or posedge rst_in or first_acq) begin
if(rst_in)
shorten_acq = 0;
else if(BUSY_out_dly==0 && adc_state==S2_ST && first_acq==1)
shorten_acq = 1;
else
shorten_acq = 0;
end
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1 || rst_lock == 1) begin
acq_count <= 1;
first_acq <= 1;
end
else begin
if (adc_state == S2_ST && rst_lock == 0 && (acq_e_c==0)) begin
first_acq <= 0;
if (acq_acqsel == 1) begin
if (acq_count <= 11)
acq_count <= acq_count + 1 + shorten_acq;
end
else begin
if (acq_count <= 4)
acq_count <= acq_count + 1 + shorten_acq;
end // else: !if(acq_acqsel == 1)
if (adc_next_state == S3_ST)
if ((acq_acqsel == 1 && acq_count < 10) || (acq_acqsel == 0 && acq_count < 4))
$display ("Warning: [Unisim %s-21] Acquisition time is not long enough at time %t. Instance: %m", MODULE_NAME, $time);
end // if (adc_state == S2_ST)
else
acq_count <= (first_acq) ? 1 : 0;
end // if (rst_in == 0)
// continuous mode
reg conv_start_cont;
wire reset_conv_start;
wire conv_start_sel;
always @(adc_state or acq_acqsel or acq_count)
if (adc_state == S2_ST) begin
if (rst_lock == 0) begin
// CR 800173
// if ( ((seq_reset_flag == 0 || (seq_reset_flag == 1 && curr_clkdiv_sel > 8'h03)) &&
// ( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) ) )
if ((acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) // acq time, adcclk cycles 4 or 10
conv_start_cont = 1;
else
conv_start_cont = 0;
end
end // if (adc_state == S2_ST)
else
conv_start_cont = 0;
assign conv_start_sel = (acq_e_c) ? CONVST_reg : conv_start_cont;
assign reset_conv_start = rst_in | (conv_count==CONV_CAL_PER_0);
always@(posedge conv_start_sel or posedge reset_conv_start) begin
if(reset_conv_start)
conv_start <= 0;
else
conv_start <= 1;
end
// end acquisition
// Conversion
always @(adc_state or adc_next_state or curr_chan or mn_mux_in or curr_b_u) begin
if ((adc_state == S3_ST && adc_next_state == S5_ST) || adc_state == S5_ST) begin
if (curr_chan == 0) begin // temperature conversion
adc_temp_result = (mn_mux_in + 273.6777) * 0.0019945*65536.0; //CR 861679
if (adc_temp_result >= 65535.0)
conv_result_int = 65535;
else if (adc_temp_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_temp_result);
if (adc_temp_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (curr_chan == 1 || curr_chan == 2 || curr_chan ==6 ||
curr_chan == 13 || curr_chan == 14 || curr_chan == 15 ||
(curr_chan >= 32 && curr_chan <= 35)) begin // internal power conversion
adc_intpwr_result = mn_mux_in * 65536.0 / 3.0;
if (adc_intpwr_result >= 65535.0)
conv_result_int = 65535;
else if (adc_intpwr_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_intpwr_result);
if (adc_intpwr_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (curr_chan == 3 || (curr_chan >=16 && curr_chan <= 31)) begin
adc_ext_result = (mn_mux_in) * 65536.0;
if (curr_b_u == 1) begin
if (adc_ext_result > 32767.0)
conv_result_int = 32767;
else if (adc_ext_result < -32768.0)
conv_result_int = -32768;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else begin
if (adc_ext_result > 65535.0)
conv_result_int = 65535;
else if (adc_ext_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
end
else begin
conv_result_int = 0;
end
end
conv_result = conv_result_int;
end // always @ ( adc_state or curr_chan or mn_mux_in, curr_b_u)
reg busy_r_rst_done;
always @(posedge adcclk or posedge rst_in) begin
if (rst_in == 1) begin
busy_r_rst <= 0;
busy_r_rst_done <= 0;
conv_count <= CONV_CAL_PER_RST;
conv_end <= 0;
end
else begin
if(adc_state == S2_ST) begin
busy_r_rst_done <= 1;
busy_r_rst <= (!busy_r_rst_done) ? 1 : 0;
if (conv_start == 1) begin
conv_count <= 0;
conv_end <= 0;
end
end
else if (adc_state == S3_ST ) begin
busy_r_rst_done <= 0;
conv_count = conv_count + 1;
if ((curr_chan!=5'b01000 ) && (conv_count==CONV_NOTCAL_PER_1 ) ||
(curr_chan==5'b01000 ) && (conv_count==CONV_CAL_PER_2 ) && (first_cal_chan) ||
(curr_chan==5'b01000 ) && (conv_count==CONV_CAL_PER_3 ) && (!first_cal_chan))
conv_end <= 1;
else
conv_end <= 0;
end
else begin //all other adc_state's except for S2_ST and S3_ST
conv_end <= 0;
conv_count <= 0;
end
end
end//always
always @(posedge adcclk or posedge rst_in) begin
if (rst_in == 1)
conv_result_reg <= 0;
else begin
if (adc_state == S5_ST)
conv_result_reg <= conv_result;
end
end
always @(posedge adcclk or posedge rst_in) begin
if (rst_in == 1)
single_chan_conv_end <= 0;
else begin
// jmcgrath - to model the behaviour correctly when a cal chanel is being converted
// an signal to signify the conversion has ended must be produced - this is for single channel mode
single_chan_conv_end <= 0;
if( (conv_count ==CONV_NOTCAL_PER_1) || (conv_count == CONV_CAL_PER_4))
single_chan_conv_end <= 1;
end
end
assign avg_amount = averaging==2'b00 ? 0 :
averaging==2'b01 ? 15 :
averaging==2'b10 ? 63 :
255 ; //2'b11
always @(posedge adcclk or posedge rst_in) begin
if (rst_in == 1) begin
seq_status_avg <= 0;
for (i = 0; i <=35; i = i +1) begin
conv_avg_count[i] <= 0; // array of integer
end
end
else begin
if (adc_state == S3_ST && adc_next_state == S5_ST && rst_lock == 0) begin
if(averaging==2'b00) begin
eoc_en <= 1;
conv_avg_count[curr_chan] <= 0;
end
else begin //averaging is on
if (conv_avg_count[curr_chan] == avg_amount) begin
eoc_en <= 1;
conv_avg_count[curr_chan] <= 0;
seq_status_avg <= seq_status_avg - 1;
end
else begin
eoc_en <= 0;
if (conv_avg_count[curr_chan] == 0) begin
seq_status_avg <= seq_status_avg + 1;
end
conv_avg_count[curr_chan] <= conv_avg_count[curr_chan] + 1;
end
end // averaging>0
end // if (adc_state == S3_ST && adc_next_state == S5_ST)
else begin
eoc_en <= 0;
end
end // else
end //always
// end conversion
// average
always @(adc_state or conv_acc[curr_chan])
if (adc_state == S5_ST )
// no signed or unsigned differences for bit vector conv_acc_vec
conv_acc_vec = conv_acc[curr_chan];
else
conv_acc_vec = 24'd0;
always @(posedge adcclk or posedge rst_in)
if (rst_in == 1) begin
for (j = 0; j <= 63; j = j + 1) begin
conv_acc[j] <= 0;
end
conv_acc_result <= 16'd0;
end
else begin
if (adc_state == S3_ST && adc_next_state == S5_ST) begin
if (averaging != 2'b00 && rst_lock != 1)
conv_acc[curr_chan] <= conv_acc[curr_chan] + conv_result_int;
else
conv_acc[curr_chan] <= 0;
end // if (adc_state == S3_ST && adc_next_state == S5_ST)
else if (eoc_en == 1) begin
case (averaging)
2'b00 : conv_acc_result <= 16'd0;
2'b01 : conv_acc_result <= conv_acc_vec[19:4];
2'b10 : conv_acc_result <= conv_acc_vec[21:6];
2'b11 : conv_acc_result <= conv_acc_vec[23:8];
endcase
conv_acc[curr_chan] <= 0;
end
end // if (rst_in == 0)
// end average
// single sequence
always @(posedge adcclk or posedge rst_in) begin
if (rst_in == 1)
single_pass_finished <= 0;
else
if (adc_state == S1_ST)
single_pass_finished <= 1; //single pass sequence selected and sequence has ended.
end
// end state
always @(posedge adcclk or posedge rst_in)
if (rst_in) begin
seq_count_en <= 0;
EOS_out_tmp <= 0;
EOC_out_tmp <= 0;
end
else begin
if ((adc_state == S3_ST && adc_next_state == S5_ST) && (curr_seq1_0_lat != SEQ_SINGLE_CHAN ) && !rst_lock )
seq_count_en <= 1;
else
seq_count_en <= 0;
if (!rst_lock) begin
EOS_out_tmp <= eos_en;
eoc_en_delay <= eoc_en;
EOC_out_tmp <= eoc_en_delay;
end
else begin
EOS_out_tmp <= 0;
eoc_en_delay <= 0;
EOC_out_tmp <= 0;
end
end
always @(posedge EOC_out_pre2 or posedge rst_in_not_seq) begin
if (rst_in_not_seq == 1) begin
data_reg[32] = 16'h0000;
data_reg[33] = 16'h0000;
data_reg[34] = 16'h0000;
data_reg[35] = 16'h0000;
data_reg[36] = 16'hFFFF;
data_reg[37] = 16'hFFFF;
data_reg[38] = 16'hFFFF;
data_reg[39] = 16'hFFFF;
data_reg[40] = 16'h0000;
data_reg[41] = 16'h0000;
data_reg[42] = 16'h0000;
data_reg[44] = 16'hFFFF;
data_reg[45] = 16'hFFFF;
data_reg[46] = 16'hFFFF;
end
else if ( rst_lock == 0) begin //also posedge EOC_out_pre2
// current or averaged values' update to status registers
if ((curr_chan_lat >= 0 && curr_chan_lat <= 3) || (curr_chan_lat == 6) ||
(curr_chan_lat >= 13 && curr_chan_lat <= 31)) begin
if (averaging_d == 2'b00)
data_reg[curr_chan_lat] <= conv_result_reg;
else
data_reg[curr_chan_lat] <= conv_acc_result;
end
else if (curr_chan_lat >= 32 && curr_chan_lat <= 35) begin //VUser0-3
if (averaging_d == 2'b00)
dr_sram[curr_chan_lat + 96] <= conv_result_reg; //80h-83h
else
dr_sram[curr_chan_lat + 96] <= conv_acc_result;
end
else if (curr_chan_lat == 4) // VREFP
data_reg[curr_chan_lat] <= 16'h0000; // CR-961722 Simulation always simulates the internal reference behavior. Hence VrefP=0V
else if (curr_chan_lat == 5) // VREFN
data_reg[curr_chan_lat] <= 16'h0000;
//min and max values' update
if (curr_chan_lat == 0 || curr_chan_lat == 1 || curr_chan_lat == 2) begin //TEMPERATURE, VCCINT and VCCAUX max and min
if (averaging_d == 2'b00) begin
if (conv_result_reg > data_reg[32 + curr_chan_lat])
data_reg[32 + curr_chan_lat] <= conv_result_reg;
if (conv_result_reg < data_reg[36 + curr_chan_lat])
data_reg[36 + curr_chan_lat] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[32 + curr_chan_lat])
data_reg[32 + curr_chan_lat] <= conv_acc_result;
if (conv_acc_result < data_reg[36 + curr_chan_lat])
data_reg[36 + curr_chan_lat] <= conv_acc_result;
end
end
else if (curr_chan_lat == 6) begin //VCCBRAM max and min
if (averaging_d == 2'b00) begin
if (conv_result_reg > data_reg[35])
data_reg[35] <= conv_result_reg;
if (conv_result_reg < data_reg[39])
data_reg[39] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[35])
data_reg[35] <= conv_acc_result;
if (conv_acc_result < data_reg[39])
data_reg[39] <= conv_acc_result;
end
end
else if (curr_chan_lat >= 13 && curr_chan_lat <= 15) begin // VPSINTLP, VPSINTFP , VPSAUX
if (averaging_d == 2'b00) begin
if (conv_result_reg > data_reg[27+curr_chan_lat])
data_reg[27+curr_chan_lat] <= conv_result_reg;
if (conv_result_reg < data_reg[31+curr_chan_lat])
data_reg[31+curr_chan_lat] <= conv_result_reg;
end
else begin
if (conv_acc_result > data_reg[27+curr_chan_lat])
data_reg[27+curr_chan_lat] <= conv_acc_result;
if (conv_acc_result < data_reg[31+curr_chan_lat])
data_reg[31+curr_chan_lat] <= conv_acc_result;
end
end
else if (curr_chan_lat >= 32 && curr_chan_lat <=35) begin //Vuser0-3
if (averaging_d == 2'b00) begin
if (conv_result_reg < dr_sram[curr_chan_lat+136])
dr_sram[curr_chan_lat+136] <= conv_result_reg;
if (conv_result_reg > dr_sram[curr_chan_lat+128])
dr_sram[curr_chan_lat+128] <= conv_result_reg;
end
else begin
if (conv_acc_result < dr_sram[curr_chan_lat+136])
dr_sram[curr_chan_lat+136] <= conv_acc_result;
if (conv_acc_result > dr_sram[curr_chan_lat+128])
dr_sram[curr_chan_lat+128] <= conv_acc_result;
end
end
end // ( rst_lock == 0)
end//always
// current measurement data
always @(negedge busy_r or posedge rst_in_not_seq )
if (rst_in_not_seq)
data_written <= 16'd0;
else begin
if (averaging == 2'b00)
data_written <= conv_result_reg;
else
data_written <= conv_acc_result;
end
reg [4:0] op_count=15;
reg BUSY_out_sync;
wire BUSY_out_low_edge;
// eos and eoc
always @( posedge EOC_out_tmp or posedge EOC_out or posedge rst_in)
if (rst_in ==1)
EOC_out_tmp1 <= 0;
else if ( EOC_out ==1)
EOC_out_tmp1 <= 0;
else if (EOC_out_tmp == 1) begin
if (curr_chan != 5'b01000 && ( sysmone12_en == 1 || (curr_seq1_0[3:2] != 2'b10 && sysmone12_en == 0))) //not calibration and check power
EOC_out_tmp1 <= 1;
else
EOC_out_tmp1 <= 0;
end
always @( posedge EOS_out_tmp or posedge EOS_out or posedge rst_in)
if (rst_in ==1)
EOS_out_tmp1 <= 0;
else if (EOS_out ==1)
EOS_out_tmp1 <= 0;
else if (EOS_out_tmp == 1 && ( sysmone12_en == 1 || (curr_seq1_0[3:2] != 2'b10 && sysmone12_en == 0)))
EOS_out_tmp1 <= 1;
assign BUSY_out_low_edge = (BUSY_out==0 && BUSY_out_sync==1) ? 1 : 0;
always @( posedge DCLK_in or posedge rst_in) begin
if (rst_in)
op_count <= 15;
else begin
if (BUSY_out_low_edge==1 )
op_count <= 0;
else if(op_count < 22)
op_count <= op_count +1;
end
end
always @(posedge DCLK_in or posedge rst_in) begin
if (rst_in) begin
EOC_out <= 0;
EOS_out <= 0;
EOC_out_pre <= 0;
EOC_out_pre2 <= 0;
end
else begin
if(op_count== 16) begin
EOC_out <= EOC_out_tmp1;
EOS_out <= EOS_out_tmp1;
EOC_out_pre <=0;
EOC_out_pre2 <=0;
end
else if (op_count==15) begin
EOC_out <= 0;
EOS_out <= 0;
EOC_out_pre <= EOC_out_tmp1;
EOC_out_pre2 <=0;
end
else if (op_count==14) begin
EOC_out <= 0;
EOS_out <= 0;
EOC_out_pre <=0;
EOC_out_pre2 <= EOC_out_tmp1;
end
else begin
EOC_out <= 0;
EOS_out <= 0;
EOC_out_pre <= 0;
EOC_out_pre2 <= 0;
end
end
end
always @( posedge DCLK_in or posedge rst_in) begin
if (rst_in) begin
BUSY_out_sync <= 0;
drp_update <= 0;
alm_update <= 0;
end
else begin // if(rst_in==0) begin
BUSY_out_sync <= BUSY_out;
drp_update <= (op_count==3)? 1 : 0;
alm_update <= (op_count==5 && EOC_out_tmp1==1) ? 1 : 0;
end
end
// end eos and eoc
// alarm
always @( posedge alm_update or posedge rst_in_not_seq ) begin
if (rst_in_not_seq == 1) begin
ot_out_reg <= 0;
alm_out_reg <= 8'b0;
end
else if (rst_lock == 0) begin
if (curr_chan_lat == 0) begin // temperature
if (data_written >= ot_limit_reg)
ot_out_reg <= 1;
else if (data_written < dr_sram[8'h57])
ot_out_reg <= 0;
if (data_written > dr_sram[8'h50])
alm_out_reg[0] <= 1;
else if (data_written < dr_sram[8'h54])
alm_out_reg[0] <= 0;
end
if (curr_chan_lat == 1) begin // VCC INT
if (data_written > dr_sram[8'h51] || data_written < dr_sram[8'h55])
alm_out_reg[1] <= 1;
else
alm_out_reg[1] <= 0;
end
if (curr_chan_lat == 2) begin //VCCAUX
if (data_written > dr_sram[8'h52] || data_written < dr_sram[8'h56])
alm_out_reg[2] <= 1;
else
alm_out_reg[2] <= 0;
end
if (curr_chan_lat == 6) begin // VCC BRAM
if (data_written > dr_sram[8'h58] || data_written < dr_sram[8'h5C])
alm_out_reg[3] <= 1;
else
alm_out_reg[3] <= 0;
end
if (curr_chan_lat == 13) begin //VCC PSINTLP
if (data_written > dr_sram[8'h59] || data_written < dr_sram[8'h5D])
alm_out_reg[4] <= 1;
else
alm_out_reg[4] <= 0;
end
if (curr_chan_lat == 14) begin // VCC PSINTFP
if (data_written > dr_sram[8'h5A] || data_written < dr_sram[8'h5E])
alm_out_reg[5] <= 1;
else
alm_out_reg[5] <= 0;
end
if (curr_chan_lat == 15) begin // VCC PSAUX
if (data_written > dr_sram[8'h5B] || data_written < dr_sram[8'h5F])
alm_out_reg[6] <= 1;
else
alm_out_reg[6] <= 0;
end
if (curr_chan_lat == 32) begin // VUSER 0
if (data_written > dr_sram[8'h60] || data_written < dr_sram[8'h68])
alm_out_reg[8] <= 1;
else
alm_out_reg[8] <= 0;
end
if (curr_chan_lat == 33) begin // VUSER 1
if (data_written > dr_sram[8'h61] || data_written < dr_sram[8'h69])
alm_out_reg[9] <= 1;
else
alm_out_reg[9] <= 0;
end
if (curr_chan_lat == 34) begin // VUSER 2
if (data_written > dr_sram[8'h62] || data_written < dr_sram[8'h6A])
alm_out_reg[10] <= 1;
else
alm_out_reg[10] <= 0;
end
if (curr_chan_lat == 35) begin // VUSER 3
if (data_written > dr_sram[8'h63] || data_written < dr_sram[8'h6B])
alm_out_reg[11] <= 1;
else
alm_out_reg[11] <= 0;
end
end//rst_lock
end // always
//always @(ot_out_reg or ot_en or alm_out_reg or alm_en) begin
always @(*) begin
OT_out = ot_out_reg & ot_en;
ALM_out[6:0] = alm_out_reg[6:0] & alm_en[6:0];
ALM_out[7] = |ALM_out[6:0];
ALM_out[11:8] = alm_out_reg[11:8] & alm_en[11:8];
ALM_out[14:12] = 'd0; // Reserved
ALM_out[15] = (|ALM_out[11:8]) | (|ALM_out[6:0]);
end
// end alarm
//*** Timing_Checks_Start_here
`ifdef XIL_TIMING
reg notifier;
wire dclk_en_n;
wire dclk_en_p;
assign dclk_en_n = IS_DCLK_INVERTED_BIN;
assign dclk_en_p = ~IS_DCLK_INVERTED_BIN;
reg notifier_do;
wire rst_en_n = ~RESET_in && dclk_en_n;
wire rst_en_p = ~RESET_in && dclk_en_p;
always @(notifier) begin
alm_out_reg = 16'bx;
OT_out = 1'bx;
BUSY_out = 1'bx;
EOC_out = 1'bx;
EOS_out = 1'bx;
curr_chan = 5'bx;
DRDY_out = 1'bx;
DO_out = 16'bx;
end
always @(notifier_do) begin
DRDY_out = 1'bx;
DO_out = 16'bx;
end
`endif
specify
(DCLK => ALM[0]) = (100:100:100, 100:100:100);
(DCLK => ALM[10]) = (100:100:100, 100:100:100);
(DCLK => ALM[11]) = (100:100:100, 100:100:100);
(DCLK => ALM[12]) = (100:100:100, 100:100:100);
(DCLK => ALM[13]) = (100:100:100, 100:100:100);
(DCLK => ALM[15]) = (100:100:100, 100:100:100);
(DCLK => ALM[1]) = (100:100:100, 100:100:100);
(DCLK => ALM[2]) = (100:100:100, 100:100:100);
(DCLK => ALM[3]) = (100:100:100, 100:100:100);
(DCLK => ALM[4]) = (100:100:100, 100:100:100);
(DCLK => ALM[5]) = (100:100:100, 100:100:100);
(DCLK => ALM[6]) = (100:100:100, 100:100:100);
(DCLK => ALM[7]) = (100:100:100, 100:100:100);
(DCLK => ALM[8]) = (100:100:100, 100:100:100);
(DCLK => ALM[9]) = (100:100:100, 100:100:100);
(DCLK => BUSY) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[0]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[1]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[2]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[3]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[4]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[5]) = (100:100:100, 100:100:100);
(DCLK => DO[0]) = (100:100:100, 100:100:100);
(DCLK => DO[10]) = (100:100:100, 100:100:100);
(DCLK => DO[11]) = (100:100:100, 100:100:100);
(DCLK => DO[12]) = (100:100:100, 100:100:100);
(DCLK => DO[13]) = (100:100:100, 100:100:100);
(DCLK => DO[14]) = (100:100:100, 100:100:100);
(DCLK => DO[15]) = (100:100:100, 100:100:100);
(DCLK => DO[1]) = (100:100:100, 100:100:100);
(DCLK => DO[2]) = (100:100:100, 100:100:100);
(DCLK => DO[3]) = (100:100:100, 100:100:100);
(DCLK => DO[4]) = (100:100:100, 100:100:100);
(DCLK => DO[5]) = (100:100:100, 100:100:100);
(DCLK => DO[6]) = (100:100:100, 100:100:100);
(DCLK => DO[7]) = (100:100:100, 100:100:100);
(DCLK => DO[8]) = (100:100:100, 100:100:100);
(DCLK => DO[9]) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK => EOC) = (100:100:100, 100:100:100);
(DCLK => EOS) = (100:100:100, 100:100:100);
(DCLK => JTAGBUSY) = (100:100:100, 100:100:100);
(DCLK => JTAGLOCKED) = (100:100:100, 100:100:100);
(DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[0]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[1]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[2]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[3]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[4]) = (100:100:100, 100:100:100);
(DCLK => OT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CONVST, 0:0:0, notifier);
$period (negedge CONVSTCLK, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (posedge CONVST, 0:0:0, notifier);
$period (posedge CONVSTCLK, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$recrem (negedge RESET, negedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_n, dclk_en_n, RESET_delay, DCLK_delay);
$recrem (negedge RESET, posedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_p, dclk_en_p, RESET_delay, DCLK_delay);
$recrem (posedge RESET, negedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_n, dclk_en_n, RESET_delay, DCLK_delay);
$recrem (posedge RESET, posedge DCLK, 0:0:0, 0:0:0, notifier, dclk_en_p, dclk_en_p, RESET_delay, DCLK_delay);
$setuphold (negedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]);
$setuphold (negedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]);
$setuphold (negedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]);
$setuphold (negedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]);
$setuphold (negedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]);
$setuphold (negedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]);
$setuphold (negedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]);
$setuphold (negedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]);
$setuphold (negedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay);
$setuphold (negedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]);
$setuphold (negedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]);
$setuphold (negedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]);
$setuphold (negedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]);
$setuphold (negedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]);
$setuphold (negedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]);
$setuphold (negedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]);
$setuphold (negedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]);
$setuphold (negedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[2]);
$setuphold (negedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[3]);
$setuphold (negedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]);
$setuphold (negedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]);
$setuphold (negedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]);
$setuphold (negedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]);
$setuphold (negedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]);
$setuphold (negedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]);
$setuphold (negedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay);
$setuphold (negedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]);
$setuphold (negedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]);
$setuphold (negedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]);
$setuphold (negedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]);
$setuphold (negedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]);
$setuphold (negedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]);
$setuphold (negedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]);
$setuphold (negedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]);
$setuphold (negedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay);
$setuphold (negedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]);
$setuphold (negedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]);
$setuphold (negedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]);
$setuphold (negedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]);
$setuphold (negedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]);
$setuphold (negedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]);
$setuphold (negedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]);
$setuphold (negedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]);
$setuphold (negedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[2]);
$setuphold (negedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[3]);
$setuphold (negedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]);
$setuphold (negedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]);
$setuphold (negedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]);
$setuphold (negedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]);
$setuphold (negedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]);
$setuphold (negedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]);
$setuphold (negedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay);
$width (negedge CONVST, 0:0:0, 0, notifier);
$width (negedge CONVSTCLK, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (posedge CONVST, 0:0:0, 0, notifier);
$width (posedge CONVSTCLK, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
//`undef CALIBRATION_ALWAYS_FIRST
endmodule
`endcelldefine
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_wiz_0.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module clk_wiz_0 (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_wiz_0.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_wiz_0_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// The divider module divides one number by another. It
// produces a signal named "ready" when the quotient output
// is ready, and takes a signal named "start" to indicate
// the the input dividend and divider is ready.
// sign -- 0 for unsigned, 1 for twos complement
// It uses a simple restoring divide algorithm.
// http://en.wikipedia.org/wiki/Division_(digital)#Restoring_division
module divider #(parameter WIDTH = 8)
(input clk, sign, start,
input [WIDTH-1:0] dividend,
input [WIDTH-1:0] divider,
output reg [WIDTH-1:0] quotient,
output [WIDTH-1:0] remainder,
output ready);
reg [WIDTH-1:0] quotient_temp;
reg [WIDTH*2-1:0] dividend_copy, divider_copy, diff;
reg negative_output;
assign remainder = (!negative_output) ?
dividend_copy[WIDTH-1:0] : ~dividend_copy[WIDTH-1:0] + 1'b1;
reg [6:0] bit;
reg del_ready = 1;
assign ready = (!bit) & ~del_ready;
wire [WIDTH-2:0] zeros = 0;
initial bit = 0;
initial negative_output = 0;
always @( posedge clk ) begin
del_ready <= !bit;
if( start ) begin
bit = WIDTH;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[WIDTH-1]) ?
{1'b0,zeros,dividend} :
{1'b0,zeros,~dividend + 1'b1};
divider_copy = (!sign || !divider[WIDTH-1]) ?
{1'b0,divider,zeros} :
{1'b0,~divider + 1'b1,zeros};
negative_output = sign &&
((divider[WIDTH-1] && !dividend[WIDTH-1])
||(!divider[WIDTH-1] && dividend[WIDTH-1]));
end
else if ( bit > 0 ) begin
diff = dividend_copy - divider_copy;
quotient_temp = quotient_temp << 1;
if( !diff[WIDTH*2-1] ) begin
dividend_copy = diff;
quotient_temp[0] = 1'd1;
end
quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1'b1;
divider_copy = divider_copy >> 1;
bit = bit - 1'b1;
end
end
endmodule
|
/*
** -----------------------------------------------------------------------------**
** color_proc353.v
**
** Color space converter (bayer-> YCbCr 4:2:1) for JPEG compressor
**
** Copyright (C) 2002-2010 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
`define debug_compressor
module color_proc (clk, // pixel clock (1/2 system clock - 80MHz)
en, // Enable (0 will reset states)
en_sdc, // enable subtracting of DC component
go, // pulse to star/restart (needed for each frame, repeat generated by the caller)
nblocks, // [17:0] number of 16x16 blocks to read (valid @ "go" pulse)
eot, // single-cycle end of transfer pulse
m_cb, // [9:0] scale for CB - default 0.564 (10'h90)
m_cr, // [9:0] scale for CB - default 0.713 (10'hb6)
memWasInit, // memory channel2 was just initialized - reset page address (at posedge clk)
di, // [7:0]
sdram_a, // [10:0] (MSB - SDRAM buffer page number)
sdram_rdy, // SDRAM buffer ready
sdram_next, // request to read a page to SDRAM buffer
inc_sdrama, // enable read sdram buffer
noMoreData, // used as alternative to end frame input (possibly broken frame)
dv_raw, // data valid for di (for testing to bypass color conversion - use di[7:0])
ignore_color, //zero Cb/Cr components
four_blocks, // use only 6 blocks fro the output, not 6
jp4_dc_improved, // in JP4 mode, compare DC coefficients to the same color ones
tile_margin, // margins around 16x16 tiles (0/1/2)
tile_shift, // tile shift from top left corner
converter_type, // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff
scale_diff, // divide differences by 2 (to fit in 8-bit range)
hdr, // second green absolute, not difference
do, // [9:0] data out (4:2:0) (signed, average=0)
avr, // [8:0] DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!
dv, // out data valid (will go high for at least 64 cycles)
ds, // single-cycle mark of the first pixel in a 64 (8x8) - pixel block
tn, // [2:0] tile number 0..3 - Y, 4 - Cb, 5 - Cr (valid with start)
first, // sending first MCU (valid @ ds)
last, // sending last MCU (valid @ ds)
n000, // [7:0] number of zero pixels (255 if 256)
n255, // [7:0] number of 0xff pixels (255 if 256)
bayer_phase, //[1:0]) bayer color filter phase 0:(GR/BG), 1:(RG/GB), 2: (BG/GR), 3: (GB/RG)
// below signals valid at ds ( 1 later than tn, first, last)
component_num, //[2:0] - component number (YCbCr: 0 - Y, 1 - Cb, 2 - Cr, JP4: 0-1-2-3 in sequence (depends on shift) 4 - don't use
component_color, // use color quantization table (YCbCR, jp4diff)
component_first, // first this component in a frame (DC absolute, otherwise - difference to previous)
component_lastinmb // last component in a macroblock;
`ifdef debug_compressor
,bcntrIsZero
,bcntr
`endif
);
input ignore_color;
input four_blocks; // use only 6 blocks fro the output, not 6
input jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones
input [1:0] tile_margin; // margins around 16x16 tiles (0/1/2)
input [2:0] tile_shift; // tile shift from top left corner
input [2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff
input scale_diff; // divide differences by 2 (to fit in 8-bit range)
input hdr; // second green absolute, not difference
input clk, en, go, en_sdc;
input [17:0] nblocks;
output eot;
input [ 9:0] m_cb; // [9:0] scale for CB - default 0.564 (10'h90)
input [ 9:0] m_cr; // [9:0] scale for CB - default 0.713 (10'hb6)
input memWasInit; // memory channel2 was just initialized - reset page address (at posedge clk)
input [ 7:0] di;
output [ 10:0] sdram_a;
input sdram_rdy;
output sdram_next;
output inc_sdrama;
input noMoreData; // (@posedge clk) used as alternative to end frame input (possibly broken frame)
output dv_raw;
// output [ 8:0] do;
output [ 9:0] do;
// output [ 7:0] avr;
output [ 8:0] avr;
output dv;
output ds;
output [ 2:0] tn;
output first;
output last;
output [7:0] n000;
output [7:0] n255;
input [1:0] bayer_phase;
output [2:0] component_num; //[1:0] - component number (YCbCr: 0 - Y, 1 - Cb, 2 - Cr, JP4: 0-1-2-3 in sequence (depends on shift), >=4 - don't use
output component_color; // use color quantization table (YCbCR, jp4diff)
output component_first; // first this component in a frame (DC absolute, otherwise - difference to previous)
output component_lastinmb; // last component in a macroblock;
//debug
`ifdef debug_compressor
output bcntrIsZero;
output [17:0] bcntr;
`endif
wire [ 9:0] m_cb; // [9:0] scale for CB - default 0.564 (10'h90)
wire [ 9:0] m_cr; // [9:0] scale for CB - default 0.713 (10'hb6)
wire [7:0] di;
wire [8:0] y_out; // data from buffer
wire [8:0] c_out; // data from buffer
reg [1:0] wpage; // page (0/1) where data is being written to (both Y and CbCr)
reg [1:0] rpage; // page (0/1) from where data is sent out ( both Y and CbCr)
wire [10:0] sdram_a;
reg sdram_next;
reg [17:0] bcntr; // down counter of blocks left
reg bcntrIsZero; // one cycle of bcntr[]==0
reg eot;
reg ccv_start_en; //
reg ccv_out_start,ccv_out_start_d; // start output of YCbCr from buffers
reg [8:0] raddr; // output address of buffer memories (MSB selects Y(0)/CbCr(1))
reg dv0; // "dv0" - one cycle ahead of "dv" to compensate for "do" register latency
reg ds0; // "ds0" - one cycle ahead of "ds" to compensate for "do" register latency
// reg [8:0] do;
// reg [8:0] pre_do;
reg [9:0] do;
reg [9:0] pre_do;
reg [1:0] pre_dv, pre_ds;
wire dv=pre_dv[1];
wire ds=pre_ds[1];
wire [2:0] tn;
reg dv_raw;
// reg [13:0] accYA,accYB,accCb, accCr;
// reg [13:0] accY0,accY1,accY2,accY3,accC2b, accCr; //will use 6 individual accumulators for larger flexibility (different input sequence)
// 16x8 dual port RAM
reg buf_sel;
reg willbe_first;
reg first,first0;
reg last,last0;
reg [4:0] preline; // number of line in a tile, down counter (0x13->0, 0x11->0, 0x0f->0), 1 cycles ahead of data from SDRAM
reg [4:0] prepix; // number of pixel in a line in a tile, down counter (0x13->0, 0x11->0, 0x0f->0)
// reg [1:0] sdram_page;
reg [1:0] sdram_a9_page;
reg [8:0] sdram_a9;
reg [8:0] seq_cntr; // master
// reg [2:0] pre_inc_sdrama;
wire [4:0] tile_size;
wire [8:0] macroblock_period_minus1;
wire all_ready;
reg preline_was_0;
reg pre_start_of_line;
reg pre_first_pixel;
reg [8:0] sdrama_top_left; // address of top left corner to be processed
reg [2:0] sdrama_line_inc; // increment amount when proceeding to next tile line
reg inc_sdrama;
reg last_from_sdram; // reading last byte from SDRAM
reg first_pixel; // reading first pixel to color converter (di will be evailable next cycle)
reg tim2next;
reg [8:0] y_in, c_in;
reg [7:0] yaddrw, caddrw;
reg ywe, cwe;
reg color_enable, pre_color_enable;// prevent random colors in monochrome/JP46 modes (pre_* - sync input)
reg cs_pre_first_out; // clear color accumulators
wire [7:0] conv18_y_in, conv20_y_in, mono_y_in, jp4_y_in;
// wire [8:0] jp4diff_y_in, conv18_c_in, conv20_c_in;
wire [8:0] jp4diff_y_in, conv18_c_in, conv20_c_in;
wire [7:0] conv18_yaddrw, conv20_yaddrw, mono_yaddrw, jp4_yaddrw, jp4diff_yaddrw;
wire [6:0] conv18_caddrw, conv20_caddrw;
wire conv18_ywe, conv18_cwe, conv20_ywe, conv20_cwe, mono_ywe, jp4_ywe, jp4diff_ywe;
wire conv18_pre_first_out, conv20_pre_first_out, mono_pre_first_out, jp4_pre_first_out, jp4diff_pre_first_out;
reg [4:0] en_converters;
reg [2:0] converter_type_r;
reg ignore_color_r;
reg jp4_dc_improved_r;
// reg jp4_diff_r;
reg four_blocks_r;
reg scale_diff_r;
reg hdr_r;
reg [1:0] tile_margin_r; // SuppressThisWarning Veditor UNUSED
// reg [2:0] tile_shift_r;
reg [1:0] bayer_phase_r;
reg [3:0] bayer_phase_onehot;
reg raddr_lastInBlock;
reg raddr_updateBlock; // first in block, after last also. Should be when *_r match the currently selected converter for the macroblock
wire [2:0] component_num; //[1:0] - component number (YCbCr: 0 - Y, 1 - Cb, 2 - Cr, JP4: 0-1-2-3 in sequence (depends on shift) >=4 - don't use
wire component_color; // use color quantization table (YCbCR, jp4diff)
wire component_first; // first this component in a frame (DC absolute, otherwise - difference to previous)
// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)
reg component_lastinmb; // last component in a macroblock;
reg [5:0] component_numsL, component_numsLS; // component_num[0] vs tn
reg [5:0] component_numsM, component_numsMS; // component_num[1] vs tn
reg [5:0] component_numsH, component_numsHS; // component_num[2] vs tn
reg [5:0] component_colors, component_colorsS; // use color quantization table (YCbCR, jp4diff)
reg [5:0] component_firsts, component_firstsS; // first this component in a frame (DC absolute, otherwise - difference to previous)
reg eof_rq; // request to end frame if there will be no more data
assign sdram_a={sdram_a9_page[1:0],sdram_a9[8:0]};
assign tn[2:0]=raddr[8:6];
assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};
assign component_color = component_colors[0];
assign component_first = component_firsts[0];
assign all_ready = sdram_rdy && ccv_start_en;
assign macroblock_period_minus1[8:0] = four_blocks?(tile_margin[1]?9'h18f:(tile_margin[0]?9'h143:9'h0ff)):(tile_margin[1]?9'h18f:9'h17f);
assign tile_size[4:0] = tile_margin[1]?5'h13:(tile_margin[0]?5'h11:5'h0f);
always @ (posedge clk) begin
if (!en) seq_cntr[8:0] <=9'h0;
else if (seq_cntr[8:0]!=0) seq_cntr[8:0] <= seq_cntr[8:0] -1;
else if (all_ready) seq_cntr[8:0] <= macroblock_period_minus1;
preline_was_0 <= (preline[4:0]==5'h0);
if ((seq_cntr[8:0]==0) || ((prepix[4:0]==0) && !preline_was_0) ) prepix[4:0] <= tile_size[4:0];
else if (prepix[4:0]!=0) prepix[4:0] <= prepix[4:0] - 1;
if (seq_cntr[8:0]==0) preline[4:0] <= tile_size[4:0];
else if ((prepix[4:0]==0) && !preline_was_0) preline[4:0] <= preline[4:0] - 1;
pre_start_of_line <= ((seq_cntr[8:0]==0) || ((prepix[4:0]==0) && !preline_was_0) );
pre_first_pixel <= en && (seq_cntr[8:0]==9'h0) && all_ready;
case (tile_shift[2:0])
3'h0: sdrama_top_left[8:0] <= 9'h0;
3'h1: sdrama_top_left[8:0] <= 9'h15;
3'h2: sdrama_top_left[8:0] <= 9'h2a;
3'h3: sdrama_top_left[8:0] <= 9'h3f;
3'h4: sdrama_top_left[8:0] <= 9'h54;
endcase
case (tile_margin[1:0])
2'h0: sdrama_line_inc[2:0] <= 3'h5;
2'h1: sdrama_line_inc[2:0] <= 3'h3;
2'h2: sdrama_line_inc[2:0] <= 3'h1;
endcase
first_pixel <= pre_first_pixel;
last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0);
inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram ));
if (pre_first_pixel) sdram_a9[8:0] <= sdrama_top_left[8:0];
else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 3'b1);
if (!en || memWasInit) sdram_a9_page[1:0] <= 2'h0;
else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1;
// wpage[1:0] valid with ywe
if (cs_pre_first_out) wpage[1:0] <= sdram_a9_page[1:0]; // copy page from SDRAM buffer
// register control modes to be valid while overlapping
if (pre_first_pixel) begin
converter_type_r [2:0] <= converter_type[2:0];
ignore_color_r <= ignore_color;
jp4_dc_improved_r <= jp4_dc_improved;
// jp4_diff_r <= (converter_type[2:0]==3'h4);
four_blocks_r <= four_blocks;
scale_diff_r <= scale_diff;
hdr_r <= hdr;
// scale_diff <= (converter_type[2:0]==3'h5);
tile_margin_r[1:0] <= tile_margin[1:0];
// tile_shift_r[2:0] <= tile_shift[2:0];
bayer_phase_r[1:0] <= bayer_phase[1:0];
bayer_phase_onehot[3:0]<={(bayer_phase[1:0]==2'h3)?1'b1:1'b0,
(bayer_phase[1:0]==2'h2)?1'b1:1'b0,
(bayer_phase[1:0]==2'h1)?1'b1:1'b0,
(bayer_phase[1:0]==2'h0)?1'b1:1'b0};
end
if (!en) en_converters[4:0] <= 0;
else if (pre_first_pixel)
en_converters[4:0]<= {(converter_type[2:0]==3'h4)?1'b1:1'b0,
(converter_type[2:0]==3'h3)?1'b1:1'b0,
(converter_type[2:0]==3'h2)?1'b1:1'b0,
(converter_type[2:0]==3'h1)?1'b1:1'b0,
(converter_type[2:0]==3'h0)?1'b1:1'b0};
end
// new
//cs_pre_first_out
reg [3:0] accYen;
reg [1:0] accCen; // individual accumulator enable (includes clearing)
reg [3:0] accYfirst;
reg [1:0] accCfirst; // add to zero, instead of to acc @ acc*en
// reg [7:0] preAccY, preAccC; // registered data from color converters, matching acc selection latency
reg [8:0] preAccY, preAccC; // registered data from color converters, matching acc selection latency
// reg [13:0] accY0,accY1,accY2,accY3,accC0,accC1;
reg [14:0] accY0,accY1,accY2,accY3,accC0,accC1;
reg cs_first_out;
reg [5:0] accCntrY0,accCntrY1,accCntrY2,accCntrY3,accCntrC0,accCntrC1;
wire [3:0] pre_accYdone;
wire [1:0] pre_accCdone; // need to make sure that pre_accCdone do not happen with pre_accYdone
reg [3:0] accYrun;
reg [1:0] accCrun;
reg [3:0] accYdone;
// reg [1:0] accCdone;
reg accYdoneAny;
reg [1:0] avrY_wa, pre_avrY_wa;
reg avrC_wa, pre_avrC_wa;
reg avrPage_wa, pre_avrPage_wa;
reg avr_we;
// reg [7:0] avermem[0:15];
reg [8:0] avermem[0:15];
wire [3:0] avr_wa= {avrPage_wa,accYdoneAny?{1'b0,avrY_wa[1:0]}:{2'b10,avrC_wa}};
reg [3:0] avr_ra; // read address
// wire [7:0] avrY_di= avrY_wa[1] ? (avrY_wa[0]?accY3[13:6]:accY2[13:6]):(avrY_wa[0]?accY1[13:6]:accY0[13:6]);
wire [8:0] avrY_di= avrY_wa[1] ? (avrY_wa[0]?accY3[14:6]:accY2[14:6]):(avrY_wa[0]?accY1[14:6]:accY0[14:6]);
// wire [7:0] avrC_di= avrC_wa ?accC1[13:6]:accC0[13:6];
wire [8:0] avrC_di= avrC_wa ?accC1[14:6]:accC0[14:6];
// wire [7:0] avr = avermem[avr_ra[3:0]];
wire [8:0] avr = avermem[avr_ra[3:0]];
assign pre_accYdone[3:0] = {(accCntrY3[5:0]==6'h3e)?1'b1:1'b0,(accCntrY2[5:0]==6'h3e)?1'b1:1'b0,(accCntrY1[5:0]==6'h3e)?1'b1:1'b0,(accCntrY0[5:0]==6'h3e)?1'b1:1'b0} & accYen[3:0];
assign pre_accCdone[1:0] = { (accCntrC1[5:0]==6'h3e)?1'b1:1'b0,(accCntrC0[5:0]==6'h3e)?1'b1:1'b0} & accCen[1:0];
always @ (posedge clk) begin
cs_first_out<=cs_pre_first_out;
// if (ywe) preAccY[7:0] <= y_in[7:0];
if (ywe) preAccY[8:0] <= y_in[8:0];
// if (cwe) preAccC[7:0] <= c_in[7:0];
if (cwe) preAccC[8:0] <= c_in[8:0];
accYen[3:0] <= {4{en & ywe}} & {yaddrw[7] & yaddrw[6], yaddrw[7] & ~yaddrw[6],~ yaddrw[7] & yaddrw[6], ~yaddrw[7] & ~yaddrw[6]};
accCen[1:0] <= {2{en & cwe}} & {caddrw[6], ~caddrw[6]};
accYfirst[3:0] <= {4{cs_first_out}} | (accYfirst[3:0] & ~accYen[3:0]);
accCfirst[1:0] <= {2{cs_first_out}} | (accCfirst[1:0] & ~accCen[1:0]);
// accAllFirst <= cs_first_out || ( accAllFirst && !(|accYen[3:0] || |accCen[1:0])); // until the first starts
if (accYen[0]) accY0[14:0]<= (accYfirst[0]?15'h0:accY0[14:0]) + {{6{preAccY[8]}},preAccY[8:0]};
if (accYen[1]) accY1[14:0]<= (accYfirst[1]?15'h0:accY1[14:0]) + {{6{preAccY[8]}},preAccY[8:0]};
if (accYen[2]) accY2[14:0]<= (accYfirst[2]?15'h0:accY2[14:0]) + {{6{preAccY[8]}},preAccY[8:0]};
if (accYen[3]) accY3[14:0]<= (accYfirst[3]?15'h0:accY3[14:0]) + {{6{preAccY[8]}},preAccY[8:0]};
if (accCen[0]) accC0[14:0]<= (accCfirst[0]?15'h0:accC0[14:0]) + {{6{preAccC[8]}},preAccC[8:0]};
if (accCen[1]) accC1[14:0]<= (accCfirst[1]?15'h0:accC1[14:0]) + {{6{preAccC[8]}},preAccC[8:0]};
/*
if (accYen[0]) accCntrY0[5:0]<= (accYfirst[0]?6'h0:(accCntrY0[5:0]+1));
if (accYen[1]) accCntrY1[5:0]<= (accYfirst[1]?6'h0:(accCntrY1[5:0]+1));
if (accYen[2]) accCntrY2[5:0]<= (accYfirst[2]?6'h0:(accCntrY2[5:0]+1));
if (accYen[3]) accCntrY3[5:0]<= (accYfirst[3]?6'h0:(accCntrY3[5:0]+1));
if (accCen[0]) accCntrC0[5:0]<= (accCfirst[0]?6'h0:(accCntrC0[5:0]+1));
if (accCen[1]) accCntrC1[5:0]<= (accCfirst[1]?6'h0:(accCntrC1[5:0]+1));
*/
if (!en) accCntrY0[5:0]<= 6'h0; else if (accYen[0]) accCntrY0[5:0]<= (accYfirst[0]?6'h0:(accCntrY0[5:0]+1));
if (!en) accCntrY1[5:0]<= 6'h0; else if (accYen[1]) accCntrY1[5:0]<= (accYfirst[1]?6'h0:(accCntrY1[5:0]+1));
if (!en) accCntrY2[5:0]<= 6'h0; else if (accYen[2]) accCntrY2[5:0]<= (accYfirst[2]?6'h0:(accCntrY2[5:0]+1));
if (!en) accCntrY3[5:0]<= 6'h0; else if (accYen[3]) accCntrY3[5:0]<= (accYfirst[3]?6'h0:(accCntrY3[5:0]+1));
if (!en) accCntrC0[5:0]<= 6'h0; else if (accCen[0]) accCntrC0[5:0]<= (accCfirst[0]?6'h0:(accCntrC0[5:0]+1));
if (!en) accCntrC1[5:0]<= 6'h0; else if (accCen[1]) accCntrC1[5:0]<= (accCfirst[1]?6'h0:(accCntrC1[5:0]+1));
accYrun[3:0] <= {4{en}} & ((accYfirst[3:0] & accYen[3:0]) | (accYrun[3:0] & ~pre_accYdone[3:0]));
accCrun[1:0] <= {2{en}} & ((accCfirst[1:0] & accCen[1:0]) | (accCrun[1:0] & ~pre_accCdone[1:0]));
accYdone[3:0] <= pre_accYdone[3:0] & accYrun[3:0];
// accCdone[1:0] <= pre_accCdone[1:0] & accCrun[1:0];
accYdoneAny <= |(pre_accYdone[3:0] & accYrun[3:0]);
avr_we <= |(pre_accYdone[3:0] & accYrun[3:0]) || |(pre_accCdone[1:0] & accCrun[1:0]);
pre_avrY_wa[1:0] <= yaddrw[7:6];
avrY_wa[1:0] <= pre_avrY_wa[1:0];
pre_avrC_wa <= caddrw[ 6];
avrC_wa <= pre_avrC_wa;
pre_avrPage_wa <= wpage[0];
avrPage_wa <= pre_avrPage_wa;
// if (avr_we) avermem[avr_wa[3:0]] <= accYdoneAny?avrY_di[7:0]:avrC_di[7:0];
if (avr_we) avermem[avr_wa[3:0]] <= en_sdc?(accYdoneAny?avrY_di[8:0]:avrC_di[8:0]):9'h0;
avr_ra[3:0] <= {rpage[0],raddr[8:6]};
end
reg transfer_ended=0; /// there was already EOT pulse for the current frame
always @ (posedge clk) begin
transfer_ended <= bcntrIsZero && (transfer_ended || eot);
/*+*/ tim2next <= (seq_cntr[8:0]=='h10); // rather arbitrary number - sdram buffer should in no case be actually overwritten before data read out
// it may depend on relation between SDRAM clk frequency (75MHz) and this clk (variable? 30MHz)
// eof_rq <= (tim2next && !bcntrIsZero) || (eof_rq && !(inc_sdrama || noMoreData ||transfer_ended));
eof_rq <= (tim2next && !bcntrIsZero) || (eof_rq && !(inc_sdrama || transfer_ended));
// ccv_start_en <= en && (ccv_start_en || go); //NOTE: Just for simulation
ccv_start_en <= en && !eot && (ccv_start_en || go); //FIXME: Still uncaught problem: SDRAM ready occurs before go_single!
// bcntrIsZero <= (bcntr[17:0]==18'b0) || noMoreData;
bcntrIsZero <= (bcntr[17:0]==18'b0);
sdram_next <= tim2next && ~sdram_next;
// eot <= (tim2next && bcntrIsZero) || (eof_rq && noMoreData);
eot <= !transfer_ended && !eot && bcntrIsZero && (tim2next || (eof_rq && noMoreData));
if (go) bcntr[17:0] <= nblocks[17:0];
else if (noMoreData) bcntr[17:0] <= 18'b0;
else if (sdram_next && !bcntrIsZero) bcntr[17:0] <= bcntr[17:0]-1;
if (ccv_out_start) rpage[1:0] <=wpage[1:0];
if (ccv_out_start) color_enable <= pre_color_enable;
ccv_out_start_d <= ccv_out_start;
raddr_lastInBlock <= en && (raddr[5:0]==6'h3e);
raddr_updateBlock <= raddr_lastInBlock || ccv_out_start;
if (ccv_out_start || !en) raddr[8:0] <= {!en,!en,7'h0}; // 9'h180/9'h000;
else if (!raddr[8] || (!four_blocks_r && !raddr[7])) raddr[8:0] <= raddr[8:0]+1; // for 4 blocks - count for 0,1; 6 blocks - 0,1,2
dv0 <= en && raddr_updateBlock?(!raddr[8] || (!four_blocks_r && !raddr[7])):dv0;
ds0 <= raddr_updateBlock && (!raddr[8] || (!four_blocks_r && !raddr[7]));
buf_sel <= raddr[8];
// pre_do[8:0] <= (buf_sel?c_out[7:0]:y_out[7:0])-avr[7:0];
// pre_do[9:0] <= (buf_sel?{c_out[8],c_out[8:0]}:{y_out[8],y_out[8:0]})-{avr[8],avr[8:0]};
pre_do[9:0] <= buf_sel?(color_enable?({c_out[8],c_out[8:0]}-{avr[8],avr[8:0]}):10'b0):({y_out[8],y_out[8:0]}-{avr[8],avr[8:0]});
//color_enable
// do[8:0] <= pre_do[8:0];
do[9:0] <= pre_do[9:0];
dv_raw <= inc_sdrama && en;
if (go) willbe_first <= 1'b1;
else if (first_pixel) willbe_first <= 1'b0;
if (first_pixel) begin
first0 <= willbe_first;
last0 <= (bcntr[17:0] == 18'b0);
end
if (ccv_out_start) begin
first <= first0;
last <= last0;
end
// 8x8 memory to hold average values
// if (avm_we) avermem[avm_a[3:0]] <= avm_d[7:0];
pre_dv[1:0] <= {pre_dv[0],dv0};
pre_ds[1:0] <= {pre_ds[0],ds0};
// Shift registers - generating block attributes to be used later in compressor
if (raddr_updateBlock) begin
if (ccv_out_start_d) begin
component_numsL[5:0] <= component_numsLS[5:0];
component_numsM[5:0] <= component_numsMS[5:0];
component_numsH[5:0] <= component_numsHS[5:0];
component_colors[5:0] <= component_colorsS[5:0];
component_firsts[5:0] <= first0? component_firstsS[5:0]:6'h0; // here we may use first0 that is one cycle earlier and ends much earlier
end else begin
component_numsL[5:0] <= {1'b0,component_numsL[5:1]};
component_numsM[5:0] <= {1'b0,component_numsM[5:1]};
component_numsH[5:0] <= {1'b0,component_numsH[5:1]};
component_colors[5:0] <= {1'b0,component_colors[5:1]};
component_firsts[5:0] <= {1'b0,component_firsts[5:1]};
end
end
component_lastinmb <= tn[0] && (four_blocks_r? tn[1] : tn[2]); // last component in a macroblock;
end
// average for each block should be calculated before the data goes to output output
always @ (posedge clk) case (converter_type_r[2:0])
3'h0:begin //color 18
cs_pre_first_out <= conv18_pre_first_out;
y_in[8:0] <= {conv18_y_in[7],conv18_y_in[7:0]};
ywe <= conv18_ywe;
yaddrw[7:0] <= {conv18_yaddrw[7],conv18_yaddrw[3],conv18_yaddrw[6:4],conv18_yaddrw[2:0]};
c_in[8:0] <= {conv18_c_in[8:0]};
cwe <= conv18_cwe;
pre_color_enable <= 1'b1;
caddrw[7:0] <= {1'b0,conv18_caddrw[6:0]};
ccv_out_start <= (conv18_yaddrw[7:0]==8'hc5); //TODO: adjust to minimal latency?
component_numsLS <= 6'h10; // component_num [0]
component_numsMS <= 6'h20; // component_num [1]
component_numsHS <= 6'h00; // component_num [2]
component_colorsS <= 6'h30; // use color quantization table (YCbCR, jp4diff)
component_firstsS <= 6'h31; // first this component in a frame (DC absolute, otherwise - difference to previous)
end
3'h1:begin //color 20
cs_pre_first_out <= conv20_pre_first_out;
y_in[8:0] <= {conv20_y_in[7],conv20_y_in[7:0]};
ywe <= conv20_ywe;
yaddrw[7:0] <= {conv20_yaddrw[7],conv20_yaddrw[3],conv20_yaddrw[6:4],conv20_yaddrw[2:0]};
c_in[8:0] <= {conv20_c_in[8:0]};
cwe <= conv20_cwe;
pre_color_enable <= 1'b1;
caddrw[7:0] <= {1'b0,conv20_caddrw[6:0]};
ccv_out_start <= (conv20_yaddrw[7:0]==8'hc5); //TODO: adjust to minimal latency?
component_numsLS <= 6'h10; // component_num [0]
component_numsMS <= 6'h20; // component_num [1]
component_numsHS <= 6'h3f; // component_num [2]
component_colorsS <= 6'h30; // use color quantization table (YCbCR, jp4diff)
component_firstsS <= 6'h31; // first this component in a frame (DC absolute, otherwise - difference to previous)
end
3'h2:begin //mono
cs_pre_first_out <= mono_pre_first_out;
y_in[8:0] <= {mono_y_in[7],mono_y_in[7:0]};
ywe <= mono_ywe;
yaddrw[7:0] <= {mono_yaddrw[7],mono_yaddrw[3],mono_yaddrw[6:4],mono_yaddrw[2:0]};
c_in[8:0] <= 9'h0;
cwe <= 1'b0;
pre_color_enable <= 1'b0;
caddrw[7:0] <= 8'h0;
ccv_out_start <= accYdone[0];
component_numsLS <= 6'h10; // component_num [0]
component_numsMS <= 6'h20; // component_num [1]
component_numsHS <= 6'h30; // component_num [2]
component_colorsS <= 6'h30; // use color quantization table (YCbCR, jp4diff)
component_firstsS <= 6'h31; // first this component in a frame (DC absolute, otherwise - difference to previous)
end
3'h3:begin // jp4
cs_pre_first_out <= jp4_pre_first_out;
y_in[8:0] <= {jp4_y_in[7],jp4_y_in[7:0]};
ywe <= jp4_ywe;
yaddrw[7:0] <= {jp4_yaddrw[7],jp4_yaddrw[3],jp4_yaddrw[6:4],jp4_yaddrw[2:0]};
c_in[8:0] <= 9'h0;
cwe <= 1'b0;
pre_color_enable <= 1'b0;
caddrw[7:0] <= 8'h0;
ccv_out_start <= accYdone[0];
component_numsLS <= jp4_dc_improved_r?6'h0a:6'h10; // LSb of component_num
component_numsMS <= jp4_dc_improved_r?6'h0c:6'h20; // MSb of component_num
component_numsHS <= 6'h30; // component_num [2]
component_colorsS <= 6'h30; // use color quantization table (YCbCR, jp4diff)
component_firstsS <= jp4_dc_improved_r?6'h3f:6'h31; // first this component in a frame (DC absolute, otherwise - difference to previous)
end
3'h4:begin //jp4diff
cs_pre_first_out <= jp4diff_pre_first_out;
y_in[8:0] <= {jp4diff_y_in[8:0]};
ywe <= jp4diff_ywe;
yaddrw[7:0] <= {jp4diff_yaddrw[7],jp4diff_yaddrw[3],jp4diff_yaddrw[6:4],jp4diff_yaddrw[2:0]};
c_in[8:0] <= 9'h0;
cwe <= 1'b0;
pre_color_enable <= 1'b0;
caddrw[7:0] <= 8'h0;
ccv_out_start <= accYdone[0];
component_numsLS <= 6'h0a; // LSb of component_num
component_numsMS <= 6'h0c; // MSb of component_num
component_numsHS <= 6'h30; // component_num [2]
component_colorsS <= {2'h3,~bayer_phase_onehot[3:0] | (hdr_r? {~bayer_phase_onehot[1:0],~bayer_phase_onehot[3:2]} : 4'h0)}; // use color quantization table (YCbCR, jp4diff)
component_firstsS <= 6'h3f; // first this component in a frame (DC absolute, otherwise - difference to previous)
end
endcase
wire limit_diff=1'b1;
csconvert18 i_csconvert18 (.RST(!en_converters[0]),
.CLK(clk),
.mono(ignore_color_r),
.limit_diff(limit_diff), // 1 - limit color outputs to -128/+127 range, 0 - let them be limited downstream
.m_cb(m_cb[9:0]), // [9:0] scale for CB - default 0.564 (10'h90)
.m_cr(m_cr[9:0]), // [9:0] scale for CB - default 0.713 (10'hb6)
.din(di[7:0]),
.pre_first_in(first_pixel),
.signed_y(conv18_y_in[7:0]),
.q(conv18_c_in[8:0]),
.yaddr(conv18_yaddrw[7:0]), //
.ywe(conv18_ywe),
.caddr(conv18_caddrw[6:0]),
.cwe(conv18_cwe),
.pre_first_out(conv18_pre_first_out),
.bayer_phase(bayer_phase_r[1:0]),
.n000(n000[7:0]), // TODO:remove ?
.n255(n255[7:0]));
csconvert_mono i_csconvert_mono (
.en(en_converters[2]),
.clk(clk),
.din(di[7:0]),
.pre_first_in(first_pixel),
.y_out (mono_y_in[7:0]),
.yaddr (mono_yaddrw[7:0]),
.ywe (mono_ywe),
.pre_first_out(mono_pre_first_out));
csconvert_jp4 i_csconvert_jp4 (
.en(en_converters[3]),
.clk(clk),
.din(di[7:0]),
.pre_first_in(first_pixel),
.y_out (jp4_y_in[7:0]),
.yaddr (jp4_yaddrw[7:0]),
.ywe (jp4_ywe),
.pre_first_out(jp4_pre_first_out));
csconvert_jp4diff i_csconvert_jp4diff (
.en(en_converters[4]),
.clk(clk),
.scale_diff(scale_diff_r),
.hdr(hdr_r),
.din(di[7:0]),
.pre_first_in(first_pixel),
.y_out (jp4diff_y_in[8:0]),
.yaddr (jp4diff_yaddrw[7:0]),
.ywe (jp4diff_ywe),
.pre_first_out(jp4diff_pre_first_out),
.bayer_phase(bayer_phase_r[1:0]));
//TODO: temporary plugs, until module is cretaed
// will be wrong, of course
assign conv20_y_in[7:0]= conv18_y_in[7:0];
assign conv20_yaddrw[7:0]= conv18_yaddrw[7:0];
assign conv20_ywe= conv18_ywe;
assign conv20_c_in[8:0]= conv18_c_in[8:0];
assign conv20_caddrw[6:0]= conv18_caddrw[6:0];
assign conv20_cwe= conv18_cwe;
assign conv20_pre_first_out= conv18_pre_first_out;
// currently only 8 bits are used in the memories
RAMB16_S9_S9 i_y_buff (
.DOA(), // Port A 8-bit Data Output
.DOPA(), // Port A 8-bit Parity Output
.ADDRA({1'b0,wpage[1:0],yaddrw[7:0]}), // Port A 11-bit Address Input
.CLKA(clk), // Port A Clock
.DIA(y_in[7:0]), // Port A 8-bit Data Input
.DIPA(y_in[8]), // Port A 1-bit parity Input
.ENA(ywe), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(y_out[7:0]), // Port B 8-bit Data Output
.DOPB(y_out[8]), // Port B 1-bit Parity Output
.ADDRB({1'b0,rpage[1:0],raddr[7:0]}), // Port B 11-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(8'h0), // Port B 8-bit Data Input
.DIPB(1'h0), // Port-B 1-bit parity Input
.ENB(!raddr[8]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
RAMB16_S9_S9 i_CrCb_buff (
.DOA(), // Port A 8-bit Data Output
.DOPA(), // Port A 8-bit Parity Output
.ADDRA({1'b0,wpage[1:0],caddrw[7:0]}), // Port A 11-bit Address Input
.CLKA(clk), // Port A Clock
.DIA(c_in[7:0]), // Port A 8-bit Data Input
.DIPA(c_in[8]), // Port A 1-bit parity Input
.ENA(cwe), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b1), // Port A Write Enable Input
.DOB(c_out[7:0]), // Port B 8-bit Data Output
.DOPB(c_out[8]), // Port B 1-bit Parity Output
.ADDRB({1'b0,rpage[1:0],raddr[7:0]}), // Port B 11-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(8'h0), // Port B 8-bit Data Input
.DIPB(1'h0), // Port-B 1-bit parity Input
.ENB(raddr[8]), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
|
module Counter_TV1 #(
parameter Width = 16
) (
(* intersynth_port = "Reset_n_i" *)
input Reset_n_i,
(* intersynth_port = "Clk_i" *)
input Clk_i,
(* intersynth_conntype = "Bit" *)
input ResetSig_i,
(* intersynth_conntype = "Bit" *)
input Preset_i,
(* intersynth_conntype = "Bit" *)
input Enable_i,
(* intersynth_conntype = "Bit" *)
input Direction_i,
(* intersynth_conntype = "Word" *)
input[Width-1:0] PresetVal_i,
(* intersynth_conntype = "Word" *)
output[Width-1:0] D_o,
(* intersynth_conntype = "Bit" *)
output Overflow_o,
(* intersynth_conntype = "Bit" *)
output Zero_o
);
reg [Width-1:0] Value;
reg Ovfl;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Value <= 'd0;
Ovfl <= 1'd0;
end
else
begin
if (ResetSig_i) begin
Value <= 'd0;
Ovfl <= 1'b0;
end else if (Preset_i) begin
Value <= PresetVal_i;
Ovfl <= 1'b0;
end else if (Enable_i)
begin
if (!Direction_i)
{Ovfl, Value} <= Value + 1'b1;
else
{Ovfl, Value} <= Value - 1'b1;
end
end
end
assign D_o = Value;
assign Zero_o = (Value == 0 ? 1'b1 : 1'b0);
assign Overflow_o = Ovfl;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_4_V
`define SKY130_FD_SC_LS__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSHOLD_PP_BLACKBOX_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold (
X ,
RESET,
VPWR ,
VGND ,
VPB ,
VNB
);
inout X ;
input RESET;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_TB_V
`define SKY130_FD_SC_HD__EDFXTP_TB_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__edfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__edfxtp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_TB_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:11:18 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 -prefix
// zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninja2 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/ninja2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/ninja2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/ninja2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_TB_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_TB_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlygate4sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_TB_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//usb_system_cpu_ociram_sp_ram, which is an nios_sp_ram
usb_system_cpu_ociram_sp_ram_module usb_system_cpu_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam usb_system_cpu_ociram_sp_ram.lpm_file = "usb_system_cpu_ociram_default_contents.dat";
`else
defparam usb_system_cpu_ociram_sp_ram.lpm_file = "usb_system_cpu_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam usb_system_cpu_ociram_sp_ram.lpm_file = "usb_system_cpu_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h08000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001d1d :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h08000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000001100000;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000001100000);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 26: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 28: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 28: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h8000020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 28: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//usb_system_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
usb_system_cpu_nios2_oci_td_mode usb_system_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
usb_system_cpu_nios2_oci_compute_input_tm_cnt the_usb_system_cpu_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
usb_system_cpu_nios2_oci_fifo_wrptr_inc the_usb_system_cpu_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
usb_system_cpu_nios2_oci_fifo_cnt_inc the_usb_system_cpu_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
usb_system_cpu_oci_test_bench the_usb_system_cpu_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifo_head[35 : 32]), fifo_head[31 : 0]} : itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 26: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
usb_system_cpu_nios2_oci_debug the_usb_system_cpu_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
usb_system_cpu_nios2_ocimem the_usb_system_cpu_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
usb_system_cpu_nios2_avalon_reg the_usb_system_cpu_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
usb_system_cpu_nios2_oci_break the_usb_system_cpu_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
usb_system_cpu_nios2_oci_xbrk the_usb_system_cpu_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
usb_system_cpu_nios2_oci_dbrk the_usb_system_cpu_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
usb_system_cpu_nios2_oci_itrace the_usb_system_cpu_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
usb_system_cpu_nios2_oci_dtrace the_usb_system_cpu_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
usb_system_cpu_nios2_oci_fifo the_usb_system_cpu_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
usb_system_cpu_nios2_oci_pib the_usb_system_cpu_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
usb_system_cpu_nios2_oci_im the_usb_system_cpu_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
usb_system_cpu_jtag_debug_module_wrapper the_usb_system_cpu_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 28: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 28: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 26: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 28: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_jmp_direct_pc_hi;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 26: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 26: 0] F_pc_no_crst_nxt;
wire [ 26: 0] F_pc_nxt;
wire [ 26: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 28: 0] F_pcb;
wire [ 28: 0] F_pcb_nxt;
wire [ 28: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 28: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 28: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 28: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_usb_system_cpu_test_bench, which is an e_instance
usb_system_cpu_test_bench the_usb_system_cpu_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000001100000;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 33554440 :
(F_pc_sel_nxt == 2'b01)? 71303688 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[28 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 33554432;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign F_jmp_direct_pc_hi = F_pc[26];
assign D_jmp_direct_target_waddr = {F_jmp_direct_pc_hi, D_iw[31 : 6]};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//usb_system_cpu_register_bank_a, which is an nios_sdp_ram
usb_system_cpu_register_bank_a_module usb_system_cpu_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam usb_system_cpu_register_bank_a.lpm_file = "usb_system_cpu_rf_ram_a.dat";
`else
defparam usb_system_cpu_register_bank_a.lpm_file = "usb_system_cpu_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam usb_system_cpu_register_bank_a.lpm_file = "usb_system_cpu_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//usb_system_cpu_register_bank_b, which is an nios_sdp_ram
usb_system_cpu_register_bank_b_module usb_system_cpu_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam usb_system_cpu_register_bank_b.lpm_file = "usb_system_cpu_rf_ram_b.dat";
`else
defparam usb_system_cpu_register_bank_b.lpm_file = "usb_system_cpu_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam usb_system_cpu_register_bank_b.lpm_file = "usb_system_cpu_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[28 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
W_cpuid_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[28 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000001100000;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000001100000;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
usb_system_cpu_nios2_oci the_usb_system_cpu_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_PP_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
wire pwrgood_pp0_out_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SLEEP_B, , KAPWR, VGND, VPWR);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_FUNCTIONAL_PP_V |
`define CYCLE_TIME 50
module TestBench;
reg Clk;
reg Reset;
reg Start;
integer i, outfile, counter;
always #(`CYCLE_TIME/2) Clk = ~Clk;
CPU CPU(
.clk_i (Clk),
.rst_i (Reset),
.start_i(Start)
);
initial begin
counter = 0;
// initialize instruction memory
for(i=0; i<128; i=i+1) begin
CPU.Instruction_Memory.memory[i] = 32'b0;
end
// initialize Register File
for(i=0; i<32; i=i+1) begin
CPU.Registers.register[i] = 32'b0;
end
// Load instructions into instruction memory
$readmemb("instruction.txt", CPU.Instruction_Memory.memory);
// Open output file
outfile = $fopen("output.txt") | 1;
Clk = 0;
Reset = 0;
Start = 0;
#(`CYCLE_TIME/4)
Reset = 1;
Start = 1;
end
always@(posedge Clk) begin
if(counter == 10) // stop after 30 cycles
$stop;
// print PC
#1
$fdisplay(outfile, "PC = %d", CPU.PC.pc_o);
// print Registers
$fdisplay(outfile, "Registers");
$fdisplay(outfile, "R0(r0) = %d, R8 (t0) = %d, R16(s0) = %d, R24(t8) = %d", CPU.Registers.register[0], CPU.Registers.register[8] , CPU.Registers.register[16], CPU.Registers.register[24]);
$fdisplay(outfile, "R1(at) = %d, R9 (t1) = %d, R17(s1) = %d, R25(t9) = %d", CPU.Registers.register[1], CPU.Registers.register[9] , CPU.Registers.register[17], CPU.Registers.register[25]);
$fdisplay(outfile, "R2(v0) = %d, R10(t2) = %d, R18(s2) = %d, R26(k0) = %d", CPU.Registers.register[2], CPU.Registers.register[10], CPU.Registers.register[18], CPU.Registers.register[26]);
$fdisplay(outfile, "R3(v1) = %d, R11(t3) = %d, R19(s3) = %d, R27(k1) = %d", CPU.Registers.register[3], CPU.Registers.register[11], CPU.Registers.register[19], CPU.Registers.register[27]);
$fdisplay(outfile, "R4(a0) = %d, R12(t4) = %d, R20(s4) = %d, R28(gp) = %d", CPU.Registers.register[4], CPU.Registers.register[12], CPU.Registers.register[20], CPU.Registers.register[28]);
$fdisplay(outfile, "R5(a1) = %d, R13(t5) = %d, R21(s5) = %d, R29(sp) = %d", CPU.Registers.register[5], CPU.Registers.register[13], CPU.Registers.register[21], CPU.Registers.register[29]);
$fdisplay(outfile, "R6(a2) = %d, R14(t6) = %d, R22(s6) = %d, R30(s8) = %d", CPU.Registers.register[6], CPU.Registers.register[14], CPU.Registers.register[22], CPU.Registers.register[30]);
$fdisplay(outfile, "R7(a3) = %d, R15(t7) = %d, R23(s7) = %d, R31(ra) = %d", CPU.Registers.register[7], CPU.Registers.register[15], CPU.Registers.register[23], CPU.Registers.register[31]);
$fdisplay(outfile, "\n");
counter = counter + 1;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_axi.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:04 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v4_0_ddr3_7Series, system_mig_7series_0_0, 2016.2" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v4_0,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=1, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=1, CLK_PERIOD=3000, PHY_RATIO=4, CLKIN_PERIOD=6000, VCCAUX_IO=1.8V, MEMORY_TYPE=COMP, MEMORY_PART=mt41k128m16xx-15e, DQ_WIDTH=16, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=LOW, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=1, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=NO_BUFFER}" *)
module mig_7series_v4_0_memc_ui_top_axi #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter SKIP_CALIB = "FALSE",
parameter TAPSPERKCLK = 56,
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 30,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// Instatiates register slices before upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN0[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Same as C_S_AXI_REG_EN0, but this register is after
// the upsizer
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
parameter FPGA_VOLT_TYPE = "N"
)
(
// Clock and reset ports
input clk,
input clk_div2,
input rst_div2,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_o,
output [2*nCK_PER_CLK-1:0] app_ecc_single_err,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// Ports to be used with SKIP_CALIB defined
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
input aresetn,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
// AXI CTRL port
input s_axi_ctrl_awvalid,
output s_axi_ctrl_awready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
// Slave Interface Write Data Ports
input s_axi_ctrl_wvalid,
output s_axi_ctrl_wready,
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
// Slave Interface Write Response Ports
output s_axi_ctrl_bvalid,
input s_axi_ctrl_bready,
output [1:0] s_axi_ctrl_bresp,
// Slave Interface Read Address Ports
input s_axi_ctrl_arvalid,
output s_axi_ctrl_arready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
// Slave Interface Read Data Ports
output s_axi_ctrl_rvalid,
input s_axi_ctrl_rready,
output [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
output [1:0] s_axi_ctrl_rresp,
// Interrupt output
output interrupt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output [1023:0] dbg_poc
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
localparam INTERFACE = "AXI4";
// Port Interface.
// # = UI - User Interface,
// = AXI4 - AXI4 Interface.
localparam C_FAMILY = "virtex7";
localparam C_MC_DATA_WIDTH_LCL = 2*nCK_PER_CLK*DATA_WIDTH ;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire app_correct_en;
wire app_correct_en_i;
wire [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_rd_data_to_axi;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_hi_pri;
wire app_sz;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_wdf_data_axi_o;
wire app_wdf_end;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire [C_MC_DATA_WIDTH_LCL/8-1:0] app_wdf_mask_axi_o;
wire app_wdf_wren;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
reg init_calib_complete_r;
//***************************************************************************
// Added a single register stage for the calib_done to fix timing
//***************************************************************************
always @(posedge clk)
init_calib_complete_r <= init_calib_complete;
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v4_0_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB (SKIP_CALIB),
.FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)
)
mem_intfc0
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
// skip calibration i/f
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.dbg_poc (dbg_poc[1023:0])
);
genvar o;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(o=0;o<8;o=o+1) begin
assign app_wdf_data[o*72+:72] = {app_wdf_data_axi_o[o*64+:8],app_wdf_data_axi_o[o*64+:64]} ;
assign app_wdf_mask[o*9+:9] = {app_wdf_mask_axi_o[o*8],app_wdf_mask_axi_o[o*8+:8]} ;
end
end else begin
end
end else begin
assign app_wdf_data = app_wdf_data_axi_o ;
assign app_wdf_mask = app_wdf_mask_axi_o ;
end
endgenerate
genvar e;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(e=0;e<8;e=e+1) begin
assign app_rd_data_to_axi[e*64+:64] = app_rd_data[e*72+:64];
end
end
end else begin
assign app_rd_data_to_axi = app_rd_data;
end
endgenerate
mig_7series_v4_0_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
// ECC ports
.app_raw_not_ecc (app_raw_not_ecc),
.app_ecc_multiple_err (app_ecc_multiple_err_o),
.app_ecc_single_err (app_ecc_single_err),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
mig_7series_v4_0_axi_mc #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_MC_DATA_WIDTH (C_MC_DATA_WIDTH_LCL),
.C_MC_ADDR_WIDTH (ADDR_WIDTH),
.C_MC_BURST_MODE (BURST_MODE),
.C_MC_nCK_PER_CLK (nCK_PER_CLK),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_ECC (ECC)
)
u_axi_mc
(
.aclk (clk),
.aresetn (aresetn),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// MC Master Interface
//CMD PORT
.mc_app_en (app_en),
.mc_app_cmd (app_cmd),
.mc_app_sz (app_sz),
.mc_app_addr (app_addr),
.mc_app_hi_pri (app_hi_pri),
.mc_app_rdy (app_rdy),
.mc_init_complete (init_calib_complete_r),
//DATA PORT
.mc_app_wdf_wren (app_wdf_wren),
.mc_app_wdf_mask (app_wdf_mask_axi_o),
.mc_app_wdf_data (app_wdf_data_axi_o),
.mc_app_wdf_end (app_wdf_end),
.mc_app_wdf_rdy (app_wdf_rdy),
.mc_app_rd_valid (app_rd_data_valid),
.mc_app_rd_data (app_rd_data_to_axi),
.mc_app_rd_end (app_rd_data_end),
.mc_app_ecc_multiple_err (app_ecc_multiple_err_o)
);
generate
if (ECC == "ON") begin : gen_axi_ctrl_top
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata_r;
mig_7series_v4_0_axi_ctrl_top #
(
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH) ,
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) ,
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH) ,
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR) ,
.C_ECC_TEST (ECC_TEST) ,
.C_DQ_WIDTH (DQ_WIDTH) ,
.C_ECC_WIDTH (ECC_WIDTH) ,
.C_MEM_ADDR_ORDER (MEM_ADDR_ORDER) ,
.C_BANK_WIDTH (BANK_WIDTH) ,
.C_ROW_WIDTH (ROW_WIDTH) ,
.C_COL_WIDTH (COL_WIDTH) ,
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE) ,
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH) ,
.C_NCK_PER_CLK (nCK_PER_CLK) ,
.C_MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH)
)
axi_ctrl_top_0
(
.aclk (clk) ,
.aresetn (aresetn) ,
.s_axi_awvalid (s_axi_ctrl_awvalid) ,
.s_axi_awready (s_axi_ctrl_awready) ,
.s_axi_awaddr (s_axi_ctrl_awaddr) ,
.s_axi_wvalid (s_axi_ctrl_wvalid) ,
.s_axi_wready (s_axi_ctrl_wready) ,
.s_axi_wdata (s_axi_ctrl_wdata) ,
.s_axi_bvalid (s_axi_ctrl_bvalid) ,
.s_axi_bready (s_axi_ctrl_bready) ,
.s_axi_bresp (s_axi_ctrl_bresp) ,
.s_axi_arvalid (s_axi_ctrl_arvalid) ,
.s_axi_arready (s_axi_ctrl_arready) ,
.s_axi_araddr (s_axi_ctrl_araddr) ,
.s_axi_rvalid (s_axi_ctrl_rvalid) ,
.s_axi_rready (s_axi_ctrl_rready) ,
.s_axi_rdata (s_axi_ctrl_rdata) ,
.s_axi_rresp (s_axi_ctrl_rresp) ,
.interrupt (interrupt) ,
.init_complete (init_calib_complete_r) ,
.ecc_single (ecc_single) ,
.ecc_multiple (ecc_multiple) ,
.ecc_err_addr (ecc_err_addr) ,
.app_correct_en (app_correct_en) ,
.dfi_rddata (dbg_rddata_r) ,
.fi_xor_we (fi_xor_we) ,
.fi_xor_wrdata (fi_xor_wrdata)
);
// dbg_rddata delayed one cycle to match ecc_*
always @(posedge clk) begin
dbg_rddata_r <= dbg_rddata;
end
//if(ECC_TEST == "ON") begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b1}};
// assign app_correct_en_i = 'b0 ;
//end else begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
// assign app_correct_en_i = app_correct_en ;
//end
assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
assign app_correct_en_i = app_correct_en ;
end
else begin : gen_no_axi_ctrl_top
assign s_axi_ctrl_awready = 1'b0;
assign s_axi_ctrl_wready = 1'b0;
assign s_axi_ctrl_bvalid = 1'b0;
assign s_axi_ctrl_bresp = 2'b0;
assign s_axi_ctrl_arready = 1'b0;
assign s_axi_ctrl_rvalid = 1'b0;
assign s_axi_ctrl_rdata = {C_S_AXI_CTRL_DATA_WIDTH{1'b0}};
assign s_axi_ctrl_rresp = 2'b0;
assign interrupt = 1'b0;
assign app_correct_en = 1'b1;
assign app_raw_not_ecc = 4'b0;
assign fi_xor_we = {DQ_WIDTH/8{1'b0}};
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}};
end
endgenerate
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module detector_tokens(
input rx_din,
input rx_sin,
input rx_resetn,
//input clock_sys,
//output reg rx_buffer_write,
output reg [13:0] info
);
wire rx_error;
reg rx_got_bit;
reg rx_got_null;
reg rx_got_nchar;
reg rx_got_time_code;
reg rx_got_fct;
wire [5:0] counter_neg;
reg [1:0] state_data_process;
reg [1:0] next_state_data_process;
reg control_bit_found;
wire posedge_clk;
wire negedge_clk;
wire bit_c_0;//N
wire bit_c_1;//P
wire bit_c_2;//N
wire bit_c_3;//P
wire bit_c_ex;//P
wire bit_d_0;//N
wire bit_d_1;//P
wire bit_d_2;//N
wire bit_d_3;//P
wire bit_d_4;//N
wire bit_d_5;//P
wire bit_d_6;//N
wire bit_d_7;//P
wire bit_d_8;//N
wire bit_d_9;//P
wire is_control;
reg is_data;
reg last_is_control;
reg last_is_data;
//reg last_is_timec;
reg last_was_control;
reg last_was_data;
reg last_was_timec;
reg [3:0] control;
reg [3:0] control_r;
reg [3:0] control_p_r;
reg [9:0] data;
reg [9:0] timecode;
reg [9:0] dta_timec;
reg [9:0] dta_timec_p;
reg [3:0] control_l_r;
reg [9:0] data_l_r;
reg parity_rec_c;
reg parity_rec_d;
reg rx_error_c;
reg rx_error_d;
reg ready_control;
reg ready_data;
reg parity_rec_c_gen;
reg parity_rec_d_gen;
reg ready_control_p;
reg ready_data_p;
reg ready_control_p_r;
reg ready_data_p_r;
wire posedge_p;
reg f_time;
//CLOCK RECOVERY
assign posedge_clk = posedge_p;
assign negedge_clk = (f_time)?!posedge_p:1'b0;
assign rx_error = rx_error_c | rx_error_d;
buf (posedge_p,rx_din ^ rx_sin);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
f_time <= 1'b0;
end
else
begin
f_time <= 1'b1;
end
end
always@(*)
begin
rx_got_bit = 1'b0;
if(rx_din | rx_sin)
begin
rx_got_bit = 1'b1;
end
end
always@(*)
begin
ready_control = 1'b0;
ready_data = 1'b0;
if(is_control && counter_neg[5:0] == 6'd4 && !posedge_p)
begin
ready_control = 1'b1;
ready_data = 1'b0;
end
else if(is_control && counter_neg[5:0] == 6'd32 && !posedge_p)
begin
ready_control = 1'b0;
ready_data = 1'b1;
end
end
bit_capture_data capture_d(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_d_0(bit_d_0),//N
.bit_d_1(bit_d_1),//P
.bit_d_2(bit_d_2),//N
.bit_d_3(bit_d_3),//P
.bit_d_4(bit_d_4),//N
.bit_d_5(bit_d_5),//P
.bit_d_6(bit_d_6),//N
.bit_d_7(bit_d_7),//P
.bit_d_8(bit_d_8),//N
.bit_d_9(bit_d_9)//P
);
bit_capture_control capture_c(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_c_0(bit_c_0),
.bit_c_1(bit_c_1),
.bit_c_2(bit_c_2),
.bit_c_3(bit_c_3)
);
counter_neg cnt_neg(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.is_control(is_control),
.counter_neg(counter_neg)
);
always@(*)
begin
next_state_data_process = state_data_process;
case(state_data_process)
2'd0:
begin
if(ready_control_p_r || ready_data_p_r)
begin
next_state_data_process = 2'd1;
end
else
begin
next_state_data_process = 2'd0;
end
end
2'd1:
begin
next_state_data_process = 2'd0;
end
default:
begin
next_state_data_process = 2'd0;
end
endcase
end
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
rx_got_fct <= 1'b0;
end
else
begin
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)
begin
rx_got_fct <= 1'b1;
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
else if(control[2:0] != 3'd7 && last_is_data)
begin
rx_got_nchar <= 1'b1;
rx_got_null <= 1'b0;
rx_got_time_code <= 1'b0;
rx_got_fct <= 1'b0;
end
else if(control[2:0] == 3'd7 && last_is_data)
begin
rx_got_time_code <= 1'b1;
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_fct <= 1'b0;
end
else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)
begin
rx_got_null <= 1'b1;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
rx_got_fct <= 1'b0;
end
else
begin
rx_got_null <= rx_got_null;
rx_got_nchar <= rx_got_nchar;
rx_got_time_code <= rx_got_time_code;
rx_got_fct <= rx_got_fct;
end
end
end
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
end
else
begin
if(counter_neg[5:0] == 6'd4 && is_control)
begin
ready_control_p_r <= 1'b1;
end
else if(counter_neg[5:0] == 6'd32)
begin
ready_data_p_r <= 1'b1;
end
else
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
end
end
end
always@(posedge posedge_clk or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_r <= 4'd0;
parity_rec_c <= 1'b0;
parity_rec_c_gen <= 1'b0;
end
else
begin
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
parity_rec_c <= bit_c_3;
if(last_is_control)
begin
parity_rec_c_gen <= !(bit_c_2^control[0]^control[1]);
end
else if(last_is_data)
begin
parity_rec_c_gen <= !(bit_c_2^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
end
end
end
always@(posedge posedge_clk or negedge rx_resetn )
begin
if(!rx_resetn)
begin
dta_timec <= 10'd0;
parity_rec_d <= 1'b0;
parity_rec_d_gen <= 1'b0;
end
else
begin
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
parity_rec_d <= bit_d_9;
if(last_is_control)
begin
parity_rec_d_gen <= !(bit_d_8^control[0]^control[1]);
end
else if(last_is_data)
begin
parity_rec_d_gen <= !(bit_d_8^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
end
end
end
always@(posedge posedge_clk or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_l_r <= 4'd0;
control <= 4'd0;
data <= 10'd0;
last_is_control <= 1'b0;
last_is_data <= 1'b0;
//last_is_timec <= 1'b0;
state_data_process <= 2'd0;
info <= 14'd0;
rx_error_c <= 1'b0;
rx_error_d <= 1'b0;
end
else
begin
state_data_process <= next_state_data_process;
case(state_data_process)
2'd0:
begin
if(ready_control_p_r)
begin
control <= control_p_r;
control_l_r <= control;
last_is_control <= 1'b1;
last_is_data <= 1'b0;
//last_is_timec <= 1'b0;
end
else if(ready_data_p_r)
begin
if(control[2:0] != 3'd7)
begin
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <=1'b0;
last_is_data <=1'b1;
//last_is_timec <=1'b0;
end
else if(control[2:0] == 3'd7)
begin
last_is_control <= 1'b0;
last_is_data <= 1'b0;
//last_is_timec <= 1'b1;
end
end
else
begin
end
end
2'd1:
begin
if(ready_control_p_r)
begin
if(parity_rec_c_gen != parity_rec_c)
begin
rx_error_c <= 1'b1;
end
else
rx_error_c <= rx_error_c;
end
else if(ready_data_p_r)
begin
if(parity_rec_d_gen != parity_rec_d)
begin
rx_error_d <= 1'b1;
end
else
rx_error_d <= rx_error_d;
end
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
end
default:
begin
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave_b2b
* this module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b
#(parameter start_cnt = 1)
(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
reg [7:0] first_byte;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1] == 2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1] == 2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
* read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge) begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
if((bytecnt == 'h0 && byte_data_received == start_cnt + 1'b1) || first_byte == start_cnt + 1'b1)
received_memory <= (byte_data_received == bytecnt + start_cnt + 1'b1) ? (received_memory + 1'b1) : received_memory;
else
received_memory <= (byte_data_received == bytecnt + start_cnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
first_byte <= 'h0;
else if(bytecnt == 'h0 && byte_data_received == start_cnt + 1'b1)
first_byte <= byte_data_received;
else
first_byte <= first_byte;
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= start_cnt;
else begin
if((first_byte == start_cnt + 1'b1) && (!recived_status))
cnt<= start_cnt + 1'b1;
else if(byte_received && recived_status)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule |
module uart(
input clk,
input rst,
// uart lines
input hwrx,
output hwtx,
// bus interface
input addr, // 2 registers
input we,
input re,
input [31:0] wdata,
output reg [31:0] rdata,
// latch char on rising edge if dosend set
// input [7:0] txchar,
// input dosend,
// rx
output reg [7:0] rxchar,
output reg rxvalid
);
initial begin
end
// 24000000 / (115200) == 208.3333
`define BAUD_DIV 208
// tx
reg [7:0] txclkdiv;
reg [9:0] txshift;
reg [3:0] txcount;
assign hwtx = txshift[0];
reg txdone;
always @ (posedge clk)
begin
if (rst)
begin
txdone <= 1;
txcount <= 0;
txshift <= 1;
txclkdiv <= 0;
end else if (we && txdone) begin
// start the tx process
txshift[0] <= 0; // start bit
txshift[8:1] <= wdata[7:0];
txshift[9] <= 1; // stop bit
txcount <= 9;
// start bit
txclkdiv <= `BAUD_DIV;
txdone <= 0;
end else if (!txdone) begin
// keep shifting bits out
if (txclkdiv == 0) begin
txshift <= txshift >> 1;
txclkdiv <= `BAUD_DIV;
if (txcount == 0) begin
// terminating condition
txdone <= 1;
end else begin
txcount <= txcount - 1;
end
end else begin
txclkdiv <= txclkdiv - 1;
end
end
end
always @(posedge clk)
begin
if (re) begin
rdata <= txdone;
end else begin
rdata <= 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
end
end
// XXX rx is disabled for now
initial begin
rxvalid <= 0;
rxchar <= 0;
end
/*
// rx
reg [7:0] rxshift;
reg [3:0] rxclkdiv;
integer rxcount;
always @ (posedge clk)
begin
if (rst)
begin
rxchar <= 0;
rxvalid <= 0;
rxcount <= 0;
rxclkdiv <= 0;
end
else
begin
// rx state machine
if (rxcount == 0) begin
if (hwrx == 0) begin
// possible start bit
rxcount <= 1;
rxclkdiv <= 1;
rxshift <= 0;
end
end else begin
if (rxclkdiv == 8) begin
if (rxcount >= 1 && rxcount <= 9) begin // rxcount > 0
// data bits
rxshift[7:1] <= rxshift[6:0];
rxshift[0] <= hwrx;
rxcount <= rxcount + 1;
end else if (rxcount == 10) begin
// stop bit
if (hwrx == 1) begin
// it's valid
$display("what");
rxchar <= rxshift;
rxvalid <= 1;
end else begin
// reject it
rxcount <= 0;
rxvalid <= 0;
end
end
end
rxclkdiv <= rxclkdiv + 1;
end
end
end
*/
endmodule // uart
|
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/extadc.v:1" *)
module ExtADC(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, SensorPower_o, SensorStart_o, SensorReady_i, AdcStart_o, AdcDone_i, AdcValue_i, PeriodCounterPreset_i, SensorValue_o, Threshold_i);
(* src = "../../verilog/extadc.v:142" *)
wire [15:0] \$0\Timer[15:0] ;
(* src = "../../verilog/extadc.v:169" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire [2:0] \$2\NextState[2:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$2\SensorPower_o[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$2\StoreNewValue[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$2\TimerPreset[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire [2:0] \$3\NextState[2:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$3\TimerEnable[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$3\TimerPreset[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire [2:0] \$4\NextState[2:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$4\TimerEnable[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire [2:0] \$5\NextState[2:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire [2:0] \$6\NextState[2:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire [2:0] \$7\NextState[2:0] ;
wire \$procmux$190_CMP ;
wire \$procmux$193_CMP ;
wire \$procmux$194_CMP ;
wire \$procmux$199_CMP ;
wire \$procmux$202_CMP ;
wire [15:0] \$procmux$23_Y ;
(* src = "../../verilog/extadc.v:156" *)
wire [15:0] \$sub$../../verilog/extadc.v:156$12_Y ;
(* src = "../../verilog/extadc.v:167" *)
wire [15:0] AbsDiffResult;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "AdcConvComplete_i" *)
(* src = "../../verilog/extadc.v:19" *)
input AdcDone_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "AdcDoConvert_o" *)
(* src = "../../verilog/extadc.v:17" *)
output AdcStart_o;
(* intersynth_conntype = "Word" *)
(* intersynth_port = "AdcValue_i" *)
(* src = "../../verilog/extadc.v:21" *)
input [15:0] AdcValue_i;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/extadc.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/extadc.v:9" *)
output CpuIntr_o;
(* src = "../../verilog/extadc.v:184" *)
wire [16:0] DiffAB;
(* src = "../../verilog/extadc.v:185" *)
wire [15:0] DiffBA;
(* src = "../../verilog/extadc.v:42" *)
wire DiffTooLarge;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/extadc.v:7" *)
input Enable_i;
(* src = "../../verilog/extadc.v:38" *)
wire [2:0] NextState;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPreset_i" *)
(* src = "../../verilog/extadc.v:23" *)
input [15:0] PeriodCounterPreset_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/extadc.v:3" *)
input Reset_n_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/extadc.v:11" *)
output SensorPower_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Inputs_i" *)
(* src = "../../verilog/extadc.v:15" *)
input SensorReady_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/extadc.v:13" *)
output SensorStart_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/extadc.v:25" *)
output [15:0] SensorValue_o;
(* src = "../../verilog/extadc.v:37" *)
wire [2:0] State;
(* src = "../../verilog/extadc.v:43" *)
wire StoreNewValue;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/extadc.v:27" *)
input [15:0] Threshold_i;
(* src = "../../verilog/extadc.v:140" *)
wire [15:0] Timer;
(* src = "../../verilog/extadc.v:41" *)
wire TimerEnable;
(* src = "../../verilog/extadc.v:39" *)
wire TimerOvfl;
(* src = "../../verilog/extadc.v:40" *)
wire TimerPreset;
(* src = "../../verilog/extadc.v:166" *)
wire [15:0] Word0;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$710 (
.A({ \$procmux$194_CMP , \$procmux$193_CMP , \$procmux$190_CMP }),
.Y(SensorStart_o)
);
(* src = "../../verilog/extadc.v:161" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/extadc.v:161$13 (
.A(Timer),
.B(16'b0000000000000000),
.Y(TimerOvfl)
);
(* src = "../../verilog/extadc.v:190" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/extadc.v:190$20 (
.A(AbsDiffResult),
.B(Threshold_i),
.Y(DiffTooLarge)
);
(* src = "../../verilog/extadc.v:142" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$706 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Timer[15:0] ),
.Q(Timer)
);
(* src = "../../verilog/extadc.v:169" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$707 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
(* src = "../../verilog/extadc.v:45" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(3'b000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000000011)
) \$procdff$708 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(NextState),
.Q(State)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$189 (
.A(1'b0),
.B({ SensorReady_i, 1'b1 }),
.S({ \$procmux$193_CMP , \$procmux$190_CMP }),
.Y(AdcStart_o)
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$190_CMP0 (
.A(State),
.B(3'b100),
.Y(\$procmux$190_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$193_CMP0 (
.A(State),
.B(3'b011),
.Y(\$procmux$193_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$194_CMP0 (
.A(State),
.B(3'b010),
.Y(\$procmux$194_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$199_CMP0 (
.A(State),
.B(3'b001),
.Y(\$procmux$199_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$202_CMP0 (
.A(State),
.B(3'b000),
.Y(\$procmux$202_CMP )
);
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$205_CMP0 (
.A(State),
.B(3'b101),
.Y(CpuIntr_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$229 (
.A(1'b0),
.B({ \$2\SensorPower_o[0:0] , 1'b1 }),
.S({ \$procmux$199_CMP , SensorStart_o }),
.Y(SensorPower_o)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$23 (
.A(Timer),
.B(\$sub$../../verilog/extadc.v:156$12_Y ),
.S(TimerEnable),
.Y(\$procmux$23_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$26 (
.A(\$procmux$23_Y ),
.B(PeriodCounterPreset_i),
.S(TimerPreset),
.Y(\$0\Timer[15:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$269 (
.A(\$procmux$190_CMP ),
.B(\$2\StoreNewValue[0:0] ),
.Y(StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000110),
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$284 (
.A(State),
.B({ \$2\NextState[2:0] , \$3\NextState[2:0] , 3'b011, \$5\NextState[2:0] , \$6\NextState[2:0] , 3'b001 }),
.S({ \$procmux$202_CMP , \$procmux$199_CMP , \$procmux$194_CMP , \$procmux$193_CMP , \$procmux$190_CMP , CpuIntr_o }),
.Y(NextState)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$29 (
.A(Word0),
.B(AdcValue_i),
.S(StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$318 (
.A(1'b0),
.B({ Enable_i, \$3\TimerEnable[0:0] }),
.S({ \$procmux$202_CMP , \$procmux$199_CMP }),
.Y(TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$338 (
.A(1'b1),
.B({ \$2\TimerPreset[0:0] , \$3\TimerPreset[0:0] }),
.S({ \$procmux$202_CMP , \$procmux$199_CMP }),
.Y(TimerPreset)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$360 (
.A(State),
.B(3'b001),
.S(Enable_i),
.Y(\$2\NextState[2:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$381 (
.A(Enable_i),
.Y(\$2\TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$420 (
.A(Enable_i),
.B(TimerOvfl),
.Y(\$2\SensorPower_o[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$441 (
.A(Enable_i),
.B(\$4\TimerEnable[0:0] ),
.Y(\$3\TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$462 (
.A(1'b1),
.B(TimerOvfl),
.S(Enable_i),
.Y(\$3\TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$483 (
.A(3'b000),
.B(\$4\NextState[2:0] ),
.S(Enable_i),
.Y(\$3\NextState[2:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$502 (
.A(TimerOvfl),
.Y(\$4\TimerEnable[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$546 (
.A(State),
.B(3'b010),
.S(TimerOvfl),
.Y(\$4\NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$586 (
.A(State),
.B(3'b100),
.S(SensorReady_i),
.Y(\$5\NextState[2:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$625 (
.A(State),
.B(\$7\NextState[2:0] ),
.S(AdcDone_i),
.Y(\$6\NextState[2:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$646 (
.A(AdcDone_i),
.B(DiffTooLarge),
.Y(\$2\StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000011)
) \$procmux$666 (
.A(3'b001),
.B(3'b101),
.S(DiffTooLarge),
.Y(\$7\NextState[2:0] )
);
(* src = "../../verilog/extadc.v:156" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/extadc.v:156$12 (
.A(Timer),
.B(1'b1),
.Y(\$sub$../../verilog/extadc.v:156$12_Y )
);
(* src = "../../verilog/extadc.v:186" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/extadc.v:186$17 (
.A({ 1'b0, AdcValue_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/extadc.v:187" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/extadc.v:187$18 (
.A(Word0),
.B(AdcValue_i),
.Y(DiffBA)
);
(* src = "../../verilog/extadc.v:188" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/extadc.v:188$19 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue_o = Word0;
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
`resetall
|
`include "constants.vh"
module ram_sync_2r1w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
output reg [BRAM_DATA_WIDTH-1:0] rdata2,
input [BRAM_ADDR_WIDTH-1:0] waddr,
input [BRAM_DATA_WIDTH-1:0] wdata,
input we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
rdata2 <= mem[raddr2];
if (we)
mem[waddr] <= wdata;
end
endmodule // ram_sync_2r1w
module ram_sync_2r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
output reg [BRAM_DATA_WIDTH-1:0] rdata1,
output reg [BRAM_DATA_WIDTH-1:0] rdata2,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
always @ (posedge clk) begin
rdata1 <= mem[raddr1];
rdata2 <= mem[raddr2];
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule // ram_sync_2r2w
module ram_sync_4r1w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input [BRAM_ADDR_WIDTH-1:0] waddr,
input [BRAM_DATA_WIDTH-1:0] wdata,
input we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
ram_sync_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
endmodule // ram_sync_4r1w
module ram_sync_4r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_4r2w
module ram_sync_6r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
input [BRAM_ADDR_WIDTH-1:0] raddr5,
input [BRAM_ADDR_WIDTH-1:0] raddr6,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
output wire [BRAM_DATA_WIDTH-1:0] rdata5,
output wire [BRAM_DATA_WIDTH-1:0] rdata6,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem2(
.clk(clk),
.raddr1(raddr5),
.raddr2(raddr6),
.rdata1(rdata5),
.rdata2(rdata6),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_6r2w
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_deframer(
input sys_clk,
input sys_rst,
/* to transceiver */
input up_stb,
output up_ack,
input up_sync,
input up_data,
/* frame data */
input en,
output reg next_frame,
output reg frame_valid,
output reg addr_valid,
output reg [19:0] addr,
output reg data_valid,
output reg [19:0] data,
output reg pcmleft_valid,
output reg [19:0] pcmleft,
output reg pcmright_valid,
output reg [19:0] pcmright
);
reg [7:0] bitcounter;
reg sync_old;
always @(posedge sys_clk) begin
if(sys_rst) begin
bitcounter <= 8'd253;
next_frame <= 1'b0;
sync_old <= 1'b0;
end else begin
if(en)
next_frame <= 1'b0;
if(up_stb & en) begin
case(bitcounter)
8'd0: frame_valid <= up_data; // Frame valid
8'd1: addr_valid <= up_data; // Slot 1 valid
8'd2: data_valid <= up_data; // Slot 2 valid
8'd3: pcmleft_valid <= up_data; // Slot 3 valid
8'd4: pcmright_valid <= up_data; // Slot 4 valid
8'd16: addr[19] <= up_data;
8'd17: addr[18] <= up_data;
8'd18: addr[17] <= up_data;
8'd19: addr[16] <= up_data;
8'd20: addr[15] <= up_data;
8'd21: addr[14] <= up_data;
8'd22: addr[13] <= up_data;
8'd23: addr[12] <= up_data;
8'd24: addr[11] <= up_data;
8'd25: addr[10] <= up_data;
8'd26: addr[9] <= up_data;
8'd27: addr[8] <= up_data;
8'd28: addr[7] <= up_data;
8'd29: addr[6] <= up_data;
8'd30: addr[5] <= up_data;
8'd31: addr[4] <= up_data;
8'd32: addr[3] <= up_data;
8'd33: addr[2] <= up_data;
8'd34: addr[1] <= up_data;
8'd35: addr[0] <= up_data;
8'd36: data[19] <= up_data;
8'd37: data[18] <= up_data;
8'd38: data[17] <= up_data;
8'd39: data[16] <= up_data;
8'd40: data[15] <= up_data;
8'd41: data[14] <= up_data;
8'd42: data[13] <= up_data;
8'd43: data[12] <= up_data;
8'd44: data[11] <= up_data;
8'd45: data[10] <= up_data;
8'd46: data[9] <= up_data;
8'd47: data[8] <= up_data;
8'd48: data[7] <= up_data;
8'd49: data[6] <= up_data;
8'd50: data[5] <= up_data;
8'd51: data[4] <= up_data;
8'd52: data[3] <= up_data;
8'd53: data[2] <= up_data;
8'd54: data[1] <= up_data;
8'd55: data[0] <= up_data;
8'd56: pcmleft[19] <= up_data;
8'd57: pcmleft[18] <= up_data;
8'd58: pcmleft[17] <= up_data;
8'd59: pcmleft[16] <= up_data;
8'd60: pcmleft[15] <= up_data;
8'd61: pcmleft[14] <= up_data;
8'd62: pcmleft[13] <= up_data;
8'd63: pcmleft[12] <= up_data;
8'd64: pcmleft[11] <= up_data;
8'd65: pcmleft[10] <= up_data;
8'd66: pcmleft[9] <= up_data;
8'd67: pcmleft[8] <= up_data;
8'd68: pcmleft[7] <= up_data;
8'd69: pcmleft[6] <= up_data;
8'd70: pcmleft[5] <= up_data;
8'd71: pcmleft[4] <= up_data;
8'd72: pcmleft[3] <= up_data;
8'd73: pcmleft[2] <= up_data;
8'd74: pcmleft[1] <= up_data;
8'd75: pcmleft[0] <= up_data;
8'd76: pcmright[19] <= up_data;
8'd77: pcmright[18] <= up_data;
8'd78: pcmright[17] <= up_data;
8'd79: pcmright[16] <= up_data;
8'd80: pcmright[15] <= up_data;
8'd81: pcmright[14] <= up_data;
8'd82: pcmright[13] <= up_data;
8'd83: pcmright[12] <= up_data;
8'd84: pcmright[11] <= up_data;
8'd85: pcmright[10] <= up_data;
8'd86: pcmright[9] <= up_data;
8'd87: pcmright[8] <= up_data;
8'd88: pcmright[7] <= up_data;
8'd89: pcmright[6] <= up_data;
8'd90: pcmright[5] <= up_data;
8'd91: pcmright[4] <= up_data;
8'd92: pcmright[3] <= up_data;
8'd93: pcmright[2] <= up_data;
8'd94: pcmright[1] <= up_data;
8'd95: pcmright[0] <= up_data;
endcase
if(bitcounter == 8'd95)
next_frame <= 1'b1;
sync_old <= up_sync;
if(up_sync & ~sync_old)
bitcounter <= 8'd0;
else
bitcounter <= bitcounter + 8'd1;
end
end
end
assign up_ack = en;
endmodule
|
`include "config.inc"
module gamma(
input clock,
input [4:0] gamma_config,
input [7:0] in,
output reg [7:0] out
);
always @(posedge clock) begin
case (gamma_config)
`GAMMA_0_714290: begin
case (in)
`include "config/gamma_0_714290.v"
endcase
end
`GAMMA_0_769231: begin
case (in)
`include "config/gamma_0_769231.v"
endcase
end
`GAMMA_0_833330: begin
case (in)
`include "config/gamma_0_833330.v"
endcase
end
`GAMMA_0_909090: begin
case (in)
`include "config/gamma_0_909090.v"
endcase
end
`GAMMA_1_1: begin
case (in)
`include "config/gamma_1_1.v"
endcase
end
`GAMMA_1_2: begin
case (in)
`include "config/gamma_1_2.v"
endcase
end
`GAMMA_1_3: begin
case (in)
`include "config/gamma_1_3.v"
endcase
end
`GAMMA_1_4: begin
case (in)
`include "config/gamma_1_4.v"
endcase
end
default: out <= in;
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Thu Aug 25 17:34:14 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/8-way/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_UTIL
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_address_range_check (
address,
is_addr_within_valid_range
);
parameter FLASH_ADDR_WIDTH = 23;
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output is_addr_within_valid_range;
assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
endmodule
module altera_onchip_flash_address_write_protection_check (
use_sector_addr,
address,
write_protection_mode,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
input use_sector_addr;
input [FLASH_ADDR_WIDTH-1:0] address;
input [4:0] write_protection_mode;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
wire is_sector1_writable;
wire is_sector2_writable;
wire is_sector3_writable;
wire is_sector4_writable;
wire is_sector5_writable;
assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_s_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
input [2:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = (address == 1);
assign is_sector2_addr = (address == 2);
assign is_sector3_addr = (address == 3);
assign is_sector4_addr = (address == 4);
assign is_sector5_addr = (address == 5);
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_a_address_write_protection_check (
address,
is_sector1_writable,
is_sector2_writable,
is_sector3_writable,
is_sector4_writable,
is_sector5_writable,
is_addr_writable
);
parameter FLASH_ADDR_WIDTH = 23;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
input is_sector1_writable;
input is_sector2_writable;
input is_sector3_writable;
input is_sector4_writable;
input is_sector5_writable;
output is_addr_writable;
wire is_sector1_addr;
wire is_sector2_addr;
wire is_sector3_addr;
wire is_sector4_addr;
wire is_sector5_addr;
assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
(is_sector2_writable && is_sector2_addr) ||
(is_sector3_writable && is_sector3_addr) ||
(is_sector4_writable && is_sector4_addr) ||
(is_sector5_writable && is_sector5_addr));
endmodule
module altera_onchip_flash_convert_address (
address,
flash_addr
);
parameter FLASH_ADDR_WIDTH = 23;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE2_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
parameter ADDR_RANGE3_OFFSET = 1;
input [FLASH_ADDR_WIDTH-1:0] address;
output [FLASH_ADDR_WIDTH-1:0] flash_addr;
assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address <= ADDR_RANGE2_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
(address + ADDR_RANGE3_OFFSET[FLASH_ADDR_WIDTH-1:0]);
endmodule
module altera_onchip_flash_convert_sector (
sector,
flash_sector
);
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
input [2:0] sector;
output [2:0] flash_sector;
assign flash_sector =
(sector == 1) ? SECTOR1_MAP[2:0] :
(sector == 2) ? SECTOR2_MAP[2:0] :
(sector == 3) ? SECTOR3_MAP[2:0] :
(sector == 4) ? SECTOR4_MAP[2:0] :
(sector == 5) ? SECTOR5_MAP[2:0] :
3'd0; // Set to 0 for invalid sector ID
endmodule
module altera_onchip_flash_counter (
clock,
reset,
count
);
input clock;
input reset;
output [4:0] count;
reg [4:0] count_reg;
assign count = count_reg;
initial begin
count_reg = 0;
end
always @ (posedge reset or posedge clock) begin
if (reset) begin
count_reg <= 0;
end
else begin
count_reg <= count_reg + 5'd1;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
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