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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_SYMBOL_V
`define SKY130_FD_SC_LS__A31OI_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/17/2017 08:53:01 PM
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb();
reg CLOCK_50;
reg rst;
wire vsync;
wire[11:0] color_out;
wire[7:0] seg_out;
wire[3:0] sel;
wire hsync;
//integer file_output;
initial begin
//file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = 1'b1;
#195 rst= 1'b0;
#1000000000 $stop;
end
top_greedy_snake top_greedy_snake1(
.clk(CLOCK_50),
.rst(rst),
.left(0),
.right(0),
.up(0),
.down(0),
.hsync(hsync),
.vsync(vsync),
.color_out(color_out),
.seg_out(seg_out),
.sel(sel)
);
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream asynchronous FIFO
*/
module axis_async_fifo #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
wire write = input_axis_tvalid & ~full;
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
assign input_axis_tready = ~full;
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
end else if (write) begin
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_next = wr_ptr + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {{{32- 8}{1'b0}},read_mux_out};
assign out_port = data_out;
endmodule
|
module conway #(
parameter WIDTH = 32,
parameter HEIGHT = 32
)(
in_states,
out_states
);
input [WIDTH*HEIGHT-1:0] in_states;
output [WIDTH*HEIGHT-1:0] out_states;
genvar r, c;
generate
for (c = 0; c < WIDTH; c=c+1) begin
assign out_states[c] = 0;
assign out_states[(HEIGHT-1)*WIDTH + c] = 0;
end
for (r = 1; r < HEIGHT-1; r=r+1) begin
assign out_states[r * WIDTH] = 0;
assign out_states[(r + 1) * WIDTH - 1] = 0;
for (c = 1; c < WIDTH-1; c=c+1) begin
wire cur_state_i;
wire [4:0] sum_i;
assign cur_state_i = in_states[r * WIDTH + c];
assign sum_i = in_states[r * WIDTH + c-WIDTH-1] + in_states[r * WIDTH + c-WIDTH] + in_states[r * WIDTH + c-WIDTH+1] + in_states[r * WIDTH + c-1] + in_states[r * WIDTH + c+1] + in_states[r * WIDTH + c+WIDTH-1] + in_states[r * WIDTH + c+WIDTH] + in_states[r * WIDTH + c+WIDTH+1];
wire eq2_i, eq3_i;
assign eq2_i = (sum_i == 2);
assign eq3_i = (sum_i == 3);
wire next_state_i;
assign next_state_i = (cur_state_i & (eq2_i | eq3_i)) | (~cur_state_i & eq3_i);
assign out_states[r * WIDTH + c] = next_state_i;
end
end
endgenerate
endmodule |
// megafunction wizard: %DDR3 High Performance Controller v11.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// ddr3_int_controller_phy
// ============================================================
// Generated by DDR3 High Performance Controller 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2012 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
dll_reference_clk,
dqs_delay_ctrl_export,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
mem_reset_n,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [23:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [255:0] local_wdata;
input [31:0] local_be;
input [4:0] local_size;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [255:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [7:0] mem_dm;
output mem_reset_n;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [63:0] mem_dq;
inout [7:0] mem_dqs;
inout [7:0] mem_dqsn;
wire signal_wire0 = 1'b0;
wire [13:0] signal_wire1 = 14'b0;
wire [13:0] signal_wire2 = 14'b0;
wire [5:0] signal_wire3 = 6'b0;
wire [5:0] signal_wire4 = 6'b0;
wire signal_wire5 = 1'b0;
wire [63:0] signal_wire6 = 64'b0;
wire [7:0] signal_wire7 = 8'b0;
wire [7:0] signal_wire8 = 8'b0;
wire [7:0] signal_wire9 = 8'b0;
wire [7:0] signal_wire10 = 8'b0;
wire [7:0] signal_wire11 = 8'b0;
wire signal_wire12 = 1'b0;
wire signal_wire13 = 1'b0;
wire signal_wire14 = 1'b0;
wire signal_wire15 = 1'b0;
wire [3:0] signal_wire16 = 4'b0;
wire [2:0] signal_wire17 = 3'b0;
wire signal_wire18 = 1'b0;
wire [8:0] signal_wire19 = 9'b0;
wire [3:0] signal_wire20 = 4'b0;
wire signal_wire21 = 1'b0;
wire signal_wire22 = 1'b0;
wire signal_wire23 = 1'b0;
wire signal_wire24 = 1'b0;
wire signal_wire25 = 1'b0;
wire signal_wire26 = 1'b0;
wire signal_wire27 = 1'b0;
wire signal_wire28 = 1'b0;
ddr3_int_controller_phy ddr3_int_controller_phy_inst(
.local_address(local_address),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_burstbegin(local_burstbegin),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_refresh_req(signal_wire0),
.oct_ctl_rs_value(signal_wire1),
.oct_ctl_rt_value(signal_wire2),
.dqs_delay_ctrl_import(signal_wire3),
.dqs_offset_delay_ctrl(signal_wire4),
.hc_scan_enable_access(signal_wire5),
.hc_scan_enable_dq(signal_wire6),
.hc_scan_enable_dm(signal_wire7),
.hc_scan_enable_dqs(signal_wire8),
.hc_scan_enable_dqs_config(signal_wire9),
.hc_scan_din(signal_wire10),
.hc_scan_update(signal_wire11),
.hc_scan_ck(signal_wire12),
.pll_reconfig_write_param(signal_wire13),
.pll_reconfig_read_param(signal_wire14),
.pll_reconfig(signal_wire15),
.pll_reconfig_counter_type(signal_wire16),
.pll_reconfig_counter_param(signal_wire17),
.pll_reconfig_soft_reset_en_n(signal_wire18),
.pll_reconfig_data_in(signal_wire19),
.pll_phasecounterselect(signal_wire20),
.pll_phaseupdown(signal_wire21),
.pll_phasestep(signal_wire22),
.pll_reconfig_enable(signal_wire23),
.local_autopch_req(signal_wire24),
.local_self_rfsh_req(signal_wire25),
.local_self_rfsh_chip(signal_wire26),
.local_multicast_req(signal_wire27),
.local_refresh_chip(signal_wire28),
.global_reset_n(global_reset_n),
.pll_ref_clk(pll_ref_clk),
.soft_reset_n(soft_reset_n),
.local_ready(local_ready),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.local_refresh_ack(local_refresh_ack),
.local_init_done(local_init_done),
.reset_phy_clk_n(reset_phy_clk_n),
.dll_reference_clk(dll_reference_clk),
.dqs_delay_ctrl_export(dqs_delay_ctrl_export),
.hc_scan_dout(),
.pll_reconfig_busy(),
.pll_reconfig_clk(),
.pll_reconfig_reset(),
.pll_reconfig_data_out(),
.pll_phase_done(),
.aux_scan_clk_reset_n(),
.aux_scan_clk(),
.local_self_rfsh_ack(),
.local_power_down_ack(),
.mem_odt(mem_odt),
.mem_cs_n(mem_cs_n),
.mem_cke(mem_cke),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_dm(mem_dm),
.mem_reset_n(mem_reset_n),
.phy_clk(phy_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.aux_half_rate_clk(aux_half_rate_clk),
.reset_request_n(reset_request_n),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqsn(mem_dqsn));
endmodule
// =========================================================
// DDR3 High Performance Controller Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, DDR3 High Performance Controller Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="DDR3 SDRAM Controller with ALTMEMPHY" version="11.1" build="173" iptb_version="1.3.0 Build 173" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRControllerMVCModel" active_core="ddr3_int_controller_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="333.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Half" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="166.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR3 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="25.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(3003 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(40000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="13" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="256" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="Custom (Micron MT41J64M16LA-15E)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="Micron" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="666.666" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="64" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="240" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="110.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.38" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="340" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="500.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="13.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="180" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="165" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="36.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="255" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="13.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="125" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="30.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="3.9" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="On the fly" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_reorder_data" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="666.666" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="666.666" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="533.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="RZQ/6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="533.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.219" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="3.47" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.192" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.203" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="4.103" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.75" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.203" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.164" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="4.853" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.219" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.164" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.193" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="ddr3_int_alt_mem_ddrx_controller_top" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "nativelink_excludes" value="ddr3_int_phy_alt_mem_phy_seq.vhd,ddr3_int_phy_alt_mem_phy_seq_wrapper.vhd,ddr3_int_phy_alt_mem_phy_seq_wrapper.v" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="ddr3_int_alt_mem_ddrx_controller_top.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+ddr3_int_alt_mem_phy_seq_wrapper;+ddr3_int_alt_mem_phy_reconfig;+ddr3_int_alt_mem_phy_pll;+ddr3_int_phy_alt_mem_phy_delay;+ddr3_int_alt_mem_phy_dq_dqs --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=C:\FPGA\max_core_3d_352b\hdl\altera_ddr3_128/ddr3_int_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="ddr3_int_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="EP2AGX95EF29I3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 7,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "84.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90908000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_PP_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module out_arbiter
(// --- data path interface
output [63:0] out_data,
output [7:0] out_ctrl,
output reg out_wr,
input out_rdy,
input [63:0] in_data0,
input in_wr0,
input in_req0,
output in_ack0,
input in_bop0,
input in_eop0,
output in_outrdy0,
input [63:0] in_data1,
input in_wr1,
input in_req1,
output in_ack1,
input in_bop1,
input in_eop1,
output in_outrdy1,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [1:0] reg_src_out,
// --- Misc
input clk,
input reset
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
reg [1:0] in_ack;
assign in_ack0 = in_ack[0];
assign in_ack1 = in_ack[1];
wire [1:0] in_req;
assign in_req[0] = in_req0;
assign in_req[1] = in_req1;
wire [1:0] in_wr;
assign in_wr[0] = in_wr0;
assign in_wr[1] = in_wr1;
wire [63:0] in_data[1:0];
assign in_data[0] = in_data0;
assign in_data[1] = in_data1;
wire [1:0] in_bop;
assign in_bop[0] = in_bop0;
assign in_bop[1] = in_bop1;
wire [1:0] in_eop;
assign in_eop[0] = in_eop0;
assign in_eop[1] = in_eop1;
//reg [1:0] in_outrdy;
//assign in_outrdy0 = in_outrdy[0];
//assign in_outrdy1 = in_outrdy[1];
assign in_outrdy0 = out_rdy;
assign in_outrdy1 = out_rdy;
reg curr_input;
reg curr_input_next;
wire curr_input_plus_1;
assign curr_input_plus_1 = (curr_input == 1) ? 0 : 1;
parameter OA_STATE_IDLE = 1'b0,
OA_STATE_TX = 1'b1;
reg oa_state;
reg oa_state_next;
always @(*) begin
in_ack = 0;
curr_input_next = curr_input;
oa_state_next = oa_state;
case(oa_state)
OA_STATE_IDLE: begin
if(in_req[curr_input]) begin
oa_state_next = OA_STATE_TX;
end else begin
curr_input_next = curr_input_plus_1;
end
end
OA_STATE_TX: begin
if(in_req[curr_input]) begin
in_ack[curr_input] = 1;
end else begin
oa_state_next = OA_STATE_IDLE;
curr_input_next = curr_input_plus_1;
end
end
default: begin
oa_state_next = OA_STATE_IDLE;
end
endcase
end
wire [63:0] fifo_in_data;
wire [7:0] fifo_in_ctrl;
wire [7:0] fifo_in_ctrl0;
wire [7:0] fifo_in_ctrl1;
wire fifo_prog_full;
wire fifo_empty;
wire fifo_wr;
wire fifo_rd;
always @(posedge clk) begin
if(reset) begin
oa_state <= 0;
curr_input <= 0;
end else begin
oa_state <= oa_state_next;
curr_input <= curr_input_next;
out_wr <= fifo_rd;
end
end
assign fifo_in_data = (curr_input == 0) ? in_data0 : in_data1;
assign fifo_in_ctrl0 = (in_bop0) ? 8'b11111111 : (in_eop0) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl1 = (in_bop1) ? 8'b11111111 : (in_eop1) ? 8'b00000001 : 0 ;
assign fifo_in_ctrl = (curr_input == 0) ? fifo_in_ctrl0 : fifo_in_ctrl1;
assign fifo_wr = (curr_input == 0) ? in_wr0 : in_wr1;
assign fifo_rd = (fifo_empty == 1) ? 0 : out_rdy;
small_fifo_test input_fifo(
.data ({fifo_in_ctrl, fifo_in_data}), // Data in
.wrreq (fifo_wr), // Write enable
.rdreq (fifo_rd), // Read the next word
.q ({out_ctrl, out_data}),
.full (),
.empty (fifo_empty),
.sclr (reset),
.clock (clk),
.usedw ()
);
//assign out_wr = (out_rdy == 0) ? 0 : (fifo_empty == 1) ? 0 : 1;
/*
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_single cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = out_data;
assign TRIG0[71:64] = out_ctrl;
assign TRIG0[80] = out_wr;
assign TRIG0[81] = out_rdy;
assign TRIG0[163:100] = in_data0;
assign TRIG0[170] = in_wr0;
assign TRIG0[171] = in_req0;
assign TRIG0[172] = in_ack0;
assign TRIG0[173] = in_bop0;
assign TRIG0[174] = in_eop0;
assign TRIG0[175] = in_outrdy0;
assign TRIG0[180] = oa_state;
assign TRIG0[181] = curr_input;
assign TRIG0[182] = fifo_empty;
assign TRIG0[183] = fifo_wr;
assign TRIG0[184] = fifo_rd;
assign TRIG0[207:200] = fifo_in_ctrl;
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:52 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_xlconcat_0_1 -prefix
// zqynq_lab_1_design_xlconcat_0_1_ zqynq_lab_1_design_xlconcat_0_0_stub.v
// Design : zqynq_lab_1_design_xlconcat_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
module zqynq_lab_1_design_xlconcat_0_1(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],dout[1:0]" */;
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_TB_V
`define SKY130_FD_SC_HD__A41OI_TB_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a41oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a41oi dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_BEHAVIORAL_PP_V |
module dis340(
input wire clk,
input wire reset,
/* IO bus - 344 interface */
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire iobus_rdi_pulse, // unused on 6
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out,
output wire iobus_dr_split,
output wire iobus_rdi_data, // unused on 6
/* Indicators */
output wire [0:17] br_ind,
output wire [0:6] brm_ind,
output wire [0:9] x_ind,
output wire [0:9] y_ind,
output wire [1:4] s_ind,
output wire [0:2] i_ind,
output wire [0:2] mode_ind,
output wire [0:1] sz_ind,
output wire [0:8] flags_ind,
output wire [0:4] fe_ind,
output wire [31:0] foo_ind,
/* Avalon slave */
input wire s_read,
output wire [31:0] s_readdata,
output wire fe_data_rq
);
assign iobus_dr_split = 0;
assign iobus_rdi_data = 0;
assign br_ind = br;
assign brm_ind = brm;
assign x_ind = x;
assign y_ind = y;
assign s_ind = s;
assign i_ind = i;
assign mode_ind = mode;
assign sz_ind = sz;
assign flags_ind = {
rfd, cf, 1'b0, // TODO: CONT?
stop, move, halt,
lp_flag, lp_enable, lp_find
};
/* 344 - fantasy */
wire dis_sel = iobus_ios == 7'b001_011_0;
wire dis_data_clr;
wire dis_data_set;
wire dis_ic_clr;
wire dis_ic_set;
wire iob_reset;
wire dis_datai = dis_sel & iobus_iob_fm_datai;
wire dis_status = dis_sel & iobus_iob_fm_status;
pa ptr_pa0(clk, reset, dis_sel & iobus_datao_clear, dis_data_clr);
pa ptr_pa1(clk, reset, dis_sel & iobus_datao_set, dis_data_set);
pa ptr_pa2(clk, reset, dis_sel & iobus_cono_clear | iob_reset, dis_ic_clr);
pa ptr_pa3(clk, reset, dis_sel & iobus_cono_set, dis_ic_set);
pa ptr_pa4(clk, reset, iobus_iob_reset, iob_reset);
assign iobus_iob_out =
dis_datai ? { y, 9'b0, x } :
dis_status ? { edge_flag_vert, lp_flag, edge_flag_horiz,
stop_inter, done_flag, 1'b0,
dis_pia_spec, dis_pia_data } :
36'b0;
wire dis_flag_spec = edge_flag_vert | edge_flag_horiz |
lp_flag | stop_inter;
wire dis_flag_data = done_flag;
wire [1:7] dis_req_spec = { dis_flag_spec, 7'b0 } >> dis_pia_spec;
wire [1:7] dis_req_data = { dis_flag_data, 7'b0 } >> dis_pia_data;
assign iobus_pi_req = dis_req_spec | dis_req_data;
reg [30:32] dis_pia_spec;
reg [33:35] dis_pia_data;
reg [0:35] dis_ib;
reg [0:1] dis_ibc;
always @(posedge clk) begin
if(dis_ic_clr) begin
dis_pia_spec <= 0;
dis_pia_data <= 0;
// not quite sure..
dis_ib <= 0;
dis_ibc <= 0;
end
if(dis_ic_set) begin
dis_pia_spec <= iobus_iob_in[30:32];
dis_pia_data <= iobus_iob_in[33:35];
end
if(dis_data_clr) begin
dis_ib <= 0;
dis_ibc <= 0;
end
if(dis_data_set) begin
dis_ib <= dis_ib | iobus_iob_in;
dis_ibc <= 2'b11;
end
if(shift_ib) begin
dis_ib[0:17] <= dis_ib[18:35];
dis_ibc <= { dis_ibc[1], 1'b0 };
end
end
wire done_flag = rfd & ~dis_ibc[0];
pa dpy_pa100(clk, reset, rfd & dis_ibc[0], data_sync);
// from interface (?)
wire dpy_go = dis_ic_set & iobus_iob_in[29];
wire resume = dis_ic_set & ~iobus_iob_in[29];
wire data_sync;
wire [0:17] br_input = dis_ib[0:17];
// ??
wire clr_flags = 0;
/* light pen */
wire lp_pulse = 0;
/* 340 */
`ifdef simulation
initial begin
rfd <= 0;
halt <= 0;
end
`endif
reg rfd;
reg stop;
reg halt;
reg move;
wire initiate;
wire escape_pulse;
wire rfd_pulse;
wire idp;
wire pm_pulse;
wire x_start_pulse;
wire y_start_pulse;
wire cg_end_pulse;
wire next_char;
wire stop_inter = stop & br[8];
wire [0:3] inc =
{4{s[1]}} & br[2:5] |
{4{s[2]}} & br[6:9] |
{4{s[3]}} & br[10:13] |
{4{s[4]}} & br[14:17];
wire l = (vm | vcm) & horiz_vec & br[10] |
im & inc[0] & inc[1] |
cg_l;
wire r = (vm | vcm) & horiz_vec & ~br[10] |
im & inc[0] & ~inc[1] |
cg_r;
wire d = (vm | vcm) & vert_vec & br[2] |
im & inc[2] & inc[3] |
cg_d;
wire u = (vm | vcm) & vert_vec & ~br[2] |
im & inc[2] & ~inc[3] |
cg_u;
pa dpy_pa0(clk, reset, dpy_go, initiate);
pa dpy_pa1(clk, reset,
initiate | cg_escape |
count_x & br[0] & halt |
dly1_pulse & cf,
escape_pulse);
pa dpy_pa2(clk, reset,
dly6_pulse | initiate | cg_escape |
count_x & halt |
dly1_pulse & cf & vcm | // TODO: ???
pm_pulse & ~br[7] |
next_char & s[4],
rfd_pulse);
pa dpy_pa3(clk, reset, data_sync, clr_br);
pa dpy_pa4(clk, reset, clr_br, clr_brm);
pa dpy_pa5(clk, reset, read_to_s, load_br);
wire shift_ib = load_br;
// TODO: what's RI?
pa dpy_pa7(clk, reset, idp & pm, pm_pulse);
pa dpy_pa8(clk, reset, idp & xym & ~lp_flag & br[1], y_start_pulse);
pa dpy_pa9(clk, reset, idp & xym & ~lp_flag & ~br[1], x_start_pulse);
pa dpy_pa10(clk, reset,
pm_pulse | x_start_pulse | y_start_pulse,
read_to_mode);
pa dpy_pa11(clk, reset, pm_pulse & br[11], store_scale);
pa dpy_pa12(clk, reset, pm_pulse & br[14], store_int_level);
pa dpy_pa13(clk, reset, y_start_pulse, clr_y);
pa dpy_pa14(clk, reset, x_start_pulse | cg_cr, clr_x);
pa dpy_pa15(clk, reset, idp & (im | vm | vcm), count_brm);
pa dpy_pa16(clk, reset, count_brm | cg_count, count_x);
pa dpy_pa17(clk, reset, count_brm | cg_count, count_y);
pa dpy_pa18(clk, reset, count_brm | next_char, shift_s);
pa dpy_pa6(clk, reset, cg_end_level, cg_end_pulse);
assign next_char = cg_end_pulse & cm;
wire int_dly1, int_dly2;
wire int_dly = int_dly1 | int_dly2 | cg_intens;
wire intensify =
int_dly1 & move & br[1] |
int_dly2 & br[7] |
cg_intens & cg_int;
wire dly1_pulse; // sequence delay
wire dly4_pulse; // 35 deflection delay
wire dly6_pulse; // 0.5 after xy intensify
ldly500ns intdly_1(clk, reset,
load_br | // actually through PA
dly1_pulse & ~cf & ~lp_flag & ~rfd |
next_char & ~s[4],
intdly1_pulse /* idp */, int_dly1);
dly2_8us dpy_dly3(clk, reset, clr_br, read_to_s);
dly200ns dpy_dly5(clk, reset, x_start_pulse, load_x);
dly200ns dpy_dly7(clk, reset, y_start_pulse, load_y);
`ifdef simulation
dly2_8us dpy_dly4(clk, reset,
`else
dly35us dpy_dly4(clk, reset,
`endif
x_start_pulse | y_start_pulse & br[7],
dly4_pulse);
ldly500ns intdly_2(clk, reset,
dly4_pulse | y_start_pulse & ~br[7],
intdly2_pulse /* dly6_pulse */, int_dly2);
dly1us dpy_dly1(clk, reset,
count_brm & ~halt |
resume & ~cm,
dly1_pulse);
always @(posedge clk) begin
if(clr_brm) begin
halt <= 0;
move <= 0;
end
if(count_x & im & s[4] |
dly1_pulse & vm & brm == 'o177)
halt <= 1;
if(count_x & (l|r|u|d))
move <= ~cm;
if(initiate | clr_flags)
stop <= 0;
if(pm_pulse & br[7])
stop <= 1;
if(clr_flags | clr_br)
rfd <= 0;
if(rfd_pulse)
rfd <= 1;
end
reg [0:17] br;
wire clr_br;
wire load_br;
reg [0:2] mode;
wire read_to_mode;
wire pm = mode == 3'b000;
wire xym = mode == 3'b001;
wire sm = mode == 3'b010;
wire cm = mode == 3'b011;
wire vm = mode == 3'b100;
wire vcm = mode == 3'b101;
wire im = mode == 3'b110;
reg [0:1] sz;
wire store_scale;
wire scx8 = sz == 2'b11;
wire scx4 = sz == 2'b10;
wire sc = sz[0] | sz[1];
reg [0:2] i;
wire store_int_level;
reg lp_find;
reg lp_enable;
reg lp_flag;
always @(posedge clk) begin
if(clr_br)
br <= 0;
if(load_br)
br <= br | br_input;
if(escape_pulse) begin
mode <= 0;
lp_find <= 0;
end
if(read_to_mode)
mode <= br[2:4];
if(store_int_level)
i <= br[15:17];
if(store_scale)
sz <= br[12:13];
if(initiate | resume) // initiate not in drawings
lp_enable <= 0;
if(read_to_mode & br[5])
lp_enable <= br[6];
if(initiate | clr_flags | resume)
lp_flag <= 0;
if((count_y | read_to_s) & lp_enable & lp_find)
lp_flag <= 1;
if(initiate | resume)
lp_find <= 0;
if(lp_pulse & lp_enable)
lp_find <= 1;
end
reg [0:6] brm;
wire [0:6] brm_comp;
wire clr_brm;
wire count_brm;
assign brm_comp[6] = 1;
assign brm_comp[5] = brm[6] | ~br[3]&~br[11];
assign brm_comp[4] = (&brm[5:6]) | (&(~br[3:4]))&(&(~br[11:12]));
assign brm_comp[3] = (&brm[4:6]) | (&(~br[3:5]))&(&(~br[11:13]));
assign brm_comp[2] = (&brm[3:6]) | (&(~br[3:6]))&(&(~br[11:14]));
assign brm_comp[1] = (&brm[2:6]);
assign brm_comp[0] = (&brm[1:6]);
wire horiz_vec = (|(~brm[0:6] & brm_comp[0:6] &
{ br[17], br[16], br[15], br[14], br[13], br[12], br[11] }));
wire vert_vec = (|(~brm[0:6] & brm_comp[0:6] &
{ br[9], br[8], br[7], br[6], br[5], br[4], br[3] }));
always @(posedge clk) begin
if(clr_brm)
brm <= 0;
if(count_brm)
brm <= brm ^ brm_comp;
end
reg [1:4] s;
wire clr_s = clr_brm; // not on drawings
wire shift_s;
wire read_to_s;
always @(posedge clk) begin
if(clr_s)
s <= 0;
if(read_to_s & cm)
s[2] <= 1;
if(read_to_s & im)
s[1] <= 1;
if(shift_s)
s <= { 1'b0, s[1:3] };
end
reg [0:9] x;
reg [0:9] y;
reg edge_flag_vert;
reg edge_flag_horiz;
wire clr_x, load_x, count_x;
wire clr_y, load_y, count_y;
wire clr_cf = clr_brm; // not on drawings
wire cf = edge_flag_vert | edge_flag_horiz;
wire [0:9] xyinc = 1<<sz;
wire [0:9] xinc = r ? xyinc : l ? -xyinc : 0;
wire [0:9] yinc = u ? xyinc : d ? -xyinc : 0;
wire [0:9] xsum = x + xinc;
wire [0:9] ysum = y + yinc;
always @(posedge clk) begin
if(clr_y)
y <= 0;
if(load_y)
y <= y | br[8:17];
if(count_y) begin
y <= ysum;
if((y[0] ^ ysum[0]) & (y[0] ^ yinc[0]))
edge_flag_vert <= 1;
end
if(clr_x)
x <= 0;
if(load_x)
x <= x | br[8:17];
if(count_x) begin
x <= xsum;
if((x[0] ^ xsum[0]) & (x[0] ^ xinc[0]))
edge_flag_horiz <= 1;
end
if(clr_cf | clr_flags | rfd_pulse) begin
edge_flag_vert <= 0;
edge_flag_horiz <= 0;
end
end
/* 342 char gen - fantasy */
wire cg_end_level = cg_end;
wire cg_cr;
wire cg_count;
wire cg_escape;
wire cg_intens;
wire [0:5] cg_char =
{6{s[2]}} & br[0:5] |
{6{s[3]}} & br[6:11] |
{6{s[4]}} & br[12:17];
reg cg_l;
reg cg_r;
reg cg_d;
reg cg_u;
reg cg_int;
reg cg_end;
reg cg_so;
reg [0:4] cg_pulse;
reg [31:0] rom_u [0:127];
reg [31:0] rom_d [0:127];
reg [31:0] rom_l [0:127];
reg [31:0] rom_r [0:127];
reg [31:0] rom_i [0:127];
reg [31:0] rom_end [0:127];
reg [29:0] rom_u_q, rom_d_q, rom_l_q, rom_r_q, rom_i_q, rom_end_q;
initial begin
$readmemh("roms/u.rom", rom_u);
$readmemh("roms/d.rom", rom_d);
$readmemh("roms/l.rom", rom_l);
$readmemh("roms/r.rom", rom_r);
$readmemh("roms/in.rom", rom_i);
$readmemh("roms/end.rom", rom_end);
end
always @(posedge clk) begin
rom_l_q <= rom_l[{cg_so, cg_char}];
rom_r_q <= rom_r[{cg_so, cg_char}];
rom_d_q <= rom_d[{cg_so, cg_char}];
rom_u_q <= rom_u[{cg_so, cg_char}];
rom_i_q <= rom_i[{cg_so, cg_char}];
rom_end_q <= rom_end[{cg_so, cg_char}];
end
wire cg_start;
wire cg_strobe, cg_strobe_0, cg_strobe_1;
wire cg_count_0, cg_count_1;
pa pa_cg0(clk, reset, idp & cm, cg_start);
pa pa_cg1(clk, reset, cg_start | cg_count_1, cg_strobe);
pa pa_cg2(clk, reset, cg_strobe, cg_strobe_0);
pa pa_cg6(clk, reset, cg_strobe_0, cg_strobe_1);
pa pa_cg3(clk, reset, cg_strobe_1 & ~cg_end, cg_count);
pa pa_cg4(clk, reset, cg_start & (cg_char == 6'o37), cg_escape);
pa pa_cg5(clk, reset, cg_start & (cg_char == 6'o34), cg_cr);
dly1us dly_cg0(clk, reset, cg_count, cg_count_0);
ldly500ns intdly_3(clk, reset,
cg_count_0, intdly3_pulse /* cg_count_1 */, cg_intens);
always @(posedge clk) begin
if(iob_reset | reset) begin
cg_l <= 0;
cg_r <= 0;
cg_d <= 0;
cg_u <= 0;
cg_int <= 0;
cg_end <= 0;
cg_so <= 0;
end
// TODO: figure out how shift is set
if(initiate)
cg_so <= 0;
if(cg_start) begin
cg_pulse <= 0;
cg_end <= 0; // has to be set before strobe so we can detect an edge
if(cg_char == 6'o35)
cg_so <= 0;
if(cg_char == 6'o36)
cg_so <= 1;
end
if(cg_strobe_0) begin
cg_l <= rom_l_q[cg_pulse];
cg_r <= rom_r_q[cg_pulse];
cg_d <= rom_d_q[cg_pulse];
cg_u <= rom_u_q[cg_pulse];
cg_int <= rom_i_q[cg_pulse];
cg_end <= rom_end_q[cg_pulse];
cg_pulse <= cg_pulse + 1;
end
end
/* FE interface */
assign fe_data_rq = fe_req;
// assign s_readdata = fe_data;
assign s_readdata = { fe_req, 8'b0, i, y, x };
reg fe_req;
reg fe_rs;
// reg [31:0] fe_data;
wire int_start;
wire intdly1_pulse, intdly2_pulse, intdly3_pulse;
reg intdly1_sync, intdly2_sync, intdly3_sync;
assign fe_ind = { intdly1_sync, intdly2_sync, intdly3_sync, fe_rs, fe_req };
reg [29:0] foo;
always @(posedge clk)
foo <= rom_end[{cg_so, cg_char}];
assign foo_ind = foo;
wire fe_reset = reset | iob_reset;
pa fe_pa0(clk, fe_reset, int_dly, int_start);
pa fe_pa1(clk, fe_reset, intdly1_sync & fe_rs, idp);
pa fe_pa2(clk, fe_reset, intdly2_sync & fe_rs, dly6_pulse);
pa fe_pa3(clk, fe_reset, intdly3_sync & fe_rs, cg_count_1);
always @(posedge clk) begin
if(fe_reset) begin
intdly1_sync <= 0;
intdly2_sync <= 0;
intdly3_sync <= 0;
fe_req <= 0;
fe_rs <= 0;
end else begin
if(int_start & intensify) begin
fe_req <= 1;
fe_rs <= 0;
// fe_data <= { 1'b1, 8'b0, i, y, x };
end
if(int_start & ~intensify | s_read) begin
fe_req <= 0;
fe_rs <= 1;
// fe_data <= 0;
end
if(intdly1_pulse)
intdly1_sync <= 1;
if(idp)
intdly1_sync <= 0;
if(intdly2_pulse)
intdly2_sync <= 1;
if(dly6_pulse)
intdly2_sync <= 0;
if(intdly3_pulse)
intdly3_sync <= 1;
if(cg_count_1)
intdly3_sync <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_LP_V
`define SKY130_FD_SC_LP__A22O_LP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_lp (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_lp (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_LP_V
|
module SigmaDelta2ndOrder_tb ();
parameter WIDTH = 16; ///< Input width
parameter GAIN = 7.0/6.0; ///< Gain parameter
parameter GROWTH = 1; ///< Growth bits on accumulators
parameter CLAMP = 1; ///< Clamp accumulators
parameter FREQ_RATE = 2000000;
reg clk;
reg rst;
reg en;
reg signed [WIDTH-1:0] in;
wire sdOut;
wire signed [15:0] dataOut;
integer i;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
in = 'd0;
#2 rst = 1'b0;
#20000 in = 2**(WIDTH-1)-1;
#20000 in = -2**(WIDTH-1)+1;
#20000 in = 'd0;
#20000 in = 'd0;
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) in = $rtoi($sin($itor(i)**2*3.14159/FREQ_RATE)*(2**(WIDTH-2)-1));
end
for (i=1; i<2**16; i=i+1) begin
@(posedge clk) in = $random();
end
$stop();
end
always #1 clk = ~clk;
SigmaDelta2ndOrder #(
.WIDTH (WIDTH ), ///< Input width
.GAIN (GAIN ), ///< Gain parameter
.GROWTH(GROWTH), ///< Growth bits on accumulators
.CLAMP (CLAMP ) ///< Clamp accumulators
)
uut (
.clk(clk),
.rst(rst),
.en(en),
.in(in), ///< [WIDTH-1:0]
.sdOut(sdOut)
);
Sinc3Filter #(
.OSR(32) // Output width is 3*ceil(log2(OSR))+1
)
testFilter (
.clk(clk),
.en(en), ///< Enable (use to clock at slower rate)
.in(sdOut),
.out(dataOut) ///< [3*$clog2(OSR):0]
);
endmodule
|
`timescale 1 ns / 1 ps
/*! REGISTER_BITS !*/
module /*! MODULE_NAME !*/
#(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
/*! USER_PARAMS !*/
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = /*! <ADDR_WIDTH !*/
)
(
// Users to add ports here
/*! USER_PORTS !*/
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
/*! REGISTER_DECL !*/
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
//USER LOGIC
/*! USER_LOGIC !*/
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
/*! LOGIC_RESET !*/
end
else begin
/*! MISC_LOGIC !*/
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
4'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0 - Control
end
4'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
if (!slv_reg0[1])
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
4'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
if (!slv_reg0[1])
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
4'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
//clear interrupt by writing 1 to correct place, quick and dirty
if (byte_index == 0 && S_AXI_WDATA[3])
IRQ_ACK <= 1;
end
4'h4:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
/*! REGISTER_HOLD !*/
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
/*! EVENTS_ON_READ !*/
end
end
end // always @ ( posedge S_AXI_ACLK )
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
/*! READ_REGISTERS !*/
default : reg_data_out <= 0;
endcase
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
/*! ASSIGN_LOGIC !*/
// User logic ends
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 c3 c4 clk configupdate locked phasecounterselect phasedone phasestep phaseupdown read readdata reset scanclk scanclkena scandata scandataout scandone write writedata bandwidth_type="AUTO" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=29 clk0_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=125000 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 18.1 cbx_altclkbuf 2019:04:11:16:04:12:SJ cbx_altiobuf_bidir 2019:04:11:16:04:12:SJ cbx_altiobuf_in 2019:04:11:16:04:12:SJ cbx_altiobuf_out 2019:04:11:16:04:12:SJ cbx_altpll 2019:04:11:16:04:12:SJ cbx_cycloneii 2019:04:11:16:04:12:SJ cbx_lpm_add_sub 2019:04:11:16:04:12:SJ cbx_lpm_compare 2019:04:11:16:04:12:SJ cbx_lpm_counter 2019:04:11:16:04:12:SJ cbx_lpm_decode 2019:04:11:16:04:12:SJ cbx_lpm_mux 2019:04:11:16:04:12:SJ cbx_lpm_shiftreg 2019:04:11:16:04:12:SJ cbx_max10_altpll_avalon 2019:04:11:16:04:12:SJ cbx_mgl 2019:04:11:16:07:46:SJ cbx_nadder 2019:04:11:16:04:12:SJ cbx_stratix 2019:04:11:16:04:12:SJ cbx_stratixii 2019:04:11:16:04:12:SJ cbx_stratixiii 2019:04:11:16:04:12:SJ cbx_stratixv 2019:04:11:16:04:12:SJ cbx_util_mgl 2019:04:11:16:04:12:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 18.1 cbx_mgl 2019:04:11:16:07:46:SJ cbx_stratixii 2019:04:11:16:04:12:SJ cbx_util_mgl 2019:04:11:16:04:12:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 18.1 cbx_mgl 2019:04:11:16:07:46:SJ cbx_stratixii 2019:04:11:16:04:12:SJ cbx_util_mgl 2019:04:11:16:04:12:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module wasca_altpll_1_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //wasca_altpll_1_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_1_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
wasca_altpll_1_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //wasca_altpll_1_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=29 clk0_phase_shift="0" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=125000 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 18.1 cbx_altclkbuf 2019:04:11:16:04:12:SJ cbx_altiobuf_bidir 2019:04:11:16:04:12:SJ cbx_altiobuf_in 2019:04:11:16:04:12:SJ cbx_altiobuf_out 2019:04:11:16:04:12:SJ cbx_altpll 2019:04:11:16:04:12:SJ cbx_cycloneii 2019:04:11:16:04:12:SJ cbx_lpm_add_sub 2019:04:11:16:04:12:SJ cbx_lpm_compare 2019:04:11:16:04:12:SJ cbx_lpm_counter 2019:04:11:16:04:12:SJ cbx_lpm_decode 2019:04:11:16:04:12:SJ cbx_lpm_mux 2019:04:11:16:04:12:SJ cbx_mgl 2019:04:11:16:07:46:SJ cbx_nadder 2019:04:11:16:04:12:SJ cbx_stratix 2019:04:11:16:04:12:SJ cbx_stratixii 2019:04:11:16:04:12:SJ cbx_stratixiii 2019:04:11:16:04:12:SJ cbx_stratixv 2019:04:11:16:04:12:SJ cbx_util_mgl 2019:04:11:16:04:12:SJ VERSION_END
//synthesis_resources = fiftyfivenm_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module wasca_altpll_1_altpll_it22
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
fiftyfivenm_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 2,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 29,
pll7.clk0_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 125000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //wasca_altpll_1_altpll_it22
//synthesis_resources = fiftyfivenm_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_1
(
address,
areset,
c0,
c1,
c2,
c3,
c4,
clk,
configupdate,
locked,
phasecounterselect,
phasedone,
phasestep,
phaseupdown,
read,
readdata,
reset,
scanclk,
scanclkena,
scandata,
scandataout,
scandone,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
output c4;
input clk;
input configupdate;
output locked;
input [2:0] phasecounterselect;
output phasedone;
input phasestep;
input phaseupdown;
input read;
output [31:0] readdata;
input reset;
input scanclk;
input scanclkena;
input scandata;
output scandataout;
output scandone;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
wasca_altpll_1_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
wasca_altpll_1_altpll_it22 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
c2 = wire_sd1_clk[2],
c3 = wire_sd1_clk[3],
c4 = wire_sd1_clk[4],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
scandataout = 1'b0,
scandone = 1'b0,
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //wasca_altpll_1
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_TB_V
`define SKY130_FD_SC_LS__NAND2_TB_V
/**
* nand2: 2-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_TB_V
|
// http://www.lti-systems.com/verilog_03.html
// altera seven seg is logic low.
module sevenseg(displayout,inputbcd);
output [6:0] displayout;
input [3:0] inputbcd;
reg [6:0] displayout; //latch the outputs
parameter bit0 = 7'b0000001;
parameter bit1 = 7'b0000010;
parameter bit2 = 7'b0000100;
parameter bit3 = 7'b0001000;
parameter bit4 = 7'b0010000;
parameter bit5 = 7'b0100000;
parameter bit6 = 7'b1000000;
parameter zero = ~(bit0 | bit1 | bit2 | bit3 | bit4 | bit5);
parameter one = ~(bit1 | bit2);
parameter two = ~(bit0 | bit1 | bit3 | bit4 | bit6);
parameter three = ~(bit0 | bit1 | bit2 | bit3 | bit6);
parameter four = ~(bit1 | bit2 | bit5 | bit6);
parameter five = ~(bit0 | bit2 | bit3 | bit5 | bit6);
parameter six = ~(bit0 | bit2 | bit3 | bit4 | bit5 | bit6);
parameter seven = ~(bit0 | bit1 | bit2);
parameter eight = ~(bit0 | bit1 | bit2 | bit3 | bit4 | bit5 | bit6);
parameter nine = ~(bit0 | bit1 | bit2 | bit5 | bit6);
parameter blank = ~(7'd0);
always @ (inputbcd)
case (inputbcd)
0: displayout = zero;
1: displayout = one;
2: displayout = two;
3: displayout = three;
4: displayout = four;
5: displayout = five;
6: displayout = six;
7: displayout = seven;
8: displayout = eight;
9: displayout = nine;
default: displayout = blank;
endcase
endmodule
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics MoreSpecif.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{Proof by Reflection}% *)
(** The last chapter highlighted a very heuristic approach to proving. In this chapter, we will study an alternative technique,%\index{proof by reflection}% _proof by reflection_ %\cite{reflection}%. We will write, in Gallina, decision procedures with proofs of correctness, and we will appeal to these procedures in writing very short proofs. Such a proof is checked by running the decision procedure. The term _reflection_ applies because we will need to translate Gallina propositions into values of inductive types representing syntax, so that Gallina programs may analyze them, and translating such a term back to the original form is called _reflecting_ it. *)
(** * Proving Evenness *)
(** Proving that particular natural number constants are even is certainly something we would rather have happen automatically. The Ltac-programming techniques that we learned in the last chapter make it easy to implement such a procedure. *)
Inductive isEven : nat -> Prop :=
| Even_O : isEven O
| Even_SS : forall n, isEven n -> isEven (S (S n)).
(* begin thide *)
Ltac prove_even := repeat constructor.
(* end thide *)
Theorem even_256 : isEven 256.
prove_even.
Qed.
Print even_256.
(** %\vspace{-.15in}% [[
even_256 =
Even_SS
(Even_SS
(Even_SS
(Even_SS
]]
%\noindent%...and so on. This procedure always works (at least on machines with infinite resources), but it has a serious drawback, which we see when we print the proof it generates that 256 is even. The final proof term has length super-linear in the input value. Coq's implicit arguments mechanism is hiding the values given for parameter [n] of [Even_SS], which is why the proof term only appears linear here. Also, proof terms are represented internally as syntax trees, with opportunity for sharing of node representations, but in this chapter we will measure proof term size as simple textual length or as the number of nodes in the term's syntax tree, two measures that are approximately equivalent. Sometimes apparently large proof terms have enough internal sharing that they take up less memory than we expect, but one avoids having to reason about such sharing by ensuring that the size of a sharing-free version of a term is low enough.
Superlinear evenness proof terms seem like a shame, since we could write a trivial and trustworthy program to verify evenness of constants. The proof checker could simply call our program where needed.
It is also unfortunate not to have static typing guarantees that our tactic always behaves appropriately. Other invocations of similar tactics might fail with dynamic type errors, and we would not know about the bugs behind these errors until we happened to attempt to prove complex enough goals.
The techniques of proof by reflection address both complaints. We will be able to write proofs like in the example above with constant size overhead beyond the size of the input, and we will do it with verified decision procedures written in Gallina.
For this example, we begin by using a type from the [MoreSpecif] module (included in the book source) to write a certified evenness checker. *)
(* begin hide *)
(* begin thide *)
Definition paartial := partial.
(* end thide *)
(* end hide *)
Print partial.
(** %\vspace{-.15in}% [[
Inductive partial (P : Prop) : Set := Proved : P -> [P] | Uncertain : [P]
]]
A [partial P] value is an optional proof of [P]. The notation [[P]] stands for [partial P]. *)
Local Open Scope partial_scope.
(** We bring into scope some notations for the [partial] type. These overlap with some of the notations we have seen previously for specification types, so they were placed in a separate scope that needs separate opening. *)
(* begin thide *)
Definition check_even : forall n : nat, [isEven n].
Hint Constructors isEven.
refine (fix F (n : nat) : [isEven n] :=
match n with
| 0 => Yes
| 1 => No
| S (S n') => Reduce (F n')
end); auto.
Defined.
(** The function [check_even] may be viewed as a _verified decision procedure_, because its type guarantees that it never returns %\coqdocnotation{%#<tt>#Yes#</tt>#%}% for inputs that are not even.
Now we can use dependent pattern-matching to write a function that performs a surprising feat. When given a [partial P], this function [partialOut] returns a proof of [P] if the [partial] value contains a proof, and it returns a (useless) proof of [True] otherwise. From the standpoint of ML and Haskell programming, it seems impossible to write such a type, but it is trivial with a [return] annotation. *)
Definition partialOut (P : Prop) (x : [P]) :=
match x return (match x with
| Proved _ => P
| Uncertain => True
end) with
| Proved pf => pf
| Uncertain => I
end.
(** It may seem strange to define a function like this. However, it turns out to be very useful in writing a reflective version of our earlier [prove_even] tactic: *)
Ltac prove_even_reflective :=
match goal with
| [ |- isEven ?N] => exact (partialOut (check_even N))
end.
(* end thide *)
(** We identify which natural number we are considering, and we "prove" its evenness by pulling the proof out of the appropriate [check_even] call. Recall that the %\index{tactics!exact}%[exact] tactic proves a proposition [P] when given a proof term of precisely type [P]. *)
Theorem even_256' : isEven 256.
prove_even_reflective.
Qed.
Print even_256'.
(** %\vspace{-.15in}% [[
even_256' = partialOut (check_even 256)
: isEven 256
]]
We can see a constant wrapper around the object of the proof. For any even number, this form of proof will suffice. The size of the proof term is now linear in the number being checked, containing two repetitions of the unary form of that number, one of which is hidden above within the implicit argument to [partialOut].
What happens if we try the tactic with an odd number? *)
Theorem even_255 : isEven 255.
(** %\vspace{-.275in}%[[
prove_even_reflective.
]]
<<
User error: No matching clauses for match goal
>>
Thankfully, the tactic fails. To see more precisely what goes wrong, we can run manually the body of the [match].
%\vspace{-.15in}%[[
exact (partialOut (check_even 255)).
]]
<<
Error: The term "partialOut (check_even 255)" has type
"match check_even 255 with
| Yes => isEven 255
| No => True
end" while it is expected to have type "isEven 255"
>>
As usual, the type checker performs no reductions to simplify error messages. If we reduced the first term ourselves, we would see that [check_even 255] reduces to a %\coqdocnotation{%#<tt>#No#</tt>#%}%, so that the first term is equivalent to [True], which certainly does not unify with [isEven 255]. *)
Abort.
(** Our tactic [prove_even_reflective] is reflective because it performs a proof search process (a trivial one, in this case) wholly within Gallina, where the only use of Ltac is to translate a goal into an appropriate use of [check_even]. *)
(** * Reifying the Syntax of a Trivial Tautology Language *)
(** We might also like to have reflective proofs of trivial tautologies like this one: *)
Theorem true_galore : (True /\ True) -> (True \/ (True /\ (True -> True))).
tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition tg := (and_ind, or_introl).
(* end thide *)
(* end hide *)
Print true_galore.
(** %\vspace{-.15in}% [[
true_galore =
fun H : True /\ True =>
and_ind (fun _ _ : True => or_introl (True /\ (True -> True)) I) H
: True /\ True -> True \/ True /\ (True -> True)
]]
As we might expect, the proof that [tauto] builds contains explicit applications of natural deduction rules. For large formulas, this can add a linear amount of proof size overhead, beyond the size of the input.
To write a reflective procedure for this class of goals, we will need to get into the actual "reflection" part of "proof by reflection." It is impossible to case-analyze a [Prop] in any way in Gallina. We must%\index{reification}% _reify_ [Prop] into some type that we _can_ analyze. This inductive type is a good candidate: *)
(* begin thide *)
Inductive taut : Set :=
| TautTrue : taut
| TautAnd : taut -> taut -> taut
| TautOr : taut -> taut -> taut
| TautImp : taut -> taut -> taut.
(** We write a recursive function to _reflect_ this syntax back to [Prop]. Such functions are also called%\index{interpretation function}% _interpretation functions_, and we have used them in previous examples to give semantics to small programming languages. *)
Fixpoint tautDenote (t : taut) : Prop :=
match t with
| TautTrue => True
| TautAnd t1 t2 => tautDenote t1 /\ tautDenote t2
| TautOr t1 t2 => tautDenote t1 \/ tautDenote t2
| TautImp t1 t2 => tautDenote t1 -> tautDenote t2
end.
(** It is easy to prove that every formula in the range of [tautDenote] is true. *)
Theorem tautTrue : forall t, tautDenote t.
induction t; crush.
Qed.
(** To use [tautTrue] to prove particular formulas, we need to implement the syntax reification process. A recursive Ltac function does the job. *)
Ltac tautReify P :=
match P with
| True => TautTrue
| ?P1 /\ ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautAnd t1 t2)
| ?P1 \/ ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautOr t1 t2)
| ?P1 -> ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautImp t1 t2)
end.
(** With [tautReify] available, it is easy to finish our reflective tactic. We look at the goal formula, reify it, and apply [tautTrue] to the reified formula. *)
Ltac obvious :=
match goal with
| [ |- ?P ] =>
let t := tautReify P in
exact (tautTrue t)
end.
(** We can verify that [obvious] solves our original example, with a proof term that does not mention details of the proof. *)
(* end thide *)
Theorem true_galore' : (True /\ True) -> (True \/ (True /\ (True -> True))).
obvious.
Qed.
Print true_galore'.
(** %\vspace{-.15in}% [[
true_galore' =
tautTrue
(TautImp (TautAnd TautTrue TautTrue)
(TautOr TautTrue (TautAnd TautTrue (TautImp TautTrue TautTrue))))
: True /\ True -> True \/ True /\ (True -> True)
]]
It is worth considering how the reflective tactic improves on a pure-Ltac implementation. The formula reification process is just as ad-hoc as before, so we gain little there. In general, proofs will be more complicated than formula translation, and the "generic proof rule" that we apply here _is_ on much better formal footing than a recursive Ltac function. The dependent type of the proof guarantees that it "works" on any input formula. This benefit is in addition to the proof-size improvement that we have already seen.
It may also be worth pointing out that our previous example of evenness testing used a function [partialOut] for sound handling of input goals that the verified decision procedure fails to prove. Here, we prove that our procedure [tautTrue] (recall that an inductive proof may be viewed as a recursive procedure) is able to prove any goal representable in [taut], so no extra step is necessary. *)
(** * A Monoid Expression Simplifier *)
(** Proof by reflection does not require encoding of all of the syntax in a goal. We can insert "variables" in our syntax types to allow injection of arbitrary pieces, even if we cannot apply specialized reasoning to them. In this section, we explore that possibility by writing a tactic for normalizing monoid equations. *)
Section monoid.
Variable A : Set.
Variable e : A.
Variable f : A -> A -> A.
Infix "+" := f.
Hypothesis assoc : forall a b c, (a + b) + c = a + (b + c).
Hypothesis identl : forall a, e + a = a.
Hypothesis identr : forall a, a + e = a.
(** We add variables and hypotheses characterizing an arbitrary instance of the algebraic structure of monoids. We have an associative binary operator and an identity element for it.
It is easy to define an expression tree type for monoid expressions. A [Var] constructor is a "catch-all" case for subexpressions that we cannot model. These subexpressions could be actual Gallina variables, or they could just use functions that our tactic is unable to understand. *)
(* begin thide *)
Inductive mexp : Set :=
| Ident : mexp
| Var : A -> mexp
| Op : mexp -> mexp -> mexp.
(** Next, we write an interpretation function. *)
Fixpoint mdenote (me : mexp) : A :=
match me with
| Ident => e
| Var v => v
| Op me1 me2 => mdenote me1 + mdenote me2
end.
(** We will normalize expressions by flattening them into lists, via associativity, so it is helpful to have a denotation function for lists of monoid values. *)
Fixpoint mldenote (ls : list A) : A :=
match ls with
| nil => e
| x :: ls' => x + mldenote ls'
end.
(** The flattening function itself is easy to implement. *)
Fixpoint flatten (me : mexp) : list A :=
match me with
| Ident => nil
| Var x => x :: nil
| Op me1 me2 => flatten me1 ++ flatten me2
end.
(** This function has a straightforward correctness proof in terms of our [denote] functions. *)
Lemma flatten_correct' : forall ml2 ml1,
mldenote ml1 + mldenote ml2 = mldenote (ml1 ++ ml2).
induction ml1; crush.
Qed.
Theorem flatten_correct : forall me, mdenote me = mldenote (flatten me).
Hint Resolve flatten_correct'.
induction me; crush.
Qed.
(** Now it is easy to prove a theorem that will be the main tool behind our simplification tactic. *)
Theorem monoid_reflect : forall me1 me2,
mldenote (flatten me1) = mldenote (flatten me2)
-> mdenote me1 = mdenote me2.
intros; repeat rewrite flatten_correct; assumption.
Qed.
(** We implement reification into the [mexp] type. *)
Ltac reify me :=
match me with
| e => Ident
| ?me1 + ?me2 =>
let r1 := reify me1 in
let r2 := reify me2 in
constr:(Op r1 r2)
| _ => constr:(Var me)
end.
(** The final [monoid] tactic works on goals that equate two monoid terms. We reify each and change the goal to refer to the reified versions, finishing off by applying [monoid_reflect] and simplifying uses of [mldenote]. Recall that the %\index{tactics!change}%[change] tactic replaces a conclusion formula with another that is definitionally equal to it. *)
Ltac monoid :=
match goal with
| [ |- ?me1 = ?me2 ] =>
let r1 := reify me1 in
let r2 := reify me2 in
change (mdenote r1 = mdenote r2);
apply monoid_reflect; simpl
end.
(** We can make short work of theorems like this one: *)
(* end thide *)
Theorem t1 : forall a b c d, a + b + c + d = a + (b + c) + d.
intros; monoid.
(** [[
============================
a + (b + (c + (d + e))) = a + (b + (c + (d + e)))
]]
Our tactic has canonicalized both sides of the equality, such that we can finish the proof by reflexivity. *)
reflexivity.
Qed.
(** It is interesting to look at the form of the proof. *)
Print t1.
(** %\vspace{-.15in}% [[
t1 =
fun a b c d : A =>
monoid_reflect (Op (Op (Op (Var a) (Var b)) (Var c)) (Var d))
(Op (Op (Var a) (Op (Var b) (Var c))) (Var d))
(eq_refl (a + (b + (c + (d + e)))))
: forall a b c d : A, a + b + c + d = a + (b + c) + d
]]
The proof term contains only restatements of the equality operands in reified form, followed by a use of reflexivity on the shared canonical form. *)
End monoid.
(** Extensions of this basic approach are used in the implementations of the %\index{tactics!ring}%[ring] and %\index{tactics!field}%[field] tactics that come packaged with Coq. *)
(** * A Smarter Tautology Solver *)
(** Now we are ready to revisit our earlier tautology solver example. We want to broaden the scope of the tactic to include formulas whose truth is not syntactically apparent. We will want to allow injection of arbitrary formulas, like we allowed arbitrary monoid expressions in the last example. Since we are working in a richer theory, it is important to be able to use equalities between different injected formulas. For instance, we cannot prove [P -> P] by translating the formula into a value like [Imp (Var P) (Var P)], because a Gallina function has no way of comparing the two [P]s for equality.
To arrive at a nice implementation satisfying these criteria, we introduce the %\index{tactics!quote}%[quote] tactic and its associated library. *)
Require Import Quote.
(* begin thide *)
Inductive formula : Set :=
| Atomic : index -> formula
| Truth : formula
| Falsehood : formula
| And : formula -> formula -> formula
| Or : formula -> formula -> formula
| Imp : formula -> formula -> formula.
(* end thide *)
(** The type %\index{Gallina terms!index}%[index] comes from the [Quote] library and represents a countable variable type. The rest of [formula]'s definition should be old hat by now.
The [quote] tactic will implement injection from [Prop] into [formula] for us, but it is not quite as smart as we might like. In particular, it wants to treat function types specially, so it gets confused if function types are part of the structure we want to encode syntactically. To trick [quote] into not noticing our uses of function types to express logical implication, we will need to declare a wrapper definition for implication, as we did in the last chapter. *)
Definition imp (P1 P2 : Prop) := P1 -> P2.
Infix "-->" := imp (no associativity, at level 95).
(** Now we can define our denotation function. *)
Definition asgn := varmap Prop.
(* begin thide *)
Fixpoint formulaDenote (atomics : asgn) (f : formula) : Prop :=
match f with
| Atomic v => varmap_find False v atomics
| Truth => True
| Falsehood => False
| And f1 f2 => formulaDenote atomics f1 /\ formulaDenote atomics f2
| Or f1 f2 => formulaDenote atomics f1 \/ formulaDenote atomics f2
| Imp f1 f2 => formulaDenote atomics f1 --> formulaDenote atomics f2
end.
(* end thide *)
(** The %\index{Gallina terms!varmap}%[varmap] type family implements maps from [index] values. In this case, we define an assignment as a map from variables to [Prop]s. Our interpretation function [formulaDenote] works with an assignment, and we use the [varmap_find] function to consult the assignment in the [Atomic] case. The first argument to [varmap_find] is a default value, in case the variable is not found. *)
Section my_tauto.
Variable atomics : asgn.
Definition holds (v : index) := varmap_find False v atomics.
(** We define some shorthand for a particular variable being true, and now we are ready to define some helpful functions based on the [ListSet] module of the standard library, which (unsurprisingly) presents a view of lists as sets. *)
Require Import ListSet.
Definition index_eq : forall x y : index, {x = y} + {x <> y}.
decide equality.
Defined.
Definition add (s : set index) (v : index) := set_add index_eq v s.
Definition In_dec : forall v (s : set index), {In v s} + {~ In v s}.
Local Open Scope specif_scope.
intro; refine (fix F (s : set index) : {In v s} + {~ In v s} :=
match s with
| nil => No
| v' :: s' => index_eq v' v || F s'
end); crush.
Defined.
(** We define what it means for all members of an index set to represent true propositions, and we prove some lemmas about this notion. *)
Fixpoint allTrue (s : set index) : Prop :=
match s with
| nil => True
| v :: s' => holds v /\ allTrue s'
end.
Theorem allTrue_add : forall v s,
allTrue s
-> holds v
-> allTrue (add s v).
induction s; crush;
match goal with
| [ |- context[if ?E then _ else _] ] => destruct E
end; crush.
Qed.
Theorem allTrue_In : forall v s,
allTrue s
-> set_In v s
-> varmap_find False v atomics.
induction s; crush.
Qed.
Hint Resolve allTrue_add allTrue_In.
Local Open Scope partial_scope.
(** Now we can write a function [forward] that implements deconstruction of hypotheses, expanding a compound formula into a set of sets of atomic formulas covering all possible cases introduced with use of [Or]. To handle consideration of multiple cases, the function takes in a continuation argument, which will be called once for each case.
The [forward] function has a dependent type, in the style of Chapter 6, guaranteeing correctness. The arguments to [forward] are a goal formula [f], a set [known] of atomic formulas that we may assume are true, a hypothesis formula [hyp], and a success continuation [cont] that we call when we have extended [known] to hold new truths implied by [hyp]. *)
Definition forward : forall (f : formula) (known : set index) (hyp : formula)
(cont : forall known', [allTrue known' -> formulaDenote atomics f]),
[allTrue known -> formulaDenote atomics hyp -> formulaDenote atomics f].
refine (fix F (f : formula) (known : set index) (hyp : formula)
(cont : forall known', [allTrue known' -> formulaDenote atomics f])
: [allTrue known -> formulaDenote atomics hyp -> formulaDenote atomics f] :=
match hyp with
| Atomic v => Reduce (cont (add known v))
| Truth => Reduce (cont known)
| Falsehood => Yes
| And h1 h2 =>
Reduce (F (Imp h2 f) known h1 (fun known' =>
Reduce (F f known' h2 cont)))
| Or h1 h2 => F f known h1 cont && F f known h2 cont
| Imp _ _ => Reduce (cont known)
end); crush.
Defined.
(** A [backward] function implements analysis of the final goal. It calls [forward] to handle implications. *)
(* begin thide *)
Definition backward : forall (known : set index) (f : formula),
[allTrue known -> formulaDenote atomics f].
refine (fix F (known : set index) (f : formula)
: [allTrue known -> formulaDenote atomics f] :=
match f with
| Atomic v => Reduce (In_dec v known)
| Truth => Yes
| Falsehood => No
| And f1 f2 => F known f1 && F known f2
| Or f1 f2 => F known f1 || F known f2
| Imp f1 f2 => forward f2 known f1 (fun known' => F known' f2)
end); crush; eauto.
Defined.
(* end thide *)
(** A simple wrapper around [backward] gives us the usual type of a partial decision procedure. *)
Definition my_tauto : forall f : formula, [formulaDenote atomics f].
(* begin thide *)
intro; refine (Reduce (backward nil f)); crush.
Defined.
(* end thide *)
End my_tauto.
(** Our final tactic implementation is now fairly straightforward. First, we [intro] all quantifiers that do not bind [Prop]s. Then we call the [quote] tactic, which implements the reification for us. Finally, we are able to construct an exact proof via [partialOut] and the [my_tauto] Gallina function. *)
Ltac my_tauto :=
repeat match goal with
| [ |- forall x : ?P, _ ] =>
match type of P with
| Prop => fail 1
| _ => intro
end
end;
quote formulaDenote;
match goal with
| [ |- formulaDenote ?m ?f ] => exact (partialOut (my_tauto m f))
end.
(* end thide *)
(** A few examples demonstrate how the tactic works. *)
Theorem mt1 : True.
my_tauto.
Qed.
Print mt1.
(** %\vspace{-.15in}% [[
mt1 = partialOut (my_tauto (Empty_vm Prop) Truth)
: True
]]
We see [my_tauto] applied with an empty [varmap], since every subformula is handled by [formulaDenote]. *)
Theorem mt2 : forall x y : nat, x = y --> x = y.
my_tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition nvm := (Node_vm, Empty_vm, End_idx, Left_idx, Right_idx).
(* end thide *)
(* end hide *)
Print mt2.
(** %\vspace{-.15in}% [[
mt2 =
fun x y : nat =>
partialOut
(my_tauto (Node_vm (x = y) (Empty_vm Prop) (Empty_vm Prop))
(Imp (Atomic End_idx) (Atomic End_idx)))
: forall x y : nat, x = y --> x = y
]]
Crucially, both instances of [x = y] are represented with the same index, [End_idx]. The value of this index only needs to appear once in the [varmap], whose form reveals that [varmap]s are represented as binary trees, where [index] values denote paths from tree roots to leaves. *)
Theorem mt3 : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
--> y > z /\ (x < y \/ x < S y).
my_tauto.
Qed.
Print mt3.
(** %\vspace{-.15in}% [[
fun x y z : nat =>
partialOut
(my_tauto
(Node_vm (x < S y) (Node_vm (x < y) (Empty_vm Prop) (Empty_vm Prop))
(Node_vm (y > z) (Empty_vm Prop) (Empty_vm Prop)))
(Imp
(Or (And (Atomic (Left_idx End_idx)) (Atomic (Right_idx End_idx)))
(And (Atomic (Right_idx End_idx)) (Atomic End_idx)))
(And (Atomic (Right_idx End_idx))
(Or (Atomic (Left_idx End_idx)) (Atomic End_idx)))))
: forall x y z : nat,
x < y /\ y > z \/ y > z /\ x < S y --> y > z /\ (x < y \/ x < S y)
]]
Our goal contained three distinct atomic formulas, and we see that a three-element [varmap] is generated.
It can be interesting to observe differences between the level of repetition in proof terms generated by [my_tauto] and [tauto] for especially trivial theorems. *)
Theorem mt4 : True /\ True /\ True /\ True /\ True /\ True /\ False --> False.
my_tauto.
Qed.
Print mt4.
(** %\vspace{-.15in}% [[
mt4 =
partialOut
(my_tauto (Empty_vm Prop)
(Imp
(And Truth
(And Truth
(And Truth (And Truth (And Truth (And Truth Falsehood))))))
Falsehood))
: True /\ True /\ True /\ True /\ True /\ True /\ False --> False
]]
*)
Theorem mt4' : True /\ True /\ True /\ True /\ True /\ True /\ False -> False.
tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition fi := False_ind.
(* end thide *)
(* end hide *)
Print mt4'.
(** %\vspace{-.15in}% [[
mt4' =
fun H : True /\ True /\ True /\ True /\ True /\ True /\ False =>
and_ind
(fun (_ : True) (H1 : True /\ True /\ True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H3 : True /\ True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H5 : True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H7 : True /\ True /\ False) =>
and_ind
(fun (_ : True) (H9 : True /\ False) =>
and_ind (fun (_ : True) (H11 : False) => False_ind False H11)
H9) H7) H5) H3) H1) H
: True /\ True /\ True /\ True /\ True /\ True /\ False -> False
]]
The traditional [tauto] tactic introduces a quadratic blow-up in the size of the proof term, whereas proofs produced by [my_tauto] always have linear size. *)
(** ** Manual Reification of Terms with Variables *)
(* begin thide *)
(** The action of the [quote] tactic above may seem like magic. Somehow it performs equality comparison between subterms of arbitrary types, so that these subterms may be represented with the same reified variable. While [quote] is implemented in OCaml, we can code the reification process completely in Ltac, as well. To make our job simpler, we will represent variables as [nat]s, indexing into a simple list of variable values that may be referenced.
Step one of the process is to crawl over a term, building a duplicate-free list of all values that appear in positions we will encode as variables. A useful helper function adds an element to a list, preventing duplicates. Note how we use Ltac pattern matching to implement an equality test on Gallina terms; this is simple syntactic equality, not even the richer definitional equality. We also represent lists as nested tuples, to allow different list elements to have different Gallina types. *)
Ltac inList x xs :=
match xs with
| tt => false
| (x, _) => true
| (_, ?xs') => inList x xs'
end.
Ltac addToList x xs :=
let b := inList x xs in
match b with
| true => xs
| false => constr:(x, xs)
end.
(** Now we can write our recursive function to calculate the list of variable values we will want to use to represent a term. *)
Ltac allVars xs e :=
match e with
| True => xs
| False => xs
| ?e1 /\ ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| ?e1 \/ ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| ?e1 -> ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| _ => addToList e xs
end.
(** We will also need a way to map a value to its position in a list. *)
Ltac lookup x xs :=
match xs with
| (x, _) => O
| (_, ?xs') =>
let n := lookup x xs' in
constr:(S n)
end.
(** The next building block is a procedure for reifying a term, given a list of all allowed variable values. We are free to make this procedure partial, where tactic failure may be triggered upon attempting to reify a term containing subterms not included in the list of variables. The type of the output term is a copy of [formula] where [index] is replaced by [nat], in the type of the constructor for atomic formulas. *)
Inductive formula' : Set :=
| Atomic' : nat -> formula'
| Truth' : formula'
| Falsehood' : formula'
| And' : formula' -> formula' -> formula'
| Or' : formula' -> formula' -> formula'
| Imp' : formula' -> formula' -> formula'.
(** Note that, when we write our own Ltac procedure, we can work directly with the normal [->] operator, rather than needing to introduce a wrapper for it. *)
Ltac reifyTerm xs e :=
match e with
| True => constr:Truth'
| False => constr:Falsehood'
| ?e1 /\ ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(And' p1 p2)
| ?e1 \/ ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(Or' p1 p2)
| ?e1 -> ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(Imp' p1 p2)
| _ =>
let n := lookup e xs in
constr:(Atomic' n)
end.
(** Finally, we bring all the pieces together. *)
Ltac reify :=
match goal with
| [ |- ?G ] => let xs := allVars tt G in
let p := reifyTerm xs G in
pose p
end.
(** A quick test verifies that we are doing reification correctly. *)
Theorem mt3' : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
-> y > z /\ (x < y \/ x < S y).
do 3 intro; reify.
(** Our simple tactic adds the translated term as a new variable:
[[
f := Imp'
(Or' (And' (Atomic' 2) (Atomic' 1)) (And' (Atomic' 1) (Atomic' 0)))
(And' (Atomic' 1) (Or' (Atomic' 2) (Atomic' 0))) : formula'
]]
*)
Abort.
(** More work would be needed to complete the reflective tactic, as we must connect our new syntax type with the real meanings of formulas, but the details are the same as in our prior implementation with [quote]. *)
(* end thide *)
(** * Building a Reification Tactic that Recurses Under Binders *)
(** All of our examples so far have stayed away from reifying the syntax of terms that use such features as quantifiers and [fun] function abstractions. Such cases are complicated by the fact that different subterms may be allowed to reference different sets of free variables. Some cleverness is needed to clear this hurdle, but a few simple patterns will suffice. Consider this example of a simple dependently typed term language, where a function abstraction body is represented conveniently with a Coq function. *)
Inductive type : Type :=
| Nat : type
| NatFunc : type -> type.
Inductive term : type -> Type :=
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall t, (nat -> term t) -> term (NatFunc t).
Fixpoint typeDenote (t : type) : Type :=
match t with
| Nat => nat
| NatFunc t => nat -> typeDenote t
end.
Fixpoint termDenote t (e : term t) : typeDenote t :=
match e with
| Const n => n
| Plus e1 e2 => termDenote e1 + termDenote e2
| Abs _ e1 => fun x => termDenote (e1 x)
end.
(** Here is a %\%naive%{}% first attempt at a reification tactic. *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac refl' e :=
match e with
| ?E1 + ?E2 =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(Plus r1 r2)
| fun x : nat => ?E1 =>
let r1 := refl' E1 in
constr:(Abs (fun x => r1 x))
| _ => constr:(Const e)
end.
(** Recall that a regular Ltac pattern variable [?X] only matches terms that _do not mention new variables introduced within the pattern_. In our %\%naive%{}% implementation, the case for matching function abstractions matches the function body in a way that prevents it from mentioning the function argument! Our code above plays fast and loose with the function body in a way that leads to independent problems, but we could change the code so that it indeed handles function abstractions that ignore their arguments.
To handle functions in general, we will use the pattern variable form [@?X], which allows [X] to mention newly introduced variables that are declared explicitly. A use of [@?X] must be followed by a list of the local variables that may be mentioned. The variable [X] then comes to stand for a Gallina function over the values of those variables. For instance: *)
Reset refl'.
(* begin hide *)
Reset red_herring.
Definition red_herring := O.
(* end hide *)
Ltac refl' e :=
match e with
| ?E1 + ?E2 =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(Plus r1 r2)
| fun x : nat => @?E1 x =>
let r1 := refl' E1 in
constr:(Abs r1)
| _ => constr:(Const e)
end.
(** Now, in the abstraction case, we bind [E1] as a function from an [x] value to the value of the abstraction body. Unfortunately, our recursive call there is not destined for success. It will match the same abstraction pattern and trigger another recursive call, and so on through infinite recursion. One last refactoring yields a working procedure. The key idea is to consider every input to [refl'] as _a function over the values of variables introduced during recursion_. *)
Reset refl'.
(* begin hide *)
Reset red_herring.
(* end hide *)
Ltac refl' e :=
match eval simpl in e with
| fun x : ?T => @?E1 x + @?E2 x =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(fun x => Plus (r1 x) (r2 x))
| fun (x : ?T) (y : nat) => @?E1 x y =>
let r1 := refl' (fun p : T * nat => E1 (fst p) (snd p)) in
constr:(fun u => Abs (fun v => r1 (u, v)))
| _ => constr:(fun x => Const (e x))
end.
(** Note how now even the addition case works in terms of functions, with [@?X] patterns. The abstraction case introduces a new variable by extending the type used to represent the free variables. In particular, the argument to [refl'] used type [T] to represent all free variables. We extend the type to [T * nat] for the type representing free variable values within the abstraction body. A bit of bookkeeping with pairs and their projections produces an appropriate version of the abstraction body to pass in a recursive call. To ensure that all this repackaging of terms does not interfere with pattern matching, we add an extra [simpl] reduction on the function argument, in the first line of the body of [refl'].
Now one more tactic provides an example of how to apply reification. Let us consider goals that are equalities between terms that can be reified. We want to change such goals into equalities between appropriate calls to [termDenote]. *)
Ltac refl :=
match goal with
| [ |- ?E1 = ?E2 ] =>
let E1' := refl' (fun _ : unit => E1) in
let E2' := refl' (fun _ : unit => E2) in
change (termDenote (E1' tt) = termDenote (E2' tt));
cbv beta iota delta [fst snd]
end.
Goal (fun (x y : nat) => x + y + 13) = (fun (_ z : nat) => z).
refl.
(** %\vspace{-.15in}%[[
============================
termDenote
(Abs
(fun y : nat =>
Abs (fun y0 : nat => Plus (Plus (Const y) (Const y0)) (Const 13)))) =
termDenote (Abs (fun _ : nat => Abs (fun y0 : nat => Const y0)))
]]
*)
Abort.
(** Our encoding here uses Coq functions to represent binding within the terms we reify, which makes it difficult to implement certain functions over reified terms. An alternative would be to represent variables with numbers. This can be done by writing a slightly smarter reification function that identifies variable references by detecting when term arguments are just compositions of [fst] and [snd]; from the order of the compositions we may read off the variable number. We leave the details as an exercise (though not a trivial one!) for the reader. *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_MS__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_BLACKBOX_V
|
// nios_system.v
// Generated using ACDS version 14.1 186 at 2016.05.04.10:35:16
`timescale 1 ps / 1 ps
module nios_system (
output wire [31:0] alu_a_export, // alu_a.export
output wire [31:0] alu_b_export, // alu_b.export
input wire alu_carry_out_export, // alu_carry_out.export
output wire [2:0] alu_control_export, // alu_control.export
input wire alu_negative_export, // alu_negative.export
input wire [31:0] alu_out_export, // alu_out.export
input wire alu_overflow_export, // alu_overflow.export
input wire alu_zero_export, // alu_zero.export
input wire clk_clk, // clk.clk
output wire [3:0] hex_0_export, // hex_0.export
output wire [3:0] hex_1_export, // hex_1.export
output wire [3:0] hex_2_export, // hex_2.export
output wire [3:0] hex_3_export, // hex_3.export
output wire [3:0] hex_4_export, // hex_4.export
output wire [3:0] hex_5_export, // hex_5.export
input wire [3:0] keys_export, // keys.export
output wire [9:0] leds_export, // leds.export
output wire [31:0] regfile_data_export, // regfile_data.export
output wire [5:0] regfile_r1sel_export, // regfile_r1sel.export
output wire [5:0] regfile_r2sel_export, // regfile_r2sel.export
input wire [31:0] regfile_reg1_export, // regfile_reg1.export
input wire [31:0] regfile_reg2_export, // regfile_reg2.export
output wire regfile_we_export, // regfile_we.export
output wire [5:0] regfile_wsel_export, // regfile_wsel.export
input wire reset_reset_n, // reset.reset_n
output wire [10:0] sram_addr_export, // sram_addr.export
output wire sram_cs_export, // sram_cs.export
inout wire [15:0] sram_data_in_export, // sram_data_in.export
output wire sram_oe_export, // sram_oe.export
output wire sram_read_write_export, // sram_read_write.export
input wire [9:0] switches_export // switches.export
);
wire [31:0] nios2_qsys_0_data_master_readdata; // mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
wire nios2_qsys_0_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
wire [18:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
wire [31:0] nios2_qsys_0_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
wire nios2_qsys_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
wire [18:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata; // nios2_qsys_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest; // nios2_qsys_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_debugaccess -> nios2_qsys_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_address -> nios2_qsys_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_read -> nios2_qsys_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_byteenable -> nios2_qsys_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_write -> nios2_qsys_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_writedata -> nios2_qsys_0:debug_mem_slave_writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [14:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_leds_s1_chipselect; // mm_interconnect_0:LEDs_s1_chipselect -> LEDs:chipselect
wire [31:0] mm_interconnect_0_leds_s1_readdata; // LEDs:readdata -> mm_interconnect_0:LEDs_s1_readdata
wire [1:0] mm_interconnect_0_leds_s1_address; // mm_interconnect_0:LEDs_s1_address -> LEDs:address
wire mm_interconnect_0_leds_s1_write; // mm_interconnect_0:LEDs_s1_write -> LEDs:write_n
wire [31:0] mm_interconnect_0_leds_s1_writedata; // mm_interconnect_0:LEDs_s1_writedata -> LEDs:writedata
wire [31:0] mm_interconnect_0_switches_s1_readdata; // switches:readdata -> mm_interconnect_0:switches_s1_readdata
wire [1:0] mm_interconnect_0_switches_s1_address; // mm_interconnect_0:switches_s1_address -> switches:address
wire mm_interconnect_0_sram_data_s1_chipselect; // mm_interconnect_0:sram_data_s1_chipselect -> sram_data:chipselect
wire [31:0] mm_interconnect_0_sram_data_s1_readdata; // sram_data:readdata -> mm_interconnect_0:sram_data_s1_readdata
wire [1:0] mm_interconnect_0_sram_data_s1_address; // mm_interconnect_0:sram_data_s1_address -> sram_data:address
wire mm_interconnect_0_sram_data_s1_write; // mm_interconnect_0:sram_data_s1_write -> sram_data:write_n
wire [31:0] mm_interconnect_0_sram_data_s1_writedata; // mm_interconnect_0:sram_data_s1_writedata -> sram_data:writedata
wire mm_interconnect_0_sram_addr_s1_chipselect; // mm_interconnect_0:sram_addr_s1_chipselect -> sram_addr:chipselect
wire [31:0] mm_interconnect_0_sram_addr_s1_readdata; // sram_addr:readdata -> mm_interconnect_0:sram_addr_s1_readdata
wire [1:0] mm_interconnect_0_sram_addr_s1_address; // mm_interconnect_0:sram_addr_s1_address -> sram_addr:address
wire mm_interconnect_0_sram_addr_s1_write; // mm_interconnect_0:sram_addr_s1_write -> sram_addr:write_n
wire [31:0] mm_interconnect_0_sram_addr_s1_writedata; // mm_interconnect_0:sram_addr_s1_writedata -> sram_addr:writedata
wire mm_interconnect_0_sram_read_write_s1_chipselect; // mm_interconnect_0:sram_read_write_s1_chipselect -> sram_read_write:chipselect
wire [31:0] mm_interconnect_0_sram_read_write_s1_readdata; // sram_read_write:readdata -> mm_interconnect_0:sram_read_write_s1_readdata
wire [1:0] mm_interconnect_0_sram_read_write_s1_address; // mm_interconnect_0:sram_read_write_s1_address -> sram_read_write:address
wire mm_interconnect_0_sram_read_write_s1_write; // mm_interconnect_0:sram_read_write_s1_write -> sram_read_write:write_n
wire [31:0] mm_interconnect_0_sram_read_write_s1_writedata; // mm_interconnect_0:sram_read_write_s1_writedata -> sram_read_write:writedata
wire mm_interconnect_0_sram_cs_s1_chipselect; // mm_interconnect_0:sram_cs_s1_chipselect -> sram_cs:chipselect
wire [31:0] mm_interconnect_0_sram_cs_s1_readdata; // sram_cs:readdata -> mm_interconnect_0:sram_cs_s1_readdata
wire [1:0] mm_interconnect_0_sram_cs_s1_address; // mm_interconnect_0:sram_cs_s1_address -> sram_cs:address
wire mm_interconnect_0_sram_cs_s1_write; // mm_interconnect_0:sram_cs_s1_write -> sram_cs:write_n
wire [31:0] mm_interconnect_0_sram_cs_s1_writedata; // mm_interconnect_0:sram_cs_s1_writedata -> sram_cs:writedata
wire mm_interconnect_0_sram_oe_s1_chipselect; // mm_interconnect_0:sram_oe_s1_chipselect -> sram_oe:chipselect
wire [31:0] mm_interconnect_0_sram_oe_s1_readdata; // sram_oe:readdata -> mm_interconnect_0:sram_oe_s1_readdata
wire [1:0] mm_interconnect_0_sram_oe_s1_address; // mm_interconnect_0:sram_oe_s1_address -> sram_oe:address
wire mm_interconnect_0_sram_oe_s1_write; // mm_interconnect_0:sram_oe_s1_write -> sram_oe:write_n
wire [31:0] mm_interconnect_0_sram_oe_s1_writedata; // mm_interconnect_0:sram_oe_s1_writedata -> sram_oe:writedata
wire mm_interconnect_0_regfile_data_s1_chipselect; // mm_interconnect_0:regfile_data_s1_chipselect -> regfile_data:chipselect
wire [31:0] mm_interconnect_0_regfile_data_s1_readdata; // regfile_data:readdata -> mm_interconnect_0:regfile_data_s1_readdata
wire [1:0] mm_interconnect_0_regfile_data_s1_address; // mm_interconnect_0:regfile_data_s1_address -> regfile_data:address
wire mm_interconnect_0_regfile_data_s1_write; // mm_interconnect_0:regfile_data_s1_write -> regfile_data:write_n
wire [31:0] mm_interconnect_0_regfile_data_s1_writedata; // mm_interconnect_0:regfile_data_s1_writedata -> regfile_data:writedata
wire [31:0] mm_interconnect_0_regfile_reg1_s1_readdata; // regfile_reg1:readdata -> mm_interconnect_0:regfile_reg1_s1_readdata
wire [1:0] mm_interconnect_0_regfile_reg1_s1_address; // mm_interconnect_0:regfile_reg1_s1_address -> regfile_reg1:address
wire [31:0] mm_interconnect_0_regfile_reg2_s1_readdata; // regfile_reg2:readdata -> mm_interconnect_0:regfile_reg2_s1_readdata
wire [1:0] mm_interconnect_0_regfile_reg2_s1_address; // mm_interconnect_0:regfile_reg2_s1_address -> regfile_reg2:address
wire mm_interconnect_0_regfile_r1sel_s1_chipselect; // mm_interconnect_0:regfile_r1sel_s1_chipselect -> regfile_r1sel:chipselect
wire [31:0] mm_interconnect_0_regfile_r1sel_s1_readdata; // regfile_r1sel:readdata -> mm_interconnect_0:regfile_r1sel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_r1sel_s1_address; // mm_interconnect_0:regfile_r1sel_s1_address -> regfile_r1sel:address
wire mm_interconnect_0_regfile_r1sel_s1_write; // mm_interconnect_0:regfile_r1sel_s1_write -> regfile_r1sel:write_n
wire [31:0] mm_interconnect_0_regfile_r1sel_s1_writedata; // mm_interconnect_0:regfile_r1sel_s1_writedata -> regfile_r1sel:writedata
wire mm_interconnect_0_regfile_r2sel_s1_chipselect; // mm_interconnect_0:regfile_r2sel_s1_chipselect -> regfile_r2sel:chipselect
wire [31:0] mm_interconnect_0_regfile_r2sel_s1_readdata; // regfile_r2sel:readdata -> mm_interconnect_0:regfile_r2sel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_r2sel_s1_address; // mm_interconnect_0:regfile_r2sel_s1_address -> regfile_r2sel:address
wire mm_interconnect_0_regfile_r2sel_s1_write; // mm_interconnect_0:regfile_r2sel_s1_write -> regfile_r2sel:write_n
wire [31:0] mm_interconnect_0_regfile_r2sel_s1_writedata; // mm_interconnect_0:regfile_r2sel_s1_writedata -> regfile_r2sel:writedata
wire mm_interconnect_0_regfile_wsel_s1_chipselect; // mm_interconnect_0:regfile_wsel_s1_chipselect -> regfile_wsel:chipselect
wire [31:0] mm_interconnect_0_regfile_wsel_s1_readdata; // regfile_wsel:readdata -> mm_interconnect_0:regfile_wsel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_wsel_s1_address; // mm_interconnect_0:regfile_wsel_s1_address -> regfile_wsel:address
wire mm_interconnect_0_regfile_wsel_s1_write; // mm_interconnect_0:regfile_wsel_s1_write -> regfile_wsel:write_n
wire [31:0] mm_interconnect_0_regfile_wsel_s1_writedata; // mm_interconnect_0:regfile_wsel_s1_writedata -> regfile_wsel:writedata
wire mm_interconnect_0_regfile_we_s1_chipselect; // mm_interconnect_0:regfile_we_s1_chipselect -> regfile_we:chipselect
wire [31:0] mm_interconnect_0_regfile_we_s1_readdata; // regfile_we:readdata -> mm_interconnect_0:regfile_we_s1_readdata
wire [1:0] mm_interconnect_0_regfile_we_s1_address; // mm_interconnect_0:regfile_we_s1_address -> regfile_we:address
wire mm_interconnect_0_regfile_we_s1_write; // mm_interconnect_0:regfile_we_s1_write -> regfile_we:write_n
wire [31:0] mm_interconnect_0_regfile_we_s1_writedata; // mm_interconnect_0:regfile_we_s1_writedata -> regfile_we:writedata
wire mm_interconnect_0_hex_0_s1_chipselect; // mm_interconnect_0:hex_0_s1_chipselect -> hex_0:chipselect
wire [31:0] mm_interconnect_0_hex_0_s1_readdata; // hex_0:readdata -> mm_interconnect_0:hex_0_s1_readdata
wire [1:0] mm_interconnect_0_hex_0_s1_address; // mm_interconnect_0:hex_0_s1_address -> hex_0:address
wire mm_interconnect_0_hex_0_s1_write; // mm_interconnect_0:hex_0_s1_write -> hex_0:write_n
wire [31:0] mm_interconnect_0_hex_0_s1_writedata; // mm_interconnect_0:hex_0_s1_writedata -> hex_0:writedata
wire mm_interconnect_0_hex_1_s1_chipselect; // mm_interconnect_0:hex_1_s1_chipselect -> hex_1:chipselect
wire [31:0] mm_interconnect_0_hex_1_s1_readdata; // hex_1:readdata -> mm_interconnect_0:hex_1_s1_readdata
wire [1:0] mm_interconnect_0_hex_1_s1_address; // mm_interconnect_0:hex_1_s1_address -> hex_1:address
wire mm_interconnect_0_hex_1_s1_write; // mm_interconnect_0:hex_1_s1_write -> hex_1:write_n
wire [31:0] mm_interconnect_0_hex_1_s1_writedata; // mm_interconnect_0:hex_1_s1_writedata -> hex_1:writedata
wire mm_interconnect_0_hex_2_s1_chipselect; // mm_interconnect_0:hex_2_s1_chipselect -> hex_2:chipselect
wire [31:0] mm_interconnect_0_hex_2_s1_readdata; // hex_2:readdata -> mm_interconnect_0:hex_2_s1_readdata
wire [1:0] mm_interconnect_0_hex_2_s1_address; // mm_interconnect_0:hex_2_s1_address -> hex_2:address
wire mm_interconnect_0_hex_2_s1_write; // mm_interconnect_0:hex_2_s1_write -> hex_2:write_n
wire [31:0] mm_interconnect_0_hex_2_s1_writedata; // mm_interconnect_0:hex_2_s1_writedata -> hex_2:writedata
wire mm_interconnect_0_hex_3_s1_chipselect; // mm_interconnect_0:hex_3_s1_chipselect -> hex_3:chipselect
wire [31:0] mm_interconnect_0_hex_3_s1_readdata; // hex_3:readdata -> mm_interconnect_0:hex_3_s1_readdata
wire [1:0] mm_interconnect_0_hex_3_s1_address; // mm_interconnect_0:hex_3_s1_address -> hex_3:address
wire mm_interconnect_0_hex_3_s1_write; // mm_interconnect_0:hex_3_s1_write -> hex_3:write_n
wire [31:0] mm_interconnect_0_hex_3_s1_writedata; // mm_interconnect_0:hex_3_s1_writedata -> hex_3:writedata
wire mm_interconnect_0_hex_4_s1_chipselect; // mm_interconnect_0:hex_4_s1_chipselect -> hex_4:chipselect
wire [31:0] mm_interconnect_0_hex_4_s1_readdata; // hex_4:readdata -> mm_interconnect_0:hex_4_s1_readdata
wire [1:0] mm_interconnect_0_hex_4_s1_address; // mm_interconnect_0:hex_4_s1_address -> hex_4:address
wire mm_interconnect_0_hex_4_s1_write; // mm_interconnect_0:hex_4_s1_write -> hex_4:write_n
wire [31:0] mm_interconnect_0_hex_4_s1_writedata; // mm_interconnect_0:hex_4_s1_writedata -> hex_4:writedata
wire mm_interconnect_0_hex_5_s1_chipselect; // mm_interconnect_0:hex_5_s1_chipselect -> hex_5:chipselect
wire [31:0] mm_interconnect_0_hex_5_s1_readdata; // hex_5:readdata -> mm_interconnect_0:hex_5_s1_readdata
wire [1:0] mm_interconnect_0_hex_5_s1_address; // mm_interconnect_0:hex_5_s1_address -> hex_5:address
wire mm_interconnect_0_hex_5_s1_write; // mm_interconnect_0:hex_5_s1_write -> hex_5:write_n
wire [31:0] mm_interconnect_0_hex_5_s1_writedata; // mm_interconnect_0:hex_5_s1_writedata -> hex_5:writedata
wire mm_interconnect_0_alu_a_s1_chipselect; // mm_interconnect_0:alu_a_s1_chipselect -> alu_a:chipselect
wire [31:0] mm_interconnect_0_alu_a_s1_readdata; // alu_a:readdata -> mm_interconnect_0:alu_a_s1_readdata
wire [1:0] mm_interconnect_0_alu_a_s1_address; // mm_interconnect_0:alu_a_s1_address -> alu_a:address
wire mm_interconnect_0_alu_a_s1_write; // mm_interconnect_0:alu_a_s1_write -> alu_a:write_n
wire [31:0] mm_interconnect_0_alu_a_s1_writedata; // mm_interconnect_0:alu_a_s1_writedata -> alu_a:writedata
wire mm_interconnect_0_alu_b_s1_chipselect; // mm_interconnect_0:alu_b_s1_chipselect -> alu_b:chipselect
wire [31:0] mm_interconnect_0_alu_b_s1_readdata; // alu_b:readdata -> mm_interconnect_0:alu_b_s1_readdata
wire [1:0] mm_interconnect_0_alu_b_s1_address; // mm_interconnect_0:alu_b_s1_address -> alu_b:address
wire mm_interconnect_0_alu_b_s1_write; // mm_interconnect_0:alu_b_s1_write -> alu_b:write_n
wire [31:0] mm_interconnect_0_alu_b_s1_writedata; // mm_interconnect_0:alu_b_s1_writedata -> alu_b:writedata
wire mm_interconnect_0_alu_control_s1_chipselect; // mm_interconnect_0:alu_control_s1_chipselect -> alu_control:chipselect
wire [31:0] mm_interconnect_0_alu_control_s1_readdata; // alu_control:readdata -> mm_interconnect_0:alu_control_s1_readdata
wire [1:0] mm_interconnect_0_alu_control_s1_address; // mm_interconnect_0:alu_control_s1_address -> alu_control:address
wire mm_interconnect_0_alu_control_s1_write; // mm_interconnect_0:alu_control_s1_write -> alu_control:write_n
wire [31:0] mm_interconnect_0_alu_control_s1_writedata; // mm_interconnect_0:alu_control_s1_writedata -> alu_control:writedata
wire [31:0] mm_interconnect_0_alu_out_s1_readdata; // alu_out:readdata -> mm_interconnect_0:alu_out_s1_readdata
wire [1:0] mm_interconnect_0_alu_out_s1_address; // mm_interconnect_0:alu_out_s1_address -> alu_out:address
wire [31:0] mm_interconnect_0_alu_zero_s1_readdata; // alu_zero:readdata -> mm_interconnect_0:alu_zero_s1_readdata
wire [1:0] mm_interconnect_0_alu_zero_s1_address; // mm_interconnect_0:alu_zero_s1_address -> alu_zero:address
wire [31:0] mm_interconnect_0_alu_overflow_s1_readdata; // alu_overflow:readdata -> mm_interconnect_0:alu_overflow_s1_readdata
wire [1:0] mm_interconnect_0_alu_overflow_s1_address; // mm_interconnect_0:alu_overflow_s1_address -> alu_overflow:address
wire [31:0] mm_interconnect_0_alu_carry_out_s1_readdata; // alu_carry_out:readdata -> mm_interconnect_0:alu_carry_out_s1_readdata
wire [1:0] mm_interconnect_0_alu_carry_out_s1_address; // mm_interconnect_0:alu_carry_out_s1_address -> alu_carry_out:address
wire [31:0] mm_interconnect_0_alu_negative_s1_readdata; // alu_negative:readdata -> mm_interconnect_0:alu_negative_s1_readdata
wire [1:0] mm_interconnect_0_alu_negative_s1_address; // mm_interconnect_0:alu_negative_s1_address -> alu_negative:address
wire [31:0] mm_interconnect_0_keys_s1_readdata; // keys:readdata -> mm_interconnect_0:keys_s1_readdata
wire [1:0] mm_interconnect_0_keys_s1_address; // mm_interconnect_0:keys_s1_address -> keys:address
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_qsys_0_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDs:reset_n, alu_a:reset_n, alu_b:reset_n, alu_carry_out:reset_n, alu_control:reset_n, alu_negative:reset_n, alu_out:reset_n, alu_overflow:reset_n, alu_zero:reset_n, hex_0:reset_n, hex_1:reset_n, hex_2:reset_n, hex_3:reset_n, hex_4:reset_n, hex_5:reset_n, irq_mapper:reset, jtag_uart_0:rst_n, keys:reset_n, mm_interconnect_0:nios2_qsys_0_reset_reset_bridge_in_reset_reset, nios2_qsys_0:reset_n, onchip_memory2_0:reset, regfile_data:reset_n, regfile_r1sel:reset_n, regfile_r2sel:reset_n, regfile_reg1:reset_n, regfile_reg2:reset_n, regfile_we:reset_n, regfile_wsel:reset_n, rst_translator:in_reset, sram_addr:reset_n, sram_cs:reset_n, sram_data:reset_n, sram_oe:reset_n, sram_read_write:reset_n, switches:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire nios2_qsys_0_debug_reset_request_reset; // nios2_qsys_0:debug_reset_request -> rst_controller:reset_in1
nios_system_LEDs leds (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_leds_s1_address), // s1.address
.write_n (~mm_interconnect_0_leds_s1_write), // .write_n
.writedata (mm_interconnect_0_leds_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_leds_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_leds_s1_readdata), // .readdata
.out_port (leds_export) // external_connection.export
);
nios_system_alu_a alu_a (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_a_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_a_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_a_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_a_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_a_s1_readdata), // .readdata
.out_port (alu_a_export) // external_connection.export
);
nios_system_alu_a alu_b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_b_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_b_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_b_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_b_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_b_s1_readdata), // .readdata
.out_port (alu_b_export) // external_connection.export
);
nios_system_alu_carry_out alu_carry_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_carry_out_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_carry_out_s1_readdata), // .readdata
.in_port (alu_carry_out_export) // external_connection.export
);
nios_system_alu_control alu_control (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_control_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_control_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_control_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_control_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_control_s1_readdata), // .readdata
.out_port (alu_control_export) // external_connection.export
);
nios_system_alu_carry_out alu_negative (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_negative_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_negative_s1_readdata), // .readdata
.in_port (alu_negative_export) // external_connection.export
);
nios_system_alu_out alu_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_out_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_out_s1_readdata), // .readdata
.in_port (alu_out_export) // external_connection.export
);
nios_system_alu_carry_out alu_overflow (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_overflow_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_overflow_s1_readdata), // .readdata
.in_port (alu_overflow_export) // external_connection.export
);
nios_system_alu_carry_out alu_zero (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_zero_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_zero_s1_readdata), // .readdata
.in_port (alu_zero_export) // external_connection.export
);
nios_system_hex_0 hex_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_0_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_0_s1_readdata), // .readdata
.out_port (hex_0_export) // external_connection.export
);
nios_system_hex_0 hex_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_1_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_1_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_1_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_1_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_1_s1_readdata), // .readdata
.out_port (hex_1_export) // external_connection.export
);
nios_system_hex_0 hex_2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_2_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_2_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_2_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_2_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_2_s1_readdata), // .readdata
.out_port (hex_2_export) // external_connection.export
);
nios_system_hex_0 hex_3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_3_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_3_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_3_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_3_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_3_s1_readdata), // .readdata
.out_port (hex_3_export) // external_connection.export
);
nios_system_hex_0 hex_4 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_4_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_4_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_4_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_4_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_4_s1_readdata), // .readdata
.out_port (hex_4_export) // external_connection.export
);
nios_system_hex_0 hex_5 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_5_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_5_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_5_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_5_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_5_s1_readdata), // .readdata
.out_port (hex_5_export) // external_connection.export
);
nios_system_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
nios_system_keys keys (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_keys_s1_address), // s1.address
.readdata (mm_interconnect_0_keys_s1_readdata), // .readdata
.in_port (keys_export) // external_connection.export
);
nios_system_nios2_qsys_0 nios2_qsys_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_qsys_0_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_0_data_master_read), // .read
.d_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_0_data_master_write), // .write
.d_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_0_instruction_master_read), // .read
.i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_qsys_0_irq_irq), // irq.irq
.debug_reset_request (nios2_qsys_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
nios_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
nios_system_alu_a regfile_data (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_data_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_data_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_data_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_data_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_data_s1_readdata), // .readdata
.out_port (regfile_data_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_r1sel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_r1sel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_r1sel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_r1sel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_r1sel_s1_readdata), // .readdata
.out_port (regfile_r1sel_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_r2sel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_r2sel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_r2sel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_r2sel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_r2sel_s1_readdata), // .readdata
.out_port (regfile_r2sel_export) // external_connection.export
);
nios_system_alu_out regfile_reg1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_reg1_s1_address), // s1.address
.readdata (mm_interconnect_0_regfile_reg1_s1_readdata), // .readdata
.in_port (regfile_reg1_export) // external_connection.export
);
nios_system_alu_out regfile_reg2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_reg2_s1_address), // s1.address
.readdata (mm_interconnect_0_regfile_reg2_s1_readdata), // .readdata
.in_port (regfile_reg2_export) // external_connection.export
);
nios_system_regfile_we regfile_we (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_we_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_we_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_we_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_we_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_we_s1_readdata), // .readdata
.out_port (regfile_we_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_wsel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_wsel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_wsel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_wsel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_wsel_s1_readdata), // .readdata
.out_port (regfile_wsel_export) // external_connection.export
);
nios_system_sram_addr sram_addr (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_addr_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_addr_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_addr_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_addr_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_addr_s1_readdata), // .readdata
.out_port (sram_addr_export) // external_connection.export
);
nios_system_regfile_we sram_cs (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_cs_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_cs_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_cs_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_cs_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_cs_s1_readdata), // .readdata
.out_port (sram_cs_export) // external_connection.export
);
nios_system_sram_data sram_data (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_data_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_data_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_data_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_data_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_data_s1_readdata), // .readdata
.bidir_port (sram_data_in_export) // external_connection.export
);
nios_system_regfile_we sram_oe (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_oe_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_oe_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_oe_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_oe_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_oe_s1_readdata), // .readdata
.out_port (sram_oe_export) // external_connection.export
);
nios_system_regfile_we sram_read_write (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_read_write_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_read_write_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_read_write_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_read_write_s1_readdata), // .readdata
.out_port (sram_read_write_export) // external_connection.export
);
nios_system_switches switches (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_switches_s1_address), // s1.address
.readdata (mm_interconnect_0_switches_s1_readdata), // .readdata
.in_port (switches_export) // external_connection.export
);
nios_system_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_qsys_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_0_reset_reset_bridge_in_reset.reset
.nios2_qsys_0_data_master_address (nios2_qsys_0_data_master_address), // nios2_qsys_0_data_master.address
.nios2_qsys_0_data_master_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.nios2_qsys_0_data_master_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.nios2_qsys_0_data_master_read (nios2_qsys_0_data_master_read), // .read
.nios2_qsys_0_data_master_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.nios2_qsys_0_data_master_write (nios2_qsys_0_data_master_write), // .write
.nios2_qsys_0_data_master_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.nios2_qsys_0_data_master_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.nios2_qsys_0_instruction_master_address (nios2_qsys_0_instruction_master_address), // nios2_qsys_0_instruction_master.address
.nios2_qsys_0_instruction_master_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.nios2_qsys_0_instruction_master_read (nios2_qsys_0_instruction_master_read), // .read
.nios2_qsys_0_instruction_master_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.alu_a_s1_address (mm_interconnect_0_alu_a_s1_address), // alu_a_s1.address
.alu_a_s1_write (mm_interconnect_0_alu_a_s1_write), // .write
.alu_a_s1_readdata (mm_interconnect_0_alu_a_s1_readdata), // .readdata
.alu_a_s1_writedata (mm_interconnect_0_alu_a_s1_writedata), // .writedata
.alu_a_s1_chipselect (mm_interconnect_0_alu_a_s1_chipselect), // .chipselect
.alu_b_s1_address (mm_interconnect_0_alu_b_s1_address), // alu_b_s1.address
.alu_b_s1_write (mm_interconnect_0_alu_b_s1_write), // .write
.alu_b_s1_readdata (mm_interconnect_0_alu_b_s1_readdata), // .readdata
.alu_b_s1_writedata (mm_interconnect_0_alu_b_s1_writedata), // .writedata
.alu_b_s1_chipselect (mm_interconnect_0_alu_b_s1_chipselect), // .chipselect
.alu_carry_out_s1_address (mm_interconnect_0_alu_carry_out_s1_address), // alu_carry_out_s1.address
.alu_carry_out_s1_readdata (mm_interconnect_0_alu_carry_out_s1_readdata), // .readdata
.alu_control_s1_address (mm_interconnect_0_alu_control_s1_address), // alu_control_s1.address
.alu_control_s1_write (mm_interconnect_0_alu_control_s1_write), // .write
.alu_control_s1_readdata (mm_interconnect_0_alu_control_s1_readdata), // .readdata
.alu_control_s1_writedata (mm_interconnect_0_alu_control_s1_writedata), // .writedata
.alu_control_s1_chipselect (mm_interconnect_0_alu_control_s1_chipselect), // .chipselect
.alu_negative_s1_address (mm_interconnect_0_alu_negative_s1_address), // alu_negative_s1.address
.alu_negative_s1_readdata (mm_interconnect_0_alu_negative_s1_readdata), // .readdata
.alu_out_s1_address (mm_interconnect_0_alu_out_s1_address), // alu_out_s1.address
.alu_out_s1_readdata (mm_interconnect_0_alu_out_s1_readdata), // .readdata
.alu_overflow_s1_address (mm_interconnect_0_alu_overflow_s1_address), // alu_overflow_s1.address
.alu_overflow_s1_readdata (mm_interconnect_0_alu_overflow_s1_readdata), // .readdata
.alu_zero_s1_address (mm_interconnect_0_alu_zero_s1_address), // alu_zero_s1.address
.alu_zero_s1_readdata (mm_interconnect_0_alu_zero_s1_readdata), // .readdata
.hex_0_s1_address (mm_interconnect_0_hex_0_s1_address), // hex_0_s1.address
.hex_0_s1_write (mm_interconnect_0_hex_0_s1_write), // .write
.hex_0_s1_readdata (mm_interconnect_0_hex_0_s1_readdata), // .readdata
.hex_0_s1_writedata (mm_interconnect_0_hex_0_s1_writedata), // .writedata
.hex_0_s1_chipselect (mm_interconnect_0_hex_0_s1_chipselect), // .chipselect
.hex_1_s1_address (mm_interconnect_0_hex_1_s1_address), // hex_1_s1.address
.hex_1_s1_write (mm_interconnect_0_hex_1_s1_write), // .write
.hex_1_s1_readdata (mm_interconnect_0_hex_1_s1_readdata), // .readdata
.hex_1_s1_writedata (mm_interconnect_0_hex_1_s1_writedata), // .writedata
.hex_1_s1_chipselect (mm_interconnect_0_hex_1_s1_chipselect), // .chipselect
.hex_2_s1_address (mm_interconnect_0_hex_2_s1_address), // hex_2_s1.address
.hex_2_s1_write (mm_interconnect_0_hex_2_s1_write), // .write
.hex_2_s1_readdata (mm_interconnect_0_hex_2_s1_readdata), // .readdata
.hex_2_s1_writedata (mm_interconnect_0_hex_2_s1_writedata), // .writedata
.hex_2_s1_chipselect (mm_interconnect_0_hex_2_s1_chipselect), // .chipselect
.hex_3_s1_address (mm_interconnect_0_hex_3_s1_address), // hex_3_s1.address
.hex_3_s1_write (mm_interconnect_0_hex_3_s1_write), // .write
.hex_3_s1_readdata (mm_interconnect_0_hex_3_s1_readdata), // .readdata
.hex_3_s1_writedata (mm_interconnect_0_hex_3_s1_writedata), // .writedata
.hex_3_s1_chipselect (mm_interconnect_0_hex_3_s1_chipselect), // .chipselect
.hex_4_s1_address (mm_interconnect_0_hex_4_s1_address), // hex_4_s1.address
.hex_4_s1_write (mm_interconnect_0_hex_4_s1_write), // .write
.hex_4_s1_readdata (mm_interconnect_0_hex_4_s1_readdata), // .readdata
.hex_4_s1_writedata (mm_interconnect_0_hex_4_s1_writedata), // .writedata
.hex_4_s1_chipselect (mm_interconnect_0_hex_4_s1_chipselect), // .chipselect
.hex_5_s1_address (mm_interconnect_0_hex_5_s1_address), // hex_5_s1.address
.hex_5_s1_write (mm_interconnect_0_hex_5_s1_write), // .write
.hex_5_s1_readdata (mm_interconnect_0_hex_5_s1_readdata), // .readdata
.hex_5_s1_writedata (mm_interconnect_0_hex_5_s1_writedata), // .writedata
.hex_5_s1_chipselect (mm_interconnect_0_hex_5_s1_chipselect), // .chipselect
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.keys_s1_address (mm_interconnect_0_keys_s1_address), // keys_s1.address
.keys_s1_readdata (mm_interconnect_0_keys_s1_readdata), // .readdata
.LEDs_s1_address (mm_interconnect_0_leds_s1_address), // LEDs_s1.address
.LEDs_s1_write (mm_interconnect_0_leds_s1_write), // .write
.LEDs_s1_readdata (mm_interconnect_0_leds_s1_readdata), // .readdata
.LEDs_s1_writedata (mm_interconnect_0_leds_s1_writedata), // .writedata
.LEDs_s1_chipselect (mm_interconnect_0_leds_s1_chipselect), // .chipselect
.nios2_qsys_0_debug_mem_slave_address (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address), // nios2_qsys_0_debug_mem_slave.address
.nios2_qsys_0_debug_mem_slave_write (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write), // .write
.nios2_qsys_0_debug_mem_slave_read (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read), // .read
.nios2_qsys_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.nios2_qsys_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.nios2_qsys_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.nios2_qsys_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_qsys_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.regfile_data_s1_address (mm_interconnect_0_regfile_data_s1_address), // regfile_data_s1.address
.regfile_data_s1_write (mm_interconnect_0_regfile_data_s1_write), // .write
.regfile_data_s1_readdata (mm_interconnect_0_regfile_data_s1_readdata), // .readdata
.regfile_data_s1_writedata (mm_interconnect_0_regfile_data_s1_writedata), // .writedata
.regfile_data_s1_chipselect (mm_interconnect_0_regfile_data_s1_chipselect), // .chipselect
.regfile_r1sel_s1_address (mm_interconnect_0_regfile_r1sel_s1_address), // regfile_r1sel_s1.address
.regfile_r1sel_s1_write (mm_interconnect_0_regfile_r1sel_s1_write), // .write
.regfile_r1sel_s1_readdata (mm_interconnect_0_regfile_r1sel_s1_readdata), // .readdata
.regfile_r1sel_s1_writedata (mm_interconnect_0_regfile_r1sel_s1_writedata), // .writedata
.regfile_r1sel_s1_chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), // .chipselect
.regfile_r2sel_s1_address (mm_interconnect_0_regfile_r2sel_s1_address), // regfile_r2sel_s1.address
.regfile_r2sel_s1_write (mm_interconnect_0_regfile_r2sel_s1_write), // .write
.regfile_r2sel_s1_readdata (mm_interconnect_0_regfile_r2sel_s1_readdata), // .readdata
.regfile_r2sel_s1_writedata (mm_interconnect_0_regfile_r2sel_s1_writedata), // .writedata
.regfile_r2sel_s1_chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), // .chipselect
.regfile_reg1_s1_address (mm_interconnect_0_regfile_reg1_s1_address), // regfile_reg1_s1.address
.regfile_reg1_s1_readdata (mm_interconnect_0_regfile_reg1_s1_readdata), // .readdata
.regfile_reg2_s1_address (mm_interconnect_0_regfile_reg2_s1_address), // regfile_reg2_s1.address
.regfile_reg2_s1_readdata (mm_interconnect_0_regfile_reg2_s1_readdata), // .readdata
.regfile_we_s1_address (mm_interconnect_0_regfile_we_s1_address), // regfile_we_s1.address
.regfile_we_s1_write (mm_interconnect_0_regfile_we_s1_write), // .write
.regfile_we_s1_readdata (mm_interconnect_0_regfile_we_s1_readdata), // .readdata
.regfile_we_s1_writedata (mm_interconnect_0_regfile_we_s1_writedata), // .writedata
.regfile_we_s1_chipselect (mm_interconnect_0_regfile_we_s1_chipselect), // .chipselect
.regfile_wsel_s1_address (mm_interconnect_0_regfile_wsel_s1_address), // regfile_wsel_s1.address
.regfile_wsel_s1_write (mm_interconnect_0_regfile_wsel_s1_write), // .write
.regfile_wsel_s1_readdata (mm_interconnect_0_regfile_wsel_s1_readdata), // .readdata
.regfile_wsel_s1_writedata (mm_interconnect_0_regfile_wsel_s1_writedata), // .writedata
.regfile_wsel_s1_chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), // .chipselect
.sram_addr_s1_address (mm_interconnect_0_sram_addr_s1_address), // sram_addr_s1.address
.sram_addr_s1_write (mm_interconnect_0_sram_addr_s1_write), // .write
.sram_addr_s1_readdata (mm_interconnect_0_sram_addr_s1_readdata), // .readdata
.sram_addr_s1_writedata (mm_interconnect_0_sram_addr_s1_writedata), // .writedata
.sram_addr_s1_chipselect (mm_interconnect_0_sram_addr_s1_chipselect), // .chipselect
.sram_cs_s1_address (mm_interconnect_0_sram_cs_s1_address), // sram_cs_s1.address
.sram_cs_s1_write (mm_interconnect_0_sram_cs_s1_write), // .write
.sram_cs_s1_readdata (mm_interconnect_0_sram_cs_s1_readdata), // .readdata
.sram_cs_s1_writedata (mm_interconnect_0_sram_cs_s1_writedata), // .writedata
.sram_cs_s1_chipselect (mm_interconnect_0_sram_cs_s1_chipselect), // .chipselect
.sram_data_s1_address (mm_interconnect_0_sram_data_s1_address), // sram_data_s1.address
.sram_data_s1_write (mm_interconnect_0_sram_data_s1_write), // .write
.sram_data_s1_readdata (mm_interconnect_0_sram_data_s1_readdata), // .readdata
.sram_data_s1_writedata (mm_interconnect_0_sram_data_s1_writedata), // .writedata
.sram_data_s1_chipselect (mm_interconnect_0_sram_data_s1_chipselect), // .chipselect
.sram_oe_s1_address (mm_interconnect_0_sram_oe_s1_address), // sram_oe_s1.address
.sram_oe_s1_write (mm_interconnect_0_sram_oe_s1_write), // .write
.sram_oe_s1_readdata (mm_interconnect_0_sram_oe_s1_readdata), // .readdata
.sram_oe_s1_writedata (mm_interconnect_0_sram_oe_s1_writedata), // .writedata
.sram_oe_s1_chipselect (mm_interconnect_0_sram_oe_s1_chipselect), // .chipselect
.sram_read_write_s1_address (mm_interconnect_0_sram_read_write_s1_address), // sram_read_write_s1.address
.sram_read_write_s1_write (mm_interconnect_0_sram_read_write_s1_write), // .write
.sram_read_write_s1_readdata (mm_interconnect_0_sram_read_write_s1_readdata), // .readdata
.sram_read_write_s1_writedata (mm_interconnect_0_sram_read_write_s1_writedata), // .writedata
.sram_read_write_s1_chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), // .chipselect
.switches_s1_address (mm_interconnect_0_switches_s1_address), // switches_s1.address
.switches_s1_readdata (mm_interconnect_0_switches_s1_readdata) // .readdata
);
nios_system_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_qsys_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_0_debug_reset_request_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_BEHAVIORAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: oq_header_parser.v
// Project: NF2.1
// Description: finds the destination port in the module headers and puts it in fifo
//
///////////////////////////////////////////////////////////////////////////////
module oq_header_parser
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter OP_LUT_STAGE_NUM = 4,
parameter IOQ_STAGE_NUM = `IO_QUEUE_STAGE_NUM,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter MAX_PKT = 2048, // allow for 2K bytes
parameter PKT_BYTE_CNT_WIDTH = log2(MAX_PKT),
parameter PKT_WORD_CNT_WIDTH = log2(MAX_PKT/CTRL_WIDTH)
)
(
parsed_dst_oq,
parsed_pkt_byte_len,
parsed_pkt_word_len,
header_parser_rdy,
dst_oq_avail,
rd_dst_oq,
in_wr,
in_ctrl,
in_data,
clk,
reset
);
output [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
output [PKT_BYTE_CNT_WIDTH-1:0] parsed_pkt_byte_len;
output [PKT_WORD_CNT_WIDTH-1:0] parsed_pkt_word_len;
output header_parser_rdy;
output dst_oq_avail;
input rd_dst_oq;
input in_wr;
input [CTRL_WIDTH-1:0] in_ctrl;
input [DATA_WIDTH-1:0] in_data;
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------- Internal parameters -----------------
parameter NUM_INPUT_STATES = 3;
parameter IN_WAIT_DST_PORT_LENGTH = 1;
parameter IN_WAIT_PKT_DATA = 2;
parameter IN_WAIT_EOP = 4;
//---------------------- Regs/Wires -----------------------
reg [NUM_INPUT_STATES-1:0] input_state;
reg [NUM_INPUT_STATES-1:0] input_state_next;
reg [NUM_OQ_WIDTH-1:0] dst_oq_encoded;
wire [PKT_BYTE_CNT_WIDTH-1:0]pkt_byte_len;
wire [PKT_WORD_CNT_WIDTH-1:0]pkt_word_len;
reg wr_en;
wire empty;
wire full;
//----------------------- Module --------------------------
fallthrough_small_fifo
#(
.WIDTH(NUM_OQ_WIDTH + PKT_BYTE_CNT_WIDTH + PKT_WORD_CNT_WIDTH)
)
dst_oq_fifo
(
.din ({pkt_word_len, pkt_byte_len, dst_oq_encoded}), // Data in
.wr_en (wr_en), // Write enable
.rd_en (rd_dst_oq), // Read the next word
.dout ({parsed_pkt_word_len, parsed_pkt_byte_len, parsed_dst_oq}),
.full (full),
.prog_full (),
.nearly_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic --------------------------
assign header_parser_rdy = !full;
assign dst_oq_avail = !empty;
/*********************************************************
* As data comes in, look for the dst port and queue it
*********************************************************/
always @(*) begin
wr_en = 0;
input_state_next = input_state;
case(input_state)
IN_WAIT_DST_PORT_LENGTH: begin
if(in_wr && in_ctrl==IOQ_STAGE_NUM) begin
wr_en = 1;
input_state_next = IN_WAIT_PKT_DATA;
end
end // case: IP_WAIT_DST_PORT
IN_WAIT_PKT_DATA: begin
if(in_wr && in_ctrl==0) begin
input_state_next = IN_WAIT_EOP;
end
end
IN_WAIT_EOP: begin
if(in_wr && in_ctrl != 0) begin
input_state_next = IN_WAIT_DST_PORT_LENGTH;
end
end
endcase // case(input_process_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
input_state <= IN_WAIT_DST_PORT_LENGTH;
end
else begin
input_state <= input_state_next;
end
// synthesis translate_off
if(in_wr && in_ctrl==0 && input_state==IN_WAIT_DST_PORT_LENGTH) begin
$display("%t %m **** ERROR: Did not find dst port", $time);
$stop;
end
// synthesis translate_on
end
/*
* get the binary form of the destination port
*/
always @(*) begin
dst_oq_encoded = 'h0;
case(in_data[`IOQ_DST_PORT_POS + NUM_OUTPUT_QUEUES - 1:`IOQ_DST_PORT_POS])
'h0: dst_oq_encoded = 'h0;
'h1: dst_oq_encoded = 'h0;
'h2: dst_oq_encoded = 'h1;
'h4: dst_oq_encoded = 'h2;
'h8: dst_oq_encoded = 'h3;
'h10: dst_oq_encoded = 'h4;
'h20: dst_oq_encoded = 'h5;
'h40: dst_oq_encoded = 'h6;
'h80: dst_oq_encoded = 'h7;
'h100: dst_oq_encoded = 'h8;
'h200: dst_oq_encoded = 'h9;
'h400: dst_oq_encoded = 'ha;
'h800: dst_oq_encoded = 'hb;
'h1000: dst_oq_encoded = 'hc;
'h2000: dst_oq_encoded = 'hd;
'h4000: dst_oq_encoded = 'he;
'h8000: dst_oq_encoded = 'hf;
endcase // case(in_data[NUM_OQ_WIDTH-1:0])
end
assign pkt_byte_len = in_data[`IOQ_BYTE_LEN_POS + PKT_BYTE_CNT_WIDTH-1:`IOQ_BYTE_LEN_POS];
assign pkt_word_len = in_data[`IOQ_WORD_LEN_POS + PKT_WORD_CNT_WIDTH-1:`IOQ_WORD_LEN_POS];
endmodule // header_parser
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SREGRBP_FUNCTIONAL_V
/**
* sregrbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
// Local signals
wire buf_Q ;
wire reset ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (reset , ASYNC );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, reset);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//*************************************************************************
// > ÎļþÃû: single_cycle_cpu_display.v
// > ÃèÊö £ºµ¥ÖÜÆÚCPUÏÔʾģ¿é£¬µ÷ÓÃFPGA°åÉϵÄIO½Ó¿ÚºÍ´¥ÃþÆÁ
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module mips_display(
//ʱÖÓÓ븴λÐźÅ
input clk,
input resetn, //ºó׺"n"´ú±íµÍµçƽÓÐЧ
//Âö³å¿ª¹Ø£¬ÓÃÓÚ²úÉúÂö³åclk£¬ÊµÏÖµ¥²½Ö´ÐÐ
input btn_clk,
//´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{ʱÖӺ͸´Î»ÐźÅ}begin
//²»ÐèÒª¸ü¸Ä£¬ÓÃÓÚµ¥²½µ÷ÊÔ
wire cpu_clk; //µ¥ÖÜÆÚCPUÀïʹÓÃÂö³å¿ª¹Ø×÷ΪʱÖÓ£¬ÒÔʵÏÖµ¥²½Ö´ÐÐ
reg btn_clk_r1;
reg btn_clk_r2;
always @(posedge clk)
begin
if (!resetn)
begin
btn_clk_r1<= 1'b0;
end
else
begin
btn_clk_r1 <= ~btn_clk;
end
btn_clk_r2 <= btn_clk_r1;
end
wire clk_en;
assign clk_en = !resetn || (!btn_clk_r1 && btn_clk_r2);
BUFGCE cpu_clk_cg(.I(clk),.CE(clk_en),.O(cpu_clk));
//-----{ʱÖӺ͸´Î»ÐźÅ}end
//-----{µ÷Óõ¥ÖÜÆÚCPUÄ£¿é}begin
//ÓÃÓÚÔÚFPGA°åÉÏÏÔʾ½á¹û
wire [31:0] cpu_pc; //CPUµÄPC
wire [31:0] cpu_inst; //¸ÃPCÈ¡³öµÄÖ¸Áî
wire [ 4:0] rf_addr; //ɨÃè¼Ä´æÆ÷¶ÑµÄµØÖ·
wire [31:0] rf_data; //¼Ä´æÆ÷¶Ñ´Óµ÷ÊԶ˿ڶÁ³öµÄÊý¾Ý
reg [31:0] mem_addr; //Òª¹Û²ìµÄÄÚ´æµØÖ·
wire [31:0] mem_data; //ÄÚ´æµØÖ·¶ÔÓ¦µÄÊý¾Ý
wire [ 4:0] cop_addr;
wire [31:0] cop_data;
wire [31:0] hi_data;
wire [31:0] lo_data;
mips cpu(
.clk(cpu_clk ),
.rst(resetn ),
.rf_addr (rf_addr ),
.mem_addr(mem_addr),
.rf_data (rf_data ),
.mem_data(mem_data),
.cpu_pc (cpu_pc ),
.cpu_inst(cpu_inst),
.cop_addr(cop_addr),
.cop_data(cop_data),
.hi_data(hi_data),
.lo_data(lo_data)
);
//-----{µ÷Óõ¥ÖÜÆÚCPUÄ£¿é}end
//---------------------{µ÷Óô¥ÃþÆÁÄ£¿é}begin--------------------//
//-----{ʵÀý»¯´¥ÃþÆÁ}begin
//´ËС½Ú²»ÐèÒª¸ü¸Ä
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//µ÷Óô¥ÃþÆÁµÄ½Ó¿Ú
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{ʵÀý»¯´¥ÃþÆÁ}end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}begin
//¸ù¾Ýʵ¼ÊÐèÒªÊäÈëµÄÊýÐ޸ĴËС½Ú£¬
//½¨Òé¶Ôÿһ¸öÊýµÄÊäÈ룬±àдµ¥¶ÀÒ»¸öalways¿é
always @(posedge clk)
begin
if (!resetn)
begin
mem_addr <= 32'd0;
end
else if (input_valid)
begin
mem_addr <= input_value;
end
end
assign rf_addr = display_number-6'd5;
assign cop_addr = display_number - 6'd25;
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}begin
//¸ù¾ÝÐèÒªÏÔʾµÄÊýÐ޸ĴËС½Ú£¬
//´¥ÃþÆÁÉϹ²ÓÐ44¿éÏÔʾÇøÓò£¬¿ÉÏÔʾ44×é32λÊý¾Ý
//44¿éÏÔʾÇøÓò´Ó1¿ªÊ¼±àºÅ£¬±àºÅΪ1~44£¬
always @(posedge clk)
begin
if (display_number >6'd4 && display_number <6'd37 )
begin //¿éºÅ5~36ÏÔʾ32¸öͨÓüĴæÆ÷µÄÖµ
display_valid <= 1'b1;
display_name[39:16] <= "REG";
display_name[15: 8] <= {4'b0011,3'b000,rf_addr[4]};
display_name[7 : 0] <= {4'b0011,rf_addr[3:0]};
display_value <= rf_data;
end
else if (display_number > 6'd36 && display_number < 6'd41) begin
display_valid <= 1'b1;
display_name[39:16] <= "COP";
display_name[15:8] <= "0";
display_name[7 : 0] <= {4'b0011,cop_addr[3:0]};
display_value <= cop_data;
end
else if (display_number == 6'd41) begin
display_valid <= 1'b1;
display_name <= " HI";
display_value <= hi_data;
end
else if (display_number == 6'd42) begin
display_valid <= 1'b1;
display_name <= " LO";
display_value <= lo_data;
end
else
begin
case(display_number)
6'd1 : //ÏÔʾPCÖµ
begin
display_valid <= 1'b1;
display_name <= " PC";
display_value <= cpu_pc;
end
6'd2 : //ÏÔʾPCÈ¡³öµÄÖ¸Áî
begin
display_valid <= 1'b1;
display_name <= " INST";
display_value <= cpu_inst;
end
6'd3 : //ÏÔʾҪ¹Û²ìµÄÄÚ´æµØÖ·
begin
display_valid <= 1'b1;
display_name <= "MADDR";
display_value <= mem_addr;
end
6'd4 : //ÏÔʾ¸ÃÄÚ´æµØÖ·¶ÔÓ¦µÄÊý¾Ý
begin
display_valid <= 1'b1;
display_name <= "MDATA";
display_value <= mem_data;
end
default :
begin
display_valid <= 1'b0;
end
endcase
end
end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}end
//----------------------{µ÷Óô¥ÃþÆÁÄ£¿é}end---------------------//
endmodule
|
`timescale 1 ns / 1 ps
module AXI4LiteToRFBridgeVerilog #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 32,
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32
)
(
// Users to add ports here
output wire [C_S_AXI_ADDR_WIDTH-1 : 0] rf_raddr,
output wire [C_S_AXI_ADDR_WIDTH-1 : 0] rf_waddr,
output wire rf_wen,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] rf_wdata,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] rf_rdata,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 16;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 8
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
// reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
wire slv_reg_rden;
wire slv_reg_wren;
// reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
// integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
assign rf_wen = slv_reg_wren;
//assign rf_waddr = axi_awaddr;
assign rf_waddr = axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB];
assign rf_wdata = S_AXI_WDATA;
// always @( posedge S_AXI_ACLK )
// begin
// if ( S_AXI_ARESETN == 1'b0 )
// begin
// slv_reg0 <= 0;
// slv_reg1 <= 0;
// slv_reg2 <= 0;
// slv_reg3 <= 0;
// slv_reg4 <= 0;
// slv_reg5 <= 0;
// slv_reg6 <= 0;
// slv_reg7 <= 0;
// end
// else begin
// if (slv_reg_wren)
// begin
// case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
// 3'h0:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 0
// slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h1:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 1
// slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h2:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 2
// slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h3:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 3
// slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h4:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 4
// slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h5:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 5
// slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h6:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 6
// slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// 3'h7:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// // Respective byte enables are asserted as per write strobes
// // Slave register 7
// slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
// default : begin
// slv_reg0 <= slv_reg0;
// slv_reg1 <= slv_reg1;
// slv_reg2 <= slv_reg2;
// slv_reg3 <= slv_reg3;
// slv_reg4 <= slv_reg4;
// slv_reg5 <= slv_reg5;
// slv_reg6 <= slv_reg6;
// slv_reg7 <= slv_reg7;
// end
// endcase
// end
// end
// end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// assign rf_raddr = axi_araddr;
assign rf_raddr = axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB];
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
// RAGHU: rf_rdata drives axi_rdata
// always @(*)
// begin
// // Address decoding for reading registers
// case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
// 3'h0 : reg_data_out <= slv_reg0;
// 3'h1 : reg_data_out <= slv_reg1;
// 3'h2 : reg_data_out <= slv_reg2;
// 3'h3 : reg_data_out <= slv_reg3;
// 3'h4 : reg_data_out <= slv_reg4;
// 3'h5 : reg_data_out <= slv_reg5;
// 3'h6 : reg_data_out <= slv_reg6;
// 3'h7 : reg_data_out <= slv_reg7;
// default : reg_data_out <= 0;
// endcase
// end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
// axi_rdata <= reg_data_out; // register read data
axi_rdata <= rf_rdata; // register read data
// axi_rdata <= 420;
end
end
end
// Add user logic here
// User logic ends
endmodule
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output mux_lo, output mux_hi,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop = conf_word[1];
// divide subcarrier frequency by 4
wire hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
hi_sniffer he(
pck0, ck_1356meg, ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, ssp_dout, he_ssp_clk,
cross_hi, cross_lo,
he_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
// Major modes:
// 000 -- HF reader, transmitting to tag; modulation depth selectable
// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 010 -- HF simulated tag
// 011 -- HF ISO14443-A
// 100 -- HF Snoop
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, he_dbg, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
// Mux for proxmark3lcd
assign mux_hi = (!major_mode[2] && major_mode[1]) || (major_mode[2] && !major_mode[1]);
assign mux_lo = ~mux_hi;
endmodule
|
module microfono_TB;
reg reset, clk, micData;
microfono uut(.reset(reset),.micData(micData),.clk(clk));
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
reset =1'b1;
#10000;
reset =1'b0;
end
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
end
initial begin: TEST_CASE
$dumpfile("microfono_TB.vcd");
$dumpvars(-1, uut);
#(100000) $finish;
end
endmodule //
|
`timescale 1ns / 1ps
/*
* File : IDEX_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ([email protected])
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Instruction Decode
* and Execute stages.
*/
module IDEX_Stage(
input clock,
input reset,
input ID_Flush,
input ID_Stall,
input EX_Stall,
// Control Signals
input ID_Link,
input ID_RegDst,
input ID_ALUSrcImm,
input [4:0] ID_ALUOp,
input ID_Movn,
input ID_Movz,
input ID_LLSC,
input ID_MemRead,
input ID_MemWrite,
input ID_MemByte,
input ID_MemHalf,
input ID_MemSignExtend,
input ID_Left,
input ID_Right,
input ID_RegWrite,
input ID_MemtoReg,
input ID_ReverseEndian,
// Hazard & Forwarding
input [4:0] ID_Rs,
input [4:0] ID_Rt,
input ID_WantRsByEX,
input ID_NeedRsByEX,
input ID_WantRtByEX,
input ID_NeedRtByEX,
// Exception Control/Info
input ID_KernelMode,
input [31:0] ID_RestartPC,
input ID_IsBDS,
input ID_Trap,
input ID_TrapCond,
input ID_EX_CanErr,
input ID_M_CanErr,
// Data Signals
input [31:0] ID_ReadData1,
input [31:0] ID_ReadData2,
input [16:0] ID_SignExtImm, // ID_Rd, ID_Shamt included here
// ----------------
output [4:0] EX_Rd,
output [4:0] EX_Shamt,
output [1:0] EX_LinkRegDst,
output [31:0] EX_SignExtImm,
// Voter Signals for Registers
input [16:0] EX_SignExtImm_pre,
input EX_RegDst,
input EX_Link,
input EX_ALUSrcImm,
input [4:0] EX_ALUOp,
input EX_Movn,
input EX_Movz,
input EX_LLSC,
input EX_MemRead,
input EX_MemWrite,
input EX_MemByte,
input EX_MemHalf,
input EX_MemSignExtend,
input EX_Left,
input EX_Right,
input EX_RegWrite,
input EX_MemtoReg,
input EX_ReverseEndian,
input [4:0] EX_Rs,
input [4:0] EX_Rt,
input EX_WantRsByEX,
input EX_NeedRsByEX,
input EX_WantRtByEX,
input EX_NeedRtByEX,
input EX_KernelMode,
input [31:0] EX_RestartPC,
input EX_IsBDS,
input EX_Trap,
input EX_TrapCond,
input EX_EX_CanErr,
input EX_M_CanErr,
input [31:0] EX_ReadData1,
input [31:0] EX_ReadData2,
output reg [16:0] vote_EX_SignExtImm_pre,
output reg vote_EX_RegDst,
output reg vote_EX_Link,
output reg vote_EX_ALUSrcImm,
output reg [4:0] vote_EX_ALUOp,
output reg vote_EX_Movn,
output reg vote_EX_Movz,
output reg vote_EX_LLSC,
output reg vote_EX_MemRead,
output reg vote_EX_MemWrite,
output reg vote_EX_MemByte,
output reg vote_EX_MemHalf,
output reg vote_EX_MemSignExtend,
output reg vote_EX_Left,
output reg vote_EX_Right,
output reg vote_EX_RegWrite,
output reg vote_EX_MemtoReg,
output reg vote_EX_ReverseEndian,
output reg [4:0] vote_EX_Rs,
output reg [4:0] vote_EX_Rt,
output reg vote_EX_WantRsByEX,
output reg vote_EX_NeedRsByEX,
output reg vote_EX_WantRtByEX,
output reg vote_EX_NeedRtByEX,
output reg vote_EX_KernelMode,
output reg [31:0] vote_EX_RestartPC,
output reg vote_EX_IsBDS,
output reg vote_EX_Trap,
output reg vote_EX_TrapCond,
output reg vote_EX_EX_CanErr,
output reg vote_EX_M_CanErr,
output reg [31:0] vote_EX_ReadData1,
output reg [31:0] vote_EX_ReadData2
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
***/
assign EX_LinkRegDst = (EX_Link) ? 2'b10 : ((EX_RegDst) ? 2'b01 : 2'b00);
assign EX_Rd = EX_SignExtImm[15:11];
assign EX_Shamt = EX_SignExtImm[10:6];
assign EX_SignExtImm = (EX_SignExtImm_pre[16]) ? {15'h7fff, EX_SignExtImm_pre[16:0]} : {15'h0000, EX_SignExtImm_pre[16:0]};
always @(posedge clock) begin
vote_EX_Link <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Link : ID_Link);
vote_EX_RegDst <= (reset) ? 1'b0 : ((EX_Stall) ? EX_RegDst : ID_RegDst);
vote_EX_ALUSrcImm <= (reset) ? 1'b0 : ((EX_Stall) ? EX_ALUSrcImm : ID_ALUSrcImm);
vote_EX_ALUOp <= (reset) ? 5'b0 : ((EX_Stall) ? EX_ALUOp : ((ID_Stall | ID_Flush) ? 5'b0 : ID_ALUOp));
vote_EX_Movn <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Movn : ID_Movn);
vote_EX_Movz <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Movz : ID_Movz);
vote_EX_LLSC <= (reset) ? 1'b0 : ((EX_Stall) ? EX_LLSC : ID_LLSC);
vote_EX_MemRead <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemRead : ((ID_Stall | ID_Flush) ? 1'b0 : ID_MemRead));
vote_EX_MemWrite <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemWrite : ((ID_Stall | ID_Flush) ? 1'b0 : ID_MemWrite));
vote_EX_MemByte <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemByte : ID_MemByte);
vote_EX_MemHalf <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemHalf : ID_MemHalf);
vote_EX_MemSignExtend <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemSignExtend : ID_MemSignExtend);
vote_EX_Left <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Left : ID_Left);
vote_EX_Right <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Right : ID_Right);
vote_EX_RegWrite <= (reset) ? 1'b0 : ((EX_Stall) ? EX_RegWrite : ((ID_Stall | ID_Flush) ? 1'b0 : ID_RegWrite));
vote_EX_MemtoReg <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemtoReg : ID_MemtoReg);
vote_EX_ReverseEndian <= (reset) ? 1'b0 : ((EX_Stall) ? EX_ReverseEndian : ID_ReverseEndian);
vote_EX_RestartPC <= (reset) ? 32'b0 : ((EX_Stall) ? EX_RestartPC : ID_RestartPC);
vote_EX_IsBDS <= (reset) ? 1'b0 : ((EX_Stall) ? EX_IsBDS : ID_IsBDS);
vote_EX_Trap <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Trap : ((ID_Stall | ID_Flush) ? 1'b0 : ID_Trap));
vote_EX_TrapCond <= (reset) ? 1'b0 : ((EX_Stall) ? EX_TrapCond : ID_TrapCond);
vote_EX_EX_CanErr <= (reset) ? 1'b0 : ((EX_Stall) ? EX_EX_CanErr : ((ID_Stall | ID_Flush) ? 1'b0 : ID_EX_CanErr));
vote_EX_M_CanErr <= (reset) ? 1'b0 : ((EX_Stall) ? EX_M_CanErr : ((ID_Stall | ID_Flush) ? 1'b0 : ID_M_CanErr));
vote_EX_ReadData1 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData1 : ID_ReadData1);
vote_EX_ReadData2 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData2 : ID_ReadData2);
vote_EX_SignExtImm_pre <= (reset) ? 17'b0 : ((EX_Stall) ? EX_SignExtImm_pre : ID_SignExtImm);
vote_EX_Rs <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rs : ID_Rs);
vote_EX_Rt <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rt : ID_Rt);
vote_EX_WantRsByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_WantRsByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_WantRsByEX));
vote_EX_NeedRsByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_NeedRsByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_NeedRsByEX));
vote_EX_WantRtByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_WantRtByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_WantRtByEX));
vote_EX_NeedRtByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_NeedRtByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_NeedRtByEX));
vote_EX_KernelMode <= (reset) ? 1'b0 : ((EX_Stall) ? EX_KernelMode : ID_KernelMode);
end
endmodule
|
module sound(
input clk,
input rst,
input en,
input wr_en,
input [15:0] data_in,
output snd_out,
output [3:0] snd_signals);
wire snd1,snd2,snd3,snd4;
wire s1_en, s2_en, s3_en, s4_en;
reg [3:0] sigma1 = 0;
reg [4:0] sigma3 = 0;
assign snd_signals = {snd4,snd3,snd2,snd1};
assign snd_out = sigma1[3];
//assign snd_out = snd1 ^ snd2;
reg [13:0] c1_divider = 0;
reg [13:0] c2_divider = 0;
reg [13:0] c3_divider = 0;
reg [13:0] c4_divider = 0;
assign s1_en = c1_divider != 0;
assign s2_en = c2_divider != 0;
assign s3_en = c3_divider != 0;
assign s4_en = c4_divider != 0;
always @(posedge clk) begin
if(rst == 1) begin
c1_divider <= 0;
c2_divider <= 0;
c3_divider <= 0;
c4_divider <= 0;
end
else if(wr_en == 1)
case(data_in[15:14])
2'b00:
c1_divider <= data_in[13:0];
2'b01:
c2_divider <= data_in[13:0];
2'b10:
c3_divider <= data_in[13:0];
2'b11:
c4_divider <= data_in[13:0];
endcase
sigma1 <= sigma1[2:0] + snd1+snd2+snd3+snd4;
sigma3 <= sigma3[2:0] + (s1_en ? (snd1 ? 1 : -1): 0) + (s2_en ? (snd2 ? 1 : -1) : 0) + 4;
//sigma2 <= sigma2[1:0] + snd3+snd4;
end
channel channel1(
// Outputs
.snd (snd1),
// Inputs
.clk (clk),
.rst (rst),
.divider (c1_divider[13:0]));
channel channel2(
// Outputs
.snd (snd2),
// Inputs
.clk (clk),
.rst (rst),
.divider (c2_divider[13:0]));
channel channel3(
// Outputs
.snd (snd3),
// Inputs
.clk (clk),
.rst (rst),
.divider (c3_divider[13:0]));
channel channel4(
// Outputs
.snd (snd4),
// Inputs
.clk (clk),
.rst (rst),
.divider (c4_divider[13:0]));
endmodule
module channel(
input clk,
input rst,
input [13:0] divider,
output reg snd);
reg [18:0] counter;
always @(posedge clk) begin
if(rst == 1) begin
snd <= 0;
counter <= 0;
end
if(counter == 0) begin
counter <= {divider,5'b0};
if(divider != 0)
snd <= ~snd;
end
else
counter <= counter - 1;
end
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200.000000, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0\
, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "system_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog wrapper for lpflow_inputiso0n with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_inputiso0n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_inputiso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n_1 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_inputiso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_tdd_cntrl (
clk,
rst,
//rf tdd interface control
tdd_enable,
tdd_secondary,
tdd_rx_only,
tdd_tx_only,
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_terminal_type,
tdd_sync_enable,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00010001;
parameter ID = 0;
input clk;
input rst;
output tdd_enable;
output tdd_secondary;
output tdd_rx_only;
output tdd_tx_only;
output tdd_gated_rx_dmapath;
output tdd_gated_tx_dmapath;
output [ 7:0] tdd_burst_count;
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
output tdd_terminal_type;
output tdd_sync_enable;
output [23:0] tdd_vco_rx_on_1;
output [23:0] tdd_vco_rx_off_1;
output [23:0] tdd_vco_tx_on_1;
output [23:0] tdd_vco_tx_off_1;
output [23:0] tdd_rx_on_1;
output [23:0] tdd_rx_off_1;
output [23:0] tdd_tx_on_1;
output [23:0] tdd_tx_off_1;
output [23:0] tdd_tx_dp_on_1;
output [23:0] tdd_tx_dp_off_1;
output [23:0] tdd_vco_rx_on_2;
output [23:0] tdd_vco_rx_off_2;
output [23:0] tdd_vco_tx_on_2;
output [23:0] tdd_vco_tx_off_2;
output [23:0] tdd_rx_on_2;
output [23:0] tdd_rx_off_2;
output [23:0] tdd_tx_on_2;
output [23:0] tdd_tx_off_2;
output [23:0] tdd_tx_dp_on_2;
output [23:0] tdd_tx_dp_off_2;
input [ 7:0] tdd_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 1'h0;
reg [31:0] up_scratch = 32'h0;
reg up_rack = 1'h0;
reg [31:0] up_rdata = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_secondary = 1'h0;
reg up_tdd_rx_only = 1'h0;
reg up_tdd_tx_only = 1'h0;
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
reg up_tdd_terminal_type = 1'h0;
reg up_tdd_sync_enable = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
reg [23:0] up_tdd_frame_length = 24'h0;
reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 7:0] up_tdd_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
up_tdd_rx_only <= 1'h0;
up_tdd_tx_only <= 1'h0;
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
up_tdd_terminal_type <= 1'h0;
up_tdd_sync_enable <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
up_tdd_vco_rx_on_1 <= 24'h0;
up_tdd_vco_rx_off_1 <= 24'h0;
up_tdd_vco_tx_on_1 <= 24'h0;
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
up_tdd_rx_only <= up_wdata[2];
up_tdd_tx_only <= up_wdata[3];
up_tdd_gated_rx_dmapath <= up_wdata[4];
up_tdd_gated_tx_dmapath <= up_wdata[5];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_burst_count <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_counter_init <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_tdd_frame_length <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_terminal_type <= up_wdata[1];
up_tdd_sync_enable <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_tdd_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
up_tdd_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
up_tdd_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
up_tdd_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
up_tdd_vco_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
up_tdd_vco_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_tdd_vco_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_tdd_vco_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
up_tdd_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
up_tdd_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
up_tdd_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 1'b0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
up_tdd_gated_rx_dmapath,
up_tdd_tx_only,
up_tdd_rx_only,
up_tdd_secondary,
up_tdd_enable};
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
8'h14: up_rdata <= {30'h0, up_tdd_terminal_type,
up_tdd_sync_enable};
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
default: up_rdata <= 32'h0;
endcase
end
end
end
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(16)) i_xfer_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_secondary,
up_tdd_rx_only,
up_tdd_tx_only,
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
up_tdd_burst_count,
up_tdd_terminal_type,
up_tdd_sync_enable
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_secondary,
tdd_rx_only,
tdd_tx_only,
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count,
tdd_terminal_type,
tdd_sync_enable
}));
up_xfer_cntrl #(.DATA_WIDTH(528)) i_xfer_tdd_counter_values (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length,
up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1,
up_tdd_vco_tx_off_1,
up_tdd_rx_on_1,
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
up_tdd_vco_rx_off_2,
up_tdd_vco_tx_on_2,
up_tdd_vco_tx_off_2,
up_tdd_rx_on_2,
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));
up_xfer_status #(.DATA_WIDTH(8)) i_xfer_tdd_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
.d_rst (rst),
.d_clk (clk),
.d_data_status (tdd_status));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ea_e
//
// Generated
// by: wig
// on: Tue Mar 30 18:39:52 2004
// cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ea_e.v,v 1.2 2006/01/19 08:50:42 wig Exp $
// $Date: 2006/01/19 08:50:42 $
// $Log: inst_ea_e.v,v $
// Revision 1.2 2006/01/19 08:50:42 wig
// Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
//
// Revision 1.1 2004/04/06 11:19:55 wig
// Adding result/autoopen
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
//
// Generator: mix_0.pl Revision: 1.28 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ea_e
//
// No `defines in this module
module inst_ea_e
//
// Generated module inst_ea
//
(
p_mix_s_eo1_go,
p_mix_s_eo2_go,
p_mix_s_eo3_go,
p_mix_s_eo4_gi,
p_mix_s_eo5_go
);
// Generated Module Inputs:
input p_mix_s_eo4_gi;
// Generated Module Outputs:
output p_mix_s_eo1_go;
output p_mix_s_eo2_go;
output p_mix_s_eo3_go;
output p_mix_s_eo5_go;
// Generated Wires:
wire p_mix_s_eo1_go;
wire p_mix_s_eo2_go;
wire p_mix_s_eo3_go;
wire p_mix_s_eo4_gi;
wire p_mix_s_eo5_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire s_eo1; // __W_PORT_SIGNAL_MAP_REQ
wire s_eo2; // __W_PORT_SIGNAL_MAP_REQ
wire s_eo3; // __W_PORT_SIGNAL_MAP_REQ
wire s_eo4; // __W_PORT_SIGNAL_MAP_REQ
wire s_eo5; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_s_eo1_go = s_eo1; // __I_O_BIT_PORT
assign p_mix_s_eo2_go = s_eo2; // __I_O_BIT_PORT
assign p_mix_s_eo3_go = s_eo3; // __I_O_BIT_PORT
assign s_eo4 = p_mix_s_eo4_gi; // __I_I_SLICE_PORT // __I_SINGLE_BIT (0)
assign p_mix_s_eo5_go = s_eo5; // __I_O_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_eaa
inst_eaa_e inst_eaa(
.s_eo1(s_eo1),
.s_eo2(s_eo2),
.s_eo3(s_eo3),
.s_eo4(s_eo4),
.s_eo5(s_eo5)
);
// End of Generated Instance Port Map for inst_eaa
// Generated Instance Port Map for inst_eab
inst_eab_e inst_eab(
);
// End of Generated Instance Port Map for inst_eab
// Generated Instance Port Map for inst_eac
inst_eac_e inst_eac(
);
// End of Generated Instance Port Map for inst_eac
endmodule
//
// End of Generated Module rtl of inst_ea_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:35:03 06/30/2013
// Design Name: qadd
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Tes_add.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+5179347; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + 3779351;
end
end
end
endmodule
|
`timescale 1ns / 1ps
module shift_acc(
input shift_enable,
input load,
input clear,
input sclk,
input [39:0] blk_in,
output [39:0] blk_out
);
reg [39:0] shift_acc_reg;
always @(posedge sclk)
begin
if (clear)
shift_acc_reg = 40'd0;
if (load && shift_enable)
shift_acc_reg = {blk_in[39], blk_in[39:1]};
else if (load && !shift_enable)
shift_acc_reg = blk_in;
else
shift_acc_reg = shift_acc_reg;
end
assign blk_out = shift_acc_reg;
endmodule
module rj_memory (input wr_en, rd_en, Sclk,
input [3:0] rj_wr_addr, rj_rd_addr,
input [15:0] data_in,
output [15:0] rj_data);
reg [15:0] rj_mem [0:15];
always @(negedge Sclk)
begin
if(wr_en == 1'b1)
rj_mem[rj_wr_addr] = data_in;
else
rj_mem[rj_wr_addr] = rj_mem[rj_wr_addr];
end
assign rj_data = (rd_en) ? rj_mem[rj_rd_addr] : 16'd0;
endmodule
module PISO (Sclk, Clear, Frame, Shifted, Serial_out, p2s_enable, OutReady);
input Sclk, Clear, p2s_enable, Frame;
input [39:0] Shifted;
output reg Serial_out, OutReady;
reg [5:0] bit_count;
reg out_rdy, frame_flag;
reg [39:0] piso_reg;
always @(negedge Sclk)
begin
if(Clear == 1'b1)
begin
bit_count = 6'd40;
piso_reg = 40'd0;
out_rdy = 1'b0;
frame_flag = 1'b0;
OutReady = 1'b0;
Serial_out = 1'b0;
end
else if (p2s_enable == 1'b1)
begin
piso_reg = Shifted;
out_rdy = 1'b1;
end
else if (Frame == 1'b1 && out_rdy == 1'b1 && frame_flag == 1'b0)
begin
bit_count = bit_count - 1'b1;
Serial_out = piso_reg [bit_count];
frame_flag = 1'b1;
out_rdy = 1'b0;
OutReady = 1'b1;
end
else if (frame_flag == 1'b1)
begin
bit_count = bit_count - 1'b1;
Serial_out = piso_reg [bit_count];
OutReady = 1'b1;
if (bit_count == 6'd0)
frame_flag = 1'b0;
end
else
begin
bit_count = 6'd40;
//piso_reg = 40'd0;
//out_rdy = 1'b0;
//frame_flag = 1'b0;
Serial_out = 1'b0;
OutReady = 1'b0;
end
end
endmodule
module MSDAP_controller (input Sclk, Dclk, Start, Reset_n, Frame, input_rdy_flag, zero_flag_L, zero_flag_R,
output reg [3:0] rj_wr_addr,
output reg [8:0] coeff_wr_addr,
output reg [7:0] data_wr_addr,
output reg rj_en, coeff_en, data_en, Clear,
output Frame_out, Dclk_out, Sclk_out,
output reg compute_enable, sleep_flag, InReady);
parameter [3:0] Startup = 4'd0, Wait_rj = 4'd1, Read_rj = 4'd2,
Wait_coeff = 4'd3, Read_coeff = 4'd4, Wait_input = 4'd5,
Compute = 4'd6, Reset = 4'd7, Sleep = 4'd8;
reg [3:0] pr_state, next_state;
reg [15:0] real_count;
reg [4:0] rj_count;
reg [9:0] coeff_count;
reg [7:0] data_count;
reg taken;
assign Frame_out = Frame;
assign Dclk_out = Dclk;
assign Sclk_out = Sclk;
always @(negedge Sclk or negedge Reset_n) // Sequential block
begin
if (!Reset_n)
begin
if (pr_state > 4'd4)
pr_state = Reset;
else
pr_state = next_state;
end
else
pr_state = next_state;
end
always @(negedge Sclk or posedge Start)
begin
if (Start == 1'b1)
next_state = Startup;
else
begin
case (pr_state)
Startup: begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
data_wr_addr = 8'd0;
rj_en = 1'b0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b1;
compute_enable = 1'b0;
InReady = 1'b0;
sleep_flag = 1'b0;
next_state = Wait_rj;
real_count = 16'd0;
rj_count = 4'd0;
coeff_count = 9'd0;
data_count = 8'd0;
end
Wait_rj: begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
data_wr_addr = 8'd0;
rj_en = 1'b0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b0;
compute_enable = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b0;
rj_count = 4'd0;
coeff_count = 9'd0;
data_count = 8'd0;
taken = 1'b0;
if (Frame == 1'b1)
next_state = Read_rj;
else
next_state = Wait_rj;
end
Read_rj: begin
coeff_wr_addr = 9'd0;
data_wr_addr = 8'd0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b0;
compute_enable = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b0;
coeff_count = 9'd0;
data_count = 8'd0;
if (input_rdy_flag == 1'b1 && taken == 1'b0)
begin
if (rj_count < 5'd16)
begin
rj_en = 1'b1;
rj_wr_addr = rj_count;
rj_count = rj_count + 1'b1;
next_state = Read_rj;
taken = 1'b1;
end
if (rj_count == 5'd16)
begin
next_state = Wait_coeff;
end
else
next_state = Read_rj;
end
else if (input_rdy_flag == 1'b0)
begin
taken = 1'b0;
rj_en = 1'b0;
rj_wr_addr = rj_wr_addr;
next_state = Read_rj;
end
else
next_state = Read_rj;
end
Wait_coeff:
begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
data_wr_addr = 8'd0;
rj_en = 1'b0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b0;
compute_enable = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b0;
coeff_count = 9'd0;
data_count = 8'd0;
if (Frame == 1'b1)
next_state = Read_coeff;
else
next_state = Wait_coeff;
end
Read_coeff: begin
rj_wr_addr = 4'd0;
data_wr_addr = 8'd0;
rj_en = 1'b0;
data_en = 1'b0;
Clear = 1'b0;
compute_enable = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b0;
data_count = 8'd0;
if (input_rdy_flag == 1'b1 && taken == 1'b0)
begin
if (coeff_count < 10'h200)
begin
coeff_en = 1'b1;
coeff_wr_addr = coeff_count;
coeff_count = coeff_count + 1'b1;
next_state = Read_coeff;
taken = 1'b1;
end
if (coeff_count == 10'h200)
next_state = Wait_input;
else
next_state = Read_coeff;
end
else if (input_rdy_flag == 1'b0)
begin
taken = 1'b0;
coeff_en = 1'b0;
coeff_wr_addr = coeff_wr_addr;
next_state = Read_coeff;
end
else
next_state = Read_coeff;
end
Wait_input: begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
data_wr_addr = 8'd0;
rj_en = 1'b0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b0;
compute_enable = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b0;
data_count = 8'd0;
if (Reset_n == 1'b0)
next_state = Reset;
else if (Frame == 1'b1)
next_state = Compute;
else
next_state = Wait_input;
end
Compute: begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
rj_en = 1'b0;
coeff_en = 1'b0;
Clear = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b0;
if (Reset_n == 1'b0)
begin
Clear = 1'b1;
next_state = Reset;
end
else if (input_rdy_flag == 1'b1 && taken == 1'b0)
begin
if (zero_flag_L && zero_flag_R)
begin
next_state = Sleep;
sleep_flag = 1'b1;
end
else
begin
data_en = 1'b1;
data_wr_addr = data_count;
data_count = data_count + 1'b1;
real_count = real_count + 1'b1;
next_state = Compute;
compute_enable = 1'b1;
taken = 1'b1;
end
end
else if (input_rdy_flag == 1'b0)
begin
taken = 1'b0;
data_en = 1'b0;
data_wr_addr = data_wr_addr;
compute_enable = 1'b0;
next_state = Compute;
end
else
begin
data_en = 1'b0;
data_wr_addr = data_wr_addr;
//real_count = real_count + 1'b1;
next_state = Compute;
compute_enable = 1'b0;
end
end
Reset: begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
data_wr_addr = 8'd0;
rj_en = 1'b0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b1;
compute_enable = 1'b0;
InReady = 1'b0;
sleep_flag = 1'b0;
data_count = 8'd0;
taken = 1'b0;
//real_count = real_count - 1'b1;
if (Reset_n == 1'b0)
next_state = Reset;
else
next_state = Wait_input;
end
Sleep: begin
rj_wr_addr = 4'd0;
coeff_wr_addr = 9'd0;
data_wr_addr = data_wr_addr;
rj_en = 1'b0;
coeff_en = 1'b0;
data_en = 1'b0;
Clear = 1'b0;
compute_enable = 1'b0;
InReady = 1'b1;
sleep_flag = 1'b1;
if (Reset_n == 1'b0)
next_state = Reset;
else if (input_rdy_flag == 1'b1 && taken == 1'b0)
begin
if (zero_flag_L && zero_flag_R)
next_state = Sleep;
else
begin
taken = 1'b1;
data_en = 1'b1;
compute_enable = 1'b1;
sleep_flag = 1'b0;
data_wr_addr = data_count;
data_count = data_count + 1'b1;
real_count = real_count + 1'b1;
next_state = Compute;
end
end
else
next_state = Sleep;
end
endcase
end
end
endmodule
module MSDAP(input Dclk, Sclk, Reset_n, Frame, Start, InputL, InputR,
output InReady, OutReady, OutputL, OutputR);
//Wires for SIPO
wire Frame_in, Dclk_in, Clear, input_rdy_flag;
wire [15:0] data_L, data_R;
//Wires for memories
wire rj_en, coeff_en, data_en; // For main controller
wire rj_en_L, coeff_en_L, xin_en_L; // For ALU controller
wire rj_en_R, coeff_en_R, xin_en_R;
wire [3:0] rj_wr_addr, rj_addr_L, rj_addr_R;
wire [8:0] coeff_wr_addr, coeff_addr_L, coeff_addr_R;
wire [7:0] data_wr_addr, xin_addr_L, xin_addr_R;
wire [15:0] rj_data_L, coeff_data_L, xin_data_L;
wire [15:0] rj_data_R, coeff_data_R, xin_data_R;
wire zero_flag_L, zero_flag_R;
//Wires for main controller
wire compute_enable, sleep_flag, Sclk_in;
//Wires for ALU controller
wire [39:0] add_inp_L, add_inp_R;
wire add_sub_L, adder_en_L, shift_enable_L, load_L, clear_L, p2s_enable_L;
wire add_sub_R, adder_en_R, shift_enable_R, load_R, clear_R, p2s_enable_R;
//Wires for adder, shifter blocks
wire [39:0] shifted_L, shifted_R, sum_L, sum_R;
//Wires for PISO
wire OutReadyL, OutReadyR;
assign add_inp_L = (xin_data_L[15]) ? {8'hFF, xin_data_L, 16'h0000} : {8'h00, xin_data_L, 16'h0000};
assign add_inp_R = (xin_data_R[15]) ? {8'hFF, xin_data_R, 16'h0000} : {8'h00, xin_data_R, 16'h0000};
//Module instantiations
SIPO SIPO_uut (.Frame(Frame_in), .Dclk(Dclk_in), .Clear(Clear),
.InputL(InputL), .InputR(InputR), .input_rdy_flag(input_rdy_flag),
.data_L(data_L), .data_R(data_R));
rj_memory rj_L (.wr_en(rj_en), .rd_en(rj_en_L), .Sclk(Sclk_in),
.rj_wr_addr(rj_wr_addr), .rj_rd_addr(rj_addr_L),
.data_in(data_L), .rj_data(rj_data_L));
rj_memory rj_R (.wr_en(rj_en), .rd_en(rj_en_R), .Sclk(Sclk_in),
.rj_wr_addr(rj_wr_addr), .rj_rd_addr(rj_addr_R),
.data_in(data_R), .rj_data(rj_data_R));
coeff_memory coeff_L (.wr_en(coeff_en), .rd_en(coeff_en_L), .Sclk(Sclk_in),
.coeff_wr_addr(coeff_wr_addr), .coeff_rd_addr(coeff_addr_L),
.data_in(data_L), .coeff_data(coeff_data_L));
coeff_memory coeff_R (.wr_en(coeff_en), .rd_en(coeff_en_R), .Sclk(Sclk_in),
.coeff_wr_addr(coeff_wr_addr), .coeff_rd_addr(coeff_addr_R),
.data_in(data_R), .coeff_data(coeff_data_R));
data_memory xin_L (.wr_en(data_en), .rd_en(xin_en_L), .Sclk(Sclk_in), .input_rdy_flag(input_rdy_flag),
.data_wr_addr(data_wr_addr), .data_rd_addr(xin_addr_L),
.data_in(data_L), .xin_data(xin_data_L), .zero_flag(zero_flag_L));
data_memory xin_R (.wr_en(data_en), .rd_en(xin_en_R), .Sclk(Sclk_in), .input_rdy_flag(input_rdy_flag),
.data_wr_addr(data_wr_addr), .data_rd_addr(xin_addr_R),
.data_in(data_R), .xin_data(xin_data_R), .zero_flag(zero_flag_R));
MSDAP_controller main_ctrl (.Sclk(Sclk), .Dclk(Dclk), .Start(Start), .Reset_n(Reset_n),
.Frame(Frame), .input_rdy_flag(input_rdy_flag), .zero_flag_L(zero_flag_L), .zero_flag_R(zero_flag_R),
.rj_wr_addr(rj_wr_addr), .coeff_wr_addr(coeff_wr_addr), .data_wr_addr(data_wr_addr),
.rj_en(rj_en), .coeff_en(coeff_en), .data_en(data_en), .Clear(Clear),
.Frame_out(Frame_in), .Dclk_out(Dclk_in), .Sclk_out(Sclk_in),
.compute_enable(compute_enable), .sleep_flag(sleep_flag),
.InReady(InReady));
alu_controller alu_ctrl (.compute_enable(compute_enable), .Clear(Clear), .Sclk(Sclk_in), .sleep_flag(sleep_flag),
.rj_data_L(rj_data_L), .coeff_data_L(coeff_data_L), .xin_data_L(xin_data_L),
.rj_data_R(rj_data_R), .coeff_data_R(coeff_data_R), .xin_data_R(xin_data_R),
.add_inp_L(add_inp_L), .add_inp_R(add_inp_R),
.rj_addr_L(rj_addr_L), .coeff_addr_L(coeff_addr_L), .xin_addr_L(xin_addr_L),
.rj_addr_R(rj_addr_R), .coeff_addr_R(coeff_addr_R), .xin_addr_R(xin_addr_R),
.rj_en_L(rj_en_L), .coeff_en_L(coeff_en_L), .xin_en_L(xin_en_L),
.rj_en_R(rj_en_R), .coeff_en_R(coeff_en_R), .xin_en_R(xin_en_R),
.add_sub_L(add_sub_L), .adder_en_L(adder_en_L), .shift_enable_L(shift_enable_L), .load_L(load_L), .clear_L(clear_L), .p2s_enable_L(p2s_enable_L),
.add_sub_R(add_sub_R), .adder_en_R(adder_en_R), .shift_enable_R(shift_enable_R), .load_R(load_R), .clear_R(clear_R), .p2s_enable_R(p2s_enable_R));
adder add_L (.a(add_inp_L), .b(shifted_L), .add_sub(add_sub_L), .adder_en(adder_en_L), .sum(sum_L));
adder add_R (.a(add_inp_R), .b(shifted_R), .add_sub(add_sub_R), .adder_en(adder_en_R), .sum(sum_R));
shift_acc shift_acc_L (.shift_enable(shift_enable_L), .load(load_L), .clear(clear_L), .sclk(Sclk_in), .blk_in(sum_L), .blk_out(shifted_L));
shift_acc shift_acc_R (.shift_enable(shift_enable_R), .load(load_R), .clear(clear_R), .sclk(Sclk_in), .blk_in(sum_R), .blk_out(shifted_R));
PISO PISO_L (.Sclk(Sclk_in), .Clear(Clear), .Frame(Frame_in), .Shifted(shifted_L), .Serial_out(OutputL), .p2s_enable(p2s_enable_L), .OutReady(OutReadyL));
PISO PISO_R (.Sclk(Sclk_in), .Clear(Clear), .Frame(Frame_in), .Shifted(shifted_R), .Serial_out(OutputR), .p2s_enable(p2s_enable_R), .OutReady(OutReadyR));
assign OutReady = OutReadyL || OutReadyR;
endmodule
module data_memory (input wr_en, rd_en, Sclk, input_rdy_flag,
input [7:0] data_wr_addr, data_rd_addr,
input [15:0] data_in,
output [15:0] xin_data,
output reg zero_flag);
reg [15:0] data_mem [0:255];
reg [11:0] zero_cnt;
always @(negedge Sclk)
begin
if(wr_en == 1'b1)
data_mem[data_wr_addr] = data_in;
else
data_mem[data_wr_addr] = data_mem[data_wr_addr];
end
always @(posedge input_rdy_flag)
begin
if (data_in == 16'd0)
begin
zero_cnt = zero_cnt + 1'b1;
if (zero_cnt == 12'd800)
zero_flag = 1'b1;
else if (zero_cnt > 12'd800)
begin
zero_cnt = 12'd800;
zero_flag = 1'b1;
end
end
else if (data_in != 16'd0)
begin
zero_cnt = 12'd0;
zero_flag = 1'b0;
end
end
assign xin_data = (rd_en) ? data_mem[data_rd_addr] : 16'd0;
endmodule
module coeff_memory (input wr_en, rd_en, Sclk,
input [8:0] coeff_wr_addr, coeff_rd_addr,
input [15:0] data_in,
output [15:0] coeff_data);
reg [15:0] coeff_mem [0:511];
always @(negedge Sclk)
begin
if(wr_en == 1'b1)
coeff_mem[coeff_wr_addr] = data_in;
else
coeff_mem[coeff_wr_addr] = coeff_mem[coeff_wr_addr];
end
assign coeff_data = (rd_en) ? coeff_mem[coeff_rd_addr] : 16'd0;
endmodule
module alu_controller (
input compute_enable,
input Clear,
input Sclk,
input sleep_flag,
input [15:0] rj_data_L, coeff_data_L, xin_data_L,
input [15:0] rj_data_R, coeff_data_R, xin_data_R,
output [39:0] add_inp_L, add_inp_R,
output reg [3:0] rj_addr_L,
output reg [8:0] coeff_addr_L,
output reg [7:0] xin_addr_L,
output reg [3:0] rj_addr_R,
output reg [8:0] coeff_addr_R,
output reg [7:0] xin_addr_R,
output reg rj_en_L, coeff_en_L, xin_en_L,
output reg rj_en_R, coeff_en_R, xin_en_R,
output reg add_sub_L, adder_en_L, shift_enable_L, load_L, clear_L, p2s_enable_L,
output reg add_sub_R, adder_en_R, shift_enable_R, load_R, clear_R, p2s_enable_R
);
parameter initial_state = 2'b00, comp_state = 2'b01, sleep_state = 2'b10;
reg [1:0] pr_state_L, next_state_L;
reg [1:0] pr_state_R, next_state_R;
reg [7:0] x_count_L, x_index_L;
reg [7:0] x_count_R, x_index_R;
reg [7:0] k_L, k_R;
reg xmem_overflow_L, start_comp_L, compute_status_L, out_done_L;
reg xmem_overflow_R, start_comp_R, compute_status_R, out_done_R;
//wire [39:0] shifted_L, shifted_R, sum_L, sum_R;
assign add_inp_L = (xin_data_L[15]) ? {8'hFF, xin_data_L, 16'h0000} : {8'h00, xin_data_L, 16'h0000};
assign add_inp_R = (xin_data_R[15]) ? {8'hFF, xin_data_R, 16'h0000} : {8'h00, xin_data_R, 16'h0000};
always @(Clear, next_state_L)
begin
if (Clear == 1'b1)
pr_state_L <= initial_state;
else
pr_state_L <= next_state_L;
end
always @(posedge Sclk)
begin
//next_state_L <= initial_state;
case (pr_state_L)
initial_state:
begin
xmem_overflow_L <= 1'b0;
//out_done_L = 1'b0;
if (Clear == 1'b1)
next_state_L <= initial_state;
else if (compute_enable == 1'b1)
begin
next_state_L <= comp_state;
x_count_L <= 8'd1;
start_comp_L <= 1'b1;
compute_status_L <= 1'b1;
end
else
begin
next_state_L <= initial_state;
x_count_L <= x_count_L;
start_comp_L <= 1'b0;
end
end
comp_state:
begin
if (compute_enable == 1'b1)
begin
x_count_L <= x_count_L + 1'b1;
start_comp_L <= 1'b1;
compute_status_L <= 1'b1;
if (x_count_L == 8'hFF)
xmem_overflow_L <= 1'b1;
else
xmem_overflow_L <= xmem_overflow_L;
end
else
begin
start_comp_L <= 1'b0;
xmem_overflow_L <= xmem_overflow_L;
if (rj_addr_L == 4'hF && coeff_addr_L == 9'h1FF && k_L == rj_data_L)
compute_status_L <= 1'b0;
else
compute_status_L <= compute_status_L;
end
if (Clear == 1'b1)
next_state_L <= initial_state;
else if (sleep_flag == 1'b1)
next_state_L <= sleep_state;
else
next_state_L <= comp_state;
end
sleep_state:
begin
x_count_L <= x_count_L;
xmem_overflow_L <= xmem_overflow_L;
start_comp_L <= 1'b0;
compute_status_L <= 1'b0;
if (Clear == 1'b1)
next_state_L <= initial_state;
else if (sleep_flag == 1'b0)
begin
x_count_L <= x_count_L + 1'b1;
start_comp_L <= 1'b1;
compute_status_L <= 1'b1;
if (x_count_L == 8'hFF)
xmem_overflow_L <= 1'b1;
else
xmem_overflow_L <= xmem_overflow_L;
next_state_L <= comp_state;
end
else
next_state_L <= sleep_state;
end
default: next_state_L <= initial_state;
endcase
end
always @(posedge Sclk)
begin
if (out_done_L)
begin
p2s_enable_L = 1'b1;
rj_addr_L = 4'd0;
coeff_addr_L = 9'd0;
k_L = 8'd0;
out_done_L = 1'b0;
clear_L = 1'b1;
end
else
p2s_enable_L = 1'b0;
if (start_comp_L == 1'b1)
begin
out_done_L = 1'b0;
rj_addr_L = 4'd0;
rj_en_L = 1'b1;
coeff_addr_L = 9'd0;
coeff_en_L = 1'b1;
xin_en_L = 1'b0;
adder_en_L = 1'b0;
shift_enable_L = 1'b0;
k_L = 8'd0;
clear_L = 1'b1;
load_L = 1'b0;
end
else if (compute_status_L == 1'b1)
begin
if (k_L == rj_data_L)
begin
xin_en_L = 1'b0;
shift_enable_L = 1'b1;
clear_L = 1'b0;
load_L = 1'b1;
adder_en_L = 1'b1;
k_L = 8'd0;
if (rj_addr_L < 4'd15)
begin
rj_addr_L = rj_addr_L + 1'b1;
end
else
begin
rj_addr_L = 4'd0;
out_done_L = 1'b1;
coeff_addr_L = 9'd0;
end
end
else
begin
shift_enable_L = 1'b0;
clear_L = 1'b0;
load_L = 1'b0;
xin_en_L = 1'b0;
x_index_L = coeff_data_L[7:0];
add_sub_L = coeff_data_L[8];
if (x_count_L - 1'b1 >= x_index_L)
begin
xin_addr_L = x_count_L - 1'b1 - x_index_L;
xin_en_L = 1'b1;
adder_en_L = 1'b1;
load_L = 1'b1;
end
else if (x_count_L - 1'b1 < x_index_L && xmem_overflow_L == 1'b1)
begin
xin_addr_L = x_count_L - 1'b1 + (9'd256 - x_index_L);
xin_en_L = 1'b1;
adder_en_L = 1'b1;
load_L = 1'b1;
end
else
begin
xin_addr_L = xin_addr_L;
adder_en_L = 1'b0;
end
if (coeff_addr_L < 9'h1FF)
coeff_addr_L = coeff_addr_L + 1'b1;
else
coeff_addr_L = coeff_addr_L;
k_L = k_L + 1'b1;
end
end
else
begin
rj_addr_L = 4'd0;
rj_en_L = 1'b0;
coeff_addr_L = 9'd0;
coeff_en_L = 1'b0;
xin_en_L = 1'b0;
adder_en_L = 1'b0;
shift_enable_L = 1'b0;
k_L = 8'd0;
load_L = 1'b0;
clear_L = 1'b1;
end
end
/*always @ (negedge p2s_enable_L)
begin
$display("%d : %X \n",x_count_L,shifted_L);
end*/
// Right side FSM
always @(Clear, next_state_R)
begin
if (Clear == 1'b1)
pr_state_R <= initial_state;
else
pr_state_R <= next_state_R;
end
always @(posedge Sclk)
begin
//next_state_R <= initial_state;
case (pr_state_R)
initial_state:
begin
xmem_overflow_R <= 1'b0;
//out_done_R = 1'b0;
if (Clear == 1'b1)
next_state_R <= initial_state;
else if (compute_enable == 1'b1)
begin
next_state_R <= comp_state;
x_count_R <= 8'd1;
start_comp_R <= 1'b1;
compute_status_R <= 1'b1;
end
else
begin
next_state_R <= initial_state;
x_count_R <= x_count_R;
start_comp_R <= 1'b0;
end
end
comp_state:
begin
if (compute_enable == 1'b1)
begin
x_count_R <= x_count_R + 1'b1;
start_comp_R <= 1'b1;
compute_status_R <= 1'b1;
if (x_count_R == 8'hFF)
xmem_overflow_R <= 1'b1;
else
xmem_overflow_R <= xmem_overflow_R;
end
else
begin
start_comp_R <= 1'b0;
xmem_overflow_R <= xmem_overflow_R;
if (rj_addr_R == 4'hF && coeff_addr_R == 9'h1FF && k_R == rj_data_R)
compute_status_R <= 1'b0;
else
compute_status_R <= compute_status_R;
end
if (Clear == 1'b1)
next_state_R <= initial_state;
//else if (sleep_flag == 1'b1)
// next_state_R <= sleep_state;
else
next_state_R <= comp_state;
end
sleep_state:
begin
x_count_R <= x_count_R;
xmem_overflow_R <= xmem_overflow_R;
start_comp_R <= 1'b0;
compute_status_R <= 1'b0;
if (Clear == 1'b1)
next_state_R <= initial_state;
else if (sleep_flag == 1'b0)
begin
x_count_R <= x_count_R + 1'b1;
start_comp_R <= 1'b1;
compute_status_R <= 1'b1;
if (x_count_R == 8'hFF)
xmem_overflow_R <= 1'b1;
else
xmem_overflow_R <= xmem_overflow_R;
next_state_R <= comp_state;
end
else
next_state_R <= sleep_state;
end
default:
begin
end
endcase
end
always @(posedge Sclk)
begin
if (out_done_R)
begin
p2s_enable_R = 1'b1;
rj_addr_R = 4'd0;
coeff_addr_R = 9'd0;
k_R = 8'd0;
out_done_R = 1'b0;
end
else
p2s_enable_R = 1'b0;
if (start_comp_R == 1'b1)
begin
out_done_R = 1'b0;
rj_addr_R = 4'd0;
rj_en_R = 1'b1;
coeff_addr_R = 9'd0;
coeff_en_R = 1'b1;
xin_en_R = 1'b0;
adder_en_R = 1'b0;
shift_enable_R = 1'b0;
k_R = 8'd0;
clear_R = 1'b1;
load_R = 1'b0;
end
else if (compute_status_R == 1'b1)
begin
if (k_R == rj_data_R)
begin
xin_en_R = 1'b0;
shift_enable_R = 1'b1;
clear_R = 1'b0;
load_R = 1'b1;
adder_en_R = 1'b1;
k_R = 8'd0;
if (rj_addr_R < 4'd15)
begin
rj_addr_R = rj_addr_R + 1'b1;
end
else
begin
rj_addr_R = 4'd0;
out_done_R = 1'b1;
coeff_addr_R = 9'd0;
end
end
else
begin
shift_enable_R = 1'b0;
clear_R = 1'b0;
load_R = 1'b0;
xin_en_R = 1'b0;
x_index_R = coeff_data_R[7:0];
add_sub_R = coeff_data_R[8];
if (x_count_R - 1'b1 >= x_index_R)
begin
xin_addr_R = x_count_R - 1'b1 - x_index_R;
xin_en_R = 1'b1;
adder_en_R = 1'b1;
load_R = 1'b1;
end
else if (x_count_R - 1'b1 < x_index_R && xmem_overflow_R == 1'b1)
begin
xin_addr_R = x_count_R - 1'b1 + (9'd256 - x_index_R);
xin_en_R = 1'b1;
adder_en_R = 1'b1;
load_R = 1'b1;
end
else
begin
xin_addr_R = xin_addr_R;
adder_en_R = 1'b0;
end
if (coeff_addr_R < 9'h1FF)
coeff_addr_R = coeff_addr_R + 1'b1;
else
coeff_addr_R = coeff_addr_R;
k_R = k_R + 1'b1;
end
end
else
begin
rj_addr_R = 4'd0;
rj_en_R = 1'b0;
coeff_addr_R = 9'd0;
coeff_en_R = 1'b0;
xin_en_R = 1'b0;
adder_en_R = 1'b0;
shift_enable_R = 1'b0;
k_R = 8'd0;
load_R = 1'b0;
clear_R = 1'b1;
end
end
/*always @ (negedge p2s_enable_R)
begin
$display("%d : %X \n",x_count_R,shifted_R);
end*/
endmodule
module adder(
input [39:0] a,
input [39:0] b,
input add_sub,
input adder_en,
output [39:0] sum
);
assign sum = (add_sub == 1'b1) ? (b - a) :
(add_sub == 1'b0) ? (b + a) :
sum;
endmodule
module SIPO (Frame, Dclk, Clear, InputL, InputR, data_L, data_R, input_rdy_flag);
input Frame, Dclk, Clear, InputL, InputR;
output reg input_rdy_flag;
output reg [15:0] data_L;
output reg [15:0] data_R;
reg [3:0] bit_count;
reg frame_status;
always @(negedge Dclk or posedge Clear)
begin
if (Clear == 1'b1)
begin
bit_count = 4'd15;
//temp_L = 16'd0;
//temp_R = 16'd0;
data_L = 16'd0;
data_R = 16'd0;
input_rdy_flag = 1'b0;
frame_status = 1'b0;
end
else
begin
if (Frame == 1'b1)
begin
bit_count = 4'd15;
input_rdy_flag = 1'b0;
data_L [bit_count] = InputL;
data_R [bit_count] = InputR;
frame_status = 1'b1;
end
else if (frame_status == 1'b1)
begin
bit_count = bit_count - 1'b1;
data_L [bit_count] = InputL;
data_R [bit_count] = InputR;
if (bit_count == 4'd0)
begin
//data_L = temp_L;
//data_R = temp_R;
input_rdy_flag = 1'b1;
frame_status = 1'b0;
end
else
begin
//data_L = data_L;
//data_R = data_R;
input_rdy_flag = 1'b0;
frame_status = 1'b1;
end
end
else
begin
bit_count = 4'd15;
data_L = 16'd0;
data_R = 16'd0;
input_rdy_flag = 1'b0;
frame_status = 1'b0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_PP_BLACKBOX_V
|
`timescale 1ns/1ps
module controlunit(instruction,IRQ,PChigh,PCplusin,PCplusout,PCSrc,RegDst,RegWr,ALUSrc1,ALUSrc2,ALUFun,Sign,MemWr,MemRd,MemtoReg,EXTOp,LUOp,JT,OpCode);
input [31:0] instruction;
input IRQ;
input PChigh;
input [31:0] PCplusin;
output [31:0] PCplusout;
output [2:0] PCSrc;
reg [2:0] PCSrc;
output [1:0] RegDst;
reg [1:0] RegDst;
output RegWr;
reg RegWr;
output ALUSrc1;
reg ALUSrc1;
output ALUSrc2;
reg ALUSrc2;
output [5:0] ALUFun;
reg [5:0] ALUFun;
output Sign;
reg Sign;
output MemWr;
reg MemWr;
output MemRd;
reg MemRd;
output [1:0] MemtoReg;
reg [1:0] MemtoReg;
output EXTOp;
reg EXTOp;
output LUOp;
reg LUOp;
output [25:0] JT;
reg [25:0] JT = 26'h0;
output [5:0] OpCode;
reg [5:0] OpCode = 6'h00;
assign PCplusout = (IRQ == 1'b0) ? PCplusin : PCplusin - 32'h00000004;
always @(*)
begin
if(~IRQ || PChigh)
begin
case(instruction[31:26])
6'h00://R instructions
begin
case(instruction[5:0])
6'h00://sll
begin
if(instruction[25:21] == 5'h00)
begin
ALUFun <= 6'h20;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 1;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//undefined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h02://srl
begin
if(instruction[25:21] == 5'h00)
begin
ALUFun <= 6'h21;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 1;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//undefined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h03://sra
begin
if(instruction[25:21] == 5'h00)
begin
ALUFun <= 6'h23;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 1;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//undefined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h08://jr
begin
if(instruction[20:6] == 15'h0000)
begin
PCSrc <= 3'b011;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h09://jalr
begin
if(instruction[20:16] == 5'h00 && instruction[10:6] == 5'h00)
begin
PCSrc <= 3'b011;
RegDst <= 2'b10;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
else
begin//undefined instruction
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h20://add
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h21://addu
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h22://sub
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h01;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h23://subu
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h01;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h24://and
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h18;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h25://or
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h1e;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h26://xor
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h16;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h27://nor
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h11;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h2a://slt
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h35;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h2b://sltu
begin
if(instruction[10:6]==5'h00)
begin
ALUFun <= 6'h35;
PCSrc <= 3'b000;
RegDst <= 2'b00;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 0;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
end
else//underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
default://underfined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
endcase
end
6'h01://bgez
begin
if(instruction[20:16]==5'h01)
begin
OpCode <= 6'h01;
PCSrc <= 3'b001;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
else//underfined instruction
begin
OpCode <= 6'h00;
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h02://j
begin
JT <= instruction[25:0];
PCSrc <= 3'b010;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
end
6'h03://jal
begin
JT <= instruction[25:0];
PCSrc <= 3'b010;
RegDst <= 2'b10;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
6'h04://beq
begin
OpCode <= 6'h04;
PCSrc <= 3'b001;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
6'h05://bne
begin
OpCode <= 6'h05;
PCSrc <= 3'b001;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
6'h06://blez
begin
OpCode <= 6'h06;
PCSrc <= 3'b001;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
6'h07://bgtz
begin
OpCode <= 6'h07;
PCSrc <= 3'b001;
RegWr <= 0;
MemWr <= 0;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
6'h08://addi
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h09://addiu
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h0a://slti
begin
ALUFun <= 6'h35;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h0b://sltiu
begin
ALUFun <= 6'h35;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
EXTOp <= 0;
LUOp <= 0;
end
6'h0c://andi
begin
ALUFun <= 6'h18;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
EXTOp <= 1;
LUOp <= 0;
end
6'h0f://lui
begin
if(instruction[25:21]==5'h00)
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 0;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b00;
LUOp <= 1;
end
else//undefined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
6'h23://lw
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 1;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 1;
MemWr <= 0;
MemRd <= 1;
MemtoReg <= 2'b01;
EXTOp <= 1;
LUOp <= 0;
end
6'h2b://sw
begin
ALUFun <= 6'h00;
PCSrc <= 3'b000;
RegDst <= 2'b01;
RegWr <= 0;
ALUSrc1 <= 0;
ALUSrc2 <= 1;
Sign <= 1;
MemWr <= 1;
MemRd <= 0;
EXTOp <= 1;
LUOp <= 0;
end
default://undefined instruction
begin
PCSrc <= 3'b101;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
endcase
end
else//interrupted
begin
PCSrc <= 3'b100;
RegDst <= 2'b11;
RegWr <= 1;
MemWr <= 0;
MemRd <= 0;
MemtoReg <= 2'b10;
end
end
endmodule
|
module Platform (
clk_clk,
hex0_2_export,
hex3_5_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
i2c_SDAT,
i2c_SCLK,
keys_export,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
switches_export,
xck_clk);
input clk_clk;
output [20:0] hex0_2_export;
output [20:0] hex3_5_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
inout i2c_SDAT;
output i2c_SCLK;
input [2:0] keys_export;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
input [9:0] switches_export;
output xck_clk;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: CLKPLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module CLKPLL (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [0:0] sub_wire2 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 7,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 7,
altpll_component.clk1_phase_shift = "-6000",
altpll_component.clk2_divide_by = 17,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 14,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=CLKPLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "17"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "70.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "70.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "41.176472"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "14"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "70.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "70.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-6.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "CLKPLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-6000"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "17"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLKPLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
module ovl_delta_wrapped(
clk,
rst,
min,
max,
test_expr,
prevConfigInvalid,
out
);
//Explicit state space exploration not feasible for large values of test_expr
`ifdef SMV
parameter width = 12;
parameter limit_width = 3;
`else
parameter width = 32;
parameter limit_width = 8;
`endif
input clk;
input rst;
input [limit_width-1:0] min;
input [limit_width-1:0] max;
input [width-1:0] test_expr;
input prevConfigInvalid;
output out;
wire [2:0] result_3bit;
wire [2:0] result_3bit_comb;
`ifdef SMV
ovl_delta ovl_delta(.width(width),
.limit_width(limit_width),
.clock(clk),
.reset(rst),
.enable(1'b1),
.min(min),
.max(max),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
`else // !`ifdef SMV
ovl_delta #(
.width(width),
.limit_width(limit_width)
)
ovl_delta(
.clock(clk),
.reset(rst),
.enable(1'b1),
.min(min),
.max(max),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
`endif // !`ifdef SMV
assign out = result_3bit_comb[0] & ~prevConfigInvalid;
endmodule
|
`timescale 1 ns / 1 ps
module vgagraph_ip_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
input wire [27:0] DISPADDR,
input wire DISPON,
output wire VBLANK,
input wire CLRVBLANK,
output wire [3:0] VGA_R, VGA_G, VGA_B,
output wire HSYNC, VSYNC,
output wire AUTO_LOAD,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_init_axi_txn,
output wire m00_axi_txn_done,
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
vgagraph_ip_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) vgagraph_ip_v1_0_M00_AXI_inst (
// user added from here
.DISPADDR(DISPADDR),
.DISPON(DISPON),
.VBLANK(VBLANK),
.CLRVBLANK(CLRVBLANK),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.HSYNC(HSYNC),
.VSYNC(VSYNC),
.AUTO_LOAD(AUTO_LOAD),
// user added ended
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.TXN_DONE(m00_axi_txn_done),
.ERROR(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2013, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : tb_top.v
// Author : Huang Leilei
// Created : 2015-09-07
// Description : test bench for top_with_more
//
//-------------------------------------------------------------------
//
// Modified : 2015-09-16 by HLL
// Description : cur_chroma provided in the order of uvuvuv...
// Modified : 2015-09-17 by HLL
// Description : ref_chroma provided in the order of uvuvuv...
// Modified : 2015-09-19 by HLL
// Description : load_db_chroma & store_db_chroma provided in the order of uvuvuv...
// more modes connected out
// Modified : 2015-10-11 by HLL
// Description : define TEST_FETCH changed to NO_FETCH
//
//-------------------------------------------------------------------
`include "enc_defines.v"
`define FETCH_AUTO_CHECK
// `define DUMP_FETCH
`define FIME_AUTO_CHECK
`define FME_AUTO_CHECK
`define MVD_AUTO_CHECK
// `define DUMP_MC
// `define DUMP_TQ
`define DB_AUTO_CHECK
// `define DUMP_INTRA
`define BS_AUTO_CHECK
// `define DUMP_BS
//`define DUMP_FSDB
`define DUMP_TIME 0
`define DUMP_FILE "tb_top.fsdb"
`define TEST_P
`define TEST_I
module tb_top;
//*** PARAMETER ****************************************************************
parameter INTRA = 0 ,
INTER = 1 ;
parameter FIME_CUR_FILE_0 = "./tv/fime_cur_mb_p32_0.dat" ,
FIME_CUR_FILE_1 = "./tv/fime_cur_mb_p32_0.dat" ,
FIME_REF_FILE = "./tv/fime_check_i.dat" ,
FME_CUR_FILE = "./tv/fme_cur_mb_p32.dat" ,
FME_REF_FILE = "./tv/fme_check_i.dat" , // just copy fime_check_i.dat
MC_CUR_FILE = "./tv/mc_cur_mb_p32.dat" ,
MC_REF_FILE = "./tv/mc_check_i.dat" ,
BS_I_CHECK_FILE = "./tv/bs_i_check_o.dat" ,
BS_P_CHECK_FILE = "./tv/bs_p_check_o.dat" ,
FIME_CHECK_FILE = "./tv/fime_check_o.dat" ,
FME_CHECK_FILE = "./tv/fme_check_o.dat" ,
MVD_CHECK_FILE = "./tv/mvd_check_o.dat" ,
FETCH_P_CUR_FILE = "./tv/fetch_p_cur.yuv" ,
FETCH_P_REF_FILE = "./tv/fetch_p_check_i.yuv" ,
FETCH_P_CHECK_FILE = "./tv/fetch_p_check_o.yuv" ,
FETCH_I_CUR_FILE = "./tv/fetch_i_cur.yuv" ,
FETCH_I_CHECK_FILE = "./tv/fetch_i_check_o.yuv" ;
//*** WIRE/REG DECLARATION *****************************************************
// GLOBAL
reg clk ;
reg rst_n ;
reg sys_start ;
wire sys_done ;
reg [`PIC_X_WIDTH-1 : 0] sys_x_total ;
reg [`PIC_Y_WIDTH-1 : 0] sys_y_total ;
reg sys_mode ;
reg [5 : 0] sys_qp ;
reg sys_type ;
reg pre_min_size ;
// EXT_IF
wire [1-1 : 0] extif_start_o ; // ext mem load start
reg [1-1 : 0] extif_done_i ; // ext mem load done
wire [5-1 : 0] extif_mode_o ; // "ext mode: {load/store} {luma
wire [6+`PIC_X_WIDTH-1 : 0] extif_x_o ; // x in ref frame
wire [6+`PIC_Y_WIDTH-1 : 0] extif_y_o ; // y in ref frame
wire [8-1 : 0] extif_width_o ; // ref window width
wire [8-1 : 0] extif_height_o ; // ref window height
reg extif_wren_i ;
reg extif_rden_i ;
reg [8-1 : 0] extif_addr_i ; // fetch ram write/read addr
reg [16*`PIXEL_WIDTH-1 : 0] extif_data_i ; // ext data reg
wire [16*`PIXEL_WIDTH-1 : 0] extif_data_o ; // ext data outp
// BS_IF
wire winc_o ;
wire [7 : 0] wdata_o ;
// WATCH
integer frame_num ;
// FIME CHECK
integer fime_check_fp_i ;
integer fime_check_fp_o ;
integer fime_check_tp ;
reg [`IMV_WIDTH-1 : 0] fime_check_mv_x ;
reg [`IMV_WIDTH-1 : 0] fime_check_mv_y ;
reg [42-1 : 0] fime_check_partition ;
// FME CHECK
integer fme_check_fp_i ;
integer fme_check_fp_o ;
integer fme_check_tp ;
integer fme_check_cntrow ;
reg [64*`PIXEL_WIDTH-1 : 0] fme_check_pixel_hw ;
reg [64*`PIXEL_WIDTH-1 : 0] fme_check_pixel_sw ;
// MC CHECK
integer mc_check_fp_i ;
integer mc_check_fp_o ;
// MVD_CHECK
integer mvd_check_tp_o ;
integer mvd_check_fp_o ;
//*** DUT DECLARATION **********************************************************
h265core dut(
// global
.clk ( clk ),
.rst_n ( rst_n ),
// config
.sys_start_i ( sys_start ),
.sys_done_o ( sys_done ),
.sys_x_total_i ( sys_x_total ),
.sys_y_total_i ( sys_y_total ),
.sys_mode_i ( sys_mode ),
.sys_qp_i ( sys_qp ),
.sys_type_i ( sys_type ),
.pre_min_size_i ( pre_min_size ),
// ext
.extif_start_o ( extif_start_o ),
.extif_done_i ( extif_done_i ),
.extif_mode_o ( extif_mode_o ),
.extif_x_o ( extif_x_o ),
.extif_y_o ( extif_y_o ),
.extif_width_o ( extif_width_o ),
.extif_height_o ( extif_height_o ),
.extif_wren_i ( extif_wren_i ),
.extif_rden_i ( extif_rden_i ),
.extif_addr_i ( extif_addr_i ),
.extif_data_i ( extif_data_i ),
.extif_data_o ( extif_data_o ),
// bs
.winc_o ( winc_o ),
.wdata_o ( wdata_o )
);
//*** MAIN BODY ****************************************************************
// clk
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
// fake ext memory : para, memory & h_w_A
parameter LOAD_CUR_SUB = 01 ,
LOAD_REF_SUB = 02 ,
LOAD_CUR_LUMA = 03 ,
LOAD_REF_LUMA = 04 ,
LOAD_CUR_CHROMA = 05 ,
LOAD_REF_CHROMA = 06 ,
LOAD_DB_LUMA = 07 ,
LOAD_DB_CHROMA = 08 ,
STORE_DB_LUMA = 09 ,
STORE_DB_CHROMA = 10 ;
reg [`PIXEL_WIDTH-1:0] ext_ori_yuv [448*256*3/2-1:0] ;
reg [`PIXEL_WIDTH-1:0] ext_rec_0_yuv [448*256*3/2-1:0] ;
reg [`PIXEL_WIDTH-1:0] ext_rec_1_yuv [448*256*3/2-1:0] ;
reg [`PIXEL_WIDTH-1:0] ext_temp_yuv ;
reg [`PIXEL_WIDTH-1:0] ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03 ;
reg [`PIXEL_WIDTH-1:0] ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07 ;
reg [`PIXEL_WIDTH-1:0] ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11 ;
reg [`PIXEL_WIDTH-1:0] ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15 ;
integer ext_check_h ;
integer ext_check_w ;
integer ext_check_A ;
reg ext_uv_cnt;
// fake ext memory : reponse logic
initial begin
extif_done_i = 0 ;
extif_wren_i = 0 ;
extif_data_i = 0 ;
ext_uv_cnt = 0 ;
#300
forever begin
@(negedge extif_start_o );
case( extif_mode_o )
LOAD_CUR_LUMA : // load luma component of current LCU: line in
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_wren_i = 1 ;
ext_check_A = (extif_y_o*64+ext_check_h)*448+extif_x_o*64+ext_check_w;
extif_data_i = { ext_ori_yuv[ext_check_A+00] ,ext_ori_yuv[ext_check_A+01] ,ext_ori_yuv[ext_check_A+02] ,ext_ori_yuv[ext_check_A+03]
,ext_ori_yuv[ext_check_A+04] ,ext_ori_yuv[ext_check_A+05] ,ext_ori_yuv[ext_check_A+06] ,ext_ori_yuv[ext_check_A+07]
,ext_ori_yuv[ext_check_A+08] ,ext_ori_yuv[ext_check_A+09] ,ext_ori_yuv[ext_check_A+10] ,ext_ori_yuv[ext_check_A+11]
,ext_ori_yuv[ext_check_A+12] ,ext_ori_yuv[ext_check_A+13] ,ext_ori_yuv[ext_check_A+14] ,ext_ori_yuv[ext_check_A+15]
};
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_i ;
@(negedge clk );
end
end
extif_wren_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
LOAD_REF_LUMA : // load luma component of reference LCU: line in
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_wren_i = 1 ;
ext_check_A = (extif_y_o+ext_check_h)*448+extif_x_o+ext_check_w ;
extif_data_i = { ext_rec_0_yuv[ext_check_A+00] ,ext_rec_0_yuv[ext_check_A+01] ,ext_rec_0_yuv[ext_check_A+02] ,ext_rec_0_yuv[ext_check_A+03]
,ext_rec_0_yuv[ext_check_A+04] ,ext_rec_0_yuv[ext_check_A+05] ,ext_rec_0_yuv[ext_check_A+06] ,ext_rec_0_yuv[ext_check_A+07]
,ext_rec_0_yuv[ext_check_A+08] ,ext_rec_0_yuv[ext_check_A+09] ,ext_rec_0_yuv[ext_check_A+10] ,ext_rec_0_yuv[ext_check_A+11]
,ext_rec_0_yuv[ext_check_A+12] ,ext_rec_0_yuv[ext_check_A+13] ,ext_rec_0_yuv[ext_check_A+14] ,ext_rec_0_yuv[ext_check_A+15]
};
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_i ;
@(negedge clk );
end
end
extif_wren_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
LOAD_CUR_CHROMA : // load chroma component of current LCU: line in, all u then all v
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o/2 ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_wren_i = 1 ;
ext_check_A = 448*256+(extif_y_o*64/2+ext_check_h)*448+extif_x_o*64+ext_check_w;
extif_data_i = { ext_ori_yuv[ext_check_A+00] ,ext_ori_yuv[ext_check_A+01] ,ext_ori_yuv[ext_check_A+02] ,ext_ori_yuv[ext_check_A+03]
,ext_ori_yuv[ext_check_A+04] ,ext_ori_yuv[ext_check_A+05] ,ext_ori_yuv[ext_check_A+06] ,ext_ori_yuv[ext_check_A+07]
,ext_ori_yuv[ext_check_A+08] ,ext_ori_yuv[ext_check_A+09] ,ext_ori_yuv[ext_check_A+10] ,ext_ori_yuv[ext_check_A+11]
,ext_ori_yuv[ext_check_A+12] ,ext_ori_yuv[ext_check_A+13] ,ext_ori_yuv[ext_check_A+14] ,ext_ori_yuv[ext_check_A+15]
};
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_i ;
@(negedge clk );
end
end
extif_wren_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
LOAD_REF_CHROMA : // load chroma component of reference LCU: line in, all u then all v
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o/2 ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_wren_i = 1 ;
ext_check_A = 448*256+(extif_y_o/2+ext_check_h)*448+extif_x_o+ext_check_w ;
extif_data_i = { ext_rec_0_yuv[ext_check_A+00] ,ext_rec_0_yuv[ext_check_A+01] ,ext_rec_0_yuv[ext_check_A+02] ,ext_rec_0_yuv[ext_check_A+03]
,ext_rec_0_yuv[ext_check_A+04] ,ext_rec_0_yuv[ext_check_A+05] ,ext_rec_0_yuv[ext_check_A+06] ,ext_rec_0_yuv[ext_check_A+07]
,ext_rec_0_yuv[ext_check_A+08] ,ext_rec_0_yuv[ext_check_A+09] ,ext_rec_0_yuv[ext_check_A+10] ,ext_rec_0_yuv[ext_check_A+11]
,ext_rec_0_yuv[ext_check_A+12] ,ext_rec_0_yuv[ext_check_A+13] ,ext_rec_0_yuv[ext_check_A+14] ,ext_rec_0_yuv[ext_check_A+15]
};
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_i ;
@(negedge clk );
end
end
extif_wren_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
LOAD_DB_LUMA : // load deblocked results: line in
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_wren_i = 1 ;
ext_check_A = (extif_y_o+ext_check_h)*448+extif_x_o+ext_check_w ;
extif_data_i = { ext_rec_1_yuv[ext_check_A+00] ,ext_rec_1_yuv[ext_check_A+01] ,ext_rec_1_yuv[ext_check_A+02] ,ext_rec_1_yuv[ext_check_A+03]
,ext_rec_1_yuv[ext_check_A+04] ,ext_rec_1_yuv[ext_check_A+05] ,ext_rec_1_yuv[ext_check_A+06] ,ext_rec_1_yuv[ext_check_A+07]
,ext_rec_1_yuv[ext_check_A+08] ,ext_rec_1_yuv[ext_check_A+09] ,ext_rec_1_yuv[ext_check_A+10] ,ext_rec_1_yuv[ext_check_A+11]
,ext_rec_1_yuv[ext_check_A+12] ,ext_rec_1_yuv[ext_check_A+13] ,ext_rec_1_yuv[ext_check_A+14] ,ext_rec_1_yuv[ext_check_A+15]
};
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_i ;
@(negedge clk );
end
end
extif_wren_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
LOAD_DB_CHROMA : // load deblocked results: line in
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o/2 ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_wren_i = 1 ;
ext_check_A = 448*256+(extif_y_o/2+ext_check_h)*448+extif_x_o+ext_check_w ;
extif_data_i = { ext_rec_1_yuv[ext_check_A+00] ,ext_rec_1_yuv[ext_check_A+01] ,ext_rec_1_yuv[ext_check_A+02] ,ext_rec_1_yuv[ext_check_A+03]
,ext_rec_1_yuv[ext_check_A+04] ,ext_rec_1_yuv[ext_check_A+05] ,ext_rec_1_yuv[ext_check_A+06] ,ext_rec_1_yuv[ext_check_A+07]
,ext_rec_1_yuv[ext_check_A+08] ,ext_rec_1_yuv[ext_check_A+09] ,ext_rec_1_yuv[ext_check_A+10] ,ext_rec_1_yuv[ext_check_A+11]
,ext_rec_1_yuv[ext_check_A+12] ,ext_rec_1_yuv[ext_check_A+13] ,ext_rec_1_yuv[ext_check_A+14] ,ext_rec_1_yuv[ext_check_A+15]
};
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_i ;
@(negedge clk );
end
end
extif_wren_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
STORE_DB_LUMA : // dump deblocked results: line in
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_rden_i = 1 ;
ext_check_A = (extif_y_o+ext_check_h)*448+extif_x_o+ext_check_w ;
{ ext_rec_1_yuv[ext_check_A+00] ,ext_rec_1_yuv[ext_check_A+01] ,ext_rec_1_yuv[ext_check_A+02] ,ext_rec_1_yuv[ext_check_A+03]
,ext_rec_1_yuv[ext_check_A+04] ,ext_rec_1_yuv[ext_check_A+05] ,ext_rec_1_yuv[ext_check_A+06] ,ext_rec_1_yuv[ext_check_A+07]
,ext_rec_1_yuv[ext_check_A+08] ,ext_rec_1_yuv[ext_check_A+09] ,ext_rec_1_yuv[ext_check_A+10] ,ext_rec_1_yuv[ext_check_A+11]
,ext_rec_1_yuv[ext_check_A+12] ,ext_rec_1_yuv[ext_check_A+13] ,ext_rec_1_yuv[ext_check_A+14] ,ext_rec_1_yuv[ext_check_A+15]
} = extif_data_o ;
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_o ;
@(negedge clk );
end
end
extif_rden_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
STORE_DB_CHROMA : // dump deblocked results: line in
begin #100 ;
@(negedge clk );
for( ext_check_h=0 ;ext_check_h<extif_height_o/2 ;ext_check_h=ext_check_h+1 ) begin
for( ext_check_w=0 ;ext_check_w<extif_width_o ;ext_check_w=ext_check_w+16 ) begin
extif_rden_i = 1 ;
ext_check_A = 448*256+(extif_y_o/2+ext_check_h)*448+extif_x_o+ext_check_w ;
{ ext_rec_1_yuv[ext_check_A+00] ,ext_rec_1_yuv[ext_check_A+01] ,ext_rec_1_yuv[ext_check_A+02] ,ext_rec_1_yuv[ext_check_A+03]
,ext_rec_1_yuv[ext_check_A+04] ,ext_rec_1_yuv[ext_check_A+05] ,ext_rec_1_yuv[ext_check_A+06] ,ext_rec_1_yuv[ext_check_A+07]
,ext_rec_1_yuv[ext_check_A+08] ,ext_rec_1_yuv[ext_check_A+09] ,ext_rec_1_yuv[ext_check_A+10] ,ext_rec_1_yuv[ext_check_A+11]
,ext_rec_1_yuv[ext_check_A+12] ,ext_rec_1_yuv[ext_check_A+13] ,ext_rec_1_yuv[ext_check_A+14] ,ext_rec_1_yuv[ext_check_A+15]
} = extif_data_o ;
{ ext_debug_yuv_00 ,ext_debug_yuv_01 ,ext_debug_yuv_02 ,ext_debug_yuv_03
,ext_debug_yuv_04 ,ext_debug_yuv_05 ,ext_debug_yuv_06 ,ext_debug_yuv_07
,ext_debug_yuv_08 ,ext_debug_yuv_09 ,ext_debug_yuv_10 ,ext_debug_yuv_11
,ext_debug_yuv_12 ,ext_debug_yuv_13 ,ext_debug_yuv_14 ,ext_debug_yuv_15
} = extif_data_o ;
@(negedge clk );
end
end
extif_rden_i = 0 ;
#100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
default : // default response
begin #100 ;
@(negedge clk)
extif_done_i = 1 ;
@(negedge clk)
extif_done_i = 0 ;
end
endcase
end
end
// ctrl : fp tp & i
integer ext_ori_i_check_i_fp ;
integer ext_ori_p_check_i_fp ;
integer ext_ori_check_i_tp ;
integer ext_ori_check_i ;
integer ext_rec_i_check_i_fp ;
integer ext_rec_p_check_i_fp ;
integer ext_rec_check_i_tp ;
integer ext_rec_i_check_o_fp ;
integer ext_rec_p_check_o_fp ;
integer ext_rec_check_o_tp ;
integer ext_rec_check_i ;
// ctrl : launch logic
initial begin
rst_n = 0 ;
sys_start = 0 ;
sys_type = 0 ; // 0:I frame 1:P frame
sys_qp = 0 ;
sys_mode = 0 ; // 0:frame mode 1:MB mode
sys_x_total = 6 ;
sys_y_total = 3 ;
pre_min_size = 1 ; // 0:4x4 1:8x8
extif_wren_i = 0 ;
extif_rden_i = 0 ;
extif_addr_i = 0 ;
extif_data_i = 0 ;
frame_num = 0 ;
#100 ;
rst_n = 1'b1;
$display( "\n\n*** CHECK TOP ! ***\n" );
ext_ori_p_check_i_fp = $fopen( FETCH_P_CUR_FILE ,"r" );
ext_rec_p_check_i_fp = $fopen( FETCH_P_REF_FILE ,"r" );
ext_rec_p_check_o_fp = $fopen( FETCH_P_CHECK_FILE ,"r" );
ext_ori_i_check_i_fp = $fopen( FETCH_I_CUR_FILE ,"r" );
ext_rec_i_check_o_fp = $fopen( FETCH_I_CHECK_FILE ,"r" );
#500 ;
$monitor( "\tat %08d, Frame Number = %02d, mb_x_first = %02d, mb_y_first = %02d",
$time, frame_num, dut.u_top.u_top_ctrl.first_x_o, dut.u_top.u_top_ctrl.first_y_o );
`ifdef TEST_P
// test P
$display("\n*** TEST P FRAMES ! ***\n");
sys_type = INTER ;
sys_qp = 22 ;
for( frame_num=0 ;frame_num<8 ;frame_num=frame_num+1 ) begin
// init ori
for( ext_ori_check_i=0 ;ext_ori_check_i<448*256*3/2 ;ext_ori_check_i=ext_ori_check_i+1 ) begin
ext_ori_check_i_tp = $fread( ext_temp_yuv ,ext_ori_p_check_i_fp );
ext_ori_yuv[ext_ori_check_i] = ext_temp_yuv ;
end
// init rec
for( ext_rec_check_i=0 ;ext_rec_check_i<448*256*3/2 ;ext_rec_check_i=ext_rec_check_i+1 ) begin
ext_rec_check_i_tp = $fread( ext_temp_yuv ,ext_rec_p_check_i_fp );
ext_rec_0_yuv[ext_rec_check_i] = ext_temp_yuv ;
end
@(negedge clk );
sys_start = 1 ;
@(negedge clk );
sys_start = 0 ;
@(posedge sys_done );
#500 ;
`ifdef FETCH_AUTO_CHECK
// check rec
for( ext_rec_check_i=0 ;ext_rec_check_i<448*256*3/2 ;ext_rec_check_i=ext_rec_check_i+1 ) begin
ext_rec_check_o_tp = $fread( ext_temp_yuv ,ext_rec_p_check_o_fp );
if( ext_rec_1_yuv[ext_rec_check_i] !== ext_temp_yuv ) begin
$display( "Error!\nrec at address %d has wrong data %x which should be %x."
,ext_rec_check_i ,ext_rec_1_yuv[ext_rec_check_i] ,ext_temp_yuv );
// $finish ;
end
end
`endif
end
`endif
`ifdef TEST_I
// test I
$display("\n*** TEST I FRAMES ! ***\n");
sys_type = INTRA ;
sys_qp = 22 ;
for( frame_num=0 ;frame_num<10 ;frame_num=frame_num+1 ) begin
// init ori
for( ext_ori_check_i=0 ;ext_ori_check_i<448*256*3/2 ;ext_ori_check_i=ext_ori_check_i+1 ) begin
ext_ori_check_i_tp = $fread( ext_temp_yuv ,ext_ori_i_check_i_fp );
ext_ori_yuv[ext_ori_check_i] = ext_temp_yuv ;
end
@(negedge clk );
sys_start = 1 ;
@(negedge clk );
sys_start = 0 ;
@(posedge sys_done );
#500 ;
`ifdef FETCH_AUTO_CHECK
// check rec
for( ext_rec_check_i=0 ;ext_rec_check_i<448*256*3/2 ;ext_rec_check_i=ext_rec_check_i+1 ) begin
ext_rec_check_o_tp = $fread( ext_temp_yuv ,ext_rec_i_check_o_fp );
if( ext_rec_1_yuv[ext_rec_check_i] !== ext_temp_yuv ) begin
$display( "Error!\nrec at address %d has wrong data %x which should be %x."
,ext_rec_check_i ,ext_rec_1_yuv[ext_rec_check_i] ,ext_temp_yuv );
// $finish ;
end
end
`endif
end
`endif
#1000 ;
$display( "\n\n*** CHECK FNISHED ! ***\n" );
#1000 ;
$finish ;
end
// sram init for cabac
initial begin
$readmemh( "../../rtl/mem/sram_0_mn.dat" ,dut.u_top.u_cabac_top.cabac_slice_init_u0.cabac_mn_1p_16x64_u0.rom_1p_16x64.mem_array );
$readmemh( "../../rtl/mem/sram_1_mn.dat" ,dut.u_top.u_cabac_top.cabac_slice_init_u0.cabac_mn_1p_16x64_u1.rom_1p_16x64.mem_array );
$readmemh( "../../rtl/mem/sram_2_mn.dat" ,dut.u_top.u_cabac_top.cabac_slice_init_u0.cabac_mn_1p_16x64_u2.rom_1p_16x64.mem_array );
$readmemh( "../../rtl/mem/sram_3_mn.dat" ,dut.u_top.u_cabac_top.cabac_slice_init_u0.cabac_mn_1p_16x64_u3.rom_1p_16x64.mem_array );
$readmemh( "../../rtl/mem/sram_4_mn.dat" ,dut.u_top.u_cabac_top.cabac_slice_init_u0.cabac_mn_1p_16x64_u4.rom_1p_16x64.mem_array );
end
//*** DUMP FSDB ****************************************************************
`ifdef DUMP_FSDB
initial begin
#`DUMP_TIME ;
$fsdbDumpfile( `DUMP_FILE );
$fsdbDumpvars( tb_top );
#100 ;
$display( "\t\t dump to this test is on !\n" );
end
`endif
//*** AUTO CHECK or DUMP *******************************************************
`ifdef DUMP_FETCH
// fime_cur
integer fime_cur_debug_fp_o;
reg fime_cur_ren_r;
initial begin
fime_cur_debug_fp_o = $fopen( "./dump/fime_cur_debug.log" ,"w" );
end
always @(posedge clk ) begin
fime_cur_ren_r <= fime_cur_ren;
if( fime_cur_ren_r ) begin
$fwrite(fime_cur_debug_fp_o ,"%128x\n", fime_cur_data );
end
end
// fime_ref
integer fime_ref_debug_fp_o;
reg fime_ref_ren_r;
initial begin
fime_ref_debug_fp_o = $fopen( "./dump/fime_ref_debug.log" ,"w" );
end
always @(posedge clk ) begin
fime_ref_ren_r <= fime_ref_ren;
if( fime_ref_ren_r ) begin
$fwrite(fime_ref_debug_fp_o ,"%128x\n", fime_ref_data );
end
end
// fme_cur
integer fme_cur_debug_fp_o;
reg fme_cur_ren_r;
initial begin
fme_cur_debug_fp_o = $fopen( "./dump/fme_cur_debug.log" ,"w" );
end
always @(posedge clk ) begin
fme_cur_ren_r <= fme_cur_ren;
if( fme_cur_ren_r ) begin
$fwrite(fme_cur_debug_fp_o ,"%128x\n", fme_cur_data );
end
end
// fme_ref
integer fme_ref_debug_fp_o;
reg fme_ref_ren_r;
initial begin
fme_ref_debug_fp_o = $fopen( "./dump/fme_ref_debug.log" ,"w" );
end
always @(posedge clk ) begin
fme_ref_ren_r <= fme_ref_ren;
if( fme_ref_ren_r ) begin
$fwrite(fme_ref_debug_fp_o ,"%128x\n", fme_ref_data );
end
end
// mc_cur
integer intra_cur_debug_fp_o;
reg intra_cur_ren_r;
initial begin
intra_cur_debug_fp_o = $fopen( "./dump/mc_cur_debug.log" ,"w" );
end
always @(posedge clk ) begin
intra_cur_ren_r <= intra_cur_ren;
if( intra_cur_ren_r ) begin
$fwrite(intra_cur_debug_fp_o ,"%128x\n", intra_cur_data );
end
end
// mc_ref
integer mc_ref_debug_fp_o;
reg mc_ref_ren_r;
initial begin
mc_ref_debug_fp_o = $fopen( "./dump/mc_ref_debug.log" ,"w" );
end
always @(posedge clk ) begin
mc_ref_ren_r <= mc_ref_ren;
// if( mc_ref_ren & (!mc_ref_ren_r) ) begin
// $fwrite( mc_ref_debug_fp_o ,"*** x: %d, y: %d, sel: %d ***\n"
// ,u_top.u_top_ctrl.first_x_o ,u_top.u_top_ctrl.first_y_o ,mc_ref_sel );
// end
if( mc_ref_ren_r ) begin
$fwrite( mc_ref_debug_fp_o ,"%128x\n", mc_ref_data );
end
end
// mc_cur_mem
integer iii;
integer fp_mc;
initial begin
fp_mc= $fopen("./dump/mc_buf.log");
end
always @ (posedge clk) begin
if( u_fetch.u_ctrl.cur_chroma_done_o ) begin
for(iii=0 ;iii<64 ;iii=iii+1)
$fdisplay( fp_mc ,"%064x" ,{ u_fetch.u_cur_chroma.cur00.buf_org_0.u_ram_1p_64x192.mem_array[iii+128],
u_fetch.u_cur_chroma.cur00.buf_org_1.u_ram_1p_64x192.mem_array[iii+128],
u_fetch.u_cur_chroma.cur00.buf_org_2.u_ram_1p_64x192.mem_array[iii+128],
u_fetch.u_cur_chroma.cur00.buf_org_3.u_ram_1p_64x192.mem_array[iii+128]
});
end
end
// db_dat
integer db_dat_debug_fp_o;
reg db_ren_r ;
initial begin
db_dat_debug_fp_o = $fopen( "./dump/db_dat_debug.log" ,"w" );
end
always @(posedge clk ) begin
db_ren_r <= !u_top.u_db_top.mb_db_ren_o ;
if( db_ren_r ) begin
$fwrite( db_dat_debug_fp_o ,"%032x\n", u_top.u_db_top.mb_db_data_i );
end
end
// db_dat_o
integer db_dat_o_debug_fp_o;
integer db_dat_o_debug_i;
reg extif_rden_r ;
initial begin
db_dat_o_debug_i = 0;
db_dat_o_debug_fp_o = $fopen( "./dump/db_dat_o_debug.log" ,"w" );
end
always @(posedge clk ) begin
extif_rden_r <= extif_rden_i ;
if( extif_rden_r ) begin
$fwrite( db_dat_o_debug_fp_o ,"%032x", extif_data_o );
if( db_dat_o_debug_i==3 ) begin
$fwrite( db_dat_o_debug_fp_o ,"\n" );
end
db_dat_o_debug_i = (db_dat_o_debug_i+1)%4;
end
end
`endif
`ifdef FIME_AUTO_CHECK
initial begin
#100 ;
$display( "\t\t fime auto check is on" );
fime_check_fp_o = $fopen( FIME_CHECK_FILE , "r" );
end
always @(negedge clk ) begin
if( dut.u_top.fmeif_en_w ) begin
fime_check_tp = $fscanf( fime_check_fp_o ,"%2h" ,fime_check_mv_x );
fime_check_tp = $fscanf( fime_check_fp_o ,"%2h" ,fime_check_mv_y );
if( (fime_check_mv_x!==dut.u_top.fmeif_mv_w[2*`IMV_WIDTH-1:1*`IMV_WIDTH])
& (fime_check_mv_y!==dut.u_top.fmeif_mv_w[1*`IMV_WIDTH-1:0*`IMV_WIDTH])
) begin
$display( "at %08d, Error!\n(MV_X,MV_Y) should be (%02h,%02h), however is (%02h,%02h)",
$time,
fime_check_mv_x, fime_check_mv_y,
dut.u_top.fmeif_mv_w[2*`IMV_WIDTH-1:1*`IMV_WIDTH], dut.u_top.fmeif_mv_w[1*`IMV_WIDTH-1:0*`IMV_WIDTH]
);
#1000 ;
$finish ;
end
end
end
always @(negedge clk ) begin
if( dut.u_top.fime_done ) begin
fime_check_tp = $fscanf( fime_check_fp_o ,"%42b" ,fime_check_partition );
//$display( "\t\tfime partition: %h", u_top.fmeif_partition_w );
if( dut.u_top.fmeif_partition_w!=fime_check_partition ) begin
$display( "at %08d, Error!\nFIME_PARTITION should be %b, however is %b",
$time,
fime_check_partition,
dut.u_top.fmeif_partition_w
);
#1000 ;
$finish ;
end
end
end
`endif
`ifdef FME_AUTO_CHECK
initial begin
#100 ;
$display( "\t\t fme auto check is on" );
fme_check_fp_o = $fopen( FME_CHECK_FILE ,"r" );
end
reg [8*`PIXEL_WIDTH-1:0] fme_check_p0 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p1 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p2 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p3 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p4 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p5 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p6 ;
reg [8*`PIXEL_WIDTH-1:0] fme_check_p7 ;
always @(posedge dut.u_top.fme_done ) begin
// check 0 1 of y
for( fme_check_cntrow=0 ;fme_check_cntrow<32 ;fme_check_cntrow=fme_check_cntrow+1 ) begin
fme_check_p0 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p1 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p2 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p3 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p4 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
fme_check_p5 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
fme_check_p6 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
fme_check_p7 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
case( fme_check_cntrow%4 )
'd0: fme_check_pixel_hw = { fme_check_p0 ,fme_check_p2 ,fme_check_p1 ,fme_check_p3
,fme_check_p4 ,fme_check_p6 ,fme_check_p5 ,fme_check_p7 };
'd1: fme_check_pixel_hw = { fme_check_p1 ,fme_check_p3 ,fme_check_p2 ,fme_check_p0
,fme_check_p5 ,fme_check_p7 ,fme_check_p6 ,fme_check_p4 };
'd2: fme_check_pixel_hw = { fme_check_p2 ,fme_check_p0 ,fme_check_p3 ,fme_check_p1
,fme_check_p6 ,fme_check_p4 ,fme_check_p7 ,fme_check_p5 };
'd3: fme_check_pixel_hw = { fme_check_p3 ,fme_check_p1 ,fme_check_p0 ,fme_check_p2
,fme_check_p7 ,fme_check_p5 ,fme_check_p4 ,fme_check_p6 };
endcase
fme_check_tp = $fscanf( fme_check_fp_o ,"%h" ,fme_check_pixel_sw );
if( fme_check_pixel_sw!==fme_check_pixel_hw ) begin
$display( "at %08d, Error!\nFME_REC should be %0128h,\nhowever is %0128h.\n"
,$time ,fme_check_pixel_sw, fme_check_pixel_hw
);
#1000 ;
$finish ;
end
end
// check 2 3 of y
for( fme_check_cntrow=64 ;fme_check_cntrow<96 ;fme_check_cntrow=fme_check_cntrow+1 ) begin
fme_check_p0 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p1 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p2 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p3 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow]
: dut.u_top.fme_rec_mem_1.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow] ;
fme_check_p4 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_0.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
fme_check_p5 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_1.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
fme_check_p6 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_2.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
fme_check_p7 = dut.u_top.sel_r ? dut.u_top.fme_rec_mem_0.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow+32]
: dut.u_top.fme_rec_mem_1.buf_org_3.u_ram_1p_64x192.mem_array[fme_check_cntrow+32] ;
case(fme_check_cntrow%4)
'd0: fme_check_pixel_hw = { fme_check_p0 ,fme_check_p2 ,fme_check_p1 ,fme_check_p3
,fme_check_p4 ,fme_check_p6 ,fme_check_p5 ,fme_check_p7 };
'd1: fme_check_pixel_hw = { fme_check_p1 ,fme_check_p3 ,fme_check_p2 ,fme_check_p0
,fme_check_p5 ,fme_check_p7 ,fme_check_p6 ,fme_check_p4 };
'd2: fme_check_pixel_hw = { fme_check_p2 ,fme_check_p0 ,fme_check_p3 ,fme_check_p1
,fme_check_p6 ,fme_check_p4 ,fme_check_p7 ,fme_check_p5 };
'd3: fme_check_pixel_hw = { fme_check_p3 ,fme_check_p1 ,fme_check_p0 ,fme_check_p2
,fme_check_p7 ,fme_check_p5 ,fme_check_p4 ,fme_check_p6 };
endcase
fme_check_tp = $fscanf( fme_check_fp_o ,"%h" ,fme_check_pixel_sw );
if( fme_check_pixel_sw!==fme_check_pixel_hw ) begin
$display( "at %08d, Error!\nFME_REC should be %0128h,\nhowever is %0128h.\n"
,$time ,fme_check_pixel_sw, fme_check_pixel_hw
);
#1000 ;
$finish ;
end
end
end
`endif
`ifdef MVD_AUTO_CHECK
initial begin
#100 ;
$display( "\t\t mvd auto check is on" );
mvd_check_fp_o = $fopen( MVD_CHECK_FILE , "r" );
end
reg [2*`FMV_WIDTH-1 : 0] mvd_check_mv_c_r ;
reg [2*`FMV_WIDTH-1 : 0] mvd_check_mv_p_r ;
reg [2*`MVD_WIDTH : 0] mvd_check_mvd_and_mvp_idx_r ;
always @(negedge clk )begin
if( dut.u_top.u_mc_top.u_mvd_top.lcu_curr_state_r[2] ) begin
case( dut.u_top.u_mc_top.u_mvd_top.cu_cnt_d1_r[1:0] )
2'd1:
begin mvd_check_tp_o = $fscanf( mvd_check_fp_o ,"%b\n" ,mvd_check_mv_c_r );
mvd_check_tp_o = $fscanf( mvd_check_fp_o ,"%b\n" ,mvd_check_mv_p_r );
if( (mvd_check_mv_c_r !== dut.u_top.u_mc_top.u_mvd_top.mv_c_r)
| (mvd_check_mv_p_r !== dut.u_top.u_mc_top.u_mvd_top.mv_p_r)
) begin
$display( "at %08d (%03d), mvd is wrong!\n" ,$time ,dut.u_top.u_mc_top.u_mvd_top.cu_idx_r );
#1000 ;
$finish ;
end
end
2'd2:
begin mvd_check_tp_o = $fscanf( mvd_check_fp_o ,"%b\n" ,mvd_check_mv_p_r );
mvd_check_tp_o = $fscanf( mvd_check_fp_o ,"%b\n" ,mvd_check_mvd_and_mvp_idx_r );
if( (mvd_check_mv_p_r !== dut.u_top.u_mc_top.u_mvd_top.mv_p_r)
| (mvd_check_mvd_and_mvp_idx_r !== dut.u_top.u_mc_top.u_mvd_top.mvd_and_mvp_idx_o )
) begin
$display( "at %08d (%03d), mvd is wrong!\n" ,$time ,dut.u_top.u_mc_top.u_mvd_top.cu_idx_r );
#1000 ;
$finish ;
end
end
endcase
end
end
`endif
`ifdef DB_AUTO_CHECK
initial begin
#100 ;
$display( "\t\t db auto check is on" ); // embedded in top.v
end
`endif
`ifdef FETCH_AUTO_CHECK
initial begin
#100 ;
$display( "\t\t fetch auto check is on" ); // embedded in above tb
end
`endif
`ifdef BS_AUTO_CHECK
integer bs_i_check_fp ;
integer bs_i_check_tp ;
integer bs_p_check_fp ;
integer bs_p_check_tp ;
reg [7 : 0] bs_check_data ;
initial begin
#100 ;
$display( "\t\t bs auto check is on" );
bs_i_check_fp = $fopen( BS_I_CHECK_FILE ,"r" );
bs_p_check_fp = $fopen( BS_P_CHECK_FILE ,"r" );
end
always @(negedge clk) begin
if( dut.winc_o ) begin
if( sys_type == INTRA )
bs_i_check_tp = $fscanf( bs_i_check_fp ,"%h" ,bs_check_data );
else begin
bs_p_check_tp = $fscanf( bs_p_check_fp ,"%h" ,bs_check_data );
end
if( bs_check_data!==dut.wdata_o ) begin
$display( "at %08d, Error!\nBS should be %h, however is data %h"
,$time ,bs_check_data ,dut.wdata_o
);
//$display("at %d,\nERROR(MB x:%3d y:%3d): check_data(%h) != bs_data(%h)", $time, u_top.mb_x_ec, u_top.mb_y_ec, check_data, u_top.wdata_o);
//#5000 $finish ;
end
end
end
`endif
//*** OTHER BENCH **************************************************************
`ifdef DUMP_BS
`include "./bench/bs_dump.v"
`endif
`ifdef DUMP_CMB
`include "./bench/cmb_dump.v"
`endif
`ifdef DUMP_INTRA
`include "./bench/intra_dump.v"
`endif
`ifdef DUMP_TQ
`include "./bench/tq_dump.v"
`endif
`ifdef DUMP_CABAC
`include "./bench/cabac_dump.v"
`endif
`ifdef DUMP_DB
`include "./bench/db_dump.v"
`endif
`ifdef DUMP_FME
`include "./bench/fme_dump.v"
`endif
`ifdef DUMP_MC
`include "./bench/mc_dump.v"
`endif
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// This module to implement the extended CSR
// current this is an empty module, user can hack it
// become a real one if they want
//
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_CSR_EAI//{
module e203_extend_csr(
// The Handshake Interface
input eai_csr_valid,
output eai_csr_ready,
input [31:0] eai_csr_addr,
input eai_csr_wr,
input [31:0] eai_csr_wdata,
output [31:0] eai_csr_rdata,
input clk,
input rst_n
);
assign eai_csr_ready = 1'b1;
assign eai_csr_rdata = 32'b0;
endmodule
`endif//}
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`define PKT_SIZE 6
`include "logic_analyzer_defines.v"
module uart_la_interface #(
parameter DEFAULT_BAUDRATE = 115200
)(
input rst,
input clk,
output reg o_en_la,
output reg o_la_reset,
input i_finished,
input [31:0] i_start_pos,
output reg o_uart_set_value_stb,
output reg o_force_trigger,
//logic analyzer control
output [31:0] o_trigger,
output [31:0] o_trigger_mask,
output [31:0] o_trigger_after,
output [31:0] o_trigger_edge,
output [31:0] o_both_edges,
output [31:0] o_repeat_count,
//data interface
input [31:0] i_la_rd_size,
output reg [31:0] o_la_rd_addr,
input [31:0] i_la_rd_data,
input i_phy_rx,
output o_phy_tx
);
localparam IDLE = 0;
localparam READ_COMMAND = 1;
localparam READ_VALUE = 2;
localparam READ_ENABLE_SET = 3;
localparam READ_LINE_FEED = 4;
localparam SEND_RESPONSE = 5;
localparam TRIGGER = 0;
localparam TRIGGER_MASK = 1;
localparam TRIGGER_AFTER = 2;
localparam TRIGGER_EDGE = 3;
localparam BOTH_EDGES = 4;
localparam REPEAT_COUNT = 5;
//UART Control
reg r_uart_wr_stb;
reg [7:0] r_uart_wr_data;
reg [3:0] r_index;
wire w_uart_rd_empty;
wire w_uart_rcv_stb;
wire [7:0] w_uart_rd_data;
reg [31:0] r_uart_rd_count;
reg [31:0] r_packet_data[5:0];
reg [31:0] r_wr_pos;
//Register/Wires
reg [3:0] rd_state = IDLE;
reg r_lcl_rst = 1;
reg [3:0] wr_state = IDLE;
reg r_wr_en;
reg r_wr_fin;
reg [7:0] r_cmd_rsps;
reg [7:0] r_rsp_sts;
wire [3:0] nibble;
wire [7:0] hex_value;
reg [7:0] r_command;
reg [31:0] r_value;
wire w_uart_wr_busy;
//submodules
uart #(
.DEFAULT_BAUDRATE (DEFAULT_BAUDRATE )
) uart (
.clk (clk ),
.rst (rst ),
.tx (o_phy_tx ),
.transmit (r_uart_wr_stb ),
.tx_byte (r_uart_wr_data ),
.is_transmitting (w_uart_wr_busy ),
.rx (i_phy_rx ),
.rx_byte (w_uart_rd_data ),
.received (w_uart_rcv_stb ),
.set_clock_div (1'h0 )
);
//asynchronous logic
assign hex_value = (r_value[31:28] >= 8'hA) ? (r_value[31:28] + 8'h37) : (r_value[31:28] + 8'h30);
assign nibble = (w_uart_rd_data >= 8'h41) ? (w_uart_rd_data - 8'h37) : (w_uart_rd_data - 8'h30);
assign valid_hex = ((8'h41 <= w_uart_rd_data) && (w_uart_rd_data <= 8'h46)) ||
((8'h30 <= w_uart_rd_data) && (w_uart_rd_data <= 8'h39));
assign o_trigger = r_packet_data[TRIGGER];
assign o_trigger_mask = r_packet_data[TRIGGER_MASK];
assign o_trigger_after = r_packet_data[TRIGGER_AFTER];
assign o_trigger_edge = r_packet_data[TRIGGER_EDGE];
assign o_both_edges = r_packet_data[BOTH_EDGES];
assign o_repeat_count = r_packet_data[REPEAT_COUNT];
//UART Interface Controller
integer i;
always @ (posedge clk) begin
//De-assert strobes
r_wr_en <= 0;
o_uart_set_value_stb <= 0;
o_la_reset <= 0;
o_force_trigger <= 0;
if (rst || r_lcl_rst) begin
o_en_la <= 0;
r_index <= 0;
rd_state <= IDLE;
r_cmd_rsps <= 0;
r_command <= 0;
r_rsp_sts <= 0;
r_uart_rd_count <= 0;
for (i = 0; i < `PKT_SIZE; i = i + 1) begin
r_packet_data[i] <= 0;
end
end
else begin
//check if incomming UART is not empty
case (rd_state)
IDLE: begin
r_uart_rd_count <= 0;
r_rsp_sts <= 0;
if (w_uart_rcv_stb && (w_uart_rd_data == `START_ID)) begin
rd_state <= READ_COMMAND;
end
end
READ_COMMAND: begin
if (w_uart_rcv_stb) begin
r_command <= w_uart_rd_data;
case (w_uart_rd_data)
`LA_PING: begin
r_cmd_rsps <= `RESPONSE_SUCCESS;
rd_state <= READ_LINE_FEED;
end
`LA_RESET: begin
o_la_reset <= 1;
r_cmd_rsps <= `RESPONSE_SUCCESS;
rd_state <= READ_LINE_FEED;
end
`LA_FORCE_TRIGGER: begin
o_force_trigger <= 1;
r_cmd_rsps <= `RESPONSE_SUCCESS;
rd_state <= READ_LINE_FEED;
end
`LA_WRITE_TRIGGER: begin
//disable the LA when updating settings
o_en_la <= 0;
rd_state <= READ_VALUE;
r_index <= TRIGGER;
end
`LA_WRITE_MASK: begin
//disable the LA when updating settings
o_en_la <= 0;
rd_state <= READ_VALUE;
r_index <= TRIGGER_MASK;
end
`LA_WRITE_TRIGGER_AFTER: begin
//disable the LA when updating settings
o_en_la <= 0;
rd_state <= READ_VALUE;
r_index <= TRIGGER_AFTER;
end
`LA_WRITE_TRIGGER_EDGE: begin
//disable the LA when updating settings
o_en_la <= 0;
rd_state <= READ_VALUE;
r_index <= TRIGGER_EDGE;
end
`LA_WRITE_BOTH_EDGES: begin
//disable the LA when updating settings
o_en_la <= 0;
rd_state <= READ_VALUE;
r_index <= BOTH_EDGES;
end
`LA_WRITE_REPEAT_COUNT: begin
//disable the LA when updating settings
o_en_la <= 0;
rd_state <= READ_VALUE;
r_index <= REPEAT_COUNT;
end
`LA_SET_ENABLE: begin
rd_state <= READ_ENABLE_SET;
end
`LA_GET_ENABLE: begin
r_cmd_rsps <= `RESPONSE_SUCCESS;
rd_state <= READ_LINE_FEED;
r_rsp_sts <= o_en_la + `HEX_0;
end
`LA_GET_START_POS: begin
rd_state <= READ_LINE_FEED;
end
`LA_GET_SIZE: begin
rd_state <= READ_LINE_FEED;
end
default: begin
//unrecognized r_command
r_cmd_rsps <= `RESPONSE_FAIL;
rd_state <= READ_LINE_FEED;
end
endcase
end
end
READ_VALUE: begin
if (w_uart_rcv_stb) begin
r_packet_data[r_index] <= {r_packet_data[r_index][27:0], nibble};
r_uart_rd_count <= r_uart_rd_count + 1;
if (r_uart_rd_count >= 7) begin
o_uart_set_value_stb <= 1;
r_cmd_rsps <= `RESPONSE_SUCCESS;
rd_state <= READ_LINE_FEED;
end
else if (!valid_hex) begin
r_cmd_rsps <= `RESPONSE_FAIL;
rd_state <= READ_LINE_FEED;
end
end
end
READ_ENABLE_SET: begin
if (w_uart_rcv_stb) begin
if (w_uart_rd_data == (0 + `HEX_0)) begin
o_en_la <= 0;
r_cmd_rsps <= `RESPONSE_SUCCESS;
end
else if (w_uart_rd_data == (1 + `HEX_0)) begin
o_en_la <= 1;
r_cmd_rsps <= `RESPONSE_SUCCESS;
end
else begin
r_cmd_rsps <= `RESPONSE_FAIL;
end
rd_state <= READ_LINE_FEED;
end
end
READ_LINE_FEED: begin
if (w_uart_rcv_stb) begin
if (w_uart_rd_data == (`LINE_FEED)) begin
rd_state <= SEND_RESPONSE;
end
end
end
SEND_RESPONSE: begin
r_wr_en <= 1;
if (r_wr_fin) begin
r_wr_en <= 0;
rd_state <= IDLE;
end
end
default: begin
rd_state <= IDLE;
end
endcase
//write data back to the host
if (wr_state == SEND_DATA_PACKET) begin
o_en_la <= 0;
end
end
end
localparam RESPONSE_WRITE_ID = 1;
localparam RESPONSE_WRITE_STATUS = 2;
localparam RESPONSE_WRITE_ARG = 3;
localparam RESPONSE_WRITE_VALUE = 4;
localparam SEND_START_POS = 5;
localparam GET_DATA_PACKET = 6;
localparam SEND_DATA_PACKET = 7;
localparam SEND_CARRIAGE_RETURN = 8;
localparam SEND_LINE_FEED = 9;
localparam FINISHED = 10;
//write data state machine
always @ (posedge clk) begin
//Deassert Strobes
r_uart_wr_stb <= 0;
r_wr_fin <= 0;
if (rst || r_lcl_rst) begin
r_uart_wr_data <= `CARRIAGE_RETURN;
wr_state <= IDLE;
o_la_rd_addr <= 0;
r_wr_pos <= 0;
r_lcl_rst <= 0;
end
else begin
case (wr_state)
IDLE: begin
r_wr_pos <= 0;
o_la_rd_addr <= 0;
if (r_wr_en) begin
wr_state <= RESPONSE_WRITE_ID;
end
else if ((rd_state == IDLE) && i_finished) begin
wr_state <= SEND_START_POS;
r_value <= i_start_pos;
end
end
RESPONSE_WRITE_ID: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_uart_wr_data <= `RESPONSE_ID;
r_uart_wr_stb <= 1;
wr_state <= RESPONSE_WRITE_STATUS;
end
end
RESPONSE_WRITE_STATUS: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_uart_wr_data <= r_cmd_rsps;
r_uart_wr_stb <= 1;
if (r_command == `LA_GET_ENABLE) begin
wr_state <= RESPONSE_WRITE_ARG;
end
else if (r_command == `LA_GET_SIZE) begin
wr_state <= RESPONSE_WRITE_VALUE;
r_value <= i_la_rd_size;
end
else if (r_command == `LA_GET_START_POS) begin
wr_state <= RESPONSE_WRITE_VALUE;
r_value <= i_start_pos;
end
else begin
wr_state <= SEND_CARRIAGE_RETURN;
end
end
end
RESPONSE_WRITE_ARG: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_uart_wr_data <= r_rsp_sts;
r_uart_wr_stb <= 1;
wr_state <= SEND_CARRIAGE_RETURN;
end
end
RESPONSE_WRITE_VALUE: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_value <= {r_value[27:0], 4'h0};
r_uart_wr_stb <= 1;
r_uart_wr_data <= hex_value;
r_wr_pos <= r_wr_pos + 1;
if (r_wr_pos >= 7) begin
wr_state <= SEND_CARRIAGE_RETURN;
end
end
end
//Write Data
SEND_START_POS: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_value <= {r_value[27:0], 4'h0};
r_uart_wr_stb <= 1;
r_uart_wr_data <= hex_value;
r_wr_pos <= r_wr_pos + 1;
if (r_wr_pos >= 7) begin
wr_state <= GET_DATA_PACKET;
end
end
end
GET_DATA_PACKET: begin
r_value <= i_la_rd_data;
r_wr_pos <= 0;
o_la_rd_addr <= o_la_rd_addr + 1;
wr_state <= SEND_DATA_PACKET;
end
SEND_DATA_PACKET: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_value <= {r_value[27:0], 4'h0};
r_uart_wr_stb <= 1;
r_uart_wr_data <= hex_value;
r_wr_pos <= r_wr_pos + 1;
if (r_wr_pos >= 7) begin
if (o_la_rd_addr < i_la_rd_size) begin
wr_state <= GET_DATA_PACKET;
end
else begin
wr_state <= SEND_CARRIAGE_RETURN;
end
end
end
end
SEND_CARRIAGE_RETURN: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_uart_wr_stb <= 1;
r_uart_wr_data <= `CARRIAGE_RETURN;
wr_state <= SEND_LINE_FEED;
end
end
SEND_LINE_FEED: begin
if (!w_uart_wr_busy && !r_uart_wr_stb) begin
r_uart_wr_stb <= 1;
r_uart_wr_data <= `LINE_FEED;
wr_state <= FINISHED;
r_wr_fin <= 1;
end
end
FINISHED: begin
r_wr_fin <= 1;
if (!r_wr_en) begin
r_wr_fin <= 0;
wr_state <= IDLE;
end
end
default begin
wr_state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_BEHAVIORAL_PP_V |
`timescale 1 ns / 1 ps
`include "MIPI_CSI_2_RX_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S_AXI_LITE_MAX_BURST_LENGTH 1
`define S_AXI_LITE_DATA_BUS_WIDTH 32
`define S_AXI_LITE_ADDRESS_BUS_WIDTH 32
`define S_AXI_LITE_MAX_DATA_SIZE (`S_AXI_LITE_DATA_BUS_WIDTH*`S_AXI_LITE_MAX_BURST_LENGTH)/8
// AMBA AXI4 Lite Range Constants
`define S_AXI_INTR_MAX_BURST_LENGTH 1
`define S_AXI_INTR_DATA_BUS_WIDTH 32
`define S_AXI_INTR_ADDRESS_BUS_WIDTH 32
`define S_AXI_INTR_MAX_DATA_SIZE (`S_AXI_INTR_DATA_BUS_WIDTH*`S_AXI_INTR_MAX_BURST_LENGTH)/8
module MIPI_CSI_2_RX_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
wire tb_irq;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.irq(tb_irq));
// Local Variables
// AMBA S_AXI_LITE AXI4 Lite Local Reg
reg [`S_AXI_LITE_DATA_BUS_WIDTH-1:0] S_AXI_LITE_rd_data_lite;
reg [`S_AXI_LITE_DATA_BUS_WIDTH-1:0] S_AXI_LITE_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S_AXI_LITE_lite_response;
reg [`S_AXI_LITE_ADDRESS_BUS_WIDTH-1:0] S_AXI_LITE_mtestAddress;
reg [3-1:0] S_AXI_LITE_mtestProtection_lite;
integer S_AXI_LITE_mtestvectorlite; // Master side testvector
integer S_AXI_LITE_mtestdatasizelite;
// AMBA S_AXI_INTR Interrupt AXI4 Lite Local Reg
reg [`S_AXI_INTR_DATA_BUS_WIDTH-1:0] S_AXI_INTR_globalenData;
reg [`S_AXI_INTR_DATA_BUS_WIDTH-1:0] S_AXI_INTR_intrenData;
reg [`S_AXI_INTR_DATA_BUS_WIDTH-1:0] S_AXI_INTR_pendData;
reg [`S_AXI_INTR_DATA_BUS_WIDTH-1:0] S_AXI_INTR_ackData;
reg [`S_AXI_INTR_ADDRESS_BUS_WIDTH-1:0] S_AXI_INTR_globalenAddress;
reg [`S_AXI_INTR_ADDRESS_BUS_WIDTH-1:0] S_AXI_INTR_intrenAddress;
reg [`S_AXI_INTR_ADDRESS_BUS_WIDTH-1:0] S_AXI_INTR_pendAddress;
reg [`S_AXI_INTR_ADDRESS_BUS_WIDTH-1:0] S_AXI_INTR_ackAddress;
reg [`RESP_BUS_WIDTH-1:0] S_AXI_INTR_lite_response;
reg [3-1:0] S_AXI_INTR_mtestProtection_lite;
integer S_AXI_INTR_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S_AXI_LITE_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S_AXI_LITE");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S_AXI_LITE_mtestvectorlite = 0;
S_AXI_LITE_mtestAddress = `S_AXI_LITE_SLAVE_ADDRESS;
S_AXI_LITE_mtestProtection_lite = 0;
S_AXI_LITE_mtestdatasizelite = `S_AXI_LITE_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S_AXI_LITE_mtestvectorlite = 0; S_AXI_LITE_mtestvectorlite <= 3; S_AXI_LITE_mtestvectorlite = S_AXI_LITE_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_LITE_mtestAddress,
S_AXI_LITE_mtestProtection_lite,
S_AXI_LITE_test_data_lite[S_AXI_LITE_mtestvectorlite],
S_AXI_LITE_mtestdatasizelite,
S_AXI_LITE_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_LITE_mtestvectorlite,S_AXI_LITE_test_data_lite[S_AXI_LITE_mtestvectorlite],S_AXI_LITE_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_LITE_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_LITE_mtestAddress,
S_AXI_LITE_mtestProtection_lite,
S_AXI_LITE_rd_data_lite,
S_AXI_LITE_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_LITE_mtestvectorlite,S_AXI_LITE_rd_data_lite,S_AXI_LITE_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_LITE_lite_response);
COMPARE_LITE_DATA(S_AXI_LITE_test_data_lite[S_AXI_LITE_mtestvectorlite],S_AXI_LITE_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_LITE_mtestvectorlite,S_AXI_LITE_mtestvectorlite);
S_AXI_LITE_mtestAddress = S_AXI_LITE_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI_LITE: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
task automatic S_AXI_INTR_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S_AXI_INTR");
$display("Simple Interrupt generation test");
$display("---------------------------------------------------------");
//Initializing local registers
S_AXI_INTR_globalenAddress = `S_AXI_INTR_SLAVE_ADDRESS;
S_AXI_INTR_intrenAddress = `S_AXI_INTR_SLAVE_ADDRESS + 32'h00000004;
S_AXI_INTR_pendAddress = `S_AXI_INTR_SLAVE_ADDRESS + 32'h00000010;
S_AXI_INTR_ackAddress = `S_AXI_INTR_SLAVE_ADDRESS + 32'h0000000c;
S_AXI_INTR_globalenData = 32'h00000001;
S_AXI_INTR_intrenData = 32'h00000001;
S_AXI_INTR_ackData = 32'h00000001;
S_AXI_INTR_pendData = 32'h00000000;
S_AXI_INTR_mtestProtection_lite = 0;
S_AXI_INTR_mtestdatasizelite = `S_AXI_INTR_MAX_DATA_SIZE;
//Enabling global interrupt generation
dut.`BD_INST_NAME.master_1.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_INTR_globalenAddress,
S_AXI_INTR_mtestProtection_lite,
S_AXI_INTR_globalenData,
S_AXI_INTR_mtestdatasizelite,
S_AXI_INTR_lite_response);
//Enabling Interrupt generation at bit 0
dut.`BD_INST_NAME.master_1.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_INTR_intrenAddress,
S_AXI_INTR_mtestProtection_lite,
S_AXI_INTR_intrenData,
S_AXI_INTR_mtestdatasizelite,
S_AXI_INTR_lite_response);
wait(tb_irq == `IRQ_ACTIVE_STATE) @(posedge tb_ACLK);
begin
#100;
//Reading Interrupt pending register value
dut.`BD_INST_NAME.master_1.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_INTR_pendAddress,
S_AXI_INTR_mtestProtection_lite,
S_AXI_INTR_pendData,
S_AXI_INTR_lite_response);
if ( S_AXI_INTR_pendData[0] != 1'b1) begin
$display("ERROR: Interrupt not generated at bit0");
$display("PTGEN_TEST: FAILED!");
$stop;
end
//clearing irq_f2p through Interrupt acknowledgement register
dut.`BD_INST_NAME.master_1.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_INTR_ackAddress,
S_AXI_INTR_mtestProtection_lite,
S_AXI_INTR_ackData,
S_AXI_INTR_mtestdatasizelite,
S_AXI_INTR_lite_response);
#100;
//Reading Interrupt pending register value
dut.`BD_INST_NAME.master_1.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_INTR_pendAddress,
S_AXI_INTR_mtestProtection_lite,
S_AXI_INTR_pendData,
S_AXI_INTR_lite_response);
if ( S_AXI_INTR_pendData[0] != 1'b0) begin
$display("ERROR: Interrupt not cleared at bit0");
$display("PTGEN_TEST: FAILED!");
$stop;
end else begin
$display ("PASS: Interrupt test successful");
$display("PTGEN_TEST: PASSED!");
end
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI_INTR: PTGEN_TEST_FINISHED!");
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S_AXI_LITE_test_data_lite[0] = 32'h0101FFFF;
S_AXI_LITE_test_data_lite[1] = 32'habcd0001;
S_AXI_LITE_test_data_lite[2] = 32'hdead0011;
S_AXI_LITE_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S_AXI_LITE_TEST();
S_AXI_INTR_TEST();
end
endmodule
|
module multiboot (
input wire clk,
input wire clk_icap, // WARNING: this clock must not be greater than 20MHz (50ns period)
input wire rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regwr,
input wire [7:0] din
);
parameter ADDR_COREADDR = 8'hFC,
ADDR_COREBOOT = 8'hFD;
reg [23:0] spi_addr = 24'h0AC000; // default: SPI address of second core as defined by the SPI memory map
reg writting_to_spi_addr = 1'b0;
reg writting_to_bootcore = 1'b0;
reg boot_core = 1'b0;
always @(posedge clk) begin
if (rst_n == 1'b0) begin
writting_to_spi_addr <= 1'b0;
writting_to_bootcore <= 1'b0;
boot_core <= 1'b0;
end
else begin
if (zxuno_addr == ADDR_COREADDR) begin
if (zxuno_regwr == 1'b1 && writting_to_spi_addr == 1'b0) begin
spi_addr <= {spi_addr[15:0], din};
writting_to_spi_addr <= 1'b1;
end
if (zxuno_regwr == 1'b0) begin
writting_to_spi_addr <= 1'b0;
end
end
else begin
writting_to_spi_addr <= 1'b0;
end
if (zxuno_addr == ADDR_COREBOOT) begin
if (zxuno_regwr == 1'b1 && din[0] == 1'b1 && writting_to_bootcore == 1'b0) begin
boot_core <= 1'b1;
writting_to_bootcore <= 1'b1;
end
if (writting_to_bootcore == 1'b1) begin
boot_core <= 1'b0;
end
if (zxuno_regwr == 1'b0) begin
writting_to_bootcore <= 1'b0;
end
end
else begin
boot_core <= 1'b0;
writting_to_bootcore <= 1'b0;
end
end
end
reg [4:0] q = 5'b00000;
reg reboot_ff = 1'b0;
always @(posedge clk_icap) begin
q[0] <= boot_core;
q[1] <= q[0];
q[2] <= q[1];
q[3] <= q[2];
q[4] <= q[3];
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
end
multiboot_spartan6 hacer_multiboot (
.CLK(clk_icap),
.MBT_RESET(1'b0),
.MBT_REBOOT(reboot_ff),
.spi_addr(spi_addr)
);
endmodule
module multiboot_spartan6 (
input wire CLK,
input wire MBT_RESET,
input wire MBT_REBOOT,
input wire [23:0] spi_addr
);
reg [15:0] icap_din;
reg icap_ce;
reg icap_wr;
reg [15:0] ff_icap_din_reversed;
reg ff_icap_ce;
reg ff_icap_wr;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
.CE (ff_icap_ce), // Clock enable input
.CLK (CLK), // Clock input
.I (ff_icap_din_reversed), // 16-bit data input
.WRITE (ff_icap_wr) // Write input
);
// -------------------------------------------------
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
// -------------------------------------------------
parameter IDLE = 0,
SYNC_H = 1,
SYNC_L = 2,
CWD_H = 3,
CWD_L = 4,
GEN1_H = 5,
GEN1_L = 6,
GEN2_H = 7,
GEN2_L = 8,
GEN3_H = 9,
GEN3_L = 10,
GEN4_H = 11,
GEN4_L = 12,
GEN5_H = 13,
GEN5_L = 14,
NUL_H = 15,
NUL_L = 16,
MOD_H = 17,
MOD_L = 18,
HCO_H = 19,
HCO_L = 20,
RBT_H = 21,
RBT_L = 22,
NOOP_0 = 23,
NOOP_1 = 24,
NOOP_2 = 25,
NOOP_3 = 26;
reg [4:0] state;
reg [4:0] next_state;
always @*
begin: COMB
case (state)
IDLE:
begin
if (MBT_REBOOT)
begin
next_state = SYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hAA99; // Sync word 1
end
else
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'hFFFF; // Null
end
end
SYNC_H:
begin
next_state = SYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h5566; // Sync word 2
end
SYNC_L:
begin
next_state = NUL_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
NUL_H:
begin
// next_state = NUL_L;
next_state = GEN1_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
end
//Q
GEN1_H:
begin
next_state = GEN1_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
end
GEN1_L:
begin
next_state = GEN2_H;
icap_ce = 0;
icap_wr = 0;
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
end
GEN2_H:
begin
next_state = GEN2_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3281; // Escritura a reg GENERAL_2
end
GEN2_L:
begin
next_state = MOD_H;
icap_ce = 0;
icap_wr = 0;
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
end
/////// Registro MODE (para carga a 4x tras reboot)
MOD_H:
begin
next_state = MOD_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3301; // Escritura a reg MODE
end
MOD_L:
begin
next_state = NUL_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
end
/////
NUL_L:
begin
next_state = RBT_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
RBT_H:
begin
next_state = RBT_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h000E; // REBOOT Command 0x000E
end
//--------------------
RBT_L:
begin
next_state = NOOP_0;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_0:
begin
next_state = NOOP_1;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_1:
begin
next_state = NOOP_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_2:
begin
next_state = NOOP_3;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
//--------------------
NOOP_3:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // NULL value
end
default:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // 16'h1111"
end
endcase
end
always @(posedge CLK)
begin: SEQ
if (MBT_RESET)
state <= IDLE;
else
state <= next_state;
end
always @(posedge CLK)
begin: ICAP_FF
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
ff_icap_din_reversed[1] <= icap_din[6];
ff_icap_din_reversed[2] <= icap_din[5];
ff_icap_din_reversed[3] <= icap_din[4];
ff_icap_din_reversed[4] <= icap_din[3];
ff_icap_din_reversed[5] <= icap_din[2];
ff_icap_din_reversed[6] <= icap_din[1];
ff_icap_din_reversed[7] <= icap_din[0];
ff_icap_din_reversed[8] <= icap_din[15];
ff_icap_din_reversed[9] <= icap_din[14];
ff_icap_din_reversed[10] <= icap_din[13];
ff_icap_din_reversed[11] <= icap_din[12];
ff_icap_din_reversed[12] <= icap_din[11];
ff_icap_din_reversed[13] <= icap_din[10];
ff_icap_din_reversed[14] <= icap_din[9];
ff_icap_din_reversed[15] <= icap_din[8];
ff_icap_ce <= icap_ce;
ff_icap_wr <= icap_wr;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:57:55 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top design_1_auto_pc_0 -prefix
// design_1_auto_pc_0_ design_1_auto_pc_0_sim_netlist.v
// Design : design_1_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_awready,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_awready;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [11:4]C;
wire [22:0]Q;
wire \RD.ar_channel_0_n_14 ;
wire \RD.ar_channel_0_n_15 ;
wire \RD.ar_channel_0_n_44 ;
wire \RD.ar_channel_0_n_45 ;
wire \RD.ar_channel_0_n_46 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_5 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_10;
wire SI_REG_n_132;
wire SI_REG_n_133;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_154;
wire SI_REG_n_155;
wire SI_REG_n_157;
wire SI_REG_n_160;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_168;
wire SI_REG_n_169;
wire SI_REG_n_170;
wire SI_REG_n_171;
wire SI_REG_n_172;
wire SI_REG_n_173;
wire SI_REG_n_174;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_183;
wire SI_REG_n_184;
wire \WR.aw_channel_0_n_47 ;
wire \WR.aw_channel_0_n_48 ;
wire \WR.aw_channel_0_n_49 ;
wire \WR.aw_channel_0_n_50 ;
wire \WR.aw_channel_0_n_7 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire \WR.b_channel_0_n_3 ;
wire aclk;
wire \ar_pipe/m_valid_i0 ;
wire \ar_pipe/p_1_in ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire \aw_pipe/p_1_in ;
wire [11:0]b_awid;
wire [3:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
wire \cmd_translator_0/incr_cmd_0/sel_first ;
wire \cmd_translator_0/incr_cmd_0/sel_first_4 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [2:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_push;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire shandshake;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel \RD.ar_channel_0
(.CO(SI_REG_n_145),
.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.E(\ar_pipe/p_1_in ),
.O({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149}),
.Q(\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.S({\RD.ar_channel_0_n_44 ,\RD.ar_channel_0_n_45 ,\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_160),
.\cnt_read_reg[1]_rep__0 (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_14 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_15 ),
.\m_payload_i_reg[11] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
.\m_payload_i_reg[35] (SI_REG_n_164),
.\m_payload_i_reg[35]_0 (SI_REG_n_165),
.\m_payload_i_reg[38] (SI_REG_n_184),
.\m_payload_i_reg[3] (SI_REG_n_175),
.\m_payload_i_reg[3]_0 ({SI_REG_n_137,SI_REG_n_138,SI_REG_n_139,SI_REG_n_140}),
.\m_payload_i_reg[44] (SI_REG_n_166),
.\m_payload_i_reg[47] (SI_REG_n_167),
.\m_payload_i_reg[47]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
.\m_payload_i_reg[61] ({s_arid,si_rs_arlen,si_rs_arburst,si_rs_arsize,si_rs_araddr}),
.\m_payload_i_reg[6] ({SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174}),
.m_valid_i0(\ar_pipe/m_valid_i0 ),
.\r_arid_r_reg[11] (s_arid_r),
.r_push(r_push),
.r_rlast(r_rlast),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(s_axi_arready),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_5 ),
.\wrap_second_len_r_reg[0] (SI_REG_n_157));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_push(r_push),
.r_rlast(r_rlast),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ));
design_1_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice SI_REG
(.CO(SI_REG_n_132),
.D({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_133,SI_REG_n_134,SI_REG_n_135,SI_REG_n_136}),
.Q({s_awid,si_rs_awlen,si_rs_awburst,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr_reg(\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_incr_reg[11] (C),
.\axaddr_incr_reg[11]_0 ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
.\axaddr_incr_reg[3] ({SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149}),
.\axaddr_incr_reg[3]_0 (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_incr_reg[7] ({SI_REG_n_137,SI_REG_n_138,SI_REG_n_139,SI_REG_n_140}),
.\axaddr_incr_reg[7]_0 (SI_REG_n_145),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
.\axaddr_offset_r_reg[0] (SI_REG_n_175),
.\axaddr_offset_r_reg[1] (SI_REG_n_164),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_154),
.\axlen_cnt_reg[3]_0 (SI_REG_n_167),
.b_push(b_push),
.\cnt_read_reg[3]_rep__2 (\RD.r_channel_0_n_0 ),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\m_axi_araddr[10] (SI_REG_n_184),
.\m_axi_awaddr[10] (SI_REG_n_183),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_44 ,\RD.ar_channel_0_n_45 ,\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 }),
.m_valid_i0(\ar_pipe/m_valid_i0 ),
.next_pending_r_reg(SI_REG_n_155),
.next_pending_r_reg_0(SI_REG_n_166),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.sel_first_1(\cmd_translator_0/incr_cmd_0/sel_first ),
.shandshake(shandshake),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\RD.ar_channel_0_n_15 ),
.\state_reg[1] (\WR.aw_channel_0_n_7 ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\RD.ar_channel_0_n_5 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_14 ),
.\state_reg[1]_rep_1 (\ar_pipe/p_1_in ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\wrap_cnt_r_reg[2] (SI_REG_n_157),
.\wrap_cnt_r_reg[2]_0 (SI_REG_n_160),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[2] (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[2]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3] (SI_REG_n_165),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel \WR.aw_channel_0
(.CO(SI_REG_n_132),
.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_133,SI_REG_n_134,SI_REG_n_135,SI_REG_n_136}),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_3 ),
.\cnt_read_reg[1]_rep__0_0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[11] (C),
.\m_payload_i_reg[38] (SI_REG_n_183),
.\m_payload_i_reg[46] (SI_REG_n_155),
.\m_payload_i_reg[47] (SI_REG_n_154),
.\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[0] (\WR.aw_channel_0_n_7 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.shandshake(shandshake),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp),
.\state_reg[0] (\WR.b_channel_0_n_3 ));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel
(\axaddr_incr_reg[3] ,
sel_first,
\wrap_boundary_axaddr_r_reg[11] ,
Q,
axaddr_offset,
\axaddr_offset_r_reg[3] ,
r_push,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
m_axi_arvalid,
r_rlast,
m_valid_i0,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
O,
\m_payload_i_reg[47] ,
m_axi_arready,
si_rs_arvalid,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[61] ,
CO,
\cnt_read_reg[1]_rep__0 ,
D,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[44] ,
areset_d1,
\m_payload_i_reg[3]_0 ,
\m_payload_i_reg[11] ,
s_axi_arvalid,
s_ready_i_reg,
\m_payload_i_reg[38] ,
\wrap_second_len_r_reg[0] ,
\m_payload_i_reg[6] );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output \wrap_boundary_axaddr_r_reg[11] ;
output [2:0]Q;
output [0:0]axaddr_offset;
output [2:0]\axaddr_offset_r_reg[3] ;
output r_push;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output m_axi_arvalid;
output r_rlast;
output m_valid_i0;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input m_axi_arready;
input si_rs_arvalid;
input \axaddr_offset_r_reg[3]_0 ;
input [30:0]\m_payload_i_reg[61] ;
input [0:0]CO;
input \cnt_read_reg[1]_rep__0 ;
input [1:0]D;
input \m_payload_i_reg[35] ;
input [2:0]\m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[44] ;
input areset_d1;
input [3:0]\m_payload_i_reg[3]_0 ;
input [3:0]\m_payload_i_reg[11] ;
input s_axi_arvalid;
input s_ready_i_reg;
input \m_payload_i_reg[38] ;
input [0:0]\wrap_second_len_r_reg[0] ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [2:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_10;
wire ar_cmd_fsm_0_n_13;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_18;
wire ar_cmd_fsm_0_n_22;
wire ar_cmd_fsm_0_n_23;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_4;
wire ar_cmd_fsm_0_n_6;
wire areset_d1;
wire [3:0]\axaddr_incr_reg[3] ;
wire [0:0]axaddr_offset;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_8;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[3] ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[47] ;
wire [2:0]\m_payload_i_reg[47]_0 ;
wire [30:0]\m_payload_i_reg[61] ;
wire [6:0]\m_payload_i_reg[6] ;
wire m_valid_i0;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push;
wire r_rlast;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sel_first;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]state;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [0:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:3]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[0] ;
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(state),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_18),
.\axaddr_offset_r_reg[0] (axaddr_offset),
.\axaddr_offset_r_reg[0]_0 (\wrap_cmd_0/axaddr_offset_r ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[0] (ar_cmd_fsm_0_n_6),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_9),
.\axlen_cnt_reg[3] (ar_cmd_fsm_0_n_17),
.\axlen_cnt_reg[6] (cmd_translator_0_n_10),
.\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[61] [15:14]),
.\m_payload_i_reg[44]_0 (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 [2:1]),
.m_valid_i0(m_valid_i0),
.next_pending_r_reg(cmd_translator_0_n_1),
.r_push_r_reg(r_push),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_10),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_13),
.s_axburst_eq1_reg_0(cmd_translator_0_n_13),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(s_ready_i_reg),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_22),
.sel_first_reg_0(ar_cmd_fsm_0_n_23),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.sel_first_reg_3(cmd_translator_0_n_8),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_0 (cmd_translator_0_n_11),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[2] (D),
.\wrap_second_len_r_reg[3] ({\wrap_cmd_0/wrap_second_len [3],\wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_cmd_0/wrap_second_len_r ,Q[0]}));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1 cmd_translator_0
(.CO(CO),
.D(ar_cmd_fsm_0_n_6),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(cmd_translator_0_n_9),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] ,\wrap_cmd_0/axaddr_offset_r }),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[1] (cmd_translator_0_n_10),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_10),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_13),
.\m_payload_i_reg[3] (\m_payload_i_reg[3]_0 ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[61] [18:0]),
.\m_payload_i_reg[47]_1 ({\m_payload_i_reg[47]_0 ,axaddr_offset}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_17),
.next_pending_r_reg(cmd_translator_0_n_1),
.next_pending_r_reg_0(cmd_translator_0_n_11),
.r_rlast(r_rlast),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_8),
.sel_first_reg_2(ar_cmd_fsm_0_n_18),
.sel_first_reg_3(ar_cmd_fsm_0_n_22),
.sel_first_reg_4(ar_cmd_fsm_0_n_23),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (cmd_translator_0_n_13),
.\state_reg[1] (state),
.\state_reg[1]_0 (ar_cmd_fsm_0_n_0),
.\state_reg[1]_rep (r_push),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_cmd_0/wrap_second_len_r ,Q}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_cmd_0/wrap_second_len [3],D,\wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_3,\wrap_second_len_r_reg[0] ,ar_cmd_fsm_0_n_4}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [19]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [29]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [30]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [20]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [21]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [22]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [23]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [24]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [25]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [26]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [27]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [28]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
\wrap_boundary_axaddr_r_reg[0] ,
E,
b_push,
m_axi_awvalid,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
in,
S,
aclk,
O,
si_rs_awvalid,
\m_payload_i_reg[47] ,
\m_payload_i_reg[61] ,
CO,
\m_payload_i_reg[46] ,
areset_d1,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
\cnt_read_reg[1]_rep__0_0 ,
\cnt_read_reg[0]_rep__0 ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[0] ;
output [0:0]E;
output b_push;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [15:0]in;
output [3:0]S;
input aclk;
input [3:0]O;
input si_rs_awvalid;
input \m_payload_i_reg[47] ;
input [30:0]\m_payload_i_reg[61] ;
input [0:0]CO;
input \m_payload_i_reg[46] ;
input areset_d1;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input \cnt_read_reg[1]_rep__0_0 ;
input \cnt_read_reg[0]_rep__0 ;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_10;
wire aw_cmd_fsm_0_n_14;
wire aw_cmd_fsm_0_n_15;
wire aw_cmd_fsm_0_n_3;
wire aw_cmd_fsm_0_n_5;
wire aw_cmd_fsm_0_n_6;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire [15:0]in;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [30:0]\m_payload_i_reg[61] ;
wire [6:0]\m_payload_i_reg[6] ;
wire sel_first;
wire sel_first__0;
wire sel_first_i;
wire si_rs_awvalid;
wire \wrap_boundary_axaddr_r_reg[0] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.E(aw_cmd_fsm_0_n_0),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axlen_cnt_reg[3] (cmd_translator_0_n_11),
.\axlen_cnt_reg[7] (aw_cmd_fsm_0_n_5),
.\axlen_cnt_reg[7]_0 (cmd_translator_0_n_9),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0_0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[39] (\m_payload_i_reg[61] [14]),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_6),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_10),
.s_axburst_eq1_reg_0(cmd_translator_0_n_10),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_3),
.sel_first_reg_0(aw_cmd_fsm_0_n_14),
.sel_first_reg_1(aw_cmd_fsm_0_n_15),
.sel_first_reg_2(cmd_translator_0_n_2),
.sel_first_reg_3(sel_first),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[0] (\wrap_boundary_axaddr_r_reg[0] ),
.wrap_next_pending(wrap_next_pending));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator cmd_translator_0
(.CO(CO),
.D(D),
.E(\wrap_boundary_axaddr_r_reg[0] ),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axlen_cnt_reg[0] (cmd_translator_0_n_9),
.\cnt_read_reg[1]_rep__0 (aw_cmd_fsm_0_n_3),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_6),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_10),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[61] [18:0]),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_11),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_14),
.sel_first_reg_2(aw_cmd_fsm_0_n_15),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (cmd_translator_0_n_10),
.\state_reg[0]_0 (aw_cmd_fsm_0_n_0),
.\state_reg[0]_1 (aw_cmd_fsm_0_n_5),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [19]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [29]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [30]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [20]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [21]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [22]),
.Q(in[7]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [23]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [24]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [25]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [26]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [27]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [28]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [15]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [16]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [17]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [18]),
.Q(in[3]),
.R(1'b0));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__0 ,
\state_reg[0] ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
shandshake,
aclk,
b_push,
m_axi_bvalid,
areset_d1,
si_rs_bready,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__0 ;
output \state_reg[0] ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input shandshake;
input aclk;
input b_push;
input m_axi_bvalid;
input areset_d1;
input si_rs_bready;
input [15:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
wire \state_reg[0] ;
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo bid_fifo_0
(.Q(bresp_cnt_reg__0),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_5),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_0 (cnt_read),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\state_reg[0] (\state_reg[0] ));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[0]),
.I1(bresp_cnt_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.bresp_push(bresp_push),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_5),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000EACECCCC))
\s_bresp_acc[0]_i_1
(.I0(m_axi_bresp[0]),
.I1(\s_bresp_acc_reg_n_0_[0] ),
.I2(\s_bresp_acc_reg_n_0_[1] ),
.I3(m_axi_bresp[1]),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EA))
\s_bresp_acc[1]_i_1
(.I0(\s_bresp_acc_reg_n_0_[1] ),
.I1(m_axi_bresp[1]),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
FDRE shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(1'b0));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first__0,
\axlen_cnt_reg[0] ,
\state_reg[0] ,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
O,
sel_first_reg_1,
sel_first_reg_2,
\m_payload_i_reg[47] ,
Q,
si_rs_awvalid,
\m_payload_i_reg[47]_0 ,
E,
CO,
\cnt_read_reg[1]_rep__0 ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\state_reg[0]_0 ,
\state_reg[0]_1 ,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first__0;
output \axlen_cnt_reg[0] ;
output \state_reg[0] ;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input [3:0]O;
input sel_first_reg_1;
input sel_first_reg_2;
input \m_payload_i_reg[47] ;
input [1:0]Q;
input si_rs_awvalid;
input [18:0]\m_payload_i_reg[47]_0 ;
input [0:0]E;
input [0:0]CO;
input \cnt_read_reg[1]_rep__0 ;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]\state_reg[0]_0 ;
input \state_reg[0]_1 ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[0] ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [18:0]\m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire \state_reg[0] ;
wire [0:0]\state_reg[0]_0 ;
wire \state_reg[0]_1 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd incr_cmd_0
(.CO(CO),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[46] ({\m_payload_i_reg[47]_0 [17:15],\m_payload_i_reg[47]_0 [13:12],\m_payload_i_reg[47]_0 [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0]_0 ),
.\state_reg[0]_0 (\state_reg[0]_1 ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[47]_0 [14]),
.I2(s_axburst_eq0),
.O(\state_reg[0] ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first__0),
.sel_first_reg_1(sel_first_reg_2),
.\state_reg[0] (\state_reg[0]_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_b2s_cmd_translator" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1
(incr_next_pending,
next_pending_r_reg,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first_reg_1,
Q,
\axlen_cnt_reg[1] ,
next_pending_r_reg_0,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
O,
sel_first_reg_3,
sel_first_reg_4,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[47]_0 ,
\state_reg[1] ,
si_rs_arvalid,
CO,
\state_reg[1]_rep ,
\m_payload_i_reg[44] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
m_valid_i_reg,
D,
\state_reg[1]_0 ,
\m_payload_i_reg[47]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
m_axi_arready);
output incr_next_pending;
output next_pending_r_reg;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first_reg_1;
output [0:0]Q;
output \axlen_cnt_reg[1] ;
output next_pending_r_reg_0;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input [3:0]O;
input sel_first_reg_3;
input sel_first_reg_4;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [18:0]\m_payload_i_reg[47]_0 ;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input [0:0]CO;
input \state_reg[1]_rep ;
input \m_payload_i_reg[44] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]m_valid_i_reg;
input [0:0]D;
input \state_reg[1]_0 ;
input [3:0]\m_payload_i_reg[47]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input m_axi_arready;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[1] ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[47] ;
wire [18:0]\m_payload_i_reg[47]_0 ;
wire [3:0]\m_payload_i_reg[47]_1 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2 incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[1]_0 (\axlen_cnt_reg[1] ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] ({\m_payload_i_reg[47]_0 [17:16],\m_payload_i_reg[47]_0 [13:12],\m_payload_i_reg[47]_0 [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_3),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_0 (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[47]_0 [14]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[47]_0 [14]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_1 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_0),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_4),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
\axlen_cnt_reg[0]_0 ,
S,
incr_next_pending,
aclk,
O,
sel_first_reg_0,
\m_payload_i_reg[47] ,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
E,
CO,
\cnt_read_reg[1]_rep__0 ,
\m_payload_i_reg[11] ,
\state_reg[0] ,
\state_reg[0]_0 );
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [3:0]S;
input incr_next_pending;
input aclk;
input [3:0]O;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [1:0]Q;
input si_rs_awvalid;
input [8:0]\m_payload_i_reg[46] ;
input [0:0]E;
input [0:0]CO;
input \cnt_read_reg[1]_rep__0 ;
input [7:0]\m_payload_i_reg[11] ;
input [0:0]\state_reg[0] ;
input \state_reg[0]_0 ;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1_n_0 ;
wire \axaddr_incr[4]_i_2_n_0 ;
wire \axaddr_incr[4]_i_3_n_0 ;
wire \axaddr_incr[4]_i_4_n_0 ;
wire \axaddr_incr[4]_i_5_n_0 ;
wire \axaddr_incr[8]_i_2_n_0 ;
wire \axaddr_incr[8]_i_3_n_0 ;
wire \axaddr_incr[8]_i_4_n_0 ;
wire \axaddr_incr[8]_i_5_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1_n_0 ;
wire \axaddr_incr_reg[4]_i_1_n_1 ;
wire \axaddr_incr_reg[4]_i_1_n_2 ;
wire \axaddr_incr_reg[4]_i_1_n_3 ;
wire \axaddr_incr_reg[4]_i_1_n_4 ;
wire \axaddr_incr_reg[4]_i_1_n_5 ;
wire \axaddr_incr_reg[4]_i_1_n_6 ;
wire \axaddr_incr_reg[4]_i_1_n_7 ;
wire \axaddr_incr_reg[8]_i_1_n_1 ;
wire \axaddr_incr_reg[8]_i_1_n_2 ;
wire \axaddr_incr_reg[8]_i_1_n_3 ;
wire \axaddr_incr_reg[8]_i_1_n_4 ;
wire \axaddr_incr_reg[8]_i_1_n_5 ;
wire \axaddr_incr_reg[8]_i_1_n_6 ;
wire \axaddr_incr_reg[8]_i_1_n_7 ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire [7:0]\m_payload_i_reg[11] ;
wire [8:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire [2:1]p_1_in;
wire sel_first_reg_0;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'hB))
\axaddr_incr[0]_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(\cnt_read_reg[1]_rep__0 ),
.O(\axaddr_incr[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h9AAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[46] [3]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[3]));
LUT4 #(
.INIT(16'h0A9A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[46] [2]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\m_payload_i_reg[46] [5]),
.I3(\m_payload_i_reg[46] [4]),
.O(S[2]));
LUT4 #(
.INIT(16'h009A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[46] [1]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[1]));
LUT4 #(
.INIT(16'h0009))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[46] [0]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2
(.I0(\m_payload_i_reg[11] [7]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3
(.I0(\m_payload_i_reg[11] [6]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4
(.I0(\m_payload_i_reg[11] [5]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5
(.I0(\m_payload_i_reg[11] [4]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1_n_0 ,\axaddr_incr_reg[4]_i_1_n_1 ,\axaddr_incr_reg[4]_i_1_n_2 ,\axaddr_incr_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1_n_4 ,\axaddr_incr_reg[4]_i_1_n_5 ,\axaddr_incr_reg[4]_i_1_n_6 ,\axaddr_incr_reg[4]_i_1_n_7 }),
.S({\axaddr_incr[4]_i_2_n_0 ,\axaddr_incr[4]_i_3_n_0 ,\axaddr_incr[4]_i_4_n_0 ,\axaddr_incr[4]_i_5_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[4]_i_1_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1
(.CI(\axaddr_incr_reg[4]_i_1_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1_n_1 ,\axaddr_incr_reg[8]_i_1_n_2 ,\axaddr_incr_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1_n_4 ,\axaddr_incr_reg[8]_i_1_n_5 ,\axaddr_incr_reg[8]_i_1_n_6 ,\axaddr_incr_reg[8]_i_1_n_7 }),
.S({\axaddr_incr[8]_i_2_n_0 ,\axaddr_incr[8]_i_3_n_0 ,\axaddr_incr[8]_i_4_n_0 ,\axaddr_incr[8]_i_5_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[0]_i_1_n_0 ),
.D(\axaddr_incr_reg[8]_i_1_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT6 #(
.INIT(64'h44444F4444444444))
\axlen_cnt[0]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[0] ),
.I1(\axlen_cnt_reg[0]_0 ),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(\m_payload_i_reg[46] [6]),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[46] [7]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(p_1_in[1]));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(p_1_in[2]));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[1]),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(p_1_in[2]),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[0]_0 ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[0]_0 ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[0]_0 ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[0]_0 ));
LUT5 #(
.INIT(32'h55545555))
next_pending_r_i_4__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[5] ),
.I4(next_pending_r_i_5_n_0),
.O(\axlen_cnt_reg[0]_0 ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_b2s_incr_cmd" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
Q,
\axlen_cnt_reg[1]_0 ,
S,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\m_payload_i_reg[47] ,
E,
CO,
\m_payload_i_reg[46] ,
\state_reg[1]_rep ,
\m_payload_i_reg[44] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
m_axi_arready,
\state_reg[1]_0 );
output incr_next_pending;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output [0:0]Q;
output \axlen_cnt_reg[1]_0 ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [0:0]CO;
input [7:0]\m_payload_i_reg[46] ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[44] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [0:0]D;
input \state_reg[1] ;
input m_axi_arready;
input [1:0]\state_reg[1]_0 ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2__0_n_0 ;
wire \axaddr_incr[4]_i_3__0_n_0 ;
wire \axaddr_incr[4]_i_4__0_n_0 ;
wire \axaddr_incr[4]_i_5__0_n_0 ;
wire \axaddr_incr[8]_i_2__0_n_0 ;
wire \axaddr_incr[8]_i_3__0_n_0 ;
wire \axaddr_incr[8]_i_4__0_n_0 ;
wire \axaddr_incr[8]_i_5__0_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_1 ;
wire \axaddr_incr_reg[4]_i_1__0_n_2 ;
wire \axaddr_incr_reg[4]_i_1__0_n_3 ;
wire \axaddr_incr_reg[4]_i_1__0_n_4 ;
wire \axaddr_incr_reg[4]_i_1__0_n_5 ;
wire \axaddr_incr_reg[4]_i_1__0_n_6 ;
wire \axaddr_incr_reg[4]_i_1__0_n_7 ;
wire \axaddr_incr_reg[8]_i_1__0_n_1 ;
wire \axaddr_incr_reg[8]_i_1__0_n_2 ;
wire \axaddr_incr_reg[8]_i_1__0_n_3 ;
wire \axaddr_incr_reg[8]_i_1__0_n_4 ;
wire \axaddr_incr_reg[8]_i_1__0_n_5 ;
wire \axaddr_incr_reg[8]_i_1__0_n_6 ;
wire \axaddr_incr_reg[8]_i_1__0_n_7 ;
wire \axlen_cnt[1]_i_1__1_n_0 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2__0_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg[1]_0 ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire [7:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__1_n_0;
wire next_pending_r_i_4_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hAAAA6AAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[3]));
LUT6 #(
.INIT(64'h2A2A262A2A2A2A2A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[2]));
LUT6 #(
.INIT(64'h0A0A060A0A0A0A0A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[1]));
LUT6 #(
.INIT(64'h0202010202020202))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2__0
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3__0
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4__0
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5__0
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1__0
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1__0_n_0 ,\axaddr_incr_reg[4]_i_1__0_n_1 ,\axaddr_incr_reg[4]_i_1__0_n_2 ,\axaddr_incr_reg[4]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1__0_n_4 ,\axaddr_incr_reg[4]_i_1__0_n_5 ,\axaddr_incr_reg[4]_i_1__0_n_6 ,\axaddr_incr_reg[4]_i_1__0_n_7 }),
.S({\axaddr_incr[4]_i_2__0_n_0 ,\axaddr_incr[4]_i_3__0_n_0 ,\axaddr_incr[4]_i_4__0_n_0 ,\axaddr_incr[4]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1__0
(.CI(\axaddr_incr_reg[4]_i_1__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1__0_n_1 ,\axaddr_incr_reg[8]_i_1__0_n_2 ,\axaddr_incr_reg[8]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1__0_n_4 ,\axaddr_incr_reg[8]_i_1__0_n_5 ,\axaddr_incr_reg[8]_i_1__0_n_6 ,\axaddr_incr_reg[8]_i_1__0_n_7 }),
.S({\axaddr_incr[8]_i_2__0_n_0 ,\axaddr_incr[8]_i_3__0_n_0 ,\axaddr_incr[8]_i_4__0_n_0 ,\axaddr_incr[8]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[46] [6]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[1]_0 ),
.O(\axlen_cnt[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[46] [7]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg[1]_0 ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[1]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h55545555))
\axlen_cnt[3]_i_3__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(next_pending_r_i_4_n_0),
.O(\axlen_cnt_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(Q),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hA6))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(Q),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D),
.Q(Q),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[1] ));
LUT5 #(
.INIT(32'hFFFF505C))
next_pending_r_i_1__2
(.I0(next_pending_r_i_2__1_n_0),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(E),
.I4(\m_payload_i_reg[44] ),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_2__1
(.I0(next_pending_r_i_4_n_0),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.O(next_pending_r_i_2__1_n_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_4
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_4_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[46] ,
r_push,
aclk,
r_rlast,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input r_push;
input aclk;
input r_rlast;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_3;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_1;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_push),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[1]_rep__3_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[2]_rep__0_0 (transaction_fifo_0_n_1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(m_valid_i_reg),
.out(out),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_3));
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__3 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (m_valid_i_reg),
.in(trans_in),
.m_valid_i_reg(transaction_fifo_0_n_1),
.r_push_r(r_push_r),
.s_ready_i_reg(rd_data_fifo_0_n_0),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm
(\axlen_cnt_reg[7] ,
Q,
D,
\axaddr_offset_r_reg[0] ,
\axlen_cnt_reg[0] ,
\wrap_second_len_r_reg[3] ,
E,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
s_axburst_eq1_reg,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axlen_cnt_reg[3] ,
\axaddr_incr_reg[11] ,
m_axi_arvalid,
m_valid_i0,
\m_payload_i_reg[0]_1 ,
sel_first_reg,
sel_first_reg_0,
m_axi_arready,
si_rs_arvalid,
\axlen_cnt_reg[6] ,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\cnt_read_reg[1]_rep__0 ,
s_axburst_eq1_reg_0,
\m_payload_i_reg[44] ,
\axlen_cnt_reg[0]_0 ,
\wrap_second_len_r_reg[2] ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47] ,
\m_payload_i_reg[35]_0 ,
\axaddr_offset_r_reg[0]_0 ,
\m_payload_i_reg[3] ,
incr_next_pending,
\m_payload_i_reg[44]_0 ,
\state_reg[0]_0 ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
sel_first_reg_2,
s_axi_arvalid,
s_ready_i_reg,
sel_first_reg_3,
aclk);
output \axlen_cnt_reg[7] ;
output [1:0]Q;
output [1:0]D;
output [0:0]\axaddr_offset_r_reg[0] ;
output [0:0]\axlen_cnt_reg[0] ;
output [1:0]\wrap_second_len_r_reg[3] ;
output [0:0]E;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output s_axburst_eq1_reg;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]\axlen_cnt_reg[3] ;
output \axaddr_incr_reg[11] ;
output m_axi_arvalid;
output m_valid_i0;
output [0:0]\m_payload_i_reg[0]_1 ;
output sel_first_reg;
output sel_first_reg_0;
input m_axi_arready;
input si_rs_arvalid;
input \axlen_cnt_reg[6] ;
input [1:0]\wrap_second_len_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3] ;
input \cnt_read_reg[1]_rep__0 ;
input s_axburst_eq1_reg_0;
input [1:0]\m_payload_i_reg[44] ;
input [0:0]\axlen_cnt_reg[0]_0 ;
input [1:0]\wrap_second_len_r_reg[2] ;
input \m_payload_i_reg[35] ;
input [1:0]\m_payload_i_reg[47] ;
input \m_payload_i_reg[35]_0 ;
input [0:0]\axaddr_offset_r_reg[0]_0 ;
input \m_payload_i_reg[3] ;
input incr_next_pending;
input \m_payload_i_reg[44]_0 ;
input \state_reg[0]_0 ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input sel_first_reg_2;
input s_axi_arvalid;
input s_ready_i_reg;
input sel_first_reg_3;
input aclk;
wire [1:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [0:0]\axaddr_offset_r_reg[0] ;
wire [0:0]\axaddr_offset_r_reg[0]_0 ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axlen_cnt_reg[0] ;
wire [0:0]\axlen_cnt_reg[0]_0 ;
wire [0:0]\axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [1:0]\m_payload_i_reg[44] ;
wire \m_payload_i_reg[44]_0 ;
wire [1:0]\m_payload_i_reg[47] ;
wire m_valid_i0;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire \state_reg[0]_0 ;
wire \wrap_cnt_r[3]_i_2__0_n_0 ;
wire wrap_next_pending;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[3] ;
wire [1:0]\wrap_second_len_r_reg[3]_0 ;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hAEAA))
\axaddr_incr[0]_i_1__0
(.I0(sel_first_reg_2),
.I1(\m_payload_i_reg[0]_0 ),
.I2(\m_payload_i_reg[0] ),
.I3(m_axi_arready),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r_reg[0]_0 ),
.I1(\m_payload_i_reg[44] [1]),
.I2(Q[0]),
.I3(si_rs_arvalid),
.I4(Q[1]),
.I5(\m_payload_i_reg[3] ),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1
(.I0(Q[1]),
.I1(si_rs_arvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[44] [1]),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\axlen_cnt_reg[6] ),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0E02))
\axlen_cnt[3]_i_1
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0]_0 ),
.I2(\m_payload_i_reg[0] ),
.I3(m_axi_arready),
.O(\axlen_cnt_reg[3] ));
LUT5 #(
.INIT(32'h00002320))
\axlen_cnt[7]_i_1
(.I0(m_axi_arready),
.I1(Q[1]),
.I2(Q[0]),
.I3(si_rs_arvalid),
.I4(\axlen_cnt_reg[6] ),
.O(\axlen_cnt_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[31]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(m_valid_i0));
LUT5 #(
.INIT(32'hFFABEEAA))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[44]_0 ),
.I1(r_push_r_reg),
.I2(E),
.I3(\state_reg[0]_0 ),
.I4(next_pending_r_reg),
.O(wrap_next_pending));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h20))
r_push_r_i_1
(.I0(m_axi_arready),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[44] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[44] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFCFFFFFCCCCCCEE))
sel_first_i_1__0
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0] ),
.I4(\m_payload_i_reg[0]_0 ),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'h000033333FFF2222))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(s_axburst_eq1_reg_0),
.I3(m_axi_arready),
.I4(Q[0]),
.I5(Q[1]),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h0FC00040))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.I4(\cnt_read_reg[1]_rep__0 ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE \state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE \state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE \state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE \state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT6 #(
.INIT(64'h5575AA8A5545AA8A))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(\axaddr_offset_r_reg[0] ),
.O(D[0]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[2] [0]),
.I2(\wrap_cnt_r[3]_i_2__0_n_0 ),
.I3(\wrap_second_len_r_reg[2] [1]),
.O(D[1]));
LUT6 #(
.INIT(64'hDD11DD11DD11DDF1))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\m_payload_i_reg[35] ),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\m_payload_i_reg[47] [0]),
.I5(\m_payload_i_reg[47] [1]),
.O(\wrap_cnt_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAABAAA8A))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(\axaddr_offset_r_reg[0] ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hFFFFF4FF44444444))
\wrap_second_len_r[3]_i_1__0
(.I0(E),
.I1(\wrap_second_len_r_reg[3]_0 [1]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[47] [0]),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_second_len_r_reg[3] [1]));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__0_0 ,
\state_reg[0] ,
SR,
bresp_push,
bvalid_i_reg,
out,
b_push,
shandshake_r,
areset_d1,
Q,
mhandshake_r,
si_rs_bready,
si_rs_bvalid,
\cnt_read_reg[1]_0 ,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output \state_reg[0] ;
output [0:0]SR;
output bresp_push;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input [7:0]Q;
input mhandshake_r;
input si_rs_bready;
input si_rs_bvalid;
input [1:0]\cnt_read_reg[1]_0 ;
input [15:0]in;
input aclk;
wire [7:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire [1:1]cnt_read;
wire \cnt_read[0]_i_1_n_0 ;
wire [1:0]cnt_read_0;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire [1:0]\cnt_read_reg[1]_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [15:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire \state_reg[0] ;
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT2 #(
.INIT(4'hE))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(bresp_push),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT4 #(
.INIT(16'h002A))
bvalid_i_i_1
(.I0(bvalid_i_i_2_n_0),
.I1(si_rs_bready),
.I2(si_rs_bvalid),
.I3(areset_d1),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_0 [1]),
.I4(\cnt_read_reg[1]_0 [0]),
.I5(si_rs_bvalid),
.O(bvalid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(cnt_read));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1_n_0 ),
.Q(cnt_read_0[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(cnt_read),
.Q(cnt_read_0[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(cnt_read),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(cnt_read),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000082))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.I1(\memory_reg[3][1]_srl4_n_0 ),
.I2(Q[1]),
.I3(Q[7]),
.I4(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I5(\memory_reg[3][0]_srl4_i_4_n_0 ),
.O(bresp_push));
LUT5 #(
.INIT(32'h04000004))
\memory_reg[3][0]_srl4_i_2__0
(.I0(Q[5]),
.I1(mhandshake_r),
.I2(Q[4]),
.I3(\memory_reg[3][3]_srl4_n_0 ),
.I4(Q[3]),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT5 #(
.INIT(32'hFFAEAEAE))
\memory_reg[3][0]_srl4_i_3
(.I0(Q[6]),
.I1(\memory_reg[3][0]_srl4_n_0 ),
.I2(Q[0]),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.I4(\cnt_read_reg[0]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT4 #(
.INIT(16'h2FF2))
\memory_reg[3][0]_srl4_i_4
(.I0(Q[0]),
.I1(\memory_reg[3][0]_srl4_n_0 ),
.I2(\memory_reg[3][2]_srl4_n_0 ),
.I3(Q[2]),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read_0[0]),
.A1(cnt_read_0[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(out[1]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT2 #(
.INIT(4'h2))
\state[0]_i_2
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.O(\state_reg[0] ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_b2s_simple_fifo" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0
(Q,
mhandshake,
m_axi_bready,
\skid_buffer_reg[1] ,
bresp_push,
shandshake_r,
m_axi_bvalid,
mhandshake_r,
in,
aclk,
areset_d1);
output [1:0]Q;
output mhandshake;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input bresp_push;
input shandshake_r;
input m_axi_bvalid;
input mhandshake_r;
input [1:0]in;
input aclk;
input areset_d1;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire bresp_push;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(Q[0]),
.I1(bresp_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1__0
(.I0(Q[0]),
.I1(bresp_push),
.I2(shandshake_r),
.I3(Q[1]),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE \cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE \cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(bresp_push),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(bresp_push),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_b2s_simple_fifo" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1
(\cnt_read_reg[1]_rep__3_0 ,
m_valid_i_reg,
m_axi_rready,
\state_reg[1]_rep ,
out,
si_rs_rready,
m_axi_rvalid,
\cnt_read_reg[2]_rep__0_0 ,
in,
aclk,
areset_d1);
output \cnt_read_reg[1]_rep__3_0 ;
output m_valid_i_reg;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input si_rs_rready;
input m_axi_rvalid;
input \cnt_read_reg[2]_rep__0_0 ;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[3]_i_2_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep__3_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep__3_0 ;
wire \cnt_read_reg[1]_rep__3_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_n_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_n_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__3_0 ),
.I2(\cnt_read[3]_i_2_n_0 ),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__3_0 ),
.I2(\cnt_read[3]_i_2_n_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFE7F0180))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__3_0 ),
.I3(\cnt_read[3]_i_2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFB20000004))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read[3]_i_2_n_0 ),
.I2(\cnt_read_reg[1]_rep__3_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[3]_rep__2_n_0 ),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h08808880FFFFFFFF))
\cnt_read[3]_i_2
(.I0(\cnt_read_reg[4]_rep__2_n_0 ),
.I1(\cnt_read_reg[3]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__3_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.I5(m_axi_rvalid),
.O(\cnt_read[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
\cnt_read[3]_i_3
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.O(\cnt_read_reg[1]_rep__3_0 ));
LUT5 #(
.INIT(32'h9AA69AAA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.I3(\cnt_read_reg[3]_rep__2_n_0 ),
.I4(\cnt_read[4]_i_3_n_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFF7F77))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[1]_rep__3_n_0 ),
.I1(\cnt_read_reg[0]_rep__3_n_0 ),
.I2(m_valid_i_reg),
.I3(si_rs_rready),
.I4(\cnt_read[3]_i_2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h00000400))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(\cnt_read[3]_i_2_n_0 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_3_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__3
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__3_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep__3
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__3_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_n_0 ),
.S(areset_d1));
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[4]_rep__2_n_0 ),
.I1(\cnt_read_reg[3]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
LUT6 #(
.INIT(64'hFFFFFFFF80000000))
m_valid_i_i_2
(.I0(\cnt_read_reg[3]_rep__2_n_0 ),
.I1(\cnt_read_reg[4]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__3_n_0 ),
.I3(\cnt_read_reg[0]_rep__3_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[2]_rep__0_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'h800AAAAAAAAAAAAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[0]_rep__3_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.I3(\cnt_read_reg[1]_rep__3_n_0 ),
.I4(\cnt_read_reg[3]_rep__2_n_0 ),
.I5(\cnt_read_reg[4]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__3_n_0 ),
.I3(\cnt_read_reg[3]_rep__2_n_0 ),
.I4(\cnt_read_reg[4]_rep__2_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_b2s_simple_fifo" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2
(\state_reg[1]_rep ,
m_valid_i_reg,
\skid_buffer_reg[46] ,
s_ready_i_reg,
r_push_r,
si_rs_rready,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[0]_rep__3 ,
in,
aclk,
areset_d1);
output \state_reg[1]_rep ;
output m_valid_i_reg;
output [12:0]\skid_buffer_reg[46] ;
input s_ready_i_reg;
input r_push_r;
input si_rs_rready;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[0]_rep__3 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__3 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h7E81))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(r_push_r),
.I2(s_ready_i_reg),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[1]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h7FFE8001))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFE80000001))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[2]_rep__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h9AA69AAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[3]_rep__0_n_0 ),
.I4(\cnt_read[4]_i_3__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h5DFFFFFF))
\cnt_read[4]_i_2__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[3]_rep__2 ),
.I3(r_push_r),
.I4(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'h00000010))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(r_push_r),
.I2(si_rs_rready),
.I3(\cnt_read_reg[3]_rep__2 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE \cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE \cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE \cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE \cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE \cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT5 #(
.INIT(32'h80000000))
m_valid_i_i_3
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__1_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBFEEAAAAAAAAAAAA))
\state[1]_i_3
(.I0(\cnt_read_reg[0]_rep__3 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__0_n_0 ),
.I3(\cnt_read_reg[2]_rep__0_n_0 ),
.I4(\cnt_read_reg[4]_rep__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm
(E,
Q,
sel_first_reg,
\wrap_boundary_axaddr_r_reg[0] ,
\axlen_cnt_reg[7] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
\m_payload_i_reg[0] ,
b_push,
m_axi_awvalid,
sel_first_reg_0,
sel_first_reg_1,
si_rs_awvalid,
\axlen_cnt_reg[7]_0 ,
\m_payload_i_reg[39] ,
\m_payload_i_reg[46] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axlen_cnt_reg[3] ,
areset_d1,
sel_first_reg_2,
\cnt_read_reg[1]_rep__0 ,
s_axburst_eq1_reg_0,
m_axi_awready,
\cnt_read_reg[1]_rep__0_0 ,
\cnt_read_reg[0]_rep__0 ,
sel_first_reg_3,
sel_first__0,
aclk);
output [0:0]E;
output [1:0]Q;
output sel_first_reg;
output [0:0]\wrap_boundary_axaddr_r_reg[0] ;
output \axlen_cnt_reg[7] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
output m_axi_awvalid;
output sel_first_reg_0;
output sel_first_reg_1;
input si_rs_awvalid;
input \axlen_cnt_reg[7]_0 ;
input [0:0]\m_payload_i_reg[39] ;
input \m_payload_i_reg[46] ;
input next_pending_r_reg;
input next_pending_r_reg_0;
input \axlen_cnt_reg[3] ;
input areset_d1;
input sel_first_reg_2;
input \cnt_read_reg[1]_rep__0 ;
input s_axburst_eq1_reg_0;
input m_axi_awready;
input \cnt_read_reg[1]_rep__0_0 ;
input \cnt_read_reg[0]_rep__0 ;
input sel_first_reg_3;
input sel_first__0;
input aclk;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire b_push;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[39] ;
wire \m_payload_i_reg[46] ;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [1:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_awvalid;
wire [0:0]\wrap_boundary_axaddr_r_reg[0] ;
wire wrap_next_pending;
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT4 #(
.INIT(16'h04FF))
\axlen_cnt[3]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(sel_first_reg),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT5 #(
.INIT(32'h000004FF))
\axlen_cnt[7]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(sel_first_reg),
.I4(\axlen_cnt_reg[7]_0 ),
.O(\axlen_cnt_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(Q[0]),
.I1(Q[1]),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'hA000A0A0A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(Q[0]),
.I1(m_axi_awready),
.I2(Q[1]),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__0_0 ),
.I5(s_axburst_eq1_reg_0),
.O(b_push));
LUT5 #(
.INIT(32'hB8BBB888))
next_pending_r_i_1
(.I0(\m_payload_i_reg[46] ),
.I1(\wrap_boundary_axaddr_r_reg[0] ),
.I2(next_pending_r_reg),
.I3(sel_first_reg),
.I4(\axlen_cnt_reg[7]_0 ),
.O(incr_next_pending));
LUT5 #(
.INIT(32'hB888B8BB))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(\wrap_boundary_axaddr_r_reg[0] ),
.I2(next_pending_r_reg_0),
.I3(sel_first_reg),
.I4(\axlen_cnt_reg[3] ),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'h0CAE0CFF00FF00FF))
next_pending_r_i_3
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(Q[1]),
.I4(m_axi_awready),
.I5(Q[0]),
.O(sel_first_reg));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[39] ),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[39] ),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFF04FF04FF04))
sel_first_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(areset_d1),
.I4(sel_first_reg),
.I5(sel_first_reg_2),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1__1
(.I0(sel_first_reg),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1__2
(.I0(sel_first_reg),
.I1(sel_first__0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_1));
LUT6 #(
.INIT(64'hF232FE32FE3EFE3E))
\state[0]_i_1
(.I0(si_rs_awvalid),
.I1(Q[0]),
.I2(Q[1]),
.I3(\cnt_read_reg[1]_rep__0 ),
.I4(s_axburst_eq1_reg_0),
.I5(m_axi_awready),
.O(next_state[0]));
LUT6 #(
.INIT(64'h20E0202000E00000))
\state[1]_i_1
(.I0(m_axi_awready),
.I1(Q[1]),
.I2(Q[0]),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__0_0 ),
.I5(s_axburst_eq1_reg_0),
.O(next_state[1]));
(* KEEP = "yes" *)
FDRE \state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE \state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.O(\wrap_boundary_axaddr_r_reg[0] ));
endmodule
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\cnt_read_reg[1]_rep__0 ,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
D,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input \cnt_read_reg[1]_rep__0 ;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [3:0]\axaddr_incr_reg[3] ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_3_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[11]_i_5_n_0 ;
wire \axaddr_wrap[11]_i_6_n_0 ;
wire \axaddr_wrap[11]_i_7_n_0 ;
wire \axaddr_wrap[11]_i_8_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_3_n_0 ;
wire \axaddr_wrap[7]_i_4_n_0 ;
wire \axaddr_wrap[7]_i_5_n_0 ;
wire \axaddr_wrap[7]_i_6_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_2_n_1 ;
wire \axaddr_wrap_reg[11]_i_2_n_2 ;
wire \axaddr_wrap_reg[11]_i_2_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \cnt_read_reg[1]_rep__0 ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire [0:0]\state_reg[0] ;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[0]_i_1
(.I0(\m_payload_i_reg[47] [0]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[0]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[10]_i_1
(.I0(\m_payload_i_reg[47] [10]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[10]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[11]_i_1
(.I0(\m_payload_i_reg[47] [11]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[11]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hBE))
\axaddr_wrap[11]_i_3
(.I0(\axaddr_wrap[11]_i_8_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_4
(.I0(axaddr_wrap[11]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5
(.I0(axaddr_wrap[10]),
.O(\axaddr_wrap[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6
(.I0(axaddr_wrap[9]),
.O(\axaddr_wrap[11]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7
(.I0(axaddr_wrap[8]),
.O(\axaddr_wrap[11]_i_7_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_8
(.I0(wrap_cnt_r[2]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(wrap_cnt_r[0]),
.O(\axaddr_wrap[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[1]_i_1
(.I0(\m_payload_i_reg[47] [1]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[1]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[2]_i_1
(.I0(\m_payload_i_reg[47] [2]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[2]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[3]_i_1
(.I0(\m_payload_i_reg[47] [3]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[3]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[4]_i_1
(.I0(\m_payload_i_reg[47] [4]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[4]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[5]_i_1
(.I0(\m_payload_i_reg[47] [5]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[5]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[6]_i_1
(.I0(\m_payload_i_reg[47] [6]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[6]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[7]_i_1
(.I0(\m_payload_i_reg[47] [7]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[7]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3
(.I0(axaddr_wrap[7]),
.O(\axaddr_wrap[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4
(.I0(axaddr_wrap[6]),
.O(\axaddr_wrap[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5
(.I0(axaddr_wrap[5]),
.O(\axaddr_wrap[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6
(.I0(axaddr_wrap[4]),
.O(\axaddr_wrap[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[8]_i_1
(.I0(\m_payload_i_reg[47] [8]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[8]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[9]_i_1
(.I0(\m_payload_i_reg[47] [9]),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(axaddr_wrap0[9]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_2
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_2_n_1 ,\axaddr_wrap_reg[11]_i_2_n_2 ,\axaddr_wrap_reg[11]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S({\axaddr_wrap[11]_i_4_n_0 ,\axaddr_wrap[11]_i_5_n_0 ,\axaddr_wrap[11]_i_6_n_0 ,\axaddr_wrap[11]_i_7_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S({\axaddr_wrap[7]_i_3_n_0 ,\axaddr_wrap[7]_i_4_n_0 ,\axaddr_wrap[7]_i_5_n_0 ,\axaddr_wrap[7]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFF555400005554))
\axlen_cnt[0]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [15]),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1__0
(.I0(\m_payload_i_reg[47] [16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAACCC3AAAACCC0))
\axlen_cnt[2]_i_1__0
(.I0(\m_payload_i_reg[47] [17]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(E),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_11_b2s_wrap_cmd" *)
module design_1_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_araddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_arvalid,
\state_reg[1]_rep ,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47]_0 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [3:0]\axaddr_incr_reg[3] ;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]\m_payload_i_reg[47]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_3__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[11]_i_5__0_n_0 ;
wire \axaddr_wrap[11]_i_6__0_n_0 ;
wire \axaddr_wrap[11]_i_7__0_n_0 ;
wire \axaddr_wrap[11]_i_8__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_3__0_n_0 ;
wire \axaddr_wrap[7]_i_4__0_n_0 ;
wire \axaddr_wrap[7]_i_5__0_n_0 ;
wire \axaddr_wrap[7]_i_6__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [3:0]\m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_arvalid;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1_n_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[47]_0 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[47]_0 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[47]_0 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[47]_0 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'hF6))
\axaddr_wrap[11]_i_3__0
(.I0(\wrap_cnt_r_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axaddr_wrap[11]_i_8__0_n_0 ),
.O(\axaddr_wrap[11]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[11] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[10] ),
.O(\axaddr_wrap[11]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[9] ),
.O(\axaddr_wrap[11]_i_6__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7__0
(.I0(\axaddr_wrap_reg_n_0_[8] ),
.O(\axaddr_wrap[11]_i_7__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_8__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3__0
(.I0(\axaddr_wrap_reg_n_0_[7] ),
.O(\axaddr_wrap[7]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[6] ),
.O(\axaddr_wrap[7]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[5] ),
.O(\axaddr_wrap[7]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[4] ),
.O(\axaddr_wrap[7]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_2__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_2__0_n_1 ,\axaddr_wrap_reg[11]_i_2__0_n_2 ,\axaddr_wrap_reg[11]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_2__0_n_4 ,\axaddr_wrap_reg[11]_i_2__0_n_5 ,\axaddr_wrap_reg[11]_i_2__0_n_6 ,\axaddr_wrap_reg[11]_i_2__0_n_7 }),
.S({\axaddr_wrap[11]_i_4__0_n_0 ,\axaddr_wrap[11]_i_5__0_n_0 ,\axaddr_wrap[11]_i_6__0_n_0 ,\axaddr_wrap[11]_i_7__0_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap[7]_i_3__0_n_0 ,\axaddr_wrap[7]_i_4__0_n_0 ,\axaddr_wrap[7]_i_5__0_n_0 ,\axaddr_wrap[7]_i_6__0_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__0
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1__2
(.I0(\m_payload_i_reg[47] [16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAAACCC3AAAACCC0))
\axlen_cnt[2]_i_1__2
(.I0(\m_payload_i_reg[47] [17]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(E),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_araddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[2] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_araddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[5] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_araddr[9]));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__2
(.I0(\state_reg[1] [0]),
.I1(si_rs_arvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h13D320E0))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1_n_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module design_1_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
D,
wrap_second_len,
Q,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[11] ,
CO,
O,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
shandshake,
\wrap_cnt_r_reg[2] ,
\wrap_second_len_r_reg[2] ,
\wrap_cnt_r_reg[2]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
\wrap_second_len_r_reg[3] ,
next_pending_r_reg_0,
\axlen_cnt_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\m_axi_awaddr[10] ,
\m_axi_araddr[10] ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
m_valid_i0,
aresetn,
\cnt_read_reg[3]_rep__2 ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\state_reg[1] ,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_0 ,
\axaddr_offset_r_reg[3]_0 ,
s_axi_awvalid,
b_push,
si_rs_bvalid,
\wrap_second_len_r_reg[2]_0 ,
\state_reg[1]_rep ,
axaddr_offset_0,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_0 ,
\state_reg[0]_rep ,
sel_first,
sel_first_1,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
axaddr_incr_reg,
\axaddr_incr_reg[3]_0 ,
E,
\state_reg[1]_rep_1 );
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [3:0]D;
output [3:0]wrap_second_len;
output [53:0]Q;
output [53:0]\s_arid_r_reg[11] ;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11]_0 ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output shandshake;
output [0:0]\wrap_cnt_r_reg[2] ;
output [1:0]\wrap_second_len_r_reg[2] ;
output \wrap_cnt_r_reg[2]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output \wrap_second_len_r_reg[3] ;
output next_pending_r_reg_0;
output \axlen_cnt_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \m_axi_awaddr[10] ;
output \m_axi_araddr[10] ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input m_valid_i0;
input aresetn;
input \cnt_read_reg[3]_rep__2 ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[1] ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1]_0 ;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input s_axi_awvalid;
input b_push;
input si_rs_bvalid;
input [2:0]\wrap_second_len_r_reg[2]_0 ;
input \state_reg[1]_rep ;
input [0:0]axaddr_offset_0;
input [2:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_0 ;
input \state_reg[0]_rep ;
input sel_first;
input sel_first_1;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [3:0]axaddr_incr_reg;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]E;
input [0:0]\state_reg[1]_rep_1 ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [53:0]Q;
wire [3:0]S;
wire aclk;
wire ar_pipe_n_2;
wire aresetn;
wire aw_pipe_n_1;
wire aw_pipe_n_92;
wire [3:0]axaddr_incr_reg;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire [3:0]axaddr_offset;
wire [0:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [2:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[3]_rep__2 ;
wire [33:0]\cnt_read_reg[4] ;
wire \m_axi_araddr[10] ;
wire \m_axi_awaddr[10] ;
wire [3:0]\m_payload_i_reg[3] ;
wire m_valid_i0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [53:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire sel_first;
wire sel_first_1;
wire shandshake;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [0:0]\state_reg[1]_rep_1 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire [0:0]\wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[2]_0 ;
wire [3:0]wrap_second_len;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [2:0]\wrap_second_len_r_reg[2]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice ar_pipe
(.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[0]_0 (aw_pipe_n_92),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11]_0 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7]_0 ),
.axaddr_offset_0(axaddr_offset_0),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[3] [1]),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\axaddr_offset_r_reg[3] [0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_axi_araddr[10] (\m_axi_araddr[10] ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i0(m_valid_i0),
.m_valid_i_reg_0(ar_pipe_n_2),
.next_pending_r_reg(next_pending_r_reg_0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.sel_first_1(sel_first_1),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_1 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2] ),
.\wrap_cnt_r_reg[2]_0 (\wrap_cnt_r_reg[2]_0 ),
.\wrap_second_len_r_reg[2] (\wrap_second_len_r_reg[2] ),
.\wrap_second_len_r_reg[2]_0 (\wrap_second_len_r_reg[2]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ));
design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0 aw_pipe
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (aw_pipe_n_92),
.\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
.axaddr_offset({axaddr_offset[2],axaddr_offset[0]}),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[3] (axaddr_offset[3]),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.\m_axi_awaddr[10] (\m_axi_awaddr[10] ),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(aw_pipe_n_1),
.sel_first(sel_first),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_0 (\state_reg[1]_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.wrap_second_len({wrap_second_len[3:2],wrap_second_len[0]}),
.\wrap_second_len_r_reg[1] (wrap_second_len[1]),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ));
design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1 b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.shandshake(shandshake),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.\cnt_read_reg[3]_rep__2 (\cnt_read_reg[3]_rep__2 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11] ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
\wrap_cnt_r_reg[2] ,
\wrap_second_len_r_reg[2] ,
\wrap_cnt_r_reg[2]_0 ,
\axaddr_offset_r_reg[2] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
\wrap_second_len_r_reg[3] ,
next_pending_r_reg,
\axlen_cnt_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\m_axi_araddr[10] ,
\aresetn_d_reg[0] ,
aclk,
m_valid_i0,
\aresetn_d_reg[0]_0 ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[2]_0 ,
\state_reg[1]_rep ,
axaddr_offset_0,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\state_reg[0]_rep ,
sel_first_1,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\axaddr_incr_reg[3]_0 ,
\state_reg[1]_rep_1 );
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [53:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11] ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [0:0]\wrap_cnt_r_reg[2] ;
output [1:0]\wrap_second_len_r_reg[2] ;
output \wrap_cnt_r_reg[2]_0 ;
output \axaddr_offset_r_reg[2] ;
output [1:0]\axaddr_offset_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output \wrap_second_len_r_reg[3] ;
output next_pending_r_reg;
output \axlen_cnt_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output \m_axi_araddr[10] ;
input \aresetn_d_reg[0] ;
input aclk;
input m_valid_i0;
input \aresetn_d_reg[0]_0 ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[2]_0 ;
input \state_reg[1]_rep ;
input [0:0]axaddr_offset_0;
input [2:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input \state_reg[0]_rep ;
input sel_first_1;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]\state_reg[1]_rep_1 ;
wire [53:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[0]_i_10__0_n_0 ;
wire \axaddr_incr[0]_i_12__0_n_0 ;
wire \axaddr_incr[0]_i_13__0_n_0 ;
wire \axaddr_incr[0]_i_14__0_n_0 ;
wire \axaddr_incr[0]_i_3__0_n_0 ;
wire \axaddr_incr[0]_i_4__0_n_0 ;
wire \axaddr_incr[0]_i_5__0_n_0 ;
wire \axaddr_incr[0]_i_6__0_n_0 ;
wire \axaddr_incr[0]_i_7__0_n_0 ;
wire \axaddr_incr[0]_i_8__0_n_0 ;
wire \axaddr_incr[0]_i_9__0_n_0 ;
wire \axaddr_incr[4]_i_10__0_n_0 ;
wire \axaddr_incr[4]_i_7__0_n_0 ;
wire \axaddr_incr[4]_i_8__0_n_0 ;
wire \axaddr_incr[4]_i_9__0_n_0 ;
wire \axaddr_incr[8]_i_10__0_n_0 ;
wire \axaddr_incr[8]_i_7__0_n_0 ;
wire \axaddr_incr[8]_i_8__0_n_0 ;
wire \axaddr_incr[8]_i_9__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_1 ;
wire \axaddr_incr_reg[0]_i_11__0_n_2 ;
wire \axaddr_incr_reg[0]_i_11__0_n_3 ;
wire \axaddr_incr_reg[0]_i_11__0_n_4 ;
wire \axaddr_incr_reg[0]_i_11__0_n_5 ;
wire \axaddr_incr_reg[0]_i_11__0_n_6 ;
wire \axaddr_incr_reg[0]_i_11__0_n_7 ;
wire \axaddr_incr_reg[0]_i_2__0_n_1 ;
wire \axaddr_incr_reg[0]_i_2__0_n_2 ;
wire \axaddr_incr_reg[0]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_1 ;
wire \axaddr_incr_reg[4]_i_6__0_n_2 ;
wire \axaddr_incr_reg[4]_i_6__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_incr_reg[8]_i_6__0_n_1 ;
wire \axaddr_incr_reg[8]_i_6__0_n_2 ;
wire \axaddr_incr_reg[8]_i_6__0_n_3 ;
wire [0:0]axaddr_offset_0;
wire \axaddr_offset_r[1]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r[3]_i_2__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire [2:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire \m_axi_araddr[10] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[52]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire \m_payload_i_reg_n_0_[38] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first_1;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [0:0]\state_reg[1]_rep_1 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [0:0]\wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[2]_0 ;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [2:0]\wrap_second_len_r_reg[2]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [0]),
.I3(sel_first_1),
.I4(\axaddr_incr_reg[0]_i_11__0_n_7 ),
.O(\axaddr_incr[0]_i_10__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12__0
(.I0(Q[2]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[0]_i_12__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[0]_i_14__0_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_1),
.O(\axaddr_incr[0]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_1),
.O(\axaddr_incr[0]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_1),
.O(\axaddr_incr[0]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_1),
.O(\axaddr_incr[0]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [3]),
.I3(sel_first_1),
.I4(\axaddr_incr_reg[0]_i_11__0_n_4 ),
.O(\axaddr_incr[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [2]),
.I3(sel_first_1),
.I4(\axaddr_incr_reg[0]_i_11__0_n_5 ),
.O(\axaddr_incr[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [1]),
.I3(sel_first_1),
.I4(\axaddr_incr_reg[0]_i_11__0_n_6 ),
.O(\axaddr_incr[0]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10__0
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7__0
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8__0
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9__0
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10__0
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7__0
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8__0
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9__0
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9__0_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11__0_n_0 ,\axaddr_incr_reg[0]_i_11__0_n_1 ,\axaddr_incr_reg[0]_i_11__0_n_2 ,\axaddr_incr_reg[0]_i_11__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12__0_n_0 ,\axaddr_incr[0]_i_13__0_n_0 ,\axaddr_incr[0]_i_14__0_n_0 }),
.O({\axaddr_incr_reg[0]_i_11__0_n_4 ,\axaddr_incr_reg[0]_i_11__0_n_5 ,\axaddr_incr_reg[0]_i_11__0_n_6 ,\axaddr_incr_reg[0]_i_11__0_n_7 }),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[0]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[7]_0 ,\axaddr_incr_reg[0]_i_2__0_n_1 ,\axaddr_incr_reg[0]_i_2__0_n_2 ,\axaddr_incr_reg[0]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3__0_n_0 ,\axaddr_incr[0]_i_4__0_n_0 ,\axaddr_incr[0]_i_5__0_n_0 ,\axaddr_incr[0]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S({\axaddr_incr[0]_i_7__0_n_0 ,\axaddr_incr[0]_i_8__0_n_0 ,\axaddr_incr[0]_i_9__0_n_0 ,\axaddr_incr[0]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6__0
(.CI(\axaddr_incr_reg[0]_i_11__0_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6__0_n_0 ,\axaddr_incr_reg[4]_i_6__0_n_1 ,\axaddr_incr_reg[4]_i_6__0_n_2 ,\axaddr_incr_reg[4]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S({\axaddr_incr[4]_i_7__0_n_0 ,\axaddr_incr[4]_i_8__0_n_0 ,\axaddr_incr[4]_i_9__0_n_0 ,\axaddr_incr[4]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6__0
(.CI(\axaddr_incr_reg[4]_i_6__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6__0_n_1 ,\axaddr_incr_reg[8]_i_6__0_n_2 ,\axaddr_incr_reg[8]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] ),
.S({\axaddr_incr[8]_i_7__0_n_0 ,\axaddr_incr[8]_i_8__0_n_0 ,\axaddr_incr[8]_i_9__0_n_0 ,\axaddr_incr[8]_i_10__0_n_0 }));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.O(\axaddr_offset_r_reg[3] [0]));
LUT6 #(
.INIT(64'h1FDF00001FDFFFFF))
\axaddr_offset_r[1]_i_2
(.I0(\axaddr_offset_r[1]_i_3_n_0 ),
.I1(Q[35]),
.I2(Q[39]),
.I3(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1__0
(.I0(Q[41]),
.I1(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I2(\state_reg[1]_rep_0 ),
.I3(s_ready_i_reg_0),
.I4(\state_reg[0]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(\axaddr_offset_r_reg[3] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_4
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\m_payload_i_reg_n_0_[38] ),
.I1(sel_first_1),
.O(\m_axi_araddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(\m_payload_i[52]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(\m_payload_i_reg_n_0_[38] ),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[52]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
FDRE m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3__0
(.I0(\state_reg[1]_rep ),
.I1(Q[38]),
.I2(Q[41]),
.I3(Q[39]),
.I4(Q[40]),
.O(next_pending_r_reg));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[0]_rep ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[38]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[38]),
.I3(Q[35]),
.I4(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888082AAAAA082A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[38]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[39]),
.I4(Q[35]),
.I5(Q[38]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[40]),
.I1(Q[35]),
.I2(Q[41]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002AA02A0A2AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[41]),
.I2(Q[35]),
.I3(Q[36]),
.I4(Q[39]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[40]),
.I3(Q[35]),
.I4(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[35]),
.I3(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hA656AAAAAAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[2] [1]),
.I1(\wrap_second_len_r_reg[2]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(axaddr_offset_0),
.I4(\wrap_cnt_r_reg[2]_0 ),
.I5(\wrap_second_len_r_reg[2] [0]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFFFBAFFFFFFFF))
\wrap_second_len_r[0]_i_2__0
(.I0(\wrap_second_len_r_reg[3] ),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r_reg[3]_0 [2]),
.I3(\axaddr_offset_r_reg[2] ),
.I4(axaddr_offset_0),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_cnt_r_reg[2]_0 ));
LUT6 #(
.INIT(64'h0EF0FFFF0EF00000))
\wrap_second_len_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\axaddr_offset_r_reg[3] [1]),
.I2(axaddr_offset_0),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[2]_0 [1]),
.O(\wrap_second_len_r_reg[2] [0]));
LUT6 #(
.INIT(64'hD2D0FFFFD2D00000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.I1(axaddr_offset_0),
.I2(\axaddr_offset_r_reg[2] ),
.I3(\axaddr_offset_r_reg[3] [1]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[2]_0 [2]),
.O(\wrap_second_len_r_reg[2] [1]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *)
module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
D,
\wrap_second_len_r_reg[1] ,
Q,
\axaddr_incr_reg[11] ,
CO,
O,
wrap_second_len,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_awaddr[10] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
S,
\state_reg[1] ,
\wrap_second_len_r_reg[3] ,
\state_reg[1]_0 ,
\axaddr_offset_r_reg[3]_0 ,
s_axi_awvalid,
b_push,
sel_first,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
axaddr_incr_reg,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [3:0]D;
output \wrap_second_len_r_reg[1] ;
output [53:0]Q;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [2:0]wrap_second_len;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[3] ;
output [1:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_awaddr[10] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [3:0]S;
input \state_reg[1] ;
input [3:0]\wrap_second_len_r_reg[3] ;
input [1:0]\state_reg[1]_0 ;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input s_axi_awvalid;
input b_push;
input sel_first;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [3:0]axaddr_incr_reg;
input [0:0]E;
wire [3:0]C;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [53:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire \axaddr_incr[0]_i_10_n_0 ;
wire \axaddr_incr[0]_i_12_n_0 ;
wire \axaddr_incr[0]_i_13_n_0 ;
wire \axaddr_incr[0]_i_14_n_0 ;
wire \axaddr_incr[0]_i_3_n_0 ;
wire \axaddr_incr[0]_i_4_n_0 ;
wire \axaddr_incr[0]_i_5_n_0 ;
wire \axaddr_incr[0]_i_6_n_0 ;
wire \axaddr_incr[0]_i_7_n_0 ;
wire \axaddr_incr[0]_i_8_n_0 ;
wire \axaddr_incr[0]_i_9_n_0 ;
wire \axaddr_incr[4]_i_10_n_0 ;
wire \axaddr_incr[4]_i_7_n_0 ;
wire \axaddr_incr[4]_i_8_n_0 ;
wire \axaddr_incr[4]_i_9_n_0 ;
wire \axaddr_incr[8]_i_10_n_0 ;
wire \axaddr_incr[8]_i_7_n_0 ;
wire \axaddr_incr[8]_i_8_n_0 ;
wire \axaddr_incr[8]_i_9_n_0 ;
wire [3:0]axaddr_incr_reg;
wire \axaddr_incr_reg[0]_i_11_n_0 ;
wire \axaddr_incr_reg[0]_i_11_n_1 ;
wire \axaddr_incr_reg[0]_i_11_n_2 ;
wire \axaddr_incr_reg[0]_i_11_n_3 ;
wire \axaddr_incr_reg[0]_i_2_n_1 ;
wire \axaddr_incr_reg[0]_i_2_n_2 ;
wire \axaddr_incr_reg[0]_i_2_n_3 ;
wire [7:0]\axaddr_incr_reg[11] ;
wire \axaddr_incr_reg[4]_i_6_n_0 ;
wire \axaddr_incr_reg[4]_i_6_n_1 ;
wire \axaddr_incr_reg[4]_i_6_n_2 ;
wire \axaddr_incr_reg[4]_i_6_n_3 ;
wire \axaddr_incr_reg[8]_i_6_n_1 ;
wire \axaddr_incr_reg[8]_i_6_n_2 ;
wire \axaddr_incr_reg[8]_i_6_n_3 ;
wire [1:0]axaddr_offset;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[0]_i_3_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_4_n_0 ;
wire \axaddr_offset_r[3]_i_2_n_0 ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \m_axi_awaddr[10] ;
wire \m_payload_i_reg_n_0_[38] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first;
wire [61:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_2_n_0 ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire [2:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[0]_i_5_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[0]),
.I3(sel_first),
.I4(C[0]),
.O(\axaddr_incr[0]_i_10_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12
(.I0(Q[2]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[0]_i_12_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[0]_i_14_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[3]),
.I3(sel_first),
.I4(C[3]),
.O(\axaddr_incr[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[2]),
.I3(sel_first),
.I4(C[2]),
.O(\axaddr_incr[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[1]),
.I3(sel_first),
.I4(C[1]),
.O(\axaddr_incr[0]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11_n_0 ,\axaddr_incr_reg[0]_i_11_n_1 ,\axaddr_incr_reg[0]_i_11_n_2 ,\axaddr_incr_reg[0]_i_11_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12_n_0 ,\axaddr_incr[0]_i_13_n_0 ,\axaddr_incr[0]_i_14_n_0 }),
.O(C),
.S(S));
CARRY4 \axaddr_incr_reg[0]_i_2
(.CI(1'b0),
.CO({CO,\axaddr_incr_reg[0]_i_2_n_1 ,\axaddr_incr_reg[0]_i_2_n_2 ,\axaddr_incr_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3_n_0 ,\axaddr_incr[0]_i_4_n_0 ,\axaddr_incr[0]_i_5_n_0 ,\axaddr_incr[0]_i_6_n_0 }),
.O(O),
.S({\axaddr_incr[0]_i_7_n_0 ,\axaddr_incr[0]_i_8_n_0 ,\axaddr_incr[0]_i_9_n_0 ,\axaddr_incr[0]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6
(.CI(\axaddr_incr_reg[0]_i_11_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6_n_0 ,\axaddr_incr_reg[4]_i_6_n_1 ,\axaddr_incr_reg[4]_i_6_n_2 ,\axaddr_incr_reg[4]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [3:0]),
.S({\axaddr_incr[4]_i_7_n_0 ,\axaddr_incr[4]_i_8_n_0 ,\axaddr_incr[4]_i_9_n_0 ,\axaddr_incr[4]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6
(.CI(\axaddr_incr_reg[4]_i_6_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6_n_1 ,\axaddr_incr_reg[8]_i_6_n_2 ,\axaddr_incr_reg[8]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [7:4]),
.S({\axaddr_incr[8]_i_7_n_0 ,\axaddr_incr[8]_i_8_n_0 ,\axaddr_incr[8]_i_9_n_0 ,\axaddr_incr[8]_i_10_n_0 }));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'h00000700FFFFF7FF))
\axaddr_offset_r[0]_i_2
(.I0(Q[38]),
.I1(\axaddr_offset_r[0]_i_3_n_0 ),
.I2(\state_reg[1]_0 [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1]_0 [0]),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1
(.I0(Q[39]),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(\state_reg[1]_0 [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1]_0 [0]),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[35]),
.I3(Q[3]),
.I4(Q[36]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'h03FFF3FF55555555))
\axaddr_offset_r[2]_i_2
(.I0(\axaddr_offset_r_reg[3]_0 [2]),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\axaddr_offset_r[2]_i_4_n_0 ),
.I5(\state_reg[1] ),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_4
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1
(.I0(Q[41]),
.I1(\axaddr_offset_r[3]_i_2_n_0 ),
.I2(\state_reg[1]_0 [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1]_0 [0]),
.I5(\axaddr_offset_r_reg[3]_0 [3]),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_3
(.I0(Q[41]),
.I1(\state_reg[1]_0 [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_0 [1]),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\m_payload_i_reg_n_0_[38] ),
.I1(sel_first),
.O(\m_axi_awaddr[10] ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\m_payload_i_reg_n_0_[38] ),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2
(.I0(Q[40]),
.I1(Q[39]),
.I2(Q[41]),
.I3(Q[38]),
.O(next_pending_r_reg));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[38]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[38]),
.I3(Q[35]),
.I4(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A002A2AAAA02A2))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[39]),
.I4(Q[36]),
.I5(Q[38]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[39]),
.I4(Q[35]),
.I5(Q[38]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[40]),
.I1(Q[35]),
.I2(Q[41]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A0A2AA02AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[41]),
.I2(Q[35]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[40]),
.I3(Q[35]),
.I4(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[35]),
.I3(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hDDDDD8DDAAAAA8AA))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r[0]_i_3_n_0 ),
.I2(\state_reg[1]_0 [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1]_0 [0]),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(D[0]));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\wrap_cnt_r[3]_i_2_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(wrap_second_len[1]),
.I1(\wrap_cnt_r[3]_i_2_n_0 ),
.I2(\wrap_second_len_r_reg[1] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(wrap_second_len[2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_cnt_r[3]_i_2_n_0 ),
.I3(wrap_second_len[1]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hAAAABAAA))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r[0]_i_2_n_0 ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[3] ),
.O(\wrap_cnt_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000800FFFFF8FF))
\wrap_cnt_r[3]_i_3
(.I0(Q[38]),
.I1(\axaddr_offset_r[0]_i_3_n_0 ),
.I2(\state_reg[1]_0 [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1]_0 [0]),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000CCCCCACC))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3] [0]),
.I2(\state_reg[1]_0 [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1]_0 [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(wrap_second_len[0]));
LUT6 #(
.INIT(64'hFFFFFFFFF2FFFFFF))
\wrap_second_len_r[0]_i_2
(.I0(\axaddr_offset_r_reg[3]_0 [3]),
.I1(\state_reg[1] ),
.I2(\wrap_second_len_r[3]_i_2_n_0 ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\axaddr_offset_r[0]_i_2_n_0 ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000FFE200E2))
\wrap_second_len_r[0]_i_3
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[2]),
.I3(Q[35]),
.I4(\wrap_second_len_r[0]_i_4_n_0 ),
.I5(\wrap_second_len_r[0]_i_5_n_0 ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[0]_i_4
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT4 #(
.INIT(16'hFFDF))
\wrap_second_len_r[0]_i_5
(.I0(Q[38]),
.I1(\state_reg[1]_0 [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_0 [1]),
.O(\wrap_second_len_r[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h2EE22E222EE22EE2))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\state_reg[1] ),
.I2(\axaddr_offset_r[0]_i_2_n_0 ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[3] ),
.I5(\axaddr_offset_r[2]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[1] ));
LUT6 #(
.INIT(64'h08F3FFFF08F30000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[3] ),
.I1(\axaddr_offset_r[0]_i_2_n_0 ),
.I2(\axaddr_offset_r_reg[1] ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\state_reg[1] ),
.I5(\wrap_second_len_r_reg[3] [2]),
.O(wrap_second_len[1]));
LUT6 #(
.INIT(64'hBF00FFFFBF00BF00))
\wrap_second_len_r[3]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r[0]_i_2_n_0 ),
.I2(\axaddr_offset_r[2]_i_2_n_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1] ),
.I5(\wrap_second_len_r_reg[3] [3]),
.O(wrap_second_len[2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_4_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *)
module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
shandshake,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output shandshake;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire shandshake;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(\skid_buffer_reg[0]_0 ),
.I1(si_rs_bvalid),
.O(shandshake));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *)
module design_1_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[3]_rep__2 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[3]_rep__2 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[3]_rep__2 ;
wire [33:0]\cnt_read_reg[4] ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\skid_buffer_reg[0]_0 ),
.I3(\cnt_read_reg[3]_rep__2 ),
.O(m_valid_i_i_1__2_n_0));
FDRE m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[3]_rep__2 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module design_1_auto_pc_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
design_1_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %altmemphy v15.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// nios_altmemddr_0_phy_alt_mem_phy
// ============================================================
// Generated by altmemphy 15.1 [Altera, IP Toolbench 1.3.0 Build 185]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module nios_altmemddr_0_phy (
pll_ref_clk,
global_reset_n,
soft_reset_n,
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
ctl_doing_rd,
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
reset_request_n,
ctl_clk,
ctl_reset_n,
ctl_wlat,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_reset_n,
dbg_rd_data,
dbg_waitrequest,
aux_half_rate_clk,
aux_full_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqs_n);
input pll_ref_clk;
input global_reset_n;
input soft_reset_n;
input [1:0] ctl_dqs_burst;
input [1:0] ctl_wdata_valid;
input [31:0] ctl_wdata;
input [3:0] ctl_dm;
input [27:0] ctl_addr;
input [3:0] ctl_ba;
input [1:0] ctl_cas_n;
input [1:0] ctl_cke;
input [1:0] ctl_cs_n;
input [1:0] ctl_odt;
input [1:0] ctl_ras_n;
input [1:0] ctl_we_n;
input [1:0] ctl_rst_n;
input [0:0] ctl_mem_clk_disable;
input [1:0] ctl_doing_rd;
input ctl_cal_req;
input [0:0] ctl_cal_byte_lane_sel_n;
input dbg_clk;
input dbg_reset_n;
input [12:0] dbg_addr;
input dbg_wr;
input dbg_rd;
input dbg_cs;
input [31:0] dbg_wr_data;
output reset_request_n;
output ctl_clk;
output ctl_reset_n;
output [4:0] ctl_wlat;
output [31:0] ctl_rdata;
output [1:0] ctl_rdata_valid;
output [4:0] ctl_rlat;
output ctl_cal_success;
output ctl_cal_fail;
output ctl_cal_warning;
output [13:0] mem_addr;
output [1:0] mem_ba;
output mem_cas_n;
output [0:0] mem_cke;
output [0:0] mem_cs_n;
output [0:0] mem_dm;
output [0:0] mem_odt;
output mem_ras_n;
output mem_we_n;
output mem_reset_n;
output [31:0] dbg_rd_data;
output dbg_waitrequest;
output aux_half_rate_clk;
output aux_full_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [7:0] mem_dq;
inout [0:0] mem_dqs;
inout [0:0] mem_dqs_n;
nios_altmemddr_0_phy_alt_mem_phy nios_altmemddr_0_phy_alt_mem_phy_inst(
.pll_ref_clk(pll_ref_clk),
.global_reset_n(global_reset_n),
.soft_reset_n(soft_reset_n),
.ctl_dqs_burst(ctl_dqs_burst),
.ctl_wdata_valid(ctl_wdata_valid),
.ctl_wdata(ctl_wdata),
.ctl_dm(ctl_dm),
.ctl_addr(ctl_addr),
.ctl_ba(ctl_ba),
.ctl_cas_n(ctl_cas_n),
.ctl_cke(ctl_cke),
.ctl_cs_n(ctl_cs_n),
.ctl_odt(ctl_odt),
.ctl_ras_n(ctl_ras_n),
.ctl_we_n(ctl_we_n),
.ctl_rst_n(ctl_rst_n),
.ctl_mem_clk_disable(ctl_mem_clk_disable),
.ctl_doing_rd(ctl_doing_rd),
.ctl_cal_req(ctl_cal_req),
.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),
.dbg_clk(dbg_clk),
.dbg_reset_n(dbg_reset_n),
.dbg_addr(dbg_addr),
.dbg_wr(dbg_wr),
.dbg_rd(dbg_rd),
.dbg_cs(dbg_cs),
.dbg_wr_data(dbg_wr_data),
.reset_request_n(reset_request_n),
.ctl_clk(ctl_clk),
.ctl_reset_n(ctl_reset_n),
.ctl_wlat(ctl_wlat),
.ctl_rdata(ctl_rdata),
.ctl_rdata_valid(ctl_rdata_valid),
.ctl_rlat(ctl_rlat),
.ctl_cal_success(ctl_cal_success),
.ctl_cal_fail(ctl_cal_fail),
.ctl_cal_warning(ctl_cal_warning),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_cas_n(mem_cas_n),
.mem_cke(mem_cke),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_odt(mem_odt),
.mem_ras_n(mem_ras_n),
.mem_we_n(mem_we_n),
.mem_reset_n(mem_reset_n),
.dbg_rd_data(dbg_rd_data),
.dbg_waitrequest(dbg_waitrequest),
.aux_half_rate_clk(aux_half_rate_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqs_n(mem_dqs_n));
defparam
nios_altmemddr_0_phy_alt_mem_phy_inst.FAMILY = "Cyclone IV E",
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR2",
nios_altmemddr_0_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
nios_altmemddr_0_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
nios_altmemddr_0_phy_alt_mem_phy_inst.DWIDTH_RATIO = 4,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 8,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 14,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 2,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CS_PER_RANK = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 7692,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "7692 ps",
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 579,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 1024,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 80,
nios_altmemddr_0_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 180,
nios_altmemddr_0_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;
endmodule
// =========================================================
// altmemphy Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="ALTMEMPHY" version="15.1" build="198" iptb_version="1.3.0 Build 185" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="nios_altmemddr_0_phy_alt_mem_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="65.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="130.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Half" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(7692 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="JEDEC" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="JEDEC DDR2-533 512Mb x8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="14" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="45.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="450" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="105.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="37.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="7.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="180" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="4.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="180" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="clk_0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_reorder_data" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.35" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.35" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper;+nios_altmemddr_0_phy_alt_mem_phy_reconfig;+nios_altmemddr_0_phy_alt_mem_phy_pll;+nios_altmemddr_0_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/tmp/alt6993_8556806898035513691.dir/0001_iptb_gen/nios_altmemddr_0_phy_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="nios_altmemddr_0_phy_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for xfcp_switch
*/
module test_xfcp_switch_4;
// Parameters
parameter PORTS = 4;
parameter XFCP_ID_TYPE = 16'h0100;
parameter XFCP_ID_STR = "XFCP Switch";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg [PORTS*8-1:0] down_xfcp_in_tdata = 0;
reg [PORTS-1:0] down_xfcp_in_tvalid = 0;
reg [PORTS-1:0] down_xfcp_in_tlast = 0;
reg [PORTS-1:0] down_xfcp_in_tuser = 0;
reg [PORTS-1:0] down_xfcp_out_tready = 0;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire [PORTS-1:0] down_xfcp_in_tready;
wire [PORTS*8-1:0] down_xfcp_out_tdata;
wire [PORTS-1:0] down_xfcp_out_tvalid;
wire [PORTS-1:0] down_xfcp_out_tlast;
wire [PORTS-1:0] down_xfcp_out_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
up_xfcp_in_tdata,
up_xfcp_in_tvalid,
up_xfcp_in_tlast,
up_xfcp_in_tuser,
up_xfcp_out_tready,
down_xfcp_in_tdata,
down_xfcp_in_tvalid,
down_xfcp_in_tlast,
down_xfcp_in_tuser,
down_xfcp_out_tready
);
$to_myhdl(
up_xfcp_in_tready,
up_xfcp_out_tdata,
up_xfcp_out_tvalid,
up_xfcp_out_tlast,
up_xfcp_out_tuser,
down_xfcp_in_tready,
down_xfcp_out_tdata,
down_xfcp_out_tvalid,
down_xfcp_out_tlast,
down_xfcp_out_tuser
);
// dump file
$dumpfile("test_xfcp_switch_4.lxt");
$dumpvars(0, test_xfcp_switch_4);
end
xfcp_switch #(
.PORTS(PORTS),
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR)
)
UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.down_xfcp_in_tdata(down_xfcp_in_tdata),
.down_xfcp_in_tvalid(down_xfcp_in_tvalid),
.down_xfcp_in_tready(down_xfcp_in_tready),
.down_xfcp_in_tlast(down_xfcp_in_tlast),
.down_xfcp_in_tuser(down_xfcp_in_tuser),
.down_xfcp_out_tdata(down_xfcp_out_tdata),
.down_xfcp_out_tvalid(down_xfcp_out_tvalid),
.down_xfcp_out_tready(down_xfcp_out_tready),
.down_xfcp_out_tlast(down_xfcp_out_tlast)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_TB_V
`define SKY130_FD_SC_MS__XOR3_TB_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_TB_V
|
module imu_logger ( clk, // system clock, negedge
xclk, // half frequency (80 MHz nominal)
we, // write enable (lower 16 bits, high - next cycle)
wa, // write address(1)/data(0)
di, // 16-bit data in (32 multiplexed)
usec, // un-latched timestamp microseconds
sec, // un-latched timestamp seconds
ext_di,
ext_do,
ext_en,
ts_rcv_sec, // [31:0] timestamp seconds received over the sync line
ts_rcv_usec, // [19:0] timestamp microseconds received over the sync line
ts_stb, // strobe when received timestamp is valid - single negedge sclk cycle
data_out, // 16-bit data out to DMA1 (@negedge clk)
data_out_stb,// data out valid (@negedge clk)
sample_counter, // could be DMA latency, safe to use sample_counter-1
debug_state
);
input clk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
input we; // write enable (lower 16 bits, high - next cycle)
input wa; // write address(1)/data(0)
input [15:0] di; // 16-bit data in (32 multiplexed)
input [19:0] usec; // latched timestamp microseconds
input [31:0] sec; // latched timestamp seconds
input [11:0] ext_di; // external GPIO in
output [11:0] ext_do; // external GPIO out
output [11:0] ext_en; // external GPIO enable out
input [31:0] ts_rcv_sec; // [31:0] timestamp seconds received over the sync line
input [19:0] ts_rcv_usec; // [19:0] timestamp microseconds received over the sync line
input ts_stb; // strobe when received timestamp is valid - single negedge sclk cycle
output [15:0] data_out; // 16-bit data out to DMA1 (@negedge clk)
output data_out_stb;// data out valid (@negedge clk)
output [23:0] sample_counter; // could be DMA latency, safe to use sample_counter-1
output [31:0] debug_state;
wire ser_di; // gps serial data in
wire gps_pulse1sec;
wire mosi; // to IMU, bit 2 in J9
wire miso; // from IMU, bit 3 on J9
wire sda, sda_en, scl, scl_en;
reg [6:0] ctrl_addr=7'h0; // 0 - period, 1 - reserved, 2..31 - registers to log, >32 - gps parameters, >64 - odometer message
reg we_d; // only if wa was 0
reg we_imu;
reg we_gps;
reg we_period;
reg we_bit_duration;
reg we_message;
reg we_config;
reg we_config_imu; // bits 1:0, 2 - enable slot[1:0]
reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
// reg we_config_rst; // bit 16, 17 - enable - reset modules
// reg we_config_debug; // bits 21:18, 22 - enable
reg [15:0] di_d;
// reg di_d2;
reg [1:0] config_imu;
reg [3:0] config_gps;
reg [4:0] config_msg;
reg config_syn;
reg config_rst;
reg [3:0] config_debug;
reg [1:0] config_imu_mclk;
reg [3:0] config_gps_mclk;
reg [4:0] config_msg_mclk;
reg config_syn_mclk;
reg config_rst_mclk;
reg [3:0] config_debug_mclk;
reg [1:0] config_imu_pre;
reg [3:0] config_gps_pre;
reg [4:0] config_msg_pre;
reg config_syn_pre;
reg config_rst_pre;
reg [3:0] config_debug_pre;
reg [15:0] bitHalfPeriod;// serial gps speed - number of xclk pulses in half bit period
reg we_bitHalfPeriod;
reg [15:0] bitHalfPeriod_mclk;
reg enable_gps;
reg enable_msg;
reg enable_syn;
reg enable_timestamps;
wire message_trig;
reg ts_stb_rq;
reg [1:0] ext_ts_stb;
wire gps_ts_stb, ser_do,ser_do_stb;
wire [15:0] imu_data;
wire [15:0] nmea_data;
wire [15:0] extts_data;
wire [15:0] msg_data;
wire [15:0] timestamps_rdata; // multiplexed timestamp data
reg [2:0] gps_pulse1sec_d;
reg [1:0] gps_pulse1sec_denoise;
reg [7:0] gps_pulse1sec_denoise_count;
reg gps_pulse1sec_single;
// wire gps_ts; // single cycle @posedge xclk
wire [3:0] timestamp_request; // 0 - imu, 1 - gps, 2 - ext, 3 - msg
wire [3:0] timestamp_ackn;
wire [23:0] sample_counter;// could be DMA latency, safe to use sample_counter-1
wire [3:0] timestamp_request_long; //from sub-module ts request until reset by arbiter, to allow timestamp_ackn
wire [3:0] channel_ready; // 0 - imu, 1 - gps, 2 - ext, 3 - msg
wire [3:0] channel_next; // 0 - imu, 1 - gps, 2 - ext, 3 - msg
wire [1:0] channel; // currently logged channel number
wire [1:0] timestamp_sel; // selected word in timestamp (0..3)
wire ts_en; // log timestamp (when false - data)
wire mux_data_valid; // data valid from multiplexer (to xclk->clk converter fifo)
reg [15:0] mux_data_source;// data multiplexed from 1 of the 4 channels
reg mux_rdy_source; // data ready multiplexed from 1of the 4 channels (to fill rest with zeros)
reg [15:0] mux_data_final; // data multiplexed between timestamps and channel data (or 0 if ~ready)
wire [15:0] data_out; // 16-bit data out to DMA1 (@negedge clk)
wire data_out_stb;// data out valid (@posegedge clk)
wire rs232_wait_pause;// may be used as reset for decoder
wire rs232_start; // serial character start (single pulse)
wire nmea_sent_start; // serial character start (single pulse)
reg pre_message_trig;
// reg [1:0] debug_reg;
reg [7:0] dbg_cntr;
assign ext_en[11:0]= {5'b0,(config_imu[1:0]==2'h3)?1'b1:1'b0,1'b0,(config_imu[1:0]==2'h2)?1'b1:1'b0,1'b0,(config_imu[1:0]==2'h1)?1'b1:1'b0,(config_imu[1:0]!=2'h0)?{sda_en,scl_en}:2'h0};
assign ext_do[11:0]= {5'b0,(config_imu[1:0]==2'h3)?mosi:1'b0,1'b0,(config_imu[1:0]==2'h2)?mosi:1'b0,1'b0,(config_imu[1:0]==2'h1)?mosi:1'b0,(config_imu[1:0]!=2'h0)?{sda,scl}:2'h0};
assign miso= config_imu[1]?(config_imu[0]?ext_di[7] :ext_di[5]):(config_imu[0]?ext_di[3]:1'b0);
assign ser_di= config_gps[1]?(config_gps[0]?ext_di[6] :ext_di[4]):(config_gps[0]?ext_di[2]:1'b0);
assign gps_pulse1sec=config_gps[2]^(config_gps[1]?(config_gps[0]?ext_di[7] :ext_di[5]):(config_gps[0]?ext_di[3]:1'b0));
//sngl_wire
always @(config_msg[3:0] or ext_di[11:0]) begin
case (config_msg[3:0])
4'h0: pre_message_trig = ext_di[0];
4'h1: pre_message_trig = ext_di[1];
4'h2: pre_message_trig = ext_di[2];
4'h3: pre_message_trig = ext_di[3];
4'h4: pre_message_trig = ext_di[4];
4'h5: pre_message_trig = ext_di[5];
4'h6: pre_message_trig = ext_di[6];
4'h7: pre_message_trig = ext_di[7];
4'h8: pre_message_trig = ext_di[8]; // internal optocoupler, use invert 5'h18
4'h9: pre_message_trig = ext_di[9];
4'ha: pre_message_trig = ext_di[10];// external optocoupler, use invert 5'h1a
4'hb: pre_message_trig = ext_di[10];
default:pre_message_trig = 1'b0;
endcase
end
assign message_trig= config_msg[4]^pre_message_trig;
assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
// filter gps_pulse1sec
always @ (posedge xclk) begin
if (config_rst) gps_pulse1sec_d[2:0] <= 3'h0;
else gps_pulse1sec_d[2:0] <= {gps_pulse1sec_d[1:0], gps_pulse1sec};
if (config_rst) gps_pulse1sec_denoise[0] <= 1'b0;
else if (gps_pulse1sec_denoise_count[7:0]==8'h0) gps_pulse1sec_denoise[0] <= gps_pulse1sec_d[2];
if (gps_pulse1sec_d[2]==gps_pulse1sec_denoise[0]) gps_pulse1sec_denoise_count[7:0] <= 8'hff;
else gps_pulse1sec_denoise_count[7:0] <= gps_pulse1sec_denoise_count[7:0] - 1;
gps_pulse1sec_denoise[1] <= gps_pulse1sec_denoise[0];
gps_pulse1sec_single <= !gps_pulse1sec_denoise[1] && gps_pulse1sec_denoise[0];
end
// re-sync single pulse @ negedge sclk - ts_stb to @posedge xclk
always @ (posedge ext_ts_stb[1] or negedge clk) begin
if (ext_ts_stb[1]) ts_stb_rq <= 1'b0;
else if (config_rst_mclk) ts_stb_rq <= 1'b0;
else if (ts_stb) ts_stb_rq <= 1'b1;
end
always @ (posedge xclk) begin
ext_ts_stb[1:0] <= {ext_ts_stb[0] & ~ext_ts_stb[1],ts_stb_rq};
end
always @ (negedge clk) begin
if (we) di_d[15:0] <= di[15:0];
// di_d2 <=di_d[0];
// we_d <= we && !wa;
we_d <= we && !wa;
we_imu <= we && !wa && (ctrl_addr[6:5] == 2'h0);
we_gps <= we && !wa && (ctrl_addr[6:5] == 2'h1);
we_message <= we && !wa && (ctrl_addr[6:5] == 2'h2);
// we_timer[4:0] <= {we_timer[3:0], we && !wa && (ctrl_addr[5:0]==6'h0)} ;
we_period <= we && !wa && (ctrl_addr[6:0]==7'h0);
we_bit_duration <= we && !wa && (ctrl_addr[6:0]==7'h1);
we_bitHalfPeriod<= we && !wa && (ctrl_addr[6:0]==7'h2);
we_config <= we && !wa && (ctrl_addr[6:0]==7'h3);
we_config_imu <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[ 2];
we_config_gps <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[ 7];
we_config_msg <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[13];
we_config_syn <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[15];
// we_config_rst <= we_config && di[1];
if (we_config_imu) config_imu_mclk[1:0] <= di_d[ 1:0]; // bits 1:0, 2 - enable slot[1:0]
if (we_config_gps) config_gps_mclk[3:0] <= di_d[ 6:3]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
if (we_config_msg) config_msg_mclk[4:0] <= di_d[12:8]; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
if (we_config_syn) config_syn_mclk <= di_d[ 14]; // bit 14, 15 - enable
if (we_config && di[1]) config_rst_mclk <= di[0]; // bit 16, 17 - enable
if (we_config && di[6]) config_debug_mclk[3:0] <= di[5:2]; // bit 21:18, 22 - enable
if (we_bitHalfPeriod) bitHalfPeriod_mclk[15:0]<=di_d[15:0];
if (we && wa) ctrl_addr[6:5] <= di[6:5];
if (we && wa) ctrl_addr[4:0] <= di[4:0];
else if (we_d && (ctrl_addr[4:0]!=5'h1f)) ctrl_addr[4:0] <=ctrl_addr[4:0]+1; // no roll over,
end
always @ (posedge xclk) begin
bitHalfPeriod[15:0] <= bitHalfPeriod_mclk[15:0];
config_imu_pre[1:0] <= config_imu_mclk[1:0];
config_gps_pre[3:0] <= config_gps_mclk[3:0];
config_msg_pre[4:0] <= config_msg_mclk[4:0];
config_syn_pre <= config_syn_mclk;
config_rst_pre <= config_rst_mclk;
config_debug_pre[3:0] <= config_debug_mclk[3:0];
config_imu[1:0] <= config_imu_pre[1:0];
config_gps[3:0] <= config_gps_pre[3:0];
config_msg[4:0] <= config_msg_pre[4:0];
config_syn <= config_syn_pre;
config_rst <= config_rst_pre;
config_debug[3:0] <= config_debug_pre[3:0];
enable_gps <= (config_gps[1:0] != 2'h0) && !config_rst;
enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst;
enable_syn <= config_syn && !config_rst;
enable_timestamps <= !config_rst;
end
always @ (posedge xclk) begin
mux_data_source[15:0] <= channel[1]?(channel[0]?msg_data[15:0]:extts_data[15:0]):(channel[0]?nmea_data[15:0]:imu_data[15:0]);
mux_rdy_source <= channel[1]?(channel[0]?channel_ready[3]:channel_ready[2]):(channel[0]?channel_ready[1]:channel_ready[0]);
mux_data_final[15:0] <= ts_en? timestamps_rdata[15:0]:(mux_rdy_source?mux_data_source[15:0]:16'h0); // replace 16'h0 with some pattern to debug output
end
imu_spi i_imu_spi ( .sclk(clk), // system clock, negedge
.xclk(xclk), // half frequency (80 MHz nominal)
.we_ra(we_imu), // write enable for registers to log (@negedge clk)
.we_div(we_bit_duration),// write enable for clock dividing(@negedge clk)
.we_period(we_period),// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
.wa(ctrl_addr[4:0]), // write address for register (5 bits, @negedge clk)
.di(di[15:0]), // 16?-bit data in (di, not di_d)
.mosi(mosi), // to IMU, bit 2 in J9
.miso(miso), // from IMU, bit 3 on J9
.config_debug(config_debug[3:0]),
.sda(sda), // sda, shared with i2c, bit 1
.sda_en(sda_en), // enable sda output (when sda==0 and 1 cycle after sda 0->1)
.scl(scl), // scl, shared with i2c, bit 0
.scl_en(scl_en), // enable scl output (when scl==0 and 1 cycle after sda 0->1)
// .sngl_wire(sngl_wire), // single wire clock/data for the 103695 rev A
.ts(timestamp_request[0]), // timestamop request
.rdy(channel_ready[0]), // data ready
.rd_stb(channel_next[0]), // data read strobe (increment address)
.rdata(imu_data[15:0])); // data out (16 bits)
/*
logs events from odometer (can be software triggered), includes 56-byte message written to the buffer
So it is possible to assert trig input (will request timestamp), write message by software, then
de-assert the trig input - message with the timestamp will be logged
fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
*/
imu_message i_imu_message(.sclk(clk), // system clock, negedge
.xclk(xclk), // half frequency (80 MHz nominal)
.we(we_message), // write enable for registers to log (@negedge sclk), with lower data half
.wa(ctrl_addr[3:0]), // write address for register (4 bits, @negedge sclk)
.di(di[15:0]), // 16-bit data in multiplexed
.en(enable_msg), // enable module operation, if 0 - reset
.trig(message_trig), // leading edge - sample time, trailing set rdy
.ts(timestamp_request[3]), // timestamop request
.rdy(channel_ready[3]), // data ready
.rd_stb(channel_next[3]), // data read strobe (increment address)
.rdata(msg_data[15:0])); // data out (16 bits)
/* logs frame synchronization data from other camera (same as frame sync) */
// ts_stb (mclk) -> trig)
imu_exttime i_imu_exttime(.xclk(xclk), // half frequency (80 MHz nominal)
.en(enable_syn), // enable module operation, if 0 - reset
.trig(ext_ts_stb[1]), // external time stamp updated, single pulse @posedge xclk
.usec(ts_rcv_usec[19:0]), // microseconds from external timestamp (should not chnage after trig for 10 xclk)
.sec(ts_rcv_sec[31:0]), // seconds from external timestamp
.ts(timestamp_request[2]), // timestamop request
.rdy(channel_ready[2]), // data ready
.rd_stb(channel_next[2]), // data read strobe (increment address)
.rdata(extts_data[15:0])); // data out (16 bits)
imu_timestamps i_imu_timestamps (
.sclk(clk), // 160MHz, negedge
.xclk(xclk), // 80 MHz, posedge
.rst(!enable_timestamps), // reset (@posedge xclk)
.sec(sec[31:0]), // running seconds (@negedge sclk)
.usec(usec[19:0]), // running microseconds (@negedge sclk)
.ts_rq(timestamp_request_long[3:0]),// requests to create timestamps (4 channels), @posedge xclk
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused; // SuppressThisWarning Veditor UNUSED
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in
.ser_rst(!enable_gps), // reset (force re-sync)
.ts_stb(gps_ts_stb), // strobe timestamp (start of message) (reset bit counters in nmea decoder)
.wait_just_pause(rs232_wait_pause),// may be used as reset for decoder
.start(rs232_start), // serial character start (single pulse)
.ser_do(ser_do), // serial data out(@posedge xclk) LSB first!
.ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
// .debug(debug_state[4:0]),
.debug({debug_state_unused,debug_state[15:12]}),
.bit_dur_cntr(debug_state[31:16]),
.bit_cntr(debug_state[11:7])
);
// output [15:0] debug_state;
// reg [7:0] dbg_cntr;
// assign debug_state[15:12]=3'b0;
assign debug_state[6:0] = dbg_cntr [6:0];
always @ (posedge xclk) begin
if (!enable_gps) dbg_cntr[7:0] <= 8'h0;
// else if (ser_do_stb) dbg_cntr[7:0] <= dbg_cntr[7:0]+1;
else if (rs232_start) dbg_cntr[7:0] <= dbg_cntr[7:0]+1;
end
nmea_decoder i_nmea_decoder (.sclk(clk), // system clock, @negedge
.we(we_gps), // registers write enable (@negedge sclk)
.wa(ctrl_addr[4:0]), // registers write adderss
.wd(di_d[7:0]), // write data
.xclk(xclk), // 80MHz, posedge
.start(gps_ts_stb), // start of the serial message
.rs232_wait_pause(rs232_wait_pause),// may be used as reset for decoder
.start_char(rs232_start), // serial character start (single pulse)
.nmea_sent_start(nmea_sent_start), // serial character start (single pulse)
.ser_di(ser_do), // serial data in (LSB first)
.ser_stb(ser_do_stb),// serial data strobe, single-cycle, first cycle after ser_di valid
.rdy(channel_ready[1]), // encoded nmea data ready
.rd_stb(channel_next[1]), // encoded nmea data read strobe (increment address)
.rdata(nmea_data[15:0]), // encoded data (16 bits)
.ser_rst(!enable_gps), // reset (now only debug register)
// .debug(debug_state[31:8])
// .debug(debug_state[15:8])
.debug()
);
logger_arbiter i_logger_arbiter(.xclk(xclk), // 80 MHz, posedge
.rst(config_rst), // module reset
.ts_rq_in(timestamp_request[3:0]), // in requests for timestamp (single-cycle - just leading edge )
.ts_rq(timestamp_request_long[3:0]), // out request for timestamp, to timestmp module
.ts_grant(timestamp_ackn[3:0]), // granted ts requests from timestamping module
.rdy(channel_ready[3:0]), // channels ready (leading edge - became ready, trailing - no more data, use zero)
.nxt(channel_next[3:0]), // pulses to modules to output next word
.channel(channel[1:0]), // decoded channel number (2 bits)
.ts_sel(timestamp_sel[1:0]), // select timestamp word to be output (0..3)
.ts_en(ts_en), // 1 - use timestamp, 0 - channel data (or 16'h0 if !ready)
.dv(mux_data_valid), // output data valid (from registered mux - 2 stage - first selects data and ready, second ts/data/zero)
.sample_counter(sample_counter));// number of 64-byte samples logged
buf_xclk_mclk16 i_buf_xclk_mclk16(.xclk(xclk), // posedge
.mclk(clk), // posedge!
.rst(config_rst), // @posedge xclk
.din(mux_data_final[15:0]),
.din_stb(mux_data_valid),
.dout(data_out[15:0]),
.dout_stb(data_out_stb));
endmodule
module logger_arbiter(xclk, // 80 MHz, posedge
rst, // module reset
ts_rq_in, // in requests for timestamp (single-cycle - just leading edge )
ts_rq, // out request for timestamp, to timestmp module
ts_grant, // granted ts requests from timestamping module
rdy, // channels ready (leading edge - became ready, trailing - no more data, use zero)
nxt, // pulses to modules to output next word
channel, // decoded channel number (2 bits)
ts_sel, // select timestamp word to be output (0..3)
ts_en, // 1 - use timestamp, 0 - channel data (or 16'h0 if !ready)
dv, // output data valid (from registered mux - 2 stage - first selects data and ready, second ts/data/zero)
sample_counter);// number of 64-byte samples logged
input xclk; // half frequency (80 MHz nominal)
input rst; // reset module
input [ 3:0] ts_rq_in; // in requests for timestamp (sinlgle-cycle)
output [ 3:0] ts_rq; // out request for timestamp, to timestmp module
input [ 3:0] ts_grant; // granted ts requests from timestamping module
input [ 3:0] rdy; // channels ready (leading edge - became ready, trailing - no more data, use zero)
output [ 3:0] nxt; // pulses to modules to output next word
output [ 1:0] channel; // decoded channel number (2 bits)
output [ 1:0] ts_sel; // select timestamp word to be output (0..3)
output ts_en; // 1 - use timestamp, 0 - channel data (or 16'h0 if !ready)
output dv; // output data valid (from registered mux - 2 stage - first selects data and ready, second ts/data/zero)
output [23:0] sample_counter;// number of 64-byte samples logged
reg [3:0] ts_rq_in_d;
reg [3:0] ts_rq;
reg [3:0] ts_valid;
// reg [3:0] ts_rq_reset;
reg [3:0] channels_ready;// channels granted and ready
reg [3:1] chn1hot; // channels 1-hot - granted and ready, priority applied
reg rq_not_zero; // at least one channel is ready for processing (same time as chn1hot[3:0])
reg [1:0] channel;
///AF: reg start;
reg busy;
wire wstart;
reg ts_en;
reg [4:0] seq_cntr;
reg seq_cntr_last;
reg [1:0] ts_sel;
reg dv;
reg inc_sample_counter;
reg [23:0] sample_counter;// number of 64-byte samples logged
reg [ 3:0] nxt;
reg pre_nxt;
reg [ 3:0] chn_servicing; //1-hot channel being service
// reg [ 3:0] rdy_d;
wire [3:0] wts_rq;
assign wstart= !busy && rq_not_zero;
assign wts_rq[3:0]= ts_rq_in[3:0] & ~ts_rq_in_d[3:0] & (~rdy[3:0] | chn_servicing[3:0]);
always @ (posedge xclk) begin
ts_rq_in_d[3:0] <= ts_rq_in[3:0];
// rdy_d[3:0] <=rdy[3:0];
if (wstart) channel[1:0] <= {chn1hot[3] | chn1hot[2],chn1hot[3] | chn1hot[1]};
if (wstart) chn_servicing[3:0] <= {chn1hot[3:1], ~|chn1hot[3:1]};
else if (!busy) chn_servicing[3:0] <= 4'h0;
// if (rst) ts_rq[3:0] <= 4'h0;
// else ts_rq[3:0] <= ~ts_rq_reset[3:0] & ((ts_rq_in[3:0] & ~ts_rq_in_d[3:0]) | ts_rq[3:0]);
if (rst) ts_rq[3:0] <= 4'h0;
// else ts_rq[3:0] <= ~ts_grant & ( (ts_rq_in[3:0] & ~ts_rq_in_d[3:0] & (~rdy[3:0] | ~ts_valid[3:0])) | ts_rq[3:0]);
else ts_rq[3:0] <= ~ts_grant & ( wts_rq[3:0] | ts_rq[3:0]);
if (rst) ts_valid[3:0] <= 4'h0;
// else ts_valid[3:0] <= ~ts_rq_reset[3:0] &( ts_grant[3:0] | (ts_valid & ~(ts_rq_in[3:0] & ~ts_rq_in_d[3:0] & ~rdy[3:0])));
else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0]));
// if (rst) request[3:0] <= 4'h0;
// else request[3:0] <= ~ts_rq_reset[3:0] &( request[3:0] | (rdy[3:0] & ~rdy_d[3:0])));
// channels_ready[3:0] <= ts_grant[3:0] & rdy[3:0];
channels_ready[3:0] <= ts_valid[3:0] & rdy[3:0] & ~chn_servicing[3:0]; // ready should go down during servicing
rq_not_zero <= channels_ready[3:0] != 4'h0;
chn1hot[3:1] <= {channels_ready[3] & ~|channels_ready[2:0],
channels_ready[2] & ~|channels_ready[1:0],
channels_ready[1] & ~channels_ready[0]};
///AF: start <= wstart;
if ((seq_cntr[4:0]=='h1e) || rst) busy <= 1'b0;
else if (rq_not_zero) busy <= 1'b1;
// if (!busy) seq_cntr[4:0] <= 5'h1f;
if (!busy) seq_cntr[4:0] <= 5'h0;
else seq_cntr[4:0] <= seq_cntr[4:0] + 1;
seq_cntr_last <= (seq_cntr[4:0]=='h1e);
if (wstart) ts_en <=1'b1;
else if (seq_cntr[1:0]==2'h3) ts_en <=1'b0;
if (!ts_en) ts_sel[1:0] <= 2'h0;
else ts_sel[1:0] <= ts_sel[1:0] + 1;
if (!busy || (seq_cntr[4:0]=='h1d)) pre_nxt <= 1'b0;
else if (seq_cntr[4:0]=='h01) pre_nxt <= 1'b1;
/*
nxt [3:0] <= pre_nxt? { channel[1] & channel[0],
channel[1] & ~channel[0],
~channel[1] & channel[0],
~channel[1] & ~channel[0]}:4'h0;
*/
nxt [3:0] <= pre_nxt? chn_servicing[3:0]:4'h0;
/*
ts_rq_reset[3:0] <= start? { channel[1] & channel[0],
channel[1] & ~channel[0],
~channel[1] & channel[0],
~channel[1] & ~channel[0]}:4'h0;
*/
dv <= busy || seq_cntr_last;
inc_sample_counter <= seq_cntr_last;
if (rst) sample_counter[23:0] <= 24'h0;
else if (inc_sample_counter) sample_counter[23:0] <= sample_counter[23:0] +1;
end
endmodule
module buf_xclk_mclk16 (xclk, // posedge
mclk, // posedge
rst, // @posedge xclk
din,
din_stb,
dout,
dout_stb);
input xclk; // half frequency (80 MHz nominal)
input mclk; // system clock - frequency (160 MHz nominal)
input rst; // reset module
input [15:0] din;
input din_stb;
output [15:0] dout;
output dout_stb;
reg [1:0] wa;
reg [1:0] wa_mclk;
reg [1:0] wa_mclk_d;
reg rst_mclk;
reg [1:0] ra;
reg [1:0] ra_next;
reg inc_ra;
wire [15:0] pre_dout;
reg [15:0] dout;
reg dout_stb;
always @ (posedge xclk) begin
if (rst) wa[1:0] <= 2'h0;
else if (din_stb) wa[1:0] <={wa[0],~wa[1]};
end
always @ (posedge mclk) begin
wa_mclk[1:0] <= wa[1:0];
wa_mclk_d[1:0] <= wa_mclk[1:0];
rst_mclk<= rst;
if (rst_mclk) ra[1:0] <= 2'h0;
else ra[1:0] <= inc_ra?{ra[0],~ra[1]}:{ra[1],ra[0]};
if (rst_mclk) ra_next[1:0] <= 2'h1;
else ra_next[1:0] <= inc_ra?{~ra[1],~ra[0]}:{ra[0],~ra[1]};
inc_ra <= !rst && (ra[1:0]!=wa_mclk_d[1:0]) && (!inc_ra || (ra_next[1:0]!=wa_mclk_d[1:0]));
dout_stb <= inc_ra;
if (inc_ra) dout[15:0] <= pre_dout[15:0];
end
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(2))
i_fifo_4x16 (.D(din[15:0]),
.WE(din_stb),
.clk(xclk),
.AW(wa[1:0]),
.AR(ra[1:0]),
.QW(),
.QR(pre_dout[15:0]));
endmodule
module imu_spi ( sclk, // system clock, negedge
xclk, // half frequency (80 MHz nominal)
we_ra, // write enable for registers to log (@negedge clk)
we_div,// write enable for clock dividing(@negedge clk)
we_period,// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
wa, // write address for register (5 bits, @negedge clk)
di, // 16?-bit data in (di, not di_d)
mosi, // to IMU, bit 2 in J9
miso, // from IMU, bit 3 on J9
config_debug, // bit 0 - long sda_en
sda, // sda, shared with i2c, bit 1
sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1)
scl, // scl, shared with i2c, bit 0
scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1)
// sngl_wire, // single wire clock/data for the 103695 rev A
ts, // timestamop request
rdy, // data ready
rd_stb, // data read strobe (increment address)
rdata); // data out (16 bits)
input sclk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
input we_ra; // write enable for registers to log (@negedge sclk)
input we_div;// write enable for clock dividing(@negedge sclk)
input we_period;// write enable for IMU cycle period(@negedge clk)
input [4:0] wa; // write address for register (5 bits, @negedge sclk)
input [15:0] di; // 16-bit data in
output mosi; // to IMU, bit 2 in J9
input miso; // from IMU, bit 3 on J9
input [3:0] config_debug;
output sda; // sda, shared with i2c, bit 1
output sda_en; // enable sda output (when sda==0 and 1 cycle after sda 0->1)
output scl; // scl, shared with i2c, bit 0
output scl_en; // enable scl output (when scl==0 and 1 cycle after sda 0->1)
output ts; // timestamp request
output rdy; // encoded nmea data ready
input rd_stb; // encoded nmea data read strobe (increment address)
output [15:0] rdata; // encoded data (16 bits)
// output sngl_wire; // combined clock/data
reg [ 7:0] bit_duration_mclk=8'h0;
reg [ 7:0] bit_duration;
reg [ 7:0] bit_duration_cntr=8'h0;
reg bit_duration_zero; // just for simulation
reg [ 3:0] clk_en=4'h0;
reg [ 1:0] clk_div;
reg [ 4:0] imu_in_word= 5'b0; // number of IMU output word in a sample (0..31), 0..3 - timestamp
reg pre_imu_wr_buf,imu_wr_buf;
wire [15:0] imu_in_buf;
reg [4:0] reg_seq_number; // number of register in a sequence
wire [6:1] imu_reg_number; // register numer to read
reg [1:0] seq_state; // 0 - idle, 1 - prepare spi(4?), 2 - spi-comm(32*29), 3 - finish (2)
reg [9:0] seq_counter;
reg end_spi, end_prepare;
reg set_mosi_prepare, set_mosi_spi;
reg seq_counter_zero, pre_seq_counter_zero;
reg [15:0] mosi_reg;
wire mosi;
reg sda, sda_d;
wire sda_en;
reg scl, scl_d;
wire scl_en;
reg shift_miso;
reg [15:0] miso_reg;
reg last_bit; // last clk _/~ in spi word (but first one)
reg last_bit_ext=1'b0; // from last bit till buffer write
reg last_buf_wr;
reg [ 4:0] raddr;
reg rdy=1'b0;
reg imu_start;
reg ts; // delay imu_start by one cycle, so it will be aftre rdy is reset
reg [31:0] period; // 0 - disable, 1 - single, >1 - period in 50 ns steps
reg [15:0] di_d;
reg imu_enabled_mclk;
reg [1:0] imu_enabled=2'h0;
reg imu_run_mclk;
reg [1:0] imu_run;
reg imu_when_ready_mclk;
reg [1:0] imu_when_ready;
reg imu_run_confirmed;
reg imu_start_mclk;
reg [1:0] imu_start_grant;
reg imu_start_first;
reg imu_start_first_was;
reg [31:0] period_counter;
wire en;
reg [4:01] we_timer;
reg first_prepare;
reg [1:0] first_prepare_d;
wire config_long_sda_en;
wire config_late_clk;
reg [7:0] stall_dur_mclk;
reg [7:0] stall_dur;
reg stall; // stall between words to satisfy SPI stall time
reg [7:0] stall_cntr; // stall counter (in half sclk periods)
reg set_stall;
reg skip_stall; // first word after CS -\_
wire shift_mosi;
reg imu_ready_reset;
reg [6:0] imu_ready_denoise_count;
reg [2:0] imu_data_ready_d;
reg [5:0] imu_data_ready;
reg [1:0] seq_state_zero;
reg pre_scl;
reg [2:0] sngl_wire_stb;
reg [1:0] sngl_wire_r;
wire sngl_wire;
wire config_single_wire; // used in 103695 rev A
assign sngl_wire=~|sngl_wire_r[1:0];
assign shift_mosi=(clk_en[3] && seq_counter[0] && !stall);
assign mosi=config_single_wire?sngl_wire:mosi_reg[15];
assign config_long_sda_en=config_debug[0];
assign config_late_clk= config_debug[1];
assign config_single_wire=config_debug[2];
assign en=imu_enabled[1];
assign sda_en= !config_single_wire && (!sda || !sda_d || (config_long_sda_en && (seq_state[1:0]!=2'b0)));
assign scl_en= !config_single_wire && (!scl || !scl_d);
always @ (negedge sclk) begin
di_d[15:0] <= di[15:0];
if (we_div) bit_duration_mclk[7:0]<=di_d[7:0];
if (we_div) stall_dur_mclk[7:0]<=di_d[15:8];
we_timer[4:1] <= {we_timer[3:1], we_period};
if (we_period) period[31:0]<={di[15:0],di_d[15:0]};
if (we_timer[2]) imu_run_mclk <= (period[31:1]!=31'b0); // double-cycle
if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0];
if (we_timer[2]) imu_when_ready_mclk <= &period[31:16]; // double-cycle
if (!imu_enabled_mclk || imu_start_grant[1]) imu_start_mclk<=1'b0;
else if (we_timer[4])imu_start_mclk<=imu_enabled_mclk;
end
// debounce imu_data_ready
always @ (posedge xclk) begin
seq_state_zero[1:0] <= {seq_state_zero[0], ~|seq_state[1:0]};
imu_ready_reset <= !imu_enabled[1] || (seq_state[1:0]!=2'b0) || !imu_when_ready[1];
if (imu_ready_reset) imu_data_ready_d[2:0] <=3'b0;
else imu_data_ready_d[2:0] <= {imu_data_ready_d[1:0], miso};
if (imu_ready_reset) imu_data_ready[0] <= 1'b0;
else if (imu_ready_denoise_count[6:0]==7'h0) imu_data_ready[0] <= imu_data_ready_d[2];
if (imu_data_ready_d[2]==imu_data_ready[0]) imu_ready_denoise_count[6:0] <= 7'h7f; // use period LSBs?
else imu_ready_denoise_count[6:0] <= imu_ready_denoise_count[6:0] - 1;
if (imu_ready_reset) imu_data_ready[1] <= 1'b0;
else if (imu_data_ready[0]) imu_data_ready[1] <= 1'b1;
if (imu_ready_reset) imu_data_ready[2] <= 1'b0;
else if (imu_data_ready[1] && !imu_data_ready[0]) imu_data_ready[2] <= 1'b1;
if (imu_ready_reset) imu_data_ready[3] <= 1'b0;
else if (imu_data_ready[2] && imu_data_ready[0]) imu_data_ready[3] <= 1'b1;
if (clk_en[1]) imu_data_ready[4] <= imu_data_ready[3] ;
imu_data_ready[5] <=clk_en[1] && imu_data_ready[3] && !imu_data_ready[4]; // single pulse @clk_en[2]
end
always @ (posedge xclk) begin
imu_enabled[1:0] <= {imu_enabled[0],imu_enabled_mclk};
imu_run[1:0] <= {imu_run[0],imu_run_mclk};
imu_when_ready[1:0] <= {imu_when_ready[0],imu_when_ready_mclk};
if (~imu_run[1:0]) imu_run_confirmed <= 1'b0;
else if (imu_start_first) imu_run_confirmed <= imu_run[1];
imu_start_grant[1:0] <= {imu_enabled_mclk && (imu_start_grant[0] || (imu_start_grant[1] && !imu_start)),imu_start_mclk};
imu_start_first_was <= imu_start_grant[1] && (imu_start_first || imu_start_first_was);
imu_start_first<=clk_en[1] && imu_start_grant[1] && !imu_start_first_was; // single xclk at clk_en[2] time slot
imu_start <=(!imu_when_ready[1] && imu_start_first)||
(!imu_when_ready[1] && imu_run_confirmed && (period_counter[31:0]==32'h1) && clk_en[2]) ||
imu_data_ready[5]; // single pulses at clk_en[3]
if (imu_start || imu_when_ready[1]) period_counter[31:0] <= period[31:0];
else if (clk_en[3]) period_counter[31:0] <= period_counter[31:0] - 1;
end
always @ (posedge xclk) begin
bit_duration[7:0] <= bit_duration_mclk[7:0];
stall_dur[7:0] <= stall_dur_mclk[7:0];
bit_duration_zero <= (bit_duration[7:0]==8'h0);
clk_div[1:0] <= en?(clk_div[1:0]+1):2'b0;
clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3};
if (bit_duration_zero || (bit_duration_cntr[7:0]==8'h0)) bit_duration_cntr[7:0]<=bit_duration[7:0];
else bit_duration_cntr[7:0] <= bit_duration_cntr[7:0]-1;
clk_en[3:0] <= {clk_en[2:0],bit_duration_cntr[7:0]==8'h3}; // change 9'h3 to enforce frequency limit
end
always @ (posedge xclk) begin
pre_seq_counter_zero <= clk_en[1] && (seq_counter[9:0]==10'h0) && (seq_state[1:0]!=2'h0); // active at clk_en[2]
seq_counter_zero <= pre_seq_counter_zero; // active at clk_en[3]
if (!en) seq_state[1:0] <= 2'h0;
else if (imu_start) seq_state[1:0] <= 2'h1;
else if (seq_counter_zero ) seq_state[1:0] <= seq_state[1:0] + 1; // will not count from 0 as seq_counter_zero will be disabled
if (!en) first_prepare <=1'b0;
else if (imu_start) first_prepare <=1'b1;
else if (clk_en[3]) first_prepare <=1'b0;
if (!en) first_prepare_d[1:0] <= 2'b0;
else if (clk_en[3]) first_prepare_d[1:0] <= {first_prepare_d[0],first_prepare};
end_prepare <= pre_seq_counter_zero && (seq_state[1:0]==2'h1);
end_spi <= pre_seq_counter_zero && (seq_state[1:0]==2'h2);
if (!en) seq_counter[9:0] <= 10'h000;
else if (imu_start) seq_counter[9:0] <= config_late_clk?10'h005:10'h003; // should be odd
else if (end_prepare) seq_counter[9:0] <= 10'h39f;
else if (end_spi) seq_counter[9:0] <= 10'h001;
else if (clk_en[3] && (seq_state[1:0]!=2'h0) && !stall) seq_counter[9:0] <= seq_counter[9:0] - 1;
set_mosi_prepare <= clk_en[2] && first_prepare;
set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5] != 5'h0) && !stall; // last word use zero
// no stall before the first word
if (!en) skip_stall <= 1'b0;
else if (end_prepare) skip_stall <= 1'b1;
else if (clk_en[3]) skip_stall <= 1'b0;
// set_stall <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && !skip_stall; // same as set_mosi_spi, but including last
// set_stall <= clk_en[1] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && !skip_stall && !stall; // @ clk_en[2]
set_stall <= clk_en[0] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && !skip_stall && !stall; // @ clk_en[1]
if (!en) mosi_reg[15:0] <= 16'h0;
else if (set_mosi_prepare) mosi_reg[15:0] <= 16'h7fff;
else if (set_mosi_spi) mosi_reg[15:0] <= {1'b0,imu_reg_number[6:1],9'b0};
else if (shift_mosi) mosi_reg[15:0] <= {mosi_reg[14:0],1'b0};
// assign shift_mosi=(clk_en[3] && seq_counter[0] && !stall);
// stall switches at clk_en[2]
// stall switches at clk_en[1]
if (!en) stall_cntr[7:0] <= 8'h0;
else if (set_stall) stall_cntr[7:0] <= stall_dur[7:0];
else if (clk_en[1]) stall_cntr[7:0] <= stall?(stall_cntr[7:0]-1):8'h0;
if (!en) stall <= 1'b0;
else if (set_stall) stall <= (stall_dur[7:0]!=0);
else if (clk_en[1] && (stall_cntr[7:1]==0)) stall <= 1'b0;
if (!en) sda <=1'b1;
else if (clk_en[3]) sda <= !(first_prepare_d[1] || (seq_counter[0] && (seq_state[1:0]==2'h3))) ;
if (!en) sda_d <=1'b1;
else if (clk_en[3]) sda_d <= sda;
// if (!en) scl <=1'b1;
// else if (clk_en[3]) scl <= (seq_state[1:0]!=2'h2) || !seq_counter[0] || stall;
if (!en) pre_scl <=1'b1;
else if (clk_en[2]) pre_scl <= (seq_state[1:0]!=2'h2) || !seq_counter[0] || stall;
scl <= pre_scl;
sngl_wire_stb[2:0] <={sngl_wire_stb[1:0], en & ((scl ^ pre_scl) | end_prepare)};
if (!en) sngl_wire_r[0]<=1'b0;
// else if (!pre_scl && scl) sngl_wire_r[0]<=1'b1;
// else if (!mosi || sngl_wire_stb[2]) sngl_wire_r[0]<=1'b0;
else if ((pre_scl ^scl) | end_prepare) sngl_wire_r[0]<=1'b1;
else if (!mosi_reg[15] || sngl_wire_stb[2] || scl) sngl_wire_r[0]<=1'b0;
if (!en) scl_d <=1'b1;
else if (clk_en[3]) scl_d <= scl;
if (imu_start) reg_seq_number[4:0] <= 5'h04;
else if (set_mosi_spi) reg_seq_number[4:0] <= reg_seq_number[4:0] + 1;
shift_miso <= !scl_d && clk_en[2]; // active at clk_en[3]
// shift_miso <= !scl_d && clk_en[2] && !stall; // active at clk_en[3]
if (shift_miso) miso_reg[15:0] <= {miso_reg[14:0], miso};
last_bit <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h0) && (seq_counter[9:5]!=5'h1c);
last_bit_ext <= en && (last_bit || (last_bit_ext && !(clk_en[2] && !seq_counter[0])));
pre_imu_wr_buf <=clk_en[1] && last_bit_ext && !seq_counter[0];
imu_wr_buf <= pre_imu_wr_buf;
if (imu_start) imu_in_word[4:0] <= 5'h0;
else if (imu_wr_buf) imu_in_word[4:0] <= imu_in_word[4:0] + 1;
last_buf_wr <= (pre_imu_wr_buf && (seq_state[1:0]==2'h3));
end
always @ (negedge xclk) begin
sngl_wire_r[1] <= sngl_wire_stb[0];
end
always @ (posedge xclk) begin
if (!en || imu_start) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (imu_start || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy <= 1'b0; // only 28 words, not 32
else if (last_buf_wr) rdy <= 1'b1;
ts <=imu_start;
end
assign imu_in_buf[15:0]= miso_reg[15:0];
myRAM_WxD_D #( .DATA_WIDTH(6),.DATA_DEPTH(5))
i_registers2log (.D(di_d[6:1]),
.WE(we_ra),
.clk(!sclk),
.AW(wa[4:0]),
.AR(reg_seq_number[4:0]),
.QW(),
.QR(imu_reg_number[6:1]));
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(5))
i_odbuf0 (.D(imu_in_buf[15:0]),
.WE(imu_wr_buf),
.clk(xclk),
.AW(imu_in_word[4:0]),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[15:0]));
endmodule
/*
logs events from odometer (can be software triggered), includes 56-byte message written to the buffer
So it is possible to assert trig input (will request timestamp), write message by software, then
de-assert the trig input - message with the timestamp will be logged
fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
*/
module imu_message ( sclk, // system clock, negedge
xclk, // half frequency (80 MHz nominal)
we, // write enable for registers to log (@negedge sclk), with lower data half
wa, // write address for register (4 bits, @negedge sclk)
di, // 16-bit data in multiplexed
en, // enable module operation, if 0 - reset
trig, // leading edge - sample time, trailing set rdy
ts, // timestamop request
rdy, // data ready
rd_stb, // data read strobe (increment address)
rdata); // data out (16 bits)
input sclk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
input we; // write enable for registers to log (@negedge sclk)
input [3:0] wa; // write address for register (4 bits, @negedge sclk)
input [15:0] di; // 16-bit data in (32 multiplexed)
input en; // enable
input trig; // leading edge - sample time, trailing set rdy
output ts; // timestamp request
output rdy; // encoded nmea data ready
input rd_stb; // encoded nmea data read strobe (increment address)
output [15:0] rdata; // encoded data (16 bits)
reg [ 4:0] raddr;
reg rdy=1'b0;
reg we_d;
reg [ 4:1] waddr;
reg [ 2:0] trig_d;
reg [ 7:0] denoise_count;
reg [ 1:0] trig_denoise;
reg ts;
reg [15:0] di_d;
always @ (negedge sclk) begin
di_d[15:0] <= di[15:0];
waddr[4:1] <= wa[3:0];
we_d <=we;
end
always @ (posedge xclk) begin
if (!en) trig_d[2:0] <= 3'h0;
else trig_d[2:0] <= {trig_d[1:0], trig};
if (!en) trig_denoise[0] <= 1'b0;
else if (denoise_count[7:0]==8'h0) trig_denoise[0] <= trig_d[2];
if (trig_d[2]==trig_denoise[0]) denoise_count[7:0] <= 8'hff;
else denoise_count[7:0] <= denoise_count[7:0] - 1;
trig_denoise[1] <= trig_denoise[0];
ts <= !trig_denoise[1] && trig_denoise[0];
if (!en || ts) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (ts || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy <= 1'b0;
else if (trig_denoise[1] && !trig_denoise[0]) rdy <= 1'b1;
end
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(5))
i_odbuf (.D(di_d[15:0]),
.WE(we | we_d),
.clk(~sclk),
.AW({waddr[4:1],we_d}),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[15:0]));
endmodule
/*
logs frame synchronization data from other camera (same as frame sync)
*/
module imu_exttime ( xclk, // half frequency (80 MHz nominal)
en, // enable module operation, if 0 - reset
trig, // external time stamp updated
usec, // microseconds from external timestamp (should not chnage after trig for 10 xclk)
sec, // seconds from external timestamp
ts, // timestamop request
rdy, // data ready
rd_stb, // data read strobe (increment address)
rdata); // data out (16 bits)
input xclk; // half frequency (80 MHz nominal)
input en; // enable
input trig; // external time stamp updated
input [19:0] usec; // microseconds from external timestamp
input [31:0] sec; // seconds from external timestamp
output ts; // timestamp request
output rdy; // encoded nmea data ready
input rd_stb;// encoded nmea data read strobe (increment address)
output [15:0] rdata; // encoded data (16 bits)
reg [ 4:0] raddr;
reg rdy=1'b0;
reg we, pre_we;
reg [ 3:0] pre_waddr;
reg [ 1:0] waddr;
reg [ 2:0] trig_d;
reg pre_ts,ts;
reg [15:0] time_mux;
always @ (posedge xclk) begin
if (!en) trig_d[2:0] <= 3'h0;
else trig_d[2:0] <= {trig_d[1:0], trig};
pre_ts <= !trig_d[2] && trig_d[1];
ts <= pre_ts; // delayed so arbiter will enable ts to go through
if (!en || pre_ts) pre_waddr[3:0] <= 4'b0;
else if (!pre_waddr[3]) pre_waddr[3:0] <= pre_waddr[3:0] + 1;
if (pre_waddr[0]) waddr[1:0] <=pre_waddr[2:1];
if (pre_waddr[0] && !pre_waddr[3]) case (pre_waddr[2:1])
2'b00: time_mux[15:0] <= usec[15:0];
2'b01: time_mux[15:0] <= {12'h0,usec[19:16]};
2'b10: time_mux[15:0] <= sec[15:0];
2'b11: time_mux[15:0] <= sec[31:16];
endcase
pre_we<=pre_waddr[0] && !pre_waddr[3];
we <= pre_we;
if (!en || pre_ts) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (pre_ts || (rd_stb && (raddr[1:0]==2'h3)) || !en) rdy <= 1'b0;
else if (we && (waddr[1:0]==2'h3)) rdy <= 1'b1;
end
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(2))
i_odbuf (.D(time_mux[15:0]),
.WE(we),
.clk(xclk),
.AW(waddr[1:0]),
.AR(raddr[1:0]),
.QW(),
.QR(rdata[15:0]));
endmodule
module rs232_rcv (xclk, // half frequency (80 MHz nominal)
bitHalfPeriod, // half of the serial bit duration, in xclk cycles
ser_di, // rs232 (ttl) serial data in
ser_rst, // reset (force re-sync)
ts_stb, // strobe timestamp (start of message) (reset bit counters in nmea decoder)
wait_just_pause,// may be used as reset for decoder
start, // serial character start (single pulse)
// char, // byte out
// char_stb); // char strobe (@posedge xclk)
ser_do, // serial data out(@posedge xclk) LSB first!
ser_do_stb, // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
debug, // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset
bit_dur_cntr,
bit_cntr);
input xclk; // half frequency (80 MHz nominal)
input [15:0] bitHalfPeriod; // half of the serial bit duration, in xclk cycles
input ser_di; // rs232 (ttl) serial data in
input ser_rst; // reset (force re-sync)
output ts_stb; // strobe timestamp (start of message)
output wait_just_pause;// may be used as reset for decoder
output start; // serial character start (single pulse)
output [4:0] debug; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset
output ser_do; // serial data out(@posedge xclk)
output ser_do_stb; // output data strobe (@posedge xclk), 2 cycles after ser_do becomes valid
output [15:0] bit_dur_cntr; // debug
output [4:0] bit_cntr; // debug
reg [4:0] ser_di_d;
reg ser_filt_di;
reg ser_filt_di_d;
reg bit_half_end; // last cycle in half-bit
reg last_half_bit;
reg wait_pause; // waiting input to stay at 1 for 10 cycles
reg wait_start; // (or use in_sync - set it after wait_pause is over?
reg receiving_byte;
reg start;
reg [15:0] bit_dur_cntr; // bit duration counter (half bit duration)
reg [4:0] bit_cntr; // counts half-bit intervals
wire error; // low level during stop slot
reg [1:0] restart;
wire reset_wait_pause;
reg ts_stb;
reg shift_en;
reg ser_do;
reg ser_do_stb;
wire sample_bit;
wire reset_bit_duration;
reg wait_just_pause;
wire wstart;
wire [4:0] debug;
reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset // SuppressThisWarning Veditor UNUSED
assign reset_wait_pause= (restart[1] && !restart[0]) || (wait_pause && !wait_start && !ser_di);
assign error=!ser_filt_di && last_half_bit && bit_half_end && receiving_byte;
assign sample_bit=shift_en && bit_half_end && !bit_cntr[0];
assign reset_bit_duration= reset_wait_pause || start || bit_half_end || ser_rst;
assign wstart=wait_start && ser_filt_di_d && !ser_filt_di;
assign debug[4:0] = {1'b0,wait_start,wait_pause,receiving_byte,shift_en};
always @ (posedge xclk) begin
// reg [4:0] ser_di_d;
// reg ser_filt_di;
// reg ser_filt_di_d;
ser_di_d[4:0] <= {ser_di_d[3:0],ser_di};
if (ser_rst || &ser_di_d[4:0]) ser_filt_di <= 1'b1;
else if (~|ser_di_d[4:0]) ser_filt_di <= 1'b0;
ser_filt_di_d <= ser_filt_di;
restart[1:0] <= {restart[0],(ser_rst || (last_half_bit && bit_half_end && receiving_byte))};
wait_pause <= !ser_rst && (reset_wait_pause ||
(receiving_byte && last_half_bit && bit_half_end ) ||
(wait_pause && !(last_half_bit && bit_half_end) && !(wait_start && !ser_filt_di)));
// start <= wait_start && ser_di_d && !ser_di;
start <= wstart;
// ts_stb <= !wait_pause && wait_start && ser_di_d && !ser_di;
ts_stb <= !wait_pause && wstart; // only first start after pause
bit_half_end <=(bit_dur_cntr[15:0]==16'h1) && !reset_bit_duration;
// wait_start <= ser_di && !ser_rst && ((wait_pause || receiving_byte) && last_half_bit && bit_half_end || wait_start);
wait_start <= !ser_rst && ((wait_pause || receiving_byte) && last_half_bit && bit_half_end || (wait_start && !wstart));
// receiving_byte <= !ser_rst && !error && (start || (receiving_byte && !(last_half_bit && bit_half_end)));
receiving_byte <= !ser_rst && (start || (receiving_byte && !(last_half_bit && bit_half_end)));
wait_just_pause <=wait_pause && !wait_start;
if (reset_bit_duration) bit_dur_cntr[15:0] <= bitHalfPeriod[15:0];
else bit_dur_cntr[15:0] <= bit_dur_cntr[15:0] - 1;
if (reset_wait_pause || ser_rst) bit_cntr[4:0] <= 5'h13;
else if (start) bit_cntr[4:0] <= 5'h12;
else if (bit_half_end) bit_cntr[4:0] <= bit_cntr[4:0] - 1;
last_half_bit <= ((bit_cntr[4:0] == 5'h0) && !bit_half_end);
shift_en <= receiving_byte && ((bit_half_end && ( bit_cntr[3:0]==4'h2))? bit_cntr[4]:shift_en);
if (sample_bit) ser_do <= ser_filt_di;
ser_do_stb <= sample_bit;
if (ser_rst) debug0[4:0] <=5'b0;
else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d[0],~ser_di_d[0]};
end
endmodule
module nmea_decoder (sclk, // system clock, @negedge
we, // registers write enable (@negedge sclk)
wa, // registers write adderss
wd, // write data
xclk, // 80MHz, posedge
start, // start of the serail message
rs232_wait_pause,// may be used as reset for decoder
start_char, // serial character start (single pulse)
nmea_sent_start, // serial character start (single pulse)
ser_di, // serial data in (LSB first)
ser_stb,// serial data strobe, single-cycle, first cycle after ser_di valid
rdy, // encoded nmea data ready
rd_stb, // encoded nmea data read strobe (increment address)
rdata, // encoded data (16 bits)
ser_rst,
debug);
input sclk; // system clock, @negedge
input we; // registers write enable (@negedge sclk)
input [4:0] wa; // registers write adderss
input [7:0] wd; // write data
input xclk; // 80MHz, posedge
input start; // start of the serail message (after pause only)
input rs232_wait_pause;// may be used as reset for decoder
input start_char; // serial character start (single pulse)
output nmea_sent_start; // serial character start (single pulse), will repeat until got "$" and the sentence recognized
input ser_di; // serial data in (LSB first)
input ser_stb;// serial data strobe, single-cycle, ends 2 cycles after ser_di valid
output rdy; // encoded nmea data ready
input rd_stb; // encoded nmea data read strobe (increment address)
output [15:0] rdata; // encoded data (16 bits)
input ser_rst;
output[23:0] debug;
reg [ 9:0] bitnum;
reg gp_exp_bit;
reg valid; // so far valid sentence
reg [3:0] sentence1hot; // one-hot sentence, matching first 6 bytes ($GPxxx)
reg restart; // reset byte number if the first byte was not "$"
reg start_d;
reg [3:0] stb; // ser_stb delayed
reg msb,bits37,bit3;
reg vfy_dollar;
reg vfy_gp;
reg vfy_sel_sent;
reg vfy_first_comma; // first comma after $GPxxx
reg proc_fields;
reg last_vfy_gp; // delayed by 1 cycle from bit counters
reg last_vfy_sent; // delayed by 1 cycle from bit counters
// reg [3:0] sent_sel_cntr; // counts 3 times to 5, as $GPxxx - each 'x' is an upper case latter (0x40..0x5f)
reg lsbs5; // 5 LSBs during reading 3 last letters in $GPxxx
reg [3:0] gpxxx_addr;
wire [3:1] sentence1hot_pri; // sentence1hot made really one-hot
reg [1:0] sentence; // decoded sentence number (0..3)
reg [4:0] format_length; // number of fields in the sentence
reg [4:0] format_length_plus_7;
reg [4:0] format_field; // current number of the field in the sentence
wire start_format;
reg read_format_length; //, read_format_length_d;
reg read_format_byte;
reg shift_format_byte;
reg format_over;
reg sentence_over;
reg [7:0] format_byte;
reg [7:1] last_byte;
wire wcomma; // comma
wire weof; //asterisk, or cr/lf (<0x10)
wire wsep; //any separator
reg [3:0] nibble;
reg [3:0] nibble_pre;
wire [7:0] wbyte;
reg nibble_stb;
reg first_byte_in_field;
reg [1:0] extra_nibble; // empty byte field - send two 4'hf nibbles
reg [6:0] nibble_count;
wire [15:0] rdata; // encoded data (16 bits)
reg [ 4:0] raddr;
wire [3:0] gpxxx_w_one;
wire [7:0] format_data;
wire w_sentence_over;
reg [4:0] last_word_written; // number of the last word (4 nibbles) written - used ro deassert rdy (garbage after)
reg rdy=1'b0;
reg nmea_sent_start;
reg save_sent_number;
// input ser_rst;
reg [ 7:0] debug0;
reg [15:0] debug1;
reg [15:0] debug1_or;
wire [23:0] debug;
// assign debug[23:0] = {debug1[15:0],debug0[7:0]};
assign debug[23:0] = {1'b0,
proc_fields,
vfy_first_comma,
vfy_sel_sent,
vfy_gp,
vfy_dollar,
bitnum[9:0],
debug0[7:0]};
assign sentence1hot_pri[3:1]={sentence1hot[3]& ~|sentence1hot[2:0],
sentence1hot[2]& ~|sentence1hot[1:0],
sentence1hot[1]& ~sentence1hot[0]};
// assign start_format=(last_vfy_sent && (sentence1hot[3:0]!=4'h0) && (stb[3] && msb));
assign start_format=(vfy_first_comma && (sentence1hot[3:0]!=4'h0) && (stb[3] && msb));
assign wbyte[7:0]={ser_di,last_byte[7:1]}; // valid up to stb[3];
assign wcomma= proc_fields && msb && (wbyte[7:0]==8'h2c);
assign weof= proc_fields && msb && ((wbyte[7:0]==8'h2a) || (wbyte[7:4]==4'h0)); // 0x2a or 0x0? (<0x10)
assign wsep= wcomma || weof;
// assign w_sentence_over=wsep && (format_field[2:0]==format_length[2:0]) && (format_field[4:3]==(format_length[4:3]+1));
assign w_sentence_over=wsep && (format_field[4:0]==format_length_plus_7[4:0]);
//format_length_plus_7
always @ (posedge xclk) begin
if (ser_rst) debug0 [7:0] <= 8'b0;
else debug0 [7:0] <=debug0 [7:0] | {rdy,
proc_fields,
shift_format_byte,
start_format,
vfy_first_comma,
vfy_sel_sent,
vfy_gp,
vfy_dollar};
if (ser_rst) debug1 [15:0] <= 16'b0;
else if (stb[1] && vfy_sel_sent && lsbs5) debug1 [15:0] <= debug1 [15:0] | debug1_or [15:0];
case (gpxxx_addr[3:0])
4'h0: debug1_or[15:0] <= 16'h0001;
4'h1: debug1_or[15:0] <= 16'h0002;
4'h2: debug1_or[15:0] <= 16'h0004;
4'h3: debug1_or[15:0] <= 16'h0008;
4'h4: debug1_or[15:0] <= 16'h0010;
4'h5: debug1_or[15:0] <= 16'h0020;
4'h6: debug1_or[15:0] <= 16'h0040;
4'h7: debug1_or[15:0] <= 16'h0080;
4'h8: debug1_or[15:0] <= 16'h0100;
4'h9: debug1_or[15:0] <= 16'h0200;
4'ha: debug1_or[15:0] <= 16'h0400;
4'hb: debug1_or[15:0] <= 16'h0800;
4'hc: debug1_or[15:0] <= 16'h1000;
4'hd: debug1_or[15:0] <= 16'h2000;
4'he: debug1_or[15:0] <= 16'h4000;
4'hf: debug1_or[15:0] <= 16'h8000;
endcase
stb[3:0] <= {stb[2:0], ser_stb};
start_d <= start;
restart <= start || sentence_over || stb[2] && msb && ((!valid && (vfy_dollar || last_vfy_gp || vfy_first_comma)) || // may abort earlier (use vfy_gp)
((sentence1hot==4'h0) && last_vfy_sent)); // may abort earlier (use vfy_sel_sent)
if (start_d) bitnum[2:0] <= 3'h0;
else if (stb[3]) bitnum[2:0] <= bitnum[2:0] + 1;
if (start_d) msb <= 1'b0;
else if (stb[3]) msb <= (bitnum[2:0] ==3'h6);
if (start_d) bit3 <= 1'b0;
else if (stb[3]) bit3 <= (bitnum[2:0] ==3'h2);
if (start_d) bits37 <= 1'b0;
else if (stb[3]) bits37 <= (bitnum[1:0] ==2'h2);
if (start_d) lsbs5 <= 1'b1;
else if (stb[3]) lsbs5 <= !bitnum[2] || (bitnum[2:0] ==3'h7);
if (restart) bitnum[9:3] <= 'h0;
else if (stb[3] && msb) bitnum[9:3] <= bitnum[9:3] + 1;
if (restart || rs232_wait_pause) vfy_dollar <= 1'b1; // byte 0
else if (stb[3] && msb) vfy_dollar <= 1'b0;
last_vfy_gp <= vfy_gp && !bitnum[3];
if (restart) vfy_gp <= 1'b0;
else if (stb[3] && msb) vfy_gp <= (valid && vfy_dollar) || (vfy_gp && !last_vfy_gp); // bytes 1-2
last_vfy_sent <= vfy_sel_sent && (bitnum[3] && bitnum[5]);
if (restart) vfy_sel_sent <= 1'b0;
else if (stb[3] && msb) vfy_sel_sent <= (valid && last_vfy_gp) || (vfy_sel_sent && !last_vfy_sent); // bytes 3,4,5
if (restart) vfy_first_comma <= 1'b0;
else if (stb[3] && msb) vfy_first_comma <= last_vfy_sent;
if (restart) valid <= 1'b1; // ready @ stb[2]
else if (stb[1] && (ser_di!=gp_exp_bit) &&
(vfy_dollar || vfy_gp || vfy_first_comma || (vfy_sel_sent && !lsbs5))) valid <= 1'b0;
if (!vfy_sel_sent) gpxxx_addr[3:0] <= 4'h0;
else if (lsbs5 &&stb[3]) gpxxx_addr[3:0] <= gpxxx_addr[3:0] + 1;
if (vfy_gp) sentence1hot[3:0] <= 4'hf;
else if (stb[1] && vfy_sel_sent && lsbs5) sentence1hot[3:0] <= sentence1hot & (ser_di?(gpxxx_w_one[3:0]): (~gpxxx_w_one[3:0]));
if (last_vfy_sent && stb[3] && msb) sentence[1:0] <= {sentence1hot_pri[3] | sentence1hot_pri[2], sentence1hot_pri[3] | sentence1hot_pri[1]};
if (restart || sentence_over) proc_fields <=1'b0;
else if (start_format) proc_fields <=1'b1;
if (!proc_fields) format_field[4:0] <= 5'h0;
else if (read_format_length) format_field[4:0] <= 5'h8;
else if (format_over) format_field[4:0] <= format_field[4:0] + 1;
format_length_plus_7[4:0] <= format_length[4:0]+7;
if (start_format) first_byte_in_field <=1'b1;
else if (stb[3] && msb) first_byte_in_field <= format_over;
read_format_length <= start_format;
if (read_format_length) format_length[4:0] <= format_data[4:0];
read_format_byte <= read_format_length || (format_over && format_field[2:0]==3'h7); // @stb[4]
shift_format_byte <= format_over; // @stb[4]
if (read_format_byte) format_byte[7:0] <= format_data[7:0];
else if (shift_format_byte) format_byte[7:0] <= {1'b0,format_byte[7:1]};
// format_byte[0] - current format
if (stb[3]) last_byte[7:1] <= {ser_di,last_byte[7:2]};
format_over <= stb[2] && wsep;
// sentence_over <= stb[2] && (weof || (wsep && w_sentence_over));
sentence_over <= stb[2] && (weof || w_sentence_over);
if (bits37 && stb[3]) nibble_pre[3:0] <= last_byte[4:1]; // always OK
if (stb[3] && bit3) nibble[3:0] <= nibble_pre[3:0];
else if (stb[3] && msb && wsep && (first_byte_in_field || !format_byte[0])) nibble[3:0] <= 4'hf;
else if (stb[3] && msb && format_byte[0]) nibble[3:0] <= {wsep,nibble_pre[2:0]};
else if (save_sent_number) nibble[3:0] <= {2'b0,sentence[1:0]};
//first_byte_in_field
extra_nibble[1:0] <= {extra_nibble[0],
msb && wsep && first_byte_in_field & proc_fields & stb[3] & format_byte[0]};// active at stb[4], stb[5]
save_sent_number <= start_format; // valid at stb[4]
nibble_stb <= save_sent_number ||
(proc_fields && ((stb[3] && bit3 && !first_byte_in_field) ||
(stb[3] && msb && !first_byte_in_field && format_byte[0]) ||
(stb[3] && msb && wsep))) || extra_nibble[1]; // extra_nibble[1] will repeat 4'hf
if (start_format) nibble_count[6:0] <= 7'h0;
else if (nibble_stb) nibble_count[6:0] <= nibble_count[6:0] + 1;
// if (weof && stb[3]) raddr[4:0] <= 5'h0;
if (sentence_over) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (nibble_stb) last_word_written[4:0]<=nibble_count[6:2];
if (start || vfy_first_comma || (rd_stb && ((raddr[4:0]==5'h1b) ||(raddr[4:0]==last_word_written[4:0])))) rdy <= 1'b0;
else if (sentence_over) rdy <= 1'b1;
nmea_sent_start <= start_char && vfy_dollar;
end
// output buffer to hold up to 32 16-bit words. Written 1 nibble at a time
myRAM_WxD_D #( .DATA_WIDTH(4),.DATA_DEPTH(5))
i_odbuf0 (.D(nibble[3:0]),
.WE(nibble_stb && (nibble_count[1:0]==2'h0)),
.clk(xclk),
.AW(nibble_count[6:2]),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[3:0]));
myRAM_WxD_D #( .DATA_WIDTH(4),.DATA_DEPTH(5))
i_odbuf1 (.D(nibble[3:0]),
.WE(nibble_stb && (nibble_count[1:0]==2'h1)),
.clk(xclk),
.AW(nibble_count[6:2]),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[7:4]));
myRAM_WxD_D #( .DATA_WIDTH(4),.DATA_DEPTH(5))
i_odbuf2 (.D(nibble[3:0]),
.WE(nibble_stb && (nibble_count[1:0]==2'h2)),
.clk(xclk),
.AW(nibble_count[6:2]),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[11:8]));
myRAM_WxD_D #( .DATA_WIDTH(4),.DATA_DEPTH(5))
i_odbuf3 (.D(nibble[3:0]),
.WE(nibble_stb && (nibble_count[1:0]==2'h3)),
.clk(xclk),
.AW(nibble_count[6:2]),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[15:12]));
myRAM_WxD_D #( .DATA_WIDTH(4),.DATA_DEPTH(4))
i_gpxxx (.D(wd[3:0]),
.WE(we & ~wa[4]), // we_d, decoded sub_address
.clk(!sclk),
.AW(wa[3:0]),
.AR(gpxxx_addr[3:0]),
.QW(),
.QR(gpxxx_w_one[3:0]));
// for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea filed (LSB first):
// 0 - nibble ("-" -> 0xd, "." -> 0xe), terminated with 0xf
// 1 - byte (2 nibbles), all bytes but last have MSB clear, last - set.
// No padding of nibbles to byte borders, bytes are encoded as 2 nibbles
myRAM_WxD_D #( .DATA_WIDTH(8),.DATA_DEPTH(4))
i_format (.D(wd[7:0]),
.WE(we & wa[4]), // we_d, decoded sub_address
.clk(!sclk),
.AW(wa[3:0]),
.AR({sentence[1:0],format_field[4:3]}),
.QW(),
.QR(format_data[7:0]));
// ROM to decode "$GP"
always @ (posedge xclk) begin
if (ser_stb) case ({(bitnum[4] & ~ vfy_sel_sent) | vfy_first_comma, bitnum[3] | vfy_sel_sent | vfy_first_comma, bitnum[2:0]}) // during vfy_sel_sent will point to 1 ('G')
5'h00: gp_exp_bit <= 1'b0; //$
5'h01: gp_exp_bit <= 1'b0;
5'h02: gp_exp_bit <= 1'b1;
5'h03: gp_exp_bit <= 1'b0;
5'h04: gp_exp_bit <= 1'b0;
5'h05: gp_exp_bit <= 1'b1;
5'h06: gp_exp_bit <= 1'b0;
5'h07: gp_exp_bit <= 1'b0;
5'h08: gp_exp_bit <= 1'b1; //G
5'h09: gp_exp_bit <= 1'b1;
5'h0a: gp_exp_bit <= 1'b1;
5'h0b: gp_exp_bit <= 1'b0;
5'h0c: gp_exp_bit <= 1'b0;
5'h0d: gp_exp_bit <= 1'b0;
5'h0e: gp_exp_bit <= 1'b1;
5'h0f: gp_exp_bit <= 1'b0;
5'h10: gp_exp_bit <= 1'b0; //P
5'h11: gp_exp_bit <= 1'b0;
5'h12: gp_exp_bit <= 1'b0;
5'h13: gp_exp_bit <= 1'b0;
5'h14: gp_exp_bit <= 1'b1;
5'h15: gp_exp_bit <= 1'b0;
5'h16: gp_exp_bit <= 1'b1;
5'h17: gp_exp_bit <= 1'b0;
5'h18: gp_exp_bit <= 1'b0; //'h2c: "," - will use later - attach first comma to $GPxxx,
5'h19: gp_exp_bit <= 1'b0;
5'h1a: gp_exp_bit <= 1'b1;
5'h1b: gp_exp_bit <= 1'b1;
5'h1c: gp_exp_bit <= 1'b0;
5'h1d: gp_exp_bit <= 1'b1;
5'h1e: gp_exp_bit <= 1'b0;
5'h1f: gp_exp_bit <= 1'b0;
default:gp_exp_bit <= 1'bX;
endcase
end
endmodule
module imu_timestamps (
sclk, // 160MHz, negedge
xclk, // 80 MHz, posedge
rst, // reset (@posedge xclk)
sec, // running seconds (@negedge sclk)
usec, // running microseconds (@negedge sclk)
ts_rq,// requests to create timestamps (4 channels), @posedge xclk
ts_ackn, // timestamp for this channel is stored
ra, // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
dout);// output data
input sclk;
input xclk;
input rst;
input [31:0] sec;
input [19:0] usec;
input [ 3:0] ts_rq;
output [ 3:0] ts_ackn;
input [ 3:0] ra;
output [15:0] dout;
reg [31:0] sec_latched;
reg [19:0] usec_latched;
reg [15:0] ts_mux;
reg [ 3:0] wa;
reg srst;
reg [3:0] rq_d;
reg [3:0] rq_d2;
reg [3:0] rq_r;
reg [3:0] rq_sclk;
reg [3:0] rq_sclk2;
reg [3:0] pri_sclk;
reg [3:0] pri_sclk_d;
reg [3:0] rst_rq;
reg [9:0] proc;
wire wstart;
reg we;
wire [3:0] wrst_rq;
reg [3:0] ts_preackn;
reg [3:0] ts_ackn;
assign wstart=|pri_sclk[3:0] && (pri_sclk[3:0] != pri_sclk_d[3:0]);
assign wrst_rq[3:0]={wa[3]&wa[2],wa[3]&~wa[2],~wa[3]&wa[2],~wa[3]&~wa[2]} & {4{proc[5]}};
always @ (posedge xclk) begin
rq_d[3:0] <= ts_rq[3:0];
rq_d2[3:0] <= rq_d[3:0];
end
always @ (negedge sclk) begin
srst <= rst;
rq_sclk[3:0] <= srst?4'h0:(~rst_rq[3:0] & (rq_r[3:0] | rq_sclk[3:0])) ;
rq_sclk2[3:0] <= srst?4'h0:(~rst_rq[3:0] & rq_sclk[3:0]) ;
pri_sclk[3:0] <= {rq_sclk2[3] & ~|rq_sclk2[2:0],
rq_sclk2[2] & ~|rq_sclk2[1:0],
rq_sclk2[1] & ~rq_sclk2[0],
rq_sclk2[0]};
pri_sclk_d[3:0] <= pri_sclk[3:0];
proc[9:0] <= {proc[8:0], wstart};
if (proc[0]) wa[3:2] <= {|pri_sclk_d[3:2], pri_sclk_d[3] | pri_sclk_d[1]};
if (proc[0]) sec_latched[31:0] <= sec[31:0];
if (proc[0]) usec_latched[19:0] <= usec[19:0];
// if (proc[2]) ts_mux[15:0] <= {6'h0,wa[3:2],4'h0,usec[19:16]};
casex({proc[8],proc[6],proc[4],proc[2]})
// 4'bXXX1: ts_mux[15:0] <= {6'h0,wa[3:2],4'h0,usec_latched[19:16]};
// 4'bXX1X: ts_mux[15:0] <= usec_latched[15: 0];
// 4'bX1XX: ts_mux[15:0] <= sec_latched[31:16];
// 4'b1XXX: ts_mux[15:0] <= sec_latched[15: 0];
4'bXXX1: ts_mux[15:0] <= usec_latched[15: 0];
4'bXX1X: ts_mux[15:0] <= {6'h0,wa[3:2],4'h0,usec_latched[19:16]};
4'bX1XX: ts_mux[15:0] <= sec_latched[15: 0];
4'b1XXX: ts_mux[15:0] <= sec_latched[31:16];
endcase
we <= proc[3] || proc[5] || proc[7] || proc[9];
if (proc[2]) wa[1:0] <= 2'b0;
else if (we) wa[1:0] <= wa[1:0] + 1;
rst_rq[3:0] <= wrst_rq[3:0] | {4{srst}};
end
always @ (posedge xclk or posedge rq_sclk2[0]) begin
if (rq_sclk2[0]) rq_r[0] <= 1'b0;
else if (srst) rq_r[0] <= 1'b0;
else if (rq_d[0] && !rq_d2[0]) rq_r[0] <= 1'b1;
end
always @ (posedge xclk or posedge rq_sclk2[1]) begin
if (rq_sclk2[1]) rq_r[1] <= 1'b0;
else if (srst) rq_r[1] <= 1'b0;
else if (rq_d[1] && !rq_d2[1]) rq_r[1] <= 1'b1;
end
always @ (posedge xclk or posedge rq_sclk2[2]) begin
if (rq_sclk2[2]) rq_r[2] <= 1'b0;
else if (srst) rq_r[2] <= 1'b0;
else if (rq_d[2] && !rq_d2[2]) rq_r[2] <= 1'b1;
end
always @ (posedge xclk or posedge rq_sclk2[3]) begin
if (rq_sclk2[3]) rq_r[3] <= 1'b0;
else if (srst) rq_r[3] <= 1'b0;
else if (rq_d[3] && !rq_d2[3]) rq_r[3] <= 1'b1;
end
always @ (posedge xclk or posedge rst_rq[0]) begin
if (rst_rq[0]) ts_preackn[0] <= 1'b1;
else if (!ts_rq[0]) ts_preackn[0] <= 1'b0;
end
always @ (posedge xclk or posedge rst_rq[1]) begin
if (rst_rq[1]) ts_preackn[1] <= 1'b1;
else if (!ts_rq[1]) ts_preackn[1] <= 1'b0;
end
always @ (posedge xclk or posedge rst_rq[2]) begin
if (rst_rq[2]) ts_preackn[2] <= 1'b1;
else if (!ts_rq[2]) ts_preackn[2] <= 1'b0;
end
always @ (posedge xclk or posedge rst_rq[3]) begin
if (rst_rq[3]) ts_preackn[3] <= 1'b1;
else if (!ts_rq[3]) ts_preackn[3] <= 1'b0;
end
always @ (posedge xclk) begin
ts_ackn[3:0] <= ts_preackn[3:0] & ts_rq[3:0];
end
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(4))
i_ts (.D(ts_mux[15:0]),
.WE(we), // we_d, decoded sub_address
.clk(!sclk),
.AW(wa[3:0]),
.AR(ra[3:0]),
.QW(),
.QR(dout[15:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_2_V
`define SKY130_FD_SC_LS__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_2_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:11 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.4 2005/11/30 14:04:15 wig Exp $
// $Date: 2005/11/30 14:04:15 $
// $Log: ent_b.v,v $
// Revision 1.4 2005/11/30 14:04:15 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
// Generated include statements
use_b.c_b1 use_b.c_b2
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_be_1024x16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_be_1024x16 (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input [1:0] byteena_a;
input [1:0] byteena_b;
input clock;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 [1:0] byteena_b;
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.byteena_b (byteena_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 2,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "2"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC "byteena_a[1..0]"
// Retrieval info: USED_PORT: byteena_b 0 0 2 0 INPUT VCC "byteena_b[1..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
// Retrieval info: CONNECT: @byteena_b 0 0 2 0 byteena_b 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_be_1024x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_be_1024x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_be_1024x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_be_1024x16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_be_1024x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_be_1024x16_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V |
module note2dds(clk, note, adder);
input wire clk;
input wire [8:0] note; // запас 2 бита. то есть нота не до 127, а до 512!
output [31:0] adder;
reg [31:0] adder_tbl [15:0];
reg [3:0] addr;
reg [3:0] divider;
// note div 12 ( * 0,08333333333333333333333333333333)
//; Add input / 16 to accumulator
//; Add input / 64 to accumulator
initial begin
addr <= 4'd0;
divider <= 4'd0;
adder_tbl[ 4'd0] <= 32'd0368205249;
adder_tbl[ 4'd1] <= 32'd0390099873;
adder_tbl[ 4'd2] <= 32'd0413296419;
adder_tbl[ 4'd3] <= 32'd0437872302;
adder_tbl[ 4'd4] <= 32'd0463909545;
adder_tbl[ 4'd5] <= 32'd0491495042;
adder_tbl[ 4'd6] <= 32'd0520720858;
adder_tbl[ 4'd7] <= 32'd0551684531;
adder_tbl[ 4'd8] <= 32'd0584489400;
adder_tbl[ 4'd9] <= 32'd0619244949;
adder_tbl[ 4'd10] <= 32'd0656067170;
adder_tbl[ 4'd11] <= 32'd0695078954;
adder_tbl[4'd12] <= 32'd0;
adder_tbl[4'd13] <= 32'd0;
adder_tbl[4'd14] <= 32'd0;
adder_tbl[4'd15] <= 32'd0;
end
assign adder = adder_tbl[addr] >> divider;
wire [5:0] diap = (note < 12) ? 6'd00 :
(note < 24) ? 6'd01 :
(note < 36) ? 6'd02 :
(note < 48) ? 6'd03 :
(note < 60) ? 6'd04 :
(note < 72) ? 6'd05 :
(note < 84) ? 6'd06 :
(note < 96) ? 6'd07 :
(note < 108) ? 6'd08 :
(note < 120) ? 6'd09 :
(note < 132) ? 6'd10 :
(note < 144) ? 6'd11 :
(note < 156) ? 6'd12 :
(note < 168) ? 6'd13 :
(note < 180) ? 6'd14 :
(note < 192) ? 6'd15 :
(note < 204) ? 6'd16 :
(note < 216) ? 6'd17 :
(note < 228) ? 6'd18 :
(note < 240) ? 6'd19 :
(note < 252) ? 6'd20 :
(note < 264) ? 6'd21 :
(note < 276) ? 6'd22 :
(note < 288) ? 6'd23 :
(note < 300) ? 6'd24 :
(note < 312) ? 6'd25 :
(note < 324) ? 6'd26 :
(note < 336) ? 6'd27 :
(note < 348) ? 6'd28 :
(note < 360) ? 6'd29 :
(note < 372) ? 6'd30 :
(note < 384) ? 6'd31 :
(note < 396) ? 6'd32 :
(note < 408) ? 6'd33 :
(note < 420) ? 6'd34 :
(note < 432) ? 6'd35 :
(note < 444) ? 6'd36 :
(note < 456) ? 6'd37 :
(note < 468) ? 6'd38 :
(note < 480) ? 6'd39 :
(note < 492) ? 6'd40 :
(note < 504) ? 6'd41 : 6'd042 ;
wire [6:0] c_addr = note - (diap * 4'd012);
always @ (posedge clk) begin
addr <= c_addr[3:0];
divider <= 6'd042 - diap;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_PP_BLACKBOX_V
|
`timescale 1ns/10ps
// -----------------------------------------------------------------------
//
// Copyright 2004,2007 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
BETTER NAME WANTED!
P i p e C o n n e c t
A pipelined interconnect for inter-core master-target communication.
Rev: 0.1
Introduction:
- Inspired by WISHBONE(tm)
- Major improvement: enhanched for pipeline operation
- Simple operation
- Synchronous
Notation:
s' is the value of s in the previous clock cycle
Signals:
Master Target Size
addr O I m
rd_strobe O I 1
wr_strobe O I 1
wr_data O I n (typical 16, 32)
wr_byteena O I n/8
hold I O 1
rd_data I O n
Operation:
Asserting rd_strobe indicates that addr is to be latched and placed on rd_data
in the next cycle. If the target can't make that, then hold is asserted
immediately and held until the cycle preceding the valid data on rd_data.
Asserting wr_strobe indicates that addr, wr_data, and wr_byteena is to be
latched and the bytes masked by wr_byteena be written at addr. If target
isn't ready to receive the command, the hold is asserted immediately and held
until the inputs are latched.
A fast target can accept a read or a write command each cycle and will never
assert hold.
Invariants:
INV #1: [MASTER] No simultations reads and write (on the same port)
rd_strobe /\ wr_strobe = 0
INV #2: [MASTER] Inputs must be held stable while hold is asserted
hold' => addr = addr' /\ rd_strobe = rd_strobe' /\
wr_strobe = wr_strobe' /\ wr_data = wr_data' /\ wr_byteena = wr_byteena'
INV #3: [TARGET] Hold can only be asserted when active
~rd_strobe /\ ~wr_strobe => hold = 0
(Maybe, still debated) rd_data must be lowered when idle
INV #4: [TARGET] ~rd_strobe' => rd_data = 0
REWIRING:
To ease the wiring of these signals, they are compounded into two
structions: request and result.
req={addr,rd_strobe,wr_strobe,wr_data,wr_byteena}
res={rd_data,hold}
************************************************************************************/
`define AWM1 31
`define REQ [`AWM1+38:0]
`define RES [32:0]
// Request subfields
`define A [`AWM1+38:38]
`define R [37]
`define W [36]
`define WD [35: 4]
`define WBE [ 3: 0]
// Result subfields
`define HOLD [0]
`define RD [32:1]
module pipechecker(where, clk, req, res);
parameter m = 32;
parameter n = 32;
input wire clk;
input wire `REQ req;
input wire `RES res;
input wire [8*16:1] where;
wire [m-1:0] addr;
wire rd_strobe;
wire wr_strobe;
wire [n-1:0] wr_data;
wire [n/8-1:0] wr_byteena;
wire hold;
wire [n-1:0] rd_data;
`ifdef SIMULATE_MAIN
reg `REQ req_ = 0;
reg `RES res_ = 0;
always @(posedge clk) begin
req_ <= req;
res_ <= res;
end
// INV #1
always @(posedge clk)
if (req`R & req`W)
$display("%5d PIPECHECKER: %s INV #1 violation, no simultaneous rd and wr", $time, where);
// INV #2
always @(posedge clk)
if (res_`HOLD && req_ != req) begin
$display("%5d PIPECHECKER: %s INV #2 violation, request changed while hold active", $time, where);
$display(" OLD: A %x R %d W %d RD %x WD %x", req_`A, req_`R, req_`W, req_`RD, req_`WD);
$display(" NEW: A %x R %d W %d RD %x WD %x", req`A, req`R, req`W, req`RD, req`WD);
end
// INV #3
always @(posedge clk)
if (~req`R & ~req`W & res`HOLD)
$display("%5d PIPECHECKER: %s INV #3 violation, hold asserted without read or write strobe", $time, where);
// INV #4
always @(posedge clk)
if (~req_`R & |res`RD)
$display("%5d PIPECHECKER: %s INV #4 violation, data non-zero without a read in last cycle", $time, where);
`endif
endmodule
/*
Examples:
Trivial parallel IO port target:
m = 0, n = 8
module ioport(input wire clk,
input wire [7:0] external_in,
output reg [7:0] external_out = 0,
input wire [m-1:0] addr,
input wire rd_strobe,
input wire wr_strobe,
input wire [n-1:0] wr_data,
input wire [n/8-1:0] wr_byteena,
output wire hold,
output reg rd_data = 0);
assign hold = 0;
always @(posedge clk) begin
rd_data <= rd_strobe ? external_in : 0;
if (wr_strobe & wr_byteena)
external_out <= wr_data;
end
endmodule
*/
// Demultiplexer: shares a master between two targets
module demux2(clk, // Unused
selA,
req, res,
portA_req, portA_res,
portB_req, portB_res);
parameter m = 32;
parameter n = 32;
input wire clk; // Unused
input wire selA;
input wire `REQ req;
output wire `RES res;
output wire `REQ portA_req;
input wire `RES portA_res;
output wire `REQ portB_req;
input wire `RES portB_res;
assign res`HOLD = portA_res`HOLD | portB_res`HOLD; // Depends on INV #3
assign res`RD = portA_res`RD | portB_res`RD; // Depends on INV #4
assign portA_req`A = req`A;
assign portA_req`R = req`R & selA;
assign portA_req`W = req`W & selA;
assign portA_req`WD = req`WD;
assign portA_req`WBE = req`WBE;
assign portB_req`A = req`A;
assign portB_req`R = req`R & ~selA;
assign portB_req`W = req`W & ~selA;
assign portB_req`WD = req`WD;
assign portB_req`WBE = req`WBE;
`ifdef SIMULATE_MAIN
pipechecker #(m,n) check("demux", clk, req, res);
pipechecker #(m,n) checkA("demux A", clk, portA_req, portA_res);
pipechecker #(m,n) checkB("demux B", clk, portB_req, portB_res);
`endif
endmodule
// Demultiplexer: shares a master between three targets
module demux3(input wire clk
,input wire selA
,input wire selB
,input wire `REQ req
,output wire `RES res
,output wire `REQ portA_req
,input wire `RES portA_res
,output wire `REQ portB_req
,input wire `RES portB_res
,output wire `REQ portC_req
,input wire `RES portC_res
);
assign res`HOLD =
portA_res`HOLD | portB_res`HOLD | portC_res`HOLD; // Depends on INV #3
assign res`RD =
portA_res`RD | portB_res`RD | portC_res`RD; // Depends on INV #4
assign portA_req`A = req`A;
assign portA_req`R = req`R & selA;
assign portA_req`W = req`W & selA;
assign portA_req`WD = req`WD;
assign portA_req`WBE = req`WBE;
assign portB_req`A = req`A;
assign portB_req`R = req`R & selB;
assign portB_req`W = req`W & selB;
assign portB_req`WD = req`WD;
assign portB_req`WBE = req`WBE;
assign portC_req`A = req`A;
assign portC_req`R = req`R & ~(selA|selB);
assign portC_req`W = req`W & ~(selA|selB);
assign portC_req`WD = req`WD;
assign portC_req`WBE = req`WBE;
`ifdef SIMULATE_MAIN
pipechecker check("demux", clk, req, res);
pipechecker checkA("demux A", clk, portA_req, portA_res);
pipechecker checkB("demux B", clk, portB_req, portB_res);
pipechecker checkC("demux C", clk, portC_req, portC_res);
`endif
endmodule
// Prioritized multiplexer (port arbitration): shares a target between
// two masters
module mux2(
input wire clk,
input wire `REQ portA_req,
output wire `RES portA_res,
input wire `REQ portB_req,
output wire `RES portB_res,
output wire `REQ req,
input wire `RES res);
parameter m = 32;
parameter n = 32;
// There are trivial for the two-port case, but to illustrate how to scale...
wire portA_strobe = portA_req`R | portA_req`W;
wire portB_strobe = portB_req`R | portB_req`W;
// Prioritized arbitration
/*
XXX Must be very careful when the target issues a hold (wait).
If it previously was in a wait condition, then current input must be
ignored until the hold clears. Tricky.
The following diagram illustrates how port B keeps the request while
the target is in the hold condition even a request from (higher
priority) port A comes in. However, as soon as B's initial bus cycle
is over, port A wins the next arbitration. (Read requests used for
this example).
Port B must keep the bus while hold is active
| Request from port B accepted, port B loses the bus to A (thus B holds)
| | Data for port B from sampled, request from port B noted
| | |
v v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
readA read ______________________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
portB read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
selected ________<BBBBBBBBBBBBBBBBBBBBBBBBBB><AAAAAAAAAAAA><BBBBBBBBBBBB>_______________________
addr --------<###### Addr B1 ###########><## Addr A ##><## Addr B2##>-----------------------
hold _____________/~~~~~~~~~~~~\________________________________________________
data _______________________________________<## Data B1##><## Data A ##><## Data B2##>
portA hold ______________________/~~~~~~~~~~~~\________________________________________________
portB hold _____________/~~~~~~~~~~~~\_________/~~~~~~~~~~~~\_______________________________________
*/
reg hold_ = 0, selA_ = 0, selB_ = 0;
wire selA = hold_ ? selA_ : portA_strobe; // INV #2
wire selB = hold_ ? selB_ : ~selA & portB_strobe; // INV #2
always @(posedge clk) hold_ <= res`HOLD;
always @(posedge clk) selA_ <= selA;
always @(posedge clk) selB_ <= selB;
assign req = selA ? portA_req : portB_req;
assign portA_res`RD = selA_ ? res`RD : 0; // INV #4
assign portB_res`RD = selB_ ? res`RD : 0; // INV #4
assign portA_res`HOLD = portA_strobe & (~selA | res`HOLD); // INV #3
assign portB_res`HOLD = portB_strobe & (~selB | res`HOLD); // INV #3
endmodule
// Prioritized multiplexer (port arbitration): shares a target between
// three masters
module mux3
(input wire clk,
input wire `REQ portA_req,
output wire `RES portA_res,
input wire `REQ portB_req,
output wire `RES portB_res,
input wire `REQ portC_req,
output wire `RES portC_res,
output wire `REQ req,
input wire `RES res);
parameter y = 1;
parameter m = 32;
parameter n = 32;
wire portA_strobe = portA_req`R | portA_req`W;
wire portB_strobe = portB_req`R | portB_req`W;
wire portC_strobe = portC_req`R | portC_req`W;
// Prioritized arbitration
reg hold_ = 0, selA_ = 0, selB_ = 0, selC_ = 0;
wire selA = hold_ ? selA_ : portA_strobe;
wire selB = hold_ ? selB_ : ~selA & portB_strobe;
wire selC = hold_ ? selC_ : ~selA & ~selB & portC_strobe;
always @(posedge clk) hold_ <= res`HOLD;
always @(posedge clk) selA_ <= selA;
always @(posedge clk) selB_ <= selB;
always @(posedge clk) selC_ <= selC;
assign req = selA ? portA_req :
selB ? portB_req :
/* */ portC_req ;
assign portA_res`RD = selA_ ? res`RD : 0; // INV #4
assign portB_res`RD = selB_ ? res`RD : 0; // INV #4
assign portC_res`RD = selC_ ? res`RD : 0; // INV #4
assign portA_res`HOLD = portA_strobe & (~selA | res`HOLD); // INV #3
assign portB_res`HOLD = portB_strobe & (~selB | res`HOLD); // INV #3
assign portC_res`HOLD = portC_strobe & (~selC | res`HOLD); // INV #3
/*
always @(posedge clk)
if (y == 1) begin
$display("%5d T%1d: hold %1d A%1d%1d%1d B%1d%1d%1d C%1d%1d%1d",
$time, y,
res`HOLD,
portA_strobe, selA, portA_res`HOLD,
portB_strobe, selB, portB_res`HOLD,
portC_strobe, selC, portC_res`HOLD);
if (portA_strobe + portB_strobe + portC_strobe > 1)
$display("CONGESTION!!");
end
*/
endmodule
// Full crossbar
module xbar2x2
(input wire clk,
input wire portM1selT1,
input wire `REQ portM1_req,
output wire `RES portM1_res,
input wire portM2selT1,
input wire `REQ portM2_req,
output wire `RES portM2_res,
output wire `REQ portT1_req,
input wire `RES portT1_res,
output wire `REQ portT2_req,
input wire `RES portT2_res);
parameter m = 32;
parameter n = 32;
wire `REQ portM1T1_req, portM1T2_req, portM2T1_req, portM2T2_req;
wire `RES portM1T1_res, portM1T2_res, portM2T1_res, portM2T2_res;
/* 1000 words:
M1 M2
___|___ ___|___
| | | |
| DEMUX | | DEMUX |
|_______| |_______|
| \T2 / |
| M1\ / |
M1|T1 \/ |
| /\ M2|T2
| M2/ \ |
|____ /T1 \ ____|
| | | |
| MUX | | MUX |
|_______| |_______|
| |
T1 T2
*/
demux2 demux2_M1(clk,
portM1selT1, portM1_req, portM1_res,
portM1T1_req, portM1T1_res,
portM1T2_req, portM1T2_res);
demux2 demux2_M2(clk,
portM2selT1, portM2_req, portM2_res,
portM2T1_req, portM2T1_res,
portM2T2_req, portM2T2_res);
mux2 mux2_T1(clk,
portM1T1_req, portM1T1_res,
portM2T1_req, portM2T1_res,
portT1_req, portT1_res);
mux2 mux2_T2(clk,
portM1T2_req, portM1T2_res,
portM2T2_req, portM2T2_res,
portT2_req, portT2_res);
`ifdef SIMULATE_MAIN
pipechecker check1("xbar M1", clk, portM1_req, portM1_res);
pipechecker check2("xbar M2", clk, portM2_req, portM2_res);
pipechecker check3("xbar T1", clk, portT1_req, portT1_res);
pipechecker check4("xbar T2", clk, portT2_req, portT2_res);
`endif
endmodule
// Full crossbar
module xbar3x2(clk,
portM1selT1, portM1_req, portM1_res,
portM2selT1, portM2_req, portM2_res,
portM3selT1, portM3_req, portM3_res,
portT1_req, portT1_res,
portT2_req, portT2_res);
parameter m = 32;
parameter n = 32;
input wire clk;
input wire portM1selT1;
input wire `REQ portM1_req;
output wire `RES portM1_res;
input wire portM2selT1;
input wire `REQ portM2_req;
output wire `RES portM2_res;
input wire portM3selT1;
input wire `REQ portM3_req;
output wire `RES portM3_res;
output wire `REQ portT1_req;
input wire `RES portT1_res;
output wire `REQ portT2_req;
input wire `RES portT2_res;
wire `REQ portM1T1_req;
wire `RES portM1T1_res;
wire `REQ portM1T2_req;
wire `RES portM1T2_res;
wire `REQ portM2T1_req;
wire `RES portM2T1_res;
wire `REQ portM2T2_req;
wire `RES portM2T2_res;
wire `REQ portM3T1_req;
wire `RES portM3T1_res;
wire `REQ portM3T2_req;
wire `RES portM3T2_res;
/* 1000 words:
M1 M2
___|___ ___|___
| | | |
| DEMUX | | DEMUX |
|_______| |_______|
| \T2 / |
| M1\ / |
M1|T1 \/ |
| /\ M2|T2
| M2/ \ |
|____ /T1 \ ____|
| | | |
| MUX | | MUX |
|_______| |_______|
| |
T1 T2
*/
demux2 demux2_M1(clk,
portM1selT1, portM1_req, portM1_res,
portM1T1_req, portM1T1_res,
portM1T2_req, portM1T2_res);
demux2 demux2_M2(clk,
portM2selT1, portM2_req, portM2_res,
portM2T1_req, portM2T1_res,
portM2T2_req, portM2T2_res);
demux2 demux2_M3(clk,
portM3selT1, portM3_req, portM3_res,
portM3T1_req, portM3T1_res,
portM3T2_req, portM3T2_res);
mux3 #(1) mux3_T1(clk,
portM1T1_req, portM1T1_res,
portM2T1_req, portM2T1_res,
portM3T1_req, portM3T1_res,
portT1_req, portT1_res);
mux3 #(2) mux3_T2(clk,
portM1T2_req, portM1T2_res,
portM2T2_req, portM2T2_res,
portM3T2_req, portM3T2_res,
portT2_req, portT2_res);
`ifdef SIMULATE_MAIN
pipechecker check1("xbar M1", clk, portM1_req, portM1_res);
pipechecker check2("xbar M2", clk, portM2_req, portM2_res);
pipechecker check3("xbar M3", clk, portM3_req, portM3_res);
pipechecker check4("xbar T1", clk, portT1_req, portT1_res);
pipechecker check5("xbar T2", clk, portT2_req, portT2_res);
`endif
endmodule
/*
* Scarily huge mostly combinatorial function
*/
/*
* XXX This is most likely a very expensive and slow way to implement
* to full crossbar. I know this. Before starting to micro-optimize
* this, I'll first reevaluated pipeconnect as an interconnect
* structure. One interesting direction is to optimize for bursts and
* multiplex the data and address bus. Sort of like a dramatically
* simplified Hypertransport. Of course this increases latency (in
* cycles), but should means lower logic and routing usage and a short
* worst case path (that is, lower cycle time). Increasing latency at
* the expense of bandwidth is reasonable if and only if we have at
* the minimum an instruction cache. Now the major traffic becomes
* multi-word cache refill, so burst traffic becomes important.
*
* In summery the goals are:
* 0) optimize for burst traffic (amortizing the overhead)
* => multiplexing data, commands, and addresses
* 1) lowering the overhead of the interconnect structure itself
* => VERY simple implementation
* => multiplexing data, commands, and addresses
* => registering paths => higher latency
* 2) generalizing to multiple outstanding transactions
* => tagging the payload with the return address (Q: automatic?)
* => the receiver may cause the sender to wait
* Q: after the fact (hold the previous value) or before the
* fact (not-ready for input)?
* 3) allowing for the receiver to be not ready
* already implied by 2)
*
* The basic structure is the peer-to-peer tunnel for sending data
* from a sender to a receiver. The sender sees a payload bus, a
* strobe, and a hold (hello again). The contract being that while
* hold is active, the payload and the strobe must be held constant.
* The payload arrives at the receiver after a tunnel specific delay,
* which can be within the same cycle.
*
* The payload can contain anything, but for the routing elements to
* ensure atomicity of burst transfers, we dedicate a bit to indicate
* the first element of a burst. It's easy to ... procrastinate.
* Back to the Xbar.
*
*/
module xbar3x3(input wire clk
,input wire portM1selT1
,input wire portM1selT2
,input wire `REQ portM1_req
,output wire `RES portM1_res
,input wire portM2selT1
,input wire portM2selT2
,input wire `REQ portM2_req
,output wire `RES portM2_res
,input wire portM3selT1
,input wire portM3selT2
,input wire `REQ portM3_req
,output wire `RES portM3_res
,output wire `REQ portT1_req
,input wire `RES portT1_res
,output wire `REQ portT2_req
,input wire `RES portT2_res
,output wire `REQ portT3_req
,input wire `RES portT3_res
);
wire `REQ portM1T1_req, portM1T2_req, portM1T3_req, portM2T1_req,
portM2T2_req, portM2T3_req, portM3T1_req, portM3T2_req, portM3T3_req;
wire `RES portM1T1_res, portM1T2_res, portM1T3_res, portM2T1_res,
portM2T2_res, portM2T3_res, portM3T1_res, portM3T2_res, portM3T3_res;
demux3 demux3_M1(clk,
portM1selT1, portM1selT2, portM1_req, portM1_res,
portM1T1_req, portM1T1_res,
portM1T2_req, portM1T2_res,
portM1T3_req, portM1T3_res);
demux3 demux3_M2(clk,
portM2selT1, portM2selT2, portM2_req, portM2_res,
portM2T1_req, portM2T1_res,
portM2T2_req, portM2T2_res,
portM2T3_req, portM2T3_res);
demux3 demux3_M3(clk,
portM3selT1, portM3selT2, portM3_req, portM3_res,
portM3T1_req, portM3T1_res,
portM3T2_req, portM3T2_res,
portM3T3_req, portM3T3_res);
mux3 #(1) mux3_T1(clk,
portM1T1_req, portM1T1_res,
portM2T1_req, portM2T1_res,
portM3T1_req, portM3T1_res,
portT1_req, portT1_res);
mux3 #(2) mux3_T2(clk,
portM1T2_req, portM1T2_res,
portM2T2_req, portM2T2_res,
portM3T2_req, portM3T2_res,
portT2_req, portT2_res);
mux3 #(3) mux3_T3(clk,
portM1T3_req, portM1T3_res,
portM2T3_req, portM2T3_res,
portM3T3_req, portM3T3_res,
portT3_req, portT3_res);
`ifdef SIMULATE_MAIN
pipechecker check1("xbar M1", clk, portM1_req, portM1_res);
pipechecker check2("xbar M2", clk, portM2_req, portM2_res);
pipechecker check3("xbar M3", clk, portM3_req, portM3_res);
pipechecker check4("xbar T1", clk, portT1_req, portT1_res);
pipechecker check5("xbar T2", clk, portT2_req, portT2_res);
pipechecker check6("xbar T3", clk, portT3_req, portT3_res);
`endif
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@brief Driver for a Solomon SSD1306 OLED controller
*/
module SSD1306 #(
parameter INTERFACE = "SPI" //this is the only supported interface for now
) (
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System-wide stuff
input wire clk, //Core and interface clock
input wire[15:0] clkdiv, //SPI clock divisor
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// To display
//System control signals
output reg rst_out_n = 0, //Reset output to display
output reg vbat_en_n = 1, //Power rail enables
output reg vdd_en_n = 1,
//SPI
output wire spi_sck, //4-wire SPI bus to display (MISO not used by this core)
output wire spi_mosi,
output reg spi_cs_n = 1,
//Misc data lines
output reg cmd_n = 0, //SPI command/data flag
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// To GPU
//Command inputs
input wire powerup, //Request to turn the display on
input wire powerdown, //Request to turn the display off
input wire refresh, //Request to refresh the display from the GPU framebuffer
//Status outputs
output wire ready, //1 = ready for new commands, 0 = busy
//All commands except "power down" are ignored when not ready.
//Power down is queued if needed.
output reg framebuffer_rd_en = 0, //Framebuffer SRAM read bus (expects single cycle latency)
output reg[8:0] framebuffer_rd_addr = 0,
input wire[7:0] framebuffer_rd_data,
output reg power_state = 0 //1=on, 0=off
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Sanity check
initial begin
if(INTERFACE != "SPI") begin
$display("ERROR: SSD1306 only supports INTERFACE=SPI for now");
$finish;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI interface
reg spi_shift_en = 0;
wire spi_shift_done;
reg[7:0] spi_tx_data = 0;
SPITransceiver #(
.SAMPLE_EDGE("RISING"),
.LOCAL_EDGE("NORMAL")
) spi_tx (
.clk(clk),
.clkdiv(clkdiv),
.spi_sck(spi_sck),
.spi_mosi(spi_mosi),
.spi_miso(1'b0), //read not hooked up
.shift_en(spi_shift_en),
.shift_done(spi_shift_done),
.tx_data(spi_tx_data),
.rx_data()
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI chip select control wrapper
reg spi_byte_en = 0;
reg[2:0] spi_byte_state = 0;
reg[2:0] spi_byte_count = 0;
reg spi_byte_done = 0;
//SPI state machine
always @(posedge clk) begin
spi_shift_en <= 0;
spi_byte_done <= 0;
case(spi_byte_state)
//Wait for command request, then assert CS
0: begin
if(spi_byte_en) begin
spi_cs_n <= 0;
spi_byte_state <= 1;
spi_byte_count <= 0;
end
end
//Wait 3 clocks of setup time, then initiate the transfer
1: begin
spi_byte_count <= spi_byte_count + 1'd1;
if(spi_byte_count == 2) begin
spi_shift_en <= 1;
spi_byte_state <= 2;
end
end
//Wait for transfer to finish
2: begin
if(spi_shift_done) begin
spi_byte_count <= 0;
spi_byte_state <= 3;
end
end
//Wait 3 clocks of hold time, then deassert CS
3: begin
spi_byte_count <= spi_byte_count + 1'd1;
if(spi_byte_count == 2) begin
spi_cs_n <= 1;
spi_byte_state <= 4;
spi_byte_count <= 0;
end
end
//Wait 3 clocks of inter-frame gap, then return
4: begin
spi_byte_count <= spi_byte_count + 1'd1;
if(spi_byte_count == 2) begin
spi_byte_done <= 1;
spi_byte_state <= 0;
end
end
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Framebuffer rotation
/*
Our framebuffer is stored in scanline order (as is common for pretty much all standard image file formats)
The display wants us to output data in 8-pixel vertical slices so we have to rotate the bit ordering
within each 8x8 block.
To read a new block of data, assert block_read and wait for block_ready to go high
*/
reg block_read = 0;
reg block_ready = 0;
reg[3:0] block_col = 0;
reg[2:0] block_row = 0;
//pixel_column[0] is scanline 0 of the block
//just a raw array of FFs for transposing
reg[7:0] pixel_column0 = 8'h80;
reg[7:0] pixel_column1 = 8'h00;
reg[7:0] pixel_column2 = 8'h00;
reg[7:0] pixel_column3 = 8'h00;
reg[7:0] pixel_column4 = 8'h00;
reg[7:0] pixel_column5 = 8'h00;
reg[7:0] pixel_column6 = 8'h00;
reg[7:0] pixel_column7 = 8'h00;
reg framebuffer_rd_en_ff = 0;
reg[2:0] block_scanline = 0;
wire[2:0] next_scanline = block_scanline + 1'h1;
wire more_scanlines = (block_scanline != 7);
/*
Address map: blocks go L-R then raster scan (16 blocks wide x 4 high, or 8 for a 64-pixel display)
Each block is 1 byte wide x 8 scanlines high
addr[8:7] = row (9:7 for 64-line displays)
addr[6:4] = scanline
addr[3:0] = col
*/
always @(posedge clk) begin
//clear flags
framebuffer_rd_en <= 0;
block_ready <= 0;
//one cycle after we dispatched a read, data is available
framebuffer_rd_en_ff <= framebuffer_rd_en;
//Start reading the first scanline of a new block
if(block_read)
block_scanline <= 0;
//Reading a new scanline if we're starting a block, or not done with current one
framebuffer_rd_addr[8:7] <= block_row[1:0];
framebuffer_rd_addr[3:0] <= block_col + 4'h1; //what is this offset from?
if(block_read) begin
framebuffer_rd_addr[6:4] <= 0;
framebuffer_rd_en <= 1;
end
if(framebuffer_rd_en_ff && more_scanlines) begin
framebuffer_rd_addr[6:4] <= next_scanline;
framebuffer_rd_en <= 1;
end
//Bump row pointer if there's more stuff to read
if(framebuffer_rd_en_ff && more_scanlines)
block_scanline <= next_scanline;
//Save completed scanlines in the buffer
//MSB in is lowest column number
//MSB out is highest row number
if(framebuffer_rd_en_ff) begin
pixel_column0 <= {framebuffer_rd_data[0], pixel_column0[7:1]};
pixel_column1 <= {framebuffer_rd_data[1], pixel_column1[7:1]};
pixel_column2 <= {framebuffer_rd_data[2], pixel_column2[7:1]};
pixel_column3 <= {framebuffer_rd_data[3], pixel_column3[7:1]};
pixel_column4 <= {framebuffer_rd_data[4], pixel_column4[7:1]};
pixel_column5 <= {framebuffer_rd_data[5], pixel_column5[7:1]};
pixel_column6 <= {framebuffer_rd_data[6], pixel_column6[7:1]};
pixel_column7 <= {framebuffer_rd_data[7], pixel_column7[7:1]};
end
//Done with the block? Let the display controller know
if(framebuffer_rd_en_ff && !more_scanlines)
block_ready <= 1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Main state machine
localparam STATE_OFF = 8'h00;
localparam STATE_BOOT_0 = 8'h01;
localparam STATE_BOOT_1 = 8'h02;
localparam STATE_BOOT_2 = 8'h03;
localparam STATE_BOOT_3 = 8'h04;
localparam STATE_BOOT_4 = 8'h05;
localparam STATE_BOOT_5 = 8'h06;
localparam STATE_WAIT_IDLE = 8'h07;
localparam STATE_IDLE = 8'h08;
localparam STATE_SHUTDOWN_0 = 8'h09;
localparam STATE_SHUTDOWN_1 = 8'h0a;
localparam STATE_SHUTDOWN_2 = 8'h0b;
localparam STATE_REFRESH_0 = 8'h0c;
localparam STATE_REFRESH_1 = 8'h0d;
localparam STATE_REFRESH_2 = 8'h0e;
localparam STATE_REFRESH_3 = 8'h0f;
localparam STATE_REFRESH_4 = 8'h10;
reg[7:0] state = 0;
reg[23:0] count = 0;
reg[2:0] block_nbit = 0;
reg powerdown_pending = 0;
assign ready = (state == STATE_IDLE) || (state == STATE_OFF);
//Microcode table of init commands
//TODO: some of this is panel specific, have a parameter to specify various configs?
reg[3:0] init_rom_addr = 0;
reg[7:0] init_rom[15:0];
initial begin
init_rom[0] <= 8'hae; //Turn display off
init_rom[1] <= 8'h8d; //Set up charge pump for internal DC-DC
init_rom[2] <= 8'h14;
init_rom[3] <= 8'hd9; //Set pre-charge period for internal DC-DCs
init_rom[4] <= 8'hf1;
init_rom[5] <= 8'ha1; //Segment re-mapping
init_rom[6] <= 8'hc8; //COM scan direction
init_rom[7] <= 8'hda; //COM hardware config. Note that panel docs say 0x02 which is wrong!
init_rom[8] <= 8'h20;
init_rom[9] <= 8'h2e; //Disable scrolling
init_rom[10] <= 8'haf; //Turn on display
init_rom[11] <= 8'he3; //nop padding for future init commands
init_rom[12] <= 8'he3;
init_rom[13] <= 8'he3;
init_rom[14] <= 8'he3;
init_rom[15] <= 8'he3;
end
wire[7:0] init_rom_cmd = init_rom[init_rom_addr];
always @(posedge clk) begin
spi_byte_en <= 0;
block_read <= 0;
if(powerdown)
powerdown_pending <= 1;
//Decrement counter if nonzero
if(count != 0)
count <= count - 1'h1;
//Bump microcode pointer after sending stuff during boot
if(spi_byte_en && (state <= STATE_BOOT_5) )
init_rom_addr <= init_rom_addr + 1'h1;
case(state)
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// OFF
STATE_OFF: begin
//Get ready to read the first ROM command
init_rom_addr <= 0;
//We're off
power_state <= 0;
//Prepare to send commands
cmd_n <= 0;
if(powerup) begin
vdd_en_n <= 0;
count <= 24'h01ffff;
state <= STATE_BOOT_0;
end
end //end STATE_OFF
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// BOOT: power etc initialization
//Give power rails ~1 ms to stabilize, then turn the display off
STATE_BOOT_0: begin
if(count == 0) begin
spi_tx_data <= init_rom_cmd;
spi_byte_en <= 1;
state <= STATE_BOOT_1;
end
end //end STATE_BOOT_0
//Wait for command to finish, then strobe reset for ~1 ms
STATE_BOOT_1: begin
if(spi_byte_done) begin
rst_out_n <= 0;
count <= 24'h01ffff;
state <= STATE_BOOT_2;
end
end //end STATE_BOOT_1
//When reset finishes, send the first init command
STATE_BOOT_2: begin
if(count == 0) begin
rst_out_n <= 1;
spi_tx_data <= init_rom_cmd;
spi_byte_en <= 1;
state <= STATE_BOOT_3;
end
end //end STATE_BOOT_2
//Send remaining init commands
STATE_BOOT_3: begin
if(spi_byte_done) begin
spi_tx_data <= init_rom_cmd;
spi_byte_en <= 1;
//If we have more commands, stay here.
//If we just sent the last command, move on.
if(init_rom_addr == 'd10)
state <= STATE_BOOT_4;
end
end //end STATE_BOOT_3
//When the last send finishes, turn on Vbat
STATE_BOOT_4: begin
if(spi_byte_done) begin
vbat_en_n <= 0;
count <= 24'hbfffff;
state <= STATE_BOOT_5;
end
end //end STATE_BOOT_4
//Wait 100 ms then go to idle
STATE_BOOT_5: begin
if(count == 0)
state <= STATE_IDLE;
end //end STATE_BOOT_5
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// WAIT: go to idle after current txn finishes
STATE_WAIT_IDLE: begin
if(spi_byte_done)
state <= STATE_IDLE;
end //end STATE_WAIT_IDLE
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// IDLE: Wait for something to happen
STATE_IDLE: begin
//We're currently turned on and running
power_state <= 1;
//If we were asked to shut down, do that
if(powerdown_pending) begin
powerdown_pending <= 0;
state <= STATE_SHUTDOWN_0;
//Read the "shutdown" command
init_rom_addr <= 0;
end
//If asked to refresh the display, do that
else if(refresh) begin
block_row <= 0;
block_col <= 0;
//Send a nop b/c REFRESH_0 expects to wait for a tx.
//init_rom_addr should always be 'd11 when in IDLE
spi_tx_data <= init_rom_cmd;
spi_byte_en <= 1;
cmd_n <= 0;
state <= STATE_REFRESH_0;
end
end //end STATE_IDLE
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// REFRESH: Update the display
//Block-based raster scan: 8 pixels high left to right, then next block
//Each byte is one pixel wide and 8 high.
//Send row pointer
STATE_REFRESH_0: begin
if(spi_byte_done) begin
spi_tx_data <= {4'hB, 1'b0, block_row};
spi_byte_en <= 1;
cmd_n <= 0;
state <= STATE_REFRESH_1;
end
end //end STATE_REFRESH_0
//Col addr low = 0
STATE_REFRESH_1: begin
if(spi_byte_done) begin
spi_tx_data <= {4'h0, block_col[0], 3'h0};
spi_byte_en <= 1;
cmd_n <= 0;
state <= STATE_REFRESH_2;
end
end //end STATE_REFRESH_1
//Col addr high = 0
STATE_REFRESH_2: begin
if(spi_byte_done) begin
spi_tx_data <= {5'h1, block_col[3:1]};
spi_byte_en <= 1;
cmd_n <= 0;
state <= STATE_REFRESH_3;
block_col <= 0;
end
end //end STATE_REFRESH_2
//Fetch the next block of data
STATE_REFRESH_3: begin
if(spi_byte_done) begin
block_read <= 1;
block_nbit <= 0;
state <= STATE_REFRESH_4;
end
end //end STATE_REFRESH_3
//When the block comes back, start sending it out
STATE_REFRESH_4: begin
if(block_ready || spi_byte_done) begin
//Send the byte
case(block_nbit)
0: spi_tx_data <= pixel_column0;
1: spi_tx_data <= pixel_column1;
2: spi_tx_data <= pixel_column2;
3: spi_tx_data <= pixel_column3;
4: spi_tx_data <= pixel_column4;
5: spi_tx_data <= pixel_column5;
6: spi_tx_data <= pixel_column6;
7: spi_tx_data <= pixel_column7;
endcase
spi_byte_en <= 1;
cmd_n <= 1;
//Go to next bitplane in the block
block_nbit <= block_nbit + 1'h1;
//If done with this block, move to the next one in the row
if(block_nbit == 7) begin
//Default to fetching the next block from the current row
block_nbit <= 0;
state <= STATE_REFRESH_3;
//If done with this column, move to next row
if(block_col == 15) begin
block_col <= 0;
block_row <= block_row + 1'h1;
state <= STATE_REFRESH_0;
//If done with the last row, finish
if(block_row == 3)
state <= STATE_WAIT_IDLE;
end
//Nope, just go to next block position
else
block_col <= block_col + 1'h1;
end
end
end //end STATE_REFRESH_4
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SHUTDOWN: turn the display off
//Send "display off" command
STATE_SHUTDOWN_0: begin
spi_tx_data <= init_rom_cmd;
spi_byte_en <= 1;
cmd_n <= 0;
state <= STATE_SHUTDOWN_1;
end //end STATE_SHUTDOWN_0
//When send finishes, turn off Vbat
STATE_SHUTDOWN_1: begin
if(spi_byte_done) begin
vbat_en_n <= 1;
count <= 24'hbfffff;
state <= STATE_SHUTDOWN_2;
end
end //end STATE_SHUTDOWN_1
//Wait 100ms then turn off Vdd and reset
STATE_SHUTDOWN_2: begin
if(count == 0) begin
vdd_en_n <= 1;
state <= STATE_OFF;
end
end //end STATE_SHUTDOWN_2
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_2_V
`define SKY130_FD_SC_LP__O22A_2_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22a_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_1_V
`define SKY130_FD_SC_LP__BUSRECEIVER_1_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog wrapper for busreceiver with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busreceiver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_1_V
|
// -----------------------------------------------------------------------------
// FILE NAME : Wu_Manber_com.v
// DEPARTMENT : Computer Engineering
// AUTHOR : Ashik Poojari
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2016-09-18 Ashik Poojari
// -----------------------------------------------------------------------------
// KEYWORDS : General file searching keywords, leave blank if none.
// -----------------------------------------------------------------------------
// PURPOSE : Short description of functionality
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
// e.g.DATA_WIDTH [32,16] : width of the data : 32 :
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Asynchronous
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Scan Methodology :
// Instantiations :
// Synthesizable (y/n) : y
// Other :
// -FHDR------------------------------------------------------------------------
`timescale 1ns/1ns
module compare #(parameter MSG_WIDTH=4, B=3, PATTERN_WIDTH=14,SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1)+1,NOS_KEY=4) //w is the width which is the B in Wu Manber Algorithm
( input clk,
input reset,
input compare_enable,
input [MSG_WIDTH*PATTERN_WIDTH-1:0] data_in,
input [MSG_WIDTH*PATTERN_WIDTH*NOS_KEY-1:0] patterns,
output reg [SHIFT_WIDTH-1:0] shift_amount,
output reg complete_match);
localparam nos_shifters = PATTERN_WIDTH -B+1;
wire [nos_shifters-1:1] compare_data, compare_data_tmp, priority_cmp;
wire [MSG_WIDTH*B-1:0] pattern_comb [nos_shifters-1:1];
wire [SHIFT_WIDTH:0] shift_amount_wire;
wire partial_match_wire,complete_match_wire;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] pattern;
reg [$clog2(NOS_KEY)-1:0] sel;
//reg count;
generate
genvar i;
for(i=1;i<nos_shifters;i=i+1)
begin: compare
assign compare_data_tmp[i] = ~(| (data_in[MSG_WIDTH*B-1:0] ^ pattern_comb[i]));
end
endgenerate
generate
genvar j;
for(j=1;j<nos_shifters;j=j+1)
begin: shifter_mux
assign pattern_comb[j] = pattern[MSG_WIDTH*(j+B)-1:MSG_WIDTH*j];
end
endgenerate
generate
genvar n;
for(n=1;n<nos_shifters;n=n+1)
begin: shifters
if(n==1) begin
assign priority_cmp[n]=1;
assign compare_data[n] = priority_cmp[n] & compare_data_tmp[n];
end
else begin
assign priority_cmp[n] = ~(|(compare_data_tmp[n-1:1]));
assign compare_data[n] = priority_cmp[n] & compare_data_tmp[n];
end
assign shift_amount_wire = compare_data[n] ? n: {SHIFT_WIDTH+1{1'bz}};
end
endgenerate
assign partial_match_wire = |(compare_data);
assign complete_match_wire = ~(|(pattern ^ data_in));
always@(posedge clk)
begin
complete_match <= complete_match_wire;
if(reset) begin
shift_amount <= 0;
sel <= 0;
// count <=0;
end
else begin
if(partial_match_wire == 1) begin
shift_amount <= shift_amount_wire;
end
else begin
shift_amount <= PATTERN_WIDTH-B+1;
end
if(compare_enable ) begin
sel <= sel + 1;
end
// if(compare_enable) begin
// count<= count+1;
// end
end
end
generate
genvar k;
for (k=0; k<NOS_KEY; k=k+1)
begin: patter
assign pattern = (sel == k) ? patterns[PATTERN_WIDTH*(k+1)*MSG_WIDTH-1: (PATTERN_WIDTH*k)*MSG_WIDTH] : {MSG_WIDTH*PATTERN_WIDTH{1'bz}};
end
endgenerate
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:09:13 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_rst_ps7_0_100M_1 -prefix
// zqynq_lab_1_design_rst_ps7_0_100M_1_ zqynq_lab_1_design_rst_ps7_0_100M_0_stub.v
// Design : zqynq_lab_1_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module zqynq_lab_1_design_rst_ps7_0_100M_1(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_1_V
`define SKY130_FD_SC_HDLL__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_1_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Set the clock signal, and its frequency
*
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/*
* Clock frequency is arbitrarily chosen
* Period = 10 ns, frequency = 100MHz
*/
#5 ck = 0;
#5 ck = 1;
end
/**
* Instantiate an instance of a convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
bin = 1'b0;
rset=0;
// @ t=3,
#3;
bin = 1'b1;
rset=0;
// @ t=10,
#7;
bin = 1'b0;
rset=0;
// @ t=19,
#9;
bin = 1'b1;
rset=0;
// @ t=29,
#10;
bin = 1'b0;
rset=0;
// @ t=39,
#10;
bin = 1'b1;
rset=0;
// @ t=50-1,
#10;
bin = 1'b0;
rset=0;
// @ t=60-1,
#10;
bin = 1'b1;
rset=0;
// @ t=70-1,
#10;
bin = 1'b0;
rset=0;
// @ t=80-1,
#10;
bin = 1'b0;
rset=0;
// @ t=90-1,
#10;
bin = 1'b1;
rset=0;
// @ t=100-1,
#10;
bin = 1'b1;
rset=1;
// @ t=110-1,
#9;
bin = 1'b0;
rset=0;
// @ t=120-1,
#10;
bin = 1'b1;
rset=0;
// @ t=130-1,
#10;
bin = 1'b0;
rset=0;
// @ t=140-1,
#10;
bin = 1'b1;
rset=1;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_1_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_1_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog wrapper for tapvpwrvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvpwrvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tapvpwrvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_1_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module title1 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("title1.mif"),
.C_INIT_FILE("title1.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(13104),
.C_READ_DEPTH_A(13104),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(13104),
.C_READ_DEPTH_B(13104),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("2"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.153268 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/20/2016 09:26:23 PM
// Design Name:
// Module Name: dstMgmt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef CARPOOL_LK_AHEAD_RC_PS
`define DST_MGMT
`endif
`ifdef CARPOOL
`define DST_MGMT
`endif
`ifdef DST_MGMT
module dstMgmt(
allocPV,
dstList_in,
dstList_out
);
input [`NUM_PORT-1:0] allocPV;
input [`DST_LIST_WIDTH-1:0] dstList_in;
output [`DST_LIST_WIDTH-1:0] dstList_out;
parameter OUTDIR = 0;
wire [`DST_LIST_WIDTH-1:0] mask_out_port;
wire replica;
wire [`NUM_PORT-1:0] w_replica;
wire [`NUM_PORT-1:0] first;
assign w_replica[0] = 1'b0;
assign first[0] = 1'b1;
//assign forked[0] = 1'b0;
genvar i;
generate
for (i=0; i<`NUM_PORT-1; i=i+1) begin: flit_is_replica
// determine if the flit is a replica
// the flit on the first allocated port is not a replica
assign first [i+1] = first [i] ? ~allocPV[i] : 1'b0;
assign w_replica[i+1] = first [i+1] ? 1'b0 : (w_replica [i] || allocPV[i]);
end
endgenerate
assign replica = w_replica[OUTDIR];
// construct the mask for mc flit
assign mask_out_port =~((w_replica[0] ? `N_MASK : 'h0) |
(w_replica[1] ? `E_MASK : 'h0) |
(w_replica[2] ? `S_MASK : 'h0) |
(w_replica[3] ? `W_MASK : 'h0) |
(w_replica[4] ? `L_MASK : 'h0));
if (OUTDIR == 0)
assign dstList_out = dstList_in & (replica ? `N_MASK : mask_out_port);
else if (OUTDIR == 1)
assign dstList_out = dstList_in & (replica ? `E_MASK : mask_out_port);
else if (OUTDIR == 2)
assign dstList_out = dstList_in & (replica ? `S_MASK : mask_out_port);
else if (OUTDIR == 3)
assign dstList_out = dstList_in & (replica ? `W_MASK : mask_out_port);
endmodule
`endif // DST_MGMT |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv5sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFNToRaw_preMul#(
parameter expWidth = 3, parameter sigWidth = 3, parameter imulEn = 1
) (
control,
op,
a,
b,
c,
roundingMode,
mulAddA,
mulAddB,
mulAddC,
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC
);
`include "HardFloat_localFuncs.vi"
input [(`floatControlWidth - 1):0] control;
input [2:0] op;
input [(expWidth + sigWidth):0] a;
input [(expWidth + sigWidth):0] b;
input [(expWidth + sigWidth):0] c;
input [2:0] roundingMode;
output [(sigWidth - 1):0] mulAddA;
output [(sigWidth - 1):0] mulAddB;
output [(sigWidth*2 - 1):0] mulAddC;
output [5:0] intermed_compactState;
output signed [(expWidth + 1):0] intermed_sExp;
output [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
output [(sigWidth + 1):0] intermed_highAlignedSigC;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam prodWidth = sigWidth*2;
localparam sigSumWidth = sigWidth + prodWidth + 3;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
wire isNaNC, isInfC, isZeroC, signC;
wire signed [(expWidth + 1):0] sExpC;
wire [sigWidth:0] sigC;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_c(c, isNaNC, isInfC, isZeroC, signC, sExpC, sigC);
wire isSigNaNC;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_c(c, isSigNaNC);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signProd = signA ^ signB ^ op[1];
wire signed [(expWidth + 2):0] sExpAlignedProd =
sExpA + sExpB + (-(1<<expWidth) + sigWidth + 3);
wire doSubMags = signProd ^ signC ^ op[0];
wire opSignC = signProd ^ doSubMags;
wire roundingMode_min = (roundingMode == `round_min);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [(expWidth + 2):0] sNatCAlignDist = sExpAlignedProd - sExpC;
wire [(expWidth + 1):0] posNatCAlignDist =
sNatCAlignDist[(expWidth + 1):0];
wire isMinCAlign = isZeroA || isZeroB || (sNatCAlignDist < 0);
wire CIsDominant =
!isZeroC && (isMinCAlign || (posNatCAlignDist <= sigWidth));
wire signed [(expWidth + 1):0] sExpSum =
CIsDominant ? sExpC : sExpAlignedProd - sigWidth;
wire [(clog2(sigSumWidth) - 1):0] CAlignDist =
isMinCAlign ? 0
: (posNatCAlignDist < sigSumWidth - 1)
? posNatCAlignDist[(clog2(sigSumWidth) - 1):0]
: sigSumWidth - 1;
wire signed [(sigSumWidth + 2):0] extComplSigC =
{doSubMags ? ~sigC : sigC, {(sigSumWidth - sigWidth + 2){doSubMags}}};
wire [(sigSumWidth + 1):0] mainAlignedSigC = extComplSigC>>>CAlignDist;
localparam CGrainAlign = (sigSumWidth - sigWidth - 1) & 3;
wire [(sigWidth + CGrainAlign):0] grainAlignedSigC = sigC<<CGrainAlign;
wire [(sigWidth + CGrainAlign)/4:0] reduced4SigC;
compressBy4#(sigWidth + 1 + CGrainAlign)
compressBy4_sigC(grainAlignedSigC, reduced4SigC);
localparam CExtraMaskHiBound = (sigSumWidth - 1)/4;
localparam CExtraMaskLoBound = (sigSumWidth - sigWidth - 1)/4;
wire [(CExtraMaskHiBound - CExtraMaskLoBound - 1):0] CExtraMask;
lowMaskHiLo#(clog2(sigSumWidth) - 2, CExtraMaskHiBound, CExtraMaskLoBound)
lowMask_CExtraMask(CAlignDist[(clog2(sigSumWidth) - 1):2], CExtraMask);
wire reduced4CExtra = |(reduced4SigC & CExtraMask);
wire [(sigSumWidth - 1):0] alignedSigC =
{mainAlignedSigC>>3,
doSubMags ? (&mainAlignedSigC[2:0]) && !reduced4CExtra
: (|mainAlignedSigC[2:0]) || reduced4CExtra};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNAOrB = isNaNA || isNaNB;
wire isNaNAny = isNaNAOrB || isNaNC;
wire isInfAOrB = isInfA || isInfB;
wire invalidProd = (isInfA && isZeroB) || (isZeroA && isInfB);
wire notSigNaN_invalidExc =
invalidProd || (!isNaNAOrB && isInfAOrB && isInfC && doSubMags);
wire invalidExc =
isSigNaNA || isSigNaNB || isSigNaNC || notSigNaN_invalidExc;
wire notNaN_addZeros = (isZeroA || isZeroB) && isZeroC;
wire specialCase = isNaNAny || isInfAOrB || isInfC || notNaN_addZeros;
wire specialNotNaN_signOut =
(isInfAOrB && signProd) || (isInfC && opSignC)
|| (notNaN_addZeros && !roundingMode_min && signProd && opSignC)
|| (notNaN_addZeros && roundingMode_min && (signProd || opSignC));
`ifdef HardFloat_propagateNaNPayloads
wire signNaN;
wire [(sigWidth - 2):0] fractNaN;
propagateFloatNaN_mulAdd#(sigWidth)
propagateNaN(
control,
op[1:0],
isNaNA,
signA,
sigA[(sigWidth - 2):0],
isNaNB,
signB,
sigB[(sigWidth - 2):0],
invalidProd,
isNaNC,
signC,
sigC[(sigWidth - 2):0],
signNaN,
fractNaN
);
wire isNaNOut = isNaNAny || notSigNaN_invalidExc;
wire special_signOut =
isNaNAny || notSigNaN_invalidExc ? signNaN : specialNotNaN_signOut;
`else
wire special_signOut = specialNotNaN_signOut;
`endif
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
if(imulEn) begin: fi1
// This part has been modified so that we can support RISC-V integer multiply instruction MUL.
// Please refer to the document for detailed implementation.
assign mulAddA = op[2] ? a[sigWidth-1:0] : sigA;
assign mulAddB = op[2] ? b[sigWidth-1:0] : sigB;
// Generate modification bits
wire [expWidth-1:0] aux_part = a[expWidth-1:0] * b[sigWidth+:expWidth] + a[sigWidth+:expWidth] * b[expWidth-1:0];
assign mulAddC = op[2] ? {{(sigWidth - expWidth){1'b0}}, aux_part, {sigWidth{1'b0}}} : alignedSigC[prodWidth:1];
end
else begin: fi2
assign mulAddA = sigA;
assign mulAddB = sigB;
assign mulAddC = alignedSigC[prodWidth:1];
end
assign intermed_compactState =
{specialCase,
invalidExc || (!specialCase && signProd ),
`ifdef HardFloat_propagateNaNPayloads
isNaNOut || (!specialCase && doSubMags ),
`else
isNaNAny || (!specialCase && doSubMags ),
`endif
isInfAOrB || isInfC || (!specialCase && CIsDominant ),
notNaN_addZeros || (!specialCase && alignedSigC[0]),
special_signOut};
assign intermed_sExp = sExpSum;
assign intermed_CDom_CAlignDist = CAlignDist[(clog2(sigWidth + 1) - 1):0];
assign intermed_highAlignedSigC =
`ifdef HardFloat_propagateNaNPayloads
isNaNOut ? fractNaN :
`endif
alignedSigC[(sigSumWidth - 1):(prodWidth + 1)];
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFNToRaw_postMul#(parameter expWidth = 3, parameter sigWidth = 3) (
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC,
mulAddResult,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
`include "HardFloat_localFuncs.vi"
input [5:0] intermed_compactState;
input signed [(expWidth + 1):0] intermed_sExp;
input [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
input [(sigWidth + 1):0] intermed_highAlignedSigC;
input [sigWidth*2:0] mulAddResult;
input [2:0] roundingMode;
output invalidExc;
output out_isNaN;
output out_isInf;
output out_isZero;
output out_sign;
output signed [(expWidth + 1):0] out_sExp;
output [(sigWidth + 2):0] out_sig;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam prodWidth = sigWidth*2;
localparam sigSumWidth = sigWidth + prodWidth + 3;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire specialCase = intermed_compactState[5];
assign invalidExc = specialCase && intermed_compactState[4];
assign out_isNaN = specialCase && intermed_compactState[3];
assign out_isInf = specialCase && intermed_compactState[2];
wire notNaN_addZeros = specialCase && intermed_compactState[1];
wire signProd = intermed_compactState[4];
wire doSubMags = intermed_compactState[3];
wire CIsDominant = intermed_compactState[2];
wire bit0AlignedSigC = intermed_compactState[1];
wire special_signOut = intermed_compactState[0];
`ifdef HardFloat_propagateNaNPayloads
wire [(sigWidth - 2):0] fractNaN = intermed_highAlignedSigC;
`endif
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire opSignC = signProd ^ doSubMags;
wire [(sigWidth + 1):0] incHighAlignedSigC = intermed_highAlignedSigC + 1;
wire [(sigSumWidth - 1):0] sigSum =
{mulAddResult[prodWidth] ? incHighAlignedSigC
: intermed_highAlignedSigC,
mulAddResult[(prodWidth - 1):0],
bit0AlignedSigC};
wire roundingMode_min = (roundingMode == `round_min);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire CDom_sign = opSignC;
wire signed [(expWidth + 1):0] CDom_sExp = intermed_sExp - doSubMags;
wire [(sigWidth*2 + 1):0] CDom_absSigSum =
doSubMags ? ~sigSum[(sigSumWidth - 1):(sigWidth + 1)]
: {1'b0, intermed_highAlignedSigC[(sigWidth + 1):sigWidth],
sigSum[(sigSumWidth - 3):(sigWidth + 2)]};
wire CDom_absSigSumExtra =
doSubMags ? !(&sigSum[sigWidth:1]) : |sigSum[(sigWidth + 1):1];
wire [(sigWidth + 4):0] CDom_mainSig =
(CDom_absSigSum<<intermed_CDom_CAlignDist)>>(sigWidth - 3);
wire [((sigWidth | 3) - 1):0] CDom_grainAlignedLowSig =
CDom_absSigSum[(sigWidth - 1):0]<<(~sigWidth & 3);
wire [sigWidth/4:0] CDom_reduced4LowSig;
compressBy4#(sigWidth | 3)
compressBy4_CDom_absSigSum(
CDom_grainAlignedLowSig, CDom_reduced4LowSig);
wire [(sigWidth/4 - 1):0] CDom_sigExtraMask;
lowMaskLoHi#(clog2(sigWidth + 1) - 2, 0, sigWidth/4)
lowMask_CDom_sigExtraMask(
intermed_CDom_CAlignDist[(clog2(sigWidth + 1) - 1):2],
CDom_sigExtraMask
);
wire CDom_reduced4SigExtra = |(CDom_reduced4LowSig & CDom_sigExtraMask);
wire [(sigWidth + 2):0] CDom_sig =
{CDom_mainSig>>3,
(|CDom_mainSig[2:0]) || CDom_reduced4SigExtra || CDom_absSigSumExtra};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notCDom_signSigSum = sigSum[prodWidth + 3];
wire [(prodWidth + 2):0] notCDom_absSigSum =
notCDom_signSigSum ? ~sigSum[(prodWidth + 2):0]
: sigSum[(prodWidth + 2):0] + doSubMags;
wire [(prodWidth + 2)/2:0] notCDom_reduced2AbsSigSum;
compressBy2#(prodWidth + 3)
compressBy2_notCDom_absSigSum(
notCDom_absSigSum, notCDom_reduced2AbsSigSum);
wire [(clog2(prodWidth + 4) - 2):0] notCDom_normDistReduced2;
countLeadingZeros#((prodWidth + 2)/2 + 1, clog2(prodWidth + 4) - 1)
countLeadingZeros_notCDom(
notCDom_reduced2AbsSigSum, notCDom_normDistReduced2);
wire [(clog2(prodWidth + 4) - 1):0] notCDom_nearNormDist =
notCDom_normDistReduced2<<1;
wire signed [(expWidth + 1):0] notCDom_sExp =
intermed_sExp - notCDom_nearNormDist;
wire [(sigWidth + 4):0] notCDom_mainSig =
({1'b0, notCDom_absSigSum}<<notCDom_nearNormDist)>>(sigWidth - 1);
wire [(((sigWidth/2 + 1) | 1) - 1):0] CDom_grainAlignedLowReduced2Sig =
notCDom_reduced2AbsSigSum[sigWidth/2:0]<<((sigWidth/2) & 1);
wire [(sigWidth + 2)/4:0] notCDom_reduced4AbsSigSum;
compressBy2#((sigWidth/2 + 1) | 1)
compressBy2_notCDom_reduced2AbsSigSum(
CDom_grainAlignedLowReduced2Sig, notCDom_reduced4AbsSigSum);
wire [((sigWidth + 2)/4 - 1):0] notCDom_sigExtraMask;
lowMaskLoHi#(clog2(prodWidth + 4) - 2, 0, (sigWidth + 2)/4)
lowMask_notCDom_sigExtraMask(
notCDom_normDistReduced2[(clog2(prodWidth + 4) - 2):1],
notCDom_sigExtraMask
);
wire notCDom_reduced4SigExtra =
|(notCDom_reduced4AbsSigSum & notCDom_sigExtraMask);
wire [(sigWidth + 2):0] notCDom_sig =
{notCDom_mainSig>>3,
(|notCDom_mainSig[2:0]) || notCDom_reduced4SigExtra};
wire notCDom_completeCancellation =
(notCDom_sig[(sigWidth + 2):(sigWidth + 1)] == 0);
wire notCDom_sign =
notCDom_completeCancellation ? roundingMode_min
: signProd ^ notCDom_signSigSum;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign out_isZero =
notNaN_addZeros || (!CIsDominant && notCDom_completeCancellation);
assign out_sign =
( specialCase && special_signOut)
|| (!specialCase && CIsDominant && CDom_sign )
|| (!specialCase && !CIsDominant && notCDom_sign );
assign out_sExp = CIsDominant ? CDom_sExp : notCDom_sExp;
`ifdef HardFloat_propagateNaNPayloads
assign out_sig =
out_isNaN ? {1'b1, fractNaN, 2'b00}
: CIsDominant ? CDom_sig : notCDom_sig;
`else
assign out_sig = CIsDominant ? CDom_sig : notCDom_sig;
`endif
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFNToRaw#(
parameter expWidth = 3,
parameter sigWidth = 3,
parameter imulEn = 1'b1 // set 1 to enable integer MUL.
) (
input [(`floatControlWidth - 1):0] control,
// by set op[2] to 1, we can reuse this module to execute RISC-V integer multiply instruction MUL.
input [2:0] op,
// Note that for both signed and unsigned multiply, the results are the same, because we truncate the sign extension when evaluating the lower part.
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [(expWidth + sigWidth):0] c,
input [2:0] roundingMode,
output invalidExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth + 2):0] out_sig,
// The output port of integer multiply.
output [expWidth + sigWidth-1:0] out_imul
);
`include "HardFloat_localFuncs.vi"
wire [(sigWidth - 1):0] mulAddA, mulAddB;
wire [(sigWidth*2 - 1):0] mulAddC;
wire [5:0] intermed_compactState;
wire signed [(expWidth + 1):0] intermed_sExp;
wire [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
wire [(sigWidth + 1):0] intermed_highAlignedSigC;
mulAddRecFNToRaw_preMul#(expWidth, sigWidth, imulEn)
mulAddToRaw_preMul(
control,
op,
a,
b,
c,
roundingMode,
mulAddA,
mulAddB,
mulAddC,
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC
);
// MAC
wire [sigWidth*2:0] mulAddResult = mulAddA * mulAddB + mulAddC;
mulAddRecFNToRaw_postMul#(expWidth, sigWidth)
mulAddToRaw_postMul(
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC,
mulAddResult,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
assign out_imul = mulAddResult[expWidth + sigWidth-1:0];
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFN#(
parameter expWidth = 3,
parameter sigWidth = 3,
parameter imulEn = 1'b1
) (
input [(`floatControlWidth - 1):0] control,
input [2:0] op,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [(expWidth + sigWidth):0] c,
input [2:0] roundingMode,
output [(expWidth + sigWidth):0] out,
output [4:0] exceptionFlags,
output [expWidth + sigWidth-1:0] out_imul
);
wire invalidExc, out_isNaN, out_isInf, out_isZero, out_sign;
wire signed [(expWidth + 1):0] out_sExp;
wire [(sigWidth + 2):0] out_sig;
mulAddRecFNToRaw#(expWidth, sigWidth, imulEn)
mulAddRecFNToRaw(
control,
op,
a,
b,
c,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
out_imul
);
roundRawFNToRecFN#(expWidth, sigWidth, 0)
roundRawOut(
control,
invalidExc,
1'b0,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
roundingMode,
out,
exceptionFlags
);
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("f64.const.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("f64.const_tb.vcd");
$dumpvars(0, cpu_tb);
#12
`assert(result, 64'hc000000000000000);
`assert(result_empty, 0);
$finish;
end
endmodule
|
`include "SVGA_DEFINES.v"
module SVGA_TIMING_GENERATION
(
pixel_clock,
reset,
h_synch,
v_synch,
blank,
pixel_count,
line_count
);
input pixel_clock; // pixel clock
input reset; // reset
output h_synch; // horizontal synch for VGA connector
output v_synch; // vertical synch for VGA connector
output blank; // composite blanking
output [10:0] pixel_count; // counts the pixels in a line
output [9:0] line_count; // counts the display lines
reg [9:0] line_count; // counts the display lines
reg [10:0] pixel_count; // counts the pixels in a line
reg h_synch; // horizontal synch
reg v_synch; // vertical synch
reg h_blank; // horizontal blanking
reg v_blank; // vertical blanking
reg blank; // composite blanking
// CREATE THE HORIZONTAL LINE PIXEL COUNTER
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset set pixel counter to 0
pixel_count <= 11'h000;
else if (pixel_count == (`H_TOTAL - 1))
// last pixel in the line, so reset pixel counter
pixel_count <= 11'h000;
else
pixel_count <= pixel_count +1;
end
// CREATE THE HORIZONTAL SYNCH PULSE
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove h_synch
h_synch <= 1'b0;
else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH -1))
// start of h_synch
h_synch <= 1'b1;
else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH -1))
// end of h_synch
h_synch <= 1'b0;
end
// CREATE THE VERTICAL FRAME LINE COUNTER
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset set line counter to 0
line_count <= 10'h000;
else if ((line_count == (`V_TOTAL - 1)) && (pixel_count == (`H_TOTAL - 1)))
// last pixel in last line of frame, so reset line counter
line_count <= 10'h000;
else if ((pixel_count == (`H_TOTAL - 1)))
// last pixel but not last line, so increment line counter
line_count <= line_count + 1;
end
// CREATE THE VERTICAL SYNCH PULSE
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove v_synch
v_synch = 1'b0;
else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH -1) &&
(pixel_count == `H_TOTAL - 1)))
// start of v_synch
v_synch = 1'b1;
else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &&
(pixel_count == (`H_TOTAL - 1)))
// end of v_synch
v_synch = 1'b0;
end
// CREATE THE HORIZONTAL BLANKING SIGNAL
// the "-2" is used instead of "-1" because of the extra register delay
// for the composite blanking signal
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove the h_blank
h_blank <= 1'b0;
else if (pixel_count == (`H_ACTIVE - 2))
// start of HBI
h_blank <= 1'b1;
else if (pixel_count == (`H_TOTAL - 2))
// end of HBI
h_blank <= 1'b0;
end
// CREATE THE VERTICAL BLANKING SIGNAL
// the "-2" is used instead of "-1" in the horizontal factor because of the extra
// register delay for the composite blanking signal
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove v_blank
v_blank <= 1'b0;
else if ((line_count == (`V_ACTIVE - 1) &&
(pixel_count == `H_TOTAL - 2)))
// start of VBI
v_blank <= 1'b1;
else if ((line_count == (`V_TOTAL - 1)) &&
(pixel_count == (`H_TOTAL - 2)))
// end of VBI
v_blank <= 1'b0;
end
// CREATE THE COMPOSITE BLANKING SIGNAL
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove blank
blank <= 1'b0;
// blank during HBI or VBI
else if (h_blank || v_blank)
blank <= 1'b1;
else
// active video do not blank
blank <= 1'b0;
end
endmodule //SVGA_TIMING_GENERATION
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_never (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_NEVER";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_never_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_never_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_never_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_never
`endif
|
//
// Wishbone wrapper for seven-segment LED display controller
//
// Copyright (C) 2015 Andrzej <[email protected]>
//
// Redistribution and use in source and non-source forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in non-source form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// Register map (assuming 32b access):
// 00 [1] - IRQ mask. 1 - IRQ enabled.
// [0] - Enable display controller
// 04 [15:0] - Clock divider for multiplexing.
// To obtain a scanning rate further divide by 256 (for PWM) and by n_digits.
// 08 [7:0] - Brightness control. 0 - minimum brightness (non-zero), 255 - maximum.
// Logarithmic progression (percepted).
// 0c [0] - (Write) Write '1' to clear IRQ flag.
// 0c [0] - (Read) IRQ Flag.
// 20 [n_segs-1:0] - First digit (or column)
// 24 [n_segs-1:0] - Second digit (or column)
// ...
//
// Example of instantiation:
// // open-drain output with logic inversion
// wire [7:0] sseg_disp_seg_oe;
// generate
// for (i = 0; i < 8; i = i+1) begin: sseg_disp_seg_tris
// assign sseg_disp_seg_o [i] = sseg_disp_seg_oe[i] ? 1'b0 : 1'bz;
// end
// endgenerate
//
// wire [7:0] sseg_disp_seg_sel;
// assign sseg_disp_an_o = ~sseg_disp_seg_sel;
//
// wb_sseg_ctrl
// #(
// .n_digits (8),
//`ifdef SIM
// .def_clk_div(4) // speed up simulation time
//`else
// .def_clk_div(128)
//`endif
// )
// sseg_ctrl
// (
// .wb_clk_i (wb_clk),
// .wb_rst_i (wb_rst),
// .async_rst_i (async_rst),
// // Wishbone slave interface
// .wb_adr_i (wb_m2s_sseg_ctrl_adr[5:2]),
// .wb_dat_i (wb_m2s_sseg_ctrl_dat),
// .wb_sel_i (wb_m2s_sseg_ctrl_sel),
// .wb_we_i (wb_m2s_sseg_ctrl_we),
// .wb_cyc_i (wb_m2s_sseg_ctrl_cyc),
// .wb_stb_i (wb_m2s_sseg_ctrl_stb),
// .wb_cti_i (wb_m2s_sseg_ctrl_cti),
// .wb_bte_i (wb_m2s_sseg_ctrl_bte),
// .wb_dat_o (wb_s2m_sseg_ctrl_dat),
// .wb_ack_o (wb_s2m_sseg_ctrl_ack),
// .wb_err_o (wb_s2m_sseg_ctrl_err),
// .wb_rty_o (wb_s2m_sseg_ctrl_rty),
// // display i/f
// .seg_o (sseg_disp_seg_oe),
// .seg_sel_o (sseg_disp_seg_sel),
// // frame sync irq
// .irq_o (sseg_didp_irq)
// );
module wb_sseg_ctrl
#(
parameter n_digits = 8,
parameter n_segs = 8,
parameter def_clk_div = 128,
//parameter def_clk_div = 4,
parameter dw = 16,
parameter aw = 4
)
(
input wb_clk_i,
input wb_rst_i,
input async_rst_i,
// Wishbone Interface
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [dw-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
// display i/f
output [n_segs-1:0] seg_o,
output [n_digits-1:0] seg_sel_o,
// frame sync irq (end of the sweep)
output irq_o
);
wire sync;
// address decoder
reg [2**aw-1:0] sel;
integer i;
always @(*)
begin
sel = {2**aw{1'b0}};
for (i = 0; i < 2**aw; i = i + 1)
if (wb_adr_i == i)
sel[i] = 1'b1;
end
// enable register
reg enable_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
enable_reg <= 1'b0;
else if (wb_rst_i)
enable_reg <= 1'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[0])
enable_reg <= wb_dat_i[0];
// mask IRQ register
reg IRQ_mask_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
IRQ_mask_reg <= 1'b0;
else if (wb_rst_i)
IRQ_mask_reg <= 1'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[0])
IRQ_mask_reg <= wb_dat_i[1];
// clock divider register
reg [15:0] clk_div_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
clk_div_reg <= def_clk_div;
else if (wb_rst_i)
clk_div_reg <= def_clk_div;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[1])
clk_div_reg <= wb_dat_i[15:0];
// brightness register
reg [7:0] brightness_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
brightness_reg <= 8'hff;
else if (wb_rst_i)
brightness_reg <= 8'hff;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[2])
brightness_reg <= wb_dat_i[7:0];
// data to display
reg [n_digits*n_segs-1:0] segments_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
segments_reg <= 0;
else if (wb_rst_i)
segments_reg <= 0;
else if (wb_cyc_i & wb_stb_i & wb_we_i)
for (i = 0; i < n_digits; i = i + 1)
if (sel[i+8])
segments_reg[n_segs*(i+1)-1 -: n_segs] <= wb_dat_i[n_segs-1:0];
// IRQ flag
// write '1' to clear it
reg IRQ_flag_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
IRQ_flag_reg <= 1'b0;
else if (wb_rst_i)
IRQ_flag_reg <= 1'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[3] & wb_dat_i[0])
IRQ_flag_reg <= 1'b0;
else if (sync)
IRQ_flag_reg <= 1'b1;
assign irq_o = IRQ_flag_reg & IRQ_mask_reg;
// read back register values
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_dat_o <= 32'b0;
else if (wb_cyc_i)
begin
wb_dat_o <= 0;
if (sel[0]) wb_dat_o[1:0] <= {IRQ_mask_reg, enable_reg};
if (sel[1]) wb_dat_o[15:0] <= clk_div_reg;
if (sel[2]) wb_dat_o[7:0] <= brightness_reg;
if (sel[3]) wb_dat_o[0] <= IRQ_flag_reg;
for (i = 0; i < n_digits; i = i + 1)
if (sel[i+8])
wb_dat_o[n_segs-1:0] <= segments_reg[n_segs*(i+1)-1 -: n_segs];
end
// Ack generation
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o <= 0;
else if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
assign wb_err_o = 0;
assign wb_rty_o = 0;
// instantiate the controller
sseg_ctrl #(.n_digits(n_digits)) ctrl
(
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.async_rst_i (async_rst_i),
// config registers
.enable_i (enable_reg),
.clk_div_i (clk_div_reg),
.brightness_i (brightness_reg),
.segments_i (segments_reg),
// display i/f
.seg_o (seg_o),
.seg_sel_o (seg_sel_o),
// sync irq
.sync_o (sync)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: lab3dpath_timesim.v
// /___/ /\ Timestamp: Mon Sep 08 14:41:57 2014
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -s 5 -pcf lab3dpath.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -insert_pp_buffers true -w -dir netgen/par -ofmt verilog -sim lab3dpath.ncd lab3dpath_timesim.v
// Device : 3s100ecp132-5 (PRODUCTION 1.27 2013-06-08)
// Input file : lab3dpath.ncd
// Output file : C:\Users\James\Desktop\Lab3_part1\netgen\par\lab3dpath_timesim.v
// # of Modules : 1
// Design Name : lab3dpath
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module lab3dpath (
y, x1, x2, x3
);
output [9 : 0] y;
input [9 : 0] x1;
input [9 : 0] x2;
input [9 : 0] x3;
wire \i2/blk00000001/sig000000d2 ;
wire \i2/blk00000001/sig000001da ;
wire \i2/blk00000001/sig000000d3 ;
wire \i2/blk00000001/sig00000188 ;
wire \i2/blk00000001/sig0000004e ;
wire \i2/blk00000001/sig000000d4 ;
wire \i2/blk00000001/sig000000c4 ;
wire \i2/blk00000001/sig000000d5 ;
wire \i2/blk00000001/sig000000c5 ;
wire \i2/blk00000001/sig0000004a ;
wire \i2/blk00000001/sig000000d6 ;
wire \i2/blk00000001/sig000000c6 ;
wire \i2/blk00000001/sig000000d7 ;
wire \i2/blk00000001/sig000000c7 ;
wire \i2/blk00000001/sig00000046 ;
wire \i2/blk00000001/sig000000d8 ;
wire \i2/blk00000001/sig000000c8 ;
wire \i2/blk00000001/sig000000d9 ;
wire \i2/blk00000001/sig000000c9 ;
wire \i2/blk00000001/sig00000042 ;
wire \i2/blk00000001/sig000000da ;
wire \i2/blk00000001/sig000000ca ;
wire \i2/blk00000001/sig000000db ;
wire \i2/blk00000001/sig000000cb ;
wire \i2/blk00000001/sig0000003e ;
wire \i2/blk00000001/sig000000dc ;
wire \i2/blk00000001/sig000000cc ;
wire \i2/blk00000001/sig000000dd ;
wire \i2/blk00000001/sig000000cd ;
wire \i2/blk00000001/sig0000003a ;
wire \i2/blk00000001/sig000000de ;
wire \i2/blk00000001/sig000000ce ;
wire \i2/blk00000001/sig000000cf ;
wire \i2/blk00000001/sig000000d0 ;
wire \i2/blk00000001/sig000000f9 ;
wire \i2/blk00000001/sig000001e0 ;
wire \i2/blk00000001/sig000000fa ;
wire \i2/blk00000001/sig0000018e ;
wire \i2/blk00000001/sig000000fb ;
wire \i2/blk00000001/sig000000eb ;
wire \i2/blk00000001/sig000000fc ;
wire \i2/blk00000001/sig000000ec ;
wire \i2/blk00000001/sig0000006b ;
wire \i2/blk00000001/sig000000fd ;
wire \i2/blk00000001/sig000000ed ;
wire \i2/blk00000001/sig000000fe ;
wire \i2/blk00000001/sig000000ee ;
wire \i2/blk00000001/sig00000067 ;
wire \i2/blk00000001/sig000000ff ;
wire \i2/blk00000001/sig000000ef ;
wire \i2/blk00000001/sig00000100 ;
wire \i2/blk00000001/sig000000f0 ;
wire \i2/blk00000001/sig00000063 ;
wire \i2/blk00000001/sig00000101 ;
wire \i2/blk00000001/sig000000f1 ;
wire \i2/blk00000001/sig00000102 ;
wire \i2/blk00000001/sig000000f2 ;
wire \i2/blk00000001/sig0000005f ;
wire \i2/blk00000001/sig00000103 ;
wire \i2/blk00000001/sig000000f3 ;
wire \i2/blk00000001/sig00000104 ;
wire \i2/blk00000001/sig000000f4 ;
wire \i2/blk00000001/sig0000005b ;
wire \i2/blk00000001/sig000000f5 ;
wire \i2/blk00000001/sig000000f6 ;
wire \i2/blk00000001/sig00000057 ;
wire \i2/blk00000001/sig000000f7 ;
wire \i2/blk00000001/sig000000f8 ;
wire \i2/blk00000001/sig00000185 ;
wire \i2/blk00000001/sig00000184 ;
wire \i2/blk00000001/sig000001d1 ;
wire \i2/blk00000001/sig00000179 ;
wire \i2/blk00000001/sig0000016e ;
wire \i2/blk00000001/sig000001c5 ;
wire \i2/blk00000001/sig00000163 ;
wire \i2/blk00000001/sig00000158 ;
wire \i2/blk00000001/sig000001b9 ;
wire \i2/blk00000001/sig0000014d ;
wire \i2/blk00000001/sig00000142 ;
wire \i2/blk00000001/sig000001ad ;
wire x2_8_IBUF_3048;
wire x2_9_IBUF_3049;
wire \i2/blk00000001/sig00000137 ;
wire \i2/blk00000001/sig0000012c ;
wire \i2/blk00000001/sig000001a1 ;
wire \i2/blk00000001/sig00000121 ;
wire \i2/blk00000001/sig00000116 ;
wire \i2/blk00000001/sig00000195 ;
wire x2_6_IBUF_3056;
wire x2_7_IBUF_3057;
wire \i2/blk00000001/sig000001d9 ;
wire \i2/blk00000001/sig00000186 ;
wire \i2/blk00000001/sig0000017a ;
wire \i2/blk00000001/sig000001cc ;
wire \i2/blk00000001/sig0000016f ;
wire \i2/blk00000001/sig00000164 ;
wire \i2/blk00000001/sig000001c0 ;
wire \i2/blk00000001/sig00000159 ;
wire \i2/blk00000001/sig0000014e ;
wire \i2/blk00000001/sig000001b4 ;
wire \i2/blk00000001/sig00000143 ;
wire \i2/blk00000001/sig00000138 ;
wire \i2/blk00000001/sig000001a8 ;
wire \i2/blk00000001/sig0000012d ;
wire \i2/blk00000001/sig00000122 ;
wire \i2/blk00000001/sig00000117 ;
wire \i2/blk00000001/sig0000010c ;
wire x2_0_IBUF_3076;
wire x2_1_IBUF_3077;
wire \i2/blk00000001/sig000001e3 ;
wire \i2/blk00000001/sig00000191 ;
wire \i2/blk00000001/sig000001e2 ;
wire \i2/blk00000001/sig0000018f ;
wire \i2/blk00000001/sig00000180 ;
wire \i2/blk00000001/sig000001cf ;
wire \i2/blk00000001/sig00000175 ;
wire \i2/blk00000001/sig0000016a ;
wire \i2/blk00000001/sig000001c3 ;
wire \i2/blk00000001/sig0000015f ;
wire \i2/blk00000001/sig00000154 ;
wire \i2/blk00000001/sig000001b7 ;
wire \i2/blk00000001/sig00000149 ;
wire \i2/blk00000001/sig0000013e ;
wire \i2/blk00000001/sig000001ab ;
wire \i2/blk00000001/sig00000133 ;
wire \i2/blk00000001/sig00000128 ;
wire \i2/blk00000001/sig0000011d ;
wire \i2/blk00000001/sig00000112 ;
wire x2_4_IBUF_3098;
wire x2_5_IBUF_3099;
wire \i2/blk00000001/sig000001dd ;
wire \i2/blk00000001/sig0000018b ;
wire \i2/blk00000001/sig000001dc ;
wire \i2/blk00000001/sig00000189 ;
wire \i2/blk00000001/sig0000017c ;
wire \i2/blk00000001/sig000001cd ;
wire \i2/blk00000001/sig00000171 ;
wire \i2/blk00000001/sig00000166 ;
wire \i2/blk00000001/sig000001c1 ;
wire \i2/blk00000001/sig0000015b ;
wire \i2/blk00000001/sig00000150 ;
wire \i2/blk00000001/sig000001b5 ;
wire \i2/blk00000001/sig00000145 ;
wire \i2/blk00000001/sig0000013a ;
wire \i2/blk00000001/sig000001a9 ;
wire \i2/blk00000001/sig0000012f ;
wire \i2/blk00000001/sig00000124 ;
wire \i2/blk00000001/sig00000119 ;
wire \i2/blk00000001/sig0000010e ;
wire \i2/blk00000001/sig000001e5 ;
wire \i2/blk00000001/sig00000192 ;
wire \i2/blk00000001/sig00000182 ;
wire \i2/blk00000001/sig000001d0 ;
wire \i2/blk00000001/sig00000177 ;
wire \i2/blk00000001/sig0000016c ;
wire \i2/blk00000001/sig000001c4 ;
wire \i2/blk00000001/sig00000161 ;
wire \i2/blk00000001/sig00000156 ;
wire \i2/blk00000001/sig000001b8 ;
wire \i2/blk00000001/sig0000014b ;
wire \i2/blk00000001/sig00000140 ;
wire \i2/blk00000001/sig000001ac ;
wire \i2/blk00000001/sig00000135 ;
wire \i2/blk00000001/sig0000012a ;
wire \i2/blk00000001/sig0000011f ;
wire \i2/blk00000001/sig00000114 ;
wire x2_2_IBUF_3138;
wire x2_3_IBUF_3139;
wire \i2/blk00000001/sig000001df ;
wire \i2/blk00000001/sig0000018c ;
wire \i2/blk00000001/sig0000017e ;
wire \i2/blk00000001/sig000001ce ;
wire \i2/blk00000001/sig00000173 ;
wire \i2/blk00000001/sig00000168 ;
wire \i2/blk00000001/sig000001c2 ;
wire \i2/blk00000001/sig0000015d ;
wire \i2/blk00000001/sig00000152 ;
wire \i2/blk00000001/sig000001b6 ;
wire \i2/blk00000001/sig00000147 ;
wire \i2/blk00000001/sig0000013c ;
wire \i2/blk00000001/sig000001aa ;
wire \i2/blk00000001/sig00000131 ;
wire \i2/blk00000001/sig00000126 ;
wire \i2/blk00000001/sig0000011b ;
wire \i2/blk00000001/sig00000110 ;
wire \i2/blk00000001/sig0000008a ;
wire \i2/blk00000001/sig00000086 ;
wire \i2/blk00000001/sig00000082 ;
wire \i2/blk00000001/sig0000007e ;
wire \i2/blk00000001/sig0000007a ;
wire \i2/blk00000001/sig000000a5 ;
wire \i2/blk00000001/sig000000a1 ;
wire \i2/blk00000001/sig0000009d ;
wire \i2/blk00000001/sig00000099 ;
wire \i2/blk00000001/sig00000095 ;
wire \i2/blk00000001/sig000000c0 ;
wire \i2/blk00000001/sig000000bc ;
wire \i2/blk00000001/sig000000b8 ;
wire \i2/blk00000001/sig000000b4 ;
wire \i2/blk00000001/sig000000b0 ;
wire \Madd_s2_Madd_cy[1] ;
wire Madd_s2C_0;
wire Madd_s2C1_0;
wire \Madd_s2_Madd_cy[3] ;
wire Madd_s2C2_0;
wire Madd_s2C3_0;
wire \Madd_s2_Madd_cy[5] ;
wire Madd_s2C4_0;
wire Madd_s2C5_0;
wire \Madd_s2_Madd_cy[7] ;
wire Madd_s2C6_0;
wire Madd_s2C7_0;
wire Madd_s2C8_0;
wire N10_0;
wire \i1/blk00000001/sig000000d2 ;
wire \i1/blk00000001/sig000001da ;
wire \i1/blk00000001/sig000000d3 ;
wire \i1/blk00000001/sig00000188 ;
wire \i1/blk00000001/sig0000004e ;
wire \i1/blk00000001/sig000000d4 ;
wire \i1/blk00000001/sig000000c4 ;
wire \i1/blk00000001/sig000000d5 ;
wire \i1/blk00000001/sig000000c5 ;
wire \i1/blk00000001/sig0000004a ;
wire \i1/blk00000001/sig000000d6 ;
wire \i1/blk00000001/sig000000c6 ;
wire \i1/blk00000001/sig000000d7 ;
wire \i1/blk00000001/sig000000c7 ;
wire \i1/blk00000001/sig00000046 ;
wire \i1/blk00000001/sig000000d8 ;
wire \i1/blk00000001/sig000000c8 ;
wire \i1/blk00000001/sig000000d9 ;
wire \i1/blk00000001/sig000000c9 ;
wire \i1/blk00000001/sig00000042 ;
wire \i1/blk00000001/sig000000da ;
wire \i1/blk00000001/sig000000ca ;
wire \i1/blk00000001/sig000000db ;
wire \i1/blk00000001/sig000000cb ;
wire \i1/blk00000001/sig0000003e ;
wire \i1/blk00000001/sig000000dc ;
wire \i1/blk00000001/sig000000cc ;
wire \i1/blk00000001/sig000000dd ;
wire \i1/blk00000001/sig000000cd ;
wire \i1/blk00000001/sig0000003a ;
wire \i1/blk00000001/sig000000de ;
wire \i1/blk00000001/sig000000ce ;
wire \i1/blk00000001/sig000000cf ;
wire \i1/blk00000001/sig000000d0 ;
wire \i1/blk00000001/sig000000f9 ;
wire \i1/blk00000001/sig000001e0 ;
wire \i1/blk00000001/sig000000fa ;
wire \i1/blk00000001/sig0000018e ;
wire \i1/blk00000001/sig000000fb ;
wire \i1/blk00000001/sig000000eb ;
wire \i1/blk00000001/sig000000fc ;
wire \i1/blk00000001/sig000000ec ;
wire \i1/blk00000001/sig0000006b ;
wire \i1/blk00000001/sig000000fd ;
wire \i1/blk00000001/sig000000ed ;
wire \i1/blk00000001/sig000000fe ;
wire \i1/blk00000001/sig000000ee ;
wire \i1/blk00000001/sig00000067 ;
wire \i1/blk00000001/sig000000ff ;
wire \i1/blk00000001/sig000000ef ;
wire \i1/blk00000001/sig00000100 ;
wire \i1/blk00000001/sig000000f0 ;
wire \i1/blk00000001/sig00000063 ;
wire \i1/blk00000001/sig00000101 ;
wire \i1/blk00000001/sig000000f1 ;
wire \i1/blk00000001/sig00000102 ;
wire \i1/blk00000001/sig000000f2 ;
wire \i1/blk00000001/sig0000005f ;
wire \i1/blk00000001/sig00000103 ;
wire \i1/blk00000001/sig000000f3 ;
wire \i1/blk00000001/sig00000104 ;
wire \i1/blk00000001/sig000000f4 ;
wire \i1/blk00000001/sig0000005b ;
wire \i1/blk00000001/sig000000f5 ;
wire \i1/blk00000001/sig000000f6 ;
wire \i1/blk00000001/sig00000057 ;
wire \i1/blk00000001/sig000000f7 ;
wire \i1/blk00000001/sig000000f8 ;
wire \i1/blk00000001/sig00000185 ;
wire \i1/blk00000001/sig00000184 ;
wire \i1/blk00000001/sig000001d1 ;
wire \i1/blk00000001/sig00000179 ;
wire \i1/blk00000001/sig0000016e ;
wire \i1/blk00000001/sig000001c5 ;
wire \i1/blk00000001/sig00000163 ;
wire \i1/blk00000001/sig00000158 ;
wire \i1/blk00000001/sig000001b9 ;
wire \i1/blk00000001/sig0000014d ;
wire \i1/blk00000001/sig00000142 ;
wire \i1/blk00000001/sig000001ad ;
wire \i1/blk00000001/sig00000137 ;
wire \i1/blk00000001/sig0000012c ;
wire \i1/blk00000001/sig000001a1 ;
wire x1_8_IBUF_3311;
wire x1_9_IBUF_3312;
wire \i1/blk00000001/sig00000121 ;
wire \i1/blk00000001/sig00000116 ;
wire \i1/blk00000001/sig0000010b ;
wire x1_6_IBUF_3317;
wire x1_7_IBUF_3318;
wire \i1/blk00000001/sig000001d9 ;
wire \i1/blk00000001/sig00000186 ;
wire \i1/blk00000001/sig0000017a ;
wire \i1/blk00000001/sig000001cc ;
wire \i1/blk00000001/sig0000016f ;
wire \i1/blk00000001/sig00000164 ;
wire \i1/blk00000001/sig000001c0 ;
wire \i1/blk00000001/sig00000159 ;
wire \i1/blk00000001/sig0000014e ;
wire \i1/blk00000001/sig000001b4 ;
wire \i1/blk00000001/sig00000143 ;
wire \i1/blk00000001/sig00000138 ;
wire \i1/blk00000001/sig000001a8 ;
wire \i1/blk00000001/sig0000012d ;
wire \i1/blk00000001/sig00000122 ;
wire \i1/blk00000001/sig00000117 ;
wire \i1/blk00000001/sig0000010c ;
wire x1_0_IBUF_3337;
wire x1_1_IBUF_3338;
wire \i1/blk00000001/sig000001e3 ;
wire \i1/blk00000001/sig00000191 ;
wire \i1/blk00000001/sig000001e2 ;
wire \i1/blk00000001/sig0000018f ;
wire \i1/blk00000001/sig00000180 ;
wire \i1/blk00000001/sig000001cf ;
wire \i1/blk00000001/sig00000175 ;
wire \i1/blk00000001/sig0000016a ;
wire \i1/blk00000001/sig000001c3 ;
wire \i1/blk00000001/sig0000015f ;
wire \i1/blk00000001/sig00000154 ;
wire \i1/blk00000001/sig000001b7 ;
wire \i1/blk00000001/sig00000149 ;
wire \i1/blk00000001/sig0000013e ;
wire \i1/blk00000001/sig000001ab ;
wire \i1/blk00000001/sig00000133 ;
wire \i1/blk00000001/sig00000128 ;
wire \i1/blk00000001/sig0000011d ;
wire \i1/blk00000001/sig00000112 ;
wire x1_4_IBUF_3359;
wire x1_5_IBUF_3360;
wire \i1/blk00000001/sig000001dd ;
wire \i1/blk00000001/sig0000018b ;
wire \i1/blk00000001/sig000001dc ;
wire \i1/blk00000001/sig00000189 ;
wire \i1/blk00000001/sig0000017c ;
wire \i1/blk00000001/sig000001cd ;
wire \i1/blk00000001/sig00000171 ;
wire \i1/blk00000001/sig00000166 ;
wire \i1/blk00000001/sig000001c1 ;
wire \i1/blk00000001/sig0000015b ;
wire \i1/blk00000001/sig00000150 ;
wire \i1/blk00000001/sig000001b5 ;
wire \i1/blk00000001/sig00000145 ;
wire \i1/blk00000001/sig0000013a ;
wire \i1/blk00000001/sig000001a9 ;
wire \i1/blk00000001/sig0000012f ;
wire \i1/blk00000001/sig00000124 ;
wire \i1/blk00000001/sig00000119 ;
wire \i1/blk00000001/sig0000010e ;
wire \i1/blk00000001/sig000001e5 ;
wire \i1/blk00000001/sig00000192 ;
wire \i1/blk00000001/sig00000182 ;
wire \i1/blk00000001/sig000001d0 ;
wire \i1/blk00000001/sig00000177 ;
wire \i1/blk00000001/sig0000016c ;
wire \i1/blk00000001/sig000001c4 ;
wire \i1/blk00000001/sig00000161 ;
wire \i1/blk00000001/sig00000156 ;
wire \i1/blk00000001/sig000001b8 ;
wire \i1/blk00000001/sig0000014b ;
wire \i1/blk00000001/sig00000140 ;
wire \i1/blk00000001/sig000001ac ;
wire \i1/blk00000001/sig00000135 ;
wire \i1/blk00000001/sig0000012a ;
wire \i1/blk00000001/sig0000011f ;
wire \i1/blk00000001/sig00000114 ;
wire x1_2_IBUF_3399;
wire x1_3_IBUF_3400;
wire \i1/blk00000001/sig000001df ;
wire \i1/blk00000001/sig0000018c ;
wire \i1/blk00000001/sig0000017e ;
wire \i1/blk00000001/sig000001ce ;
wire \i1/blk00000001/sig00000173 ;
wire \i1/blk00000001/sig00000168 ;
wire \i1/blk00000001/sig000001c2 ;
wire \i1/blk00000001/sig0000015d ;
wire \i1/blk00000001/sig00000152 ;
wire \i1/blk00000001/sig000001b6 ;
wire \i1/blk00000001/sig00000147 ;
wire \i1/blk00000001/sig0000013c ;
wire \i1/blk00000001/sig000001aa ;
wire \i1/blk00000001/sig00000131 ;
wire \i1/blk00000001/sig00000126 ;
wire \i1/blk00000001/sig0000011b ;
wire \i1/blk00000001/sig00000110 ;
wire \i1/blk00000001/sig0000008a ;
wire \i1/blk00000001/sig00000086 ;
wire \i1/blk00000001/sig00000082 ;
wire \i1/blk00000001/sig0000007e ;
wire \i1/blk00000001/sig0000007a ;
wire \i1/blk00000001/sig000000a5 ;
wire \i1/blk00000001/sig000000a1 ;
wire \i1/blk00000001/sig0000009d ;
wire \i1/blk00000001/sig00000099 ;
wire \i1/blk00000001/sig00000095 ;
wire \i1/blk00000001/sig000000c0 ;
wire \i1/blk00000001/sig000000bc ;
wire \i1/blk00000001/sig000000b8 ;
wire \i1/blk00000001/sig000000b4 ;
wire \i1/blk00000001/sig000000b0 ;
wire \i3/blk00000001/sig000000d2 ;
wire \i3/blk00000001/sig000001da ;
wire \i3/blk00000001/sig000000d3 ;
wire \i3/blk00000001/sig00000188 ;
wire \i3/blk00000001/sig0000004e ;
wire \i3/blk00000001/sig000000d4 ;
wire \i3/blk00000001/sig000000c4 ;
wire \i3/blk00000001/sig000000d5 ;
wire \i3/blk00000001/sig000000c5 ;
wire \i3/blk00000001/sig0000004a ;
wire \i3/blk00000001/sig000000d6 ;
wire \i3/blk00000001/sig000000c6 ;
wire \i3/blk00000001/sig000000d7 ;
wire \i3/blk00000001/sig000000c7 ;
wire \i3/blk00000001/sig00000046 ;
wire \i3/blk00000001/sig000000d8 ;
wire \i3/blk00000001/sig000000c8 ;
wire \i3/blk00000001/sig000000d9 ;
wire \i3/blk00000001/sig000000c9 ;
wire \i3/blk00000001/sig00000042 ;
wire \i3/blk00000001/sig000000da ;
wire \i3/blk00000001/sig000000ca ;
wire \i3/blk00000001/sig000000db ;
wire \i3/blk00000001/sig000000cb ;
wire \i3/blk00000001/sig0000003e ;
wire \i3/blk00000001/sig000000dc ;
wire \i3/blk00000001/sig000000cc ;
wire \i3/blk00000001/sig000000dd ;
wire \i3/blk00000001/sig000000cd ;
wire \i3/blk00000001/sig0000003a ;
wire \i3/blk00000001/sig000000de ;
wire \i3/blk00000001/sig000000ce ;
wire \i3/blk00000001/sig000000cf ;
wire \i3/blk00000001/sig000000d0 ;
wire \i3/blk00000001/sig000000f9 ;
wire \i3/blk00000001/sig000001e0 ;
wire \i3/blk00000001/sig000000fa ;
wire \i3/blk00000001/sig0000018e ;
wire \i3/blk00000001/sig000000fb ;
wire \i3/blk00000001/sig000000eb ;
wire \i3/blk00000001/sig000000fc ;
wire \i3/blk00000001/sig000000ec ;
wire \i3/blk00000001/sig0000006b ;
wire \i3/blk00000001/sig000000fd ;
wire \i3/blk00000001/sig000000ed ;
wire \i3/blk00000001/sig000000fe ;
wire \i3/blk00000001/sig000000ee ;
wire \i3/blk00000001/sig00000067 ;
wire \i3/blk00000001/sig000000ff ;
wire \i3/blk00000001/sig000000ef ;
wire \i3/blk00000001/sig00000100 ;
wire \i3/blk00000001/sig000000f0 ;
wire \i3/blk00000001/sig00000063 ;
wire \i3/blk00000001/sig00000101 ;
wire \i3/blk00000001/sig000000f1 ;
wire \i3/blk00000001/sig00000102 ;
wire \i3/blk00000001/sig000000f2 ;
wire \i3/blk00000001/sig0000005f ;
wire \i3/blk00000001/sig00000103 ;
wire \i3/blk00000001/sig000000f3 ;
wire \i3/blk00000001/sig00000104 ;
wire \i3/blk00000001/sig000000f4 ;
wire \i3/blk00000001/sig0000005b ;
wire \i3/blk00000001/sig000000f5 ;
wire \i3/blk00000001/sig000000f6 ;
wire \i3/blk00000001/sig00000057 ;
wire \i3/blk00000001/sig000000f7 ;
wire \i3/blk00000001/sig000000f8 ;
wire \i3/blk00000001/sig00000185 ;
wire \i3/blk00000001/sig00000184 ;
wire \i3/blk00000001/sig000001d1 ;
wire \i3/blk00000001/sig00000179 ;
wire \i3/blk00000001/sig0000016e ;
wire \i3/blk00000001/sig000001c5 ;
wire \i3/blk00000001/sig00000163 ;
wire \i3/blk00000001/sig00000158 ;
wire \i3/blk00000001/sig000001b9 ;
wire \i3/blk00000001/sig0000014d ;
wire \i3/blk00000001/sig00000142 ;
wire \i3/blk00000001/sig000001ad ;
wire \i3/blk00000001/sig00000137 ;
wire \i3/blk00000001/sig0000012c ;
wire \i3/blk00000001/sig000001a1 ;
wire x3_8_IBUF_3523;
wire x3_9_IBUF_3524;
wire \i3/blk00000001/sig00000121 ;
wire \i3/blk00000001/sig00000116 ;
wire \i3/blk00000001/sig0000010b ;
wire x3_6_IBUF_3529;
wire x3_7_IBUF_3530;
wire \i3/blk00000001/sig000001d9 ;
wire \i3/blk00000001/sig00000186 ;
wire \i3/blk00000001/sig0000017a ;
wire \i3/blk00000001/sig000001cc ;
wire \i3/blk00000001/sig0000016f ;
wire \i3/blk00000001/sig00000164 ;
wire \i3/blk00000001/sig000001c0 ;
wire \i3/blk00000001/sig00000159 ;
wire \i3/blk00000001/sig0000014e ;
wire \i3/blk00000001/sig000001b4 ;
wire \i3/blk00000001/sig00000143 ;
wire \i3/blk00000001/sig00000138 ;
wire \i3/blk00000001/sig000001a8 ;
wire \i3/blk00000001/sig0000012d ;
wire \i3/blk00000001/sig00000122 ;
wire \i3/blk00000001/sig00000117 ;
wire \i3/blk00000001/sig0000010c ;
wire x3_0_IBUF_3549;
wire x3_1_IBUF_3550;
wire \i3/blk00000001/sig000001e3 ;
wire \i3/blk00000001/sig00000191 ;
wire \i3/blk00000001/sig000001e2 ;
wire \i3/blk00000001/sig0000018f ;
wire \i3/blk00000001/sig00000180 ;
wire \i3/blk00000001/sig000001cf ;
wire \i3/blk00000001/sig00000175 ;
wire \i3/blk00000001/sig0000016a ;
wire \i3/blk00000001/sig000001c3 ;
wire \i3/blk00000001/sig0000015f ;
wire \i3/blk00000001/sig00000154 ;
wire \i3/blk00000001/sig000001b7 ;
wire \i3/blk00000001/sig00000149 ;
wire \i3/blk00000001/sig0000013e ;
wire \i3/blk00000001/sig000001ab ;
wire \i3/blk00000001/sig00000133 ;
wire \i3/blk00000001/sig00000128 ;
wire \i3/blk00000001/sig0000011d ;
wire \i3/blk00000001/sig00000112 ;
wire x3_4_IBUF_3571;
wire x3_5_IBUF_3572;
wire \i3/blk00000001/sig000001dd ;
wire \i3/blk00000001/sig0000018b ;
wire \i3/blk00000001/sig000001dc ;
wire \i3/blk00000001/sig00000189 ;
wire \i3/blk00000001/sig0000017c ;
wire \i3/blk00000001/sig000001cd ;
wire \i3/blk00000001/sig00000171 ;
wire \i3/blk00000001/sig00000166 ;
wire \i3/blk00000001/sig000001c1 ;
wire \i3/blk00000001/sig0000015b ;
wire \i3/blk00000001/sig00000150 ;
wire \i3/blk00000001/sig000001b5 ;
wire \i3/blk00000001/sig00000145 ;
wire \i3/blk00000001/sig0000013a ;
wire \i3/blk00000001/sig000001a9 ;
wire \i3/blk00000001/sig0000012f ;
wire \i3/blk00000001/sig00000124 ;
wire \i3/blk00000001/sig00000119 ;
wire \i3/blk00000001/sig0000010e ;
wire \i3/blk00000001/sig000001e5 ;
wire \i3/blk00000001/sig00000192 ;
wire \i3/blk00000001/sig00000182 ;
wire \i3/blk00000001/sig000001d0 ;
wire \i3/blk00000001/sig00000177 ;
wire \i3/blk00000001/sig0000016c ;
wire \i3/blk00000001/sig000001c4 ;
wire \i3/blk00000001/sig00000161 ;
wire \i3/blk00000001/sig00000156 ;
wire \i3/blk00000001/sig000001b8 ;
wire \i3/blk00000001/sig0000014b ;
wire \i3/blk00000001/sig00000140 ;
wire \i3/blk00000001/sig000001ac ;
wire \i3/blk00000001/sig00000135 ;
wire \i3/blk00000001/sig0000012a ;
wire \i3/blk00000001/sig0000011f ;
wire \i3/blk00000001/sig00000114 ;
wire x3_2_IBUF_3611;
wire x3_3_IBUF_3612;
wire \i3/blk00000001/sig000001df ;
wire \i3/blk00000001/sig0000018c ;
wire \i3/blk00000001/sig0000017e ;
wire \i3/blk00000001/sig000001ce ;
wire \i3/blk00000001/sig00000173 ;
wire \i3/blk00000001/sig00000168 ;
wire \i3/blk00000001/sig000001c2 ;
wire \i3/blk00000001/sig0000015d ;
wire \i3/blk00000001/sig00000152 ;
wire \i3/blk00000001/sig000001b6 ;
wire \i3/blk00000001/sig00000147 ;
wire \i3/blk00000001/sig0000013c ;
wire \i3/blk00000001/sig000001aa ;
wire \i3/blk00000001/sig00000131 ;
wire \i3/blk00000001/sig00000126 ;
wire \i3/blk00000001/sig0000011b ;
wire \i3/blk00000001/sig00000110 ;
wire \i3/blk00000001/sig0000008a ;
wire \i3/blk00000001/sig00000086 ;
wire \i3/blk00000001/sig00000082 ;
wire \i3/blk00000001/sig0000007e ;
wire \i3/blk00000001/sig0000007a ;
wire \i3/blk00000001/sig000000a5 ;
wire \i3/blk00000001/sig000000a1 ;
wire \i3/blk00000001/sig0000009d ;
wire \i3/blk00000001/sig00000099 ;
wire \i3/blk00000001/sig00000095 ;
wire \i3/blk00000001/sig000000c0 ;
wire \i3/blk00000001/sig000000bc ;
wire \i3/blk00000001/sig000000b8 ;
wire \i3/blk00000001/sig000000b4 ;
wire \i3/blk00000001/sig000000b0 ;
wire \i2/blk00000001/sig0000004e/CYINIT_3678 ;
wire \i2/blk00000001/sig0000004e/CY0F_3677 ;
wire \i2/blk00000001/sig0000004e/CYSELF_3669 ;
wire \i2/blk00000001/sig00000051 ;
wire \i2/blk00000001/sig0000004e/BXINV_3667 ;
wire \i2/blk00000001/sig0000004e/CYMUXG_3666 ;
wire \i2/blk00000001/sig00000050 ;
wire \i2/blk00000001/sig0000004e/CY0G_3664 ;
wire \i2/blk00000001/sig0000004e/CYSELG_3656 ;
wire \i2/blk00000001/sig0000004f ;
wire \t2<11>/CYINIT_3714 ;
wire \t2<11>/CY0F_3713 ;
wire \i2/blk00000001/sig0000004d ;
wire \t2<11>/XORG_3703 ;
wire \i2/blk00000001/sig0000004c ;
wire \t2<11>/CYSELF_3701 ;
wire \t2<11>/CYMUXFAST_3700 ;
wire \t2<11>/CYAND_3699 ;
wire \t2<11>/FASTCARRY_3698 ;
wire \t2<11>/CYMUXG2_3697 ;
wire \t2<11>/CYMUXF2_3696 ;
wire \t2<11>/CY0G_3695 ;
wire \t2<11>/CYSELG_3687 ;
wire \i2/blk00000001/sig0000004b ;
wire \t2<12>/XORF_3752 ;
wire \t2<12>/CYINIT_3751 ;
wire \t2<12>/CY0F_3750 ;
wire \i2/blk00000001/sig00000049 ;
wire \t2<12>/XORG_3740 ;
wire \i2/blk00000001/sig00000048 ;
wire \t2<12>/CYSELF_3738 ;
wire \t2<12>/CYMUXFAST_3737 ;
wire \t2<12>/CYAND_3736 ;
wire \t2<12>/FASTCARRY_3735 ;
wire \t2<12>/CYMUXG2_3734 ;
wire \t2<12>/CYMUXF2_3733 ;
wire \t2<12>/CY0G_3732 ;
wire \t2<12>/CYSELG_3724 ;
wire \i2/blk00000001/sig00000047 ;
wire \t2<14>/XORF_3791 ;
wire \t2<14>/CYINIT_3790 ;
wire \t2<14>/CY0F_3789 ;
wire \i2/blk00000001/sig00000045 ;
wire \t2<14>/XORG_3779 ;
wire \i2/blk00000001/sig00000044 ;
wire \t2<14>/CYSELF_3777 ;
wire \t2<14>/CYMUXFAST_3776 ;
wire \t2<14>/CYAND_3775 ;
wire \t2<14>/FASTCARRY_3774 ;
wire \t2<14>/CYMUXG2_3773 ;
wire \t2<14>/CYMUXF2_3772 ;
wire \t2<14>/CY0G_3771 ;
wire \t2<14>/CYSELG_3763 ;
wire \i2/blk00000001/sig00000043 ;
wire \t2<16>/XORF_3830 ;
wire \t2<16>/CYINIT_3829 ;
wire \t2<16>/CY0F_3828 ;
wire \i2/blk00000001/sig00000041 ;
wire \t2<16>/XORG_3818 ;
wire \i2/blk00000001/sig00000040 ;
wire \t2<16>/CYSELF_3816 ;
wire \t2<16>/CYMUXFAST_3815 ;
wire \t2<16>/CYAND_3814 ;
wire \t2<16>/FASTCARRY_3813 ;
wire \t2<16>/CYMUXG2_3812 ;
wire \t2<16>/CYMUXF2_3811 ;
wire \t2<16>/CY0G_3810 ;
wire \t2<16>/CYSELG_3802 ;
wire \i2/blk00000001/sig0000003f ;
wire \t2<18>/XORF_3869 ;
wire \t2<18>/CYINIT_3868 ;
wire \t2<18>/CY0F_3867 ;
wire \i2/blk00000001/sig0000003d ;
wire \t2<18>/XORG_3857 ;
wire \i2/blk00000001/sig0000003c ;
wire \t2<18>/CYSELF_3855 ;
wire \t2<18>/CYMUXFAST_3854 ;
wire \t2<18>/CYAND_3853 ;
wire \t2<18>/FASTCARRY_3852 ;
wire \t2<18>/CYMUXG2_3851 ;
wire \t2<18>/CYMUXF2_3850 ;
wire \t2<18>/CY0G_3849 ;
wire \t2<18>/CYSELG_3841 ;
wire \i2/blk00000001/sig0000003b ;
wire \t2<20>/XORF_3908 ;
wire \t2<20>/CYINIT_3907 ;
wire \t2<20>/CY0F_3906 ;
wire \i2/blk00000001/sig00000039 ;
wire \t2<20>/XORG_3896 ;
wire \i2/blk00000001/sig00000038 ;
wire \t2<20>/CYSELF_3894 ;
wire \t2<20>/CYMUXFAST_3893 ;
wire \t2<20>/CYAND_3892 ;
wire \t2<20>/FASTCARRY_3891 ;
wire \t2<20>/CYMUXG2_3890 ;
wire \t2<20>/CYMUXF2_3889 ;
wire \t2<20>/CY0G_3888 ;
wire \t2<20>/CYSELG_3880 ;
wire \i2/blk00000001/sig00000037 ;
wire \t2<22>/XORF_3923 ;
wire \t2<22>/CYINIT_3922 ;
wire \i2/blk00000001/sig00000035 ;
wire \i2/blk00000001/sig0000006f/CYINIT_3954 ;
wire \i2/blk00000001/sig0000006f/CY0F_3953 ;
wire \i2/blk00000001/sig0000006f/CYSELF_3945 ;
wire \i2/blk00000001/sig00000072 ;
wire \i2/blk00000001/sig0000006f/BXINV_3943 ;
wire \i2/blk00000001/sig0000006f/CYMUXG_3942 ;
wire \i2/blk00000001/sig00000071 ;
wire \i2/blk00000001/sig0000006f/CY0G_3940 ;
wire \i2/blk00000001/sig0000006f/CYSELG_3932 ;
wire \i2/blk00000001/sig00000070 ;
wire \i2/blk00000001/sig0000006b/CY0F_3985 ;
wire \i2/blk00000001/sig0000006e ;
wire \i2/blk00000001/sig0000006b/CYSELF_3976 ;
wire \i2/blk00000001/sig0000006b/CYMUXFAST_3975 ;
wire \i2/blk00000001/sig0000006b/CYAND_3974 ;
wire \i2/blk00000001/sig0000006b/FASTCARRY_3973 ;
wire \i2/blk00000001/sig0000006b/CYMUXG2_3972 ;
wire \i2/blk00000001/sig0000006b/CYMUXF2_3971 ;
wire \i2/blk00000001/sig0000006b/CY0G_3970 ;
wire \i2/blk00000001/sig0000006b/CYSELG_3962 ;
wire \i2/blk00000001/sig0000006c ;
wire \i2/blk00000001/sig000000d2/XORF_4023 ;
wire \i2/blk00000001/sig000000d2/CYINIT_4022 ;
wire \i2/blk00000001/sig000000d2/CY0F_4021 ;
wire \i2/blk00000001/sig0000006a ;
wire \i2/blk00000001/sig000000d2/XORG_4011 ;
wire \i2/blk00000001/sig00000069 ;
wire \i2/blk00000001/sig000000d2/CYSELF_4009 ;
wire \i2/blk00000001/sig000000d2/CYMUXFAST_4008 ;
wire \i2/blk00000001/sig000000d2/CYAND_4007 ;
wire \i2/blk00000001/sig000000d2/FASTCARRY_4006 ;
wire \i2/blk00000001/sig000000d2/CYMUXG2_4005 ;
wire \i2/blk00000001/sig000000d2/CYMUXF2_4004 ;
wire \i2/blk00000001/sig000000d2/CY0G_4003 ;
wire \i2/blk00000001/sig000000d2/CYSELG_3995 ;
wire \i2/blk00000001/sig00000068 ;
wire \i2/blk00000001/sig000000d4/XORF_4062 ;
wire \i2/blk00000001/sig000000d4/CYINIT_4061 ;
wire \i2/blk00000001/sig000000d4/CY0F_4060 ;
wire \i2/blk00000001/sig00000066 ;
wire \i2/blk00000001/sig000000d4/XORG_4050 ;
wire \i2/blk00000001/sig00000065 ;
wire \i2/blk00000001/sig000000d4/CYSELF_4048 ;
wire \i2/blk00000001/sig000000d4/CYMUXFAST_4047 ;
wire \i2/blk00000001/sig000000d4/CYAND_4046 ;
wire \i2/blk00000001/sig000000d4/FASTCARRY_4045 ;
wire \i2/blk00000001/sig000000d4/CYMUXG2_4044 ;
wire \i2/blk00000001/sig000000d4/CYMUXF2_4043 ;
wire \i2/blk00000001/sig000000d4/CY0G_4042 ;
wire \i2/blk00000001/sig000000d4/CYSELG_4034 ;
wire \i2/blk00000001/sig00000064 ;
wire \i2/blk00000001/sig000000d6/XORF_4101 ;
wire \i2/blk00000001/sig000000d6/CYINIT_4100 ;
wire \i2/blk00000001/sig000000d6/CY0F_4099 ;
wire \i2/blk00000001/sig00000062 ;
wire \i2/blk00000001/sig000000d6/XORG_4089 ;
wire \i2/blk00000001/sig00000061 ;
wire \i2/blk00000001/sig000000d6/CYSELF_4087 ;
wire \i2/blk00000001/sig000000d6/CYMUXFAST_4086 ;
wire \i2/blk00000001/sig000000d6/CYAND_4085 ;
wire \i2/blk00000001/sig000000d6/FASTCARRY_4084 ;
wire \i2/blk00000001/sig000000d6/CYMUXG2_4083 ;
wire \i2/blk00000001/sig000000d6/CYMUXF2_4082 ;
wire \i2/blk00000001/sig000000d6/CY0G_4081 ;
wire \i2/blk00000001/sig000000d6/CYSELG_4073 ;
wire \i2/blk00000001/sig00000060 ;
wire \i2/blk00000001/sig000000d8/XORF_4140 ;
wire \i2/blk00000001/sig000000d8/CYINIT_4139 ;
wire \i2/blk00000001/sig000000d8/CY0F_4138 ;
wire \i2/blk00000001/sig0000005e ;
wire \i2/blk00000001/sig000000d8/XORG_4128 ;
wire \i2/blk00000001/sig0000005d ;
wire \i2/blk00000001/sig000000d8/CYSELF_4126 ;
wire \i2/blk00000001/sig000000d8/CYMUXFAST_4125 ;
wire \i2/blk00000001/sig000000d8/CYAND_4124 ;
wire \i2/blk00000001/sig000000d8/FASTCARRY_4123 ;
wire \i2/blk00000001/sig000000d8/CYMUXG2_4122 ;
wire \i2/blk00000001/sig000000d8/CYMUXF2_4121 ;
wire \i2/blk00000001/sig000000d8/CY0G_4120 ;
wire \i2/blk00000001/sig000000d8/CYSELG_4112 ;
wire \i2/blk00000001/sig0000005c ;
wire \i2/blk00000001/sig000000da/XORF_4179 ;
wire \i2/blk00000001/sig000000da/CYINIT_4178 ;
wire \i2/blk00000001/sig000000da/CY0F_4177 ;
wire \i2/blk00000001/sig0000005a ;
wire \i2/blk00000001/sig000000da/XORG_4167 ;
wire \i2/blk00000001/sig00000059 ;
wire \i2/blk00000001/sig000000da/CYSELF_4165 ;
wire \i2/blk00000001/sig000000da/CYMUXFAST_4164 ;
wire \i2/blk00000001/sig000000da/CYAND_4163 ;
wire \i2/blk00000001/sig000000da/FASTCARRY_4162 ;
wire \i2/blk00000001/sig000000da/CYMUXG2_4161 ;
wire \i2/blk00000001/sig000000da/CYMUXF2_4160 ;
wire \i2/blk00000001/sig000000da/CY0G_4159 ;
wire \i2/blk00000001/sig000000da/CYSELG_4151 ;
wire \i2/blk00000001/sig00000058 ;
wire \i2/blk00000001/sig000000dc/XORF_4218 ;
wire \i2/blk00000001/sig000000dc/CYINIT_4217 ;
wire \i2/blk00000001/sig000000dc/CY0F_4216 ;
wire \i2/blk00000001/sig00000056 ;
wire \i2/blk00000001/sig000000dc/XORG_4206 ;
wire \i2/blk00000001/sig00000055 ;
wire \i2/blk00000001/sig000000dc/CYSELF_4204 ;
wire \i2/blk00000001/sig000000dc/CYMUXFAST_4203 ;
wire \i2/blk00000001/sig000000dc/CYAND_4202 ;
wire \i2/blk00000001/sig000000dc/FASTCARRY_4201 ;
wire \i2/blk00000001/sig000000dc/CYMUXG2_4200 ;
wire \i2/blk00000001/sig000000dc/CYMUXF2_4199 ;
wire \i2/blk00000001/sig000000dc/CY0G_4198 ;
wire \i2/blk00000001/sig000000dc/CYSELG_4190 ;
wire \i2/blk00000001/sig00000054 ;
wire \i2/blk00000001/sig000000de/XORF_4233 ;
wire \i2/blk00000001/sig000000de/CYINIT_4232 ;
wire \i2/blk00000001/sig00000052 ;
wire \i2/blk00000001/sig00000185/XORF_4266 ;
wire \i2/blk00000001/sig00000185/CYINIT_4265 ;
wire \i2/blk00000001/sig00000185/F ;
wire \i2/blk00000001/sig00000185/BXINV_4254 ;
wire \i2/blk00000001/sig00000185/XORG_4252 ;
wire \i2/blk00000001/sig00000185/CYMUXG_4251 ;
wire \i2/blk00000001/sig00000185/LOGIC_ONE_4250 ;
wire \i2/blk00000001/sig000001d7 ;
wire \i2/blk00000001/sig00000185/G ;
wire \i2/blk00000001/sig00000179/XORF_4298 ;
wire \i2/blk00000001/sig00000179/LOGIC_ONE_4297 ;
wire \i2/blk00000001/sig00000179/CYINIT_4296 ;
wire \i2/blk00000001/sig00000179/F ;
wire \i2/blk00000001/sig00000179/XORG_4284 ;
wire \i2/blk00000001/sig000001cb ;
wire \i2/blk00000001/sig00000179/G ;
wire \i2/blk00000001/sig00000163/XORF_4330 ;
wire \i2/blk00000001/sig00000163/LOGIC_ONE_4329 ;
wire \i2/blk00000001/sig00000163/CYINIT_4328 ;
wire \i2/blk00000001/sig00000163/F ;
wire \i2/blk00000001/sig00000163/XORG_4316 ;
wire \i2/blk00000001/sig000001bf ;
wire \i2/blk00000001/sig00000163/G ;
wire \i2/blk00000001/sig0000014d/XORF_4362 ;
wire \i2/blk00000001/sig0000014d/LOGIC_ONE_4361 ;
wire \i2/blk00000001/sig0000014d/CYINIT_4360 ;
wire \i2/blk00000001/sig0000014d/F ;
wire \i2/blk00000001/sig0000014d/XORG_4348 ;
wire \i2/blk00000001/sig000001b3 ;
wire \i2/blk00000001/sig0000014d/G ;
wire \i2/blk00000001/sig00000137/XORF_4403 ;
wire \i2/blk00000001/sig00000137/CYINIT_4402 ;
wire \i2/blk00000001/sig00000137/CY0F_4401 ;
wire \i2/blk00000001/sig000001fa ;
wire \i2/blk00000001/sig000000e3 ;
wire \i2/blk00000001/sig00000137/XORG_4390 ;
wire \i2/blk00000001/sig000001a7 ;
wire \i2/blk00000001/sig00000137/CYSELF_4388 ;
wire \i2/blk00000001/sig00000137/CYMUXFAST_4387 ;
wire \i2/blk00000001/sig00000137/CYAND_4386 ;
wire \i2/blk00000001/sig00000137/FASTCARRY_4385 ;
wire \i2/blk00000001/sig00000137/CYMUXG2_4384 ;
wire \i2/blk00000001/sig00000137/CYMUXF2_4383 ;
wire \i2/blk00000001/sig00000137/CY0G_4382 ;
wire \i2/blk00000001/sig000001f4 ;
wire \i2/blk00000001/sig00000137/CYSELG_4374 ;
wire \i2/blk00000001/sig000000e2 ;
wire \i2/blk00000001/sig00000121/XORF_4444 ;
wire \i2/blk00000001/sig00000121/CYINIT_4443 ;
wire \i2/blk00000001/sig00000121/CY0F_4442 ;
wire \i2/blk00000001/sig000001ee ;
wire \i2/blk00000001/sig000000e1 ;
wire \i2/blk00000001/sig00000121/XORG_4431 ;
wire \i2/blk00000001/sig0000019b ;
wire \i2/blk00000001/sig00000121/CYSELF_4429 ;
wire \i2/blk00000001/sig00000121/CYMUXFAST_4428 ;
wire \i2/blk00000001/sig00000121/CYAND_4427 ;
wire \i2/blk00000001/sig00000121/FASTCARRY_4426 ;
wire \i2/blk00000001/sig00000121/CYMUXG2_4425 ;
wire \i2/blk00000001/sig00000121/CYMUXF2_4424 ;
wire \i2/blk00000001/sig00000121/CY0G_4423 ;
wire \i2/blk00000001/sig000001e8 ;
wire \i2/blk00000001/sig00000121/CYSELG_4415 ;
wire \i2/blk00000001/sig000000e0 ;
wire \i2/blk00000001/sig000001da/XORF_4482 ;
wire \i2/blk00000001/sig000001da/CYINIT_4481 ;
wire \i2/blk00000001/sig000001da/CY0F_4480 ;
wire \i2/blk00000001/sig0000022c ;
wire \i2/blk00000001/sig000001da/CYSELF_4471 ;
wire \i2/blk00000001/sig000001da/F ;
wire \i2/blk00000001/sig000001da/BXINV_4469 ;
wire \i2/blk00000001/sig000001da/XORG_4467 ;
wire \i2/blk00000001/sig000001da/CYMUXG_4466 ;
wire \i2/blk00000001/sig000001db ;
wire \i2/blk00000001/sig000001da/CY0G_4464 ;
wire \i2/blk00000001/sig0000022b ;
wire \i2/blk00000001/sig000001da/CYSELG_4455 ;
wire \i2/blk00000001/sig000001da/G ;
wire \i2/blk00000001/sig00000186/XORF_4523 ;
wire \i2/blk00000001/sig00000186/CYINIT_4522 ;
wire \i2/blk00000001/sig00000186/CY0F_4521 ;
wire \i2/blk00000001/sig00000225 ;
wire \i2/blk00000001/sig00000186/F ;
wire \i2/blk00000001/sig00000186/XORG_4510 ;
wire \i2/blk00000001/sig000001d2 ;
wire \i2/blk00000001/sig00000186/CYSELF_4508 ;
wire \i2/blk00000001/sig00000186/CYMUXFAST_4507 ;
wire \i2/blk00000001/sig00000186/CYAND_4506 ;
wire \i2/blk00000001/sig00000186/FASTCARRY_4505 ;
wire \i2/blk00000001/sig00000186/CYMUXG2_4504 ;
wire \i2/blk00000001/sig00000186/CYMUXF2_4503 ;
wire \i2/blk00000001/sig00000186/CY0G_4502 ;
wire \i2/blk00000001/sig0000021f ;
wire \i2/blk00000001/sig00000186/CYSELG_4493 ;
wire \i2/blk00000001/sig00000186/G ;
wire \i2/blk00000001/sig0000016f/XORF_4564 ;
wire \i2/blk00000001/sig0000016f/CYINIT_4563 ;
wire \i2/blk00000001/sig0000016f/CY0F_4562 ;
wire \i2/blk00000001/sig00000219 ;
wire \i2/blk00000001/sig0000016f/F ;
wire \i2/blk00000001/sig0000016f/XORG_4551 ;
wire \i2/blk00000001/sig000001c6 ;
wire \i2/blk00000001/sig0000016f/CYSELF_4549 ;
wire \i2/blk00000001/sig0000016f/CYMUXFAST_4548 ;
wire \i2/blk00000001/sig0000016f/CYAND_4547 ;
wire \i2/blk00000001/sig0000016f/FASTCARRY_4546 ;
wire \i2/blk00000001/sig0000016f/CYMUXG2_4545 ;
wire \i2/blk00000001/sig0000016f/CYMUXF2_4544 ;
wire \i2/blk00000001/sig0000016f/CY0G_4543 ;
wire \i2/blk00000001/sig00000213 ;
wire \i2/blk00000001/sig0000016f/CYSELG_4534 ;
wire \i2/blk00000001/sig0000016f/G ;
wire \i2/blk00000001/sig00000159/XORF_4605 ;
wire \i2/blk00000001/sig00000159/CYINIT_4604 ;
wire \i2/blk00000001/sig00000159/CY0F_4603 ;
wire \i2/blk00000001/sig0000020d ;
wire \i2/blk00000001/sig00000159/F ;
wire \i2/blk00000001/sig00000159/XORG_4592 ;
wire \i2/blk00000001/sig000001ba ;
wire \i2/blk00000001/sig00000159/CYSELF_4590 ;
wire \i2/blk00000001/sig00000159/CYMUXFAST_4589 ;
wire \i2/blk00000001/sig00000159/CYAND_4588 ;
wire \i2/blk00000001/sig00000159/FASTCARRY_4587 ;
wire \i2/blk00000001/sig00000159/CYMUXG2_4586 ;
wire \i2/blk00000001/sig00000159/CYMUXF2_4585 ;
wire \i2/blk00000001/sig00000159/CY0G_4584 ;
wire \i2/blk00000001/sig00000207 ;
wire \i2/blk00000001/sig00000159/CYSELG_4575 ;
wire \i2/blk00000001/sig00000159/G ;
wire \i2/blk00000001/sig00000143/XORF_4646 ;
wire \i2/blk00000001/sig00000143/CYINIT_4645 ;
wire \i2/blk00000001/sig00000143/CY0F_4644 ;
wire \i2/blk00000001/sig00000201 ;
wire \i2/blk00000001/sig00000143/F ;
wire \i2/blk00000001/sig00000143/XORG_4634 ;
wire \i2/blk00000001/sig000001ae ;
wire \i2/blk00000001/sig00000143/CYSELF_4632 ;
wire \i2/blk00000001/sig00000143/CYMUXFAST_4631 ;
wire \i2/blk00000001/sig00000143/CYAND_4630 ;
wire \i2/blk00000001/sig00000143/FASTCARRY_4629 ;
wire \i2/blk00000001/sig00000143/CYMUXG2_4628 ;
wire \i2/blk00000001/sig00000143/CYMUXF2_4627 ;
wire \i2/blk00000001/sig00000143/CY0G_4626 ;
wire \i2/blk00000001/sig000001fb ;
wire \i2/blk00000001/sig00000143/CYSELG_4617 ;
wire \i2/blk00000001/sig00000143/G ;
wire \i2/blk00000001/sig0000012d/XORF_4687 ;
wire \i2/blk00000001/sig0000012d/CYINIT_4686 ;
wire \i2/blk00000001/sig0000012d/CY0F_4685 ;
wire \i2/blk00000001/sig000001f5 ;
wire \i2/blk00000001/sig0000012d/F ;
wire \i2/blk00000001/sig0000012d/XORG_4675 ;
wire \i2/blk00000001/sig000001a2 ;
wire \i2/blk00000001/sig0000012d/CYSELF_4673 ;
wire \i2/blk00000001/sig0000012d/CYMUXFAST_4672 ;
wire \i2/blk00000001/sig0000012d/CYAND_4671 ;
wire \i2/blk00000001/sig0000012d/FASTCARRY_4670 ;
wire \i2/blk00000001/sig0000012d/CYMUXG2_4669 ;
wire \i2/blk00000001/sig0000012d/CYMUXF2_4668 ;
wire \i2/blk00000001/sig0000012d/CY0G_4667 ;
wire \i2/blk00000001/sig000001ef ;
wire \i2/blk00000001/sig0000012d/CYSELG_4658 ;
wire \i2/blk00000001/sig0000012d/G ;
wire \i2/blk00000001/sig00000117/XORF_4719 ;
wire \i2/blk00000001/sig00000117/CYINIT_4718 ;
wire \i2/blk00000001/sig00000117/CY0F_4717 ;
wire \i2/blk00000001/sig000001e9 ;
wire \i2/blk00000001/sig00000117/CYSELF_4708 ;
wire \i2/blk00000001/sig00000117/F ;
wire \i2/blk00000001/sig00000117/XORG_4705 ;
wire \i2/blk00000001/sig00000196 ;
wire \i2/blk00000001/sig00000117/G ;
wire \i2/blk00000001/sig000001e3/XORF_4757 ;
wire \i2/blk00000001/sig000001e3/CYINIT_4756 ;
wire \i2/blk00000001/sig000001e3/CY0F_4755 ;
wire \i2/blk00000001/sig00000235 ;
wire \i2/blk00000001/sig000001e3/CYSELF_4746 ;
wire \i2/blk00000001/sig000001e3/F ;
wire \i2/blk00000001/sig000001e3/BXINV_4744 ;
wire \i2/blk00000001/sig000001e3/XORG_4742 ;
wire \i2/blk00000001/sig000001e3/CYMUXG_4741 ;
wire \i2/blk00000001/sig000001e4 ;
wire \i2/blk00000001/sig000001e3/CY0G_4739 ;
wire \i2/blk00000001/sig00000234 ;
wire \i2/blk00000001/sig000001e3/CYSELG_4730 ;
wire \i2/blk00000001/sig000001e3/G ;
wire \i2/blk00000001/sig0000018f/XORF_4798 ;
wire \i2/blk00000001/sig0000018f/CYINIT_4797 ;
wire \i2/blk00000001/sig0000018f/CY0F_4796 ;
wire \i2/blk00000001/sig00000228 ;
wire \i2/blk00000001/sig0000018f/F ;
wire \i2/blk00000001/sig0000018f/XORG_4785 ;
wire \i2/blk00000001/sig000001d5 ;
wire \i2/blk00000001/sig0000018f/CYSELF_4783 ;
wire \i2/blk00000001/sig0000018f/CYMUXFAST_4782 ;
wire \i2/blk00000001/sig0000018f/CYAND_4781 ;
wire \i2/blk00000001/sig0000018f/FASTCARRY_4780 ;
wire \i2/blk00000001/sig0000018f/CYMUXG2_4779 ;
wire \i2/blk00000001/sig0000018f/CYMUXF2_4778 ;
wire \i2/blk00000001/sig0000018f/CY0G_4777 ;
wire \i2/blk00000001/sig00000222 ;
wire \i2/blk00000001/sig0000018f/CYSELG_4768 ;
wire \i2/blk00000001/sig0000018f/G ;
wire \i2/blk00000001/sig00000175/XORF_4839 ;
wire \i2/blk00000001/sig00000175/CYINIT_4838 ;
wire \i2/blk00000001/sig00000175/CY0F_4837 ;
wire \i2/blk00000001/sig0000021c ;
wire \i2/blk00000001/sig00000175/F ;
wire \i2/blk00000001/sig00000175/XORG_4826 ;
wire \i2/blk00000001/sig000001c9 ;
wire \i2/blk00000001/sig00000175/CYSELF_4824 ;
wire \i2/blk00000001/sig00000175/CYMUXFAST_4823 ;
wire \i2/blk00000001/sig00000175/CYAND_4822 ;
wire \i2/blk00000001/sig00000175/FASTCARRY_4821 ;
wire \i2/blk00000001/sig00000175/CYMUXG2_4820 ;
wire \i2/blk00000001/sig00000175/CYMUXF2_4819 ;
wire \i2/blk00000001/sig00000175/CY0G_4818 ;
wire \i2/blk00000001/sig00000216 ;
wire \i2/blk00000001/sig00000175/CYSELG_4809 ;
wire \i2/blk00000001/sig00000175/G ;
wire \i2/blk00000001/sig0000015f/XORF_4880 ;
wire \i2/blk00000001/sig0000015f/CYINIT_4879 ;
wire \i2/blk00000001/sig0000015f/CY0F_4878 ;
wire \i2/blk00000001/sig00000210 ;
wire \i2/blk00000001/sig0000015f/F ;
wire \i2/blk00000001/sig0000015f/XORG_4867 ;
wire \i2/blk00000001/sig000001bd ;
wire \i2/blk00000001/sig0000015f/CYSELF_4865 ;
wire \i2/blk00000001/sig0000015f/CYMUXFAST_4864 ;
wire \i2/blk00000001/sig0000015f/CYAND_4863 ;
wire \i2/blk00000001/sig0000015f/FASTCARRY_4862 ;
wire \i2/blk00000001/sig0000015f/CYMUXG2_4861 ;
wire \i2/blk00000001/sig0000015f/CYMUXF2_4860 ;
wire \i2/blk00000001/sig0000015f/CY0G_4859 ;
wire \i2/blk00000001/sig0000020a ;
wire \i2/blk00000001/sig0000015f/CYSELG_4850 ;
wire \i2/blk00000001/sig0000015f/G ;
wire \i2/blk00000001/sig00000149/XORF_4921 ;
wire \i2/blk00000001/sig00000149/CYINIT_4920 ;
wire \i2/blk00000001/sig00000149/CY0F_4919 ;
wire \i2/blk00000001/sig00000204 ;
wire \i2/blk00000001/sig00000149/F ;
wire \i2/blk00000001/sig00000149/XORG_4909 ;
wire \i2/blk00000001/sig000001b1 ;
wire \i2/blk00000001/sig00000149/CYSELF_4907 ;
wire \i2/blk00000001/sig00000149/CYMUXFAST_4906 ;
wire \i2/blk00000001/sig00000149/CYAND_4905 ;
wire \i2/blk00000001/sig00000149/FASTCARRY_4904 ;
wire \i2/blk00000001/sig00000149/CYMUXG2_4903 ;
wire \i2/blk00000001/sig00000149/CYMUXF2_4902 ;
wire \i2/blk00000001/sig00000149/CY0G_4901 ;
wire \i2/blk00000001/sig000001fe ;
wire \i2/blk00000001/sig00000149/CYSELG_4892 ;
wire \i2/blk00000001/sig00000149/G ;
wire \i2/blk00000001/sig00000133/XORF_4962 ;
wire \i2/blk00000001/sig00000133/CYINIT_4961 ;
wire \i2/blk00000001/sig00000133/CY0F_4960 ;
wire \i2/blk00000001/sig000001f8 ;
wire \i2/blk00000001/sig00000133/F ;
wire \i2/blk00000001/sig00000133/XORG_4950 ;
wire \i2/blk00000001/sig000001a5 ;
wire \i2/blk00000001/sig00000133/CYSELF_4948 ;
wire \i2/blk00000001/sig00000133/CYMUXFAST_4947 ;
wire \i2/blk00000001/sig00000133/CYAND_4946 ;
wire \i2/blk00000001/sig00000133/FASTCARRY_4945 ;
wire \i2/blk00000001/sig00000133/CYMUXG2_4944 ;
wire \i2/blk00000001/sig00000133/CYMUXF2_4943 ;
wire \i2/blk00000001/sig00000133/CY0G_4942 ;
wire \i2/blk00000001/sig000001f2 ;
wire \i2/blk00000001/sig00000133/CYSELG_4933 ;
wire \i2/blk00000001/sig00000133/G ;
wire \i2/blk00000001/sig0000011d/XORF_4994 ;
wire \i2/blk00000001/sig0000011d/CYINIT_4993 ;
wire \i2/blk00000001/sig0000011d/CY0F_4992 ;
wire \i2/blk00000001/sig000001ec ;
wire \i2/blk00000001/sig0000011d/CYSELF_4983 ;
wire \i2/blk00000001/sig0000011d/F ;
wire \i2/blk00000001/sig0000011d/XORG_4980 ;
wire \i2/blk00000001/sig00000199 ;
wire \i2/blk00000001/sig0000011d/G ;
wire \i2/blk00000001/sig000001dd/XORF_5032 ;
wire \i2/blk00000001/sig000001dd/CYINIT_5031 ;
wire \i2/blk00000001/sig000001dd/CY0F_5030 ;
wire \i2/blk00000001/sig0000022f ;
wire \i2/blk00000001/sig000001dd/CYSELF_5021 ;
wire \i2/blk00000001/sig000001dd/F ;
wire \i2/blk00000001/sig000001dd/BXINV_5019 ;
wire \i2/blk00000001/sig000001dd/XORG_5017 ;
wire \i2/blk00000001/sig000001dd/CYMUXG_5016 ;
wire \i2/blk00000001/sig000001de ;
wire \i2/blk00000001/sig000001dd/CY0G_5014 ;
wire \i2/blk00000001/sig0000022e ;
wire \i2/blk00000001/sig000001dd/CYSELG_5005 ;
wire \i2/blk00000001/sig000001dd/G ;
wire \i2/blk00000001/sig00000189/XORF_5073 ;
wire \i2/blk00000001/sig00000189/CYINIT_5072 ;
wire \i2/blk00000001/sig00000189/CY0F_5071 ;
wire \i2/blk00000001/sig00000226 ;
wire \i2/blk00000001/sig00000189/F ;
wire \i2/blk00000001/sig00000189/XORG_5060 ;
wire \i2/blk00000001/sig000001d3 ;
wire \i2/blk00000001/sig00000189/CYSELF_5058 ;
wire \i2/blk00000001/sig00000189/CYMUXFAST_5057 ;
wire \i2/blk00000001/sig00000189/CYAND_5056 ;
wire \i2/blk00000001/sig00000189/FASTCARRY_5055 ;
wire \i2/blk00000001/sig00000189/CYMUXG2_5054 ;
wire \i2/blk00000001/sig00000189/CYMUXF2_5053 ;
wire \i2/blk00000001/sig00000189/CY0G_5052 ;
wire \i2/blk00000001/sig00000220 ;
wire \i2/blk00000001/sig00000189/CYSELG_5043 ;
wire \i2/blk00000001/sig00000189/G ;
wire \i2/blk00000001/sig00000171/XORF_5114 ;
wire \i2/blk00000001/sig00000171/CYINIT_5113 ;
wire \i2/blk00000001/sig00000171/CY0F_5112 ;
wire \i2/blk00000001/sig0000021a ;
wire \i2/blk00000001/sig00000171/F ;
wire \i2/blk00000001/sig00000171/XORG_5101 ;
wire \i2/blk00000001/sig000001c7 ;
wire \i2/blk00000001/sig00000171/CYSELF_5099 ;
wire \i2/blk00000001/sig00000171/CYMUXFAST_5098 ;
wire \i2/blk00000001/sig00000171/CYAND_5097 ;
wire \i2/blk00000001/sig00000171/FASTCARRY_5096 ;
wire \i2/blk00000001/sig00000171/CYMUXG2_5095 ;
wire \i2/blk00000001/sig00000171/CYMUXF2_5094 ;
wire \i2/blk00000001/sig00000171/CY0G_5093 ;
wire \i2/blk00000001/sig00000214 ;
wire \i2/blk00000001/sig00000171/CYSELG_5084 ;
wire \i2/blk00000001/sig00000171/G ;
wire \i2/blk00000001/sig0000015b/XORF_5155 ;
wire \i2/blk00000001/sig0000015b/CYINIT_5154 ;
wire \i2/blk00000001/sig0000015b/CY0F_5153 ;
wire \i2/blk00000001/sig0000020e ;
wire \i2/blk00000001/sig0000015b/F ;
wire \i2/blk00000001/sig0000015b/XORG_5142 ;
wire \i2/blk00000001/sig000001bb ;
wire \i2/blk00000001/sig0000015b/CYSELF_5140 ;
wire \i2/blk00000001/sig0000015b/CYMUXFAST_5139 ;
wire \i2/blk00000001/sig0000015b/CYAND_5138 ;
wire \i2/blk00000001/sig0000015b/FASTCARRY_5137 ;
wire \i2/blk00000001/sig0000015b/CYMUXG2_5136 ;
wire \i2/blk00000001/sig0000015b/CYMUXF2_5135 ;
wire \i2/blk00000001/sig0000015b/CY0G_5134 ;
wire \i2/blk00000001/sig00000208 ;
wire \i2/blk00000001/sig0000015b/CYSELG_5125 ;
wire \i2/blk00000001/sig0000015b/G ;
wire \i2/blk00000001/sig00000145/XORF_5196 ;
wire \i2/blk00000001/sig00000145/CYINIT_5195 ;
wire \i2/blk00000001/sig00000145/CY0F_5194 ;
wire \i2/blk00000001/sig00000202 ;
wire \i2/blk00000001/sig00000145/F ;
wire \i2/blk00000001/sig00000145/XORG_5184 ;
wire \i2/blk00000001/sig000001af ;
wire \i2/blk00000001/sig00000145/CYSELF_5182 ;
wire \i2/blk00000001/sig00000145/CYMUXFAST_5181 ;
wire \i2/blk00000001/sig00000145/CYAND_5180 ;
wire \i2/blk00000001/sig00000145/FASTCARRY_5179 ;
wire \i2/blk00000001/sig00000145/CYMUXG2_5178 ;
wire \i2/blk00000001/sig00000145/CYMUXF2_5177 ;
wire \i2/blk00000001/sig00000145/CY0G_5176 ;
wire \i2/blk00000001/sig000001fc ;
wire \i2/blk00000001/sig00000145/CYSELG_5167 ;
wire \i2/blk00000001/sig00000145/G ;
wire \i2/blk00000001/sig0000012f/XORF_5237 ;
wire \i2/blk00000001/sig0000012f/CYINIT_5236 ;
wire \i2/blk00000001/sig0000012f/CY0F_5235 ;
wire \i2/blk00000001/sig000001f6 ;
wire \i2/blk00000001/sig0000012f/F ;
wire \i2/blk00000001/sig0000012f/XORG_5225 ;
wire \i2/blk00000001/sig000001a3 ;
wire \i2/blk00000001/sig0000012f/CYSELF_5223 ;
wire \i2/blk00000001/sig0000012f/CYMUXFAST_5222 ;
wire \i2/blk00000001/sig0000012f/CYAND_5221 ;
wire \i2/blk00000001/sig0000012f/FASTCARRY_5220 ;
wire \i2/blk00000001/sig0000012f/CYMUXG2_5219 ;
wire \i2/blk00000001/sig0000012f/CYMUXF2_5218 ;
wire \i2/blk00000001/sig0000012f/CY0G_5217 ;
wire \i2/blk00000001/sig000001f0 ;
wire \i2/blk00000001/sig0000012f/CYSELG_5208 ;
wire \i2/blk00000001/sig0000012f/G ;
wire \i2/blk00000001/sig00000119/XORF_5269 ;
wire \i2/blk00000001/sig00000119/CYINIT_5268 ;
wire \i2/blk00000001/sig00000119/CY0F_5267 ;
wire \i2/blk00000001/sig000001ea ;
wire \i2/blk00000001/sig00000119/CYSELF_5258 ;
wire \i2/blk00000001/sig00000119/F ;
wire \i2/blk00000001/sig00000119/XORG_5255 ;
wire \i2/blk00000001/sig00000197 ;
wire \i2/blk00000001/sig00000119/G ;
wire \i2/blk00000001/sig000001e5/CYINIT_5302 ;
wire \i2/blk00000001/sig000001e5/CY0F_5301 ;
wire \i2/blk00000001/sig00000238 ;
wire \i2/blk00000001/sig000001e5/CYSELF_5292 ;
wire \i2/blk00000001/sig000001e5/F ;
wire \i2/blk00000001/sig000001e5/BXINV_5290 ;
wire \i2/blk00000001/sig000001e5/CYMUXG_5289 ;
wire \i2/blk00000001/sig000001e6 ;
wire \i2/blk00000001/sig000001e5/CY0G_5287 ;
wire \i2/blk00000001/sig00000237 ;
wire \i2/blk00000001/sig000001e5/CYSELG_5278 ;
wire \i2/blk00000001/sig000001e5/G ;
wire \i2/blk00000001/sig00000192/XORF_5342 ;
wire \i2/blk00000001/sig00000192/CYINIT_5341 ;
wire \i2/blk00000001/sig00000192/CY0F_5340 ;
wire \i2/blk00000001/sig00000229 ;
wire \i2/blk00000001/sig00000192/F ;
wire \i2/blk00000001/sig00000192/XORG_5329 ;
wire \i2/blk00000001/sig000001d6 ;
wire \i2/blk00000001/sig00000192/CYSELF_5327 ;
wire \i2/blk00000001/sig00000192/CYMUXFAST_5326 ;
wire \i2/blk00000001/sig00000192/CYAND_5325 ;
wire \i2/blk00000001/sig00000192/FASTCARRY_5324 ;
wire \i2/blk00000001/sig00000192/CYMUXG2_5323 ;
wire \i2/blk00000001/sig00000192/CYMUXF2_5322 ;
wire \i2/blk00000001/sig00000192/CY0G_5321 ;
wire \i2/blk00000001/sig00000223 ;
wire \i2/blk00000001/sig00000192/CYSELG_5312 ;
wire \i2/blk00000001/sig00000192/G ;
wire \i2/blk00000001/sig00000177/XORF_5383 ;
wire \i2/blk00000001/sig00000177/CYINIT_5382 ;
wire \i2/blk00000001/sig00000177/CY0F_5381 ;
wire \i2/blk00000001/sig0000021d ;
wire \i2/blk00000001/sig00000177/F ;
wire \i2/blk00000001/sig00000177/XORG_5370 ;
wire \i2/blk00000001/sig000001ca ;
wire \i2/blk00000001/sig00000177/CYSELF_5368 ;
wire \i2/blk00000001/sig00000177/CYMUXFAST_5367 ;
wire \i2/blk00000001/sig00000177/CYAND_5366 ;
wire \i2/blk00000001/sig00000177/FASTCARRY_5365 ;
wire \i2/blk00000001/sig00000177/CYMUXG2_5364 ;
wire \i2/blk00000001/sig00000177/CYMUXF2_5363 ;
wire \i2/blk00000001/sig00000177/CY0G_5362 ;
wire \i2/blk00000001/sig00000217 ;
wire \i2/blk00000001/sig00000177/CYSELG_5353 ;
wire \i2/blk00000001/sig00000177/G ;
wire \i2/blk00000001/sig00000161/XORF_5424 ;
wire \i2/blk00000001/sig00000161/CYINIT_5423 ;
wire \i2/blk00000001/sig00000161/CY0F_5422 ;
wire \i2/blk00000001/sig00000211 ;
wire \i2/blk00000001/sig00000161/F ;
wire \i2/blk00000001/sig00000161/XORG_5411 ;
wire \i2/blk00000001/sig000001be ;
wire \i2/blk00000001/sig00000161/CYSELF_5409 ;
wire \i2/blk00000001/sig00000161/CYMUXFAST_5408 ;
wire \i2/blk00000001/sig00000161/CYAND_5407 ;
wire \i2/blk00000001/sig00000161/FASTCARRY_5406 ;
wire \i2/blk00000001/sig00000161/CYMUXG2_5405 ;
wire \i2/blk00000001/sig00000161/CYMUXF2_5404 ;
wire \i2/blk00000001/sig00000161/CY0G_5403 ;
wire \i2/blk00000001/sig0000020b ;
wire \i2/blk00000001/sig00000161/CYSELG_5394 ;
wire \i2/blk00000001/sig00000161/G ;
wire \i2/blk00000001/sig0000014b/XORF_5465 ;
wire \i2/blk00000001/sig0000014b/CYINIT_5464 ;
wire \i2/blk00000001/sig0000014b/CY0F_5463 ;
wire \i2/blk00000001/sig00000205 ;
wire \i2/blk00000001/sig0000014b/F ;
wire \i2/blk00000001/sig0000014b/XORG_5452 ;
wire \i2/blk00000001/sig000001b2 ;
wire \i2/blk00000001/sig0000014b/CYSELF_5450 ;
wire \i2/blk00000001/sig0000014b/CYMUXFAST_5449 ;
wire \i2/blk00000001/sig0000014b/CYAND_5448 ;
wire \i2/blk00000001/sig0000014b/FASTCARRY_5447 ;
wire \i2/blk00000001/sig0000014b/CYMUXG2_5446 ;
wire \i2/blk00000001/sig0000014b/CYMUXF2_5445 ;
wire \i2/blk00000001/sig0000014b/CY0G_5444 ;
wire \i2/blk00000001/sig000001ff ;
wire \i2/blk00000001/sig0000014b/CYSELG_5435 ;
wire \i2/blk00000001/sig0000014b/G ;
wire \i2/blk00000001/sig00000135/XORF_5506 ;
wire \i2/blk00000001/sig00000135/CYINIT_5505 ;
wire \i2/blk00000001/sig00000135/CY0F_5504 ;
wire \i2/blk00000001/sig000001f9 ;
wire \i2/blk00000001/sig00000135/F ;
wire \i2/blk00000001/sig00000135/XORG_5493 ;
wire \i2/blk00000001/sig000001a6 ;
wire \i2/blk00000001/sig00000135/CYSELF_5491 ;
wire \i2/blk00000001/sig00000135/CYMUXFAST_5490 ;
wire \i2/blk00000001/sig00000135/CYAND_5489 ;
wire \i2/blk00000001/sig00000135/FASTCARRY_5488 ;
wire \i2/blk00000001/sig00000135/CYMUXG2_5487 ;
wire \i2/blk00000001/sig00000135/CYMUXF2_5486 ;
wire \i2/blk00000001/sig00000135/CY0G_5485 ;
wire \i2/blk00000001/sig000001f3 ;
wire \i2/blk00000001/sig00000135/CYSELG_5476 ;
wire \i2/blk00000001/sig00000135/G ;
wire \i2/blk00000001/sig0000011f/XORF_5538 ;
wire \i2/blk00000001/sig0000011f/CYINIT_5537 ;
wire \i2/blk00000001/sig0000011f/CY0F_5536 ;
wire \i2/blk00000001/sig000001ed ;
wire \i2/blk00000001/sig0000011f/CYSELF_5527 ;
wire \i2/blk00000001/sig0000011f/F ;
wire \i2/blk00000001/sig0000011f/XORG_5524 ;
wire \i2/blk00000001/sig0000019a ;
wire \i2/blk00000001/sig0000011f/G ;
wire \i2/blk00000001/sig000001e0/XORF_5576 ;
wire \i2/blk00000001/sig000001e0/CYINIT_5575 ;
wire \i2/blk00000001/sig000001e0/CY0F_5574 ;
wire \i2/blk00000001/sig00000232 ;
wire \i2/blk00000001/sig000001e0/CYSELF_5565 ;
wire \i2/blk00000001/sig000001e0/F ;
wire \i2/blk00000001/sig000001e0/BXINV_5563 ;
wire \i2/blk00000001/sig000001e0/XORG_5561 ;
wire \i2/blk00000001/sig000001e0/CYMUXG_5560 ;
wire \i2/blk00000001/sig000001e1 ;
wire \i2/blk00000001/sig000001e0/CY0G_5558 ;
wire \i2/blk00000001/sig00000231 ;
wire \i2/blk00000001/sig000001e0/CYSELG_5549 ;
wire \i2/blk00000001/sig000001e0/G ;
wire \i2/blk00000001/sig0000018c/XORF_5617 ;
wire \i2/blk00000001/sig0000018c/CYINIT_5616 ;
wire \i2/blk00000001/sig0000018c/CY0F_5615 ;
wire \i2/blk00000001/sig00000227 ;
wire \i2/blk00000001/sig0000018c/F ;
wire \i2/blk00000001/sig0000018c/XORG_5604 ;
wire \i2/blk00000001/sig000001d4 ;
wire \i2/blk00000001/sig0000018c/CYSELF_5602 ;
wire \i2/blk00000001/sig0000018c/CYMUXFAST_5601 ;
wire \i2/blk00000001/sig0000018c/CYAND_5600 ;
wire \i2/blk00000001/sig0000018c/FASTCARRY_5599 ;
wire \i2/blk00000001/sig0000018c/CYMUXG2_5598 ;
wire \i2/blk00000001/sig0000018c/CYMUXF2_5597 ;
wire \i2/blk00000001/sig0000018c/CY0G_5596 ;
wire \i2/blk00000001/sig00000221 ;
wire \i2/blk00000001/sig0000018c/CYSELG_5587 ;
wire \i2/blk00000001/sig0000018c/G ;
wire \i2/blk00000001/sig00000173/XORF_5658 ;
wire \i2/blk00000001/sig00000173/CYINIT_5657 ;
wire \i2/blk00000001/sig00000173/CY0F_5656 ;
wire \i2/blk00000001/sig0000021b ;
wire \i2/blk00000001/sig00000173/F ;
wire \i2/blk00000001/sig00000173/XORG_5645 ;
wire \i2/blk00000001/sig000001c8 ;
wire \i2/blk00000001/sig00000173/CYSELF_5643 ;
wire \i2/blk00000001/sig00000173/CYMUXFAST_5642 ;
wire \i2/blk00000001/sig00000173/CYAND_5641 ;
wire \i2/blk00000001/sig00000173/FASTCARRY_5640 ;
wire \i2/blk00000001/sig00000173/CYMUXG2_5639 ;
wire \i2/blk00000001/sig00000173/CYMUXF2_5638 ;
wire \i2/blk00000001/sig00000173/CY0G_5637 ;
wire \i2/blk00000001/sig00000215 ;
wire \i2/blk00000001/sig00000173/CYSELG_5628 ;
wire \i2/blk00000001/sig00000173/G ;
wire \i2/blk00000001/sig0000015d/XORF_5699 ;
wire \i2/blk00000001/sig0000015d/CYINIT_5698 ;
wire \i2/blk00000001/sig0000015d/CY0F_5697 ;
wire \i2/blk00000001/sig0000020f ;
wire \i2/blk00000001/sig0000015d/F ;
wire \i2/blk00000001/sig0000015d/XORG_5686 ;
wire \i2/blk00000001/sig000001bc ;
wire \i2/blk00000001/sig0000015d/CYSELF_5684 ;
wire \i2/blk00000001/sig0000015d/CYMUXFAST_5683 ;
wire \i2/blk00000001/sig0000015d/CYAND_5682 ;
wire \i2/blk00000001/sig0000015d/FASTCARRY_5681 ;
wire \i2/blk00000001/sig0000015d/CYMUXG2_5680 ;
wire \i2/blk00000001/sig0000015d/CYMUXF2_5679 ;
wire \i2/blk00000001/sig0000015d/CY0G_5678 ;
wire \i2/blk00000001/sig00000209 ;
wire \i2/blk00000001/sig0000015d/CYSELG_5669 ;
wire \i2/blk00000001/sig0000015d/G ;
wire \i2/blk00000001/sig00000147/XORF_5740 ;
wire \i2/blk00000001/sig00000147/CYINIT_5739 ;
wire \i2/blk00000001/sig00000147/CY0F_5738 ;
wire \i2/blk00000001/sig00000203 ;
wire \i2/blk00000001/sig00000147/F ;
wire \i2/blk00000001/sig00000147/XORG_5728 ;
wire \i2/blk00000001/sig000001b0 ;
wire \i2/blk00000001/sig00000147/CYSELF_5726 ;
wire \i2/blk00000001/sig00000147/CYMUXFAST_5725 ;
wire \i2/blk00000001/sig00000147/CYAND_5724 ;
wire \i2/blk00000001/sig00000147/FASTCARRY_5723 ;
wire \i2/blk00000001/sig00000147/CYMUXG2_5722 ;
wire \i2/blk00000001/sig00000147/CYMUXF2_5721 ;
wire \i2/blk00000001/sig00000147/CY0G_5720 ;
wire \i2/blk00000001/sig000001fd ;
wire \i2/blk00000001/sig00000147/CYSELG_5711 ;
wire \i2/blk00000001/sig00000147/G ;
wire \i2/blk00000001/sig00000131/XORF_5781 ;
wire \i2/blk00000001/sig00000131/CYINIT_5780 ;
wire \i2/blk00000001/sig00000131/CY0F_5779 ;
wire \i2/blk00000001/sig000001f7 ;
wire \i2/blk00000001/sig00000131/F ;
wire \i2/blk00000001/sig00000131/XORG_5769 ;
wire \i2/blk00000001/sig000001a4 ;
wire \i2/blk00000001/sig00000131/CYSELF_5767 ;
wire \i2/blk00000001/sig00000131/CYMUXFAST_5766 ;
wire \i2/blk00000001/sig00000131/CYAND_5765 ;
wire \i2/blk00000001/sig00000131/FASTCARRY_5764 ;
wire \i2/blk00000001/sig00000131/CYMUXG2_5763 ;
wire \i2/blk00000001/sig00000131/CYMUXF2_5762 ;
wire \i2/blk00000001/sig00000131/CY0G_5761 ;
wire \i2/blk00000001/sig000001f1 ;
wire \i2/blk00000001/sig00000131/CYSELG_5752 ;
wire \i2/blk00000001/sig00000131/G ;
wire \i2/blk00000001/sig0000011b/XORF_5813 ;
wire \i2/blk00000001/sig0000011b/CYINIT_5812 ;
wire \i2/blk00000001/sig0000011b/CY0F_5811 ;
wire \i2/blk00000001/sig000001eb ;
wire \i2/blk00000001/sig0000011b/CYSELF_5802 ;
wire \i2/blk00000001/sig0000011b/F ;
wire \i2/blk00000001/sig0000011b/XORG_5799 ;
wire \i2/blk00000001/sig00000198 ;
wire \i2/blk00000001/sig0000011b/G ;
wire \i2/blk00000001/sig000000c4/XORF_5849 ;
wire \i2/blk00000001/sig000000c4/CYINIT_5848 ;
wire \i2/blk00000001/sig000000c4/CY0F_5847 ;
wire \i2/blk00000001/sig000000c4/CYSELF_5839 ;
wire \i2/blk00000001/sig0000008d ;
wire \i2/blk00000001/sig000000c4/BXINV_5837 ;
wire \i2/blk00000001/sig000000c4/XORG_5835 ;
wire \i2/blk00000001/sig000000c4/CYMUXG_5834 ;
wire \i2/blk00000001/sig0000008c ;
wire \i2/blk00000001/sig000000c4/CY0G_5832 ;
wire \i2/blk00000001/sig000000c4/CYSELG_5824 ;
wire \i2/blk00000001/sig0000008b ;
wire \i2/blk00000001/sig000000c6/XORF_5888 ;
wire \i2/blk00000001/sig000000c6/CYINIT_5887 ;
wire \i2/blk00000001/sig000000c6/CY0F_5886 ;
wire \i2/blk00000001/sig00000089 ;
wire \i2/blk00000001/sig000000c6/XORG_5876 ;
wire \i2/blk00000001/sig00000088 ;
wire \i2/blk00000001/sig000000c6/CYSELF_5874 ;
wire \i2/blk00000001/sig000000c6/CYMUXFAST_5873 ;
wire \i2/blk00000001/sig000000c6/CYAND_5872 ;
wire \i2/blk00000001/sig000000c6/FASTCARRY_5871 ;
wire \i2/blk00000001/sig000000c6/CYMUXG2_5870 ;
wire \i2/blk00000001/sig000000c6/CYMUXF2_5869 ;
wire \i2/blk00000001/sig000000c6/CY0G_5868 ;
wire \i2/blk00000001/sig000000c6/CYSELG_5860 ;
wire \i2/blk00000001/sig00000087 ;
wire \i2/blk00000001/sig000000c8/XORF_5927 ;
wire \i2/blk00000001/sig000000c8/CYINIT_5926 ;
wire \i2/blk00000001/sig000000c8/CY0F_5925 ;
wire \i2/blk00000001/sig00000085 ;
wire \i2/blk00000001/sig000000c8/XORG_5915 ;
wire \i2/blk00000001/sig00000084 ;
wire \i2/blk00000001/sig000000c8/CYSELF_5913 ;
wire \i2/blk00000001/sig000000c8/CYMUXFAST_5912 ;
wire \i2/blk00000001/sig000000c8/CYAND_5911 ;
wire \i2/blk00000001/sig000000c8/FASTCARRY_5910 ;
wire \i2/blk00000001/sig000000c8/CYMUXG2_5909 ;
wire \i2/blk00000001/sig000000c8/CYMUXF2_5908 ;
wire \i2/blk00000001/sig000000c8/CY0G_5907 ;
wire \i2/blk00000001/sig000000c8/CYSELG_5899 ;
wire \i2/blk00000001/sig00000083 ;
wire \i2/blk00000001/sig000000ca/XORF_5966 ;
wire \i2/blk00000001/sig000000ca/CYINIT_5965 ;
wire \i2/blk00000001/sig000000ca/CY0F_5964 ;
wire \i2/blk00000001/sig00000081 ;
wire \i2/blk00000001/sig000000ca/XORG_5954 ;
wire \i2/blk00000001/sig00000080 ;
wire \i2/blk00000001/sig000000ca/CYSELF_5952 ;
wire \i2/blk00000001/sig000000ca/CYMUXFAST_5951 ;
wire \i2/blk00000001/sig000000ca/CYAND_5950 ;
wire \i2/blk00000001/sig000000ca/FASTCARRY_5949 ;
wire \i2/blk00000001/sig000000ca/CYMUXG2_5948 ;
wire \i2/blk00000001/sig000000ca/CYMUXF2_5947 ;
wire \i2/blk00000001/sig000000ca/CY0G_5946 ;
wire \i2/blk00000001/sig000000ca/CYSELG_5938 ;
wire \i2/blk00000001/sig0000007f ;
wire \i2/blk00000001/sig000000cc/XORF_6005 ;
wire \i2/blk00000001/sig000000cc/CYINIT_6004 ;
wire \i2/blk00000001/sig000000cc/CY0F_6003 ;
wire \i2/blk00000001/sig0000007d ;
wire \i2/blk00000001/sig000000cc/XORG_5993 ;
wire \i2/blk00000001/sig0000007c ;
wire \i2/blk00000001/sig000000cc/CYSELF_5991 ;
wire \i2/blk00000001/sig000000cc/CYMUXFAST_5990 ;
wire \i2/blk00000001/sig000000cc/CYAND_5989 ;
wire \i2/blk00000001/sig000000cc/FASTCARRY_5988 ;
wire \i2/blk00000001/sig000000cc/CYMUXG2_5987 ;
wire \i2/blk00000001/sig000000cc/CYMUXF2_5986 ;
wire \i2/blk00000001/sig000000cc/CY0G_5985 ;
wire \i2/blk00000001/sig000000cc/CYSELG_5977 ;
wire \i2/blk00000001/sig0000007b ;
wire \i2/blk00000001/sig000000ce/XORF_6044 ;
wire \i2/blk00000001/sig000000ce/CYINIT_6043 ;
wire \i2/blk00000001/sig000000ce/CY0F_6042 ;
wire \i2/blk00000001/sig00000079 ;
wire \i2/blk00000001/sig000000ce/XORG_6032 ;
wire \i2/blk00000001/sig00000078 ;
wire \i2/blk00000001/sig000000ce/CYSELF_6030 ;
wire \i2/blk00000001/sig000000ce/CYMUXFAST_6029 ;
wire \i2/blk00000001/sig000000ce/CYAND_6028 ;
wire \i2/blk00000001/sig000000ce/FASTCARRY_6027 ;
wire \i2/blk00000001/sig000000ce/CYMUXG2_6026 ;
wire \i2/blk00000001/sig000000ce/CYMUXF2_6025 ;
wire \i2/blk00000001/sig000000ce/CY0G_6024 ;
wire \i2/blk00000001/sig000000ce/CYSELG_6016 ;
wire \i2/blk00000001/sig00000077 ;
wire \i2/blk00000001/sig000000d0/XORF_6059 ;
wire \i2/blk00000001/sig000000d0/CYINIT_6058 ;
wire \i2/blk00000001/sig00000075 ;
wire \i2/blk00000001/sig000000eb/XORF_6095 ;
wire \i2/blk00000001/sig000000eb/CYINIT_6094 ;
wire \i2/blk00000001/sig000000eb/CY0F_6093 ;
wire \i2/blk00000001/sig000000eb/CYSELF_6085 ;
wire \i2/blk00000001/sig000000a8 ;
wire \i2/blk00000001/sig000000eb/BXINV_6083 ;
wire \i2/blk00000001/sig000000eb/XORG_6081 ;
wire \i2/blk00000001/sig000000eb/CYMUXG_6080 ;
wire \i2/blk00000001/sig000000a7 ;
wire \i2/blk00000001/sig000000eb/CY0G_6078 ;
wire \i2/blk00000001/sig000000eb/CYSELG_6070 ;
wire \i2/blk00000001/sig000000a6 ;
wire \i2/blk00000001/sig000000ed/XORF_6134 ;
wire \i2/blk00000001/sig000000ed/CYINIT_6133 ;
wire \i2/blk00000001/sig000000ed/CY0F_6132 ;
wire \i2/blk00000001/sig000000a4 ;
wire \i2/blk00000001/sig000000ed/XORG_6122 ;
wire \i2/blk00000001/sig000000a3 ;
wire \i2/blk00000001/sig000000ed/CYSELF_6120 ;
wire \i2/blk00000001/sig000000ed/CYMUXFAST_6119 ;
wire \i2/blk00000001/sig000000ed/CYAND_6118 ;
wire \i2/blk00000001/sig000000ed/FASTCARRY_6117 ;
wire \i2/blk00000001/sig000000ed/CYMUXG2_6116 ;
wire \i2/blk00000001/sig000000ed/CYMUXF2_6115 ;
wire \i2/blk00000001/sig000000ed/CY0G_6114 ;
wire \i2/blk00000001/sig000000ed/CYSELG_6106 ;
wire \i2/blk00000001/sig000000a2 ;
wire \i2/blk00000001/sig000000ef/XORF_6173 ;
wire \i2/blk00000001/sig000000ef/CYINIT_6172 ;
wire \i2/blk00000001/sig000000ef/CY0F_6171 ;
wire \i2/blk00000001/sig000000a0 ;
wire \i2/blk00000001/sig000000ef/XORG_6161 ;
wire \i2/blk00000001/sig0000009f ;
wire \i2/blk00000001/sig000000ef/CYSELF_6159 ;
wire \i2/blk00000001/sig000000ef/CYMUXFAST_6158 ;
wire \i2/blk00000001/sig000000ef/CYAND_6157 ;
wire \i2/blk00000001/sig000000ef/FASTCARRY_6156 ;
wire \i2/blk00000001/sig000000ef/CYMUXG2_6155 ;
wire \i2/blk00000001/sig000000ef/CYMUXF2_6154 ;
wire \i2/blk00000001/sig000000ef/CY0G_6153 ;
wire \i2/blk00000001/sig000000ef/CYSELG_6145 ;
wire \i2/blk00000001/sig0000009e ;
wire \i2/blk00000001/sig000000f1/XORF_6212 ;
wire \i2/blk00000001/sig000000f1/CYINIT_6211 ;
wire \i2/blk00000001/sig000000f1/CY0F_6210 ;
wire \i2/blk00000001/sig0000009c ;
wire \i2/blk00000001/sig000000f1/XORG_6200 ;
wire \i2/blk00000001/sig0000009b ;
wire \i2/blk00000001/sig000000f1/CYSELF_6198 ;
wire \i2/blk00000001/sig000000f1/CYMUXFAST_6197 ;
wire \i2/blk00000001/sig000000f1/CYAND_6196 ;
wire \i2/blk00000001/sig000000f1/FASTCARRY_6195 ;
wire \i2/blk00000001/sig000000f1/CYMUXG2_6194 ;
wire \i2/blk00000001/sig000000f1/CYMUXF2_6193 ;
wire \i2/blk00000001/sig000000f1/CY0G_6192 ;
wire \i2/blk00000001/sig000000f1/CYSELG_6184 ;
wire \i2/blk00000001/sig0000009a ;
wire \i2/blk00000001/sig000000f3/XORF_6251 ;
wire \i2/blk00000001/sig000000f3/CYINIT_6250 ;
wire \i2/blk00000001/sig000000f3/CY0F_6249 ;
wire \i2/blk00000001/sig00000098 ;
wire \i2/blk00000001/sig000000f3/XORG_6239 ;
wire \i2/blk00000001/sig00000097 ;
wire \i2/blk00000001/sig000000f3/CYSELF_6237 ;
wire \i2/blk00000001/sig000000f3/CYMUXFAST_6236 ;
wire \i2/blk00000001/sig000000f3/CYAND_6235 ;
wire \i2/blk00000001/sig000000f3/FASTCARRY_6234 ;
wire \i2/blk00000001/sig000000f3/CYMUXG2_6233 ;
wire \i2/blk00000001/sig000000f3/CYMUXF2_6232 ;
wire \i2/blk00000001/sig000000f3/CY0G_6231 ;
wire \i2/blk00000001/sig000000f3/CYSELG_6223 ;
wire \i2/blk00000001/sig00000096 ;
wire \i2/blk00000001/sig000000f5/XORF_6290 ;
wire \i2/blk00000001/sig000000f5/CYINIT_6289 ;
wire \i2/blk00000001/sig000000f5/CY0F_6288 ;
wire \i2/blk00000001/sig00000094 ;
wire \i2/blk00000001/sig000000f5/XORG_6278 ;
wire \i2/blk00000001/sig00000093 ;
wire \i2/blk00000001/sig000000f5/CYSELF_6276 ;
wire \i2/blk00000001/sig000000f5/CYMUXFAST_6275 ;
wire \i2/blk00000001/sig000000f5/CYAND_6274 ;
wire \i2/blk00000001/sig000000f5/FASTCARRY_6273 ;
wire \i2/blk00000001/sig000000f5/CYMUXG2_6272 ;
wire \i2/blk00000001/sig000000f5/CYMUXF2_6271 ;
wire \i2/blk00000001/sig000000f5/CY0G_6270 ;
wire \i2/blk00000001/sig000000f5/CYSELG_6262 ;
wire \i2/blk00000001/sig00000092 ;
wire \i2/blk00000001/sig000000f7/XORF_6321 ;
wire \i2/blk00000001/sig000000f7/CYINIT_6320 ;
wire \i2/blk00000001/sig000000f7/CY0F_6319 ;
wire \i2/blk00000001/sig000000f7/CYSELF_6311 ;
wire \i2/blk00000001/sig00000090 ;
wire \i2/blk00000001/sig000000f7/XORG_6308 ;
wire \i2/blk00000001/sig0000008f ;
wire \i2/blk00000001/sig0000008e ;
wire \i2/blk00000001/sig000000c0/CYINIT_6352 ;
wire \i2/blk00000001/sig000000c0/CY0F_6351 ;
wire \i2/blk00000001/sig000000c0/CYSELF_6343 ;
wire \i2/blk00000001/sig000000c3 ;
wire \i2/blk00000001/sig000000c0/BXINV_6341 ;
wire \i2/blk00000001/sig000000c0/CYMUXG_6340 ;
wire \i2/blk00000001/sig000000c2 ;
wire \i2/blk00000001/sig000000c0/CY0G_6338 ;
wire \i2/blk00000001/sig000000c0/CYSELG_6330 ;
wire \i2/blk00000001/sig000000c1 ;
wire \i2/blk00000001/sig000000f9/XORF_6390 ;
wire \i2/blk00000001/sig000000f9/CYINIT_6389 ;
wire \i2/blk00000001/sig000000f9/CY0F_6388 ;
wire \i2/blk00000001/sig000000bf ;
wire \i2/blk00000001/sig000000f9/XORG_6378 ;
wire \i2/blk00000001/sig000000be ;
wire \i2/blk00000001/sig000000f9/CYSELF_6376 ;
wire \i2/blk00000001/sig000000f9/CYMUXFAST_6375 ;
wire \i2/blk00000001/sig000000f9/CYAND_6374 ;
wire \i2/blk00000001/sig000000f9/FASTCARRY_6373 ;
wire \i2/blk00000001/sig000000f9/CYMUXG2_6372 ;
wire \i2/blk00000001/sig000000f9/CYMUXF2_6371 ;
wire \i2/blk00000001/sig000000f9/CY0G_6370 ;
wire \i2/blk00000001/sig000000f9/CYSELG_6362 ;
wire \i2/blk00000001/sig000000bd ;
wire \i2/blk00000001/sig000000fb/XORF_6429 ;
wire \i2/blk00000001/sig000000fb/CYINIT_6428 ;
wire \i2/blk00000001/sig000000fb/CY0F_6427 ;
wire \i2/blk00000001/sig000000bb ;
wire \i2/blk00000001/sig000000fb/XORG_6417 ;
wire \i2/blk00000001/sig000000ba ;
wire \i2/blk00000001/sig000000fb/CYSELF_6415 ;
wire \i2/blk00000001/sig000000fb/CYMUXFAST_6414 ;
wire \i2/blk00000001/sig000000fb/CYAND_6413 ;
wire \i2/blk00000001/sig000000fb/FASTCARRY_6412 ;
wire \i2/blk00000001/sig000000fb/CYMUXG2_6411 ;
wire \i2/blk00000001/sig000000fb/CYMUXF2_6410 ;
wire \i2/blk00000001/sig000000fb/CY0G_6409 ;
wire \i2/blk00000001/sig000000fb/CYSELG_6401 ;
wire \i2/blk00000001/sig000000b9 ;
wire \i2/blk00000001/sig000000fd/XORF_6468 ;
wire \i2/blk00000001/sig000000fd/CYINIT_6467 ;
wire \i2/blk00000001/sig000000fd/CY0F_6466 ;
wire \i2/blk00000001/sig000000b7 ;
wire \i2/blk00000001/sig000000fd/XORG_6456 ;
wire \i2/blk00000001/sig000000b6 ;
wire \i2/blk00000001/sig000000fd/CYSELF_6454 ;
wire \i2/blk00000001/sig000000fd/CYMUXFAST_6453 ;
wire \i2/blk00000001/sig000000fd/CYAND_6452 ;
wire \i2/blk00000001/sig000000fd/FASTCARRY_6451 ;
wire \i2/blk00000001/sig000000fd/CYMUXG2_6450 ;
wire \i2/blk00000001/sig000000fd/CYMUXF2_6449 ;
wire \i2/blk00000001/sig000000fd/CY0G_6448 ;
wire \i2/blk00000001/sig000000fd/CYSELG_6440 ;
wire \i2/blk00000001/sig000000b5 ;
wire \i2/blk00000001/sig000000ff/XORF_6507 ;
wire \i2/blk00000001/sig000000ff/CYINIT_6506 ;
wire \i2/blk00000001/sig000000ff/CY0F_6505 ;
wire \i2/blk00000001/sig000000b3 ;
wire \i2/blk00000001/sig000000ff/XORG_6495 ;
wire \i2/blk00000001/sig000000b2 ;
wire \i2/blk00000001/sig000000ff/CYSELF_6493 ;
wire \i2/blk00000001/sig000000ff/CYMUXFAST_6492 ;
wire \i2/blk00000001/sig000000ff/CYAND_6491 ;
wire \i2/blk00000001/sig000000ff/FASTCARRY_6490 ;
wire \i2/blk00000001/sig000000ff/CYMUXG2_6489 ;
wire \i2/blk00000001/sig000000ff/CYMUXF2_6488 ;
wire \i2/blk00000001/sig000000ff/CY0G_6487 ;
wire \i2/blk00000001/sig000000ff/CYSELG_6479 ;
wire \i2/blk00000001/sig000000b1 ;
wire \i2/blk00000001/sig00000101/XORF_6546 ;
wire \i2/blk00000001/sig00000101/CYINIT_6545 ;
wire \i2/blk00000001/sig00000101/CY0F_6544 ;
wire \i2/blk00000001/sig000000af ;
wire \i2/blk00000001/sig00000101/XORG_6534 ;
wire \i2/blk00000001/sig000000ae ;
wire \i2/blk00000001/sig00000101/CYSELF_6532 ;
wire \i2/blk00000001/sig00000101/CYMUXFAST_6531 ;
wire \i2/blk00000001/sig00000101/CYAND_6530 ;
wire \i2/blk00000001/sig00000101/FASTCARRY_6529 ;
wire \i2/blk00000001/sig00000101/CYMUXG2_6528 ;
wire \i2/blk00000001/sig00000101/CYMUXF2_6527 ;
wire \i2/blk00000001/sig00000101/CY0G_6526 ;
wire \i2/blk00000001/sig00000101/CYSELG_6518 ;
wire \i2/blk00000001/sig000000ad ;
wire \i2/blk00000001/sig00000103/XORF_6577 ;
wire \i2/blk00000001/sig00000103/CYINIT_6576 ;
wire \i2/blk00000001/sig00000103/CY0F_6575 ;
wire \i2/blk00000001/sig00000103/CYSELF_6567 ;
wire \i2/blk00000001/sig000000ab ;
wire \i2/blk00000001/sig00000103/XORG_6564 ;
wire \i2/blk00000001/sig000000aa ;
wire \i2/blk00000001/sig000000a9 ;
wire \Madd_s2_Madd_cy<1>/CYINIT_6608 ;
wire \Madd_s2_Madd_cy<1>/CY0F_6607 ;
wire \Madd_s2_Madd_cy<1>/CYSELF_6599 ;
wire \Madd_s2_Madd_lut[0] ;
wire \Madd_s2_Madd_cy<1>/CYMUXG_6596 ;
wire \Madd_s2_Madd_cy[0] ;
wire \Madd_s2_Madd_cy<1>/LOGIC_ZERO_6594 ;
wire \Madd_s2_Madd_cy<1>/CYSELG_6587 ;
wire Madd_s2R;
wire \y_0_OBUF/XORF_6646 ;
wire \y_0_OBUF/CYINIT_6645 ;
wire \y_0_OBUF/CY0F_6644 ;
wire \Madd_s2_Madd_lut[2] ;
wire \y_0_OBUF/XORG_6636 ;
wire \Madd_s2_Madd_cy[2] ;
wire \y_0_OBUF/CYSELF_6634 ;
wire \y_0_OBUF/CYMUXFAST_6633 ;
wire \y_0_OBUF/CYAND_6632 ;
wire \y_0_OBUF/FASTCARRY_6631 ;
wire \y_0_OBUF/CYMUXG2_6630 ;
wire \y_0_OBUF/CYMUXF2_6629 ;
wire \y_0_OBUF/CY0G_6628 ;
wire \y_0_OBUF/CYSELG_6622 ;
wire \Madd_s2_Madd_lut[3] ;
wire \y_2_OBUF/XORF_6685 ;
wire \y_2_OBUF/CYINIT_6684 ;
wire \y_2_OBUF/CY0F_6683 ;
wire \Madd_s2_Madd_lut[4] ;
wire \y_2_OBUF/XORG_6675 ;
wire \Madd_s2_Madd_cy[4] ;
wire \y_2_OBUF/CYSELF_6673 ;
wire \y_2_OBUF/CYMUXFAST_6672 ;
wire \y_2_OBUF/CYAND_6671 ;
wire \y_2_OBUF/FASTCARRY_6670 ;
wire \y_2_OBUF/CYMUXG2_6669 ;
wire \y_2_OBUF/CYMUXF2_6668 ;
wire \y_2_OBUF/CY0G_6667 ;
wire \y_2_OBUF/CYSELG_6661 ;
wire \Madd_s2_Madd_lut[5] ;
wire \y_4_OBUF/XORF_6724 ;
wire \y_4_OBUF/CYINIT_6723 ;
wire \y_4_OBUF/CY0F_6722 ;
wire \Madd_s2_Madd_lut[6] ;
wire \y_4_OBUF/XORG_6714 ;
wire \Madd_s2_Madd_cy[6] ;
wire \y_4_OBUF/CYSELF_6712 ;
wire \y_4_OBUF/CYMUXFAST_6711 ;
wire \y_4_OBUF/CYAND_6710 ;
wire \y_4_OBUF/FASTCARRY_6709 ;
wire \y_4_OBUF/CYMUXG2_6708 ;
wire \y_4_OBUF/CYMUXF2_6707 ;
wire \y_4_OBUF/CY0G_6706 ;
wire \y_4_OBUF/CYSELG_6700 ;
wire \Madd_s2_Madd_lut[7] ;
wire \y_6_OBUF/XORF_6763 ;
wire \y_6_OBUF/CYINIT_6762 ;
wire \y_6_OBUF/CY0F_6761 ;
wire \Madd_s2_Madd_lut[8] ;
wire \y_6_OBUF/XORG_6753 ;
wire \Madd_s2_Madd_cy[8] ;
wire \y_6_OBUF/CYSELF_6751 ;
wire \y_6_OBUF/CYMUXFAST_6750 ;
wire \y_6_OBUF/CYAND_6749 ;
wire \y_6_OBUF/FASTCARRY_6748 ;
wire \y_6_OBUF/CYMUXG2_6747 ;
wire \y_6_OBUF/CYMUXF2_6746 ;
wire \y_6_OBUF/CY0G_6745 ;
wire \y_6_OBUF/CYSELG_6739 ;
wire \Madd_s2_Madd_lut[9] ;
wire \y_8_OBUF/XORF_6794 ;
wire \y_8_OBUF/CYINIT_6793 ;
wire \y_8_OBUF/CY0F_6792 ;
wire \y_8_OBUF/CYSELF_6786 ;
wire \Madd_s2_Madd_lut[10] ;
wire \y_8_OBUF/XORG_6783 ;
wire \Madd_s2_Madd_cy[10] ;
wire \Madd_s2_Madd_lut[11] ;
wire \i1/blk00000001/sig0000004e/CYINIT_6825 ;
wire \i1/blk00000001/sig0000004e/CY0F_6824 ;
wire \i1/blk00000001/sig0000004e/CYSELF_6816 ;
wire \i1/blk00000001/sig00000051 ;
wire \i1/blk00000001/sig0000004e/BXINV_6814 ;
wire \i1/blk00000001/sig0000004e/CYMUXG_6813 ;
wire \i1/blk00000001/sig00000050 ;
wire \i1/blk00000001/sig0000004e/CY0G_6811 ;
wire \i1/blk00000001/sig0000004e/CYSELG_6803 ;
wire \i1/blk00000001/sig0000004f ;
wire \t1<11>/CYINIT_6861 ;
wire \t1<11>/CY0F_6860 ;
wire \i1/blk00000001/sig0000004d ;
wire \t1<11>/XORG_6850 ;
wire \i1/blk00000001/sig0000004c ;
wire \t1<11>/CYSELF_6848 ;
wire \t1<11>/CYMUXFAST_6847 ;
wire \t1<11>/CYAND_6846 ;
wire \t1<11>/FASTCARRY_6845 ;
wire \t1<11>/CYMUXG2_6844 ;
wire \t1<11>/CYMUXF2_6843 ;
wire \t1<11>/CY0G_6842 ;
wire \t1<11>/CYSELG_6834 ;
wire \i1/blk00000001/sig0000004b ;
wire \t1<12>/XORF_6899 ;
wire \t1<12>/CYINIT_6898 ;
wire \t1<12>/CY0F_6897 ;
wire \i1/blk00000001/sig00000049 ;
wire \t1<12>/XORG_6887 ;
wire \i1/blk00000001/sig00000048 ;
wire \t1<12>/CYSELF_6885 ;
wire \t1<12>/CYMUXFAST_6884 ;
wire \t1<12>/CYAND_6883 ;
wire \t1<12>/FASTCARRY_6882 ;
wire \t1<12>/CYMUXG2_6881 ;
wire \t1<12>/CYMUXF2_6880 ;
wire \t1<12>/CY0G_6879 ;
wire \t1<12>/CYSELG_6871 ;
wire \i1/blk00000001/sig00000047 ;
wire \t1<14>/XORF_6938 ;
wire \t1<14>/CYINIT_6937 ;
wire \t1<14>/CY0F_6936 ;
wire \i1/blk00000001/sig00000045 ;
wire \t1<14>/XORG_6926 ;
wire \i1/blk00000001/sig00000044 ;
wire \t1<14>/CYSELF_6924 ;
wire \t1<14>/CYMUXFAST_6923 ;
wire \t1<14>/CYAND_6922 ;
wire \t1<14>/FASTCARRY_6921 ;
wire \t1<14>/CYMUXG2_6920 ;
wire \t1<14>/CYMUXF2_6919 ;
wire \t1<14>/CY0G_6918 ;
wire \t1<14>/CYSELG_6910 ;
wire \i1/blk00000001/sig00000043 ;
wire \t1<16>/XORF_6977 ;
wire \t1<16>/CYINIT_6976 ;
wire \t1<16>/CY0F_6975 ;
wire \i1/blk00000001/sig00000041 ;
wire \t1<16>/XORG_6965 ;
wire \i1/blk00000001/sig00000040 ;
wire \t1<16>/CYSELF_6963 ;
wire \t1<16>/CYMUXFAST_6962 ;
wire \t1<16>/CYAND_6961 ;
wire \t1<16>/FASTCARRY_6960 ;
wire \t1<16>/CYMUXG2_6959 ;
wire \t1<16>/CYMUXF2_6958 ;
wire \t1<16>/CY0G_6957 ;
wire \t1<16>/CYSELG_6949 ;
wire \i1/blk00000001/sig0000003f ;
wire \t1<18>/XORF_7016 ;
wire \t1<18>/CYINIT_7015 ;
wire \t1<18>/CY0F_7014 ;
wire \i1/blk00000001/sig0000003d ;
wire \t1<18>/XORG_7004 ;
wire \i1/blk00000001/sig0000003c ;
wire \t1<18>/CYSELF_7002 ;
wire \t1<18>/CYMUXFAST_7001 ;
wire \t1<18>/CYAND_7000 ;
wire \t1<18>/FASTCARRY_6999 ;
wire \t1<18>/CYMUXG2_6998 ;
wire \t1<18>/CYMUXF2_6997 ;
wire \t1<18>/CY0G_6996 ;
wire \t1<18>/CYSELG_6988 ;
wire \i1/blk00000001/sig0000003b ;
wire \t1<20>/XORF_7055 ;
wire \t1<20>/CYINIT_7054 ;
wire \t1<20>/CY0F_7053 ;
wire \i1/blk00000001/sig00000039 ;
wire \t1<20>/XORG_7043 ;
wire \i1/blk00000001/sig00000038 ;
wire \t1<20>/CYSELF_7041 ;
wire \t1<20>/CYMUXFAST_7040 ;
wire \t1<20>/CYAND_7039 ;
wire \t1<20>/FASTCARRY_7038 ;
wire \t1<20>/CYMUXG2_7037 ;
wire \t1<20>/CYMUXF2_7036 ;
wire \t1<20>/CY0G_7035 ;
wire \t1<20>/CYSELG_7027 ;
wire \i1/blk00000001/sig00000037 ;
wire \t1<22>/XORF_7070 ;
wire \t1<22>/CYINIT_7069 ;
wire \i1/blk00000001/sig00000035 ;
wire \i1/blk00000001/sig0000006f/CYINIT_7101 ;
wire \i1/blk00000001/sig0000006f/CY0F_7100 ;
wire \i1/blk00000001/sig0000006f/CYSELF_7092 ;
wire \i1/blk00000001/sig00000072 ;
wire \i1/blk00000001/sig0000006f/BXINV_7090 ;
wire \i1/blk00000001/sig0000006f/CYMUXG_7089 ;
wire \i1/blk00000001/sig00000071 ;
wire \i1/blk00000001/sig0000006f/CY0G_7087 ;
wire \i1/blk00000001/sig0000006f/CYSELG_7079 ;
wire \i1/blk00000001/sig00000070 ;
wire \i1/blk00000001/sig0000006b/CY0F_7132 ;
wire \i1/blk00000001/sig0000006e ;
wire \i1/blk00000001/sig0000006b/CYSELF_7123 ;
wire \i1/blk00000001/sig0000006b/CYMUXFAST_7122 ;
wire \i1/blk00000001/sig0000006b/CYAND_7121 ;
wire \i1/blk00000001/sig0000006b/FASTCARRY_7120 ;
wire \i1/blk00000001/sig0000006b/CYMUXG2_7119 ;
wire \i1/blk00000001/sig0000006b/CYMUXF2_7118 ;
wire \i1/blk00000001/sig0000006b/CY0G_7117 ;
wire \i1/blk00000001/sig0000006b/CYSELG_7109 ;
wire \i1/blk00000001/sig0000006c ;
wire \i1/blk00000001/sig000000d2/XORF_7170 ;
wire \i1/blk00000001/sig000000d2/CYINIT_7169 ;
wire \i1/blk00000001/sig000000d2/CY0F_7168 ;
wire \i1/blk00000001/sig0000006a ;
wire \i1/blk00000001/sig000000d2/XORG_7158 ;
wire \i1/blk00000001/sig00000069 ;
wire \i1/blk00000001/sig000000d2/CYSELF_7156 ;
wire \i1/blk00000001/sig000000d2/CYMUXFAST_7155 ;
wire \i1/blk00000001/sig000000d2/CYAND_7154 ;
wire \i1/blk00000001/sig000000d2/FASTCARRY_7153 ;
wire \i1/blk00000001/sig000000d2/CYMUXG2_7152 ;
wire \i1/blk00000001/sig000000d2/CYMUXF2_7151 ;
wire \i1/blk00000001/sig000000d2/CY0G_7150 ;
wire \i1/blk00000001/sig000000d2/CYSELG_7142 ;
wire \i1/blk00000001/sig00000068 ;
wire \i1/blk00000001/sig000000d4/XORF_7209 ;
wire \i1/blk00000001/sig000000d4/CYINIT_7208 ;
wire \i1/blk00000001/sig000000d4/CY0F_7207 ;
wire \i1/blk00000001/sig00000066 ;
wire \i1/blk00000001/sig000000d4/XORG_7197 ;
wire \i1/blk00000001/sig00000065 ;
wire \i1/blk00000001/sig000000d4/CYSELF_7195 ;
wire \i1/blk00000001/sig000000d4/CYMUXFAST_7194 ;
wire \i1/blk00000001/sig000000d4/CYAND_7193 ;
wire \i1/blk00000001/sig000000d4/FASTCARRY_7192 ;
wire \i1/blk00000001/sig000000d4/CYMUXG2_7191 ;
wire \i1/blk00000001/sig000000d4/CYMUXF2_7190 ;
wire \i1/blk00000001/sig000000d4/CY0G_7189 ;
wire \i1/blk00000001/sig000000d4/CYSELG_7181 ;
wire \i1/blk00000001/sig00000064 ;
wire \i1/blk00000001/sig000000d6/XORF_7248 ;
wire \i1/blk00000001/sig000000d6/CYINIT_7247 ;
wire \i1/blk00000001/sig000000d6/CY0F_7246 ;
wire \i1/blk00000001/sig00000062 ;
wire \i1/blk00000001/sig000000d6/XORG_7236 ;
wire \i1/blk00000001/sig00000061 ;
wire \i1/blk00000001/sig000000d6/CYSELF_7234 ;
wire \i1/blk00000001/sig000000d6/CYMUXFAST_7233 ;
wire \i1/blk00000001/sig000000d6/CYAND_7232 ;
wire \i1/blk00000001/sig000000d6/FASTCARRY_7231 ;
wire \i1/blk00000001/sig000000d6/CYMUXG2_7230 ;
wire \i1/blk00000001/sig000000d6/CYMUXF2_7229 ;
wire \i1/blk00000001/sig000000d6/CY0G_7228 ;
wire \i1/blk00000001/sig000000d6/CYSELG_7220 ;
wire \i1/blk00000001/sig00000060 ;
wire \i1/blk00000001/sig000000d8/XORF_7287 ;
wire \i1/blk00000001/sig000000d8/CYINIT_7286 ;
wire \i1/blk00000001/sig000000d8/CY0F_7285 ;
wire \i1/blk00000001/sig0000005e ;
wire \i1/blk00000001/sig000000d8/XORG_7275 ;
wire \i1/blk00000001/sig0000005d ;
wire \i1/blk00000001/sig000000d8/CYSELF_7273 ;
wire \i1/blk00000001/sig000000d8/CYMUXFAST_7272 ;
wire \i1/blk00000001/sig000000d8/CYAND_7271 ;
wire \i1/blk00000001/sig000000d8/FASTCARRY_7270 ;
wire \i1/blk00000001/sig000000d8/CYMUXG2_7269 ;
wire \i1/blk00000001/sig000000d8/CYMUXF2_7268 ;
wire \i1/blk00000001/sig000000d8/CY0G_7267 ;
wire \i1/blk00000001/sig000000d8/CYSELG_7259 ;
wire \i1/blk00000001/sig0000005c ;
wire \i1/blk00000001/sig000000da/XORF_7326 ;
wire \i1/blk00000001/sig000000da/CYINIT_7325 ;
wire \i1/blk00000001/sig000000da/CY0F_7324 ;
wire \i1/blk00000001/sig0000005a ;
wire \i1/blk00000001/sig000000da/XORG_7314 ;
wire \i1/blk00000001/sig00000059 ;
wire \i1/blk00000001/sig000000da/CYSELF_7312 ;
wire \i1/blk00000001/sig000000da/CYMUXFAST_7311 ;
wire \i1/blk00000001/sig000000da/CYAND_7310 ;
wire \i1/blk00000001/sig000000da/FASTCARRY_7309 ;
wire \i1/blk00000001/sig000000da/CYMUXG2_7308 ;
wire \i1/blk00000001/sig000000da/CYMUXF2_7307 ;
wire \i1/blk00000001/sig000000da/CY0G_7306 ;
wire \i1/blk00000001/sig000000da/CYSELG_7298 ;
wire \i1/blk00000001/sig00000058 ;
wire \i1/blk00000001/sig000000dc/XORF_7365 ;
wire \i1/blk00000001/sig000000dc/CYINIT_7364 ;
wire \i1/blk00000001/sig000000dc/CY0F_7363 ;
wire \i1/blk00000001/sig00000056 ;
wire \i1/blk00000001/sig000000dc/XORG_7353 ;
wire \i1/blk00000001/sig00000055 ;
wire \i1/blk00000001/sig000000dc/CYSELF_7351 ;
wire \i1/blk00000001/sig000000dc/CYMUXFAST_7350 ;
wire \i1/blk00000001/sig000000dc/CYAND_7349 ;
wire \i1/blk00000001/sig000000dc/FASTCARRY_7348 ;
wire \i1/blk00000001/sig000000dc/CYMUXG2_7347 ;
wire \i1/blk00000001/sig000000dc/CYMUXF2_7346 ;
wire \i1/blk00000001/sig000000dc/CY0G_7345 ;
wire \i1/blk00000001/sig000000dc/CYSELG_7337 ;
wire \i1/blk00000001/sig00000054 ;
wire \i1/blk00000001/sig000000de/XORF_7380 ;
wire \i1/blk00000001/sig000000de/CYINIT_7379 ;
wire \i1/blk00000001/sig00000052 ;
wire \i1/blk00000001/sig00000185/XORF_7413 ;
wire \i1/blk00000001/sig00000185/CYINIT_7412 ;
wire \i1/blk00000001/sig00000185/F ;
wire \i1/blk00000001/sig00000185/BXINV_7401 ;
wire \i1/blk00000001/sig00000185/XORG_7399 ;
wire \i1/blk00000001/sig00000185/CYMUXG_7398 ;
wire \i1/blk00000001/sig00000185/LOGIC_ONE_7397 ;
wire \i1/blk00000001/sig000001d7 ;
wire \i1/blk00000001/sig00000185/G ;
wire \i1/blk00000001/sig00000179/XORF_7445 ;
wire \i1/blk00000001/sig00000179/LOGIC_ONE_7444 ;
wire \i1/blk00000001/sig00000179/CYINIT_7443 ;
wire \i1/blk00000001/sig00000179/F ;
wire \i1/blk00000001/sig00000179/XORG_7431 ;
wire \i1/blk00000001/sig000001cb ;
wire \i1/blk00000001/sig00000179/G ;
wire \i1/blk00000001/sig00000163/XORF_7477 ;
wire \i1/blk00000001/sig00000163/LOGIC_ONE_7476 ;
wire \i1/blk00000001/sig00000163/CYINIT_7475 ;
wire \i1/blk00000001/sig00000163/F ;
wire \i1/blk00000001/sig00000163/XORG_7463 ;
wire \i1/blk00000001/sig000001bf ;
wire \i1/blk00000001/sig00000163/G ;
wire \i1/blk00000001/sig0000014d/XORF_7509 ;
wire \i1/blk00000001/sig0000014d/LOGIC_ONE_7508 ;
wire \i1/blk00000001/sig0000014d/CYINIT_7507 ;
wire \i1/blk00000001/sig0000014d/F ;
wire \i1/blk00000001/sig0000014d/XORG_7495 ;
wire \i1/blk00000001/sig000001b3 ;
wire \i1/blk00000001/sig0000014d/G ;
wire \i1/blk00000001/sig00000137/XORF_7541 ;
wire \i1/blk00000001/sig00000137/LOGIC_ONE_7540 ;
wire \i1/blk00000001/sig00000137/CYINIT_7539 ;
wire \i1/blk00000001/sig00000137/F ;
wire \i1/blk00000001/sig00000137/XORG_7527 ;
wire \i1/blk00000001/sig000001a7 ;
wire \i1/blk00000001/sig00000137/G ;
wire \i1/blk00000001/sig00000121/XORF_7582 ;
wire \i1/blk00000001/sig00000121/CYINIT_7581 ;
wire \i1/blk00000001/sig00000121/CY0F_7580 ;
wire \i1/blk00000001/sig000001ee ;
wire \i1/blk00000001/sig000000e1 ;
wire \i1/blk00000001/sig00000121/XORG_7569 ;
wire \i1/blk00000001/sig0000019b ;
wire \i1/blk00000001/sig00000121/CYSELF_7567 ;
wire \i1/blk00000001/sig00000121/CYMUXFAST_7566 ;
wire \i1/blk00000001/sig00000121/CYAND_7565 ;
wire \i1/blk00000001/sig00000121/FASTCARRY_7564 ;
wire \i1/blk00000001/sig00000121/CYMUXG2_7563 ;
wire \i1/blk00000001/sig00000121/CYMUXF2_7562 ;
wire \i1/blk00000001/sig00000121/CY0G_7561 ;
wire \i1/blk00000001/sig000001e8 ;
wire \i1/blk00000001/sig00000121/CYSELG_7553 ;
wire \i1/blk00000001/sig000000e0 ;
wire \i1/blk00000001/sig0000010b/XORF_7597 ;
wire \i1/blk00000001/sig0000010b/CYINIT_7596 ;
wire \i1/blk00000001/sig0000023a ;
wire \i1/blk00000001/sig000001da/XORF_7635 ;
wire \i1/blk00000001/sig000001da/CYINIT_7634 ;
wire \i1/blk00000001/sig000001da/CY0F_7633 ;
wire \i1/blk00000001/sig0000022c ;
wire \i1/blk00000001/sig000001da/CYSELF_7624 ;
wire \i1/blk00000001/sig000001da/F ;
wire \i1/blk00000001/sig000001da/BXINV_7622 ;
wire \i1/blk00000001/sig000001da/XORG_7620 ;
wire \i1/blk00000001/sig000001da/CYMUXG_7619 ;
wire \i1/blk00000001/sig000001db ;
wire \i1/blk00000001/sig000001da/CY0G_7617 ;
wire \i1/blk00000001/sig0000022b ;
wire \i1/blk00000001/sig000001da/CYSELG_7608 ;
wire \i1/blk00000001/sig000001da/G ;
wire \i1/blk00000001/sig00000186/XORF_7676 ;
wire \i1/blk00000001/sig00000186/CYINIT_7675 ;
wire \i1/blk00000001/sig00000186/CY0F_7674 ;
wire \i1/blk00000001/sig00000225 ;
wire \i1/blk00000001/sig00000186/F ;
wire \i1/blk00000001/sig00000186/XORG_7663 ;
wire \i1/blk00000001/sig000001d2 ;
wire \i1/blk00000001/sig00000186/CYSELF_7661 ;
wire \i1/blk00000001/sig00000186/CYMUXFAST_7660 ;
wire \i1/blk00000001/sig00000186/CYAND_7659 ;
wire \i1/blk00000001/sig00000186/FASTCARRY_7658 ;
wire \i1/blk00000001/sig00000186/CYMUXG2_7657 ;
wire \i1/blk00000001/sig00000186/CYMUXF2_7656 ;
wire \i1/blk00000001/sig00000186/CY0G_7655 ;
wire \i1/blk00000001/sig0000021f ;
wire \i1/blk00000001/sig00000186/CYSELG_7646 ;
wire \i1/blk00000001/sig00000186/G ;
wire \i1/blk00000001/sig0000016f/XORF_7717 ;
wire \i1/blk00000001/sig0000016f/CYINIT_7716 ;
wire \i1/blk00000001/sig0000016f/CY0F_7715 ;
wire \i1/blk00000001/sig00000219 ;
wire \i1/blk00000001/sig0000016f/F ;
wire \i1/blk00000001/sig0000016f/XORG_7704 ;
wire \i1/blk00000001/sig000001c6 ;
wire \i1/blk00000001/sig0000016f/CYSELF_7702 ;
wire \i1/blk00000001/sig0000016f/CYMUXFAST_7701 ;
wire \i1/blk00000001/sig0000016f/CYAND_7700 ;
wire \i1/blk00000001/sig0000016f/FASTCARRY_7699 ;
wire \i1/blk00000001/sig0000016f/CYMUXG2_7698 ;
wire \i1/blk00000001/sig0000016f/CYMUXF2_7697 ;
wire \i1/blk00000001/sig0000016f/CY0G_7696 ;
wire \i1/blk00000001/sig00000213 ;
wire \i1/blk00000001/sig0000016f/CYSELG_7687 ;
wire \i1/blk00000001/sig0000016f/G ;
wire \i1/blk00000001/sig00000159/XORF_7758 ;
wire \i1/blk00000001/sig00000159/CYINIT_7757 ;
wire \i1/blk00000001/sig00000159/CY0F_7756 ;
wire \i1/blk00000001/sig0000020d ;
wire \i1/blk00000001/sig00000159/F ;
wire \i1/blk00000001/sig00000159/XORG_7745 ;
wire \i1/blk00000001/sig000001ba ;
wire \i1/blk00000001/sig00000159/CYSELF_7743 ;
wire \i1/blk00000001/sig00000159/CYMUXFAST_7742 ;
wire \i1/blk00000001/sig00000159/CYAND_7741 ;
wire \i1/blk00000001/sig00000159/FASTCARRY_7740 ;
wire \i1/blk00000001/sig00000159/CYMUXG2_7739 ;
wire \i1/blk00000001/sig00000159/CYMUXF2_7738 ;
wire \i1/blk00000001/sig00000159/CY0G_7737 ;
wire \i1/blk00000001/sig00000207 ;
wire \i1/blk00000001/sig00000159/CYSELG_7728 ;
wire \i1/blk00000001/sig00000159/G ;
wire \i1/blk00000001/sig00000143/XORF_7799 ;
wire \i1/blk00000001/sig00000143/CYINIT_7798 ;
wire \i1/blk00000001/sig00000143/CY0F_7797 ;
wire \i1/blk00000001/sig00000201 ;
wire \i1/blk00000001/sig00000143/F ;
wire \i1/blk00000001/sig00000143/XORG_7786 ;
wire \i1/blk00000001/sig000001ae ;
wire \i1/blk00000001/sig00000143/CYSELF_7784 ;
wire \i1/blk00000001/sig00000143/CYMUXFAST_7783 ;
wire \i1/blk00000001/sig00000143/CYAND_7782 ;
wire \i1/blk00000001/sig00000143/FASTCARRY_7781 ;
wire \i1/blk00000001/sig00000143/CYMUXG2_7780 ;
wire \i1/blk00000001/sig00000143/CYMUXF2_7779 ;
wire \i1/blk00000001/sig00000143/CY0G_7778 ;
wire \i1/blk00000001/sig000001fb ;
wire \i1/blk00000001/sig00000143/CYSELG_7769 ;
wire \i1/blk00000001/sig00000143/G ;
wire \i1/blk00000001/sig0000012d/XORF_7840 ;
wire \i1/blk00000001/sig0000012d/CYINIT_7839 ;
wire \i1/blk00000001/sig0000012d/CY0F_7838 ;
wire \i1/blk00000001/sig000001f5 ;
wire \i1/blk00000001/sig0000012d/F ;
wire \i1/blk00000001/sig0000012d/XORG_7828 ;
wire \i1/blk00000001/sig000001a2 ;
wire \i1/blk00000001/sig0000012d/CYSELF_7826 ;
wire \i1/blk00000001/sig0000012d/CYMUXFAST_7825 ;
wire \i1/blk00000001/sig0000012d/CYAND_7824 ;
wire \i1/blk00000001/sig0000012d/FASTCARRY_7823 ;
wire \i1/blk00000001/sig0000012d/CYMUXG2_7822 ;
wire \i1/blk00000001/sig0000012d/CYMUXF2_7821 ;
wire \i1/blk00000001/sig0000012d/CY0G_7820 ;
wire \i1/blk00000001/sig000001ef ;
wire \i1/blk00000001/sig0000012d/CYSELG_7812 ;
wire \i1/blk00000001/sig00000118 ;
wire \i1/blk00000001/sig00000117/XORF_7872 ;
wire \i1/blk00000001/sig00000117/CYINIT_7871 ;
wire \i1/blk00000001/sig00000117/CY0F_7870 ;
wire \i1/blk00000001/sig000001e9 ;
wire \i1/blk00000001/sig00000117/CYSELF_7862 ;
wire \i1/blk00000001/sig0000010d ;
wire \i1/blk00000001/sig00000117/XORG_7859 ;
wire \i1/blk00000001/sig00000196 ;
wire \i1/blk00000001/sig00000106 ;
wire \i1/blk00000001/sig000001e3/XORF_7910 ;
wire \i1/blk00000001/sig000001e3/CYINIT_7909 ;
wire \i1/blk00000001/sig000001e3/CY0F_7908 ;
wire \i1/blk00000001/sig00000235 ;
wire \i1/blk00000001/sig000001e3/CYSELF_7899 ;
wire \i1/blk00000001/sig000001e3/F ;
wire \i1/blk00000001/sig000001e3/BXINV_7897 ;
wire \i1/blk00000001/sig000001e3/XORG_7895 ;
wire \i1/blk00000001/sig000001e3/CYMUXG_7894 ;
wire \i1/blk00000001/sig000001e4 ;
wire \i1/blk00000001/sig000001e3/CY0G_7892 ;
wire \i1/blk00000001/sig00000234 ;
wire \i1/blk00000001/sig000001e3/CYSELG_7883 ;
wire \i1/blk00000001/sig000001e3/G ;
wire \i1/blk00000001/sig0000018f/XORF_7951 ;
wire \i1/blk00000001/sig0000018f/CYINIT_7950 ;
wire \i1/blk00000001/sig0000018f/CY0F_7949 ;
wire \i1/blk00000001/sig00000228 ;
wire \i1/blk00000001/sig0000018f/F ;
wire \i1/blk00000001/sig0000018f/XORG_7938 ;
wire \i1/blk00000001/sig000001d5 ;
wire \i1/blk00000001/sig0000018f/CYSELF_7936 ;
wire \i1/blk00000001/sig0000018f/CYMUXFAST_7935 ;
wire \i1/blk00000001/sig0000018f/CYAND_7934 ;
wire \i1/blk00000001/sig0000018f/FASTCARRY_7933 ;
wire \i1/blk00000001/sig0000018f/CYMUXG2_7932 ;
wire \i1/blk00000001/sig0000018f/CYMUXF2_7931 ;
wire \i1/blk00000001/sig0000018f/CY0G_7930 ;
wire \i1/blk00000001/sig00000222 ;
wire \i1/blk00000001/sig0000018f/CYSELG_7921 ;
wire \i1/blk00000001/sig0000018f/G ;
wire \i1/blk00000001/sig00000175/XORF_7992 ;
wire \i1/blk00000001/sig00000175/CYINIT_7991 ;
wire \i1/blk00000001/sig00000175/CY0F_7990 ;
wire \i1/blk00000001/sig0000021c ;
wire \i1/blk00000001/sig00000175/F ;
wire \i1/blk00000001/sig00000175/XORG_7979 ;
wire \i1/blk00000001/sig000001c9 ;
wire \i1/blk00000001/sig00000175/CYSELF_7977 ;
wire \i1/blk00000001/sig00000175/CYMUXFAST_7976 ;
wire \i1/blk00000001/sig00000175/CYAND_7975 ;
wire \i1/blk00000001/sig00000175/FASTCARRY_7974 ;
wire \i1/blk00000001/sig00000175/CYMUXG2_7973 ;
wire \i1/blk00000001/sig00000175/CYMUXF2_7972 ;
wire \i1/blk00000001/sig00000175/CY0G_7971 ;
wire \i1/blk00000001/sig00000216 ;
wire \i1/blk00000001/sig00000175/CYSELG_7962 ;
wire \i1/blk00000001/sig00000175/G ;
wire \i1/blk00000001/sig0000015f/XORF_8033 ;
wire \i1/blk00000001/sig0000015f/CYINIT_8032 ;
wire \i1/blk00000001/sig0000015f/CY0F_8031 ;
wire \i1/blk00000001/sig00000210 ;
wire \i1/blk00000001/sig0000015f/F ;
wire \i1/blk00000001/sig0000015f/XORG_8020 ;
wire \i1/blk00000001/sig000001bd ;
wire \i1/blk00000001/sig0000015f/CYSELF_8018 ;
wire \i1/blk00000001/sig0000015f/CYMUXFAST_8017 ;
wire \i1/blk00000001/sig0000015f/CYAND_8016 ;
wire \i1/blk00000001/sig0000015f/FASTCARRY_8015 ;
wire \i1/blk00000001/sig0000015f/CYMUXG2_8014 ;
wire \i1/blk00000001/sig0000015f/CYMUXF2_8013 ;
wire \i1/blk00000001/sig0000015f/CY0G_8012 ;
wire \i1/blk00000001/sig0000020a ;
wire \i1/blk00000001/sig0000015f/CYSELG_8003 ;
wire \i1/blk00000001/sig0000015f/G ;
wire \i1/blk00000001/sig00000149/XORF_8074 ;
wire \i1/blk00000001/sig00000149/CYINIT_8073 ;
wire \i1/blk00000001/sig00000149/CY0F_8072 ;
wire \i1/blk00000001/sig00000204 ;
wire \i1/blk00000001/sig00000149/F ;
wire \i1/blk00000001/sig00000149/XORG_8061 ;
wire \i1/blk00000001/sig000001b1 ;
wire \i1/blk00000001/sig00000149/CYSELF_8059 ;
wire \i1/blk00000001/sig00000149/CYMUXFAST_8058 ;
wire \i1/blk00000001/sig00000149/CYAND_8057 ;
wire \i1/blk00000001/sig00000149/FASTCARRY_8056 ;
wire \i1/blk00000001/sig00000149/CYMUXG2_8055 ;
wire \i1/blk00000001/sig00000149/CYMUXF2_8054 ;
wire \i1/blk00000001/sig00000149/CY0G_8053 ;
wire \i1/blk00000001/sig000001fe ;
wire \i1/blk00000001/sig00000149/CYSELG_8044 ;
wire \i1/blk00000001/sig00000149/G ;
wire \i1/blk00000001/sig00000133/XORF_8115 ;
wire \i1/blk00000001/sig00000133/CYINIT_8114 ;
wire \i1/blk00000001/sig00000133/CY0F_8113 ;
wire \i1/blk00000001/sig000001f8 ;
wire \i1/blk00000001/sig00000133/F ;
wire \i1/blk00000001/sig00000133/XORG_8103 ;
wire \i1/blk00000001/sig000001a5 ;
wire \i1/blk00000001/sig00000133/CYSELF_8101 ;
wire \i1/blk00000001/sig00000133/CYMUXFAST_8100 ;
wire \i1/blk00000001/sig00000133/CYAND_8099 ;
wire \i1/blk00000001/sig00000133/FASTCARRY_8098 ;
wire \i1/blk00000001/sig00000133/CYMUXG2_8097 ;
wire \i1/blk00000001/sig00000133/CYMUXF2_8096 ;
wire \i1/blk00000001/sig00000133/CY0G_8095 ;
wire \i1/blk00000001/sig000001f2 ;
wire \i1/blk00000001/sig00000133/CYSELG_8087 ;
wire \i1/blk00000001/sig0000011e ;
wire \i1/blk00000001/sig0000011d/XORF_8147 ;
wire \i1/blk00000001/sig0000011d/CYINIT_8146 ;
wire \i1/blk00000001/sig0000011d/CY0F_8145 ;
wire \i1/blk00000001/sig000001ec ;
wire \i1/blk00000001/sig0000011d/CYSELF_8137 ;
wire \i1/blk00000001/sig00000113 ;
wire \i1/blk00000001/sig0000011d/XORG_8134 ;
wire \i1/blk00000001/sig00000199 ;
wire \i1/blk00000001/sig00000109 ;
wire \i1/blk00000001/sig000001dd/XORF_8185 ;
wire \i1/blk00000001/sig000001dd/CYINIT_8184 ;
wire \i1/blk00000001/sig000001dd/CY0F_8183 ;
wire \i1/blk00000001/sig0000022f ;
wire \i1/blk00000001/sig000001dd/CYSELF_8174 ;
wire \i1/blk00000001/sig000001dd/F ;
wire \i1/blk00000001/sig000001dd/BXINV_8172 ;
wire \i1/blk00000001/sig000001dd/XORG_8170 ;
wire \i1/blk00000001/sig000001dd/CYMUXG_8169 ;
wire \i1/blk00000001/sig000001de ;
wire \i1/blk00000001/sig000001dd/CY0G_8167 ;
wire \i1/blk00000001/sig0000022e ;
wire \i1/blk00000001/sig000001dd/CYSELG_8158 ;
wire \i1/blk00000001/sig000001dd/G ;
wire \i1/blk00000001/sig00000189/XORF_8226 ;
wire \i1/blk00000001/sig00000189/CYINIT_8225 ;
wire \i1/blk00000001/sig00000189/CY0F_8224 ;
wire \i1/blk00000001/sig00000226 ;
wire \i1/blk00000001/sig00000189/F ;
wire \i1/blk00000001/sig00000189/XORG_8213 ;
wire \i1/blk00000001/sig000001d3 ;
wire \i1/blk00000001/sig00000189/CYSELF_8211 ;
wire \i1/blk00000001/sig00000189/CYMUXFAST_8210 ;
wire \i1/blk00000001/sig00000189/CYAND_8209 ;
wire \i1/blk00000001/sig00000189/FASTCARRY_8208 ;
wire \i1/blk00000001/sig00000189/CYMUXG2_8207 ;
wire \i1/blk00000001/sig00000189/CYMUXF2_8206 ;
wire \i1/blk00000001/sig00000189/CY0G_8205 ;
wire \i1/blk00000001/sig00000220 ;
wire \i1/blk00000001/sig00000189/CYSELG_8196 ;
wire \i1/blk00000001/sig00000189/G ;
wire \i1/blk00000001/sig00000171/XORF_8267 ;
wire \i1/blk00000001/sig00000171/CYINIT_8266 ;
wire \i1/blk00000001/sig00000171/CY0F_8265 ;
wire \i1/blk00000001/sig0000021a ;
wire \i1/blk00000001/sig00000171/F ;
wire \i1/blk00000001/sig00000171/XORG_8254 ;
wire \i1/blk00000001/sig000001c7 ;
wire \i1/blk00000001/sig00000171/CYSELF_8252 ;
wire \i1/blk00000001/sig00000171/CYMUXFAST_8251 ;
wire \i1/blk00000001/sig00000171/CYAND_8250 ;
wire \i1/blk00000001/sig00000171/FASTCARRY_8249 ;
wire \i1/blk00000001/sig00000171/CYMUXG2_8248 ;
wire \i1/blk00000001/sig00000171/CYMUXF2_8247 ;
wire \i1/blk00000001/sig00000171/CY0G_8246 ;
wire \i1/blk00000001/sig00000214 ;
wire \i1/blk00000001/sig00000171/CYSELG_8237 ;
wire \i1/blk00000001/sig00000171/G ;
wire \i1/blk00000001/sig0000015b/XORF_8308 ;
wire \i1/blk00000001/sig0000015b/CYINIT_8307 ;
wire \i1/blk00000001/sig0000015b/CY0F_8306 ;
wire \i1/blk00000001/sig0000020e ;
wire \i1/blk00000001/sig0000015b/F ;
wire \i1/blk00000001/sig0000015b/XORG_8295 ;
wire \i1/blk00000001/sig000001bb ;
wire \i1/blk00000001/sig0000015b/CYSELF_8293 ;
wire \i1/blk00000001/sig0000015b/CYMUXFAST_8292 ;
wire \i1/blk00000001/sig0000015b/CYAND_8291 ;
wire \i1/blk00000001/sig0000015b/FASTCARRY_8290 ;
wire \i1/blk00000001/sig0000015b/CYMUXG2_8289 ;
wire \i1/blk00000001/sig0000015b/CYMUXF2_8288 ;
wire \i1/blk00000001/sig0000015b/CY0G_8287 ;
wire \i1/blk00000001/sig00000208 ;
wire \i1/blk00000001/sig0000015b/CYSELG_8278 ;
wire \i1/blk00000001/sig0000015b/G ;
wire \i1/blk00000001/sig00000145/XORF_8349 ;
wire \i1/blk00000001/sig00000145/CYINIT_8348 ;
wire \i1/blk00000001/sig00000145/CY0F_8347 ;
wire \i1/blk00000001/sig00000202 ;
wire \i1/blk00000001/sig00000145/F ;
wire \i1/blk00000001/sig00000145/XORG_8336 ;
wire \i1/blk00000001/sig000001af ;
wire \i1/blk00000001/sig00000145/CYSELF_8334 ;
wire \i1/blk00000001/sig00000145/CYMUXFAST_8333 ;
wire \i1/blk00000001/sig00000145/CYAND_8332 ;
wire \i1/blk00000001/sig00000145/FASTCARRY_8331 ;
wire \i1/blk00000001/sig00000145/CYMUXG2_8330 ;
wire \i1/blk00000001/sig00000145/CYMUXF2_8329 ;
wire \i1/blk00000001/sig00000145/CY0G_8328 ;
wire \i1/blk00000001/sig000001fc ;
wire \i1/blk00000001/sig00000145/CYSELG_8319 ;
wire \i1/blk00000001/sig00000145/G ;
wire \i1/blk00000001/sig0000012f/XORF_8390 ;
wire \i1/blk00000001/sig0000012f/CYINIT_8389 ;
wire \i1/blk00000001/sig0000012f/CY0F_8388 ;
wire \i1/blk00000001/sig000001f6 ;
wire \i1/blk00000001/sig0000012f/F ;
wire \i1/blk00000001/sig0000012f/XORG_8378 ;
wire \i1/blk00000001/sig000001a3 ;
wire \i1/blk00000001/sig0000012f/CYSELF_8376 ;
wire \i1/blk00000001/sig0000012f/CYMUXFAST_8375 ;
wire \i1/blk00000001/sig0000012f/CYAND_8374 ;
wire \i1/blk00000001/sig0000012f/FASTCARRY_8373 ;
wire \i1/blk00000001/sig0000012f/CYMUXG2_8372 ;
wire \i1/blk00000001/sig0000012f/CYMUXF2_8371 ;
wire \i1/blk00000001/sig0000012f/CY0G_8370 ;
wire \i1/blk00000001/sig000001f0 ;
wire \i1/blk00000001/sig0000012f/CYSELG_8362 ;
wire \i1/blk00000001/sig0000011a ;
wire \i1/blk00000001/sig00000119/XORF_8422 ;
wire \i1/blk00000001/sig00000119/CYINIT_8421 ;
wire \i1/blk00000001/sig00000119/CY0F_8420 ;
wire \i1/blk00000001/sig000001ea ;
wire \i1/blk00000001/sig00000119/CYSELF_8412 ;
wire \i1/blk00000001/sig0000010f ;
wire \i1/blk00000001/sig00000119/XORG_8409 ;
wire \i1/blk00000001/sig00000197 ;
wire \i1/blk00000001/sig00000107 ;
wire \i1/blk00000001/sig000001e5/CYINIT_8455 ;
wire \i1/blk00000001/sig000001e5/CY0F_8454 ;
wire \i1/blk00000001/sig00000238 ;
wire \i1/blk00000001/sig000001e5/CYSELF_8445 ;
wire \i1/blk00000001/sig000001e5/F ;
wire \i1/blk00000001/sig000001e5/BXINV_8443 ;
wire \i1/blk00000001/sig000001e5/CYMUXG_8442 ;
wire \i1/blk00000001/sig000001e6 ;
wire \i1/blk00000001/sig000001e5/CY0G_8440 ;
wire \i1/blk00000001/sig00000237 ;
wire \i1/blk00000001/sig000001e5/CYSELG_8431 ;
wire \i1/blk00000001/sig000001e5/G ;
wire \i1/blk00000001/sig00000192/XORF_8495 ;
wire \i1/blk00000001/sig00000192/CYINIT_8494 ;
wire \i1/blk00000001/sig00000192/CY0F_8493 ;
wire \i1/blk00000001/sig00000229 ;
wire \i1/blk00000001/sig00000192/F ;
wire \i1/blk00000001/sig00000192/XORG_8482 ;
wire \i1/blk00000001/sig000001d6 ;
wire \i1/blk00000001/sig00000192/CYSELF_8480 ;
wire \i1/blk00000001/sig00000192/CYMUXFAST_8479 ;
wire \i1/blk00000001/sig00000192/CYAND_8478 ;
wire \i1/blk00000001/sig00000192/FASTCARRY_8477 ;
wire \i1/blk00000001/sig00000192/CYMUXG2_8476 ;
wire \i1/blk00000001/sig00000192/CYMUXF2_8475 ;
wire \i1/blk00000001/sig00000192/CY0G_8474 ;
wire \i1/blk00000001/sig00000223 ;
wire \i1/blk00000001/sig00000192/CYSELG_8465 ;
wire \i1/blk00000001/sig00000192/G ;
wire \i1/blk00000001/sig00000177/XORF_8536 ;
wire \i1/blk00000001/sig00000177/CYINIT_8535 ;
wire \i1/blk00000001/sig00000177/CY0F_8534 ;
wire \i1/blk00000001/sig0000021d ;
wire \i1/blk00000001/sig00000177/F ;
wire \i1/blk00000001/sig00000177/XORG_8523 ;
wire \i1/blk00000001/sig000001ca ;
wire \i1/blk00000001/sig00000177/CYSELF_8521 ;
wire \i1/blk00000001/sig00000177/CYMUXFAST_8520 ;
wire \i1/blk00000001/sig00000177/CYAND_8519 ;
wire \i1/blk00000001/sig00000177/FASTCARRY_8518 ;
wire \i1/blk00000001/sig00000177/CYMUXG2_8517 ;
wire \i1/blk00000001/sig00000177/CYMUXF2_8516 ;
wire \i1/blk00000001/sig00000177/CY0G_8515 ;
wire \i1/blk00000001/sig00000217 ;
wire \i1/blk00000001/sig00000177/CYSELG_8506 ;
wire \i1/blk00000001/sig00000177/G ;
wire \i1/blk00000001/sig00000161/XORF_8577 ;
wire \i1/blk00000001/sig00000161/CYINIT_8576 ;
wire \i1/blk00000001/sig00000161/CY0F_8575 ;
wire \i1/blk00000001/sig00000211 ;
wire \i1/blk00000001/sig00000161/F ;
wire \i1/blk00000001/sig00000161/XORG_8564 ;
wire \i1/blk00000001/sig000001be ;
wire \i1/blk00000001/sig00000161/CYSELF_8562 ;
wire \i1/blk00000001/sig00000161/CYMUXFAST_8561 ;
wire \i1/blk00000001/sig00000161/CYAND_8560 ;
wire \i1/blk00000001/sig00000161/FASTCARRY_8559 ;
wire \i1/blk00000001/sig00000161/CYMUXG2_8558 ;
wire \i1/blk00000001/sig00000161/CYMUXF2_8557 ;
wire \i1/blk00000001/sig00000161/CY0G_8556 ;
wire \i1/blk00000001/sig0000020b ;
wire \i1/blk00000001/sig00000161/CYSELG_8547 ;
wire \i1/blk00000001/sig00000161/G ;
wire \i1/blk00000001/sig0000014b/XORF_8618 ;
wire \i1/blk00000001/sig0000014b/CYINIT_8617 ;
wire \i1/blk00000001/sig0000014b/CY0F_8616 ;
wire \i1/blk00000001/sig00000205 ;
wire \i1/blk00000001/sig0000014b/F ;
wire \i1/blk00000001/sig0000014b/XORG_8605 ;
wire \i1/blk00000001/sig000001b2 ;
wire \i1/blk00000001/sig0000014b/CYSELF_8603 ;
wire \i1/blk00000001/sig0000014b/CYMUXFAST_8602 ;
wire \i1/blk00000001/sig0000014b/CYAND_8601 ;
wire \i1/blk00000001/sig0000014b/FASTCARRY_8600 ;
wire \i1/blk00000001/sig0000014b/CYMUXG2_8599 ;
wire \i1/blk00000001/sig0000014b/CYMUXF2_8598 ;
wire \i1/blk00000001/sig0000014b/CY0G_8597 ;
wire \i1/blk00000001/sig000001ff ;
wire \i1/blk00000001/sig0000014b/CYSELG_8588 ;
wire \i1/blk00000001/sig0000014b/G ;
wire \i1/blk00000001/sig00000135/XORF_8659 ;
wire \i1/blk00000001/sig00000135/CYINIT_8658 ;
wire \i1/blk00000001/sig00000135/CY0F_8657 ;
wire \i1/blk00000001/sig000001f9 ;
wire \i1/blk00000001/sig00000135/F ;
wire \i1/blk00000001/sig00000135/XORG_8646 ;
wire \i1/blk00000001/sig000001a6 ;
wire \i1/blk00000001/sig00000135/CYSELF_8644 ;
wire \i1/blk00000001/sig00000135/CYMUXFAST_8643 ;
wire \i1/blk00000001/sig00000135/CYAND_8642 ;
wire \i1/blk00000001/sig00000135/FASTCARRY_8641 ;
wire \i1/blk00000001/sig00000135/CYMUXG2_8640 ;
wire \i1/blk00000001/sig00000135/CYMUXF2_8639 ;
wire \i1/blk00000001/sig00000135/CY0G_8638 ;
wire \i1/blk00000001/sig000001f3 ;
wire \i1/blk00000001/sig00000135/CYSELG_8629 ;
wire \i1/blk00000001/sig00000135/G ;
wire \i1/blk00000001/sig0000011f/XORF_8691 ;
wire \i1/blk00000001/sig0000011f/CYINIT_8690 ;
wire \i1/blk00000001/sig0000011f/CY0F_8689 ;
wire \i1/blk00000001/sig000001ed ;
wire \i1/blk00000001/sig0000011f/CYSELF_8680 ;
wire \i1/blk00000001/sig0000011f/F ;
wire \i1/blk00000001/sig0000011f/XORG_8677 ;
wire \i1/blk00000001/sig0000019a ;
wire \i1/blk00000001/sig0000011f/G ;
wire \i1/blk00000001/sig000001e0/XORF_8729 ;
wire \i1/blk00000001/sig000001e0/CYINIT_8728 ;
wire \i1/blk00000001/sig000001e0/CY0F_8727 ;
wire \i1/blk00000001/sig00000232 ;
wire \i1/blk00000001/sig000001e0/CYSELF_8718 ;
wire \i1/blk00000001/sig000001e0/F ;
wire \i1/blk00000001/sig000001e0/BXINV_8716 ;
wire \i1/blk00000001/sig000001e0/XORG_8714 ;
wire \i1/blk00000001/sig000001e0/CYMUXG_8713 ;
wire \i1/blk00000001/sig000001e1 ;
wire \i1/blk00000001/sig000001e0/CY0G_8711 ;
wire \i1/blk00000001/sig00000231 ;
wire \i1/blk00000001/sig000001e0/CYSELG_8702 ;
wire \i1/blk00000001/sig000001e0/G ;
wire \i1/blk00000001/sig0000018c/XORF_8770 ;
wire \i1/blk00000001/sig0000018c/CYINIT_8769 ;
wire \i1/blk00000001/sig0000018c/CY0F_8768 ;
wire \i1/blk00000001/sig00000227 ;
wire \i1/blk00000001/sig0000018c/F ;
wire \i1/blk00000001/sig0000018c/XORG_8757 ;
wire \i1/blk00000001/sig000001d4 ;
wire \i1/blk00000001/sig0000018c/CYSELF_8755 ;
wire \i1/blk00000001/sig0000018c/CYMUXFAST_8754 ;
wire \i1/blk00000001/sig0000018c/CYAND_8753 ;
wire \i1/blk00000001/sig0000018c/FASTCARRY_8752 ;
wire \i1/blk00000001/sig0000018c/CYMUXG2_8751 ;
wire \i1/blk00000001/sig0000018c/CYMUXF2_8750 ;
wire \i1/blk00000001/sig0000018c/CY0G_8749 ;
wire \i1/blk00000001/sig00000221 ;
wire \i1/blk00000001/sig0000018c/CYSELG_8740 ;
wire \i1/blk00000001/sig0000018c/G ;
wire \i1/blk00000001/sig00000173/XORF_8811 ;
wire \i1/blk00000001/sig00000173/CYINIT_8810 ;
wire \i1/blk00000001/sig00000173/CY0F_8809 ;
wire \i1/blk00000001/sig0000021b ;
wire \i1/blk00000001/sig00000173/F ;
wire \i1/blk00000001/sig00000173/XORG_8798 ;
wire \i1/blk00000001/sig000001c8 ;
wire \i1/blk00000001/sig00000173/CYSELF_8796 ;
wire \i1/blk00000001/sig00000173/CYMUXFAST_8795 ;
wire \i1/blk00000001/sig00000173/CYAND_8794 ;
wire \i1/blk00000001/sig00000173/FASTCARRY_8793 ;
wire \i1/blk00000001/sig00000173/CYMUXG2_8792 ;
wire \i1/blk00000001/sig00000173/CYMUXF2_8791 ;
wire \i1/blk00000001/sig00000173/CY0G_8790 ;
wire \i1/blk00000001/sig00000215 ;
wire \i1/blk00000001/sig00000173/CYSELG_8781 ;
wire \i1/blk00000001/sig00000173/G ;
wire \i1/blk00000001/sig0000015d/XORF_8852 ;
wire \i1/blk00000001/sig0000015d/CYINIT_8851 ;
wire \i1/blk00000001/sig0000015d/CY0F_8850 ;
wire \i1/blk00000001/sig0000020f ;
wire \i1/blk00000001/sig0000015d/F ;
wire \i1/blk00000001/sig0000015d/XORG_8839 ;
wire \i1/blk00000001/sig000001bc ;
wire \i1/blk00000001/sig0000015d/CYSELF_8837 ;
wire \i1/blk00000001/sig0000015d/CYMUXFAST_8836 ;
wire \i1/blk00000001/sig0000015d/CYAND_8835 ;
wire \i1/blk00000001/sig0000015d/FASTCARRY_8834 ;
wire \i1/blk00000001/sig0000015d/CYMUXG2_8833 ;
wire \i1/blk00000001/sig0000015d/CYMUXF2_8832 ;
wire \i1/blk00000001/sig0000015d/CY0G_8831 ;
wire \i1/blk00000001/sig00000209 ;
wire \i1/blk00000001/sig0000015d/CYSELG_8822 ;
wire \i1/blk00000001/sig0000015d/G ;
wire \i1/blk00000001/sig00000147/XORF_8893 ;
wire \i1/blk00000001/sig00000147/CYINIT_8892 ;
wire \i1/blk00000001/sig00000147/CY0F_8891 ;
wire \i1/blk00000001/sig00000203 ;
wire \i1/blk00000001/sig00000147/F ;
wire \i1/blk00000001/sig00000147/XORG_8880 ;
wire \i1/blk00000001/sig000001b0 ;
wire \i1/blk00000001/sig00000147/CYSELF_8878 ;
wire \i1/blk00000001/sig00000147/CYMUXFAST_8877 ;
wire \i1/blk00000001/sig00000147/CYAND_8876 ;
wire \i1/blk00000001/sig00000147/FASTCARRY_8875 ;
wire \i1/blk00000001/sig00000147/CYMUXG2_8874 ;
wire \i1/blk00000001/sig00000147/CYMUXF2_8873 ;
wire \i1/blk00000001/sig00000147/CY0G_8872 ;
wire \i1/blk00000001/sig000001fd ;
wire \i1/blk00000001/sig00000147/CYSELG_8863 ;
wire \i1/blk00000001/sig00000147/G ;
wire \i1/blk00000001/sig00000131/XORF_8934 ;
wire \i1/blk00000001/sig00000131/CYINIT_8933 ;
wire \i1/blk00000001/sig00000131/CY0F_8932 ;
wire \i1/blk00000001/sig000001f7 ;
wire \i1/blk00000001/sig00000131/F ;
wire \i1/blk00000001/sig00000131/XORG_8922 ;
wire \i1/blk00000001/sig000001a4 ;
wire \i1/blk00000001/sig00000131/CYSELF_8920 ;
wire \i1/blk00000001/sig00000131/CYMUXFAST_8919 ;
wire \i1/blk00000001/sig00000131/CYAND_8918 ;
wire \i1/blk00000001/sig00000131/FASTCARRY_8917 ;
wire \i1/blk00000001/sig00000131/CYMUXG2_8916 ;
wire \i1/blk00000001/sig00000131/CYMUXF2_8915 ;
wire \i1/blk00000001/sig00000131/CY0G_8914 ;
wire \i1/blk00000001/sig000001f1 ;
wire \i1/blk00000001/sig00000131/CYSELG_8906 ;
wire \i1/blk00000001/sig0000011c ;
wire \i1/blk00000001/sig0000011b/XORF_8966 ;
wire \i1/blk00000001/sig0000011b/CYINIT_8965 ;
wire \i1/blk00000001/sig0000011b/CY0F_8964 ;
wire \i1/blk00000001/sig000001eb ;
wire \i1/blk00000001/sig0000011b/CYSELF_8956 ;
wire \i1/blk00000001/sig00000111 ;
wire \i1/blk00000001/sig0000011b/XORG_8953 ;
wire \i1/blk00000001/sig00000198 ;
wire \i1/blk00000001/sig00000108 ;
wire \i1/blk00000001/sig000000c4/XORF_9002 ;
wire \i1/blk00000001/sig000000c4/CYINIT_9001 ;
wire \i1/blk00000001/sig000000c4/CY0F_9000 ;
wire \i1/blk00000001/sig000000c4/CYSELF_8992 ;
wire \i1/blk00000001/sig0000008d ;
wire \i1/blk00000001/sig000000c4/BXINV_8990 ;
wire \i1/blk00000001/sig000000c4/XORG_8988 ;
wire \i1/blk00000001/sig000000c4/CYMUXG_8987 ;
wire \i1/blk00000001/sig0000008c ;
wire \i1/blk00000001/sig000000c4/CY0G_8985 ;
wire \i1/blk00000001/sig000000c4/CYSELG_8977 ;
wire \i1/blk00000001/sig0000008b ;
wire \i1/blk00000001/sig000000c6/XORF_9041 ;
wire \i1/blk00000001/sig000000c6/CYINIT_9040 ;
wire \i1/blk00000001/sig000000c6/CY0F_9039 ;
wire \i1/blk00000001/sig00000089 ;
wire \i1/blk00000001/sig000000c6/XORG_9029 ;
wire \i1/blk00000001/sig00000088 ;
wire \i1/blk00000001/sig000000c6/CYSELF_9027 ;
wire \i1/blk00000001/sig000000c6/CYMUXFAST_9026 ;
wire \i1/blk00000001/sig000000c6/CYAND_9025 ;
wire \i1/blk00000001/sig000000c6/FASTCARRY_9024 ;
wire \i1/blk00000001/sig000000c6/CYMUXG2_9023 ;
wire \i1/blk00000001/sig000000c6/CYMUXF2_9022 ;
wire \i1/blk00000001/sig000000c6/CY0G_9021 ;
wire \i1/blk00000001/sig000000c6/CYSELG_9013 ;
wire \i1/blk00000001/sig00000087 ;
wire \i1/blk00000001/sig000000c8/XORF_9080 ;
wire \i1/blk00000001/sig000000c8/CYINIT_9079 ;
wire \i1/blk00000001/sig000000c8/CY0F_9078 ;
wire \i1/blk00000001/sig00000085 ;
wire \i1/blk00000001/sig000000c8/XORG_9068 ;
wire \i1/blk00000001/sig00000084 ;
wire \i1/blk00000001/sig000000c8/CYSELF_9066 ;
wire \i1/blk00000001/sig000000c8/CYMUXFAST_9065 ;
wire \i1/blk00000001/sig000000c8/CYAND_9064 ;
wire \i1/blk00000001/sig000000c8/FASTCARRY_9063 ;
wire \i1/blk00000001/sig000000c8/CYMUXG2_9062 ;
wire \i1/blk00000001/sig000000c8/CYMUXF2_9061 ;
wire \i1/blk00000001/sig000000c8/CY0G_9060 ;
wire \i1/blk00000001/sig000000c8/CYSELG_9052 ;
wire \i1/blk00000001/sig00000083 ;
wire \i1/blk00000001/sig000000ca/XORF_9119 ;
wire \i1/blk00000001/sig000000ca/CYINIT_9118 ;
wire \i1/blk00000001/sig000000ca/CY0F_9117 ;
wire \i1/blk00000001/sig00000081 ;
wire \i1/blk00000001/sig000000ca/XORG_9107 ;
wire \i1/blk00000001/sig00000080 ;
wire \i1/blk00000001/sig000000ca/CYSELF_9105 ;
wire \i1/blk00000001/sig000000ca/CYMUXFAST_9104 ;
wire \i1/blk00000001/sig000000ca/CYAND_9103 ;
wire \i1/blk00000001/sig000000ca/FASTCARRY_9102 ;
wire \i1/blk00000001/sig000000ca/CYMUXG2_9101 ;
wire \i1/blk00000001/sig000000ca/CYMUXF2_9100 ;
wire \i1/blk00000001/sig000000ca/CY0G_9099 ;
wire \i1/blk00000001/sig000000ca/CYSELG_9091 ;
wire \i1/blk00000001/sig0000007f ;
wire \i1/blk00000001/sig000000cc/XORF_9158 ;
wire \i1/blk00000001/sig000000cc/CYINIT_9157 ;
wire \i1/blk00000001/sig000000cc/CY0F_9156 ;
wire \i1/blk00000001/sig0000007d ;
wire \i1/blk00000001/sig000000cc/XORG_9146 ;
wire \i1/blk00000001/sig0000007c ;
wire \i1/blk00000001/sig000000cc/CYSELF_9144 ;
wire \i1/blk00000001/sig000000cc/CYMUXFAST_9143 ;
wire \i1/blk00000001/sig000000cc/CYAND_9142 ;
wire \i1/blk00000001/sig000000cc/FASTCARRY_9141 ;
wire \i1/blk00000001/sig000000cc/CYMUXG2_9140 ;
wire \i1/blk00000001/sig000000cc/CYMUXF2_9139 ;
wire \i1/blk00000001/sig000000cc/CY0G_9138 ;
wire \i1/blk00000001/sig000000cc/CYSELG_9130 ;
wire \i1/blk00000001/sig0000007b ;
wire \i1/blk00000001/sig000000ce/XORF_9197 ;
wire \i1/blk00000001/sig000000ce/CYINIT_9196 ;
wire \i1/blk00000001/sig000000ce/CY0F_9195 ;
wire \i1/blk00000001/sig00000079 ;
wire \i1/blk00000001/sig000000ce/XORG_9185 ;
wire \i1/blk00000001/sig00000078 ;
wire \i1/blk00000001/sig000000ce/CYSELF_9183 ;
wire \i1/blk00000001/sig000000ce/CYMUXFAST_9182 ;
wire \i1/blk00000001/sig000000ce/CYAND_9181 ;
wire \i1/blk00000001/sig000000ce/FASTCARRY_9180 ;
wire \i1/blk00000001/sig000000ce/CYMUXG2_9179 ;
wire \i1/blk00000001/sig000000ce/CYMUXF2_9178 ;
wire \i1/blk00000001/sig000000ce/CY0G_9177 ;
wire \i1/blk00000001/sig000000ce/CYSELG_9169 ;
wire \i1/blk00000001/sig00000077 ;
wire \i1/blk00000001/sig000000d0/XORF_9212 ;
wire \i1/blk00000001/sig000000d0/CYINIT_9211 ;
wire \i1/blk00000001/sig00000075 ;
wire \i1/blk00000001/sig000000eb/XORF_9248 ;
wire \i1/blk00000001/sig000000eb/CYINIT_9247 ;
wire \i1/blk00000001/sig000000eb/CY0F_9246 ;
wire \i1/blk00000001/sig000000eb/CYSELF_9238 ;
wire \i1/blk00000001/sig000000a8 ;
wire \i1/blk00000001/sig000000eb/BXINV_9236 ;
wire \i1/blk00000001/sig000000eb/XORG_9234 ;
wire \i1/blk00000001/sig000000eb/CYMUXG_9233 ;
wire \i1/blk00000001/sig000000a7 ;
wire \i1/blk00000001/sig000000eb/CY0G_9231 ;
wire \i1/blk00000001/sig000000eb/CYSELG_9223 ;
wire \i1/blk00000001/sig000000a6 ;
wire \i1/blk00000001/sig000000ed/XORF_9287 ;
wire \i1/blk00000001/sig000000ed/CYINIT_9286 ;
wire \i1/blk00000001/sig000000ed/CY0F_9285 ;
wire \i1/blk00000001/sig000000a4 ;
wire \i1/blk00000001/sig000000ed/XORG_9275 ;
wire \i1/blk00000001/sig000000a3 ;
wire \i1/blk00000001/sig000000ed/CYSELF_9273 ;
wire \i1/blk00000001/sig000000ed/CYMUXFAST_9272 ;
wire \i1/blk00000001/sig000000ed/CYAND_9271 ;
wire \i1/blk00000001/sig000000ed/FASTCARRY_9270 ;
wire \i1/blk00000001/sig000000ed/CYMUXG2_9269 ;
wire \i1/blk00000001/sig000000ed/CYMUXF2_9268 ;
wire \i1/blk00000001/sig000000ed/CY0G_9267 ;
wire \i1/blk00000001/sig000000ed/CYSELG_9259 ;
wire \i1/blk00000001/sig000000a2 ;
wire \i1/blk00000001/sig000000ef/XORF_9326 ;
wire \i1/blk00000001/sig000000ef/CYINIT_9325 ;
wire \i1/blk00000001/sig000000ef/CY0F_9324 ;
wire \i1/blk00000001/sig000000a0 ;
wire \i1/blk00000001/sig000000ef/XORG_9314 ;
wire \i1/blk00000001/sig0000009f ;
wire \i1/blk00000001/sig000000ef/CYSELF_9312 ;
wire \i1/blk00000001/sig000000ef/CYMUXFAST_9311 ;
wire \i1/blk00000001/sig000000ef/CYAND_9310 ;
wire \i1/blk00000001/sig000000ef/FASTCARRY_9309 ;
wire \i1/blk00000001/sig000000ef/CYMUXG2_9308 ;
wire \i1/blk00000001/sig000000ef/CYMUXF2_9307 ;
wire \i1/blk00000001/sig000000ef/CY0G_9306 ;
wire \i1/blk00000001/sig000000ef/CYSELG_9298 ;
wire \i1/blk00000001/sig0000009e ;
wire \i1/blk00000001/sig000000f1/XORF_9365 ;
wire \i1/blk00000001/sig000000f1/CYINIT_9364 ;
wire \i1/blk00000001/sig000000f1/CY0F_9363 ;
wire \i1/blk00000001/sig0000009c ;
wire \i1/blk00000001/sig000000f1/XORG_9353 ;
wire \i1/blk00000001/sig0000009b ;
wire \i1/blk00000001/sig000000f1/CYSELF_9351 ;
wire \i1/blk00000001/sig000000f1/CYMUXFAST_9350 ;
wire \i1/blk00000001/sig000000f1/CYAND_9349 ;
wire \i1/blk00000001/sig000000f1/FASTCARRY_9348 ;
wire \i1/blk00000001/sig000000f1/CYMUXG2_9347 ;
wire \i1/blk00000001/sig000000f1/CYMUXF2_9346 ;
wire \i1/blk00000001/sig000000f1/CY0G_9345 ;
wire \i1/blk00000001/sig000000f1/CYSELG_9337 ;
wire \i1/blk00000001/sig0000009a ;
wire \i1/blk00000001/sig000000f3/XORF_9404 ;
wire \i1/blk00000001/sig000000f3/CYINIT_9403 ;
wire \i1/blk00000001/sig000000f3/CY0F_9402 ;
wire \i1/blk00000001/sig00000098 ;
wire \i1/blk00000001/sig000000f3/XORG_9392 ;
wire \i1/blk00000001/sig00000097 ;
wire \i1/blk00000001/sig000000f3/CYSELF_9390 ;
wire \i1/blk00000001/sig000000f3/CYMUXFAST_9389 ;
wire \i1/blk00000001/sig000000f3/CYAND_9388 ;
wire \i1/blk00000001/sig000000f3/FASTCARRY_9387 ;
wire \i1/blk00000001/sig000000f3/CYMUXG2_9386 ;
wire \i1/blk00000001/sig000000f3/CYMUXF2_9385 ;
wire \i1/blk00000001/sig000000f3/CY0G_9384 ;
wire \i1/blk00000001/sig000000f3/CYSELG_9376 ;
wire \i1/blk00000001/sig00000096 ;
wire \i1/blk00000001/sig000000f5/XORF_9443 ;
wire \i1/blk00000001/sig000000f5/CYINIT_9442 ;
wire \i1/blk00000001/sig000000f5/CY0F_9441 ;
wire \i1/blk00000001/sig00000094 ;
wire \i1/blk00000001/sig000000f5/XORG_9431 ;
wire \i1/blk00000001/sig00000093 ;
wire \i1/blk00000001/sig000000f5/CYSELF_9429 ;
wire \i1/blk00000001/sig000000f5/CYMUXFAST_9428 ;
wire \i1/blk00000001/sig000000f5/CYAND_9427 ;
wire \i1/blk00000001/sig000000f5/FASTCARRY_9426 ;
wire \i1/blk00000001/sig000000f5/CYMUXG2_9425 ;
wire \i1/blk00000001/sig000000f5/CYMUXF2_9424 ;
wire \i1/blk00000001/sig000000f5/CY0G_9423 ;
wire \i1/blk00000001/sig000000f5/CYSELG_9415 ;
wire \i1/blk00000001/sig00000092 ;
wire \i1/blk00000001/sig000000f7/XORF_9474 ;
wire \i1/blk00000001/sig000000f7/CYINIT_9473 ;
wire \i1/blk00000001/sig000000f7/CY0F_9472 ;
wire \i1/blk00000001/sig000000f7/CYSELF_9464 ;
wire \i1/blk00000001/sig00000090 ;
wire \i1/blk00000001/sig000000f7/XORG_9461 ;
wire \i1/blk00000001/sig0000008f ;
wire \i1/blk00000001/sig0000008e ;
wire \i1/blk00000001/sig000000c0/CYINIT_9505 ;
wire \i1/blk00000001/sig000000c0/CY0F_9504 ;
wire \i1/blk00000001/sig000000c0/CYSELF_9496 ;
wire \i1/blk00000001/sig000000c3 ;
wire \i1/blk00000001/sig000000c0/BXINV_9494 ;
wire \i1/blk00000001/sig000000c0/CYMUXG_9493 ;
wire \i1/blk00000001/sig000000c2 ;
wire \i1/blk00000001/sig000000c0/CY0G_9491 ;
wire \i1/blk00000001/sig000000c0/CYSELG_9483 ;
wire \i1/blk00000001/sig000000c1 ;
wire \i1/blk00000001/sig000000f9/XORF_9543 ;
wire \i1/blk00000001/sig000000f9/CYINIT_9542 ;
wire \i1/blk00000001/sig000000f9/CY0F_9541 ;
wire \i1/blk00000001/sig000000bf ;
wire \i1/blk00000001/sig000000f9/XORG_9531 ;
wire \i1/blk00000001/sig000000be ;
wire \i1/blk00000001/sig000000f9/CYSELF_9529 ;
wire \i1/blk00000001/sig000000f9/CYMUXFAST_9528 ;
wire \i1/blk00000001/sig000000f9/CYAND_9527 ;
wire \i1/blk00000001/sig000000f9/FASTCARRY_9526 ;
wire \i1/blk00000001/sig000000f9/CYMUXG2_9525 ;
wire \i1/blk00000001/sig000000f9/CYMUXF2_9524 ;
wire \i1/blk00000001/sig000000f9/CY0G_9523 ;
wire \i1/blk00000001/sig000000f9/CYSELG_9515 ;
wire \i1/blk00000001/sig000000bd ;
wire \i1/blk00000001/sig000000fb/XORF_9582 ;
wire \i1/blk00000001/sig000000fb/CYINIT_9581 ;
wire \i1/blk00000001/sig000000fb/CY0F_9580 ;
wire \i1/blk00000001/sig000000bb ;
wire \i1/blk00000001/sig000000fb/XORG_9570 ;
wire \i1/blk00000001/sig000000ba ;
wire \i1/blk00000001/sig000000fb/CYSELF_9568 ;
wire \i1/blk00000001/sig000000fb/CYMUXFAST_9567 ;
wire \i1/blk00000001/sig000000fb/CYAND_9566 ;
wire \i1/blk00000001/sig000000fb/FASTCARRY_9565 ;
wire \i1/blk00000001/sig000000fb/CYMUXG2_9564 ;
wire \i1/blk00000001/sig000000fb/CYMUXF2_9563 ;
wire \i1/blk00000001/sig000000fb/CY0G_9562 ;
wire \i1/blk00000001/sig000000fb/CYSELG_9554 ;
wire \i1/blk00000001/sig000000b9 ;
wire \i1/blk00000001/sig000000fd/XORF_9621 ;
wire \i1/blk00000001/sig000000fd/CYINIT_9620 ;
wire \i1/blk00000001/sig000000fd/CY0F_9619 ;
wire \i1/blk00000001/sig000000b7 ;
wire \i1/blk00000001/sig000000fd/XORG_9609 ;
wire \i1/blk00000001/sig000000b6 ;
wire \i1/blk00000001/sig000000fd/CYSELF_9607 ;
wire \i1/blk00000001/sig000000fd/CYMUXFAST_9606 ;
wire \i1/blk00000001/sig000000fd/CYAND_9605 ;
wire \i1/blk00000001/sig000000fd/FASTCARRY_9604 ;
wire \i1/blk00000001/sig000000fd/CYMUXG2_9603 ;
wire \i1/blk00000001/sig000000fd/CYMUXF2_9602 ;
wire \i1/blk00000001/sig000000fd/CY0G_9601 ;
wire \i1/blk00000001/sig000000fd/CYSELG_9593 ;
wire \i1/blk00000001/sig000000b5 ;
wire \i1/blk00000001/sig000000ff/XORF_9660 ;
wire \i1/blk00000001/sig000000ff/CYINIT_9659 ;
wire \i1/blk00000001/sig000000ff/CY0F_9658 ;
wire \i1/blk00000001/sig000000b3 ;
wire \i1/blk00000001/sig000000ff/XORG_9648 ;
wire \i1/blk00000001/sig000000b2 ;
wire \i1/blk00000001/sig000000ff/CYSELF_9646 ;
wire \i1/blk00000001/sig000000ff/CYMUXFAST_9645 ;
wire \i1/blk00000001/sig000000ff/CYAND_9644 ;
wire \i1/blk00000001/sig000000ff/FASTCARRY_9643 ;
wire \i1/blk00000001/sig000000ff/CYMUXG2_9642 ;
wire \i1/blk00000001/sig000000ff/CYMUXF2_9641 ;
wire \i1/blk00000001/sig000000ff/CY0G_9640 ;
wire \i1/blk00000001/sig000000ff/CYSELG_9632 ;
wire \i1/blk00000001/sig000000b1 ;
wire \i1/blk00000001/sig00000101/XORF_9699 ;
wire \i1/blk00000001/sig00000101/CYINIT_9698 ;
wire \i1/blk00000001/sig00000101/CY0F_9697 ;
wire \i1/blk00000001/sig000000af ;
wire \i1/blk00000001/sig00000101/XORG_9687 ;
wire \i1/blk00000001/sig000000ae ;
wire \i1/blk00000001/sig00000101/CYSELF_9685 ;
wire \i1/blk00000001/sig00000101/CYMUXFAST_9684 ;
wire \i1/blk00000001/sig00000101/CYAND_9683 ;
wire \i1/blk00000001/sig00000101/FASTCARRY_9682 ;
wire \i1/blk00000001/sig00000101/CYMUXG2_9681 ;
wire \i1/blk00000001/sig00000101/CYMUXF2_9680 ;
wire \i1/blk00000001/sig00000101/CY0G_9679 ;
wire \i1/blk00000001/sig00000101/CYSELG_9671 ;
wire \i1/blk00000001/sig000000ad ;
wire \i1/blk00000001/sig00000103/XORF_9730 ;
wire \i1/blk00000001/sig00000103/CYINIT_9729 ;
wire \i1/blk00000001/sig00000103/CY0F_9728 ;
wire \i1/blk00000001/sig00000103/CYSELF_9720 ;
wire \i1/blk00000001/sig000000ab ;
wire \i1/blk00000001/sig00000103/XORG_9717 ;
wire \i1/blk00000001/sig000000aa ;
wire \i1/blk00000001/sig000000a9 ;
wire \i3/blk00000001/sig0000004e/CYINIT_9761 ;
wire \i3/blk00000001/sig0000004e/CY0F_9760 ;
wire \i3/blk00000001/sig0000004e/CYSELF_9752 ;
wire \i3/blk00000001/sig00000051 ;
wire \i3/blk00000001/sig0000004e/BXINV_9750 ;
wire \i3/blk00000001/sig0000004e/CYMUXG_9749 ;
wire \i3/blk00000001/sig00000050 ;
wire \i3/blk00000001/sig0000004e/CY0G_9747 ;
wire \i3/blk00000001/sig0000004e/CYSELG_9739 ;
wire \i3/blk00000001/sig0000004f ;
wire \t3<11>/CYINIT_9797 ;
wire \t3<11>/CY0F_9796 ;
wire \i3/blk00000001/sig0000004d ;
wire \t3<11>/XORG_9786 ;
wire \i3/blk00000001/sig0000004c ;
wire \t3<11>/CYSELF_9784 ;
wire \t3<11>/CYMUXFAST_9783 ;
wire \t3<11>/CYAND_9782 ;
wire \t3<11>/FASTCARRY_9781 ;
wire \t3<11>/CYMUXG2_9780 ;
wire \t3<11>/CYMUXF2_9779 ;
wire \t3<11>/CY0G_9778 ;
wire \t3<11>/CYSELG_9770 ;
wire \i3/blk00000001/sig0000004b ;
wire \t3<12>/XORF_9835 ;
wire \t3<12>/CYINIT_9834 ;
wire \t3<12>/CY0F_9833 ;
wire \i3/blk00000001/sig00000049 ;
wire \t3<12>/XORG_9823 ;
wire \i3/blk00000001/sig00000048 ;
wire \t3<12>/CYSELF_9821 ;
wire \t3<12>/CYMUXFAST_9820 ;
wire \t3<12>/CYAND_9819 ;
wire \t3<12>/FASTCARRY_9818 ;
wire \t3<12>/CYMUXG2_9817 ;
wire \t3<12>/CYMUXF2_9816 ;
wire \t3<12>/CY0G_9815 ;
wire \t3<12>/CYSELG_9807 ;
wire \i3/blk00000001/sig00000047 ;
wire \t3<14>/XORF_9874 ;
wire \t3<14>/CYINIT_9873 ;
wire \t3<14>/CY0F_9872 ;
wire \i3/blk00000001/sig00000045 ;
wire \t3<14>/XORG_9862 ;
wire \i3/blk00000001/sig00000044 ;
wire \t3<14>/CYSELF_9860 ;
wire \t3<14>/CYMUXFAST_9859 ;
wire \t3<14>/CYAND_9858 ;
wire \t3<14>/FASTCARRY_9857 ;
wire \t3<14>/CYMUXG2_9856 ;
wire \t3<14>/CYMUXF2_9855 ;
wire \t3<14>/CY0G_9854 ;
wire \t3<14>/CYSELG_9846 ;
wire \i3/blk00000001/sig00000043 ;
wire \t3<16>/XORF_9913 ;
wire \t3<16>/CYINIT_9912 ;
wire \t3<16>/CY0F_9911 ;
wire \i3/blk00000001/sig00000041 ;
wire \t3<16>/XORG_9901 ;
wire \i3/blk00000001/sig00000040 ;
wire \t3<16>/CYSELF_9899 ;
wire \t3<16>/CYMUXFAST_9898 ;
wire \t3<16>/CYAND_9897 ;
wire \t3<16>/FASTCARRY_9896 ;
wire \t3<16>/CYMUXG2_9895 ;
wire \t3<16>/CYMUXF2_9894 ;
wire \t3<16>/CY0G_9893 ;
wire \t3<16>/CYSELG_9885 ;
wire \i3/blk00000001/sig0000003f ;
wire \t3<18>/XORF_9952 ;
wire \t3<18>/CYINIT_9951 ;
wire \t3<18>/CY0F_9950 ;
wire \i3/blk00000001/sig0000003d ;
wire \t3<18>/XORG_9940 ;
wire \i3/blk00000001/sig0000003c ;
wire \t3<18>/CYSELF_9938 ;
wire \t3<18>/CYMUXFAST_9937 ;
wire \t3<18>/CYAND_9936 ;
wire \t3<18>/FASTCARRY_9935 ;
wire \t3<18>/CYMUXG2_9934 ;
wire \t3<18>/CYMUXF2_9933 ;
wire \t3<18>/CY0G_9932 ;
wire \t3<18>/CYSELG_9924 ;
wire \i3/blk00000001/sig0000003b ;
wire \t3<20>/XORF_9991 ;
wire \t3<20>/CYINIT_9990 ;
wire \t3<20>/CY0F_9989 ;
wire \i3/blk00000001/sig00000039 ;
wire \t3<20>/XORG_9979 ;
wire \i3/blk00000001/sig00000038 ;
wire \t3<20>/CYSELF_9977 ;
wire \t3<20>/CYMUXFAST_9976 ;
wire \t3<20>/CYAND_9975 ;
wire \t3<20>/FASTCARRY_9974 ;
wire \t3<20>/CYMUXG2_9973 ;
wire \t3<20>/CYMUXF2_9972 ;
wire \t3<20>/CY0G_9971 ;
wire \t3<20>/CYSELG_9963 ;
wire \i3/blk00000001/sig00000037 ;
wire \t3<22>/XORF_10006 ;
wire \t3<22>/CYINIT_10005 ;
wire \i3/blk00000001/sig00000035 ;
wire \i3/blk00000001/sig0000006f/CYINIT_10037 ;
wire \i3/blk00000001/sig0000006f/CY0F_10036 ;
wire \i3/blk00000001/sig0000006f/CYSELF_10028 ;
wire \i3/blk00000001/sig00000072 ;
wire \i3/blk00000001/sig0000006f/BXINV_10026 ;
wire \i3/blk00000001/sig0000006f/CYMUXG_10025 ;
wire \i3/blk00000001/sig00000071 ;
wire \i3/blk00000001/sig0000006f/CY0G_10023 ;
wire \i3/blk00000001/sig0000006f/CYSELG_10015 ;
wire \i3/blk00000001/sig00000070 ;
wire \i3/blk00000001/sig0000006b/CY0F_10068 ;
wire \i3/blk00000001/sig0000006e ;
wire \i3/blk00000001/sig0000006b/CYSELF_10059 ;
wire \i3/blk00000001/sig0000006b/CYMUXFAST_10058 ;
wire \i3/blk00000001/sig0000006b/CYAND_10057 ;
wire \i3/blk00000001/sig0000006b/FASTCARRY_10056 ;
wire \i3/blk00000001/sig0000006b/CYMUXG2_10055 ;
wire \i3/blk00000001/sig0000006b/CYMUXF2_10054 ;
wire \i3/blk00000001/sig0000006b/CY0G_10053 ;
wire \i3/blk00000001/sig0000006b/CYSELG_10045 ;
wire \i3/blk00000001/sig0000006c ;
wire \i3/blk00000001/sig000000d2/XORF_10106 ;
wire \i3/blk00000001/sig000000d2/CYINIT_10105 ;
wire \i3/blk00000001/sig000000d2/CY0F_10104 ;
wire \i3/blk00000001/sig0000006a ;
wire \i3/blk00000001/sig000000d2/XORG_10094 ;
wire \i3/blk00000001/sig00000069 ;
wire \i3/blk00000001/sig000000d2/CYSELF_10092 ;
wire \i3/blk00000001/sig000000d2/CYMUXFAST_10091 ;
wire \i3/blk00000001/sig000000d2/CYAND_10090 ;
wire \i3/blk00000001/sig000000d2/FASTCARRY_10089 ;
wire \i3/blk00000001/sig000000d2/CYMUXG2_10088 ;
wire \i3/blk00000001/sig000000d2/CYMUXF2_10087 ;
wire \i3/blk00000001/sig000000d2/CY0G_10086 ;
wire \i3/blk00000001/sig000000d2/CYSELG_10078 ;
wire \i3/blk00000001/sig00000068 ;
wire \i3/blk00000001/sig000000d4/XORF_10145 ;
wire \i3/blk00000001/sig000000d4/CYINIT_10144 ;
wire \i3/blk00000001/sig000000d4/CY0F_10143 ;
wire \i3/blk00000001/sig00000066 ;
wire \i3/blk00000001/sig000000d4/XORG_10133 ;
wire \i3/blk00000001/sig00000065 ;
wire \i3/blk00000001/sig000000d4/CYSELF_10131 ;
wire \i3/blk00000001/sig000000d4/CYMUXFAST_10130 ;
wire \i3/blk00000001/sig000000d4/CYAND_10129 ;
wire \i3/blk00000001/sig000000d4/FASTCARRY_10128 ;
wire \i3/blk00000001/sig000000d4/CYMUXG2_10127 ;
wire \i3/blk00000001/sig000000d4/CYMUXF2_10126 ;
wire \i3/blk00000001/sig000000d4/CY0G_10125 ;
wire \i3/blk00000001/sig000000d4/CYSELG_10117 ;
wire \i3/blk00000001/sig00000064 ;
wire \i3/blk00000001/sig000000d6/XORF_10184 ;
wire \i3/blk00000001/sig000000d6/CYINIT_10183 ;
wire \i3/blk00000001/sig000000d6/CY0F_10182 ;
wire \i3/blk00000001/sig00000062 ;
wire \i3/blk00000001/sig000000d6/XORG_10172 ;
wire \i3/blk00000001/sig00000061 ;
wire \i3/blk00000001/sig000000d6/CYSELF_10170 ;
wire \i3/blk00000001/sig000000d6/CYMUXFAST_10169 ;
wire \i3/blk00000001/sig000000d6/CYAND_10168 ;
wire \i3/blk00000001/sig000000d6/FASTCARRY_10167 ;
wire \i3/blk00000001/sig000000d6/CYMUXG2_10166 ;
wire \i3/blk00000001/sig000000d6/CYMUXF2_10165 ;
wire \i3/blk00000001/sig000000d6/CY0G_10164 ;
wire \i3/blk00000001/sig000000d6/CYSELG_10156 ;
wire \i3/blk00000001/sig00000060 ;
wire \i3/blk00000001/sig000000d8/XORF_10223 ;
wire \i3/blk00000001/sig000000d8/CYINIT_10222 ;
wire \i3/blk00000001/sig000000d8/CY0F_10221 ;
wire \i3/blk00000001/sig0000005e ;
wire \i3/blk00000001/sig000000d8/XORG_10211 ;
wire \i3/blk00000001/sig0000005d ;
wire \i3/blk00000001/sig000000d8/CYSELF_10209 ;
wire \i3/blk00000001/sig000000d8/CYMUXFAST_10208 ;
wire \i3/blk00000001/sig000000d8/CYAND_10207 ;
wire \i3/blk00000001/sig000000d8/FASTCARRY_10206 ;
wire \i3/blk00000001/sig000000d8/CYMUXG2_10205 ;
wire \i3/blk00000001/sig000000d8/CYMUXF2_10204 ;
wire \i3/blk00000001/sig000000d8/CY0G_10203 ;
wire \i3/blk00000001/sig000000d8/CYSELG_10195 ;
wire \i3/blk00000001/sig0000005c ;
wire \i3/blk00000001/sig000000da/XORF_10262 ;
wire \i3/blk00000001/sig000000da/CYINIT_10261 ;
wire \i3/blk00000001/sig000000da/CY0F_10260 ;
wire \i3/blk00000001/sig0000005a ;
wire \i3/blk00000001/sig000000da/XORG_10250 ;
wire \i3/blk00000001/sig00000059 ;
wire \i3/blk00000001/sig000000da/CYSELF_10248 ;
wire \i3/blk00000001/sig000000da/CYMUXFAST_10247 ;
wire \i3/blk00000001/sig000000da/CYAND_10246 ;
wire \i3/blk00000001/sig000000da/FASTCARRY_10245 ;
wire \i3/blk00000001/sig000000da/CYMUXG2_10244 ;
wire \i3/blk00000001/sig000000da/CYMUXF2_10243 ;
wire \i3/blk00000001/sig000000da/CY0G_10242 ;
wire \i3/blk00000001/sig000000da/CYSELG_10234 ;
wire \i3/blk00000001/sig00000058 ;
wire \i3/blk00000001/sig000000dc/XORF_10301 ;
wire \i3/blk00000001/sig000000dc/CYINIT_10300 ;
wire \i3/blk00000001/sig000000dc/CY0F_10299 ;
wire \i3/blk00000001/sig00000056 ;
wire \i3/blk00000001/sig000000dc/XORG_10289 ;
wire \i3/blk00000001/sig00000055 ;
wire \i3/blk00000001/sig000000dc/CYSELF_10287 ;
wire \i3/blk00000001/sig000000dc/CYMUXFAST_10286 ;
wire \i3/blk00000001/sig000000dc/CYAND_10285 ;
wire \i3/blk00000001/sig000000dc/FASTCARRY_10284 ;
wire \i3/blk00000001/sig000000dc/CYMUXG2_10283 ;
wire \i3/blk00000001/sig000000dc/CYMUXF2_10282 ;
wire \i3/blk00000001/sig000000dc/CY0G_10281 ;
wire \i3/blk00000001/sig000000dc/CYSELG_10273 ;
wire \i3/blk00000001/sig00000054 ;
wire \i3/blk00000001/sig000000de/XORF_10316 ;
wire \i3/blk00000001/sig000000de/CYINIT_10315 ;
wire \i3/blk00000001/sig00000052 ;
wire \i3/blk00000001/sig00000185/XORF_10349 ;
wire \i3/blk00000001/sig00000185/CYINIT_10348 ;
wire \i3/blk00000001/sig00000185/F ;
wire \i3/blk00000001/sig00000185/BXINV_10337 ;
wire \i3/blk00000001/sig00000185/XORG_10335 ;
wire \i3/blk00000001/sig00000185/CYMUXG_10334 ;
wire \i3/blk00000001/sig00000185/LOGIC_ONE_10333 ;
wire \i3/blk00000001/sig000001d7 ;
wire \i3/blk00000001/sig00000185/G ;
wire \i3/blk00000001/sig00000179/XORF_10381 ;
wire \i3/blk00000001/sig00000179/LOGIC_ONE_10380 ;
wire \i3/blk00000001/sig00000179/CYINIT_10379 ;
wire \i3/blk00000001/sig00000179/F ;
wire \i3/blk00000001/sig00000179/XORG_10367 ;
wire \i3/blk00000001/sig000001cb ;
wire \i3/blk00000001/sig00000179/G ;
wire \i3/blk00000001/sig00000163/XORF_10413 ;
wire \i3/blk00000001/sig00000163/LOGIC_ONE_10412 ;
wire \i3/blk00000001/sig00000163/CYINIT_10411 ;
wire \i3/blk00000001/sig00000163/F ;
wire \i3/blk00000001/sig00000163/XORG_10399 ;
wire \i3/blk00000001/sig000001bf ;
wire \i3/blk00000001/sig00000163/G ;
wire \i3/blk00000001/sig0000014d/XORF_10445 ;
wire \i3/blk00000001/sig0000014d/LOGIC_ONE_10444 ;
wire \i3/blk00000001/sig0000014d/CYINIT_10443 ;
wire \i3/blk00000001/sig0000014d/F ;
wire \i3/blk00000001/sig0000014d/XORG_10431 ;
wire \i3/blk00000001/sig000001b3 ;
wire \i3/blk00000001/sig0000014d/G ;
wire \i3/blk00000001/sig00000137/XORF_10477 ;
wire \i3/blk00000001/sig00000137/LOGIC_ONE_10476 ;
wire \i3/blk00000001/sig00000137/CYINIT_10475 ;
wire \i3/blk00000001/sig00000137/F ;
wire \i3/blk00000001/sig00000137/XORG_10463 ;
wire \i3/blk00000001/sig000001a7 ;
wire \i3/blk00000001/sig00000137/G ;
wire \i3/blk00000001/sig00000121/XORF_10518 ;
wire \i3/blk00000001/sig00000121/CYINIT_10517 ;
wire \i3/blk00000001/sig00000121/CY0F_10516 ;
wire \i3/blk00000001/sig000001ee ;
wire \i3/blk00000001/sig000000e1 ;
wire \i3/blk00000001/sig00000121/XORG_10505 ;
wire \i3/blk00000001/sig0000019b ;
wire \i3/blk00000001/sig00000121/CYSELF_10503 ;
wire \i3/blk00000001/sig00000121/CYMUXFAST_10502 ;
wire \i3/blk00000001/sig00000121/CYAND_10501 ;
wire \i3/blk00000001/sig00000121/FASTCARRY_10500 ;
wire \i3/blk00000001/sig00000121/CYMUXG2_10499 ;
wire \i3/blk00000001/sig00000121/CYMUXF2_10498 ;
wire \i3/blk00000001/sig00000121/CY0G_10497 ;
wire \i3/blk00000001/sig000001e8 ;
wire \i3/blk00000001/sig00000121/CYSELG_10489 ;
wire \i3/blk00000001/sig000000e0 ;
wire \i3/blk00000001/sig0000010b/XORF_10533 ;
wire \i3/blk00000001/sig0000010b/CYINIT_10532 ;
wire \i3/blk00000001/sig0000023a ;
wire \i3/blk00000001/sig000001da/XORF_10571 ;
wire \i3/blk00000001/sig000001da/CYINIT_10570 ;
wire \i3/blk00000001/sig000001da/CY0F_10569 ;
wire \i3/blk00000001/sig0000022c ;
wire \i3/blk00000001/sig000001da/CYSELF_10560 ;
wire \i3/blk00000001/sig000001da/F ;
wire \i3/blk00000001/sig000001da/BXINV_10558 ;
wire \i3/blk00000001/sig000001da/XORG_10556 ;
wire \i3/blk00000001/sig000001da/CYMUXG_10555 ;
wire \i3/blk00000001/sig000001db ;
wire \i3/blk00000001/sig000001da/CY0G_10553 ;
wire \i3/blk00000001/sig0000022b ;
wire \i3/blk00000001/sig000001da/CYSELG_10544 ;
wire \i3/blk00000001/sig000001da/G ;
wire \i3/blk00000001/sig00000186/XORF_10612 ;
wire \i3/blk00000001/sig00000186/CYINIT_10611 ;
wire \i3/blk00000001/sig00000186/CY0F_10610 ;
wire \i3/blk00000001/sig00000225 ;
wire \i3/blk00000001/sig00000186/F ;
wire \i3/blk00000001/sig00000186/XORG_10599 ;
wire \i3/blk00000001/sig000001d2 ;
wire \i3/blk00000001/sig00000186/CYSELF_10597 ;
wire \i3/blk00000001/sig00000186/CYMUXFAST_10596 ;
wire \i3/blk00000001/sig00000186/CYAND_10595 ;
wire \i3/blk00000001/sig00000186/FASTCARRY_10594 ;
wire \i3/blk00000001/sig00000186/CYMUXG2_10593 ;
wire \i3/blk00000001/sig00000186/CYMUXF2_10592 ;
wire \i3/blk00000001/sig00000186/CY0G_10591 ;
wire \i3/blk00000001/sig0000021f ;
wire \i3/blk00000001/sig00000186/CYSELG_10582 ;
wire \i3/blk00000001/sig00000186/G ;
wire \i3/blk00000001/sig0000016f/XORF_10653 ;
wire \i3/blk00000001/sig0000016f/CYINIT_10652 ;
wire \i3/blk00000001/sig0000016f/CY0F_10651 ;
wire \i3/blk00000001/sig00000219 ;
wire \i3/blk00000001/sig0000016f/F ;
wire \i3/blk00000001/sig0000016f/XORG_10640 ;
wire \i3/blk00000001/sig000001c6 ;
wire \i3/blk00000001/sig0000016f/CYSELF_10638 ;
wire \i3/blk00000001/sig0000016f/CYMUXFAST_10637 ;
wire \i3/blk00000001/sig0000016f/CYAND_10636 ;
wire \i3/blk00000001/sig0000016f/FASTCARRY_10635 ;
wire \i3/blk00000001/sig0000016f/CYMUXG2_10634 ;
wire \i3/blk00000001/sig0000016f/CYMUXF2_10633 ;
wire \i3/blk00000001/sig0000016f/CY0G_10632 ;
wire \i3/blk00000001/sig00000213 ;
wire \i3/blk00000001/sig0000016f/CYSELG_10623 ;
wire \i3/blk00000001/sig0000016f/G ;
wire \i3/blk00000001/sig00000159/XORF_10694 ;
wire \i3/blk00000001/sig00000159/CYINIT_10693 ;
wire \i3/blk00000001/sig00000159/CY0F_10692 ;
wire \i3/blk00000001/sig0000020d ;
wire \i3/blk00000001/sig00000159/F ;
wire \i3/blk00000001/sig00000159/XORG_10681 ;
wire \i3/blk00000001/sig000001ba ;
wire \i3/blk00000001/sig00000159/CYSELF_10679 ;
wire \i3/blk00000001/sig00000159/CYMUXFAST_10678 ;
wire \i3/blk00000001/sig00000159/CYAND_10677 ;
wire \i3/blk00000001/sig00000159/FASTCARRY_10676 ;
wire \i3/blk00000001/sig00000159/CYMUXG2_10675 ;
wire \i3/blk00000001/sig00000159/CYMUXF2_10674 ;
wire \i3/blk00000001/sig00000159/CY0G_10673 ;
wire \i3/blk00000001/sig00000207 ;
wire \i3/blk00000001/sig00000159/CYSELG_10664 ;
wire \i3/blk00000001/sig00000159/G ;
wire \i3/blk00000001/sig00000143/XORF_10735 ;
wire \i3/blk00000001/sig00000143/CYINIT_10734 ;
wire \i3/blk00000001/sig00000143/CY0F_10733 ;
wire \i3/blk00000001/sig00000201 ;
wire \i3/blk00000001/sig00000143/F ;
wire \i3/blk00000001/sig00000143/XORG_10722 ;
wire \i3/blk00000001/sig000001ae ;
wire \i3/blk00000001/sig00000143/CYSELF_10720 ;
wire \i3/blk00000001/sig00000143/CYMUXFAST_10719 ;
wire \i3/blk00000001/sig00000143/CYAND_10718 ;
wire \i3/blk00000001/sig00000143/FASTCARRY_10717 ;
wire \i3/blk00000001/sig00000143/CYMUXG2_10716 ;
wire \i3/blk00000001/sig00000143/CYMUXF2_10715 ;
wire \i3/blk00000001/sig00000143/CY0G_10714 ;
wire \i3/blk00000001/sig000001fb ;
wire \i3/blk00000001/sig00000143/CYSELG_10705 ;
wire \i3/blk00000001/sig00000143/G ;
wire \i3/blk00000001/sig0000012d/XORF_10776 ;
wire \i3/blk00000001/sig0000012d/CYINIT_10775 ;
wire \i3/blk00000001/sig0000012d/CY0F_10774 ;
wire \i3/blk00000001/sig000001f5 ;
wire \i3/blk00000001/sig0000012d/F ;
wire \i3/blk00000001/sig0000012d/XORG_10764 ;
wire \i3/blk00000001/sig000001a2 ;
wire \i3/blk00000001/sig0000012d/CYSELF_10762 ;
wire \i3/blk00000001/sig0000012d/CYMUXFAST_10761 ;
wire \i3/blk00000001/sig0000012d/CYAND_10760 ;
wire \i3/blk00000001/sig0000012d/FASTCARRY_10759 ;
wire \i3/blk00000001/sig0000012d/CYMUXG2_10758 ;
wire \i3/blk00000001/sig0000012d/CYMUXF2_10757 ;
wire \i3/blk00000001/sig0000012d/CY0G_10756 ;
wire \i3/blk00000001/sig000001ef ;
wire \i3/blk00000001/sig0000012d/CYSELG_10748 ;
wire \i3/blk00000001/sig00000118 ;
wire \i3/blk00000001/sig00000117/XORF_10808 ;
wire \i3/blk00000001/sig00000117/CYINIT_10807 ;
wire \i3/blk00000001/sig00000117/CY0F_10806 ;
wire \i3/blk00000001/sig000001e9 ;
wire \i3/blk00000001/sig00000117/CYSELF_10798 ;
wire \i3/blk00000001/sig0000010d ;
wire \i3/blk00000001/sig00000117/XORG_10795 ;
wire \i3/blk00000001/sig00000196 ;
wire \i3/blk00000001/sig00000106 ;
wire \i3/blk00000001/sig000001e3/XORF_10846 ;
wire \i3/blk00000001/sig000001e3/CYINIT_10845 ;
wire \i3/blk00000001/sig000001e3/CY0F_10844 ;
wire \i3/blk00000001/sig00000235 ;
wire \i3/blk00000001/sig000001e3/CYSELF_10835 ;
wire \i3/blk00000001/sig000001e3/F ;
wire \i3/blk00000001/sig000001e3/BXINV_10833 ;
wire \i3/blk00000001/sig000001e3/XORG_10831 ;
wire \i3/blk00000001/sig000001e3/CYMUXG_10830 ;
wire \i3/blk00000001/sig000001e4 ;
wire \i3/blk00000001/sig000001e3/CY0G_10828 ;
wire \i3/blk00000001/sig00000234 ;
wire \i3/blk00000001/sig000001e3/CYSELG_10819 ;
wire \i3/blk00000001/sig000001e3/G ;
wire \i3/blk00000001/sig0000018f/XORF_10887 ;
wire \i3/blk00000001/sig0000018f/CYINIT_10886 ;
wire \i3/blk00000001/sig0000018f/CY0F_10885 ;
wire \i3/blk00000001/sig00000228 ;
wire \i3/blk00000001/sig0000018f/F ;
wire \i3/blk00000001/sig0000018f/XORG_10874 ;
wire \i3/blk00000001/sig000001d5 ;
wire \i3/blk00000001/sig0000018f/CYSELF_10872 ;
wire \i3/blk00000001/sig0000018f/CYMUXFAST_10871 ;
wire \i3/blk00000001/sig0000018f/CYAND_10870 ;
wire \i3/blk00000001/sig0000018f/FASTCARRY_10869 ;
wire \i3/blk00000001/sig0000018f/CYMUXG2_10868 ;
wire \i3/blk00000001/sig0000018f/CYMUXF2_10867 ;
wire \i3/blk00000001/sig0000018f/CY0G_10866 ;
wire \i3/blk00000001/sig00000222 ;
wire \i3/blk00000001/sig0000018f/CYSELG_10857 ;
wire \i3/blk00000001/sig0000018f/G ;
wire \i3/blk00000001/sig00000175/XORF_10928 ;
wire \i3/blk00000001/sig00000175/CYINIT_10927 ;
wire \i3/blk00000001/sig00000175/CY0F_10926 ;
wire \i3/blk00000001/sig0000021c ;
wire \i3/blk00000001/sig00000175/F ;
wire \i3/blk00000001/sig00000175/XORG_10915 ;
wire \i3/blk00000001/sig000001c9 ;
wire \i3/blk00000001/sig00000175/CYSELF_10913 ;
wire \i3/blk00000001/sig00000175/CYMUXFAST_10912 ;
wire \i3/blk00000001/sig00000175/CYAND_10911 ;
wire \i3/blk00000001/sig00000175/FASTCARRY_10910 ;
wire \i3/blk00000001/sig00000175/CYMUXG2_10909 ;
wire \i3/blk00000001/sig00000175/CYMUXF2_10908 ;
wire \i3/blk00000001/sig00000175/CY0G_10907 ;
wire \i3/blk00000001/sig00000216 ;
wire \i3/blk00000001/sig00000175/CYSELG_10898 ;
wire \i3/blk00000001/sig00000175/G ;
wire \i3/blk00000001/sig0000015f/XORF_10969 ;
wire \i3/blk00000001/sig0000015f/CYINIT_10968 ;
wire \i3/blk00000001/sig0000015f/CY0F_10967 ;
wire \i3/blk00000001/sig00000210 ;
wire \i3/blk00000001/sig0000015f/F ;
wire \i3/blk00000001/sig0000015f/XORG_10956 ;
wire \i3/blk00000001/sig000001bd ;
wire \i3/blk00000001/sig0000015f/CYSELF_10954 ;
wire \i3/blk00000001/sig0000015f/CYMUXFAST_10953 ;
wire \i3/blk00000001/sig0000015f/CYAND_10952 ;
wire \i3/blk00000001/sig0000015f/FASTCARRY_10951 ;
wire \i3/blk00000001/sig0000015f/CYMUXG2_10950 ;
wire \i3/blk00000001/sig0000015f/CYMUXF2_10949 ;
wire \i3/blk00000001/sig0000015f/CY0G_10948 ;
wire \i3/blk00000001/sig0000020a ;
wire \i3/blk00000001/sig0000015f/CYSELG_10939 ;
wire \i3/blk00000001/sig0000015f/G ;
wire \i3/blk00000001/sig00000149/XORF_11010 ;
wire \i3/blk00000001/sig00000149/CYINIT_11009 ;
wire \i3/blk00000001/sig00000149/CY0F_11008 ;
wire \i3/blk00000001/sig00000204 ;
wire \i3/blk00000001/sig00000149/F ;
wire \i3/blk00000001/sig00000149/XORG_10997 ;
wire \i3/blk00000001/sig000001b1 ;
wire \i3/blk00000001/sig00000149/CYSELF_10995 ;
wire \i3/blk00000001/sig00000149/CYMUXFAST_10994 ;
wire \i3/blk00000001/sig00000149/CYAND_10993 ;
wire \i3/blk00000001/sig00000149/FASTCARRY_10992 ;
wire \i3/blk00000001/sig00000149/CYMUXG2_10991 ;
wire \i3/blk00000001/sig00000149/CYMUXF2_10990 ;
wire \i3/blk00000001/sig00000149/CY0G_10989 ;
wire \i3/blk00000001/sig000001fe ;
wire \i3/blk00000001/sig00000149/CYSELG_10980 ;
wire \i3/blk00000001/sig00000149/G ;
wire \i3/blk00000001/sig00000133/XORF_11051 ;
wire \i3/blk00000001/sig00000133/CYINIT_11050 ;
wire \i3/blk00000001/sig00000133/CY0F_11049 ;
wire \i3/blk00000001/sig000001f8 ;
wire \i3/blk00000001/sig00000133/F ;
wire \i3/blk00000001/sig00000133/XORG_11039 ;
wire \i3/blk00000001/sig000001a5 ;
wire \i3/blk00000001/sig00000133/CYSELF_11037 ;
wire \i3/blk00000001/sig00000133/CYMUXFAST_11036 ;
wire \i3/blk00000001/sig00000133/CYAND_11035 ;
wire \i3/blk00000001/sig00000133/FASTCARRY_11034 ;
wire \i3/blk00000001/sig00000133/CYMUXG2_11033 ;
wire \i3/blk00000001/sig00000133/CYMUXF2_11032 ;
wire \i3/blk00000001/sig00000133/CY0G_11031 ;
wire \i3/blk00000001/sig000001f2 ;
wire \i3/blk00000001/sig00000133/CYSELG_11023 ;
wire \i3/blk00000001/sig0000011e ;
wire \i3/blk00000001/sig0000011d/XORF_11083 ;
wire \i3/blk00000001/sig0000011d/CYINIT_11082 ;
wire \i3/blk00000001/sig0000011d/CY0F_11081 ;
wire \i3/blk00000001/sig000001ec ;
wire \i3/blk00000001/sig0000011d/CYSELF_11073 ;
wire \i3/blk00000001/sig00000113 ;
wire \i3/blk00000001/sig0000011d/XORG_11070 ;
wire \i3/blk00000001/sig00000199 ;
wire \i3/blk00000001/sig00000109 ;
wire \i3/blk00000001/sig000001dd/XORF_11121 ;
wire \i3/blk00000001/sig000001dd/CYINIT_11120 ;
wire \i3/blk00000001/sig000001dd/CY0F_11119 ;
wire \i3/blk00000001/sig0000022f ;
wire \i3/blk00000001/sig000001dd/CYSELF_11110 ;
wire \i3/blk00000001/sig000001dd/F ;
wire \i3/blk00000001/sig000001dd/BXINV_11108 ;
wire \i3/blk00000001/sig000001dd/XORG_11106 ;
wire \i3/blk00000001/sig000001dd/CYMUXG_11105 ;
wire \i3/blk00000001/sig000001de ;
wire \i3/blk00000001/sig000001dd/CY0G_11103 ;
wire \i3/blk00000001/sig0000022e ;
wire \i3/blk00000001/sig000001dd/CYSELG_11094 ;
wire \i3/blk00000001/sig000001dd/G ;
wire \i3/blk00000001/sig00000189/XORF_11162 ;
wire \i3/blk00000001/sig00000189/CYINIT_11161 ;
wire \i3/blk00000001/sig00000189/CY0F_11160 ;
wire \i3/blk00000001/sig00000226 ;
wire \i3/blk00000001/sig00000189/F ;
wire \i3/blk00000001/sig00000189/XORG_11149 ;
wire \i3/blk00000001/sig000001d3 ;
wire \i3/blk00000001/sig00000189/CYSELF_11147 ;
wire \i3/blk00000001/sig00000189/CYMUXFAST_11146 ;
wire \i3/blk00000001/sig00000189/CYAND_11145 ;
wire \i3/blk00000001/sig00000189/FASTCARRY_11144 ;
wire \i3/blk00000001/sig00000189/CYMUXG2_11143 ;
wire \i3/blk00000001/sig00000189/CYMUXF2_11142 ;
wire \i3/blk00000001/sig00000189/CY0G_11141 ;
wire \i3/blk00000001/sig00000220 ;
wire \i3/blk00000001/sig00000189/CYSELG_11132 ;
wire \i3/blk00000001/sig00000189/G ;
wire \i3/blk00000001/sig00000171/XORF_11203 ;
wire \i3/blk00000001/sig00000171/CYINIT_11202 ;
wire \i3/blk00000001/sig00000171/CY0F_11201 ;
wire \i3/blk00000001/sig0000021a ;
wire \i3/blk00000001/sig00000171/F ;
wire \i3/blk00000001/sig00000171/XORG_11190 ;
wire \i3/blk00000001/sig000001c7 ;
wire \i3/blk00000001/sig00000171/CYSELF_11188 ;
wire \i3/blk00000001/sig00000171/CYMUXFAST_11187 ;
wire \i3/blk00000001/sig00000171/CYAND_11186 ;
wire \i3/blk00000001/sig00000171/FASTCARRY_11185 ;
wire \i3/blk00000001/sig00000171/CYMUXG2_11184 ;
wire \i3/blk00000001/sig00000171/CYMUXF2_11183 ;
wire \i3/blk00000001/sig00000171/CY0G_11182 ;
wire \i3/blk00000001/sig00000214 ;
wire \i3/blk00000001/sig00000171/CYSELG_11173 ;
wire \i3/blk00000001/sig00000171/G ;
wire \i3/blk00000001/sig0000015b/XORF_11244 ;
wire \i3/blk00000001/sig0000015b/CYINIT_11243 ;
wire \i3/blk00000001/sig0000015b/CY0F_11242 ;
wire \i3/blk00000001/sig0000020e ;
wire \i3/blk00000001/sig0000015b/F ;
wire \i3/blk00000001/sig0000015b/XORG_11231 ;
wire \i3/blk00000001/sig000001bb ;
wire \i3/blk00000001/sig0000015b/CYSELF_11229 ;
wire \i3/blk00000001/sig0000015b/CYMUXFAST_11228 ;
wire \i3/blk00000001/sig0000015b/CYAND_11227 ;
wire \i3/blk00000001/sig0000015b/FASTCARRY_11226 ;
wire \i3/blk00000001/sig0000015b/CYMUXG2_11225 ;
wire \i3/blk00000001/sig0000015b/CYMUXF2_11224 ;
wire \i3/blk00000001/sig0000015b/CY0G_11223 ;
wire \i3/blk00000001/sig00000208 ;
wire \i3/blk00000001/sig0000015b/CYSELG_11214 ;
wire \i3/blk00000001/sig0000015b/G ;
wire \i3/blk00000001/sig00000145/XORF_11285 ;
wire \i3/blk00000001/sig00000145/CYINIT_11284 ;
wire \i3/blk00000001/sig00000145/CY0F_11283 ;
wire \i3/blk00000001/sig00000202 ;
wire \i3/blk00000001/sig00000145/F ;
wire \i3/blk00000001/sig00000145/XORG_11272 ;
wire \i3/blk00000001/sig000001af ;
wire \i3/blk00000001/sig00000145/CYSELF_11270 ;
wire \i3/blk00000001/sig00000145/CYMUXFAST_11269 ;
wire \i3/blk00000001/sig00000145/CYAND_11268 ;
wire \i3/blk00000001/sig00000145/FASTCARRY_11267 ;
wire \i3/blk00000001/sig00000145/CYMUXG2_11266 ;
wire \i3/blk00000001/sig00000145/CYMUXF2_11265 ;
wire \i3/blk00000001/sig00000145/CY0G_11264 ;
wire \i3/blk00000001/sig000001fc ;
wire \i3/blk00000001/sig00000145/CYSELG_11255 ;
wire \i3/blk00000001/sig00000145/G ;
wire \i3/blk00000001/sig0000012f/XORF_11326 ;
wire \i3/blk00000001/sig0000012f/CYINIT_11325 ;
wire \i3/blk00000001/sig0000012f/CY0F_11324 ;
wire \i3/blk00000001/sig000001f6 ;
wire \i3/blk00000001/sig0000012f/F ;
wire \i3/blk00000001/sig0000012f/XORG_11314 ;
wire \i3/blk00000001/sig000001a3 ;
wire \i3/blk00000001/sig0000012f/CYSELF_11312 ;
wire \i3/blk00000001/sig0000012f/CYMUXFAST_11311 ;
wire \i3/blk00000001/sig0000012f/CYAND_11310 ;
wire \i3/blk00000001/sig0000012f/FASTCARRY_11309 ;
wire \i3/blk00000001/sig0000012f/CYMUXG2_11308 ;
wire \i3/blk00000001/sig0000012f/CYMUXF2_11307 ;
wire \i3/blk00000001/sig0000012f/CY0G_11306 ;
wire \i3/blk00000001/sig000001f0 ;
wire \i3/blk00000001/sig0000012f/CYSELG_11298 ;
wire \i3/blk00000001/sig0000011a ;
wire \i3/blk00000001/sig00000119/XORF_11358 ;
wire \i3/blk00000001/sig00000119/CYINIT_11357 ;
wire \i3/blk00000001/sig00000119/CY0F_11356 ;
wire \i3/blk00000001/sig000001ea ;
wire \i3/blk00000001/sig00000119/CYSELF_11348 ;
wire \i3/blk00000001/sig0000010f ;
wire \i3/blk00000001/sig00000119/XORG_11345 ;
wire \i3/blk00000001/sig00000197 ;
wire \i3/blk00000001/sig00000107 ;
wire \i3/blk00000001/sig000001e5/CYINIT_11391 ;
wire \i3/blk00000001/sig000001e5/CY0F_11390 ;
wire \i3/blk00000001/sig00000238 ;
wire \i3/blk00000001/sig000001e5/CYSELF_11381 ;
wire \i3/blk00000001/sig000001e5/F ;
wire \i3/blk00000001/sig000001e5/BXINV_11379 ;
wire \i3/blk00000001/sig000001e5/CYMUXG_11378 ;
wire \i3/blk00000001/sig000001e6 ;
wire \i3/blk00000001/sig000001e5/CY0G_11376 ;
wire \i3/blk00000001/sig00000237 ;
wire \i3/blk00000001/sig000001e5/CYSELG_11367 ;
wire \i3/blk00000001/sig000001e5/G ;
wire \i3/blk00000001/sig00000192/XORF_11431 ;
wire \i3/blk00000001/sig00000192/CYINIT_11430 ;
wire \i3/blk00000001/sig00000192/CY0F_11429 ;
wire \i3/blk00000001/sig00000229 ;
wire \i3/blk00000001/sig00000192/F ;
wire \i3/blk00000001/sig00000192/XORG_11418 ;
wire \i3/blk00000001/sig000001d6 ;
wire \i3/blk00000001/sig00000192/CYSELF_11416 ;
wire \i3/blk00000001/sig00000192/CYMUXFAST_11415 ;
wire \i3/blk00000001/sig00000192/CYAND_11414 ;
wire \i3/blk00000001/sig00000192/FASTCARRY_11413 ;
wire \i3/blk00000001/sig00000192/CYMUXG2_11412 ;
wire \i3/blk00000001/sig00000192/CYMUXF2_11411 ;
wire \i3/blk00000001/sig00000192/CY0G_11410 ;
wire \i3/blk00000001/sig00000223 ;
wire \i3/blk00000001/sig00000192/CYSELG_11401 ;
wire \i3/blk00000001/sig00000192/G ;
wire \i3/blk00000001/sig00000177/XORF_11472 ;
wire \i3/blk00000001/sig00000177/CYINIT_11471 ;
wire \i3/blk00000001/sig00000177/CY0F_11470 ;
wire \i3/blk00000001/sig0000021d ;
wire \i3/blk00000001/sig00000177/F ;
wire \i3/blk00000001/sig00000177/XORG_11459 ;
wire \i3/blk00000001/sig000001ca ;
wire \i3/blk00000001/sig00000177/CYSELF_11457 ;
wire \i3/blk00000001/sig00000177/CYMUXFAST_11456 ;
wire \i3/blk00000001/sig00000177/CYAND_11455 ;
wire \i3/blk00000001/sig00000177/FASTCARRY_11454 ;
wire \i3/blk00000001/sig00000177/CYMUXG2_11453 ;
wire \i3/blk00000001/sig00000177/CYMUXF2_11452 ;
wire \i3/blk00000001/sig00000177/CY0G_11451 ;
wire \i3/blk00000001/sig00000217 ;
wire \i3/blk00000001/sig00000177/CYSELG_11442 ;
wire \i3/blk00000001/sig00000177/G ;
wire \i3/blk00000001/sig00000161/XORF_11513 ;
wire \i3/blk00000001/sig00000161/CYINIT_11512 ;
wire \i3/blk00000001/sig00000161/CY0F_11511 ;
wire \i3/blk00000001/sig00000211 ;
wire \i3/blk00000001/sig00000161/F ;
wire \i3/blk00000001/sig00000161/XORG_11500 ;
wire \i3/blk00000001/sig000001be ;
wire \i3/blk00000001/sig00000161/CYSELF_11498 ;
wire \i3/blk00000001/sig00000161/CYMUXFAST_11497 ;
wire \i3/blk00000001/sig00000161/CYAND_11496 ;
wire \i3/blk00000001/sig00000161/FASTCARRY_11495 ;
wire \i3/blk00000001/sig00000161/CYMUXG2_11494 ;
wire \i3/blk00000001/sig00000161/CYMUXF2_11493 ;
wire \i3/blk00000001/sig00000161/CY0G_11492 ;
wire \i3/blk00000001/sig0000020b ;
wire \i3/blk00000001/sig00000161/CYSELG_11483 ;
wire \i3/blk00000001/sig00000161/G ;
wire \i3/blk00000001/sig0000014b/XORF_11554 ;
wire \i3/blk00000001/sig0000014b/CYINIT_11553 ;
wire \i3/blk00000001/sig0000014b/CY0F_11552 ;
wire \i3/blk00000001/sig00000205 ;
wire \i3/blk00000001/sig0000014b/F ;
wire \i3/blk00000001/sig0000014b/XORG_11541 ;
wire \i3/blk00000001/sig000001b2 ;
wire \i3/blk00000001/sig0000014b/CYSELF_11539 ;
wire \i3/blk00000001/sig0000014b/CYMUXFAST_11538 ;
wire \i3/blk00000001/sig0000014b/CYAND_11537 ;
wire \i3/blk00000001/sig0000014b/FASTCARRY_11536 ;
wire \i3/blk00000001/sig0000014b/CYMUXG2_11535 ;
wire \i3/blk00000001/sig0000014b/CYMUXF2_11534 ;
wire \i3/blk00000001/sig0000014b/CY0G_11533 ;
wire \i3/blk00000001/sig000001ff ;
wire \i3/blk00000001/sig0000014b/CYSELG_11524 ;
wire \i3/blk00000001/sig0000014b/G ;
wire \i3/blk00000001/sig00000135/XORF_11595 ;
wire \i3/blk00000001/sig00000135/CYINIT_11594 ;
wire \i3/blk00000001/sig00000135/CY0F_11593 ;
wire \i3/blk00000001/sig000001f9 ;
wire \i3/blk00000001/sig00000135/F ;
wire \i3/blk00000001/sig00000135/XORG_11582 ;
wire \i3/blk00000001/sig000001a6 ;
wire \i3/blk00000001/sig00000135/CYSELF_11580 ;
wire \i3/blk00000001/sig00000135/CYMUXFAST_11579 ;
wire \i3/blk00000001/sig00000135/CYAND_11578 ;
wire \i3/blk00000001/sig00000135/FASTCARRY_11577 ;
wire \i3/blk00000001/sig00000135/CYMUXG2_11576 ;
wire \i3/blk00000001/sig00000135/CYMUXF2_11575 ;
wire \i3/blk00000001/sig00000135/CY0G_11574 ;
wire \i3/blk00000001/sig000001f3 ;
wire \i3/blk00000001/sig00000135/CYSELG_11565 ;
wire \i3/blk00000001/sig00000135/G ;
wire \i3/blk00000001/sig0000011f/XORF_11627 ;
wire \i3/blk00000001/sig0000011f/CYINIT_11626 ;
wire \i3/blk00000001/sig0000011f/CY0F_11625 ;
wire \i3/blk00000001/sig000001ed ;
wire \i3/blk00000001/sig0000011f/CYSELF_11616 ;
wire \i3/blk00000001/sig0000011f/F ;
wire \i3/blk00000001/sig0000011f/XORG_11613 ;
wire \i3/blk00000001/sig0000019a ;
wire \i3/blk00000001/sig0000011f/G ;
wire \i3/blk00000001/sig000001e0/XORF_11665 ;
wire \i3/blk00000001/sig000001e0/CYINIT_11664 ;
wire \i3/blk00000001/sig000001e0/CY0F_11663 ;
wire \i3/blk00000001/sig00000232 ;
wire \i3/blk00000001/sig000001e0/CYSELF_11654 ;
wire \i3/blk00000001/sig000001e0/F ;
wire \i3/blk00000001/sig000001e0/BXINV_11652 ;
wire \i3/blk00000001/sig000001e0/XORG_11650 ;
wire \i3/blk00000001/sig000001e0/CYMUXG_11649 ;
wire \i3/blk00000001/sig000001e1 ;
wire \i3/blk00000001/sig000001e0/CY0G_11647 ;
wire \i3/blk00000001/sig00000231 ;
wire \i3/blk00000001/sig000001e0/CYSELG_11638 ;
wire \i3/blk00000001/sig000001e0/G ;
wire \i3/blk00000001/sig0000018c/XORF_11706 ;
wire \i3/blk00000001/sig0000018c/CYINIT_11705 ;
wire \i3/blk00000001/sig0000018c/CY0F_11704 ;
wire \i3/blk00000001/sig00000227 ;
wire \i3/blk00000001/sig0000018c/F ;
wire \i3/blk00000001/sig0000018c/XORG_11693 ;
wire \i3/blk00000001/sig000001d4 ;
wire \i3/blk00000001/sig0000018c/CYSELF_11691 ;
wire \i3/blk00000001/sig0000018c/CYMUXFAST_11690 ;
wire \i3/blk00000001/sig0000018c/CYAND_11689 ;
wire \i3/blk00000001/sig0000018c/FASTCARRY_11688 ;
wire \i3/blk00000001/sig0000018c/CYMUXG2_11687 ;
wire \i3/blk00000001/sig0000018c/CYMUXF2_11686 ;
wire \i3/blk00000001/sig0000018c/CY0G_11685 ;
wire \i3/blk00000001/sig00000221 ;
wire \i3/blk00000001/sig0000018c/CYSELG_11676 ;
wire \i3/blk00000001/sig0000018c/G ;
wire \i3/blk00000001/sig00000173/XORF_11747 ;
wire \i3/blk00000001/sig00000173/CYINIT_11746 ;
wire \i3/blk00000001/sig00000173/CY0F_11745 ;
wire \i3/blk00000001/sig0000021b ;
wire \i3/blk00000001/sig00000173/F ;
wire \i3/blk00000001/sig00000173/XORG_11734 ;
wire \i3/blk00000001/sig000001c8 ;
wire \i3/blk00000001/sig00000173/CYSELF_11732 ;
wire \i3/blk00000001/sig00000173/CYMUXFAST_11731 ;
wire \i3/blk00000001/sig00000173/CYAND_11730 ;
wire \i3/blk00000001/sig00000173/FASTCARRY_11729 ;
wire \i3/blk00000001/sig00000173/CYMUXG2_11728 ;
wire \i3/blk00000001/sig00000173/CYMUXF2_11727 ;
wire \i3/blk00000001/sig00000173/CY0G_11726 ;
wire \i3/blk00000001/sig00000215 ;
wire \i3/blk00000001/sig00000173/CYSELG_11717 ;
wire \i3/blk00000001/sig00000173/G ;
wire \i3/blk00000001/sig0000015d/XORF_11788 ;
wire \i3/blk00000001/sig0000015d/CYINIT_11787 ;
wire \i3/blk00000001/sig0000015d/CY0F_11786 ;
wire \i3/blk00000001/sig0000020f ;
wire \i3/blk00000001/sig0000015d/F ;
wire \i3/blk00000001/sig0000015d/XORG_11775 ;
wire \i3/blk00000001/sig000001bc ;
wire \i3/blk00000001/sig0000015d/CYSELF_11773 ;
wire \i3/blk00000001/sig0000015d/CYMUXFAST_11772 ;
wire \i3/blk00000001/sig0000015d/CYAND_11771 ;
wire \i3/blk00000001/sig0000015d/FASTCARRY_11770 ;
wire \i3/blk00000001/sig0000015d/CYMUXG2_11769 ;
wire \i3/blk00000001/sig0000015d/CYMUXF2_11768 ;
wire \i3/blk00000001/sig0000015d/CY0G_11767 ;
wire \i3/blk00000001/sig00000209 ;
wire \i3/blk00000001/sig0000015d/CYSELG_11758 ;
wire \i3/blk00000001/sig0000015d/G ;
wire \i3/blk00000001/sig00000147/XORF_11829 ;
wire \i3/blk00000001/sig00000147/CYINIT_11828 ;
wire \i3/blk00000001/sig00000147/CY0F_11827 ;
wire \i3/blk00000001/sig00000203 ;
wire \i3/blk00000001/sig00000147/F ;
wire \i3/blk00000001/sig00000147/XORG_11816 ;
wire \i3/blk00000001/sig000001b0 ;
wire \i3/blk00000001/sig00000147/CYSELF_11814 ;
wire \i3/blk00000001/sig00000147/CYMUXFAST_11813 ;
wire \i3/blk00000001/sig00000147/CYAND_11812 ;
wire \i3/blk00000001/sig00000147/FASTCARRY_11811 ;
wire \i3/blk00000001/sig00000147/CYMUXG2_11810 ;
wire \i3/blk00000001/sig00000147/CYMUXF2_11809 ;
wire \i3/blk00000001/sig00000147/CY0G_11808 ;
wire \i3/blk00000001/sig000001fd ;
wire \i3/blk00000001/sig00000147/CYSELG_11799 ;
wire \i3/blk00000001/sig00000147/G ;
wire \i3/blk00000001/sig00000131/XORF_11870 ;
wire \i3/blk00000001/sig00000131/CYINIT_11869 ;
wire \i3/blk00000001/sig00000131/CY0F_11868 ;
wire \i3/blk00000001/sig000001f7 ;
wire \i3/blk00000001/sig00000131/F ;
wire \i3/blk00000001/sig00000131/XORG_11858 ;
wire \i3/blk00000001/sig000001a4 ;
wire \i3/blk00000001/sig00000131/CYSELF_11856 ;
wire \i3/blk00000001/sig00000131/CYMUXFAST_11855 ;
wire \i3/blk00000001/sig00000131/CYAND_11854 ;
wire \i3/blk00000001/sig00000131/FASTCARRY_11853 ;
wire \i3/blk00000001/sig00000131/CYMUXG2_11852 ;
wire \i3/blk00000001/sig00000131/CYMUXF2_11851 ;
wire \i3/blk00000001/sig00000131/CY0G_11850 ;
wire \i3/blk00000001/sig000001f1 ;
wire \i3/blk00000001/sig00000131/CYSELG_11842 ;
wire \i3/blk00000001/sig0000011c ;
wire \i3/blk00000001/sig0000011b/XORF_11902 ;
wire \i3/blk00000001/sig0000011b/CYINIT_11901 ;
wire \i3/blk00000001/sig0000011b/CY0F_11900 ;
wire \i3/blk00000001/sig000001eb ;
wire \i3/blk00000001/sig0000011b/CYSELF_11892 ;
wire \i3/blk00000001/sig00000111 ;
wire \i3/blk00000001/sig0000011b/XORG_11889 ;
wire \i3/blk00000001/sig00000198 ;
wire \i3/blk00000001/sig00000108 ;
wire \i3/blk00000001/sig000000c4/XORF_11938 ;
wire \i3/blk00000001/sig000000c4/CYINIT_11937 ;
wire \i3/blk00000001/sig000000c4/CY0F_11936 ;
wire \i3/blk00000001/sig000000c4/CYSELF_11928 ;
wire \i3/blk00000001/sig0000008d ;
wire \i3/blk00000001/sig000000c4/BXINV_11926 ;
wire \i3/blk00000001/sig000000c4/XORG_11924 ;
wire \i3/blk00000001/sig000000c4/CYMUXG_11923 ;
wire \i3/blk00000001/sig0000008c ;
wire \i3/blk00000001/sig000000c4/CY0G_11921 ;
wire \i3/blk00000001/sig000000c4/CYSELG_11913 ;
wire \i3/blk00000001/sig0000008b ;
wire \i3/blk00000001/sig000000c6/XORF_11977 ;
wire \i3/blk00000001/sig000000c6/CYINIT_11976 ;
wire \i3/blk00000001/sig000000c6/CY0F_11975 ;
wire \i3/blk00000001/sig00000089 ;
wire \i3/blk00000001/sig000000c6/XORG_11965 ;
wire \i3/blk00000001/sig00000088 ;
wire \i3/blk00000001/sig000000c6/CYSELF_11963 ;
wire \i3/blk00000001/sig000000c6/CYMUXFAST_11962 ;
wire \i3/blk00000001/sig000000c6/CYAND_11961 ;
wire \i3/blk00000001/sig000000c6/FASTCARRY_11960 ;
wire \i3/blk00000001/sig000000c6/CYMUXG2_11959 ;
wire \i3/blk00000001/sig000000c6/CYMUXF2_11958 ;
wire \i3/blk00000001/sig000000c6/CY0G_11957 ;
wire \i3/blk00000001/sig000000c6/CYSELG_11949 ;
wire \i3/blk00000001/sig00000087 ;
wire \i3/blk00000001/sig000000c8/XORF_12016 ;
wire \i3/blk00000001/sig000000c8/CYINIT_12015 ;
wire \i3/blk00000001/sig000000c8/CY0F_12014 ;
wire \i3/blk00000001/sig00000085 ;
wire \i3/blk00000001/sig000000c8/XORG_12004 ;
wire \i3/blk00000001/sig00000084 ;
wire \i3/blk00000001/sig000000c8/CYSELF_12002 ;
wire \i3/blk00000001/sig000000c8/CYMUXFAST_12001 ;
wire \i3/blk00000001/sig000000c8/CYAND_12000 ;
wire \i3/blk00000001/sig000000c8/FASTCARRY_11999 ;
wire \i3/blk00000001/sig000000c8/CYMUXG2_11998 ;
wire \i3/blk00000001/sig000000c8/CYMUXF2_11997 ;
wire \i3/blk00000001/sig000000c8/CY0G_11996 ;
wire \i3/blk00000001/sig000000c8/CYSELG_11988 ;
wire \i3/blk00000001/sig00000083 ;
wire \i3/blk00000001/sig000000ca/XORF_12055 ;
wire \i3/blk00000001/sig000000ca/CYINIT_12054 ;
wire \i3/blk00000001/sig000000ca/CY0F_12053 ;
wire \i3/blk00000001/sig00000081 ;
wire \i3/blk00000001/sig000000ca/XORG_12043 ;
wire \i3/blk00000001/sig00000080 ;
wire \i3/blk00000001/sig000000ca/CYSELF_12041 ;
wire \i3/blk00000001/sig000000ca/CYMUXFAST_12040 ;
wire \i3/blk00000001/sig000000ca/CYAND_12039 ;
wire \i3/blk00000001/sig000000ca/FASTCARRY_12038 ;
wire \i3/blk00000001/sig000000ca/CYMUXG2_12037 ;
wire \i3/blk00000001/sig000000ca/CYMUXF2_12036 ;
wire \i3/blk00000001/sig000000ca/CY0G_12035 ;
wire \i3/blk00000001/sig000000ca/CYSELG_12027 ;
wire \i3/blk00000001/sig0000007f ;
wire \i3/blk00000001/sig000000cc/XORF_12094 ;
wire \i3/blk00000001/sig000000cc/CYINIT_12093 ;
wire \i3/blk00000001/sig000000cc/CY0F_12092 ;
wire \i3/blk00000001/sig0000007d ;
wire \i3/blk00000001/sig000000cc/XORG_12082 ;
wire \i3/blk00000001/sig0000007c ;
wire \i3/blk00000001/sig000000cc/CYSELF_12080 ;
wire \i3/blk00000001/sig000000cc/CYMUXFAST_12079 ;
wire \i3/blk00000001/sig000000cc/CYAND_12078 ;
wire \i3/blk00000001/sig000000cc/FASTCARRY_12077 ;
wire \i3/blk00000001/sig000000cc/CYMUXG2_12076 ;
wire \i3/blk00000001/sig000000cc/CYMUXF2_12075 ;
wire \i3/blk00000001/sig000000cc/CY0G_12074 ;
wire \i3/blk00000001/sig000000cc/CYSELG_12066 ;
wire \i3/blk00000001/sig0000007b ;
wire \i3/blk00000001/sig000000ce/XORF_12133 ;
wire \i3/blk00000001/sig000000ce/CYINIT_12132 ;
wire \i3/blk00000001/sig000000ce/CY0F_12131 ;
wire \i3/blk00000001/sig00000079 ;
wire \i3/blk00000001/sig000000ce/XORG_12121 ;
wire \i3/blk00000001/sig00000078 ;
wire \i3/blk00000001/sig000000ce/CYSELF_12119 ;
wire \i3/blk00000001/sig000000ce/CYMUXFAST_12118 ;
wire \i3/blk00000001/sig000000ce/CYAND_12117 ;
wire \i3/blk00000001/sig000000ce/FASTCARRY_12116 ;
wire \i3/blk00000001/sig000000ce/CYMUXG2_12115 ;
wire \i3/blk00000001/sig000000ce/CYMUXF2_12114 ;
wire \i3/blk00000001/sig000000ce/CY0G_12113 ;
wire \i3/blk00000001/sig000000ce/CYSELG_12105 ;
wire \i3/blk00000001/sig00000077 ;
wire \i3/blk00000001/sig000000d0/XORF_12148 ;
wire \i3/blk00000001/sig000000d0/CYINIT_12147 ;
wire \i3/blk00000001/sig00000075 ;
wire \i3/blk00000001/sig000000eb/XORF_12184 ;
wire \i3/blk00000001/sig000000eb/CYINIT_12183 ;
wire \i3/blk00000001/sig000000eb/CY0F_12182 ;
wire \i3/blk00000001/sig000000eb/CYSELF_12174 ;
wire \i3/blk00000001/sig000000a8 ;
wire \i3/blk00000001/sig000000eb/BXINV_12172 ;
wire \i3/blk00000001/sig000000eb/XORG_12170 ;
wire \i3/blk00000001/sig000000eb/CYMUXG_12169 ;
wire \i3/blk00000001/sig000000a7 ;
wire \i3/blk00000001/sig000000eb/CY0G_12167 ;
wire \i3/blk00000001/sig000000eb/CYSELG_12159 ;
wire \i3/blk00000001/sig000000a6 ;
wire \i3/blk00000001/sig000000ed/XORF_12223 ;
wire \i3/blk00000001/sig000000ed/CYINIT_12222 ;
wire \i3/blk00000001/sig000000ed/CY0F_12221 ;
wire \i3/blk00000001/sig000000a4 ;
wire \i3/blk00000001/sig000000ed/XORG_12211 ;
wire \i3/blk00000001/sig000000a3 ;
wire \i3/blk00000001/sig000000ed/CYSELF_12209 ;
wire \i3/blk00000001/sig000000ed/CYMUXFAST_12208 ;
wire \i3/blk00000001/sig000000ed/CYAND_12207 ;
wire \i3/blk00000001/sig000000ed/FASTCARRY_12206 ;
wire \i3/blk00000001/sig000000ed/CYMUXG2_12205 ;
wire \i3/blk00000001/sig000000ed/CYMUXF2_12204 ;
wire \i3/blk00000001/sig000000ed/CY0G_12203 ;
wire \i3/blk00000001/sig000000ed/CYSELG_12195 ;
wire \i3/blk00000001/sig000000a2 ;
wire \i3/blk00000001/sig000000ef/XORF_12262 ;
wire \i3/blk00000001/sig000000ef/CYINIT_12261 ;
wire \i3/blk00000001/sig000000ef/CY0F_12260 ;
wire \i3/blk00000001/sig000000a0 ;
wire \i3/blk00000001/sig000000ef/XORG_12250 ;
wire \i3/blk00000001/sig0000009f ;
wire \i3/blk00000001/sig000000ef/CYSELF_12248 ;
wire \i3/blk00000001/sig000000ef/CYMUXFAST_12247 ;
wire \i3/blk00000001/sig000000ef/CYAND_12246 ;
wire \i3/blk00000001/sig000000ef/FASTCARRY_12245 ;
wire \i3/blk00000001/sig000000ef/CYMUXG2_12244 ;
wire \i3/blk00000001/sig000000ef/CYMUXF2_12243 ;
wire \i3/blk00000001/sig000000ef/CY0G_12242 ;
wire \i3/blk00000001/sig000000ef/CYSELG_12234 ;
wire \i3/blk00000001/sig0000009e ;
wire \i3/blk00000001/sig000000f1/XORF_12301 ;
wire \i3/blk00000001/sig000000f1/CYINIT_12300 ;
wire \i3/blk00000001/sig000000f1/CY0F_12299 ;
wire \i3/blk00000001/sig0000009c ;
wire \i3/blk00000001/sig000000f1/XORG_12289 ;
wire \i3/blk00000001/sig0000009b ;
wire \i3/blk00000001/sig000000f1/CYSELF_12287 ;
wire \i3/blk00000001/sig000000f1/CYMUXFAST_12286 ;
wire \i3/blk00000001/sig000000f1/CYAND_12285 ;
wire \i3/blk00000001/sig000000f1/FASTCARRY_12284 ;
wire \i3/blk00000001/sig000000f1/CYMUXG2_12283 ;
wire \i3/blk00000001/sig000000f1/CYMUXF2_12282 ;
wire \i3/blk00000001/sig000000f1/CY0G_12281 ;
wire \i3/blk00000001/sig000000f1/CYSELG_12273 ;
wire \i3/blk00000001/sig0000009a ;
wire \i3/blk00000001/sig000000f3/XORF_12340 ;
wire \i3/blk00000001/sig000000f3/CYINIT_12339 ;
wire \i3/blk00000001/sig000000f3/CY0F_12338 ;
wire \i3/blk00000001/sig00000098 ;
wire \i3/blk00000001/sig000000f3/XORG_12328 ;
wire \i3/blk00000001/sig00000097 ;
wire \i3/blk00000001/sig000000f3/CYSELF_12326 ;
wire \i3/blk00000001/sig000000f3/CYMUXFAST_12325 ;
wire \i3/blk00000001/sig000000f3/CYAND_12324 ;
wire \i3/blk00000001/sig000000f3/FASTCARRY_12323 ;
wire \i3/blk00000001/sig000000f3/CYMUXG2_12322 ;
wire \i3/blk00000001/sig000000f3/CYMUXF2_12321 ;
wire \i3/blk00000001/sig000000f3/CY0G_12320 ;
wire \i3/blk00000001/sig000000f3/CYSELG_12312 ;
wire \i3/blk00000001/sig00000096 ;
wire \i3/blk00000001/sig000000f5/XORF_12379 ;
wire \i3/blk00000001/sig000000f5/CYINIT_12378 ;
wire \i3/blk00000001/sig000000f5/CY0F_12377 ;
wire \i3/blk00000001/sig00000094 ;
wire \i3/blk00000001/sig000000f5/XORG_12367 ;
wire \i3/blk00000001/sig00000093 ;
wire \i3/blk00000001/sig000000f5/CYSELF_12365 ;
wire \i3/blk00000001/sig000000f5/CYMUXFAST_12364 ;
wire \i3/blk00000001/sig000000f5/CYAND_12363 ;
wire \i3/blk00000001/sig000000f5/FASTCARRY_12362 ;
wire \i3/blk00000001/sig000000f5/CYMUXG2_12361 ;
wire \i3/blk00000001/sig000000f5/CYMUXF2_12360 ;
wire \i3/blk00000001/sig000000f5/CY0G_12359 ;
wire \i3/blk00000001/sig000000f5/CYSELG_12351 ;
wire \i3/blk00000001/sig00000092 ;
wire \i3/blk00000001/sig000000f7/XORF_12410 ;
wire \i3/blk00000001/sig000000f7/CYINIT_12409 ;
wire \i3/blk00000001/sig000000f7/CY0F_12408 ;
wire \i3/blk00000001/sig000000f7/CYSELF_12400 ;
wire \i3/blk00000001/sig00000090 ;
wire \i3/blk00000001/sig000000f7/XORG_12397 ;
wire \i3/blk00000001/sig0000008f ;
wire \i3/blk00000001/sig0000008e ;
wire \i3/blk00000001/sig000000c0/CYINIT_12441 ;
wire \i3/blk00000001/sig000000c0/CY0F_12440 ;
wire \i3/blk00000001/sig000000c0/CYSELF_12432 ;
wire \i3/blk00000001/sig000000c3 ;
wire \i3/blk00000001/sig000000c0/BXINV_12430 ;
wire \i3/blk00000001/sig000000c0/CYMUXG_12429 ;
wire \i3/blk00000001/sig000000c2 ;
wire \i3/blk00000001/sig000000c0/CY0G_12427 ;
wire \i3/blk00000001/sig000000c0/CYSELG_12419 ;
wire \i3/blk00000001/sig000000c1 ;
wire \i3/blk00000001/sig000000f9/XORF_12479 ;
wire \i3/blk00000001/sig000000f9/CYINIT_12478 ;
wire \i3/blk00000001/sig000000f9/CY0F_12477 ;
wire \i3/blk00000001/sig000000bf ;
wire \i3/blk00000001/sig000000f9/XORG_12467 ;
wire \i3/blk00000001/sig000000be ;
wire \i3/blk00000001/sig000000f9/CYSELF_12465 ;
wire \i3/blk00000001/sig000000f9/CYMUXFAST_12464 ;
wire \i3/blk00000001/sig000000f9/CYAND_12463 ;
wire \i3/blk00000001/sig000000f9/FASTCARRY_12462 ;
wire \i3/blk00000001/sig000000f9/CYMUXG2_12461 ;
wire \i3/blk00000001/sig000000f9/CYMUXF2_12460 ;
wire \i3/blk00000001/sig000000f9/CY0G_12459 ;
wire \i3/blk00000001/sig000000f9/CYSELG_12451 ;
wire \i3/blk00000001/sig000000bd ;
wire \i3/blk00000001/sig000000fb/XORF_12518 ;
wire \i3/blk00000001/sig000000fb/CYINIT_12517 ;
wire \i3/blk00000001/sig000000fb/CY0F_12516 ;
wire \i3/blk00000001/sig000000bb ;
wire \i3/blk00000001/sig000000fb/XORG_12506 ;
wire \i3/blk00000001/sig000000ba ;
wire \i3/blk00000001/sig000000fb/CYSELF_12504 ;
wire \i3/blk00000001/sig000000fb/CYMUXFAST_12503 ;
wire \i3/blk00000001/sig000000fb/CYAND_12502 ;
wire \i3/blk00000001/sig000000fb/FASTCARRY_12501 ;
wire \i3/blk00000001/sig000000fb/CYMUXG2_12500 ;
wire \i3/blk00000001/sig000000fb/CYMUXF2_12499 ;
wire \i3/blk00000001/sig000000fb/CY0G_12498 ;
wire \i3/blk00000001/sig000000fb/CYSELG_12490 ;
wire \i3/blk00000001/sig000000b9 ;
wire \i3/blk00000001/sig000000fd/XORF_12557 ;
wire \i3/blk00000001/sig000000fd/CYINIT_12556 ;
wire \i3/blk00000001/sig000000fd/CY0F_12555 ;
wire \i3/blk00000001/sig000000b7 ;
wire \i3/blk00000001/sig000000fd/XORG_12545 ;
wire \i3/blk00000001/sig000000b6 ;
wire \i3/blk00000001/sig000000fd/CYSELF_12543 ;
wire \i3/blk00000001/sig000000fd/CYMUXFAST_12542 ;
wire \i3/blk00000001/sig000000fd/CYAND_12541 ;
wire \i3/blk00000001/sig000000fd/FASTCARRY_12540 ;
wire \i3/blk00000001/sig000000fd/CYMUXG2_12539 ;
wire \i3/blk00000001/sig000000fd/CYMUXF2_12538 ;
wire \i3/blk00000001/sig000000fd/CY0G_12537 ;
wire \i3/blk00000001/sig000000fd/CYSELG_12529 ;
wire \i3/blk00000001/sig000000b5 ;
wire \i3/blk00000001/sig000000ff/XORF_12596 ;
wire \i3/blk00000001/sig000000ff/CYINIT_12595 ;
wire \i3/blk00000001/sig000000ff/CY0F_12594 ;
wire \i3/blk00000001/sig000000b3 ;
wire \i3/blk00000001/sig000000ff/XORG_12584 ;
wire \i3/blk00000001/sig000000b2 ;
wire \i3/blk00000001/sig000000ff/CYSELF_12582 ;
wire \i3/blk00000001/sig000000ff/CYMUXFAST_12581 ;
wire \i3/blk00000001/sig000000ff/CYAND_12580 ;
wire \i3/blk00000001/sig000000ff/FASTCARRY_12579 ;
wire \i3/blk00000001/sig000000ff/CYMUXG2_12578 ;
wire \i3/blk00000001/sig000000ff/CYMUXF2_12577 ;
wire \i3/blk00000001/sig000000ff/CY0G_12576 ;
wire \i3/blk00000001/sig000000ff/CYSELG_12568 ;
wire \i3/blk00000001/sig000000b1 ;
wire \i3/blk00000001/sig00000101/XORF_12635 ;
wire \i3/blk00000001/sig00000101/CYINIT_12634 ;
wire \i3/blk00000001/sig00000101/CY0F_12633 ;
wire \i3/blk00000001/sig000000af ;
wire \i3/blk00000001/sig00000101/XORG_12623 ;
wire \i3/blk00000001/sig000000ae ;
wire \i3/blk00000001/sig00000101/CYSELF_12621 ;
wire \i3/blk00000001/sig00000101/CYMUXFAST_12620 ;
wire \i3/blk00000001/sig00000101/CYAND_12619 ;
wire \i3/blk00000001/sig00000101/FASTCARRY_12618 ;
wire \i3/blk00000001/sig00000101/CYMUXG2_12617 ;
wire \i3/blk00000001/sig00000101/CYMUXF2_12616 ;
wire \i3/blk00000001/sig00000101/CY0G_12615 ;
wire \i3/blk00000001/sig00000101/CYSELG_12607 ;
wire \i3/blk00000001/sig000000ad ;
wire \i3/blk00000001/sig00000103/XORF_12666 ;
wire \i3/blk00000001/sig00000103/CYINIT_12665 ;
wire \i3/blk00000001/sig00000103/CY0F_12664 ;
wire \i3/blk00000001/sig00000103/CYSELF_12656 ;
wire \i3/blk00000001/sig000000ab ;
wire \i3/blk00000001/sig00000103/XORG_12653 ;
wire \i3/blk00000001/sig000000aa ;
wire \i3/blk00000001/sig000000a9 ;
wire \y<0>/O ;
wire \y<1>/O ;
wire \y<2>/O ;
wire \y<3>/O ;
wire \y<4>/O ;
wire \y<5>/O ;
wire \y<6>/O ;
wire \y<7>/O ;
wire \y<8>/O ;
wire \y<9>/O ;
wire \x1<0>/INBUF ;
wire \x1<1>/INBUF ;
wire \x1<2>/INBUF ;
wire \x1<3>/INBUF ;
wire \x2<0>/INBUF ;
wire \x1<4>/INBUF ;
wire \x2<1>/INBUF ;
wire \x1<5>/INBUF ;
wire \x2<2>/INBUF ;
wire \x1<6>/INBUF ;
wire \x2<3>/INBUF ;
wire \x1<7>/INBUF ;
wire \x3<0>/INBUF ;
wire \x2<4>/INBUF ;
wire \x1<8>/INBUF ;
wire \x3<1>/INBUF ;
wire \x2<5>/INBUF ;
wire \x1<9>/INBUF ;
wire \x3<2>/INBUF ;
wire \x2<6>/INBUF ;
wire \x3<3>/INBUF ;
wire \x2<7>/INBUF ;
wire \x3<4>/INBUF ;
wire \x2<8>/INBUF ;
wire \x3<5>/INBUF ;
wire \x2<9>/INBUF ;
wire \x3<6>/INBUF ;
wire \x3<7>/INBUF ;
wire \x3<8>/INBUF ;
wire \x3<9>/INBUF ;
wire N10;
wire Madd_s2C;
wire Madd_s2C1_12961;
wire Madd_s2C2;
wire Madd_s2C3;
wire Madd_s2C4;
wire Madd_s2C5;
wire Madd_s2C6;
wire Madd_s2C7;
wire Madd_s2C8;
wire \NlwBufferSignal_i2/blk00000001/sig00000137/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000137/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000121/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000121/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001da/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001da/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000186/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000186/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000016f/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000016f/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000159/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000159/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000143/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000143/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000012d/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000012d/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000117/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001e3/FAND/IN0 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001e3/GAND/IN0 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000018f/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000018f/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000175/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000175/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000015f/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000015f/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000149/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000149/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000133/FAND/IN0 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000133/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000011d/FAND/IN0 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001dd/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001dd/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000189/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000189/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000171/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000171/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000015b/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000015b/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000145/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000145/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000012f/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000012f/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000119/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig000001e0/GAND/IN0 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000018c/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000018c/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000173/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000173/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000015d/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000015d/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000147/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000147/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000131/FAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig00000131/GAND/IN1 ;
wire \NlwBufferSignal_i2/blk00000001/sig0000011b/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000121/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000121/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig000001da/FAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig000001da/GAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000186/FAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000186/GAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000016f/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000016f/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000159/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000159/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000143/FAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000143/GAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000012d/FAND/IN0 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000012d/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000117/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig000001e3/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000018f/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000018f/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000175/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000175/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000015f/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000015f/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000149/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000149/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000133/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000133/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000011d/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000171/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000171/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000015b/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000015b/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000145/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000145/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000012f/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000012f/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000119/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000147/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000147/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000131/FAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig00000131/GAND/IN1 ;
wire \NlwBufferSignal_i1/blk00000001/sig0000011b/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000121/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000121/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001da/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001da/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000186/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000186/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000016f/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000016f/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000159/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000159/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000143/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000143/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000012d/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000012d/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000117/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001e3/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001e3/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000018f/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000018f/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000175/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000175/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000015f/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000015f/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000149/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000149/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000133/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000133/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000011d/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001dd/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001dd/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000189/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000189/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000171/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000171/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000015b/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000015b/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000145/FAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000145/GAND/IN0 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000012f/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000012f/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000119/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001e0/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig000001e0/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000018c/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000018c/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000173/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000173/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000015d/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000015d/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000147/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000147/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000131/FAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig00000131/GAND/IN1 ;
wire \NlwBufferSignal_i3/blk00000001/sig0000011b/FAND/IN1 ;
wire VCC;
wire \NLW_i2/blk00000001/sig00000185/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i2/blk00000001/sig00000185/CYMUXG_IA_UNCONNECTED ;
wire \NLW_i2/blk00000001/sig00000179/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i2/blk00000001/sig00000163/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i2/blk00000001/sig0000014d/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i1/blk00000001/sig00000185/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i1/blk00000001/sig00000185/CYMUXG_IA_UNCONNECTED ;
wire \NLW_i1/blk00000001/sig00000179/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i1/blk00000001/sig00000163/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i1/blk00000001/sig0000014d/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i1/blk00000001/sig00000137/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i3/blk00000001/sig00000185/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i3/blk00000001/sig00000185/CYMUXG_IA_UNCONNECTED ;
wire \NLW_i3/blk00000001/sig00000179/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i3/blk00000001/sig00000163/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i3/blk00000001/sig0000014d/CYMUXF_IA_UNCONNECTED ;
wire \NLW_i3/blk00000001/sig00000137/CYMUXF_IA_UNCONNECTED ;
wire GND;
wire [22 : 11] t2;
wire [22 : 11] t1;
wire [22 : 12] t3;
initial $sdf_annotate("netgen/par/lab3dpath_timesim.sdf");
X_MUX2 #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CYMUXF (
.IA(\i2/blk00000001/sig0000004e/CY0F_3677 ),
.IB(\i2/blk00000001/sig0000004e/CYINIT_3678 ),
.SEL(\i2/blk00000001/sig0000004e/CYSELF_3669 ),
.O(\i2/blk00000001/sig00000050 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CYINIT (
.I(\i2/blk00000001/sig0000004e/BXINV_3667 ),
.O(\i2/blk00000001/sig0000004e/CYINIT_3678 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CY0F (
.I(\i2/blk00000001/sig000000d2 ),
.O(\i2/blk00000001/sig0000004e/CY0F_3677 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CYSELF (
.I(\i2/blk00000001/sig00000051 ),
.O(\i2/blk00000001/sig0000004e/CYSELF_3669 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig0000004e/BXINV_3667 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/COUTUSED (
.I(\i2/blk00000001/sig0000004e/CYMUXG_3666 ),
.O(\i2/blk00000001/sig0000004e )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CYMUXG (
.IA(\i2/blk00000001/sig0000004e/CY0G_3664 ),
.IB(\i2/blk00000001/sig00000050 ),
.SEL(\i2/blk00000001/sig0000004e/CYSELG_3656 ),
.O(\i2/blk00000001/sig0000004e/CYMUXG_3666 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CY0G (
.I(\i2/blk00000001/sig000000d3 ),
.O(\i2/blk00000001/sig0000004e/CY0G_3664 )
);
X_BUF #(
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/sig0000004e/CYSELG (
.I(\i2/blk00000001/sig0000004f ),
.O(\i2/blk00000001/sig0000004e/CYSELG_3656 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYMUXF (
.IA(\t2<11>/CY0F_3713 ),
.IB(\t2<11>/CYINIT_3714 ),
.SEL(\t2<11>/CYSELF_3701 ),
.O(\i2/blk00000001/sig0000004c )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYMUXF2 (
.IA(\t2<11>/CY0F_3713 ),
.IB(\t2<11>/CY0F_3713 ),
.SEL(\t2<11>/CYSELF_3701 ),
.O(\t2<11>/CYMUXF2_3696 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYINIT (
.I(\i2/blk00000001/sig0000004e ),
.O(\t2<11>/CYINIT_3714 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CY0F (
.I(\i2/blk00000001/sig000000d4 ),
.O(\t2<11>/CY0F_3713 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYSELF (
.I(\i2/blk00000001/sig0000004d ),
.O(\t2<11>/CYSELF_3701 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/YUSED (
.I(\t2<11>/XORG_3703 ),
.O(t2[11])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/XORG (
.I0(\i2/blk00000001/sig0000004c ),
.I1(\i2/blk00000001/sig0000004b ),
.O(\t2<11>/XORG_3703 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/COUTUSED (
.I(\t2<11>/CYMUXFAST_3700 ),
.O(\i2/blk00000001/sig0000004a )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/FASTCARRY (
.I(\i2/blk00000001/sig0000004e ),
.O(\t2<11>/FASTCARRY_3698 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYAND (
.I0(\t2<11>/CYSELG_3687 ),
.I1(\t2<11>/CYSELF_3701 ),
.O(\t2<11>/CYAND_3699 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYMUXFAST (
.IA(\t2<11>/CYMUXG2_3697 ),
.IB(\t2<11>/FASTCARRY_3698 ),
.SEL(\t2<11>/CYAND_3699 ),
.O(\t2<11>/CYMUXFAST_3700 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYMUXG2 (
.IA(\t2<11>/CY0G_3695 ),
.IB(\t2<11>/CYMUXF2_3696 ),
.SEL(\t2<11>/CYSELG_3687 ),
.O(\t2<11>/CYMUXG2_3697 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CY0G (
.I(\i2/blk00000001/sig000000d5 ),
.O(\t2<11>/CY0G_3695 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\t2<11>/CYSELG (
.I(\i2/blk00000001/sig0000004b ),
.O(\t2<11>/CYSELG_3687 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/XUSED (
.I(\t2<12>/XORF_3752 ),
.O(t2[12])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/XORF (
.I0(\t2<12>/CYINIT_3751 ),
.I1(\i2/blk00000001/sig00000049 ),
.O(\t2<12>/XORF_3752 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYMUXF (
.IA(\t2<12>/CY0F_3750 ),
.IB(\t2<12>/CYINIT_3751 ),
.SEL(\t2<12>/CYSELF_3738 ),
.O(\i2/blk00000001/sig00000048 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYMUXF2 (
.IA(\t2<12>/CY0F_3750 ),
.IB(\t2<12>/CY0F_3750 ),
.SEL(\t2<12>/CYSELF_3738 ),
.O(\t2<12>/CYMUXF2_3733 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYINIT (
.I(\i2/blk00000001/sig0000004a ),
.O(\t2<12>/CYINIT_3751 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CY0F (
.I(\i2/blk00000001/sig000000d6 ),
.O(\t2<12>/CY0F_3750 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYSELF (
.I(\i2/blk00000001/sig00000049 ),
.O(\t2<12>/CYSELF_3738 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/YUSED (
.I(\t2<12>/XORG_3740 ),
.O(t2[13])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/XORG (
.I0(\i2/blk00000001/sig00000048 ),
.I1(\i2/blk00000001/sig00000047 ),
.O(\t2<12>/XORG_3740 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/COUTUSED (
.I(\t2<12>/CYMUXFAST_3737 ),
.O(\i2/blk00000001/sig00000046 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/FASTCARRY (
.I(\i2/blk00000001/sig0000004a ),
.O(\t2<12>/FASTCARRY_3735 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYAND (
.I0(\t2<12>/CYSELG_3724 ),
.I1(\t2<12>/CYSELF_3738 ),
.O(\t2<12>/CYAND_3736 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYMUXFAST (
.IA(\t2<12>/CYMUXG2_3734 ),
.IB(\t2<12>/FASTCARRY_3735 ),
.SEL(\t2<12>/CYAND_3736 ),
.O(\t2<12>/CYMUXFAST_3737 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYMUXG2 (
.IA(\t2<12>/CY0G_3732 ),
.IB(\t2<12>/CYMUXF2_3733 ),
.SEL(\t2<12>/CYSELG_3724 ),
.O(\t2<12>/CYMUXG2_3734 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CY0G (
.I(\i2/blk00000001/sig000000d7 ),
.O(\t2<12>/CY0G_3732 )
);
X_BUF #(
.LOC ( "SLICE_X23Y30" ))
\t2<12>/CYSELG (
.I(\i2/blk00000001/sig00000047 ),
.O(\t2<12>/CYSELG_3724 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/XUSED (
.I(\t2<14>/XORF_3791 ),
.O(t2[14])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/XORF (
.I0(\t2<14>/CYINIT_3790 ),
.I1(\i2/blk00000001/sig00000045 ),
.O(\t2<14>/XORF_3791 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYMUXF (
.IA(\t2<14>/CY0F_3789 ),
.IB(\t2<14>/CYINIT_3790 ),
.SEL(\t2<14>/CYSELF_3777 ),
.O(\i2/blk00000001/sig00000044 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYMUXF2 (
.IA(\t2<14>/CY0F_3789 ),
.IB(\t2<14>/CY0F_3789 ),
.SEL(\t2<14>/CYSELF_3777 ),
.O(\t2<14>/CYMUXF2_3772 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYINIT (
.I(\i2/blk00000001/sig00000046 ),
.O(\t2<14>/CYINIT_3790 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CY0F (
.I(\i2/blk00000001/sig000000d8 ),
.O(\t2<14>/CY0F_3789 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYSELF (
.I(\i2/blk00000001/sig00000045 ),
.O(\t2<14>/CYSELF_3777 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/YUSED (
.I(\t2<14>/XORG_3779 ),
.O(t2[15])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/XORG (
.I0(\i2/blk00000001/sig00000044 ),
.I1(\i2/blk00000001/sig00000043 ),
.O(\t2<14>/XORG_3779 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/COUTUSED (
.I(\t2<14>/CYMUXFAST_3776 ),
.O(\i2/blk00000001/sig00000042 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/FASTCARRY (
.I(\i2/blk00000001/sig00000046 ),
.O(\t2<14>/FASTCARRY_3774 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYAND (
.I0(\t2<14>/CYSELG_3763 ),
.I1(\t2<14>/CYSELF_3777 ),
.O(\t2<14>/CYAND_3775 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYMUXFAST (
.IA(\t2<14>/CYMUXG2_3773 ),
.IB(\t2<14>/FASTCARRY_3774 ),
.SEL(\t2<14>/CYAND_3775 ),
.O(\t2<14>/CYMUXFAST_3776 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYMUXG2 (
.IA(\t2<14>/CY0G_3771 ),
.IB(\t2<14>/CYMUXF2_3772 ),
.SEL(\t2<14>/CYSELG_3763 ),
.O(\t2<14>/CYMUXG2_3773 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CY0G (
.I(\i2/blk00000001/sig000000d9 ),
.O(\t2<14>/CY0G_3771 )
);
X_BUF #(
.LOC ( "SLICE_X23Y31" ))
\t2<14>/CYSELG (
.I(\i2/blk00000001/sig00000043 ),
.O(\t2<14>/CYSELG_3763 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y31" ))
\i2/blk00000001/blk0000010d (
.ADR0(\i2/blk00000001/sig000000c9 ),
.ADR1(\i2/blk00000001/sig000000d9 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000043 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y32" ))
\i2/blk00000001/blk0000010a (
.ADR0(\i2/blk00000001/sig000000ca ),
.ADR1(\i2/blk00000001/sig000000da ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000041 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/XUSED (
.I(\t2<16>/XORF_3830 ),
.O(t2[16])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/XORF (
.I0(\t2<16>/CYINIT_3829 ),
.I1(\i2/blk00000001/sig00000041 ),
.O(\t2<16>/XORF_3830 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYMUXF (
.IA(\t2<16>/CY0F_3828 ),
.IB(\t2<16>/CYINIT_3829 ),
.SEL(\t2<16>/CYSELF_3816 ),
.O(\i2/blk00000001/sig00000040 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYMUXF2 (
.IA(\t2<16>/CY0F_3828 ),
.IB(\t2<16>/CY0F_3828 ),
.SEL(\t2<16>/CYSELF_3816 ),
.O(\t2<16>/CYMUXF2_3811 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYINIT (
.I(\i2/blk00000001/sig00000042 ),
.O(\t2<16>/CYINIT_3829 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CY0F (
.I(\i2/blk00000001/sig000000da ),
.O(\t2<16>/CY0F_3828 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYSELF (
.I(\i2/blk00000001/sig00000041 ),
.O(\t2<16>/CYSELF_3816 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/YUSED (
.I(\t2<16>/XORG_3818 ),
.O(t2[17])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/XORG (
.I0(\i2/blk00000001/sig00000040 ),
.I1(\i2/blk00000001/sig0000003f ),
.O(\t2<16>/XORG_3818 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/COUTUSED (
.I(\t2<16>/CYMUXFAST_3815 ),
.O(\i2/blk00000001/sig0000003e )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/FASTCARRY (
.I(\i2/blk00000001/sig00000042 ),
.O(\t2<16>/FASTCARRY_3813 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYAND (
.I0(\t2<16>/CYSELG_3802 ),
.I1(\t2<16>/CYSELF_3816 ),
.O(\t2<16>/CYAND_3814 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYMUXFAST (
.IA(\t2<16>/CYMUXG2_3812 ),
.IB(\t2<16>/FASTCARRY_3813 ),
.SEL(\t2<16>/CYAND_3814 ),
.O(\t2<16>/CYMUXFAST_3815 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYMUXG2 (
.IA(\t2<16>/CY0G_3810 ),
.IB(\t2<16>/CYMUXF2_3811 ),
.SEL(\t2<16>/CYSELG_3802 ),
.O(\t2<16>/CYMUXG2_3812 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CY0G (
.I(\i2/blk00000001/sig000000db ),
.O(\t2<16>/CY0G_3810 )
);
X_BUF #(
.LOC ( "SLICE_X23Y32" ))
\t2<16>/CYSELG (
.I(\i2/blk00000001/sig0000003f ),
.O(\t2<16>/CYSELG_3802 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/XUSED (
.I(\t2<18>/XORF_3869 ),
.O(t2[18])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/XORF (
.I0(\t2<18>/CYINIT_3868 ),
.I1(\i2/blk00000001/sig0000003d ),
.O(\t2<18>/XORF_3869 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYMUXF (
.IA(\t2<18>/CY0F_3867 ),
.IB(\t2<18>/CYINIT_3868 ),
.SEL(\t2<18>/CYSELF_3855 ),
.O(\i2/blk00000001/sig0000003c )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYMUXF2 (
.IA(\t2<18>/CY0F_3867 ),
.IB(\t2<18>/CY0F_3867 ),
.SEL(\t2<18>/CYSELF_3855 ),
.O(\t2<18>/CYMUXF2_3850 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYINIT (
.I(\i2/blk00000001/sig0000003e ),
.O(\t2<18>/CYINIT_3868 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CY0F (
.I(\i2/blk00000001/sig000000dc ),
.O(\t2<18>/CY0F_3867 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYSELF (
.I(\i2/blk00000001/sig0000003d ),
.O(\t2<18>/CYSELF_3855 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/YUSED (
.I(\t2<18>/XORG_3857 ),
.O(t2[19])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/XORG (
.I0(\i2/blk00000001/sig0000003c ),
.I1(\i2/blk00000001/sig0000003b ),
.O(\t2<18>/XORG_3857 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/COUTUSED (
.I(\t2<18>/CYMUXFAST_3854 ),
.O(\i2/blk00000001/sig0000003a )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/FASTCARRY (
.I(\i2/blk00000001/sig0000003e ),
.O(\t2<18>/FASTCARRY_3852 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYAND (
.I0(\t2<18>/CYSELG_3841 ),
.I1(\t2<18>/CYSELF_3855 ),
.O(\t2<18>/CYAND_3853 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYMUXFAST (
.IA(\t2<18>/CYMUXG2_3851 ),
.IB(\t2<18>/FASTCARRY_3852 ),
.SEL(\t2<18>/CYAND_3853 ),
.O(\t2<18>/CYMUXFAST_3854 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYMUXG2 (
.IA(\t2<18>/CY0G_3849 ),
.IB(\t2<18>/CYMUXF2_3850 ),
.SEL(\t2<18>/CYSELG_3841 ),
.O(\t2<18>/CYMUXG2_3851 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CY0G (
.I(\i2/blk00000001/sig000000dd ),
.O(\t2<18>/CY0G_3849 )
);
X_BUF #(
.LOC ( "SLICE_X23Y33" ))
\t2<18>/CYSELG (
.I(\i2/blk00000001/sig0000003b ),
.O(\t2<18>/CYSELG_3841 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/XUSED (
.I(\t2<20>/XORF_3908 ),
.O(t2[20])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/XORF (
.I0(\t2<20>/CYINIT_3907 ),
.I1(\i2/blk00000001/sig00000039 ),
.O(\t2<20>/XORF_3908 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYMUXF (
.IA(\t2<20>/CY0F_3906 ),
.IB(\t2<20>/CYINIT_3907 ),
.SEL(\t2<20>/CYSELF_3894 ),
.O(\i2/blk00000001/sig00000038 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYMUXF2 (
.IA(\t2<20>/CY0F_3906 ),
.IB(\t2<20>/CY0F_3906 ),
.SEL(\t2<20>/CYSELF_3894 ),
.O(\t2<20>/CYMUXF2_3889 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYINIT (
.I(\i2/blk00000001/sig0000003a ),
.O(\t2<20>/CYINIT_3907 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CY0F (
.I(\i2/blk00000001/sig000000de ),
.O(\t2<20>/CY0F_3906 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYSELF (
.I(\i2/blk00000001/sig00000039 ),
.O(\t2<20>/CYSELF_3894 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/YUSED (
.I(\t2<20>/XORG_3896 ),
.O(t2[21])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/XORG (
.I0(\i2/blk00000001/sig00000038 ),
.I1(\i2/blk00000001/sig00000037 ),
.O(\t2<20>/XORG_3896 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/FASTCARRY (
.I(\i2/blk00000001/sig0000003a ),
.O(\t2<20>/FASTCARRY_3891 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYAND (
.I0(\t2<20>/CYSELG_3880 ),
.I1(\t2<20>/CYSELF_3894 ),
.O(\t2<20>/CYAND_3892 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYMUXFAST (
.IA(\t2<20>/CYMUXG2_3890 ),
.IB(\t2<20>/FASTCARRY_3891 ),
.SEL(\t2<20>/CYAND_3892 ),
.O(\t2<20>/CYMUXFAST_3893 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYMUXG2 (
.IA(\t2<20>/CY0G_3888 ),
.IB(\t2<20>/CYMUXF2_3889 ),
.SEL(\t2<20>/CYSELG_3880 ),
.O(\t2<20>/CYMUXG2_3890 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CY0G (
.I(\i2/blk00000001/sig000000de ),
.O(\t2<20>/CY0G_3888 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\t2<20>/CYSELG (
.I(\i2/blk00000001/sig00000037 ),
.O(\t2<20>/CYSELG_3880 )
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\t2<22>/XUSED (
.I(\t2<22>/XORF_3923 ),
.O(t2[22])
);
X_XOR2 #(
.LOC ( "SLICE_X23Y35" ))
\t2<22>/XORF (
.I0(\t2<22>/CYINIT_3922 ),
.I1(\i2/blk00000001/sig00000035 ),
.O(\t2<22>/XORF_3923 )
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\t2<22>/CYINIT (
.I(\t2<20>/CYMUXFAST_3893 ),
.O(\t2<22>/CYINIT_3922 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X23Y35" ))
\i2/blk00000001/blk000000f8 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000de ),
.ADR2(\i2/blk00000001/sig000000d0 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000035 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CYMUXF (
.IA(\i2/blk00000001/sig0000006f/CY0F_3953 ),
.IB(\i2/blk00000001/sig0000006f/CYINIT_3954 ),
.SEL(\i2/blk00000001/sig0000006f/CYSELF_3945 ),
.O(\i2/blk00000001/sig00000071 )
);
X_BUF #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CYINIT (
.I(\i2/blk00000001/sig0000006f/BXINV_3943 ),
.O(\i2/blk00000001/sig0000006f/CYINIT_3954 )
);
X_BUF #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CY0F (
.I(\i2/blk00000001/sig000000f9 ),
.O(\i2/blk00000001/sig0000006f/CY0F_3953 )
);
X_BUF #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CYSELF (
.I(\i2/blk00000001/sig00000072 ),
.O(\i2/blk00000001/sig0000006f/CYSELF_3945 )
);
X_BUF #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig0000006f/BXINV_3943 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CYMUXG (
.IA(\i2/blk00000001/sig0000006f/CY0G_3940 ),
.IB(\i2/blk00000001/sig00000071 ),
.SEL(\i2/blk00000001/sig0000006f/CYSELG_3932 ),
.O(\i2/blk00000001/sig0000006f/CYMUXG_3942 )
);
X_BUF #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CY0G (
.I(\i2/blk00000001/sig000000fa ),
.O(\i2/blk00000001/sig0000006f/CY0G_3940 )
);
X_BUF #(
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/sig0000006f/CYSELG (
.I(\i2/blk00000001/sig00000070 ),
.O(\i2/blk00000001/sig0000006f/CYSELG_3932 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CYMUXF2 (
.IA(\i2/blk00000001/sig0000006b/CY0F_3985 ),
.IB(\i2/blk00000001/sig0000006b/CY0F_3985 ),
.SEL(\i2/blk00000001/sig0000006b/CYSELF_3976 ),
.O(\i2/blk00000001/sig0000006b/CYMUXF2_3971 )
);
X_BUF #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CY0F (
.I(\i2/blk00000001/sig000000fb ),
.O(\i2/blk00000001/sig0000006b/CY0F_3985 )
);
X_BUF #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CYSELF (
.I(\i2/blk00000001/sig0000006e ),
.O(\i2/blk00000001/sig0000006b/CYSELF_3976 )
);
X_BUF #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/COUTUSED (
.I(\i2/blk00000001/sig0000006b/CYMUXFAST_3975 ),
.O(\i2/blk00000001/sig0000006b )
);
X_BUF #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/FASTCARRY (
.I(\i2/blk00000001/sig0000006f/CYMUXG_3942 ),
.O(\i2/blk00000001/sig0000006b/FASTCARRY_3973 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CYAND (
.I0(\i2/blk00000001/sig0000006b/CYSELG_3962 ),
.I1(\i2/blk00000001/sig0000006b/CYSELF_3976 ),
.O(\i2/blk00000001/sig0000006b/CYAND_3974 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CYMUXFAST (
.IA(\i2/blk00000001/sig0000006b/CYMUXG2_3972 ),
.IB(\i2/blk00000001/sig0000006b/FASTCARRY_3973 ),
.SEL(\i2/blk00000001/sig0000006b/CYAND_3974 ),
.O(\i2/blk00000001/sig0000006b/CYMUXFAST_3975 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CYMUXG2 (
.IA(\i2/blk00000001/sig0000006b/CY0G_3970 ),
.IB(\i2/blk00000001/sig0000006b/CYMUXF2_3971 ),
.SEL(\i2/blk00000001/sig0000006b/CYSELG_3962 ),
.O(\i2/blk00000001/sig0000006b/CYMUXG2_3972 )
);
X_BUF #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CY0G (
.I(\i2/blk00000001/sig000000fc ),
.O(\i2/blk00000001/sig0000006b/CY0G_3970 )
);
X_BUF #(
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/sig0000006b/CYSELG (
.I(\i2/blk00000001/sig0000006c ),
.O(\i2/blk00000001/sig0000006b/CYSELG_3962 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/blk0000014e (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000fb ),
.ADR2(\i2/blk00000001/sig000000eb ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000006e )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/XUSED (
.I(\i2/blk00000001/sig000000d2/XORF_4023 ),
.O(\i2/blk00000001/sig000000d2 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/XORF (
.I0(\i2/blk00000001/sig000000d2/CYINIT_4022 ),
.I1(\i2/blk00000001/sig0000006a ),
.O(\i2/blk00000001/sig000000d2/XORF_4023 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYMUXF (
.IA(\i2/blk00000001/sig000000d2/CY0F_4021 ),
.IB(\i2/blk00000001/sig000000d2/CYINIT_4022 ),
.SEL(\i2/blk00000001/sig000000d2/CYSELF_4009 ),
.O(\i2/blk00000001/sig00000069 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYMUXF2 (
.IA(\i2/blk00000001/sig000000d2/CY0F_4021 ),
.IB(\i2/blk00000001/sig000000d2/CY0F_4021 ),
.SEL(\i2/blk00000001/sig000000d2/CYSELF_4009 ),
.O(\i2/blk00000001/sig000000d2/CYMUXF2_4004 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYINIT (
.I(\i2/blk00000001/sig0000006b ),
.O(\i2/blk00000001/sig000000d2/CYINIT_4022 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CY0F (
.I(\i2/blk00000001/sig000000fd ),
.O(\i2/blk00000001/sig000000d2/CY0F_4021 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYSELF (
.I(\i2/blk00000001/sig0000006a ),
.O(\i2/blk00000001/sig000000d2/CYSELF_4009 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/YUSED (
.I(\i2/blk00000001/sig000000d2/XORG_4011 ),
.O(\i2/blk00000001/sig000000d3 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/XORG (
.I0(\i2/blk00000001/sig00000069 ),
.I1(\i2/blk00000001/sig00000068 ),
.O(\i2/blk00000001/sig000000d2/XORG_4011 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/COUTUSED (
.I(\i2/blk00000001/sig000000d2/CYMUXFAST_4008 ),
.O(\i2/blk00000001/sig00000067 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/FASTCARRY (
.I(\i2/blk00000001/sig0000006b ),
.O(\i2/blk00000001/sig000000d2/FASTCARRY_4006 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYAND (
.I0(\i2/blk00000001/sig000000d2/CYSELG_3995 ),
.I1(\i2/blk00000001/sig000000d2/CYSELF_4009 ),
.O(\i2/blk00000001/sig000000d2/CYAND_4007 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYMUXFAST (
.IA(\i2/blk00000001/sig000000d2/CYMUXG2_4005 ),
.IB(\i2/blk00000001/sig000000d2/FASTCARRY_4006 ),
.SEL(\i2/blk00000001/sig000000d2/CYAND_4007 ),
.O(\i2/blk00000001/sig000000d2/CYMUXFAST_4008 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYMUXG2 (
.IA(\i2/blk00000001/sig000000d2/CY0G_4003 ),
.IB(\i2/blk00000001/sig000000d2/CYMUXF2_4004 ),
.SEL(\i2/blk00000001/sig000000d2/CYSELG_3995 ),
.O(\i2/blk00000001/sig000000d2/CYMUXG2_4005 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CY0G (
.I(\i2/blk00000001/sig000000fe ),
.O(\i2/blk00000001/sig000000d2/CY0G_4003 )
);
X_BUF #(
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/sig000000d2/CYSELG (
.I(\i2/blk00000001/sig00000068 ),
.O(\i2/blk00000001/sig000000d2/CYSELG_3995 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/XUSED (
.I(\i2/blk00000001/sig000000d4/XORF_4062 ),
.O(\i2/blk00000001/sig000000d4 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/XORF (
.I0(\i2/blk00000001/sig000000d4/CYINIT_4061 ),
.I1(\i2/blk00000001/sig00000066 ),
.O(\i2/blk00000001/sig000000d4/XORF_4062 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYMUXF (
.IA(\i2/blk00000001/sig000000d4/CY0F_4060 ),
.IB(\i2/blk00000001/sig000000d4/CYINIT_4061 ),
.SEL(\i2/blk00000001/sig000000d4/CYSELF_4048 ),
.O(\i2/blk00000001/sig00000065 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYMUXF2 (
.IA(\i2/blk00000001/sig000000d4/CY0F_4060 ),
.IB(\i2/blk00000001/sig000000d4/CY0F_4060 ),
.SEL(\i2/blk00000001/sig000000d4/CYSELF_4048 ),
.O(\i2/blk00000001/sig000000d4/CYMUXF2_4043 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYINIT (
.I(\i2/blk00000001/sig00000067 ),
.O(\i2/blk00000001/sig000000d4/CYINIT_4061 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CY0F (
.I(\i2/blk00000001/sig000000ff ),
.O(\i2/blk00000001/sig000000d4/CY0F_4060 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYSELF (
.I(\i2/blk00000001/sig00000066 ),
.O(\i2/blk00000001/sig000000d4/CYSELF_4048 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/YUSED (
.I(\i2/blk00000001/sig000000d4/XORG_4050 ),
.O(\i2/blk00000001/sig000000d5 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/XORG (
.I0(\i2/blk00000001/sig00000065 ),
.I1(\i2/blk00000001/sig00000064 ),
.O(\i2/blk00000001/sig000000d4/XORG_4050 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/COUTUSED (
.I(\i2/blk00000001/sig000000d4/CYMUXFAST_4047 ),
.O(\i2/blk00000001/sig00000063 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/FASTCARRY (
.I(\i2/blk00000001/sig00000067 ),
.O(\i2/blk00000001/sig000000d4/FASTCARRY_4045 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYAND (
.I0(\i2/blk00000001/sig000000d4/CYSELG_4034 ),
.I1(\i2/blk00000001/sig000000d4/CYSELF_4048 ),
.O(\i2/blk00000001/sig000000d4/CYAND_4046 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYMUXFAST (
.IA(\i2/blk00000001/sig000000d4/CYMUXG2_4044 ),
.IB(\i2/blk00000001/sig000000d4/FASTCARRY_4045 ),
.SEL(\i2/blk00000001/sig000000d4/CYAND_4046 ),
.O(\i2/blk00000001/sig000000d4/CYMUXFAST_4047 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYMUXG2 (
.IA(\i2/blk00000001/sig000000d4/CY0G_4042 ),
.IB(\i2/blk00000001/sig000000d4/CYMUXF2_4043 ),
.SEL(\i2/blk00000001/sig000000d4/CYSELG_4034 ),
.O(\i2/blk00000001/sig000000d4/CYMUXG2_4044 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CY0G (
.I(\i2/blk00000001/sig00000100 ),
.O(\i2/blk00000001/sig000000d4/CY0G_4042 )
);
X_BUF #(
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/sig000000d4/CYSELG (
.I(\i2/blk00000001/sig00000064 ),
.O(\i2/blk00000001/sig000000d4/CYSELG_4034 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/blk0000013f (
.ADR0(\i2/blk00000001/sig000000f0 ),
.ADR1(\i2/blk00000001/sig00000100 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000064 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/XUSED (
.I(\i2/blk00000001/sig000000d6/XORF_4101 ),
.O(\i2/blk00000001/sig000000d6 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/XORF (
.I0(\i2/blk00000001/sig000000d6/CYINIT_4100 ),
.I1(\i2/blk00000001/sig00000062 ),
.O(\i2/blk00000001/sig000000d6/XORF_4101 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYMUXF (
.IA(\i2/blk00000001/sig000000d6/CY0F_4099 ),
.IB(\i2/blk00000001/sig000000d6/CYINIT_4100 ),
.SEL(\i2/blk00000001/sig000000d6/CYSELF_4087 ),
.O(\i2/blk00000001/sig00000061 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYMUXF2 (
.IA(\i2/blk00000001/sig000000d6/CY0F_4099 ),
.IB(\i2/blk00000001/sig000000d6/CY0F_4099 ),
.SEL(\i2/blk00000001/sig000000d6/CYSELF_4087 ),
.O(\i2/blk00000001/sig000000d6/CYMUXF2_4082 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYINIT (
.I(\i2/blk00000001/sig00000063 ),
.O(\i2/blk00000001/sig000000d6/CYINIT_4100 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CY0F (
.I(\i2/blk00000001/sig00000101 ),
.O(\i2/blk00000001/sig000000d6/CY0F_4099 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYSELF (
.I(\i2/blk00000001/sig00000062 ),
.O(\i2/blk00000001/sig000000d6/CYSELF_4087 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/YUSED (
.I(\i2/blk00000001/sig000000d6/XORG_4089 ),
.O(\i2/blk00000001/sig000000d7 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/XORG (
.I0(\i2/blk00000001/sig00000061 ),
.I1(\i2/blk00000001/sig00000060 ),
.O(\i2/blk00000001/sig000000d6/XORG_4089 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/COUTUSED (
.I(\i2/blk00000001/sig000000d6/CYMUXFAST_4086 ),
.O(\i2/blk00000001/sig0000005f )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/FASTCARRY (
.I(\i2/blk00000001/sig00000063 ),
.O(\i2/blk00000001/sig000000d6/FASTCARRY_4084 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYAND (
.I0(\i2/blk00000001/sig000000d6/CYSELG_4073 ),
.I1(\i2/blk00000001/sig000000d6/CYSELF_4087 ),
.O(\i2/blk00000001/sig000000d6/CYAND_4085 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYMUXFAST (
.IA(\i2/blk00000001/sig000000d6/CYMUXG2_4083 ),
.IB(\i2/blk00000001/sig000000d6/FASTCARRY_4084 ),
.SEL(\i2/blk00000001/sig000000d6/CYAND_4085 ),
.O(\i2/blk00000001/sig000000d6/CYMUXFAST_4086 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYMUXG2 (
.IA(\i2/blk00000001/sig000000d6/CY0G_4081 ),
.IB(\i2/blk00000001/sig000000d6/CYMUXF2_4082 ),
.SEL(\i2/blk00000001/sig000000d6/CYSELG_4073 ),
.O(\i2/blk00000001/sig000000d6/CYMUXG2_4083 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CY0G (
.I(\i2/blk00000001/sig00000102 ),
.O(\i2/blk00000001/sig000000d6/CY0G_4081 )
);
X_BUF #(
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/sig000000d6/CYSELG (
.I(\i2/blk00000001/sig00000060 ),
.O(\i2/blk00000001/sig000000d6/CYSELG_4073 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/XUSED (
.I(\i2/blk00000001/sig000000d8/XORF_4140 ),
.O(\i2/blk00000001/sig000000d8 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/XORF (
.I0(\i2/blk00000001/sig000000d8/CYINIT_4139 ),
.I1(\i2/blk00000001/sig0000005e ),
.O(\i2/blk00000001/sig000000d8/XORF_4140 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYMUXF (
.IA(\i2/blk00000001/sig000000d8/CY0F_4138 ),
.IB(\i2/blk00000001/sig000000d8/CYINIT_4139 ),
.SEL(\i2/blk00000001/sig000000d8/CYSELF_4126 ),
.O(\i2/blk00000001/sig0000005d )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYMUXF2 (
.IA(\i2/blk00000001/sig000000d8/CY0F_4138 ),
.IB(\i2/blk00000001/sig000000d8/CY0F_4138 ),
.SEL(\i2/blk00000001/sig000000d8/CYSELF_4126 ),
.O(\i2/blk00000001/sig000000d8/CYMUXF2_4121 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYINIT (
.I(\i2/blk00000001/sig0000005f ),
.O(\i2/blk00000001/sig000000d8/CYINIT_4139 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CY0F (
.I(\i2/blk00000001/sig00000103 ),
.O(\i2/blk00000001/sig000000d8/CY0F_4138 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYSELF (
.I(\i2/blk00000001/sig0000005e ),
.O(\i2/blk00000001/sig000000d8/CYSELF_4126 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/YUSED (
.I(\i2/blk00000001/sig000000d8/XORG_4128 ),
.O(\i2/blk00000001/sig000000d9 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/XORG (
.I0(\i2/blk00000001/sig0000005d ),
.I1(\i2/blk00000001/sig0000005c ),
.O(\i2/blk00000001/sig000000d8/XORG_4128 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/COUTUSED (
.I(\i2/blk00000001/sig000000d8/CYMUXFAST_4125 ),
.O(\i2/blk00000001/sig0000005b )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/FASTCARRY (
.I(\i2/blk00000001/sig0000005f ),
.O(\i2/blk00000001/sig000000d8/FASTCARRY_4123 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYAND (
.I0(\i2/blk00000001/sig000000d8/CYSELG_4112 ),
.I1(\i2/blk00000001/sig000000d8/CYSELF_4126 ),
.O(\i2/blk00000001/sig000000d8/CYAND_4124 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYMUXFAST (
.IA(\i2/blk00000001/sig000000d8/CYMUXG2_4122 ),
.IB(\i2/blk00000001/sig000000d8/FASTCARRY_4123 ),
.SEL(\i2/blk00000001/sig000000d8/CYAND_4124 ),
.O(\i2/blk00000001/sig000000d8/CYMUXFAST_4125 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYMUXG2 (
.IA(\i2/blk00000001/sig000000d8/CY0G_4120 ),
.IB(\i2/blk00000001/sig000000d8/CYMUXF2_4121 ),
.SEL(\i2/blk00000001/sig000000d8/CYSELG_4112 ),
.O(\i2/blk00000001/sig000000d8/CYMUXG2_4122 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CY0G (
.I(\i2/blk00000001/sig00000104 ),
.O(\i2/blk00000001/sig000000d8/CY0G_4120 )
);
X_BUF #(
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/sig000000d8/CYSELG (
.I(\i2/blk00000001/sig0000005c ),
.O(\i2/blk00000001/sig000000d8/CYSELG_4112 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/XUSED (
.I(\i2/blk00000001/sig000000da/XORF_4179 ),
.O(\i2/blk00000001/sig000000da )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/XORF (
.I0(\i2/blk00000001/sig000000da/CYINIT_4178 ),
.I1(\i2/blk00000001/sig0000005a ),
.O(\i2/blk00000001/sig000000da/XORF_4179 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYMUXF (
.IA(\i2/blk00000001/sig000000da/CY0F_4177 ),
.IB(\i2/blk00000001/sig000000da/CYINIT_4178 ),
.SEL(\i2/blk00000001/sig000000da/CYSELF_4165 ),
.O(\i2/blk00000001/sig00000059 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYMUXF2 (
.IA(\i2/blk00000001/sig000000da/CY0F_4177 ),
.IB(\i2/blk00000001/sig000000da/CY0F_4177 ),
.SEL(\i2/blk00000001/sig000000da/CYSELF_4165 ),
.O(\i2/blk00000001/sig000000da/CYMUXF2_4160 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYINIT (
.I(\i2/blk00000001/sig0000005b ),
.O(\i2/blk00000001/sig000000da/CYINIT_4178 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CY0F (
.I(\i2/blk00000001/sig00000104 ),
.O(\i2/blk00000001/sig000000da/CY0F_4177 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYSELF (
.I(\i2/blk00000001/sig0000005a ),
.O(\i2/blk00000001/sig000000da/CYSELF_4165 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/YUSED (
.I(\i2/blk00000001/sig000000da/XORG_4167 ),
.O(\i2/blk00000001/sig000000db )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/XORG (
.I0(\i2/blk00000001/sig00000059 ),
.I1(\i2/blk00000001/sig00000058 ),
.O(\i2/blk00000001/sig000000da/XORG_4167 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/COUTUSED (
.I(\i2/blk00000001/sig000000da/CYMUXFAST_4164 ),
.O(\i2/blk00000001/sig00000057 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/FASTCARRY (
.I(\i2/blk00000001/sig0000005b ),
.O(\i2/blk00000001/sig000000da/FASTCARRY_4162 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYAND (
.I0(\i2/blk00000001/sig000000da/CYSELG_4151 ),
.I1(\i2/blk00000001/sig000000da/CYSELF_4165 ),
.O(\i2/blk00000001/sig000000da/CYAND_4163 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYMUXFAST (
.IA(\i2/blk00000001/sig000000da/CYMUXG2_4161 ),
.IB(\i2/blk00000001/sig000000da/FASTCARRY_4162 ),
.SEL(\i2/blk00000001/sig000000da/CYAND_4163 ),
.O(\i2/blk00000001/sig000000da/CYMUXFAST_4164 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYMUXG2 (
.IA(\i2/blk00000001/sig000000da/CY0G_4159 ),
.IB(\i2/blk00000001/sig000000da/CYMUXF2_4160 ),
.SEL(\i2/blk00000001/sig000000da/CYSELG_4151 ),
.O(\i2/blk00000001/sig000000da/CYMUXG2_4161 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CY0G (
.I(\i2/blk00000001/sig00000104 ),
.O(\i2/blk00000001/sig000000da/CY0G_4159 )
);
X_BUF #(
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/sig000000da/CYSELG (
.I(\i2/blk00000001/sig00000058 ),
.O(\i2/blk00000001/sig000000da/CYSELG_4151 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/XUSED (
.I(\i2/blk00000001/sig000000dc/XORF_4218 ),
.O(\i2/blk00000001/sig000000dc )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/XORF (
.I0(\i2/blk00000001/sig000000dc/CYINIT_4217 ),
.I1(\i2/blk00000001/sig00000056 ),
.O(\i2/blk00000001/sig000000dc/XORF_4218 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYMUXF (
.IA(\i2/blk00000001/sig000000dc/CY0F_4216 ),
.IB(\i2/blk00000001/sig000000dc/CYINIT_4217 ),
.SEL(\i2/blk00000001/sig000000dc/CYSELF_4204 ),
.O(\i2/blk00000001/sig00000055 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYMUXF2 (
.IA(\i2/blk00000001/sig000000dc/CY0F_4216 ),
.IB(\i2/blk00000001/sig000000dc/CY0F_4216 ),
.SEL(\i2/blk00000001/sig000000dc/CYSELF_4204 ),
.O(\i2/blk00000001/sig000000dc/CYMUXF2_4199 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYINIT (
.I(\i2/blk00000001/sig00000057 ),
.O(\i2/blk00000001/sig000000dc/CYINIT_4217 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CY0F (
.I(\i2/blk00000001/sig00000104 ),
.O(\i2/blk00000001/sig000000dc/CY0F_4216 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYSELF (
.I(\i2/blk00000001/sig00000056 ),
.O(\i2/blk00000001/sig000000dc/CYSELF_4204 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/YUSED (
.I(\i2/blk00000001/sig000000dc/XORG_4206 ),
.O(\i2/blk00000001/sig000000dd )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/XORG (
.I0(\i2/blk00000001/sig00000055 ),
.I1(\i2/blk00000001/sig00000054 ),
.O(\i2/blk00000001/sig000000dc/XORG_4206 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/FASTCARRY (
.I(\i2/blk00000001/sig00000057 ),
.O(\i2/blk00000001/sig000000dc/FASTCARRY_4201 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYAND (
.I0(\i2/blk00000001/sig000000dc/CYSELG_4190 ),
.I1(\i2/blk00000001/sig000000dc/CYSELF_4204 ),
.O(\i2/blk00000001/sig000000dc/CYAND_4202 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYMUXFAST (
.IA(\i2/blk00000001/sig000000dc/CYMUXG2_4200 ),
.IB(\i2/blk00000001/sig000000dc/FASTCARRY_4201 ),
.SEL(\i2/blk00000001/sig000000dc/CYAND_4202 ),
.O(\i2/blk00000001/sig000000dc/CYMUXFAST_4203 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYMUXG2 (
.IA(\i2/blk00000001/sig000000dc/CY0G_4198 ),
.IB(\i2/blk00000001/sig000000dc/CYMUXF2_4199 ),
.SEL(\i2/blk00000001/sig000000dc/CYSELG_4190 ),
.O(\i2/blk00000001/sig000000dc/CYMUXG2_4200 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CY0G (
.I(\i2/blk00000001/sig00000104 ),
.O(\i2/blk00000001/sig000000dc/CY0G_4198 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/sig000000dc/CYSELG (
.I(\i2/blk00000001/sig00000054 ),
.O(\i2/blk00000001/sig000000dc/CYSELG_4190 )
);
X_BUF #(
.LOC ( "SLICE_X25Y35" ))
\i2/blk00000001/sig000000de/XUSED (
.I(\i2/blk00000001/sig000000de/XORF_4233 ),
.O(\i2/blk00000001/sig000000de )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y35" ))
\i2/blk00000001/sig000000de/XORF (
.I0(\i2/blk00000001/sig000000de/CYINIT_4232 ),
.I1(\i2/blk00000001/sig00000052 ),
.O(\i2/blk00000001/sig000000de/XORF_4233 )
);
X_BUF #(
.LOC ( "SLICE_X25Y35" ))
\i2/blk00000001/sig000000de/CYINIT (
.I(\i2/blk00000001/sig000000dc/CYMUXFAST_4203 ),
.O(\i2/blk00000001/sig000000de/CYINIT_4232 )
);
X_ONE #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/LOGIC_ONE (
.O(\i2/blk00000001/sig00000185/LOGIC_ONE_4250 )
);
X_BUF #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/XUSED (
.I(\i2/blk00000001/sig00000185/XORF_4266 ),
.O(\i2/blk00000001/sig00000185 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/XORF (
.I0(\i2/blk00000001/sig00000185/CYINIT_4265 ),
.I1(\i2/blk00000001/sig00000185/F ),
.O(\i2/blk00000001/sig00000185/XORF_4266 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/CYMUXF (
.IA(\NLW_i2/blk00000001/sig00000185/CYMUXF_IA_UNCONNECTED ),
.IB(\i2/blk00000001/sig00000185/CYINIT_4265 ),
.SEL(\i2/blk00000001/sig00000185/LOGIC_ONE_4250 ),
.O(\i2/blk00000001/sig000001d7 )
);
X_BUF #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/CYINIT (
.I(\i2/blk00000001/sig00000185/BXINV_4254 ),
.O(\i2/blk00000001/sig00000185/CYINIT_4265 )
);
X_BUF #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/BXINV (
.I(1'b1),
.O(\i2/blk00000001/sig00000185/BXINV_4254 )
);
X_BUF #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/YUSED (
.I(\i2/blk00000001/sig00000185/XORG_4252 ),
.O(\i2/blk00000001/sig00000184 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/XORG (
.I0(\i2/blk00000001/sig000001d7 ),
.I1(\i2/blk00000001/sig00000185/G ),
.O(\i2/blk00000001/sig00000185/XORG_4252 )
);
X_BUF #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/COUTUSED (
.I(\i2/blk00000001/sig00000185/CYMUXG_4251 ),
.O(\i2/blk00000001/sig000001d1 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/CYMUXG (
.IA(\NLW_i2/blk00000001/sig00000185/CYMUXG_IA_UNCONNECTED ),
.IB(\i2/blk00000001/sig000001d7 ),
.SEL(\i2/blk00000001/sig00000185/LOGIC_ONE_4250 ),
.O(\i2/blk00000001/sig00000185/CYMUXG_4251 )
);
X_ONE #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/LOGIC_ONE (
.O(\i2/blk00000001/sig00000179/LOGIC_ONE_4297 )
);
X_BUF #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/XUSED (
.I(\i2/blk00000001/sig00000179/XORF_4298 ),
.O(\i2/blk00000001/sig00000179 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/XORF (
.I0(\i2/blk00000001/sig00000179/CYINIT_4296 ),
.I1(\i2/blk00000001/sig00000179/F ),
.O(\i2/blk00000001/sig00000179/XORF_4298 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/CYMUXF (
.IA(\NLW_i2/blk00000001/sig00000179/CYMUXF_IA_UNCONNECTED ),
.IB(\i2/blk00000001/sig00000179/CYINIT_4296 ),
.SEL(\i2/blk00000001/sig00000179/LOGIC_ONE_4297 ),
.O(\i2/blk00000001/sig000001cb )
);
X_BUF #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/CYINIT (
.I(\i2/blk00000001/sig000001d1 ),
.O(\i2/blk00000001/sig00000179/CYINIT_4296 )
);
X_BUF #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/YUSED (
.I(\i2/blk00000001/sig00000179/XORG_4284 ),
.O(\i2/blk00000001/sig0000016e )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/XORG (
.I0(\i2/blk00000001/sig000001cb ),
.I1(\i2/blk00000001/sig00000179/G ),
.O(\i2/blk00000001/sig00000179/XORG_4284 )
);
X_BUF #(
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/COUTUSED (
.I(\i2/blk00000001/sig000001d1 ),
.O(\i2/blk00000001/sig000001c5 )
);
X_ONE #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/LOGIC_ONE (
.O(\i2/blk00000001/sig00000163/LOGIC_ONE_4329 )
);
X_BUF #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/XUSED (
.I(\i2/blk00000001/sig00000163/XORF_4330 ),
.O(\i2/blk00000001/sig00000163 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/XORF (
.I0(\i2/blk00000001/sig00000163/CYINIT_4328 ),
.I1(\i2/blk00000001/sig00000163/F ),
.O(\i2/blk00000001/sig00000163/XORF_4330 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/CYMUXF (
.IA(\NLW_i2/blk00000001/sig00000163/CYMUXF_IA_UNCONNECTED ),
.IB(\i2/blk00000001/sig00000163/CYINIT_4328 ),
.SEL(\i2/blk00000001/sig00000163/LOGIC_ONE_4329 ),
.O(\i2/blk00000001/sig000001bf )
);
X_BUF #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/CYINIT (
.I(\i2/blk00000001/sig000001c5 ),
.O(\i2/blk00000001/sig00000163/CYINIT_4328 )
);
X_BUF #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/YUSED (
.I(\i2/blk00000001/sig00000163/XORG_4316 ),
.O(\i2/blk00000001/sig00000158 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/XORG (
.I0(\i2/blk00000001/sig000001bf ),
.I1(\i2/blk00000001/sig00000163/G ),
.O(\i2/blk00000001/sig00000163/XORG_4316 )
);
X_BUF #(
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/COUTUSED (
.I(\i2/blk00000001/sig000001c5 ),
.O(\i2/blk00000001/sig000001b9 )
);
X_ONE #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/LOGIC_ONE (
.O(\i2/blk00000001/sig0000014d/LOGIC_ONE_4361 )
);
X_BUF #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/XUSED (
.I(\i2/blk00000001/sig0000014d/XORF_4362 ),
.O(\i2/blk00000001/sig0000014d )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/XORF (
.I0(\i2/blk00000001/sig0000014d/CYINIT_4360 ),
.I1(\i2/blk00000001/sig0000014d/F ),
.O(\i2/blk00000001/sig0000014d/XORF_4362 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/CYMUXF (
.IA(\NLW_i2/blk00000001/sig0000014d/CYMUXF_IA_UNCONNECTED ),
.IB(\i2/blk00000001/sig0000014d/CYINIT_4360 ),
.SEL(\i2/blk00000001/sig0000014d/LOGIC_ONE_4361 ),
.O(\i2/blk00000001/sig000001b3 )
);
X_BUF #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/CYINIT (
.I(\i2/blk00000001/sig000001b9 ),
.O(\i2/blk00000001/sig0000014d/CYINIT_4360 )
);
X_BUF #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/YUSED (
.I(\i2/blk00000001/sig0000014d/XORG_4348 ),
.O(\i2/blk00000001/sig00000142 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/XORG (
.I0(\i2/blk00000001/sig000001b3 ),
.I1(\i2/blk00000001/sig0000014d/G ),
.O(\i2/blk00000001/sig0000014d/XORG_4348 )
);
X_BUF #(
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/COUTUSED (
.I(\i2/blk00000001/sig000001b9 ),
.O(\i2/blk00000001/sig000001ad )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/XUSED (
.I(\i2/blk00000001/sig00000137/XORF_4403 ),
.O(\i2/blk00000001/sig00000137 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/XORF (
.I0(\i2/blk00000001/sig00000137/CYINIT_4402 ),
.I1(\i2/blk00000001/sig000000e3 ),
.O(\i2/blk00000001/sig00000137/XORF_4403 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYMUXF (
.IA(\i2/blk00000001/sig00000137/CY0F_4401 ),
.IB(\i2/blk00000001/sig00000137/CYINIT_4402 ),
.SEL(\i2/blk00000001/sig00000137/CYSELF_4388 ),
.O(\i2/blk00000001/sig000001a7 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYMUXF2 (
.IA(\i2/blk00000001/sig00000137/CY0F_4401 ),
.IB(\i2/blk00000001/sig00000137/CY0F_4401 ),
.SEL(\i2/blk00000001/sig00000137/CYSELF_4388 ),
.O(\i2/blk00000001/sig00000137/CYMUXF2_4383 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYINIT (
.I(\i2/blk00000001/sig000001ad ),
.O(\i2/blk00000001/sig00000137/CYINIT_4402 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CY0F (
.I(\i2/blk00000001/sig000001fa ),
.O(\i2/blk00000001/sig00000137/CY0F_4401 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000137/FAND/IN1 ),
.O(\i2/blk00000001/sig000001fa )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYSELF (
.I(\i2/blk00000001/sig000000e3 ),
.O(\i2/blk00000001/sig00000137/CYSELF_4388 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/YUSED (
.I(\i2/blk00000001/sig00000137/XORG_4390 ),
.O(\i2/blk00000001/sig0000012c )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/XORG (
.I0(\i2/blk00000001/sig000001a7 ),
.I1(\i2/blk00000001/sig000000e2 ),
.O(\i2/blk00000001/sig00000137/XORG_4390 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/COUTUSED (
.I(\i2/blk00000001/sig00000137/CYMUXFAST_4387 ),
.O(\i2/blk00000001/sig000001a1 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/FASTCARRY (
.I(\i2/blk00000001/sig000001ad ),
.O(\i2/blk00000001/sig00000137/FASTCARRY_4385 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYAND (
.I0(\i2/blk00000001/sig00000137/CYSELG_4374 ),
.I1(\i2/blk00000001/sig00000137/CYSELF_4388 ),
.O(\i2/blk00000001/sig00000137/CYAND_4386 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYMUXFAST (
.IA(\i2/blk00000001/sig00000137/CYMUXG2_4384 ),
.IB(\i2/blk00000001/sig00000137/FASTCARRY_4385 ),
.SEL(\i2/blk00000001/sig00000137/CYAND_4386 ),
.O(\i2/blk00000001/sig00000137/CYMUXFAST_4387 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYMUXG2 (
.IA(\i2/blk00000001/sig00000137/CY0G_4382 ),
.IB(\i2/blk00000001/sig00000137/CYMUXF2_4383 ),
.SEL(\i2/blk00000001/sig00000137/CYSELG_4374 ),
.O(\i2/blk00000001/sig00000137/CYMUXG2_4384 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CY0G (
.I(\i2/blk00000001/sig000001f4 ),
.O(\i2/blk00000001/sig00000137/CY0G_4382 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000137/GAND/IN1 ),
.O(\i2/blk00000001/sig000001f4 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/sig00000137/CYSELG (
.I(\i2/blk00000001/sig000000e2 ),
.O(\i2/blk00000001/sig00000137/CYSELG_4374 )
);
X_LUT4 #(
.INIT ( 16'h5555 ),
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/blk000001d2 (
.ADR0(x2_8_IBUF_3048),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000e1 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/XUSED (
.I(\i2/blk00000001/sig00000121/XORF_4444 ),
.O(\i2/blk00000001/sig00000121 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/XORF (
.I0(\i2/blk00000001/sig00000121/CYINIT_4443 ),
.I1(\i2/blk00000001/sig000000e1 ),
.O(\i2/blk00000001/sig00000121/XORF_4444 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYMUXF (
.IA(\i2/blk00000001/sig00000121/CY0F_4442 ),
.IB(\i2/blk00000001/sig00000121/CYINIT_4443 ),
.SEL(\i2/blk00000001/sig00000121/CYSELF_4429 ),
.O(\i2/blk00000001/sig0000019b )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYMUXF2 (
.IA(\i2/blk00000001/sig00000121/CY0F_4442 ),
.IB(\i2/blk00000001/sig00000121/CY0F_4442 ),
.SEL(\i2/blk00000001/sig00000121/CYSELF_4429 ),
.O(\i2/blk00000001/sig00000121/CYMUXF2_4424 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYINIT (
.I(\i2/blk00000001/sig000001a1 ),
.O(\i2/blk00000001/sig00000121/CYINIT_4443 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CY0F (
.I(\i2/blk00000001/sig000001ee ),
.O(\i2/blk00000001/sig00000121/CY0F_4442 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000121/FAND/IN1 ),
.O(\i2/blk00000001/sig000001ee )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYSELF (
.I(\i2/blk00000001/sig000000e1 ),
.O(\i2/blk00000001/sig00000121/CYSELF_4429 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/YUSED (
.I(\i2/blk00000001/sig00000121/XORG_4431 ),
.O(\i2/blk00000001/sig00000116 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/XORG (
.I0(\i2/blk00000001/sig0000019b ),
.I1(\i2/blk00000001/sig000000e0 ),
.O(\i2/blk00000001/sig00000121/XORG_4431 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/COUTUSED (
.I(\i2/blk00000001/sig00000121/CYMUXFAST_4428 ),
.O(\i2/blk00000001/sig00000195 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/FASTCARRY (
.I(\i2/blk00000001/sig000001a1 ),
.O(\i2/blk00000001/sig00000121/FASTCARRY_4426 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYAND (
.I0(\i2/blk00000001/sig00000121/CYSELG_4415 ),
.I1(\i2/blk00000001/sig00000121/CYSELF_4429 ),
.O(\i2/blk00000001/sig00000121/CYAND_4427 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYMUXFAST (
.IA(\i2/blk00000001/sig00000121/CYMUXG2_4425 ),
.IB(\i2/blk00000001/sig00000121/FASTCARRY_4426 ),
.SEL(\i2/blk00000001/sig00000121/CYAND_4427 ),
.O(\i2/blk00000001/sig00000121/CYMUXFAST_4428 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYMUXG2 (
.IA(\i2/blk00000001/sig00000121/CY0G_4423 ),
.IB(\i2/blk00000001/sig00000121/CYMUXF2_4424 ),
.SEL(\i2/blk00000001/sig00000121/CYSELG_4415 ),
.O(\i2/blk00000001/sig00000121/CYMUXG2_4425 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CY0G (
.I(\i2/blk00000001/sig000001e8 ),
.O(\i2/blk00000001/sig00000121/CY0G_4423 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000121/GAND/IN1 ),
.O(\i2/blk00000001/sig000001e8 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/sig00000121/CYSELG (
.I(\i2/blk00000001/sig000000e0 ),
.O(\i2/blk00000001/sig00000121/CYSELG_4415 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/XUSED (
.I(\i2/blk00000001/sig000001da/XORF_4482 ),
.O(\i2/blk00000001/sig000001da )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/XORF (
.I0(\i2/blk00000001/sig000001da/CYINIT_4481 ),
.I1(\i2/blk00000001/sig000001da/F ),
.O(\i2/blk00000001/sig000001da/XORF_4482 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CYMUXF (
.IA(\i2/blk00000001/sig000001da/CY0F_4480 ),
.IB(\i2/blk00000001/sig000001da/CYINIT_4481 ),
.SEL(\i2/blk00000001/sig000001da/CYSELF_4471 ),
.O(\i2/blk00000001/sig000001db )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CYINIT (
.I(\i2/blk00000001/sig000001da/BXINV_4469 ),
.O(\i2/blk00000001/sig000001da/CYINIT_4481 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CY0F (
.I(\i2/blk00000001/sig0000022c ),
.O(\i2/blk00000001/sig000001da/CY0F_4480 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig000001da/FAND/IN1 ),
.O(\i2/blk00000001/sig0000022c )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CYSELF (
.I(\i2/blk00000001/sig000001da/F ),
.O(\i2/blk00000001/sig000001da/CYSELF_4471 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000001da/BXINV_4469 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/YUSED (
.I(\i2/blk00000001/sig000001da/XORG_4467 ),
.O(\i2/blk00000001/sig00000188 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/XORG (
.I0(\i2/blk00000001/sig000001db ),
.I1(\i2/blk00000001/sig000001da/G ),
.O(\i2/blk00000001/sig000001da/XORG_4467 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/COUTUSED (
.I(\i2/blk00000001/sig000001da/CYMUXG_4466 ),
.O(\i2/blk00000001/sig000001d9 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CYMUXG (
.IA(\i2/blk00000001/sig000001da/CY0G_4464 ),
.IB(\i2/blk00000001/sig000001db ),
.SEL(\i2/blk00000001/sig000001da/CYSELG_4455 ),
.O(\i2/blk00000001/sig000001da/CYMUXG_4466 )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CY0G (
.I(\i2/blk00000001/sig0000022b ),
.O(\i2/blk00000001/sig000001da/CY0G_4464 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig000001da/GAND/IN1 ),
.O(\i2/blk00000001/sig0000022b )
);
X_BUF #(
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/CYSELG (
.I(\i2/blk00000001/sig000001da/G ),
.O(\i2/blk00000001/sig000001da/CYSELG_4455 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/XUSED (
.I(\i2/blk00000001/sig00000186/XORF_4523 ),
.O(\i2/blk00000001/sig00000186 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/XORF (
.I0(\i2/blk00000001/sig00000186/CYINIT_4522 ),
.I1(\i2/blk00000001/sig00000186/F ),
.O(\i2/blk00000001/sig00000186/XORF_4523 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYMUXF (
.IA(\i2/blk00000001/sig00000186/CY0F_4521 ),
.IB(\i2/blk00000001/sig00000186/CYINIT_4522 ),
.SEL(\i2/blk00000001/sig00000186/CYSELF_4508 ),
.O(\i2/blk00000001/sig000001d2 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYMUXF2 (
.IA(\i2/blk00000001/sig00000186/CY0F_4521 ),
.IB(\i2/blk00000001/sig00000186/CY0F_4521 ),
.SEL(\i2/blk00000001/sig00000186/CYSELF_4508 ),
.O(\i2/blk00000001/sig00000186/CYMUXF2_4503 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYINIT (
.I(\i2/blk00000001/sig000001d9 ),
.O(\i2/blk00000001/sig00000186/CYINIT_4522 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CY0F (
.I(\i2/blk00000001/sig00000225 ),
.O(\i2/blk00000001/sig00000186/CY0F_4521 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000186/FAND/IN1 ),
.O(\i2/blk00000001/sig00000225 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYSELF (
.I(\i2/blk00000001/sig00000186/F ),
.O(\i2/blk00000001/sig00000186/CYSELF_4508 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/YUSED (
.I(\i2/blk00000001/sig00000186/XORG_4510 ),
.O(\i2/blk00000001/sig0000017a )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/XORG (
.I0(\i2/blk00000001/sig000001d2 ),
.I1(\i2/blk00000001/sig00000186/G ),
.O(\i2/blk00000001/sig00000186/XORG_4510 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/COUTUSED (
.I(\i2/blk00000001/sig00000186/CYMUXFAST_4507 ),
.O(\i2/blk00000001/sig000001cc )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/FASTCARRY (
.I(\i2/blk00000001/sig000001d9 ),
.O(\i2/blk00000001/sig00000186/FASTCARRY_4505 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYAND (
.I0(\i2/blk00000001/sig00000186/CYSELG_4493 ),
.I1(\i2/blk00000001/sig00000186/CYSELF_4508 ),
.O(\i2/blk00000001/sig00000186/CYAND_4506 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYMUXFAST (
.IA(\i2/blk00000001/sig00000186/CYMUXG2_4504 ),
.IB(\i2/blk00000001/sig00000186/FASTCARRY_4505 ),
.SEL(\i2/blk00000001/sig00000186/CYAND_4506 ),
.O(\i2/blk00000001/sig00000186/CYMUXFAST_4507 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYMUXG2 (
.IA(\i2/blk00000001/sig00000186/CY0G_4502 ),
.IB(\i2/blk00000001/sig00000186/CYMUXF2_4503 ),
.SEL(\i2/blk00000001/sig00000186/CYSELG_4493 ),
.O(\i2/blk00000001/sig00000186/CYMUXG2_4504 )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CY0G (
.I(\i2/blk00000001/sig0000021f ),
.O(\i2/blk00000001/sig00000186/CY0G_4502 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000186/GAND/IN1 ),
.O(\i2/blk00000001/sig0000021f )
);
X_BUF #(
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/CYSELG (
.I(\i2/blk00000001/sig00000186/G ),
.O(\i2/blk00000001/sig00000186/CYSELG_4493 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/XUSED (
.I(\i2/blk00000001/sig0000016f/XORF_4564 ),
.O(\i2/blk00000001/sig0000016f )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/XORF (
.I0(\i2/blk00000001/sig0000016f/CYINIT_4563 ),
.I1(\i2/blk00000001/sig0000016f/F ),
.O(\i2/blk00000001/sig0000016f/XORF_4564 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYMUXF (
.IA(\i2/blk00000001/sig0000016f/CY0F_4562 ),
.IB(\i2/blk00000001/sig0000016f/CYINIT_4563 ),
.SEL(\i2/blk00000001/sig0000016f/CYSELF_4549 ),
.O(\i2/blk00000001/sig000001c6 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYMUXF2 (
.IA(\i2/blk00000001/sig0000016f/CY0F_4562 ),
.IB(\i2/blk00000001/sig0000016f/CY0F_4562 ),
.SEL(\i2/blk00000001/sig0000016f/CYSELF_4549 ),
.O(\i2/blk00000001/sig0000016f/CYMUXF2_4544 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYINIT (
.I(\i2/blk00000001/sig000001cc ),
.O(\i2/blk00000001/sig0000016f/CYINIT_4563 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CY0F (
.I(\i2/blk00000001/sig00000219 ),
.O(\i2/blk00000001/sig0000016f/CY0F_4562 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000016f/FAND/IN1 ),
.O(\i2/blk00000001/sig00000219 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYSELF (
.I(\i2/blk00000001/sig0000016f/F ),
.O(\i2/blk00000001/sig0000016f/CYSELF_4549 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/YUSED (
.I(\i2/blk00000001/sig0000016f/XORG_4551 ),
.O(\i2/blk00000001/sig00000164 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/XORG (
.I0(\i2/blk00000001/sig000001c6 ),
.I1(\i2/blk00000001/sig0000016f/G ),
.O(\i2/blk00000001/sig0000016f/XORG_4551 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/COUTUSED (
.I(\i2/blk00000001/sig0000016f/CYMUXFAST_4548 ),
.O(\i2/blk00000001/sig000001c0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/FASTCARRY (
.I(\i2/blk00000001/sig000001cc ),
.O(\i2/blk00000001/sig0000016f/FASTCARRY_4546 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYAND (
.I0(\i2/blk00000001/sig0000016f/CYSELG_4534 ),
.I1(\i2/blk00000001/sig0000016f/CYSELF_4549 ),
.O(\i2/blk00000001/sig0000016f/CYAND_4547 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYMUXFAST (
.IA(\i2/blk00000001/sig0000016f/CYMUXG2_4545 ),
.IB(\i2/blk00000001/sig0000016f/FASTCARRY_4546 ),
.SEL(\i2/blk00000001/sig0000016f/CYAND_4547 ),
.O(\i2/blk00000001/sig0000016f/CYMUXFAST_4548 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYMUXG2 (
.IA(\i2/blk00000001/sig0000016f/CY0G_4543 ),
.IB(\i2/blk00000001/sig0000016f/CYMUXF2_4544 ),
.SEL(\i2/blk00000001/sig0000016f/CYSELG_4534 ),
.O(\i2/blk00000001/sig0000016f/CYMUXG2_4545 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CY0G (
.I(\i2/blk00000001/sig00000213 ),
.O(\i2/blk00000001/sig0000016f/CY0G_4543 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000016f/GAND/IN1 ),
.O(\i2/blk00000001/sig00000213 )
);
X_BUF #(
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/CYSELG (
.I(\i2/blk00000001/sig0000016f/G ),
.O(\i2/blk00000001/sig0000016f/CYSELG_4534 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/XUSED (
.I(\i2/blk00000001/sig00000159/XORF_4605 ),
.O(\i2/blk00000001/sig00000159 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/XORF (
.I0(\i2/blk00000001/sig00000159/CYINIT_4604 ),
.I1(\i2/blk00000001/sig00000159/F ),
.O(\i2/blk00000001/sig00000159/XORF_4605 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYMUXF (
.IA(\i2/blk00000001/sig00000159/CY0F_4603 ),
.IB(\i2/blk00000001/sig00000159/CYINIT_4604 ),
.SEL(\i2/blk00000001/sig00000159/CYSELF_4590 ),
.O(\i2/blk00000001/sig000001ba )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYMUXF2 (
.IA(\i2/blk00000001/sig00000159/CY0F_4603 ),
.IB(\i2/blk00000001/sig00000159/CY0F_4603 ),
.SEL(\i2/blk00000001/sig00000159/CYSELF_4590 ),
.O(\i2/blk00000001/sig00000159/CYMUXF2_4585 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYINIT (
.I(\i2/blk00000001/sig000001c0 ),
.O(\i2/blk00000001/sig00000159/CYINIT_4604 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CY0F (
.I(\i2/blk00000001/sig0000020d ),
.O(\i2/blk00000001/sig00000159/CY0F_4603 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000159/FAND/IN1 ),
.O(\i2/blk00000001/sig0000020d )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYSELF (
.I(\i2/blk00000001/sig00000159/F ),
.O(\i2/blk00000001/sig00000159/CYSELF_4590 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/YUSED (
.I(\i2/blk00000001/sig00000159/XORG_4592 ),
.O(\i2/blk00000001/sig0000014e )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/XORG (
.I0(\i2/blk00000001/sig000001ba ),
.I1(\i2/blk00000001/sig00000159/G ),
.O(\i2/blk00000001/sig00000159/XORG_4592 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/COUTUSED (
.I(\i2/blk00000001/sig00000159/CYMUXFAST_4589 ),
.O(\i2/blk00000001/sig000001b4 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/FASTCARRY (
.I(\i2/blk00000001/sig000001c0 ),
.O(\i2/blk00000001/sig00000159/FASTCARRY_4587 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYAND (
.I0(\i2/blk00000001/sig00000159/CYSELG_4575 ),
.I1(\i2/blk00000001/sig00000159/CYSELF_4590 ),
.O(\i2/blk00000001/sig00000159/CYAND_4588 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYMUXFAST (
.IA(\i2/blk00000001/sig00000159/CYMUXG2_4586 ),
.IB(\i2/blk00000001/sig00000159/FASTCARRY_4587 ),
.SEL(\i2/blk00000001/sig00000159/CYAND_4588 ),
.O(\i2/blk00000001/sig00000159/CYMUXFAST_4589 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYMUXG2 (
.IA(\i2/blk00000001/sig00000159/CY0G_4584 ),
.IB(\i2/blk00000001/sig00000159/CYMUXF2_4585 ),
.SEL(\i2/blk00000001/sig00000159/CYSELG_4575 ),
.O(\i2/blk00000001/sig00000159/CYMUXG2_4586 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CY0G (
.I(\i2/blk00000001/sig00000207 ),
.O(\i2/blk00000001/sig00000159/CY0G_4584 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000159/GAND/IN1 ),
.O(\i2/blk00000001/sig00000207 )
);
X_BUF #(
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/CYSELG (
.I(\i2/blk00000001/sig00000159/G ),
.O(\i2/blk00000001/sig00000159/CYSELG_4575 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/XUSED (
.I(\i2/blk00000001/sig00000143/XORF_4646 ),
.O(\i2/blk00000001/sig00000143 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/XORF (
.I0(\i2/blk00000001/sig00000143/CYINIT_4645 ),
.I1(\i2/blk00000001/sig00000143/F ),
.O(\i2/blk00000001/sig00000143/XORF_4646 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYMUXF (
.IA(\i2/blk00000001/sig00000143/CY0F_4644 ),
.IB(\i2/blk00000001/sig00000143/CYINIT_4645 ),
.SEL(\i2/blk00000001/sig00000143/CYSELF_4632 ),
.O(\i2/blk00000001/sig000001ae )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYMUXF2 (
.IA(\i2/blk00000001/sig00000143/CY0F_4644 ),
.IB(\i2/blk00000001/sig00000143/CY0F_4644 ),
.SEL(\i2/blk00000001/sig00000143/CYSELF_4632 ),
.O(\i2/blk00000001/sig00000143/CYMUXF2_4627 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYINIT (
.I(\i2/blk00000001/sig000001b4 ),
.O(\i2/blk00000001/sig00000143/CYINIT_4645 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CY0F (
.I(\i2/blk00000001/sig00000201 ),
.O(\i2/blk00000001/sig00000143/CY0F_4644 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000143/FAND/IN1 ),
.O(\i2/blk00000001/sig00000201 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYSELF (
.I(\i2/blk00000001/sig00000143/F ),
.O(\i2/blk00000001/sig00000143/CYSELF_4632 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/YUSED (
.I(\i2/blk00000001/sig00000143/XORG_4634 ),
.O(\i2/blk00000001/sig00000138 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/XORG (
.I0(\i2/blk00000001/sig000001ae ),
.I1(\i2/blk00000001/sig00000143/G ),
.O(\i2/blk00000001/sig00000143/XORG_4634 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/COUTUSED (
.I(\i2/blk00000001/sig00000143/CYMUXFAST_4631 ),
.O(\i2/blk00000001/sig000001a8 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/FASTCARRY (
.I(\i2/blk00000001/sig000001b4 ),
.O(\i2/blk00000001/sig00000143/FASTCARRY_4629 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYAND (
.I0(\i2/blk00000001/sig00000143/CYSELG_4617 ),
.I1(\i2/blk00000001/sig00000143/CYSELF_4632 ),
.O(\i2/blk00000001/sig00000143/CYAND_4630 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYMUXFAST (
.IA(\i2/blk00000001/sig00000143/CYMUXG2_4628 ),
.IB(\i2/blk00000001/sig00000143/FASTCARRY_4629 ),
.SEL(\i2/blk00000001/sig00000143/CYAND_4630 ),
.O(\i2/blk00000001/sig00000143/CYMUXFAST_4631 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYMUXG2 (
.IA(\i2/blk00000001/sig00000143/CY0G_4626 ),
.IB(\i2/blk00000001/sig00000143/CYMUXF2_4627 ),
.SEL(\i2/blk00000001/sig00000143/CYSELG_4617 ),
.O(\i2/blk00000001/sig00000143/CYMUXG2_4628 )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CY0G (
.I(\i2/blk00000001/sig000001fb ),
.O(\i2/blk00000001/sig00000143/CY0G_4626 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000143/GAND/IN1 ),
.O(\i2/blk00000001/sig000001fb )
);
X_BUF #(
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/CYSELG (
.I(\i2/blk00000001/sig00000143/G ),
.O(\i2/blk00000001/sig00000143/CYSELG_4617 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/XUSED (
.I(\i2/blk00000001/sig0000012d/XORF_4687 ),
.O(\i2/blk00000001/sig0000012d )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/XORF (
.I0(\i2/blk00000001/sig0000012d/CYINIT_4686 ),
.I1(\i2/blk00000001/sig0000012d/F ),
.O(\i2/blk00000001/sig0000012d/XORF_4687 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYMUXF (
.IA(\i2/blk00000001/sig0000012d/CY0F_4685 ),
.IB(\i2/blk00000001/sig0000012d/CYINIT_4686 ),
.SEL(\i2/blk00000001/sig0000012d/CYSELF_4673 ),
.O(\i2/blk00000001/sig000001a2 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYMUXF2 (
.IA(\i2/blk00000001/sig0000012d/CY0F_4685 ),
.IB(\i2/blk00000001/sig0000012d/CY0F_4685 ),
.SEL(\i2/blk00000001/sig0000012d/CYSELF_4673 ),
.O(\i2/blk00000001/sig0000012d/CYMUXF2_4668 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYINIT (
.I(\i2/blk00000001/sig000001a8 ),
.O(\i2/blk00000001/sig0000012d/CYINIT_4686 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CY0F (
.I(\i2/blk00000001/sig000001f5 ),
.O(\i2/blk00000001/sig0000012d/CY0F_4685 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000012d/FAND/IN1 ),
.O(\i2/blk00000001/sig000001f5 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYSELF (
.I(\i2/blk00000001/sig0000012d/F ),
.O(\i2/blk00000001/sig0000012d/CYSELF_4673 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/YUSED (
.I(\i2/blk00000001/sig0000012d/XORG_4675 ),
.O(\i2/blk00000001/sig00000122 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/XORG (
.I0(\i2/blk00000001/sig000001a2 ),
.I1(\i2/blk00000001/sig0000012d/G ),
.O(\i2/blk00000001/sig0000012d/XORG_4675 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/FASTCARRY (
.I(\i2/blk00000001/sig000001a8 ),
.O(\i2/blk00000001/sig0000012d/FASTCARRY_4670 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYAND (
.I0(\i2/blk00000001/sig0000012d/CYSELG_4658 ),
.I1(\i2/blk00000001/sig0000012d/CYSELF_4673 ),
.O(\i2/blk00000001/sig0000012d/CYAND_4671 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYMUXFAST (
.IA(\i2/blk00000001/sig0000012d/CYMUXG2_4669 ),
.IB(\i2/blk00000001/sig0000012d/FASTCARRY_4670 ),
.SEL(\i2/blk00000001/sig0000012d/CYAND_4671 ),
.O(\i2/blk00000001/sig0000012d/CYMUXFAST_4672 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYMUXG2 (
.IA(\i2/blk00000001/sig0000012d/CY0G_4667 ),
.IB(\i2/blk00000001/sig0000012d/CYMUXF2_4668 ),
.SEL(\i2/blk00000001/sig0000012d/CYSELG_4658 ),
.O(\i2/blk00000001/sig0000012d/CYMUXG2_4669 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CY0G (
.I(\i2/blk00000001/sig000001ef ),
.O(\i2/blk00000001/sig0000012d/CY0G_4667 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000012d/GAND/IN1 ),
.O(\i2/blk00000001/sig000001ef )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/CYSELG (
.I(\i2/blk00000001/sig0000012d/G ),
.O(\i2/blk00000001/sig0000012d/CYSELG_4658 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/XUSED (
.I(\i2/blk00000001/sig00000117/XORF_4719 ),
.O(\i2/blk00000001/sig00000117 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/XORF (
.I0(\i2/blk00000001/sig00000117/CYINIT_4718 ),
.I1(\i2/blk00000001/sig00000117/F ),
.O(\i2/blk00000001/sig00000117/XORF_4719 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/CYMUXF (
.IA(\i2/blk00000001/sig00000117/CY0F_4717 ),
.IB(\i2/blk00000001/sig00000117/CYINIT_4718 ),
.SEL(\i2/blk00000001/sig00000117/CYSELF_4708 ),
.O(\i2/blk00000001/sig00000196 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/CYINIT (
.I(\i2/blk00000001/sig0000012d/CYMUXFAST_4672 ),
.O(\i2/blk00000001/sig00000117/CYINIT_4718 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/CY0F (
.I(\i2/blk00000001/sig000001e9 ),
.O(\i2/blk00000001/sig00000117/CY0F_4717 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000117/FAND/IN1 ),
.O(\i2/blk00000001/sig000001e9 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/CYSELF (
.I(\i2/blk00000001/sig00000117/F ),
.O(\i2/blk00000001/sig00000117/CYSELF_4708 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/YUSED (
.I(\i2/blk00000001/sig00000117/XORG_4705 ),
.O(\i2/blk00000001/sig0000010c )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/XORG (
.I0(\i2/blk00000001/sig00000196 ),
.I1(\i2/blk00000001/sig00000117/G ),
.O(\i2/blk00000001/sig00000117/XORG_4705 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/XUSED (
.I(\i2/blk00000001/sig000001e3/XORF_4757 ),
.O(\i2/blk00000001/sig000001e3 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/XORF (
.I0(\i2/blk00000001/sig000001e3/CYINIT_4756 ),
.I1(\i2/blk00000001/sig000001e3/F ),
.O(\i2/blk00000001/sig000001e3/XORF_4757 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CYMUXF (
.IA(\i2/blk00000001/sig000001e3/CY0F_4755 ),
.IB(\i2/blk00000001/sig000001e3/CYINIT_4756 ),
.SEL(\i2/blk00000001/sig000001e3/CYSELF_4746 ),
.O(\i2/blk00000001/sig000001e4 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CYINIT (
.I(\i2/blk00000001/sig000001e3/BXINV_4744 ),
.O(\i2/blk00000001/sig000001e3/CYINIT_4756 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CY0F (
.I(\i2/blk00000001/sig00000235 ),
.O(\i2/blk00000001/sig000001e3/CY0F_4755 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/FAND (
.I0(\NlwBufferSignal_i2/blk00000001/sig000001e3/FAND/IN0 ),
.I1(1'b0),
.O(\i2/blk00000001/sig00000235 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CYSELF (
.I(\i2/blk00000001/sig000001e3/F ),
.O(\i2/blk00000001/sig000001e3/CYSELF_4746 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000001e3/BXINV_4744 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/YUSED (
.I(\i2/blk00000001/sig000001e3/XORG_4742 ),
.O(\i2/blk00000001/sig00000191 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/XORG (
.I0(\i2/blk00000001/sig000001e4 ),
.I1(\i2/blk00000001/sig000001e3/G ),
.O(\i2/blk00000001/sig000001e3/XORG_4742 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/COUTUSED (
.I(\i2/blk00000001/sig000001e3/CYMUXG_4741 ),
.O(\i2/blk00000001/sig000001e2 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CYMUXG (
.IA(\i2/blk00000001/sig000001e3/CY0G_4739 ),
.IB(\i2/blk00000001/sig000001e4 ),
.SEL(\i2/blk00000001/sig000001e3/CYSELG_4730 ),
.O(\i2/blk00000001/sig000001e3/CYMUXG_4741 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CY0G (
.I(\i2/blk00000001/sig00000234 ),
.O(\i2/blk00000001/sig000001e3/CY0G_4739 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/GAND (
.I0(\NlwBufferSignal_i2/blk00000001/sig000001e3/GAND/IN0 ),
.I1(1'b0),
.O(\i2/blk00000001/sig00000234 )
);
X_BUF #(
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/CYSELG (
.I(\i2/blk00000001/sig000001e3/G ),
.O(\i2/blk00000001/sig000001e3/CYSELG_4730 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/XUSED (
.I(\i2/blk00000001/sig0000018f/XORF_4798 ),
.O(\i2/blk00000001/sig0000018f )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/XORF (
.I0(\i2/blk00000001/sig0000018f/CYINIT_4797 ),
.I1(\i2/blk00000001/sig0000018f/F ),
.O(\i2/blk00000001/sig0000018f/XORF_4798 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYMUXF (
.IA(\i2/blk00000001/sig0000018f/CY0F_4796 ),
.IB(\i2/blk00000001/sig0000018f/CYINIT_4797 ),
.SEL(\i2/blk00000001/sig0000018f/CYSELF_4783 ),
.O(\i2/blk00000001/sig000001d5 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYMUXF2 (
.IA(\i2/blk00000001/sig0000018f/CY0F_4796 ),
.IB(\i2/blk00000001/sig0000018f/CY0F_4796 ),
.SEL(\i2/blk00000001/sig0000018f/CYSELF_4783 ),
.O(\i2/blk00000001/sig0000018f/CYMUXF2_4778 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYINIT (
.I(\i2/blk00000001/sig000001e2 ),
.O(\i2/blk00000001/sig0000018f/CYINIT_4797 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CY0F (
.I(\i2/blk00000001/sig00000228 ),
.O(\i2/blk00000001/sig0000018f/CY0F_4796 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000018f/FAND/IN1 ),
.O(\i2/blk00000001/sig00000228 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYSELF (
.I(\i2/blk00000001/sig0000018f/F ),
.O(\i2/blk00000001/sig0000018f/CYSELF_4783 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/YUSED (
.I(\i2/blk00000001/sig0000018f/XORG_4785 ),
.O(\i2/blk00000001/sig00000180 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/XORG (
.I0(\i2/blk00000001/sig000001d5 ),
.I1(\i2/blk00000001/sig0000018f/G ),
.O(\i2/blk00000001/sig0000018f/XORG_4785 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/COUTUSED (
.I(\i2/blk00000001/sig0000018f/CYMUXFAST_4782 ),
.O(\i2/blk00000001/sig000001cf )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/FASTCARRY (
.I(\i2/blk00000001/sig000001e2 ),
.O(\i2/blk00000001/sig0000018f/FASTCARRY_4780 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYAND (
.I0(\i2/blk00000001/sig0000018f/CYSELG_4768 ),
.I1(\i2/blk00000001/sig0000018f/CYSELF_4783 ),
.O(\i2/blk00000001/sig0000018f/CYAND_4781 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYMUXFAST (
.IA(\i2/blk00000001/sig0000018f/CYMUXG2_4779 ),
.IB(\i2/blk00000001/sig0000018f/FASTCARRY_4780 ),
.SEL(\i2/blk00000001/sig0000018f/CYAND_4781 ),
.O(\i2/blk00000001/sig0000018f/CYMUXFAST_4782 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYMUXG2 (
.IA(\i2/blk00000001/sig0000018f/CY0G_4777 ),
.IB(\i2/blk00000001/sig0000018f/CYMUXF2_4778 ),
.SEL(\i2/blk00000001/sig0000018f/CYSELG_4768 ),
.O(\i2/blk00000001/sig0000018f/CYMUXG2_4779 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CY0G (
.I(\i2/blk00000001/sig00000222 ),
.O(\i2/blk00000001/sig0000018f/CY0G_4777 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000018f/GAND/IN1 ),
.O(\i2/blk00000001/sig00000222 )
);
X_BUF #(
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/CYSELG (
.I(\i2/blk00000001/sig0000018f/G ),
.O(\i2/blk00000001/sig0000018f/CYSELG_4768 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/XUSED (
.I(\i2/blk00000001/sig00000175/XORF_4839 ),
.O(\i2/blk00000001/sig00000175 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/XORF (
.I0(\i2/blk00000001/sig00000175/CYINIT_4838 ),
.I1(\i2/blk00000001/sig00000175/F ),
.O(\i2/blk00000001/sig00000175/XORF_4839 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYMUXF (
.IA(\i2/blk00000001/sig00000175/CY0F_4837 ),
.IB(\i2/blk00000001/sig00000175/CYINIT_4838 ),
.SEL(\i2/blk00000001/sig00000175/CYSELF_4824 ),
.O(\i2/blk00000001/sig000001c9 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYMUXF2 (
.IA(\i2/blk00000001/sig00000175/CY0F_4837 ),
.IB(\i2/blk00000001/sig00000175/CY0F_4837 ),
.SEL(\i2/blk00000001/sig00000175/CYSELF_4824 ),
.O(\i2/blk00000001/sig00000175/CYMUXF2_4819 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYINIT (
.I(\i2/blk00000001/sig000001cf ),
.O(\i2/blk00000001/sig00000175/CYINIT_4838 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CY0F (
.I(\i2/blk00000001/sig0000021c ),
.O(\i2/blk00000001/sig00000175/CY0F_4837 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000175/FAND/IN1 ),
.O(\i2/blk00000001/sig0000021c )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYSELF (
.I(\i2/blk00000001/sig00000175/F ),
.O(\i2/blk00000001/sig00000175/CYSELF_4824 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/YUSED (
.I(\i2/blk00000001/sig00000175/XORG_4826 ),
.O(\i2/blk00000001/sig0000016a )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/XORG (
.I0(\i2/blk00000001/sig000001c9 ),
.I1(\i2/blk00000001/sig00000175/G ),
.O(\i2/blk00000001/sig00000175/XORG_4826 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/COUTUSED (
.I(\i2/blk00000001/sig00000175/CYMUXFAST_4823 ),
.O(\i2/blk00000001/sig000001c3 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/FASTCARRY (
.I(\i2/blk00000001/sig000001cf ),
.O(\i2/blk00000001/sig00000175/FASTCARRY_4821 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYAND (
.I0(\i2/blk00000001/sig00000175/CYSELG_4809 ),
.I1(\i2/blk00000001/sig00000175/CYSELF_4824 ),
.O(\i2/blk00000001/sig00000175/CYAND_4822 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYMUXFAST (
.IA(\i2/blk00000001/sig00000175/CYMUXG2_4820 ),
.IB(\i2/blk00000001/sig00000175/FASTCARRY_4821 ),
.SEL(\i2/blk00000001/sig00000175/CYAND_4822 ),
.O(\i2/blk00000001/sig00000175/CYMUXFAST_4823 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYMUXG2 (
.IA(\i2/blk00000001/sig00000175/CY0G_4818 ),
.IB(\i2/blk00000001/sig00000175/CYMUXF2_4819 ),
.SEL(\i2/blk00000001/sig00000175/CYSELG_4809 ),
.O(\i2/blk00000001/sig00000175/CYMUXG2_4820 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CY0G (
.I(\i2/blk00000001/sig00000216 ),
.O(\i2/blk00000001/sig00000175/CY0G_4818 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000175/GAND/IN1 ),
.O(\i2/blk00000001/sig00000216 )
);
X_BUF #(
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/CYSELG (
.I(\i2/blk00000001/sig00000175/G ),
.O(\i2/blk00000001/sig00000175/CYSELG_4809 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/XUSED (
.I(\i2/blk00000001/sig0000015f/XORF_4880 ),
.O(\i2/blk00000001/sig0000015f )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/XORF (
.I0(\i2/blk00000001/sig0000015f/CYINIT_4879 ),
.I1(\i2/blk00000001/sig0000015f/F ),
.O(\i2/blk00000001/sig0000015f/XORF_4880 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYMUXF (
.IA(\i2/blk00000001/sig0000015f/CY0F_4878 ),
.IB(\i2/blk00000001/sig0000015f/CYINIT_4879 ),
.SEL(\i2/blk00000001/sig0000015f/CYSELF_4865 ),
.O(\i2/blk00000001/sig000001bd )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYMUXF2 (
.IA(\i2/blk00000001/sig0000015f/CY0F_4878 ),
.IB(\i2/blk00000001/sig0000015f/CY0F_4878 ),
.SEL(\i2/blk00000001/sig0000015f/CYSELF_4865 ),
.O(\i2/blk00000001/sig0000015f/CYMUXF2_4860 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYINIT (
.I(\i2/blk00000001/sig000001c3 ),
.O(\i2/blk00000001/sig0000015f/CYINIT_4879 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CY0F (
.I(\i2/blk00000001/sig00000210 ),
.O(\i2/blk00000001/sig0000015f/CY0F_4878 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000015f/FAND/IN1 ),
.O(\i2/blk00000001/sig00000210 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYSELF (
.I(\i2/blk00000001/sig0000015f/F ),
.O(\i2/blk00000001/sig0000015f/CYSELF_4865 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/YUSED (
.I(\i2/blk00000001/sig0000015f/XORG_4867 ),
.O(\i2/blk00000001/sig00000154 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/XORG (
.I0(\i2/blk00000001/sig000001bd ),
.I1(\i2/blk00000001/sig0000015f/G ),
.O(\i2/blk00000001/sig0000015f/XORG_4867 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/COUTUSED (
.I(\i2/blk00000001/sig0000015f/CYMUXFAST_4864 ),
.O(\i2/blk00000001/sig000001b7 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/FASTCARRY (
.I(\i2/blk00000001/sig000001c3 ),
.O(\i2/blk00000001/sig0000015f/FASTCARRY_4862 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYAND (
.I0(\i2/blk00000001/sig0000015f/CYSELG_4850 ),
.I1(\i2/blk00000001/sig0000015f/CYSELF_4865 ),
.O(\i2/blk00000001/sig0000015f/CYAND_4863 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYMUXFAST (
.IA(\i2/blk00000001/sig0000015f/CYMUXG2_4861 ),
.IB(\i2/blk00000001/sig0000015f/FASTCARRY_4862 ),
.SEL(\i2/blk00000001/sig0000015f/CYAND_4863 ),
.O(\i2/blk00000001/sig0000015f/CYMUXFAST_4864 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYMUXG2 (
.IA(\i2/blk00000001/sig0000015f/CY0G_4859 ),
.IB(\i2/blk00000001/sig0000015f/CYMUXF2_4860 ),
.SEL(\i2/blk00000001/sig0000015f/CYSELG_4850 ),
.O(\i2/blk00000001/sig0000015f/CYMUXG2_4861 )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CY0G (
.I(\i2/blk00000001/sig0000020a ),
.O(\i2/blk00000001/sig0000015f/CY0G_4859 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000015f/GAND/IN1 ),
.O(\i2/blk00000001/sig0000020a )
);
X_BUF #(
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/CYSELG (
.I(\i2/blk00000001/sig0000015f/G ),
.O(\i2/blk00000001/sig0000015f/CYSELG_4850 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/XUSED (
.I(\i2/blk00000001/sig00000149/XORF_4921 ),
.O(\i2/blk00000001/sig00000149 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/XORF (
.I0(\i2/blk00000001/sig00000149/CYINIT_4920 ),
.I1(\i2/blk00000001/sig00000149/F ),
.O(\i2/blk00000001/sig00000149/XORF_4921 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYMUXF (
.IA(\i2/blk00000001/sig00000149/CY0F_4919 ),
.IB(\i2/blk00000001/sig00000149/CYINIT_4920 ),
.SEL(\i2/blk00000001/sig00000149/CYSELF_4907 ),
.O(\i2/blk00000001/sig000001b1 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYMUXF2 (
.IA(\i2/blk00000001/sig00000149/CY0F_4919 ),
.IB(\i2/blk00000001/sig00000149/CY0F_4919 ),
.SEL(\i2/blk00000001/sig00000149/CYSELF_4907 ),
.O(\i2/blk00000001/sig00000149/CYMUXF2_4902 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYINIT (
.I(\i2/blk00000001/sig000001b7 ),
.O(\i2/blk00000001/sig00000149/CYINIT_4920 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CY0F (
.I(\i2/blk00000001/sig00000204 ),
.O(\i2/blk00000001/sig00000149/CY0F_4919 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000149/FAND/IN1 ),
.O(\i2/blk00000001/sig00000204 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYSELF (
.I(\i2/blk00000001/sig00000149/F ),
.O(\i2/blk00000001/sig00000149/CYSELF_4907 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/YUSED (
.I(\i2/blk00000001/sig00000149/XORG_4909 ),
.O(\i2/blk00000001/sig0000013e )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/XORG (
.I0(\i2/blk00000001/sig000001b1 ),
.I1(\i2/blk00000001/sig00000149/G ),
.O(\i2/blk00000001/sig00000149/XORG_4909 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/COUTUSED (
.I(\i2/blk00000001/sig00000149/CYMUXFAST_4906 ),
.O(\i2/blk00000001/sig000001ab )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/FASTCARRY (
.I(\i2/blk00000001/sig000001b7 ),
.O(\i2/blk00000001/sig00000149/FASTCARRY_4904 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYAND (
.I0(\i2/blk00000001/sig00000149/CYSELG_4892 ),
.I1(\i2/blk00000001/sig00000149/CYSELF_4907 ),
.O(\i2/blk00000001/sig00000149/CYAND_4905 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYMUXFAST (
.IA(\i2/blk00000001/sig00000149/CYMUXG2_4903 ),
.IB(\i2/blk00000001/sig00000149/FASTCARRY_4904 ),
.SEL(\i2/blk00000001/sig00000149/CYAND_4905 ),
.O(\i2/blk00000001/sig00000149/CYMUXFAST_4906 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYMUXG2 (
.IA(\i2/blk00000001/sig00000149/CY0G_4901 ),
.IB(\i2/blk00000001/sig00000149/CYMUXF2_4902 ),
.SEL(\i2/blk00000001/sig00000149/CYSELG_4892 ),
.O(\i2/blk00000001/sig00000149/CYMUXG2_4903 )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CY0G (
.I(\i2/blk00000001/sig000001fe ),
.O(\i2/blk00000001/sig00000149/CY0G_4901 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000149/GAND/IN1 ),
.O(\i2/blk00000001/sig000001fe )
);
X_BUF #(
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/CYSELG (
.I(\i2/blk00000001/sig00000149/G ),
.O(\i2/blk00000001/sig00000149/CYSELG_4892 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/XUSED (
.I(\i2/blk00000001/sig00000133/XORF_4962 ),
.O(\i2/blk00000001/sig00000133 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/XORF (
.I0(\i2/blk00000001/sig00000133/CYINIT_4961 ),
.I1(\i2/blk00000001/sig00000133/F ),
.O(\i2/blk00000001/sig00000133/XORF_4962 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYMUXF (
.IA(\i2/blk00000001/sig00000133/CY0F_4960 ),
.IB(\i2/blk00000001/sig00000133/CYINIT_4961 ),
.SEL(\i2/blk00000001/sig00000133/CYSELF_4948 ),
.O(\i2/blk00000001/sig000001a5 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYMUXF2 (
.IA(\i2/blk00000001/sig00000133/CY0F_4960 ),
.IB(\i2/blk00000001/sig00000133/CY0F_4960 ),
.SEL(\i2/blk00000001/sig00000133/CYSELF_4948 ),
.O(\i2/blk00000001/sig00000133/CYMUXF2_4943 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYINIT (
.I(\i2/blk00000001/sig000001ab ),
.O(\i2/blk00000001/sig00000133/CYINIT_4961 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CY0F (
.I(\i2/blk00000001/sig000001f8 ),
.O(\i2/blk00000001/sig00000133/CY0F_4960 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/FAND (
.I0(\NlwBufferSignal_i2/blk00000001/sig00000133/FAND/IN0 ),
.I1(1'b0),
.O(\i2/blk00000001/sig000001f8 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYSELF (
.I(\i2/blk00000001/sig00000133/F ),
.O(\i2/blk00000001/sig00000133/CYSELF_4948 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/YUSED (
.I(\i2/blk00000001/sig00000133/XORG_4950 ),
.O(\i2/blk00000001/sig00000128 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/XORG (
.I0(\i2/blk00000001/sig000001a5 ),
.I1(\i2/blk00000001/sig00000133/G ),
.O(\i2/blk00000001/sig00000133/XORG_4950 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/FASTCARRY (
.I(\i2/blk00000001/sig000001ab ),
.O(\i2/blk00000001/sig00000133/FASTCARRY_4945 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYAND (
.I0(\i2/blk00000001/sig00000133/CYSELG_4933 ),
.I1(\i2/blk00000001/sig00000133/CYSELF_4948 ),
.O(\i2/blk00000001/sig00000133/CYAND_4946 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYMUXFAST (
.IA(\i2/blk00000001/sig00000133/CYMUXG2_4944 ),
.IB(\i2/blk00000001/sig00000133/FASTCARRY_4945 ),
.SEL(\i2/blk00000001/sig00000133/CYAND_4946 ),
.O(\i2/blk00000001/sig00000133/CYMUXFAST_4947 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYMUXG2 (
.IA(\i2/blk00000001/sig00000133/CY0G_4942 ),
.IB(\i2/blk00000001/sig00000133/CYMUXF2_4943 ),
.SEL(\i2/blk00000001/sig00000133/CYSELG_4933 ),
.O(\i2/blk00000001/sig00000133/CYMUXG2_4944 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CY0G (
.I(\i2/blk00000001/sig000001f2 ),
.O(\i2/blk00000001/sig00000133/CY0G_4942 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000133/GAND/IN1 ),
.O(\i2/blk00000001/sig000001f2 )
);
X_BUF #(
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/CYSELG (
.I(\i2/blk00000001/sig00000133/G ),
.O(\i2/blk00000001/sig00000133/CYSELG_4933 )
);
X_BUF #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/XUSED (
.I(\i2/blk00000001/sig0000011d/XORF_4994 ),
.O(\i2/blk00000001/sig0000011d )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/XORF (
.I0(\i2/blk00000001/sig0000011d/CYINIT_4993 ),
.I1(\i2/blk00000001/sig0000011d/F ),
.O(\i2/blk00000001/sig0000011d/XORF_4994 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/CYMUXF (
.IA(\i2/blk00000001/sig0000011d/CY0F_4992 ),
.IB(\i2/blk00000001/sig0000011d/CYINIT_4993 ),
.SEL(\i2/blk00000001/sig0000011d/CYSELF_4983 ),
.O(\i2/blk00000001/sig00000199 )
);
X_BUF #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/CYINIT (
.I(\i2/blk00000001/sig00000133/CYMUXFAST_4947 ),
.O(\i2/blk00000001/sig0000011d/CYINIT_4993 )
);
X_BUF #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/CY0F (
.I(\i2/blk00000001/sig000001ec ),
.O(\i2/blk00000001/sig0000011d/CY0F_4992 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/FAND (
.I0(\NlwBufferSignal_i2/blk00000001/sig0000011d/FAND/IN0 ),
.I1(1'b0),
.O(\i2/blk00000001/sig000001ec )
);
X_BUF #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/CYSELF (
.I(\i2/blk00000001/sig0000011d/F ),
.O(\i2/blk00000001/sig0000011d/CYSELF_4983 )
);
X_BUF #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/YUSED (
.I(\i2/blk00000001/sig0000011d/XORG_4980 ),
.O(\i2/blk00000001/sig00000112 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/XORG (
.I0(\i2/blk00000001/sig00000199 ),
.I1(\i2/blk00000001/sig0000011d/G ),
.O(\i2/blk00000001/sig0000011d/XORG_4980 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/XUSED (
.I(\i2/blk00000001/sig000001dd/XORF_5032 ),
.O(\i2/blk00000001/sig000001dd )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/XORF (
.I0(\i2/blk00000001/sig000001dd/CYINIT_5031 ),
.I1(\i2/blk00000001/sig000001dd/F ),
.O(\i2/blk00000001/sig000001dd/XORF_5032 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CYMUXF (
.IA(\i2/blk00000001/sig000001dd/CY0F_5030 ),
.IB(\i2/blk00000001/sig000001dd/CYINIT_5031 ),
.SEL(\i2/blk00000001/sig000001dd/CYSELF_5021 ),
.O(\i2/blk00000001/sig000001de )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CYINIT (
.I(\i2/blk00000001/sig000001dd/BXINV_5019 ),
.O(\i2/blk00000001/sig000001dd/CYINIT_5031 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CY0F (
.I(\i2/blk00000001/sig0000022f ),
.O(\i2/blk00000001/sig000001dd/CY0F_5030 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig000001dd/FAND/IN1 ),
.O(\i2/blk00000001/sig0000022f )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CYSELF (
.I(\i2/blk00000001/sig000001dd/F ),
.O(\i2/blk00000001/sig000001dd/CYSELF_5021 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000001dd/BXINV_5019 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/YUSED (
.I(\i2/blk00000001/sig000001dd/XORG_5017 ),
.O(\i2/blk00000001/sig0000018b )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/XORG (
.I0(\i2/blk00000001/sig000001de ),
.I1(\i2/blk00000001/sig000001dd/G ),
.O(\i2/blk00000001/sig000001dd/XORG_5017 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/COUTUSED (
.I(\i2/blk00000001/sig000001dd/CYMUXG_5016 ),
.O(\i2/blk00000001/sig000001dc )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CYMUXG (
.IA(\i2/blk00000001/sig000001dd/CY0G_5014 ),
.IB(\i2/blk00000001/sig000001de ),
.SEL(\i2/blk00000001/sig000001dd/CYSELG_5005 ),
.O(\i2/blk00000001/sig000001dd/CYMUXG_5016 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CY0G (
.I(\i2/blk00000001/sig0000022e ),
.O(\i2/blk00000001/sig000001dd/CY0G_5014 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig000001dd/GAND/IN1 ),
.O(\i2/blk00000001/sig0000022e )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/CYSELG (
.I(\i2/blk00000001/sig000001dd/G ),
.O(\i2/blk00000001/sig000001dd/CYSELG_5005 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/XUSED (
.I(\i2/blk00000001/sig00000189/XORF_5073 ),
.O(\i2/blk00000001/sig00000189 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/XORF (
.I0(\i2/blk00000001/sig00000189/CYINIT_5072 ),
.I1(\i2/blk00000001/sig00000189/F ),
.O(\i2/blk00000001/sig00000189/XORF_5073 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYMUXF (
.IA(\i2/blk00000001/sig00000189/CY0F_5071 ),
.IB(\i2/blk00000001/sig00000189/CYINIT_5072 ),
.SEL(\i2/blk00000001/sig00000189/CYSELF_5058 ),
.O(\i2/blk00000001/sig000001d3 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYMUXF2 (
.IA(\i2/blk00000001/sig00000189/CY0F_5071 ),
.IB(\i2/blk00000001/sig00000189/CY0F_5071 ),
.SEL(\i2/blk00000001/sig00000189/CYSELF_5058 ),
.O(\i2/blk00000001/sig00000189/CYMUXF2_5053 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYINIT (
.I(\i2/blk00000001/sig000001dc ),
.O(\i2/blk00000001/sig00000189/CYINIT_5072 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CY0F (
.I(\i2/blk00000001/sig00000226 ),
.O(\i2/blk00000001/sig00000189/CY0F_5071 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000189/FAND/IN1 ),
.O(\i2/blk00000001/sig00000226 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYSELF (
.I(\i2/blk00000001/sig00000189/F ),
.O(\i2/blk00000001/sig00000189/CYSELF_5058 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/YUSED (
.I(\i2/blk00000001/sig00000189/XORG_5060 ),
.O(\i2/blk00000001/sig0000017c )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/XORG (
.I0(\i2/blk00000001/sig000001d3 ),
.I1(\i2/blk00000001/sig00000189/G ),
.O(\i2/blk00000001/sig00000189/XORG_5060 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/COUTUSED (
.I(\i2/blk00000001/sig00000189/CYMUXFAST_5057 ),
.O(\i2/blk00000001/sig000001cd )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/FASTCARRY (
.I(\i2/blk00000001/sig000001dc ),
.O(\i2/blk00000001/sig00000189/FASTCARRY_5055 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYAND (
.I0(\i2/blk00000001/sig00000189/CYSELG_5043 ),
.I1(\i2/blk00000001/sig00000189/CYSELF_5058 ),
.O(\i2/blk00000001/sig00000189/CYAND_5056 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYMUXFAST (
.IA(\i2/blk00000001/sig00000189/CYMUXG2_5054 ),
.IB(\i2/blk00000001/sig00000189/FASTCARRY_5055 ),
.SEL(\i2/blk00000001/sig00000189/CYAND_5056 ),
.O(\i2/blk00000001/sig00000189/CYMUXFAST_5057 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYMUXG2 (
.IA(\i2/blk00000001/sig00000189/CY0G_5052 ),
.IB(\i2/blk00000001/sig00000189/CYMUXF2_5053 ),
.SEL(\i2/blk00000001/sig00000189/CYSELG_5043 ),
.O(\i2/blk00000001/sig00000189/CYMUXG2_5054 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CY0G (
.I(\i2/blk00000001/sig00000220 ),
.O(\i2/blk00000001/sig00000189/CY0G_5052 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000189/GAND/IN1 ),
.O(\i2/blk00000001/sig00000220 )
);
X_BUF #(
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/CYSELG (
.I(\i2/blk00000001/sig00000189/G ),
.O(\i2/blk00000001/sig00000189/CYSELG_5043 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/XUSED (
.I(\i2/blk00000001/sig00000171/XORF_5114 ),
.O(\i2/blk00000001/sig00000171 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/XORF (
.I0(\i2/blk00000001/sig00000171/CYINIT_5113 ),
.I1(\i2/blk00000001/sig00000171/F ),
.O(\i2/blk00000001/sig00000171/XORF_5114 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYMUXF (
.IA(\i2/blk00000001/sig00000171/CY0F_5112 ),
.IB(\i2/blk00000001/sig00000171/CYINIT_5113 ),
.SEL(\i2/blk00000001/sig00000171/CYSELF_5099 ),
.O(\i2/blk00000001/sig000001c7 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYMUXF2 (
.IA(\i2/blk00000001/sig00000171/CY0F_5112 ),
.IB(\i2/blk00000001/sig00000171/CY0F_5112 ),
.SEL(\i2/blk00000001/sig00000171/CYSELF_5099 ),
.O(\i2/blk00000001/sig00000171/CYMUXF2_5094 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYINIT (
.I(\i2/blk00000001/sig000001cd ),
.O(\i2/blk00000001/sig00000171/CYINIT_5113 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CY0F (
.I(\i2/blk00000001/sig0000021a ),
.O(\i2/blk00000001/sig00000171/CY0F_5112 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000171/FAND/IN1 ),
.O(\i2/blk00000001/sig0000021a )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYSELF (
.I(\i2/blk00000001/sig00000171/F ),
.O(\i2/blk00000001/sig00000171/CYSELF_5099 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/YUSED (
.I(\i2/blk00000001/sig00000171/XORG_5101 ),
.O(\i2/blk00000001/sig00000166 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/XORG (
.I0(\i2/blk00000001/sig000001c7 ),
.I1(\i2/blk00000001/sig00000171/G ),
.O(\i2/blk00000001/sig00000171/XORG_5101 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/COUTUSED (
.I(\i2/blk00000001/sig00000171/CYMUXFAST_5098 ),
.O(\i2/blk00000001/sig000001c1 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/FASTCARRY (
.I(\i2/blk00000001/sig000001cd ),
.O(\i2/blk00000001/sig00000171/FASTCARRY_5096 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYAND (
.I0(\i2/blk00000001/sig00000171/CYSELG_5084 ),
.I1(\i2/blk00000001/sig00000171/CYSELF_5099 ),
.O(\i2/blk00000001/sig00000171/CYAND_5097 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYMUXFAST (
.IA(\i2/blk00000001/sig00000171/CYMUXG2_5095 ),
.IB(\i2/blk00000001/sig00000171/FASTCARRY_5096 ),
.SEL(\i2/blk00000001/sig00000171/CYAND_5097 ),
.O(\i2/blk00000001/sig00000171/CYMUXFAST_5098 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYMUXG2 (
.IA(\i2/blk00000001/sig00000171/CY0G_5093 ),
.IB(\i2/blk00000001/sig00000171/CYMUXF2_5094 ),
.SEL(\i2/blk00000001/sig00000171/CYSELG_5084 ),
.O(\i2/blk00000001/sig00000171/CYMUXG2_5095 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CY0G (
.I(\i2/blk00000001/sig00000214 ),
.O(\i2/blk00000001/sig00000171/CY0G_5093 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000171/GAND/IN1 ),
.O(\i2/blk00000001/sig00000214 )
);
X_BUF #(
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/CYSELG (
.I(\i2/blk00000001/sig00000171/G ),
.O(\i2/blk00000001/sig00000171/CYSELG_5084 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/XUSED (
.I(\i2/blk00000001/sig0000015b/XORF_5155 ),
.O(\i2/blk00000001/sig0000015b )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/XORF (
.I0(\i2/blk00000001/sig0000015b/CYINIT_5154 ),
.I1(\i2/blk00000001/sig0000015b/F ),
.O(\i2/blk00000001/sig0000015b/XORF_5155 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYMUXF (
.IA(\i2/blk00000001/sig0000015b/CY0F_5153 ),
.IB(\i2/blk00000001/sig0000015b/CYINIT_5154 ),
.SEL(\i2/blk00000001/sig0000015b/CYSELF_5140 ),
.O(\i2/blk00000001/sig000001bb )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYMUXF2 (
.IA(\i2/blk00000001/sig0000015b/CY0F_5153 ),
.IB(\i2/blk00000001/sig0000015b/CY0F_5153 ),
.SEL(\i2/blk00000001/sig0000015b/CYSELF_5140 ),
.O(\i2/blk00000001/sig0000015b/CYMUXF2_5135 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYINIT (
.I(\i2/blk00000001/sig000001c1 ),
.O(\i2/blk00000001/sig0000015b/CYINIT_5154 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CY0F (
.I(\i2/blk00000001/sig0000020e ),
.O(\i2/blk00000001/sig0000015b/CY0F_5153 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000015b/FAND/IN1 ),
.O(\i2/blk00000001/sig0000020e )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYSELF (
.I(\i2/blk00000001/sig0000015b/F ),
.O(\i2/blk00000001/sig0000015b/CYSELF_5140 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/YUSED (
.I(\i2/blk00000001/sig0000015b/XORG_5142 ),
.O(\i2/blk00000001/sig00000150 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/XORG (
.I0(\i2/blk00000001/sig000001bb ),
.I1(\i2/blk00000001/sig0000015b/G ),
.O(\i2/blk00000001/sig0000015b/XORG_5142 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/COUTUSED (
.I(\i2/blk00000001/sig0000015b/CYMUXFAST_5139 ),
.O(\i2/blk00000001/sig000001b5 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/FASTCARRY (
.I(\i2/blk00000001/sig000001c1 ),
.O(\i2/blk00000001/sig0000015b/FASTCARRY_5137 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYAND (
.I0(\i2/blk00000001/sig0000015b/CYSELG_5125 ),
.I1(\i2/blk00000001/sig0000015b/CYSELF_5140 ),
.O(\i2/blk00000001/sig0000015b/CYAND_5138 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYMUXFAST (
.IA(\i2/blk00000001/sig0000015b/CYMUXG2_5136 ),
.IB(\i2/blk00000001/sig0000015b/FASTCARRY_5137 ),
.SEL(\i2/blk00000001/sig0000015b/CYAND_5138 ),
.O(\i2/blk00000001/sig0000015b/CYMUXFAST_5139 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYMUXG2 (
.IA(\i2/blk00000001/sig0000015b/CY0G_5134 ),
.IB(\i2/blk00000001/sig0000015b/CYMUXF2_5135 ),
.SEL(\i2/blk00000001/sig0000015b/CYSELG_5125 ),
.O(\i2/blk00000001/sig0000015b/CYMUXG2_5136 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CY0G (
.I(\i2/blk00000001/sig00000208 ),
.O(\i2/blk00000001/sig0000015b/CY0G_5134 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000015b/GAND/IN1 ),
.O(\i2/blk00000001/sig00000208 )
);
X_BUF #(
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/CYSELG (
.I(\i2/blk00000001/sig0000015b/G ),
.O(\i2/blk00000001/sig0000015b/CYSELG_5125 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/XUSED (
.I(\i2/blk00000001/sig00000145/XORF_5196 ),
.O(\i2/blk00000001/sig00000145 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/XORF (
.I0(\i2/blk00000001/sig00000145/CYINIT_5195 ),
.I1(\i2/blk00000001/sig00000145/F ),
.O(\i2/blk00000001/sig00000145/XORF_5196 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYMUXF (
.IA(\i2/blk00000001/sig00000145/CY0F_5194 ),
.IB(\i2/blk00000001/sig00000145/CYINIT_5195 ),
.SEL(\i2/blk00000001/sig00000145/CYSELF_5182 ),
.O(\i2/blk00000001/sig000001af )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYMUXF2 (
.IA(\i2/blk00000001/sig00000145/CY0F_5194 ),
.IB(\i2/blk00000001/sig00000145/CY0F_5194 ),
.SEL(\i2/blk00000001/sig00000145/CYSELF_5182 ),
.O(\i2/blk00000001/sig00000145/CYMUXF2_5177 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYINIT (
.I(\i2/blk00000001/sig000001b5 ),
.O(\i2/blk00000001/sig00000145/CYINIT_5195 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CY0F (
.I(\i2/blk00000001/sig00000202 ),
.O(\i2/blk00000001/sig00000145/CY0F_5194 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000145/FAND/IN1 ),
.O(\i2/blk00000001/sig00000202 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYSELF (
.I(\i2/blk00000001/sig00000145/F ),
.O(\i2/blk00000001/sig00000145/CYSELF_5182 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/YUSED (
.I(\i2/blk00000001/sig00000145/XORG_5184 ),
.O(\i2/blk00000001/sig0000013a )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/XORG (
.I0(\i2/blk00000001/sig000001af ),
.I1(\i2/blk00000001/sig00000145/G ),
.O(\i2/blk00000001/sig00000145/XORG_5184 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/COUTUSED (
.I(\i2/blk00000001/sig00000145/CYMUXFAST_5181 ),
.O(\i2/blk00000001/sig000001a9 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/FASTCARRY (
.I(\i2/blk00000001/sig000001b5 ),
.O(\i2/blk00000001/sig00000145/FASTCARRY_5179 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYAND (
.I0(\i2/blk00000001/sig00000145/CYSELG_5167 ),
.I1(\i2/blk00000001/sig00000145/CYSELF_5182 ),
.O(\i2/blk00000001/sig00000145/CYAND_5180 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYMUXFAST (
.IA(\i2/blk00000001/sig00000145/CYMUXG2_5178 ),
.IB(\i2/blk00000001/sig00000145/FASTCARRY_5179 ),
.SEL(\i2/blk00000001/sig00000145/CYAND_5180 ),
.O(\i2/blk00000001/sig00000145/CYMUXFAST_5181 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYMUXG2 (
.IA(\i2/blk00000001/sig00000145/CY0G_5176 ),
.IB(\i2/blk00000001/sig00000145/CYMUXF2_5177 ),
.SEL(\i2/blk00000001/sig00000145/CYSELG_5167 ),
.O(\i2/blk00000001/sig00000145/CYMUXG2_5178 )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CY0G (
.I(\i2/blk00000001/sig000001fc ),
.O(\i2/blk00000001/sig00000145/CY0G_5176 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000145/GAND/IN1 ),
.O(\i2/blk00000001/sig000001fc )
);
X_BUF #(
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/CYSELG (
.I(\i2/blk00000001/sig00000145/G ),
.O(\i2/blk00000001/sig00000145/CYSELG_5167 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/XUSED (
.I(\i2/blk00000001/sig0000012f/XORF_5237 ),
.O(\i2/blk00000001/sig0000012f )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/XORF (
.I0(\i2/blk00000001/sig0000012f/CYINIT_5236 ),
.I1(\i2/blk00000001/sig0000012f/F ),
.O(\i2/blk00000001/sig0000012f/XORF_5237 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYMUXF (
.IA(\i2/blk00000001/sig0000012f/CY0F_5235 ),
.IB(\i2/blk00000001/sig0000012f/CYINIT_5236 ),
.SEL(\i2/blk00000001/sig0000012f/CYSELF_5223 ),
.O(\i2/blk00000001/sig000001a3 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYMUXF2 (
.IA(\i2/blk00000001/sig0000012f/CY0F_5235 ),
.IB(\i2/blk00000001/sig0000012f/CY0F_5235 ),
.SEL(\i2/blk00000001/sig0000012f/CYSELF_5223 ),
.O(\i2/blk00000001/sig0000012f/CYMUXF2_5218 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYINIT (
.I(\i2/blk00000001/sig000001a9 ),
.O(\i2/blk00000001/sig0000012f/CYINIT_5236 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CY0F (
.I(\i2/blk00000001/sig000001f6 ),
.O(\i2/blk00000001/sig0000012f/CY0F_5235 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000012f/FAND/IN1 ),
.O(\i2/blk00000001/sig000001f6 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYSELF (
.I(\i2/blk00000001/sig0000012f/F ),
.O(\i2/blk00000001/sig0000012f/CYSELF_5223 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/YUSED (
.I(\i2/blk00000001/sig0000012f/XORG_5225 ),
.O(\i2/blk00000001/sig00000124 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/XORG (
.I0(\i2/blk00000001/sig000001a3 ),
.I1(\i2/blk00000001/sig0000012f/G ),
.O(\i2/blk00000001/sig0000012f/XORG_5225 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/FASTCARRY (
.I(\i2/blk00000001/sig000001a9 ),
.O(\i2/blk00000001/sig0000012f/FASTCARRY_5220 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYAND (
.I0(\i2/blk00000001/sig0000012f/CYSELG_5208 ),
.I1(\i2/blk00000001/sig0000012f/CYSELF_5223 ),
.O(\i2/blk00000001/sig0000012f/CYAND_5221 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYMUXFAST (
.IA(\i2/blk00000001/sig0000012f/CYMUXG2_5219 ),
.IB(\i2/blk00000001/sig0000012f/FASTCARRY_5220 ),
.SEL(\i2/blk00000001/sig0000012f/CYAND_5221 ),
.O(\i2/blk00000001/sig0000012f/CYMUXFAST_5222 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYMUXG2 (
.IA(\i2/blk00000001/sig0000012f/CY0G_5217 ),
.IB(\i2/blk00000001/sig0000012f/CYMUXF2_5218 ),
.SEL(\i2/blk00000001/sig0000012f/CYSELG_5208 ),
.O(\i2/blk00000001/sig0000012f/CYMUXG2_5219 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CY0G (
.I(\i2/blk00000001/sig000001f0 ),
.O(\i2/blk00000001/sig0000012f/CY0G_5217 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000012f/GAND/IN1 ),
.O(\i2/blk00000001/sig000001f0 )
);
X_BUF #(
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/CYSELG (
.I(\i2/blk00000001/sig0000012f/G ),
.O(\i2/blk00000001/sig0000012f/CYSELG_5208 )
);
X_BUF #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/XUSED (
.I(\i2/blk00000001/sig00000119/XORF_5269 ),
.O(\i2/blk00000001/sig00000119 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/XORF (
.I0(\i2/blk00000001/sig00000119/CYINIT_5268 ),
.I1(\i2/blk00000001/sig00000119/F ),
.O(\i2/blk00000001/sig00000119/XORF_5269 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/CYMUXF (
.IA(\i2/blk00000001/sig00000119/CY0F_5267 ),
.IB(\i2/blk00000001/sig00000119/CYINIT_5268 ),
.SEL(\i2/blk00000001/sig00000119/CYSELF_5258 ),
.O(\i2/blk00000001/sig00000197 )
);
X_BUF #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/CYINIT (
.I(\i2/blk00000001/sig0000012f/CYMUXFAST_5222 ),
.O(\i2/blk00000001/sig00000119/CYINIT_5268 )
);
X_BUF #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/CY0F (
.I(\i2/blk00000001/sig000001ea ),
.O(\i2/blk00000001/sig00000119/CY0F_5267 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000119/FAND/IN1 ),
.O(\i2/blk00000001/sig000001ea )
);
X_BUF #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/CYSELF (
.I(\i2/blk00000001/sig00000119/F ),
.O(\i2/blk00000001/sig00000119/CYSELF_5258 )
);
X_BUF #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/YUSED (
.I(\i2/blk00000001/sig00000119/XORG_5255 ),
.O(\i2/blk00000001/sig0000010e )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/XORG (
.I0(\i2/blk00000001/sig00000197 ),
.I1(\i2/blk00000001/sig00000119/G ),
.O(\i2/blk00000001/sig00000119/XORG_5255 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CYMUXF (
.IA(\i2/blk00000001/sig000001e5/CY0F_5301 ),
.IB(\i2/blk00000001/sig000001e5/CYINIT_5302 ),
.SEL(\i2/blk00000001/sig000001e5/CYSELF_5292 ),
.O(\i2/blk00000001/sig000001e6 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CYINIT (
.I(\i2/blk00000001/sig000001e5/BXINV_5290 ),
.O(\i2/blk00000001/sig000001e5/CYINIT_5302 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CY0F (
.I(\i2/blk00000001/sig00000238 ),
.O(\i2/blk00000001/sig000001e5/CY0F_5301 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000238 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CYSELF (
.I(\i2/blk00000001/sig000001e5/F ),
.O(\i2/blk00000001/sig000001e5/CYSELF_5292 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000001e5/BXINV_5290 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/COUTUSED (
.I(\i2/blk00000001/sig000001e5/CYMUXG_5289 ),
.O(\i2/blk00000001/sig000001e5 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CYMUXG (
.IA(\i2/blk00000001/sig000001e5/CY0G_5287 ),
.IB(\i2/blk00000001/sig000001e6 ),
.SEL(\i2/blk00000001/sig000001e5/CYSELG_5278 ),
.O(\i2/blk00000001/sig000001e5/CYMUXG_5289 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CY0G (
.I(\i2/blk00000001/sig00000237 ),
.O(\i2/blk00000001/sig000001e5/CY0G_5287 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000237 )
);
X_BUF #(
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/CYSELG (
.I(\i2/blk00000001/sig000001e5/G ),
.O(\i2/blk00000001/sig000001e5/CYSELG_5278 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/XUSED (
.I(\i2/blk00000001/sig00000192/XORF_5342 ),
.O(\i2/blk00000001/sig00000192 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/XORF (
.I0(\i2/blk00000001/sig00000192/CYINIT_5341 ),
.I1(\i2/blk00000001/sig00000192/F ),
.O(\i2/blk00000001/sig00000192/XORF_5342 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYMUXF (
.IA(\i2/blk00000001/sig00000192/CY0F_5340 ),
.IB(\i2/blk00000001/sig00000192/CYINIT_5341 ),
.SEL(\i2/blk00000001/sig00000192/CYSELF_5327 ),
.O(\i2/blk00000001/sig000001d6 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYMUXF2 (
.IA(\i2/blk00000001/sig00000192/CY0F_5340 ),
.IB(\i2/blk00000001/sig00000192/CY0F_5340 ),
.SEL(\i2/blk00000001/sig00000192/CYSELF_5327 ),
.O(\i2/blk00000001/sig00000192/CYMUXF2_5322 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYINIT (
.I(\i2/blk00000001/sig000001e5 ),
.O(\i2/blk00000001/sig00000192/CYINIT_5341 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CY0F (
.I(\i2/blk00000001/sig00000229 ),
.O(\i2/blk00000001/sig00000192/CY0F_5340 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000229 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYSELF (
.I(\i2/blk00000001/sig00000192/F ),
.O(\i2/blk00000001/sig00000192/CYSELF_5327 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/YUSED (
.I(\i2/blk00000001/sig00000192/XORG_5329 ),
.O(\i2/blk00000001/sig00000182 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/XORG (
.I0(\i2/blk00000001/sig000001d6 ),
.I1(\i2/blk00000001/sig00000192/G ),
.O(\i2/blk00000001/sig00000192/XORG_5329 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/COUTUSED (
.I(\i2/blk00000001/sig00000192/CYMUXFAST_5326 ),
.O(\i2/blk00000001/sig000001d0 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/FASTCARRY (
.I(\i2/blk00000001/sig000001e5 ),
.O(\i2/blk00000001/sig00000192/FASTCARRY_5324 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYAND (
.I0(\i2/blk00000001/sig00000192/CYSELG_5312 ),
.I1(\i2/blk00000001/sig00000192/CYSELF_5327 ),
.O(\i2/blk00000001/sig00000192/CYAND_5325 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYMUXFAST (
.IA(\i2/blk00000001/sig00000192/CYMUXG2_5323 ),
.IB(\i2/blk00000001/sig00000192/FASTCARRY_5324 ),
.SEL(\i2/blk00000001/sig00000192/CYAND_5325 ),
.O(\i2/blk00000001/sig00000192/CYMUXFAST_5326 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYMUXG2 (
.IA(\i2/blk00000001/sig00000192/CY0G_5321 ),
.IB(\i2/blk00000001/sig00000192/CYMUXF2_5322 ),
.SEL(\i2/blk00000001/sig00000192/CYSELG_5312 ),
.O(\i2/blk00000001/sig00000192/CYMUXG2_5323 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CY0G (
.I(\i2/blk00000001/sig00000223 ),
.O(\i2/blk00000001/sig00000192/CY0G_5321 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000223 )
);
X_BUF #(
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/CYSELG (
.I(\i2/blk00000001/sig00000192/G ),
.O(\i2/blk00000001/sig00000192/CYSELG_5312 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/XUSED (
.I(\i2/blk00000001/sig00000177/XORF_5383 ),
.O(\i2/blk00000001/sig00000177 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/XORF (
.I0(\i2/blk00000001/sig00000177/CYINIT_5382 ),
.I1(\i2/blk00000001/sig00000177/F ),
.O(\i2/blk00000001/sig00000177/XORF_5383 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYMUXF (
.IA(\i2/blk00000001/sig00000177/CY0F_5381 ),
.IB(\i2/blk00000001/sig00000177/CYINIT_5382 ),
.SEL(\i2/blk00000001/sig00000177/CYSELF_5368 ),
.O(\i2/blk00000001/sig000001ca )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYMUXF2 (
.IA(\i2/blk00000001/sig00000177/CY0F_5381 ),
.IB(\i2/blk00000001/sig00000177/CY0F_5381 ),
.SEL(\i2/blk00000001/sig00000177/CYSELF_5368 ),
.O(\i2/blk00000001/sig00000177/CYMUXF2_5363 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYINIT (
.I(\i2/blk00000001/sig000001d0 ),
.O(\i2/blk00000001/sig00000177/CYINIT_5382 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CY0F (
.I(\i2/blk00000001/sig0000021d ),
.O(\i2/blk00000001/sig00000177/CY0F_5381 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig0000021d )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYSELF (
.I(\i2/blk00000001/sig00000177/F ),
.O(\i2/blk00000001/sig00000177/CYSELF_5368 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/YUSED (
.I(\i2/blk00000001/sig00000177/XORG_5370 ),
.O(\i2/blk00000001/sig0000016c )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/XORG (
.I0(\i2/blk00000001/sig000001ca ),
.I1(\i2/blk00000001/sig00000177/G ),
.O(\i2/blk00000001/sig00000177/XORG_5370 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/COUTUSED (
.I(\i2/blk00000001/sig00000177/CYMUXFAST_5367 ),
.O(\i2/blk00000001/sig000001c4 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/FASTCARRY (
.I(\i2/blk00000001/sig000001d0 ),
.O(\i2/blk00000001/sig00000177/FASTCARRY_5365 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYAND (
.I0(\i2/blk00000001/sig00000177/CYSELG_5353 ),
.I1(\i2/blk00000001/sig00000177/CYSELF_5368 ),
.O(\i2/blk00000001/sig00000177/CYAND_5366 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYMUXFAST (
.IA(\i2/blk00000001/sig00000177/CYMUXG2_5364 ),
.IB(\i2/blk00000001/sig00000177/FASTCARRY_5365 ),
.SEL(\i2/blk00000001/sig00000177/CYAND_5366 ),
.O(\i2/blk00000001/sig00000177/CYMUXFAST_5367 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYMUXG2 (
.IA(\i2/blk00000001/sig00000177/CY0G_5362 ),
.IB(\i2/blk00000001/sig00000177/CYMUXF2_5363 ),
.SEL(\i2/blk00000001/sig00000177/CYSELG_5353 ),
.O(\i2/blk00000001/sig00000177/CYMUXG2_5364 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CY0G (
.I(\i2/blk00000001/sig00000217 ),
.O(\i2/blk00000001/sig00000177/CY0G_5362 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000217 )
);
X_BUF #(
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/CYSELG (
.I(\i2/blk00000001/sig00000177/G ),
.O(\i2/blk00000001/sig00000177/CYSELG_5353 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/XUSED (
.I(\i2/blk00000001/sig00000161/XORF_5424 ),
.O(\i2/blk00000001/sig00000161 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/XORF (
.I0(\i2/blk00000001/sig00000161/CYINIT_5423 ),
.I1(\i2/blk00000001/sig00000161/F ),
.O(\i2/blk00000001/sig00000161/XORF_5424 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYMUXF (
.IA(\i2/blk00000001/sig00000161/CY0F_5422 ),
.IB(\i2/blk00000001/sig00000161/CYINIT_5423 ),
.SEL(\i2/blk00000001/sig00000161/CYSELF_5409 ),
.O(\i2/blk00000001/sig000001be )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYMUXF2 (
.IA(\i2/blk00000001/sig00000161/CY0F_5422 ),
.IB(\i2/blk00000001/sig00000161/CY0F_5422 ),
.SEL(\i2/blk00000001/sig00000161/CYSELF_5409 ),
.O(\i2/blk00000001/sig00000161/CYMUXF2_5404 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYINIT (
.I(\i2/blk00000001/sig000001c4 ),
.O(\i2/blk00000001/sig00000161/CYINIT_5423 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CY0F (
.I(\i2/blk00000001/sig00000211 ),
.O(\i2/blk00000001/sig00000161/CY0F_5422 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000211 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYSELF (
.I(\i2/blk00000001/sig00000161/F ),
.O(\i2/blk00000001/sig00000161/CYSELF_5409 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/YUSED (
.I(\i2/blk00000001/sig00000161/XORG_5411 ),
.O(\i2/blk00000001/sig00000156 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/XORG (
.I0(\i2/blk00000001/sig000001be ),
.I1(\i2/blk00000001/sig00000161/G ),
.O(\i2/blk00000001/sig00000161/XORG_5411 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/COUTUSED (
.I(\i2/blk00000001/sig00000161/CYMUXFAST_5408 ),
.O(\i2/blk00000001/sig000001b8 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/FASTCARRY (
.I(\i2/blk00000001/sig000001c4 ),
.O(\i2/blk00000001/sig00000161/FASTCARRY_5406 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYAND (
.I0(\i2/blk00000001/sig00000161/CYSELG_5394 ),
.I1(\i2/blk00000001/sig00000161/CYSELF_5409 ),
.O(\i2/blk00000001/sig00000161/CYAND_5407 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYMUXFAST (
.IA(\i2/blk00000001/sig00000161/CYMUXG2_5405 ),
.IB(\i2/blk00000001/sig00000161/FASTCARRY_5406 ),
.SEL(\i2/blk00000001/sig00000161/CYAND_5407 ),
.O(\i2/blk00000001/sig00000161/CYMUXFAST_5408 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYMUXG2 (
.IA(\i2/blk00000001/sig00000161/CY0G_5403 ),
.IB(\i2/blk00000001/sig00000161/CYMUXF2_5404 ),
.SEL(\i2/blk00000001/sig00000161/CYSELG_5394 ),
.O(\i2/blk00000001/sig00000161/CYMUXG2_5405 )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CY0G (
.I(\i2/blk00000001/sig0000020b ),
.O(\i2/blk00000001/sig00000161/CY0G_5403 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig0000020b )
);
X_BUF #(
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/CYSELG (
.I(\i2/blk00000001/sig00000161/G ),
.O(\i2/blk00000001/sig00000161/CYSELG_5394 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/XUSED (
.I(\i2/blk00000001/sig0000014b/XORF_5465 ),
.O(\i2/blk00000001/sig0000014b )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/XORF (
.I0(\i2/blk00000001/sig0000014b/CYINIT_5464 ),
.I1(\i2/blk00000001/sig0000014b/F ),
.O(\i2/blk00000001/sig0000014b/XORF_5465 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYMUXF (
.IA(\i2/blk00000001/sig0000014b/CY0F_5463 ),
.IB(\i2/blk00000001/sig0000014b/CYINIT_5464 ),
.SEL(\i2/blk00000001/sig0000014b/CYSELF_5450 ),
.O(\i2/blk00000001/sig000001b2 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYMUXF2 (
.IA(\i2/blk00000001/sig0000014b/CY0F_5463 ),
.IB(\i2/blk00000001/sig0000014b/CY0F_5463 ),
.SEL(\i2/blk00000001/sig0000014b/CYSELF_5450 ),
.O(\i2/blk00000001/sig0000014b/CYMUXF2_5445 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYINIT (
.I(\i2/blk00000001/sig000001b8 ),
.O(\i2/blk00000001/sig0000014b/CYINIT_5464 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CY0F (
.I(\i2/blk00000001/sig00000205 ),
.O(\i2/blk00000001/sig0000014b/CY0F_5463 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig00000205 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYSELF (
.I(\i2/blk00000001/sig0000014b/F ),
.O(\i2/blk00000001/sig0000014b/CYSELF_5450 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/YUSED (
.I(\i2/blk00000001/sig0000014b/XORG_5452 ),
.O(\i2/blk00000001/sig00000140 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/XORG (
.I0(\i2/blk00000001/sig000001b2 ),
.I1(\i2/blk00000001/sig0000014b/G ),
.O(\i2/blk00000001/sig0000014b/XORG_5452 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/COUTUSED (
.I(\i2/blk00000001/sig0000014b/CYMUXFAST_5449 ),
.O(\i2/blk00000001/sig000001ac )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/FASTCARRY (
.I(\i2/blk00000001/sig000001b8 ),
.O(\i2/blk00000001/sig0000014b/FASTCARRY_5447 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYAND (
.I0(\i2/blk00000001/sig0000014b/CYSELG_5435 ),
.I1(\i2/blk00000001/sig0000014b/CYSELF_5450 ),
.O(\i2/blk00000001/sig0000014b/CYAND_5448 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYMUXFAST (
.IA(\i2/blk00000001/sig0000014b/CYMUXG2_5446 ),
.IB(\i2/blk00000001/sig0000014b/FASTCARRY_5447 ),
.SEL(\i2/blk00000001/sig0000014b/CYAND_5448 ),
.O(\i2/blk00000001/sig0000014b/CYMUXFAST_5449 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYMUXG2 (
.IA(\i2/blk00000001/sig0000014b/CY0G_5444 ),
.IB(\i2/blk00000001/sig0000014b/CYMUXF2_5445 ),
.SEL(\i2/blk00000001/sig0000014b/CYSELG_5435 ),
.O(\i2/blk00000001/sig0000014b/CYMUXG2_5446 )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CY0G (
.I(\i2/blk00000001/sig000001ff ),
.O(\i2/blk00000001/sig0000014b/CY0G_5444 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/GAND (
.I0(1'b1),
.I1(1'b0),
.O(\i2/blk00000001/sig000001ff )
);
X_BUF #(
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/CYSELG (
.I(\i2/blk00000001/sig0000014b/G ),
.O(\i2/blk00000001/sig0000014b/CYSELG_5435 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/XUSED (
.I(\i2/blk00000001/sig00000135/XORF_5506 ),
.O(\i2/blk00000001/sig00000135 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/XORF (
.I0(\i2/blk00000001/sig00000135/CYINIT_5505 ),
.I1(\i2/blk00000001/sig00000135/F ),
.O(\i2/blk00000001/sig00000135/XORF_5506 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYMUXF (
.IA(\i2/blk00000001/sig00000135/CY0F_5504 ),
.IB(\i2/blk00000001/sig00000135/CYINIT_5505 ),
.SEL(\i2/blk00000001/sig00000135/CYSELF_5491 ),
.O(\i2/blk00000001/sig000001a6 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYMUXF2 (
.IA(\i2/blk00000001/sig00000135/CY0F_5504 ),
.IB(\i2/blk00000001/sig00000135/CY0F_5504 ),
.SEL(\i2/blk00000001/sig00000135/CYSELF_5491 ),
.O(\i2/blk00000001/sig00000135/CYMUXF2_5486 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYINIT (
.I(\i2/blk00000001/sig000001ac ),
.O(\i2/blk00000001/sig00000135/CYINIT_5505 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CY0F (
.I(\i2/blk00000001/sig000001f9 ),
.O(\i2/blk00000001/sig00000135/CY0F_5504 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig000001f9 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYSELF (
.I(\i2/blk00000001/sig00000135/F ),
.O(\i2/blk00000001/sig00000135/CYSELF_5491 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/YUSED (
.I(\i2/blk00000001/sig00000135/XORG_5493 ),
.O(\i2/blk00000001/sig0000012a )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/XORG (
.I0(\i2/blk00000001/sig000001a6 ),
.I1(\i2/blk00000001/sig00000135/G ),
.O(\i2/blk00000001/sig00000135/XORG_5493 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/FASTCARRY (
.I(\i2/blk00000001/sig000001ac ),
.O(\i2/blk00000001/sig00000135/FASTCARRY_5488 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYAND (
.I0(\i2/blk00000001/sig00000135/CYSELG_5476 ),
.I1(\i2/blk00000001/sig00000135/CYSELF_5491 ),
.O(\i2/blk00000001/sig00000135/CYAND_5489 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYMUXFAST (
.IA(\i2/blk00000001/sig00000135/CYMUXG2_5487 ),
.IB(\i2/blk00000001/sig00000135/FASTCARRY_5488 ),
.SEL(\i2/blk00000001/sig00000135/CYAND_5489 ),
.O(\i2/blk00000001/sig00000135/CYMUXFAST_5490 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYMUXG2 (
.IA(\i2/blk00000001/sig00000135/CY0G_5485 ),
.IB(\i2/blk00000001/sig00000135/CYMUXF2_5486 ),
.SEL(\i2/blk00000001/sig00000135/CYSELG_5476 ),
.O(\i2/blk00000001/sig00000135/CYMUXG2_5487 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CY0G (
.I(\i2/blk00000001/sig000001f3 ),
.O(\i2/blk00000001/sig00000135/CY0G_5485 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/GAND (
.I0(1'b1),
.I1(1'b0),
.O(\i2/blk00000001/sig000001f3 )
);
X_BUF #(
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/CYSELG (
.I(\i2/blk00000001/sig00000135/G ),
.O(\i2/blk00000001/sig00000135/CYSELG_5476 )
);
X_BUF #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/XUSED (
.I(\i2/blk00000001/sig0000011f/XORF_5538 ),
.O(\i2/blk00000001/sig0000011f )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/XORF (
.I0(\i2/blk00000001/sig0000011f/CYINIT_5537 ),
.I1(\i2/blk00000001/sig0000011f/F ),
.O(\i2/blk00000001/sig0000011f/XORF_5538 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/CYMUXF (
.IA(\i2/blk00000001/sig0000011f/CY0F_5536 ),
.IB(\i2/blk00000001/sig0000011f/CYINIT_5537 ),
.SEL(\i2/blk00000001/sig0000011f/CYSELF_5527 ),
.O(\i2/blk00000001/sig0000019a )
);
X_BUF #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/CYINIT (
.I(\i2/blk00000001/sig00000135/CYMUXFAST_5490 ),
.O(\i2/blk00000001/sig0000011f/CYINIT_5537 )
);
X_BUF #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/CY0F (
.I(\i2/blk00000001/sig000001ed ),
.O(\i2/blk00000001/sig0000011f/CY0F_5536 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i2/blk00000001/sig000001ed )
);
X_BUF #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/CYSELF (
.I(\i2/blk00000001/sig0000011f/F ),
.O(\i2/blk00000001/sig0000011f/CYSELF_5527 )
);
X_BUF #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/YUSED (
.I(\i2/blk00000001/sig0000011f/XORG_5524 ),
.O(\i2/blk00000001/sig00000114 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/XORG (
.I0(\i2/blk00000001/sig0000019a ),
.I1(\i2/blk00000001/sig0000011f/G ),
.O(\i2/blk00000001/sig0000011f/XORG_5524 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/XUSED (
.I(\i2/blk00000001/sig000001e0/XORF_5576 ),
.O(\i2/blk00000001/sig000001e0 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/XORF (
.I0(\i2/blk00000001/sig000001e0/CYINIT_5575 ),
.I1(\i2/blk00000001/sig000001e0/F ),
.O(\i2/blk00000001/sig000001e0/XORF_5576 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CYMUXF (
.IA(\i2/blk00000001/sig000001e0/CY0F_5574 ),
.IB(\i2/blk00000001/sig000001e0/CYINIT_5575 ),
.SEL(\i2/blk00000001/sig000001e0/CYSELF_5565 ),
.O(\i2/blk00000001/sig000001e1 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CYINIT (
.I(\i2/blk00000001/sig000001e0/BXINV_5563 ),
.O(\i2/blk00000001/sig000001e0/CYINIT_5575 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CY0F (
.I(\i2/blk00000001/sig00000232 ),
.O(\i2/blk00000001/sig000001e0/CY0F_5574 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/FAND (
.I0(x2_2_IBUF_3138),
.I1(1'b0),
.O(\i2/blk00000001/sig00000232 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CYSELF (
.I(\i2/blk00000001/sig000001e0/F ),
.O(\i2/blk00000001/sig000001e0/CYSELF_5565 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000001e0/BXINV_5563 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/YUSED (
.I(\i2/blk00000001/sig000001e0/XORG_5561 ),
.O(\i2/blk00000001/sig0000018e )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/XORG (
.I0(\i2/blk00000001/sig000001e1 ),
.I1(\i2/blk00000001/sig000001e0/G ),
.O(\i2/blk00000001/sig000001e0/XORG_5561 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/COUTUSED (
.I(\i2/blk00000001/sig000001e0/CYMUXG_5560 ),
.O(\i2/blk00000001/sig000001df )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CYMUXG (
.IA(\i2/blk00000001/sig000001e0/CY0G_5558 ),
.IB(\i2/blk00000001/sig000001e1 ),
.SEL(\i2/blk00000001/sig000001e0/CYSELG_5549 ),
.O(\i2/blk00000001/sig000001e0/CYMUXG_5560 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CY0G (
.I(\i2/blk00000001/sig00000231 ),
.O(\i2/blk00000001/sig000001e0/CY0G_5558 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/GAND (
.I0(\NlwBufferSignal_i2/blk00000001/sig000001e0/GAND/IN0 ),
.I1(1'b0),
.O(\i2/blk00000001/sig00000231 )
);
X_BUF #(
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/CYSELG (
.I(\i2/blk00000001/sig000001e0/G ),
.O(\i2/blk00000001/sig000001e0/CYSELG_5549 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/XUSED (
.I(\i2/blk00000001/sig0000018c/XORF_5617 ),
.O(\i2/blk00000001/sig0000018c )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/XORF (
.I0(\i2/blk00000001/sig0000018c/CYINIT_5616 ),
.I1(\i2/blk00000001/sig0000018c/F ),
.O(\i2/blk00000001/sig0000018c/XORF_5617 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYMUXF (
.IA(\i2/blk00000001/sig0000018c/CY0F_5615 ),
.IB(\i2/blk00000001/sig0000018c/CYINIT_5616 ),
.SEL(\i2/blk00000001/sig0000018c/CYSELF_5602 ),
.O(\i2/blk00000001/sig000001d4 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYMUXF2 (
.IA(\i2/blk00000001/sig0000018c/CY0F_5615 ),
.IB(\i2/blk00000001/sig0000018c/CY0F_5615 ),
.SEL(\i2/blk00000001/sig0000018c/CYSELF_5602 ),
.O(\i2/blk00000001/sig0000018c/CYMUXF2_5597 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYINIT (
.I(\i2/blk00000001/sig000001df ),
.O(\i2/blk00000001/sig0000018c/CYINIT_5616 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CY0F (
.I(\i2/blk00000001/sig00000227 ),
.O(\i2/blk00000001/sig0000018c/CY0F_5615 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000018c/FAND/IN1 ),
.O(\i2/blk00000001/sig00000227 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYSELF (
.I(\i2/blk00000001/sig0000018c/F ),
.O(\i2/blk00000001/sig0000018c/CYSELF_5602 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/YUSED (
.I(\i2/blk00000001/sig0000018c/XORG_5604 ),
.O(\i2/blk00000001/sig0000017e )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/XORG (
.I0(\i2/blk00000001/sig000001d4 ),
.I1(\i2/blk00000001/sig0000018c/G ),
.O(\i2/blk00000001/sig0000018c/XORG_5604 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/COUTUSED (
.I(\i2/blk00000001/sig0000018c/CYMUXFAST_5601 ),
.O(\i2/blk00000001/sig000001ce )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/FASTCARRY (
.I(\i2/blk00000001/sig000001df ),
.O(\i2/blk00000001/sig0000018c/FASTCARRY_5599 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYAND (
.I0(\i2/blk00000001/sig0000018c/CYSELG_5587 ),
.I1(\i2/blk00000001/sig0000018c/CYSELF_5602 ),
.O(\i2/blk00000001/sig0000018c/CYAND_5600 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYMUXFAST (
.IA(\i2/blk00000001/sig0000018c/CYMUXG2_5598 ),
.IB(\i2/blk00000001/sig0000018c/FASTCARRY_5599 ),
.SEL(\i2/blk00000001/sig0000018c/CYAND_5600 ),
.O(\i2/blk00000001/sig0000018c/CYMUXFAST_5601 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYMUXG2 (
.IA(\i2/blk00000001/sig0000018c/CY0G_5596 ),
.IB(\i2/blk00000001/sig0000018c/CYMUXF2_5597 ),
.SEL(\i2/blk00000001/sig0000018c/CYSELG_5587 ),
.O(\i2/blk00000001/sig0000018c/CYMUXG2_5598 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CY0G (
.I(\i2/blk00000001/sig00000221 ),
.O(\i2/blk00000001/sig0000018c/CY0G_5596 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000018c/GAND/IN1 ),
.O(\i2/blk00000001/sig00000221 )
);
X_BUF #(
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/CYSELG (
.I(\i2/blk00000001/sig0000018c/G ),
.O(\i2/blk00000001/sig0000018c/CYSELG_5587 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/XUSED (
.I(\i2/blk00000001/sig00000173/XORF_5658 ),
.O(\i2/blk00000001/sig00000173 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/XORF (
.I0(\i2/blk00000001/sig00000173/CYINIT_5657 ),
.I1(\i2/blk00000001/sig00000173/F ),
.O(\i2/blk00000001/sig00000173/XORF_5658 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYMUXF (
.IA(\i2/blk00000001/sig00000173/CY0F_5656 ),
.IB(\i2/blk00000001/sig00000173/CYINIT_5657 ),
.SEL(\i2/blk00000001/sig00000173/CYSELF_5643 ),
.O(\i2/blk00000001/sig000001c8 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYMUXF2 (
.IA(\i2/blk00000001/sig00000173/CY0F_5656 ),
.IB(\i2/blk00000001/sig00000173/CY0F_5656 ),
.SEL(\i2/blk00000001/sig00000173/CYSELF_5643 ),
.O(\i2/blk00000001/sig00000173/CYMUXF2_5638 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYINIT (
.I(\i2/blk00000001/sig000001ce ),
.O(\i2/blk00000001/sig00000173/CYINIT_5657 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CY0F (
.I(\i2/blk00000001/sig0000021b ),
.O(\i2/blk00000001/sig00000173/CY0F_5656 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000173/FAND/IN1 ),
.O(\i2/blk00000001/sig0000021b )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYSELF (
.I(\i2/blk00000001/sig00000173/F ),
.O(\i2/blk00000001/sig00000173/CYSELF_5643 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/YUSED (
.I(\i2/blk00000001/sig00000173/XORG_5645 ),
.O(\i2/blk00000001/sig00000168 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/XORG (
.I0(\i2/blk00000001/sig000001c8 ),
.I1(\i2/blk00000001/sig00000173/G ),
.O(\i2/blk00000001/sig00000173/XORG_5645 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/COUTUSED (
.I(\i2/blk00000001/sig00000173/CYMUXFAST_5642 ),
.O(\i2/blk00000001/sig000001c2 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/FASTCARRY (
.I(\i2/blk00000001/sig000001ce ),
.O(\i2/blk00000001/sig00000173/FASTCARRY_5640 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYAND (
.I0(\i2/blk00000001/sig00000173/CYSELG_5628 ),
.I1(\i2/blk00000001/sig00000173/CYSELF_5643 ),
.O(\i2/blk00000001/sig00000173/CYAND_5641 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYMUXFAST (
.IA(\i2/blk00000001/sig00000173/CYMUXG2_5639 ),
.IB(\i2/blk00000001/sig00000173/FASTCARRY_5640 ),
.SEL(\i2/blk00000001/sig00000173/CYAND_5641 ),
.O(\i2/blk00000001/sig00000173/CYMUXFAST_5642 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYMUXG2 (
.IA(\i2/blk00000001/sig00000173/CY0G_5637 ),
.IB(\i2/blk00000001/sig00000173/CYMUXF2_5638 ),
.SEL(\i2/blk00000001/sig00000173/CYSELG_5628 ),
.O(\i2/blk00000001/sig00000173/CYMUXG2_5639 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CY0G (
.I(\i2/blk00000001/sig00000215 ),
.O(\i2/blk00000001/sig00000173/CY0G_5637 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000173/GAND/IN1 ),
.O(\i2/blk00000001/sig00000215 )
);
X_BUF #(
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/CYSELG (
.I(\i2/blk00000001/sig00000173/G ),
.O(\i2/blk00000001/sig00000173/CYSELG_5628 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/XUSED (
.I(\i2/blk00000001/sig0000015d/XORF_5699 ),
.O(\i2/blk00000001/sig0000015d )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/XORF (
.I0(\i2/blk00000001/sig0000015d/CYINIT_5698 ),
.I1(\i2/blk00000001/sig0000015d/F ),
.O(\i2/blk00000001/sig0000015d/XORF_5699 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYMUXF (
.IA(\i2/blk00000001/sig0000015d/CY0F_5697 ),
.IB(\i2/blk00000001/sig0000015d/CYINIT_5698 ),
.SEL(\i2/blk00000001/sig0000015d/CYSELF_5684 ),
.O(\i2/blk00000001/sig000001bc )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYMUXF2 (
.IA(\i2/blk00000001/sig0000015d/CY0F_5697 ),
.IB(\i2/blk00000001/sig0000015d/CY0F_5697 ),
.SEL(\i2/blk00000001/sig0000015d/CYSELF_5684 ),
.O(\i2/blk00000001/sig0000015d/CYMUXF2_5679 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYINIT (
.I(\i2/blk00000001/sig000001c2 ),
.O(\i2/blk00000001/sig0000015d/CYINIT_5698 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CY0F (
.I(\i2/blk00000001/sig0000020f ),
.O(\i2/blk00000001/sig0000015d/CY0F_5697 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000015d/FAND/IN1 ),
.O(\i2/blk00000001/sig0000020f )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYSELF (
.I(\i2/blk00000001/sig0000015d/F ),
.O(\i2/blk00000001/sig0000015d/CYSELF_5684 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/YUSED (
.I(\i2/blk00000001/sig0000015d/XORG_5686 ),
.O(\i2/blk00000001/sig00000152 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/XORG (
.I0(\i2/blk00000001/sig000001bc ),
.I1(\i2/blk00000001/sig0000015d/G ),
.O(\i2/blk00000001/sig0000015d/XORG_5686 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/COUTUSED (
.I(\i2/blk00000001/sig0000015d/CYMUXFAST_5683 ),
.O(\i2/blk00000001/sig000001b6 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/FASTCARRY (
.I(\i2/blk00000001/sig000001c2 ),
.O(\i2/blk00000001/sig0000015d/FASTCARRY_5681 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYAND (
.I0(\i2/blk00000001/sig0000015d/CYSELG_5669 ),
.I1(\i2/blk00000001/sig0000015d/CYSELF_5684 ),
.O(\i2/blk00000001/sig0000015d/CYAND_5682 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYMUXFAST (
.IA(\i2/blk00000001/sig0000015d/CYMUXG2_5680 ),
.IB(\i2/blk00000001/sig0000015d/FASTCARRY_5681 ),
.SEL(\i2/blk00000001/sig0000015d/CYAND_5682 ),
.O(\i2/blk00000001/sig0000015d/CYMUXFAST_5683 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYMUXG2 (
.IA(\i2/blk00000001/sig0000015d/CY0G_5678 ),
.IB(\i2/blk00000001/sig0000015d/CYMUXF2_5679 ),
.SEL(\i2/blk00000001/sig0000015d/CYSELG_5669 ),
.O(\i2/blk00000001/sig0000015d/CYMUXG2_5680 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CY0G (
.I(\i2/blk00000001/sig00000209 ),
.O(\i2/blk00000001/sig0000015d/CY0G_5678 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000015d/GAND/IN1 ),
.O(\i2/blk00000001/sig00000209 )
);
X_BUF #(
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/CYSELG (
.I(\i2/blk00000001/sig0000015d/G ),
.O(\i2/blk00000001/sig0000015d/CYSELG_5669 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/XUSED (
.I(\i2/blk00000001/sig00000147/XORF_5740 ),
.O(\i2/blk00000001/sig00000147 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/XORF (
.I0(\i2/blk00000001/sig00000147/CYINIT_5739 ),
.I1(\i2/blk00000001/sig00000147/F ),
.O(\i2/blk00000001/sig00000147/XORF_5740 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYMUXF (
.IA(\i2/blk00000001/sig00000147/CY0F_5738 ),
.IB(\i2/blk00000001/sig00000147/CYINIT_5739 ),
.SEL(\i2/blk00000001/sig00000147/CYSELF_5726 ),
.O(\i2/blk00000001/sig000001b0 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYMUXF2 (
.IA(\i2/blk00000001/sig00000147/CY0F_5738 ),
.IB(\i2/blk00000001/sig00000147/CY0F_5738 ),
.SEL(\i2/blk00000001/sig00000147/CYSELF_5726 ),
.O(\i2/blk00000001/sig00000147/CYMUXF2_5721 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYINIT (
.I(\i2/blk00000001/sig000001b6 ),
.O(\i2/blk00000001/sig00000147/CYINIT_5739 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CY0F (
.I(\i2/blk00000001/sig00000203 ),
.O(\i2/blk00000001/sig00000147/CY0F_5738 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000147/FAND/IN1 ),
.O(\i2/blk00000001/sig00000203 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYSELF (
.I(\i2/blk00000001/sig00000147/F ),
.O(\i2/blk00000001/sig00000147/CYSELF_5726 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/YUSED (
.I(\i2/blk00000001/sig00000147/XORG_5728 ),
.O(\i2/blk00000001/sig0000013c )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/XORG (
.I0(\i2/blk00000001/sig000001b0 ),
.I1(\i2/blk00000001/sig00000147/G ),
.O(\i2/blk00000001/sig00000147/XORG_5728 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/COUTUSED (
.I(\i2/blk00000001/sig00000147/CYMUXFAST_5725 ),
.O(\i2/blk00000001/sig000001aa )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/FASTCARRY (
.I(\i2/blk00000001/sig000001b6 ),
.O(\i2/blk00000001/sig00000147/FASTCARRY_5723 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYAND (
.I0(\i2/blk00000001/sig00000147/CYSELG_5711 ),
.I1(\i2/blk00000001/sig00000147/CYSELF_5726 ),
.O(\i2/blk00000001/sig00000147/CYAND_5724 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYMUXFAST (
.IA(\i2/blk00000001/sig00000147/CYMUXG2_5722 ),
.IB(\i2/blk00000001/sig00000147/FASTCARRY_5723 ),
.SEL(\i2/blk00000001/sig00000147/CYAND_5724 ),
.O(\i2/blk00000001/sig00000147/CYMUXFAST_5725 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYMUXG2 (
.IA(\i2/blk00000001/sig00000147/CY0G_5720 ),
.IB(\i2/blk00000001/sig00000147/CYMUXF2_5721 ),
.SEL(\i2/blk00000001/sig00000147/CYSELG_5711 ),
.O(\i2/blk00000001/sig00000147/CYMUXG2_5722 )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CY0G (
.I(\i2/blk00000001/sig000001fd ),
.O(\i2/blk00000001/sig00000147/CY0G_5720 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000147/GAND/IN1 ),
.O(\i2/blk00000001/sig000001fd )
);
X_BUF #(
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/CYSELG (
.I(\i2/blk00000001/sig00000147/G ),
.O(\i2/blk00000001/sig00000147/CYSELG_5711 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/XUSED (
.I(\i2/blk00000001/sig00000131/XORF_5781 ),
.O(\i2/blk00000001/sig00000131 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/XORF (
.I0(\i2/blk00000001/sig00000131/CYINIT_5780 ),
.I1(\i2/blk00000001/sig00000131/F ),
.O(\i2/blk00000001/sig00000131/XORF_5781 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYMUXF (
.IA(\i2/blk00000001/sig00000131/CY0F_5779 ),
.IB(\i2/blk00000001/sig00000131/CYINIT_5780 ),
.SEL(\i2/blk00000001/sig00000131/CYSELF_5767 ),
.O(\i2/blk00000001/sig000001a4 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYMUXF2 (
.IA(\i2/blk00000001/sig00000131/CY0F_5779 ),
.IB(\i2/blk00000001/sig00000131/CY0F_5779 ),
.SEL(\i2/blk00000001/sig00000131/CYSELF_5767 ),
.O(\i2/blk00000001/sig00000131/CYMUXF2_5762 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYINIT (
.I(\i2/blk00000001/sig000001aa ),
.O(\i2/blk00000001/sig00000131/CYINIT_5780 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CY0F (
.I(\i2/blk00000001/sig000001f7 ),
.O(\i2/blk00000001/sig00000131/CY0F_5779 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000131/FAND/IN1 ),
.O(\i2/blk00000001/sig000001f7 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYSELF (
.I(\i2/blk00000001/sig00000131/F ),
.O(\i2/blk00000001/sig00000131/CYSELF_5767 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/YUSED (
.I(\i2/blk00000001/sig00000131/XORG_5769 ),
.O(\i2/blk00000001/sig00000126 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/XORG (
.I0(\i2/blk00000001/sig000001a4 ),
.I1(\i2/blk00000001/sig00000131/G ),
.O(\i2/blk00000001/sig00000131/XORG_5769 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/FASTCARRY (
.I(\i2/blk00000001/sig000001aa ),
.O(\i2/blk00000001/sig00000131/FASTCARRY_5764 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYAND (
.I0(\i2/blk00000001/sig00000131/CYSELG_5752 ),
.I1(\i2/blk00000001/sig00000131/CYSELF_5767 ),
.O(\i2/blk00000001/sig00000131/CYAND_5765 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYMUXFAST (
.IA(\i2/blk00000001/sig00000131/CYMUXG2_5763 ),
.IB(\i2/blk00000001/sig00000131/FASTCARRY_5764 ),
.SEL(\i2/blk00000001/sig00000131/CYAND_5765 ),
.O(\i2/blk00000001/sig00000131/CYMUXFAST_5766 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYMUXG2 (
.IA(\i2/blk00000001/sig00000131/CY0G_5761 ),
.IB(\i2/blk00000001/sig00000131/CYMUXF2_5762 ),
.SEL(\i2/blk00000001/sig00000131/CYSELG_5752 ),
.O(\i2/blk00000001/sig00000131/CYMUXG2_5763 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CY0G (
.I(\i2/blk00000001/sig000001f1 ),
.O(\i2/blk00000001/sig00000131/CY0G_5761 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i2/blk00000001/sig00000131/GAND/IN1 ),
.O(\i2/blk00000001/sig000001f1 )
);
X_BUF #(
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/CYSELG (
.I(\i2/blk00000001/sig00000131/G ),
.O(\i2/blk00000001/sig00000131/CYSELG_5752 )
);
X_BUF #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/XUSED (
.I(\i2/blk00000001/sig0000011b/XORF_5813 ),
.O(\i2/blk00000001/sig0000011b )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/XORF (
.I0(\i2/blk00000001/sig0000011b/CYINIT_5812 ),
.I1(\i2/blk00000001/sig0000011b/F ),
.O(\i2/blk00000001/sig0000011b/XORF_5813 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/CYMUXF (
.IA(\i2/blk00000001/sig0000011b/CY0F_5811 ),
.IB(\i2/blk00000001/sig0000011b/CYINIT_5812 ),
.SEL(\i2/blk00000001/sig0000011b/CYSELF_5802 ),
.O(\i2/blk00000001/sig00000198 )
);
X_BUF #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/CYINIT (
.I(\i2/blk00000001/sig00000131/CYMUXFAST_5766 ),
.O(\i2/blk00000001/sig0000011b/CYINIT_5812 )
);
X_BUF #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/CY0F (
.I(\i2/blk00000001/sig000001eb ),
.O(\i2/blk00000001/sig0000011b/CY0F_5811 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i2/blk00000001/sig0000011b/FAND/IN1 ),
.O(\i2/blk00000001/sig000001eb )
);
X_BUF #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/CYSELF (
.I(\i2/blk00000001/sig0000011b/F ),
.O(\i2/blk00000001/sig0000011b/CYSELF_5802 )
);
X_BUF #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/YUSED (
.I(\i2/blk00000001/sig0000011b/XORG_5799 ),
.O(\i2/blk00000001/sig00000110 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/XORG (
.I0(\i2/blk00000001/sig00000198 ),
.I1(\i2/blk00000001/sig0000011b/G ),
.O(\i2/blk00000001/sig0000011b/XORG_5799 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/XUSED (
.I(\i2/blk00000001/sig000000c4/XORF_5849 ),
.O(\i2/blk00000001/sig000000c4 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/XORF (
.I0(\i2/blk00000001/sig000000c4/CYINIT_5848 ),
.I1(\i2/blk00000001/sig0000008d ),
.O(\i2/blk00000001/sig000000c4/XORF_5849 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CYMUXF (
.IA(\i2/blk00000001/sig000000c4/CY0F_5847 ),
.IB(\i2/blk00000001/sig000000c4/CYINIT_5848 ),
.SEL(\i2/blk00000001/sig000000c4/CYSELF_5839 ),
.O(\i2/blk00000001/sig0000008c )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CYINIT (
.I(\i2/blk00000001/sig000000c4/BXINV_5837 ),
.O(\i2/blk00000001/sig000000c4/CYINIT_5848 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CY0F (
.I(\i2/blk00000001/sig00000186 ),
.O(\i2/blk00000001/sig000000c4/CY0F_5847 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CYSELF (
.I(\i2/blk00000001/sig0000008d ),
.O(\i2/blk00000001/sig000000c4/CYSELF_5839 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000000c4/BXINV_5837 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/YUSED (
.I(\i2/blk00000001/sig000000c4/XORG_5835 ),
.O(\i2/blk00000001/sig000000c5 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/XORG (
.I0(\i2/blk00000001/sig0000008c ),
.I1(\i2/blk00000001/sig0000008b ),
.O(\i2/blk00000001/sig000000c4/XORG_5835 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/COUTUSED (
.I(\i2/blk00000001/sig000000c4/CYMUXG_5834 ),
.O(\i2/blk00000001/sig0000008a )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CYMUXG (
.IA(\i2/blk00000001/sig000000c4/CY0G_5832 ),
.IB(\i2/blk00000001/sig0000008c ),
.SEL(\i2/blk00000001/sig000000c4/CYSELG_5824 ),
.O(\i2/blk00000001/sig000000c4/CYMUXG_5834 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CY0G (
.I(\i2/blk00000001/sig0000017a ),
.O(\i2/blk00000001/sig000000c4/CY0G_5832 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/sig000000c4/CYSELG (
.I(\i2/blk00000001/sig0000008b ),
.O(\i2/blk00000001/sig000000c4/CYSELG_5824 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/XUSED (
.I(\i2/blk00000001/sig000000c6/XORF_5888 ),
.O(\i2/blk00000001/sig000000c6 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/XORF (
.I0(\i2/blk00000001/sig000000c6/CYINIT_5887 ),
.I1(\i2/blk00000001/sig00000089 ),
.O(\i2/blk00000001/sig000000c6/XORF_5888 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYMUXF (
.IA(\i2/blk00000001/sig000000c6/CY0F_5886 ),
.IB(\i2/blk00000001/sig000000c6/CYINIT_5887 ),
.SEL(\i2/blk00000001/sig000000c6/CYSELF_5874 ),
.O(\i2/blk00000001/sig00000088 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYMUXF2 (
.IA(\i2/blk00000001/sig000000c6/CY0F_5886 ),
.IB(\i2/blk00000001/sig000000c6/CY0F_5886 ),
.SEL(\i2/blk00000001/sig000000c6/CYSELF_5874 ),
.O(\i2/blk00000001/sig000000c6/CYMUXF2_5869 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYINIT (
.I(\i2/blk00000001/sig0000008a ),
.O(\i2/blk00000001/sig000000c6/CYINIT_5887 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CY0F (
.I(\i2/blk00000001/sig0000016f ),
.O(\i2/blk00000001/sig000000c6/CY0F_5886 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYSELF (
.I(\i2/blk00000001/sig00000089 ),
.O(\i2/blk00000001/sig000000c6/CYSELF_5874 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/YUSED (
.I(\i2/blk00000001/sig000000c6/XORG_5876 ),
.O(\i2/blk00000001/sig000000c7 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/XORG (
.I0(\i2/blk00000001/sig00000088 ),
.I1(\i2/blk00000001/sig00000087 ),
.O(\i2/blk00000001/sig000000c6/XORG_5876 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/COUTUSED (
.I(\i2/blk00000001/sig000000c6/CYMUXFAST_5873 ),
.O(\i2/blk00000001/sig00000086 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/FASTCARRY (
.I(\i2/blk00000001/sig0000008a ),
.O(\i2/blk00000001/sig000000c6/FASTCARRY_5871 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYAND (
.I0(\i2/blk00000001/sig000000c6/CYSELG_5860 ),
.I1(\i2/blk00000001/sig000000c6/CYSELF_5874 ),
.O(\i2/blk00000001/sig000000c6/CYAND_5872 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYMUXFAST (
.IA(\i2/blk00000001/sig000000c6/CYMUXG2_5870 ),
.IB(\i2/blk00000001/sig000000c6/FASTCARRY_5871 ),
.SEL(\i2/blk00000001/sig000000c6/CYAND_5872 ),
.O(\i2/blk00000001/sig000000c6/CYMUXFAST_5873 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYMUXG2 (
.IA(\i2/blk00000001/sig000000c6/CY0G_5868 ),
.IB(\i2/blk00000001/sig000000c6/CYMUXF2_5869 ),
.SEL(\i2/blk00000001/sig000000c6/CYSELG_5860 ),
.O(\i2/blk00000001/sig000000c6/CYMUXG2_5870 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CY0G (
.I(\i2/blk00000001/sig00000164 ),
.O(\i2/blk00000001/sig000000c6/CY0G_5868 )
);
X_BUF #(
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/sig000000c6/CYSELG (
.I(\i2/blk00000001/sig00000087 ),
.O(\i2/blk00000001/sig000000c6/CYSELG_5860 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/blk00000171 (
.ADR0(\i2/blk00000001/sig00000159 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000163 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000085 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/XUSED (
.I(\i2/blk00000001/sig000000c8/XORF_5927 ),
.O(\i2/blk00000001/sig000000c8 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/XORF (
.I0(\i2/blk00000001/sig000000c8/CYINIT_5926 ),
.I1(\i2/blk00000001/sig00000085 ),
.O(\i2/blk00000001/sig000000c8/XORF_5927 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYMUXF (
.IA(\i2/blk00000001/sig000000c8/CY0F_5925 ),
.IB(\i2/blk00000001/sig000000c8/CYINIT_5926 ),
.SEL(\i2/blk00000001/sig000000c8/CYSELF_5913 ),
.O(\i2/blk00000001/sig00000084 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYMUXF2 (
.IA(\i2/blk00000001/sig000000c8/CY0F_5925 ),
.IB(\i2/blk00000001/sig000000c8/CY0F_5925 ),
.SEL(\i2/blk00000001/sig000000c8/CYSELF_5913 ),
.O(\i2/blk00000001/sig000000c8/CYMUXF2_5908 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYINIT (
.I(\i2/blk00000001/sig00000086 ),
.O(\i2/blk00000001/sig000000c8/CYINIT_5926 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CY0F (
.I(\i2/blk00000001/sig00000159 ),
.O(\i2/blk00000001/sig000000c8/CY0F_5925 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYSELF (
.I(\i2/blk00000001/sig00000085 ),
.O(\i2/blk00000001/sig000000c8/CYSELF_5913 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/YUSED (
.I(\i2/blk00000001/sig000000c8/XORG_5915 ),
.O(\i2/blk00000001/sig000000c9 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/XORG (
.I0(\i2/blk00000001/sig00000084 ),
.I1(\i2/blk00000001/sig00000083 ),
.O(\i2/blk00000001/sig000000c8/XORG_5915 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/COUTUSED (
.I(\i2/blk00000001/sig000000c8/CYMUXFAST_5912 ),
.O(\i2/blk00000001/sig00000082 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/FASTCARRY (
.I(\i2/blk00000001/sig00000086 ),
.O(\i2/blk00000001/sig000000c8/FASTCARRY_5910 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYAND (
.I0(\i2/blk00000001/sig000000c8/CYSELG_5899 ),
.I1(\i2/blk00000001/sig000000c8/CYSELF_5913 ),
.O(\i2/blk00000001/sig000000c8/CYAND_5911 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYMUXFAST (
.IA(\i2/blk00000001/sig000000c8/CYMUXG2_5909 ),
.IB(\i2/blk00000001/sig000000c8/FASTCARRY_5910 ),
.SEL(\i2/blk00000001/sig000000c8/CYAND_5911 ),
.O(\i2/blk00000001/sig000000c8/CYMUXFAST_5912 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYMUXG2 (
.IA(\i2/blk00000001/sig000000c8/CY0G_5907 ),
.IB(\i2/blk00000001/sig000000c8/CYMUXF2_5908 ),
.SEL(\i2/blk00000001/sig000000c8/CYSELG_5899 ),
.O(\i2/blk00000001/sig000000c8/CYMUXG2_5909 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CY0G (
.I(\i2/blk00000001/sig0000014e ),
.O(\i2/blk00000001/sig000000c8/CY0G_5907 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/sig000000c8/CYSELG (
.I(\i2/blk00000001/sig00000083 ),
.O(\i2/blk00000001/sig000000c8/CYSELG_5899 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/XUSED (
.I(\i2/blk00000001/sig000000ca/XORF_5966 ),
.O(\i2/blk00000001/sig000000ca )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/XORF (
.I0(\i2/blk00000001/sig000000ca/CYINIT_5965 ),
.I1(\i2/blk00000001/sig00000081 ),
.O(\i2/blk00000001/sig000000ca/XORF_5966 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYMUXF (
.IA(\i2/blk00000001/sig000000ca/CY0F_5964 ),
.IB(\i2/blk00000001/sig000000ca/CYINIT_5965 ),
.SEL(\i2/blk00000001/sig000000ca/CYSELF_5952 ),
.O(\i2/blk00000001/sig00000080 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYMUXF2 (
.IA(\i2/blk00000001/sig000000ca/CY0F_5964 ),
.IB(\i2/blk00000001/sig000000ca/CY0F_5964 ),
.SEL(\i2/blk00000001/sig000000ca/CYSELF_5952 ),
.O(\i2/blk00000001/sig000000ca/CYMUXF2_5947 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYINIT (
.I(\i2/blk00000001/sig00000082 ),
.O(\i2/blk00000001/sig000000ca/CYINIT_5965 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CY0F (
.I(\i2/blk00000001/sig00000143 ),
.O(\i2/blk00000001/sig000000ca/CY0F_5964 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYSELF (
.I(\i2/blk00000001/sig00000081 ),
.O(\i2/blk00000001/sig000000ca/CYSELF_5952 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/YUSED (
.I(\i2/blk00000001/sig000000ca/XORG_5954 ),
.O(\i2/blk00000001/sig000000cb )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/XORG (
.I0(\i2/blk00000001/sig00000080 ),
.I1(\i2/blk00000001/sig0000007f ),
.O(\i2/blk00000001/sig000000ca/XORG_5954 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/COUTUSED (
.I(\i2/blk00000001/sig000000ca/CYMUXFAST_5951 ),
.O(\i2/blk00000001/sig0000007e )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/FASTCARRY (
.I(\i2/blk00000001/sig00000082 ),
.O(\i2/blk00000001/sig000000ca/FASTCARRY_5949 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYAND (
.I0(\i2/blk00000001/sig000000ca/CYSELG_5938 ),
.I1(\i2/blk00000001/sig000000ca/CYSELF_5952 ),
.O(\i2/blk00000001/sig000000ca/CYAND_5950 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYMUXFAST (
.IA(\i2/blk00000001/sig000000ca/CYMUXG2_5948 ),
.IB(\i2/blk00000001/sig000000ca/FASTCARRY_5949 ),
.SEL(\i2/blk00000001/sig000000ca/CYAND_5950 ),
.O(\i2/blk00000001/sig000000ca/CYMUXFAST_5951 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYMUXG2 (
.IA(\i2/blk00000001/sig000000ca/CY0G_5946 ),
.IB(\i2/blk00000001/sig000000ca/CYMUXF2_5947 ),
.SEL(\i2/blk00000001/sig000000ca/CYSELG_5938 ),
.O(\i2/blk00000001/sig000000ca/CYMUXG2_5948 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CY0G (
.I(\i2/blk00000001/sig00000138 ),
.O(\i2/blk00000001/sig000000ca/CY0G_5946 )
);
X_BUF #(
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/sig000000ca/CYSELG (
.I(\i2/blk00000001/sig0000007f ),
.O(\i2/blk00000001/sig000000ca/CYSELG_5938 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/blk00000168 (
.ADR0(\i2/blk00000001/sig00000142 ),
.ADR1(\i2/blk00000001/sig00000138 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000007f )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/XUSED (
.I(\i2/blk00000001/sig000000cc/XORF_6005 ),
.O(\i2/blk00000001/sig000000cc )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/XORF (
.I0(\i2/blk00000001/sig000000cc/CYINIT_6004 ),
.I1(\i2/blk00000001/sig0000007d ),
.O(\i2/blk00000001/sig000000cc/XORF_6005 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYMUXF (
.IA(\i2/blk00000001/sig000000cc/CY0F_6003 ),
.IB(\i2/blk00000001/sig000000cc/CYINIT_6004 ),
.SEL(\i2/blk00000001/sig000000cc/CYSELF_5991 ),
.O(\i2/blk00000001/sig0000007c )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYMUXF2 (
.IA(\i2/blk00000001/sig000000cc/CY0F_6003 ),
.IB(\i2/blk00000001/sig000000cc/CY0F_6003 ),
.SEL(\i2/blk00000001/sig000000cc/CYSELF_5991 ),
.O(\i2/blk00000001/sig000000cc/CYMUXF2_5986 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYINIT (
.I(\i2/blk00000001/sig0000007e ),
.O(\i2/blk00000001/sig000000cc/CYINIT_6004 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CY0F (
.I(\i2/blk00000001/sig0000012d ),
.O(\i2/blk00000001/sig000000cc/CY0F_6003 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYSELF (
.I(\i2/blk00000001/sig0000007d ),
.O(\i2/blk00000001/sig000000cc/CYSELF_5991 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/YUSED (
.I(\i2/blk00000001/sig000000cc/XORG_5993 ),
.O(\i2/blk00000001/sig000000cd )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/XORG (
.I0(\i2/blk00000001/sig0000007c ),
.I1(\i2/blk00000001/sig0000007b ),
.O(\i2/blk00000001/sig000000cc/XORG_5993 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/COUTUSED (
.I(\i2/blk00000001/sig000000cc/CYMUXFAST_5990 ),
.O(\i2/blk00000001/sig0000007a )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/FASTCARRY (
.I(\i2/blk00000001/sig0000007e ),
.O(\i2/blk00000001/sig000000cc/FASTCARRY_5988 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYAND (
.I0(\i2/blk00000001/sig000000cc/CYSELG_5977 ),
.I1(\i2/blk00000001/sig000000cc/CYSELF_5991 ),
.O(\i2/blk00000001/sig000000cc/CYAND_5989 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYMUXFAST (
.IA(\i2/blk00000001/sig000000cc/CYMUXG2_5987 ),
.IB(\i2/blk00000001/sig000000cc/FASTCARRY_5988 ),
.SEL(\i2/blk00000001/sig000000cc/CYAND_5989 ),
.O(\i2/blk00000001/sig000000cc/CYMUXFAST_5990 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYMUXG2 (
.IA(\i2/blk00000001/sig000000cc/CY0G_5985 ),
.IB(\i2/blk00000001/sig000000cc/CYMUXF2_5986 ),
.SEL(\i2/blk00000001/sig000000cc/CYSELG_5977 ),
.O(\i2/blk00000001/sig000000cc/CYMUXG2_5987 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CY0G (
.I(\i2/blk00000001/sig00000122 ),
.O(\i2/blk00000001/sig000000cc/CY0G_5985 )
);
X_BUF #(
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/sig000000cc/CYSELG (
.I(\i2/blk00000001/sig0000007b ),
.O(\i2/blk00000001/sig000000cc/CYSELG_5977 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/XUSED (
.I(\i2/blk00000001/sig000000ce/XORF_6044 ),
.O(\i2/blk00000001/sig000000ce )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/XORF (
.I0(\i2/blk00000001/sig000000ce/CYINIT_6043 ),
.I1(\i2/blk00000001/sig00000079 ),
.O(\i2/blk00000001/sig000000ce/XORF_6044 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYMUXF (
.IA(\i2/blk00000001/sig000000ce/CY0F_6042 ),
.IB(\i2/blk00000001/sig000000ce/CYINIT_6043 ),
.SEL(\i2/blk00000001/sig000000ce/CYSELF_6030 ),
.O(\i2/blk00000001/sig00000078 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYMUXF2 (
.IA(\i2/blk00000001/sig000000ce/CY0F_6042 ),
.IB(\i2/blk00000001/sig000000ce/CY0F_6042 ),
.SEL(\i2/blk00000001/sig000000ce/CYSELF_6030 ),
.O(\i2/blk00000001/sig000000ce/CYMUXF2_6025 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYINIT (
.I(\i2/blk00000001/sig0000007a ),
.O(\i2/blk00000001/sig000000ce/CYINIT_6043 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CY0F (
.I(\i2/blk00000001/sig00000117 ),
.O(\i2/blk00000001/sig000000ce/CY0F_6042 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYSELF (
.I(\i2/blk00000001/sig00000079 ),
.O(\i2/blk00000001/sig000000ce/CYSELF_6030 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/YUSED (
.I(\i2/blk00000001/sig000000ce/XORG_6032 ),
.O(\i2/blk00000001/sig000000cf )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/XORG (
.I0(\i2/blk00000001/sig00000078 ),
.I1(\i2/blk00000001/sig00000077 ),
.O(\i2/blk00000001/sig000000ce/XORG_6032 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/FASTCARRY (
.I(\i2/blk00000001/sig0000007a ),
.O(\i2/blk00000001/sig000000ce/FASTCARRY_6027 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYAND (
.I0(\i2/blk00000001/sig000000ce/CYSELG_6016 ),
.I1(\i2/blk00000001/sig000000ce/CYSELF_6030 ),
.O(\i2/blk00000001/sig000000ce/CYAND_6028 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYMUXFAST (
.IA(\i2/blk00000001/sig000000ce/CYMUXG2_6026 ),
.IB(\i2/blk00000001/sig000000ce/FASTCARRY_6027 ),
.SEL(\i2/blk00000001/sig000000ce/CYAND_6028 ),
.O(\i2/blk00000001/sig000000ce/CYMUXFAST_6029 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYMUXG2 (
.IA(\i2/blk00000001/sig000000ce/CY0G_6024 ),
.IB(\i2/blk00000001/sig000000ce/CYMUXF2_6025 ),
.SEL(\i2/blk00000001/sig000000ce/CYSELG_6016 ),
.O(\i2/blk00000001/sig000000ce/CYMUXG2_6026 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CY0G (
.I(\i2/blk00000001/sig0000010c ),
.O(\i2/blk00000001/sig000000ce/CY0G_6024 )
);
X_BUF #(
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/sig000000ce/CYSELG (
.I(\i2/blk00000001/sig00000077 ),
.O(\i2/blk00000001/sig000000ce/CYSELG_6016 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\i2/blk00000001/sig000000d0/XUSED (
.I(\i2/blk00000001/sig000000d0/XORF_6059 ),
.O(\i2/blk00000001/sig000000d0 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y31" ))
\i2/blk00000001/sig000000d0/XORF (
.I0(\i2/blk00000001/sig000000d0/CYINIT_6058 ),
.I1(\i2/blk00000001/sig00000075 ),
.O(\i2/blk00000001/sig000000d0/XORF_6059 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\i2/blk00000001/sig000000d0/CYINIT (
.I(\i2/blk00000001/sig000000ce/CYMUXFAST_6029 ),
.O(\i2/blk00000001/sig000000d0/CYINIT_6058 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/XUSED (
.I(\i2/blk00000001/sig000000eb/XORF_6095 ),
.O(\i2/blk00000001/sig000000eb )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/XORF (
.I0(\i2/blk00000001/sig000000eb/CYINIT_6094 ),
.I1(\i2/blk00000001/sig000000a8 ),
.O(\i2/blk00000001/sig000000eb/XORF_6095 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CYMUXF (
.IA(\i2/blk00000001/sig000000eb/CY0F_6093 ),
.IB(\i2/blk00000001/sig000000eb/CYINIT_6094 ),
.SEL(\i2/blk00000001/sig000000eb/CYSELF_6085 ),
.O(\i2/blk00000001/sig000000a7 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CYINIT (
.I(\i2/blk00000001/sig000000eb/BXINV_6083 ),
.O(\i2/blk00000001/sig000000eb/CYINIT_6094 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CY0F (
.I(\i2/blk00000001/sig0000018c ),
.O(\i2/blk00000001/sig000000eb/CY0F_6093 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CYSELF (
.I(\i2/blk00000001/sig000000a8 ),
.O(\i2/blk00000001/sig000000eb/CYSELF_6085 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000000eb/BXINV_6083 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/YUSED (
.I(\i2/blk00000001/sig000000eb/XORG_6081 ),
.O(\i2/blk00000001/sig000000ec )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/XORG (
.I0(\i2/blk00000001/sig000000a7 ),
.I1(\i2/blk00000001/sig000000a6 ),
.O(\i2/blk00000001/sig000000eb/XORG_6081 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/COUTUSED (
.I(\i2/blk00000001/sig000000eb/CYMUXG_6080 ),
.O(\i2/blk00000001/sig000000a5 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CYMUXG (
.IA(\i2/blk00000001/sig000000eb/CY0G_6078 ),
.IB(\i2/blk00000001/sig000000a7 ),
.SEL(\i2/blk00000001/sig000000eb/CYSELG_6070 ),
.O(\i2/blk00000001/sig000000eb/CYMUXG_6080 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CY0G (
.I(\i2/blk00000001/sig0000017e ),
.O(\i2/blk00000001/sig000000eb/CY0G_6078 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/sig000000eb/CYSELG (
.I(\i2/blk00000001/sig000000a6 ),
.O(\i2/blk00000001/sig000000eb/CYSELG_6070 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/XUSED (
.I(\i2/blk00000001/sig000000ed/XORF_6134 ),
.O(\i2/blk00000001/sig000000ed )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/XORF (
.I0(\i2/blk00000001/sig000000ed/CYINIT_6133 ),
.I1(\i2/blk00000001/sig000000a4 ),
.O(\i2/blk00000001/sig000000ed/XORF_6134 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYMUXF (
.IA(\i2/blk00000001/sig000000ed/CY0F_6132 ),
.IB(\i2/blk00000001/sig000000ed/CYINIT_6133 ),
.SEL(\i2/blk00000001/sig000000ed/CYSELF_6120 ),
.O(\i2/blk00000001/sig000000a3 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYMUXF2 (
.IA(\i2/blk00000001/sig000000ed/CY0F_6132 ),
.IB(\i2/blk00000001/sig000000ed/CY0F_6132 ),
.SEL(\i2/blk00000001/sig000000ed/CYSELF_6120 ),
.O(\i2/blk00000001/sig000000ed/CYMUXF2_6115 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYINIT (
.I(\i2/blk00000001/sig000000a5 ),
.O(\i2/blk00000001/sig000000ed/CYINIT_6133 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CY0F (
.I(\i2/blk00000001/sig00000173 ),
.O(\i2/blk00000001/sig000000ed/CY0F_6132 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYSELF (
.I(\i2/blk00000001/sig000000a4 ),
.O(\i2/blk00000001/sig000000ed/CYSELF_6120 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/YUSED (
.I(\i2/blk00000001/sig000000ed/XORG_6122 ),
.O(\i2/blk00000001/sig000000ee )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/XORG (
.I0(\i2/blk00000001/sig000000a3 ),
.I1(\i2/blk00000001/sig000000a2 ),
.O(\i2/blk00000001/sig000000ed/XORG_6122 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/COUTUSED (
.I(\i2/blk00000001/sig000000ed/CYMUXFAST_6119 ),
.O(\i2/blk00000001/sig000000a1 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/FASTCARRY (
.I(\i2/blk00000001/sig000000a5 ),
.O(\i2/blk00000001/sig000000ed/FASTCARRY_6117 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYAND (
.I0(\i2/blk00000001/sig000000ed/CYSELG_6106 ),
.I1(\i2/blk00000001/sig000000ed/CYSELF_6120 ),
.O(\i2/blk00000001/sig000000ed/CYAND_6118 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYMUXFAST (
.IA(\i2/blk00000001/sig000000ed/CYMUXG2_6116 ),
.IB(\i2/blk00000001/sig000000ed/FASTCARRY_6117 ),
.SEL(\i2/blk00000001/sig000000ed/CYAND_6118 ),
.O(\i2/blk00000001/sig000000ed/CYMUXFAST_6119 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYMUXG2 (
.IA(\i2/blk00000001/sig000000ed/CY0G_6114 ),
.IB(\i2/blk00000001/sig000000ed/CYMUXF2_6115 ),
.SEL(\i2/blk00000001/sig000000ed/CYSELG_6106 ),
.O(\i2/blk00000001/sig000000ed/CYMUXG2_6116 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CY0G (
.I(\i2/blk00000001/sig00000168 ),
.O(\i2/blk00000001/sig000000ed/CY0G_6114 )
);
X_BUF #(
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/sig000000ed/CYSELG (
.I(\i2/blk00000001/sig000000a2 ),
.O(\i2/blk00000001/sig000000ed/CYSELG_6106 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/XUSED (
.I(\i2/blk00000001/sig000000ef/XORF_6173 ),
.O(\i2/blk00000001/sig000000ef )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/XORF (
.I0(\i2/blk00000001/sig000000ef/CYINIT_6172 ),
.I1(\i2/blk00000001/sig000000a0 ),
.O(\i2/blk00000001/sig000000ef/XORF_6173 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYMUXF (
.IA(\i2/blk00000001/sig000000ef/CY0F_6171 ),
.IB(\i2/blk00000001/sig000000ef/CYINIT_6172 ),
.SEL(\i2/blk00000001/sig000000ef/CYSELF_6159 ),
.O(\i2/blk00000001/sig0000009f )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYMUXF2 (
.IA(\i2/blk00000001/sig000000ef/CY0F_6171 ),
.IB(\i2/blk00000001/sig000000ef/CY0F_6171 ),
.SEL(\i2/blk00000001/sig000000ef/CYSELF_6159 ),
.O(\i2/blk00000001/sig000000ef/CYMUXF2_6154 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYINIT (
.I(\i2/blk00000001/sig000000a1 ),
.O(\i2/blk00000001/sig000000ef/CYINIT_6172 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CY0F (
.I(\i2/blk00000001/sig0000015d ),
.O(\i2/blk00000001/sig000000ef/CY0F_6171 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYSELF (
.I(\i2/blk00000001/sig000000a0 ),
.O(\i2/blk00000001/sig000000ef/CYSELF_6159 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/YUSED (
.I(\i2/blk00000001/sig000000ef/XORG_6161 ),
.O(\i2/blk00000001/sig000000f0 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/XORG (
.I0(\i2/blk00000001/sig0000009f ),
.I1(\i2/blk00000001/sig0000009e ),
.O(\i2/blk00000001/sig000000ef/XORG_6161 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/COUTUSED (
.I(\i2/blk00000001/sig000000ef/CYMUXFAST_6158 ),
.O(\i2/blk00000001/sig0000009d )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/FASTCARRY (
.I(\i2/blk00000001/sig000000a1 ),
.O(\i2/blk00000001/sig000000ef/FASTCARRY_6156 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYAND (
.I0(\i2/blk00000001/sig000000ef/CYSELG_6145 ),
.I1(\i2/blk00000001/sig000000ef/CYSELF_6159 ),
.O(\i2/blk00000001/sig000000ef/CYAND_6157 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYMUXFAST (
.IA(\i2/blk00000001/sig000000ef/CYMUXG2_6155 ),
.IB(\i2/blk00000001/sig000000ef/FASTCARRY_6156 ),
.SEL(\i2/blk00000001/sig000000ef/CYAND_6157 ),
.O(\i2/blk00000001/sig000000ef/CYMUXFAST_6158 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYMUXG2 (
.IA(\i2/blk00000001/sig000000ef/CY0G_6153 ),
.IB(\i2/blk00000001/sig000000ef/CYMUXF2_6154 ),
.SEL(\i2/blk00000001/sig000000ef/CYSELG_6145 ),
.O(\i2/blk00000001/sig000000ef/CYMUXG2_6155 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CY0G (
.I(\i2/blk00000001/sig00000152 ),
.O(\i2/blk00000001/sig000000ef/CY0G_6153 )
);
X_BUF #(
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/sig000000ef/CYSELG (
.I(\i2/blk00000001/sig0000009e ),
.O(\i2/blk00000001/sig000000ef/CYSELG_6145 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/XUSED (
.I(\i2/blk00000001/sig000000f1/XORF_6212 ),
.O(\i2/blk00000001/sig000000f1 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/XORF (
.I0(\i2/blk00000001/sig000000f1/CYINIT_6211 ),
.I1(\i2/blk00000001/sig0000009c ),
.O(\i2/blk00000001/sig000000f1/XORF_6212 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYMUXF (
.IA(\i2/blk00000001/sig000000f1/CY0F_6210 ),
.IB(\i2/blk00000001/sig000000f1/CYINIT_6211 ),
.SEL(\i2/blk00000001/sig000000f1/CYSELF_6198 ),
.O(\i2/blk00000001/sig0000009b )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYMUXF2 (
.IA(\i2/blk00000001/sig000000f1/CY0F_6210 ),
.IB(\i2/blk00000001/sig000000f1/CY0F_6210 ),
.SEL(\i2/blk00000001/sig000000f1/CYSELF_6198 ),
.O(\i2/blk00000001/sig000000f1/CYMUXF2_6193 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYINIT (
.I(\i2/blk00000001/sig0000009d ),
.O(\i2/blk00000001/sig000000f1/CYINIT_6211 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CY0F (
.I(\i2/blk00000001/sig00000147 ),
.O(\i2/blk00000001/sig000000f1/CY0F_6210 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYSELF (
.I(\i2/blk00000001/sig0000009c ),
.O(\i2/blk00000001/sig000000f1/CYSELF_6198 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/YUSED (
.I(\i2/blk00000001/sig000000f1/XORG_6200 ),
.O(\i2/blk00000001/sig000000f2 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/XORG (
.I0(\i2/blk00000001/sig0000009b ),
.I1(\i2/blk00000001/sig0000009a ),
.O(\i2/blk00000001/sig000000f1/XORG_6200 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/COUTUSED (
.I(\i2/blk00000001/sig000000f1/CYMUXFAST_6197 ),
.O(\i2/blk00000001/sig00000099 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/FASTCARRY (
.I(\i2/blk00000001/sig0000009d ),
.O(\i2/blk00000001/sig000000f1/FASTCARRY_6195 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYAND (
.I0(\i2/blk00000001/sig000000f1/CYSELG_6184 ),
.I1(\i2/blk00000001/sig000000f1/CYSELF_6198 ),
.O(\i2/blk00000001/sig000000f1/CYAND_6196 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYMUXFAST (
.IA(\i2/blk00000001/sig000000f1/CYMUXG2_6194 ),
.IB(\i2/blk00000001/sig000000f1/FASTCARRY_6195 ),
.SEL(\i2/blk00000001/sig000000f1/CYAND_6196 ),
.O(\i2/blk00000001/sig000000f1/CYMUXFAST_6197 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYMUXG2 (
.IA(\i2/blk00000001/sig000000f1/CY0G_6192 ),
.IB(\i2/blk00000001/sig000000f1/CYMUXF2_6193 ),
.SEL(\i2/blk00000001/sig000000f1/CYSELG_6184 ),
.O(\i2/blk00000001/sig000000f1/CYMUXG2_6194 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CY0G (
.I(\i2/blk00000001/sig0000013c ),
.O(\i2/blk00000001/sig000000f1/CY0G_6192 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/sig000000f1/CYSELG (
.I(\i2/blk00000001/sig0000009a ),
.O(\i2/blk00000001/sig000000f1/CYSELG_6184 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/XUSED (
.I(\i2/blk00000001/sig000000f3/XORF_6251 ),
.O(\i2/blk00000001/sig000000f3 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/XORF (
.I0(\i2/blk00000001/sig000000f3/CYINIT_6250 ),
.I1(\i2/blk00000001/sig00000098 ),
.O(\i2/blk00000001/sig000000f3/XORF_6251 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYMUXF (
.IA(\i2/blk00000001/sig000000f3/CY0F_6249 ),
.IB(\i2/blk00000001/sig000000f3/CYINIT_6250 ),
.SEL(\i2/blk00000001/sig000000f3/CYSELF_6237 ),
.O(\i2/blk00000001/sig00000097 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYMUXF2 (
.IA(\i2/blk00000001/sig000000f3/CY0F_6249 ),
.IB(\i2/blk00000001/sig000000f3/CY0F_6249 ),
.SEL(\i2/blk00000001/sig000000f3/CYSELF_6237 ),
.O(\i2/blk00000001/sig000000f3/CYMUXF2_6232 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYINIT (
.I(\i2/blk00000001/sig00000099 ),
.O(\i2/blk00000001/sig000000f3/CYINIT_6250 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CY0F (
.I(\i2/blk00000001/sig00000131 ),
.O(\i2/blk00000001/sig000000f3/CY0F_6249 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYSELF (
.I(\i2/blk00000001/sig00000098 ),
.O(\i2/blk00000001/sig000000f3/CYSELF_6237 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/YUSED (
.I(\i2/blk00000001/sig000000f3/XORG_6239 ),
.O(\i2/blk00000001/sig000000f4 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/XORG (
.I0(\i2/blk00000001/sig00000097 ),
.I1(\i2/blk00000001/sig00000096 ),
.O(\i2/blk00000001/sig000000f3/XORG_6239 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/COUTUSED (
.I(\i2/blk00000001/sig000000f3/CYMUXFAST_6236 ),
.O(\i2/blk00000001/sig00000095 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/FASTCARRY (
.I(\i2/blk00000001/sig00000099 ),
.O(\i2/blk00000001/sig000000f3/FASTCARRY_6234 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYAND (
.I0(\i2/blk00000001/sig000000f3/CYSELG_6223 ),
.I1(\i2/blk00000001/sig000000f3/CYSELF_6237 ),
.O(\i2/blk00000001/sig000000f3/CYAND_6235 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYMUXFAST (
.IA(\i2/blk00000001/sig000000f3/CYMUXG2_6233 ),
.IB(\i2/blk00000001/sig000000f3/FASTCARRY_6234 ),
.SEL(\i2/blk00000001/sig000000f3/CYAND_6235 ),
.O(\i2/blk00000001/sig000000f3/CYMUXFAST_6236 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYMUXG2 (
.IA(\i2/blk00000001/sig000000f3/CY0G_6231 ),
.IB(\i2/blk00000001/sig000000f3/CYMUXF2_6232 ),
.SEL(\i2/blk00000001/sig000000f3/CYSELG_6223 ),
.O(\i2/blk00000001/sig000000f3/CYMUXG2_6233 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CY0G (
.I(\i2/blk00000001/sig00000126 ),
.O(\i2/blk00000001/sig000000f3/CY0G_6231 )
);
X_BUF #(
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/sig000000f3/CYSELG (
.I(\i2/blk00000001/sig00000096 ),
.O(\i2/blk00000001/sig000000f3/CYSELG_6223 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/XUSED (
.I(\i2/blk00000001/sig000000f5/XORF_6290 ),
.O(\i2/blk00000001/sig000000f5 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/XORF (
.I0(\i2/blk00000001/sig000000f5/CYINIT_6289 ),
.I1(\i2/blk00000001/sig00000094 ),
.O(\i2/blk00000001/sig000000f5/XORF_6290 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYMUXF (
.IA(\i2/blk00000001/sig000000f5/CY0F_6288 ),
.IB(\i2/blk00000001/sig000000f5/CYINIT_6289 ),
.SEL(\i2/blk00000001/sig000000f5/CYSELF_6276 ),
.O(\i2/blk00000001/sig00000093 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYMUXF2 (
.IA(\i2/blk00000001/sig000000f5/CY0F_6288 ),
.IB(\i2/blk00000001/sig000000f5/CY0F_6288 ),
.SEL(\i2/blk00000001/sig000000f5/CYSELF_6276 ),
.O(\i2/blk00000001/sig000000f5/CYMUXF2_6271 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYINIT (
.I(\i2/blk00000001/sig00000095 ),
.O(\i2/blk00000001/sig000000f5/CYINIT_6289 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CY0F (
.I(\i2/blk00000001/sig0000011b ),
.O(\i2/blk00000001/sig000000f5/CY0F_6288 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYSELF (
.I(\i2/blk00000001/sig00000094 ),
.O(\i2/blk00000001/sig000000f5/CYSELF_6276 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/YUSED (
.I(\i2/blk00000001/sig000000f5/XORG_6278 ),
.O(\i2/blk00000001/sig000000f6 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/XORG (
.I0(\i2/blk00000001/sig00000093 ),
.I1(\i2/blk00000001/sig00000092 ),
.O(\i2/blk00000001/sig000000f5/XORG_6278 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/FASTCARRY (
.I(\i2/blk00000001/sig00000095 ),
.O(\i2/blk00000001/sig000000f5/FASTCARRY_6273 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYAND (
.I0(\i2/blk00000001/sig000000f5/CYSELG_6262 ),
.I1(\i2/blk00000001/sig000000f5/CYSELF_6276 ),
.O(\i2/blk00000001/sig000000f5/CYAND_6274 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYMUXFAST (
.IA(\i2/blk00000001/sig000000f5/CYMUXG2_6272 ),
.IB(\i2/blk00000001/sig000000f5/FASTCARRY_6273 ),
.SEL(\i2/blk00000001/sig000000f5/CYAND_6274 ),
.O(\i2/blk00000001/sig000000f5/CYMUXFAST_6275 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYMUXG2 (
.IA(\i2/blk00000001/sig000000f5/CY0G_6270 ),
.IB(\i2/blk00000001/sig000000f5/CYMUXF2_6271 ),
.SEL(\i2/blk00000001/sig000000f5/CYSELG_6262 ),
.O(\i2/blk00000001/sig000000f5/CYMUXG2_6272 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CY0G (
.I(\i2/blk00000001/sig00000110 ),
.O(\i2/blk00000001/sig000000f5/CY0G_6270 )
);
X_BUF #(
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/sig000000f5/CYSELG (
.I(\i2/blk00000001/sig00000092 ),
.O(\i2/blk00000001/sig000000f5/CYSELG_6262 )
);
X_BUF #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/XUSED (
.I(\i2/blk00000001/sig000000f7/XORF_6321 ),
.O(\i2/blk00000001/sig000000f7 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/XORF (
.I0(\i2/blk00000001/sig000000f7/CYINIT_6320 ),
.I1(\i2/blk00000001/sig00000090 ),
.O(\i2/blk00000001/sig000000f7/XORF_6321 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/CYMUXF (
.IA(\i2/blk00000001/sig000000f7/CY0F_6319 ),
.IB(\i2/blk00000001/sig000000f7/CYINIT_6320 ),
.SEL(\i2/blk00000001/sig000000f7/CYSELF_6311 ),
.O(\i2/blk00000001/sig0000008f )
);
X_BUF #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/CYINIT (
.I(\i2/blk00000001/sig000000f5/CYMUXFAST_6275 ),
.O(\i2/blk00000001/sig000000f7/CYINIT_6320 )
);
X_BUF #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/CY0F (
.I(\i2/blk00000001/sig00000110 ),
.O(\i2/blk00000001/sig000000f7/CY0F_6319 )
);
X_BUF #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/CYSELF (
.I(\i2/blk00000001/sig00000090 ),
.O(\i2/blk00000001/sig000000f7/CYSELF_6311 )
);
X_BUF #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/YUSED (
.I(\i2/blk00000001/sig000000f7/XORG_6308 ),
.O(\i2/blk00000001/sig000000f8 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/sig000000f7/XORG (
.I0(\i2/blk00000001/sig0000008f ),
.I1(\i2/blk00000001/sig0000008e ),
.O(\i2/blk00000001/sig000000f7/XORG_6308 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CYMUXF (
.IA(\i2/blk00000001/sig000000c0/CY0F_6351 ),
.IB(\i2/blk00000001/sig000000c0/CYINIT_6352 ),
.SEL(\i2/blk00000001/sig000000c0/CYSELF_6343 ),
.O(\i2/blk00000001/sig000000c2 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CYINIT (
.I(\i2/blk00000001/sig000000c0/BXINV_6341 ),
.O(\i2/blk00000001/sig000000c0/CYINIT_6352 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CY0F (
.I(\i2/blk00000001/sig00000192 ),
.O(\i2/blk00000001/sig000000c0/CY0F_6351 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CYSELF (
.I(\i2/blk00000001/sig000000c3 ),
.O(\i2/blk00000001/sig000000c0/CYSELF_6343 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/BXINV (
.I(1'b0),
.O(\i2/blk00000001/sig000000c0/BXINV_6341 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/COUTUSED (
.I(\i2/blk00000001/sig000000c0/CYMUXG_6340 ),
.O(\i2/blk00000001/sig000000c0 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CYMUXG (
.IA(\i2/blk00000001/sig000000c0/CY0G_6338 ),
.IB(\i2/blk00000001/sig000000c2 ),
.SEL(\i2/blk00000001/sig000000c0/CYSELG_6330 ),
.O(\i2/blk00000001/sig000000c0/CYMUXG_6340 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CY0G (
.I(\i2/blk00000001/sig00000182 ),
.O(\i2/blk00000001/sig000000c0/CY0G_6338 )
);
X_BUF #(
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/sig000000c0/CYSELG (
.I(\i2/blk00000001/sig000000c1 ),
.O(\i2/blk00000001/sig000000c0/CYSELG_6330 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/XUSED (
.I(\i2/blk00000001/sig000000f9/XORF_6390 ),
.O(\i2/blk00000001/sig000000f9 )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/XORF (
.I0(\i2/blk00000001/sig000000f9/CYINIT_6389 ),
.I1(\i2/blk00000001/sig000000bf ),
.O(\i2/blk00000001/sig000000f9/XORF_6390 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYMUXF (
.IA(\i2/blk00000001/sig000000f9/CY0F_6388 ),
.IB(\i2/blk00000001/sig000000f9/CYINIT_6389 ),
.SEL(\i2/blk00000001/sig000000f9/CYSELF_6376 ),
.O(\i2/blk00000001/sig000000be )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYMUXF2 (
.IA(\i2/blk00000001/sig000000f9/CY0F_6388 ),
.IB(\i2/blk00000001/sig000000f9/CY0F_6388 ),
.SEL(\i2/blk00000001/sig000000f9/CYSELF_6376 ),
.O(\i2/blk00000001/sig000000f9/CYMUXF2_6371 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYINIT (
.I(\i2/blk00000001/sig000000c0 ),
.O(\i2/blk00000001/sig000000f9/CYINIT_6389 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CY0F (
.I(\i2/blk00000001/sig00000177 ),
.O(\i2/blk00000001/sig000000f9/CY0F_6388 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYSELF (
.I(\i2/blk00000001/sig000000bf ),
.O(\i2/blk00000001/sig000000f9/CYSELF_6376 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/YUSED (
.I(\i2/blk00000001/sig000000f9/XORG_6378 ),
.O(\i2/blk00000001/sig000000fa )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/XORG (
.I0(\i2/blk00000001/sig000000be ),
.I1(\i2/blk00000001/sig000000bd ),
.O(\i2/blk00000001/sig000000f9/XORG_6378 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/COUTUSED (
.I(\i2/blk00000001/sig000000f9/CYMUXFAST_6375 ),
.O(\i2/blk00000001/sig000000bc )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/FASTCARRY (
.I(\i2/blk00000001/sig000000c0 ),
.O(\i2/blk00000001/sig000000f9/FASTCARRY_6373 )
);
X_AND2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYAND (
.I0(\i2/blk00000001/sig000000f9/CYSELG_6362 ),
.I1(\i2/blk00000001/sig000000f9/CYSELF_6376 ),
.O(\i2/blk00000001/sig000000f9/CYAND_6374 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYMUXFAST (
.IA(\i2/blk00000001/sig000000f9/CYMUXG2_6372 ),
.IB(\i2/blk00000001/sig000000f9/FASTCARRY_6373 ),
.SEL(\i2/blk00000001/sig000000f9/CYAND_6374 ),
.O(\i2/blk00000001/sig000000f9/CYMUXFAST_6375 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYMUXG2 (
.IA(\i2/blk00000001/sig000000f9/CY0G_6370 ),
.IB(\i2/blk00000001/sig000000f9/CYMUXF2_6371 ),
.SEL(\i2/blk00000001/sig000000f9/CYSELG_6362 ),
.O(\i2/blk00000001/sig000000f9/CYMUXG2_6372 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CY0G (
.I(\i2/blk00000001/sig0000016c ),
.O(\i2/blk00000001/sig000000f9/CY0G_6370 )
);
X_BUF #(
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/sig000000f9/CYSELG (
.I(\i2/blk00000001/sig000000bd ),
.O(\i2/blk00000001/sig000000f9/CYSELG_6362 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/XUSED (
.I(\i2/blk00000001/sig000000fb/XORF_6429 ),
.O(\i2/blk00000001/sig000000fb )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/XORF (
.I0(\i2/blk00000001/sig000000fb/CYINIT_6428 ),
.I1(\i2/blk00000001/sig000000bb ),
.O(\i2/blk00000001/sig000000fb/XORF_6429 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYMUXF (
.IA(\i2/blk00000001/sig000000fb/CY0F_6427 ),
.IB(\i2/blk00000001/sig000000fb/CYINIT_6428 ),
.SEL(\i2/blk00000001/sig000000fb/CYSELF_6415 ),
.O(\i2/blk00000001/sig000000ba )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYMUXF2 (
.IA(\i2/blk00000001/sig000000fb/CY0F_6427 ),
.IB(\i2/blk00000001/sig000000fb/CY0F_6427 ),
.SEL(\i2/blk00000001/sig000000fb/CYSELF_6415 ),
.O(\i2/blk00000001/sig000000fb/CYMUXF2_6410 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYINIT (
.I(\i2/blk00000001/sig000000bc ),
.O(\i2/blk00000001/sig000000fb/CYINIT_6428 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CY0F (
.I(\i2/blk00000001/sig00000161 ),
.O(\i2/blk00000001/sig000000fb/CY0F_6427 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYSELF (
.I(\i2/blk00000001/sig000000bb ),
.O(\i2/blk00000001/sig000000fb/CYSELF_6415 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/YUSED (
.I(\i2/blk00000001/sig000000fb/XORG_6417 ),
.O(\i2/blk00000001/sig000000fc )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/XORG (
.I0(\i2/blk00000001/sig000000ba ),
.I1(\i2/blk00000001/sig000000b9 ),
.O(\i2/blk00000001/sig000000fb/XORG_6417 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/COUTUSED (
.I(\i2/blk00000001/sig000000fb/CYMUXFAST_6414 ),
.O(\i2/blk00000001/sig000000b8 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/FASTCARRY (
.I(\i2/blk00000001/sig000000bc ),
.O(\i2/blk00000001/sig000000fb/FASTCARRY_6412 )
);
X_AND2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYAND (
.I0(\i2/blk00000001/sig000000fb/CYSELG_6401 ),
.I1(\i2/blk00000001/sig000000fb/CYSELF_6415 ),
.O(\i2/blk00000001/sig000000fb/CYAND_6413 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYMUXFAST (
.IA(\i2/blk00000001/sig000000fb/CYMUXG2_6411 ),
.IB(\i2/blk00000001/sig000000fb/FASTCARRY_6412 ),
.SEL(\i2/blk00000001/sig000000fb/CYAND_6413 ),
.O(\i2/blk00000001/sig000000fb/CYMUXFAST_6414 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYMUXG2 (
.IA(\i2/blk00000001/sig000000fb/CY0G_6409 ),
.IB(\i2/blk00000001/sig000000fb/CYMUXF2_6410 ),
.SEL(\i2/blk00000001/sig000000fb/CYSELG_6401 ),
.O(\i2/blk00000001/sig000000fb/CYMUXG2_6411 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CY0G (
.I(\i2/blk00000001/sig00000156 ),
.O(\i2/blk00000001/sig000000fb/CY0G_6409 )
);
X_BUF #(
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/sig000000fb/CYSELG (
.I(\i2/blk00000001/sig000000b9 ),
.O(\i2/blk00000001/sig000000fb/CYSELG_6401 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/XUSED (
.I(\i2/blk00000001/sig000000fd/XORF_6468 ),
.O(\i2/blk00000001/sig000000fd )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/XORF (
.I0(\i2/blk00000001/sig000000fd/CYINIT_6467 ),
.I1(\i2/blk00000001/sig000000b7 ),
.O(\i2/blk00000001/sig000000fd/XORF_6468 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYMUXF (
.IA(\i2/blk00000001/sig000000fd/CY0F_6466 ),
.IB(\i2/blk00000001/sig000000fd/CYINIT_6467 ),
.SEL(\i2/blk00000001/sig000000fd/CYSELF_6454 ),
.O(\i2/blk00000001/sig000000b6 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYMUXF2 (
.IA(\i2/blk00000001/sig000000fd/CY0F_6466 ),
.IB(\i2/blk00000001/sig000000fd/CY0F_6466 ),
.SEL(\i2/blk00000001/sig000000fd/CYSELF_6454 ),
.O(\i2/blk00000001/sig000000fd/CYMUXF2_6449 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYINIT (
.I(\i2/blk00000001/sig000000b8 ),
.O(\i2/blk00000001/sig000000fd/CYINIT_6467 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CY0F (
.I(\i2/blk00000001/sig0000014b ),
.O(\i2/blk00000001/sig000000fd/CY0F_6466 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYSELF (
.I(\i2/blk00000001/sig000000b7 ),
.O(\i2/blk00000001/sig000000fd/CYSELF_6454 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/YUSED (
.I(\i2/blk00000001/sig000000fd/XORG_6456 ),
.O(\i2/blk00000001/sig000000fe )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/XORG (
.I0(\i2/blk00000001/sig000000b6 ),
.I1(\i2/blk00000001/sig000000b5 ),
.O(\i2/blk00000001/sig000000fd/XORG_6456 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/COUTUSED (
.I(\i2/blk00000001/sig000000fd/CYMUXFAST_6453 ),
.O(\i2/blk00000001/sig000000b4 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/FASTCARRY (
.I(\i2/blk00000001/sig000000b8 ),
.O(\i2/blk00000001/sig000000fd/FASTCARRY_6451 )
);
X_AND2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYAND (
.I0(\i2/blk00000001/sig000000fd/CYSELG_6440 ),
.I1(\i2/blk00000001/sig000000fd/CYSELF_6454 ),
.O(\i2/blk00000001/sig000000fd/CYAND_6452 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYMUXFAST (
.IA(\i2/blk00000001/sig000000fd/CYMUXG2_6450 ),
.IB(\i2/blk00000001/sig000000fd/FASTCARRY_6451 ),
.SEL(\i2/blk00000001/sig000000fd/CYAND_6452 ),
.O(\i2/blk00000001/sig000000fd/CYMUXFAST_6453 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYMUXG2 (
.IA(\i2/blk00000001/sig000000fd/CY0G_6448 ),
.IB(\i2/blk00000001/sig000000fd/CYMUXF2_6449 ),
.SEL(\i2/blk00000001/sig000000fd/CYSELG_6440 ),
.O(\i2/blk00000001/sig000000fd/CYMUXG2_6450 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CY0G (
.I(\i2/blk00000001/sig00000140 ),
.O(\i2/blk00000001/sig000000fd/CY0G_6448 )
);
X_BUF #(
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/sig000000fd/CYSELG (
.I(\i2/blk00000001/sig000000b5 ),
.O(\i2/blk00000001/sig000000fd/CYSELG_6440 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/XUSED (
.I(\i2/blk00000001/sig000000ff/XORF_6507 ),
.O(\i2/blk00000001/sig000000ff )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/XORF (
.I0(\i2/blk00000001/sig000000ff/CYINIT_6506 ),
.I1(\i2/blk00000001/sig000000b3 ),
.O(\i2/blk00000001/sig000000ff/XORF_6507 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYMUXF (
.IA(\i2/blk00000001/sig000000ff/CY0F_6505 ),
.IB(\i2/blk00000001/sig000000ff/CYINIT_6506 ),
.SEL(\i2/blk00000001/sig000000ff/CYSELF_6493 ),
.O(\i2/blk00000001/sig000000b2 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYMUXF2 (
.IA(\i2/blk00000001/sig000000ff/CY0F_6505 ),
.IB(\i2/blk00000001/sig000000ff/CY0F_6505 ),
.SEL(\i2/blk00000001/sig000000ff/CYSELF_6493 ),
.O(\i2/blk00000001/sig000000ff/CYMUXF2_6488 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYINIT (
.I(\i2/blk00000001/sig000000b4 ),
.O(\i2/blk00000001/sig000000ff/CYINIT_6506 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CY0F (
.I(\i2/blk00000001/sig00000135 ),
.O(\i2/blk00000001/sig000000ff/CY0F_6505 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYSELF (
.I(\i2/blk00000001/sig000000b3 ),
.O(\i2/blk00000001/sig000000ff/CYSELF_6493 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/YUSED (
.I(\i2/blk00000001/sig000000ff/XORG_6495 ),
.O(\i2/blk00000001/sig00000100 )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/XORG (
.I0(\i2/blk00000001/sig000000b2 ),
.I1(\i2/blk00000001/sig000000b1 ),
.O(\i2/blk00000001/sig000000ff/XORG_6495 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/COUTUSED (
.I(\i2/blk00000001/sig000000ff/CYMUXFAST_6492 ),
.O(\i2/blk00000001/sig000000b0 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/FASTCARRY (
.I(\i2/blk00000001/sig000000b4 ),
.O(\i2/blk00000001/sig000000ff/FASTCARRY_6490 )
);
X_AND2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYAND (
.I0(\i2/blk00000001/sig000000ff/CYSELG_6479 ),
.I1(\i2/blk00000001/sig000000ff/CYSELF_6493 ),
.O(\i2/blk00000001/sig000000ff/CYAND_6491 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYMUXFAST (
.IA(\i2/blk00000001/sig000000ff/CYMUXG2_6489 ),
.IB(\i2/blk00000001/sig000000ff/FASTCARRY_6490 ),
.SEL(\i2/blk00000001/sig000000ff/CYAND_6491 ),
.O(\i2/blk00000001/sig000000ff/CYMUXFAST_6492 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYMUXG2 (
.IA(\i2/blk00000001/sig000000ff/CY0G_6487 ),
.IB(\i2/blk00000001/sig000000ff/CYMUXF2_6488 ),
.SEL(\i2/blk00000001/sig000000ff/CYSELG_6479 ),
.O(\i2/blk00000001/sig000000ff/CYMUXG2_6489 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CY0G (
.I(\i2/blk00000001/sig0000012a ),
.O(\i2/blk00000001/sig000000ff/CY0G_6487 )
);
X_BUF #(
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/sig000000ff/CYSELG (
.I(\i2/blk00000001/sig000000b1 ),
.O(\i2/blk00000001/sig000000ff/CYSELG_6479 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/XUSED (
.I(\i2/blk00000001/sig00000101/XORF_6546 ),
.O(\i2/blk00000001/sig00000101 )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/XORF (
.I0(\i2/blk00000001/sig00000101/CYINIT_6545 ),
.I1(\i2/blk00000001/sig000000af ),
.O(\i2/blk00000001/sig00000101/XORF_6546 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYMUXF (
.IA(\i2/blk00000001/sig00000101/CY0F_6544 ),
.IB(\i2/blk00000001/sig00000101/CYINIT_6545 ),
.SEL(\i2/blk00000001/sig00000101/CYSELF_6532 ),
.O(\i2/blk00000001/sig000000ae )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYMUXF2 (
.IA(\i2/blk00000001/sig00000101/CY0F_6544 ),
.IB(\i2/blk00000001/sig00000101/CY0F_6544 ),
.SEL(\i2/blk00000001/sig00000101/CYSELF_6532 ),
.O(\i2/blk00000001/sig00000101/CYMUXF2_6527 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYINIT (
.I(\i2/blk00000001/sig000000b0 ),
.O(\i2/blk00000001/sig00000101/CYINIT_6545 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CY0F (
.I(\i2/blk00000001/sig0000011f ),
.O(\i2/blk00000001/sig00000101/CY0F_6544 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYSELF (
.I(\i2/blk00000001/sig000000af ),
.O(\i2/blk00000001/sig00000101/CYSELF_6532 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/YUSED (
.I(\i2/blk00000001/sig00000101/XORG_6534 ),
.O(\i2/blk00000001/sig00000102 )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/XORG (
.I0(\i2/blk00000001/sig000000ae ),
.I1(\i2/blk00000001/sig000000ad ),
.O(\i2/blk00000001/sig00000101/XORG_6534 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/FASTCARRY (
.I(\i2/blk00000001/sig000000b0 ),
.O(\i2/blk00000001/sig00000101/FASTCARRY_6529 )
);
X_AND2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYAND (
.I0(\i2/blk00000001/sig00000101/CYSELG_6518 ),
.I1(\i2/blk00000001/sig00000101/CYSELF_6532 ),
.O(\i2/blk00000001/sig00000101/CYAND_6530 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYMUXFAST (
.IA(\i2/blk00000001/sig00000101/CYMUXG2_6528 ),
.IB(\i2/blk00000001/sig00000101/FASTCARRY_6529 ),
.SEL(\i2/blk00000001/sig00000101/CYAND_6530 ),
.O(\i2/blk00000001/sig00000101/CYMUXFAST_6531 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYMUXG2 (
.IA(\i2/blk00000001/sig00000101/CY0G_6526 ),
.IB(\i2/blk00000001/sig00000101/CYMUXF2_6527 ),
.SEL(\i2/blk00000001/sig00000101/CYSELG_6518 ),
.O(\i2/blk00000001/sig00000101/CYMUXG2_6528 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CY0G (
.I(\i2/blk00000001/sig00000114 ),
.O(\i2/blk00000001/sig00000101/CY0G_6526 )
);
X_BUF #(
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/sig00000101/CYSELG (
.I(\i2/blk00000001/sig000000ad ),
.O(\i2/blk00000001/sig00000101/CYSELG_6518 )
);
X_BUF #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/XUSED (
.I(\i2/blk00000001/sig00000103/XORF_6577 ),
.O(\i2/blk00000001/sig00000103 )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/XORF (
.I0(\i2/blk00000001/sig00000103/CYINIT_6576 ),
.I1(\i2/blk00000001/sig000000ab ),
.O(\i2/blk00000001/sig00000103/XORF_6577 )
);
X_MUX2 #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/CYMUXF (
.IA(\i2/blk00000001/sig00000103/CY0F_6575 ),
.IB(\i2/blk00000001/sig00000103/CYINIT_6576 ),
.SEL(\i2/blk00000001/sig00000103/CYSELF_6567 ),
.O(\i2/blk00000001/sig000000aa )
);
X_BUF #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/CYINIT (
.I(\i2/blk00000001/sig00000101/CYMUXFAST_6531 ),
.O(\i2/blk00000001/sig00000103/CYINIT_6576 )
);
X_BUF #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/CY0F (
.I(\i2/blk00000001/sig00000114 ),
.O(\i2/blk00000001/sig00000103/CY0F_6575 )
);
X_BUF #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/CYSELF (
.I(\i2/blk00000001/sig000000ab ),
.O(\i2/blk00000001/sig00000103/CYSELF_6567 )
);
X_BUF #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/YUSED (
.I(\i2/blk00000001/sig00000103/XORG_6564 ),
.O(\i2/blk00000001/sig00000104 )
);
X_XOR2 #(
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/sig00000103/XORG (
.I0(\i2/blk00000001/sig000000aa ),
.I1(\i2/blk00000001/sig000000a9 ),
.O(\i2/blk00000001/sig00000103/XORG_6564 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_lut<0> (
.ADR0(t1[11]),
.ADR1(t2[11]),
.ADR2(VCC),
.ADR3(VCC),
.O(\Madd_s2_Madd_lut[0] )
);
X_ZERO #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/LOGIC_ZERO (
.O(\Madd_s2_Madd_cy<1>/LOGIC_ZERO_6594 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/CYMUXF (
.IA(\Madd_s2_Madd_cy<1>/CY0F_6607 ),
.IB(\Madd_s2_Madd_cy<1>/CYINIT_6608 ),
.SEL(\Madd_s2_Madd_cy<1>/CYSELF_6599 ),
.O(\Madd_s2_Madd_cy[0] )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/CYINIT (
.I(\t3<11>/XORG_9786 ),
.O(\Madd_s2_Madd_cy<1>/CYINIT_6608 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/CY0F (
.I(t2[11]),
.O(\Madd_s2_Madd_cy<1>/CY0F_6607 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/CYSELF (
.I(\Madd_s2_Madd_lut[0] ),
.O(\Madd_s2_Madd_cy<1>/CYSELF_6599 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/COUTUSED (
.I(\Madd_s2_Madd_cy<1>/CYMUXG_6596 ),
.O(\Madd_s2_Madd_cy[1] )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/CYMUXG (
.IA(\Madd_s2_Madd_cy<1>/LOGIC_ZERO_6594 ),
.IB(\Madd_s2_Madd_cy[0] ),
.SEL(\Madd_s2_Madd_cy<1>/CYSELG_6587 ),
.O(\Madd_s2_Madd_cy<1>/CYMUXG_6596 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\Madd_s2_Madd_cy<1>/CYSELG (
.I(Madd_s2R),
.O(\Madd_s2_Madd_cy<1>/CYSELG_6587 )
);
X_LUT4 #(
.INIT ( 16'h9966 ),
.LOC ( "SLICE_X19Y25" ))
Madd_s2R11 (
.ADR0(t1[12]),
.ADR1(t2[12]),
.ADR2(VCC),
.ADR3(t3[12]),
.O(Madd_s2R)
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y26" ))
\Madd_s2_Madd_lut<2> (
.ADR0(Madd_s2C_0),
.ADR1(t3[13]),
.ADR2(t2[13]),
.ADR3(t1[13]),
.O(\Madd_s2_Madd_lut[2] )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/XORF (
.I0(\y_0_OBUF/CYINIT_6645 ),
.I1(\Madd_s2_Madd_lut[2] ),
.O(\y_0_OBUF/XORF_6646 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYMUXF (
.IA(\y_0_OBUF/CY0F_6644 ),
.IB(\y_0_OBUF/CYINIT_6645 ),
.SEL(\y_0_OBUF/CYSELF_6634 ),
.O(\Madd_s2_Madd_cy[2] )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYMUXF2 (
.IA(\y_0_OBUF/CY0F_6644 ),
.IB(\y_0_OBUF/CY0F_6644 ),
.SEL(\y_0_OBUF/CYSELF_6634 ),
.O(\y_0_OBUF/CYMUXF2_6629 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYINIT (
.I(\Madd_s2_Madd_cy[1] ),
.O(\y_0_OBUF/CYINIT_6645 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CY0F (
.I(Madd_s2C_0),
.O(\y_0_OBUF/CY0F_6644 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYSELF (
.I(\Madd_s2_Madd_lut[2] ),
.O(\y_0_OBUF/CYSELF_6634 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/XORG (
.I0(\Madd_s2_Madd_cy[2] ),
.I1(\Madd_s2_Madd_lut[3] ),
.O(\y_0_OBUF/XORG_6636 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/COUTUSED (
.I(\y_0_OBUF/CYMUXFAST_6633 ),
.O(\Madd_s2_Madd_cy[3] )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/FASTCARRY (
.I(\Madd_s2_Madd_cy[1] ),
.O(\y_0_OBUF/FASTCARRY_6631 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYAND (
.I0(\y_0_OBUF/CYSELG_6622 ),
.I1(\y_0_OBUF/CYSELF_6634 ),
.O(\y_0_OBUF/CYAND_6632 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYMUXFAST (
.IA(\y_0_OBUF/CYMUXG2_6630 ),
.IB(\y_0_OBUF/FASTCARRY_6631 ),
.SEL(\y_0_OBUF/CYAND_6632 ),
.O(\y_0_OBUF/CYMUXFAST_6633 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYMUXG2 (
.IA(\y_0_OBUF/CY0G_6628 ),
.IB(\y_0_OBUF/CYMUXF2_6629 ),
.SEL(\y_0_OBUF/CYSELG_6622 ),
.O(\y_0_OBUF/CYMUXG2_6630 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CY0G (
.I(Madd_s2C1_0),
.O(\y_0_OBUF/CY0G_6628 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\y_0_OBUF/CYSELG (
.I(\Madd_s2_Madd_lut[3] ),
.O(\y_0_OBUF/CYSELG_6622 )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y26" ))
\Madd_s2_Madd_lut<3> (
.ADR0(Madd_s2C1_0),
.ADR1(t3[14]),
.ADR2(t2[14]),
.ADR3(t1[14]),
.O(\Madd_s2_Madd_lut[3] )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/XORF (
.I0(\y_2_OBUF/CYINIT_6684 ),
.I1(\Madd_s2_Madd_lut[4] ),
.O(\y_2_OBUF/XORF_6685 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYMUXF (
.IA(\y_2_OBUF/CY0F_6683 ),
.IB(\y_2_OBUF/CYINIT_6684 ),
.SEL(\y_2_OBUF/CYSELF_6673 ),
.O(\Madd_s2_Madd_cy[4] )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYMUXF2 (
.IA(\y_2_OBUF/CY0F_6683 ),
.IB(\y_2_OBUF/CY0F_6683 ),
.SEL(\y_2_OBUF/CYSELF_6673 ),
.O(\y_2_OBUF/CYMUXF2_6668 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYINIT (
.I(\Madd_s2_Madd_cy[3] ),
.O(\y_2_OBUF/CYINIT_6684 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CY0F (
.I(Madd_s2C2_0),
.O(\y_2_OBUF/CY0F_6683 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYSELF (
.I(\Madd_s2_Madd_lut[4] ),
.O(\y_2_OBUF/CYSELF_6673 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/XORG (
.I0(\Madd_s2_Madd_cy[4] ),
.I1(\Madd_s2_Madd_lut[5] ),
.O(\y_2_OBUF/XORG_6675 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/COUTUSED (
.I(\y_2_OBUF/CYMUXFAST_6672 ),
.O(\Madd_s2_Madd_cy[5] )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/FASTCARRY (
.I(\Madd_s2_Madd_cy[3] ),
.O(\y_2_OBUF/FASTCARRY_6670 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYAND (
.I0(\y_2_OBUF/CYSELG_6661 ),
.I1(\y_2_OBUF/CYSELF_6673 ),
.O(\y_2_OBUF/CYAND_6671 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYMUXFAST (
.IA(\y_2_OBUF/CYMUXG2_6669 ),
.IB(\y_2_OBUF/FASTCARRY_6670 ),
.SEL(\y_2_OBUF/CYAND_6671 ),
.O(\y_2_OBUF/CYMUXFAST_6672 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYMUXG2 (
.IA(\y_2_OBUF/CY0G_6667 ),
.IB(\y_2_OBUF/CYMUXF2_6668 ),
.SEL(\y_2_OBUF/CYSELG_6661 ),
.O(\y_2_OBUF/CYMUXG2_6669 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CY0G (
.I(Madd_s2C3_0),
.O(\y_2_OBUF/CY0G_6667 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\y_2_OBUF/CYSELG (
.I(\Madd_s2_Madd_lut[5] ),
.O(\y_2_OBUF/CYSELG_6661 )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y27" ))
\Madd_s2_Madd_lut<5> (
.ADR0(t2[16]),
.ADR1(Madd_s2C3_0),
.ADR2(t1[16]),
.ADR3(t3[16]),
.O(\Madd_s2_Madd_lut[5] )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/XORF (
.I0(\y_4_OBUF/CYINIT_6723 ),
.I1(\Madd_s2_Madd_lut[6] ),
.O(\y_4_OBUF/XORF_6724 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYMUXF (
.IA(\y_4_OBUF/CY0F_6722 ),
.IB(\y_4_OBUF/CYINIT_6723 ),
.SEL(\y_4_OBUF/CYSELF_6712 ),
.O(\Madd_s2_Madd_cy[6] )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYMUXF2 (
.IA(\y_4_OBUF/CY0F_6722 ),
.IB(\y_4_OBUF/CY0F_6722 ),
.SEL(\y_4_OBUF/CYSELF_6712 ),
.O(\y_4_OBUF/CYMUXF2_6707 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYINIT (
.I(\Madd_s2_Madd_cy[5] ),
.O(\y_4_OBUF/CYINIT_6723 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CY0F (
.I(Madd_s2C4_0),
.O(\y_4_OBUF/CY0F_6722 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYSELF (
.I(\Madd_s2_Madd_lut[6] ),
.O(\y_4_OBUF/CYSELF_6712 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/XORG (
.I0(\Madd_s2_Madd_cy[6] ),
.I1(\Madd_s2_Madd_lut[7] ),
.O(\y_4_OBUF/XORG_6714 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/COUTUSED (
.I(\y_4_OBUF/CYMUXFAST_6711 ),
.O(\Madd_s2_Madd_cy[7] )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/FASTCARRY (
.I(\Madd_s2_Madd_cy[5] ),
.O(\y_4_OBUF/FASTCARRY_6709 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYAND (
.I0(\y_4_OBUF/CYSELG_6700 ),
.I1(\y_4_OBUF/CYSELF_6712 ),
.O(\y_4_OBUF/CYAND_6710 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYMUXFAST (
.IA(\y_4_OBUF/CYMUXG2_6708 ),
.IB(\y_4_OBUF/FASTCARRY_6709 ),
.SEL(\y_4_OBUF/CYAND_6710 ),
.O(\y_4_OBUF/CYMUXFAST_6711 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYMUXG2 (
.IA(\y_4_OBUF/CY0G_6706 ),
.IB(\y_4_OBUF/CYMUXF2_6707 ),
.SEL(\y_4_OBUF/CYSELG_6700 ),
.O(\y_4_OBUF/CYMUXG2_6708 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CY0G (
.I(Madd_s2C5_0),
.O(\y_4_OBUF/CY0G_6706 )
);
X_BUF #(
.LOC ( "SLICE_X19Y28" ))
\y_4_OBUF/CYSELG (
.I(\Madd_s2_Madd_lut[7] ),
.O(\y_4_OBUF/CYSELG_6700 )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y29" ))
\Madd_s2_Madd_lut<9> (
.ADR0(Madd_s2C7_0),
.ADR1(t2[20]),
.ADR2(t1[20]),
.ADR3(t3[20]),
.O(\Madd_s2_Madd_lut[9] )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y29" ))
\Madd_s2_Madd_lut<8> (
.ADR0(t2[19]),
.ADR1(Madd_s2C6_0),
.ADR2(t3[19]),
.ADR3(t1[19]),
.O(\Madd_s2_Madd_lut[8] )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/XORF (
.I0(\y_6_OBUF/CYINIT_6762 ),
.I1(\Madd_s2_Madd_lut[8] ),
.O(\y_6_OBUF/XORF_6763 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYMUXF (
.IA(\y_6_OBUF/CY0F_6761 ),
.IB(\y_6_OBUF/CYINIT_6762 ),
.SEL(\y_6_OBUF/CYSELF_6751 ),
.O(\Madd_s2_Madd_cy[8] )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYMUXF2 (
.IA(\y_6_OBUF/CY0F_6761 ),
.IB(\y_6_OBUF/CY0F_6761 ),
.SEL(\y_6_OBUF/CYSELF_6751 ),
.O(\y_6_OBUF/CYMUXF2_6746 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYINIT (
.I(\Madd_s2_Madd_cy[7] ),
.O(\y_6_OBUF/CYINIT_6762 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CY0F (
.I(Madd_s2C6_0),
.O(\y_6_OBUF/CY0F_6761 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYSELF (
.I(\Madd_s2_Madd_lut[8] ),
.O(\y_6_OBUF/CYSELF_6751 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/XORG (
.I0(\Madd_s2_Madd_cy[8] ),
.I1(\Madd_s2_Madd_lut[9] ),
.O(\y_6_OBUF/XORG_6753 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/FASTCARRY (
.I(\Madd_s2_Madd_cy[7] ),
.O(\y_6_OBUF/FASTCARRY_6748 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYAND (
.I0(\y_6_OBUF/CYSELG_6739 ),
.I1(\y_6_OBUF/CYSELF_6751 ),
.O(\y_6_OBUF/CYAND_6749 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYMUXFAST (
.IA(\y_6_OBUF/CYMUXG2_6747 ),
.IB(\y_6_OBUF/FASTCARRY_6748 ),
.SEL(\y_6_OBUF/CYAND_6749 ),
.O(\y_6_OBUF/CYMUXFAST_6750 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYMUXG2 (
.IA(\y_6_OBUF/CY0G_6745 ),
.IB(\y_6_OBUF/CYMUXF2_6746 ),
.SEL(\y_6_OBUF/CYSELG_6739 ),
.O(\y_6_OBUF/CYMUXG2_6747 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CY0G (
.I(Madd_s2C7_0),
.O(\y_6_OBUF/CY0G_6745 )
);
X_BUF #(
.LOC ( "SLICE_X19Y29" ))
\y_6_OBUF/CYSELG (
.I(\Madd_s2_Madd_lut[9] ),
.O(\y_6_OBUF/CYSELG_6739 )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y30" ))
\Madd_s2_Madd_lut<10> (
.ADR0(Madd_s2C8_0),
.ADR1(t2[21]),
.ADR2(t3[21]),
.ADR3(t1[21]),
.O(\Madd_s2_Madd_lut[10] )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y30" ))
\y_8_OBUF/XORF (
.I0(\y_8_OBUF/CYINIT_6793 ),
.I1(\Madd_s2_Madd_lut[10] ),
.O(\y_8_OBUF/XORF_6794 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y30" ))
\y_8_OBUF/CYMUXF (
.IA(\y_8_OBUF/CY0F_6792 ),
.IB(\y_8_OBUF/CYINIT_6793 ),
.SEL(\y_8_OBUF/CYSELF_6786 ),
.O(\Madd_s2_Madd_cy[10] )
);
X_BUF #(
.LOC ( "SLICE_X19Y30" ))
\y_8_OBUF/CYINIT (
.I(\y_6_OBUF/CYMUXFAST_6750 ),
.O(\y_8_OBUF/CYINIT_6793 )
);
X_BUF #(
.LOC ( "SLICE_X19Y30" ))
\y_8_OBUF/CY0F (
.I(Madd_s2C8_0),
.O(\y_8_OBUF/CY0F_6792 )
);
X_BUF #(
.LOC ( "SLICE_X19Y30" ))
\y_8_OBUF/CYSELF (
.I(\Madd_s2_Madd_lut[10] ),
.O(\y_8_OBUF/CYSELF_6786 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y30" ))
\y_8_OBUF/XORG (
.I0(\Madd_s2_Madd_cy[10] ),
.I1(\Madd_s2_Madd_lut[11] ),
.O(\y_8_OBUF/XORG_6783 )
);
X_LUT4 #(
.INIT ( 16'h9669 ),
.LOC ( "SLICE_X19Y30" ))
\Madd_s2_Madd_lut<11> (
.ADR0(t2[22]),
.ADR1(t1[22]),
.ADR2(N10_0),
.ADR3(t3[22]),
.O(\Madd_s2_Madd_lut[11] )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CYMUXF (
.IA(\i1/blk00000001/sig0000004e/CY0F_6824 ),
.IB(\i1/blk00000001/sig0000004e/CYINIT_6825 ),
.SEL(\i1/blk00000001/sig0000004e/CYSELF_6816 ),
.O(\i1/blk00000001/sig00000050 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CYINIT (
.I(\i1/blk00000001/sig0000004e/BXINV_6814 ),
.O(\i1/blk00000001/sig0000004e/CYINIT_6825 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CY0F (
.I(\i1/blk00000001/sig000000d2 ),
.O(\i1/blk00000001/sig0000004e/CY0F_6824 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CYSELF (
.I(\i1/blk00000001/sig00000051 ),
.O(\i1/blk00000001/sig0000004e/CYSELF_6816 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig0000004e/BXINV_6814 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/COUTUSED (
.I(\i1/blk00000001/sig0000004e/CYMUXG_6813 ),
.O(\i1/blk00000001/sig0000004e )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CYMUXG (
.IA(\i1/blk00000001/sig0000004e/CY0G_6811 ),
.IB(\i1/blk00000001/sig00000050 ),
.SEL(\i1/blk00000001/sig0000004e/CYSELG_6803 ),
.O(\i1/blk00000001/sig0000004e/CYMUXG_6813 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CY0G (
.I(\i1/blk00000001/sig000000d3 ),
.O(\i1/blk00000001/sig0000004e/CY0G_6811 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/sig0000004e/CYSELG (
.I(\i1/blk00000001/sig0000004f ),
.O(\i1/blk00000001/sig0000004e/CYSELG_6803 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/blk0000011f (
.ADR0(\i1/blk00000001/sig000000d3 ),
.ADR1(\i1/blk00000001/sig00000188 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000004f )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYMUXF (
.IA(\t1<11>/CY0F_6860 ),
.IB(\t1<11>/CYINIT_6861 ),
.SEL(\t1<11>/CYSELF_6848 ),
.O(\i1/blk00000001/sig0000004c )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYMUXF2 (
.IA(\t1<11>/CY0F_6860 ),
.IB(\t1<11>/CY0F_6860 ),
.SEL(\t1<11>/CYSELF_6848 ),
.O(\t1<11>/CYMUXF2_6843 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYINIT (
.I(\i1/blk00000001/sig0000004e ),
.O(\t1<11>/CYINIT_6861 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CY0F (
.I(\i1/blk00000001/sig000000d4 ),
.O(\t1<11>/CY0F_6860 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYSELF (
.I(\i1/blk00000001/sig0000004d ),
.O(\t1<11>/CYSELF_6848 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/YUSED (
.I(\t1<11>/XORG_6850 ),
.O(t1[11])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/XORG (
.I0(\i1/blk00000001/sig0000004c ),
.I1(\i1/blk00000001/sig0000004b ),
.O(\t1<11>/XORG_6850 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/COUTUSED (
.I(\t1<11>/CYMUXFAST_6847 ),
.O(\i1/blk00000001/sig0000004a )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/FASTCARRY (
.I(\i1/blk00000001/sig0000004e ),
.O(\t1<11>/FASTCARRY_6845 )
);
X_AND2 #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYAND (
.I0(\t1<11>/CYSELG_6834 ),
.I1(\t1<11>/CYSELF_6848 ),
.O(\t1<11>/CYAND_6846 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYMUXFAST (
.IA(\t1<11>/CYMUXG2_6844 ),
.IB(\t1<11>/FASTCARRY_6845 ),
.SEL(\t1<11>/CYAND_6846 ),
.O(\t1<11>/CYMUXFAST_6847 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYMUXG2 (
.IA(\t1<11>/CY0G_6842 ),
.IB(\t1<11>/CYMUXF2_6843 ),
.SEL(\t1<11>/CYSELG_6834 ),
.O(\t1<11>/CYMUXG2_6844 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CY0G (
.I(\i1/blk00000001/sig000000d5 ),
.O(\t1<11>/CY0G_6842 )
);
X_BUF #(
.LOC ( "SLICE_X16Y12" ))
\t1<11>/CYSELG (
.I(\i1/blk00000001/sig0000004b ),
.O(\t1<11>/CYSELG_6834 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/XUSED (
.I(\t1<12>/XORF_6899 ),
.O(t1[12])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/XORF (
.I0(\t1<12>/CYINIT_6898 ),
.I1(\i1/blk00000001/sig00000049 ),
.O(\t1<12>/XORF_6899 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYMUXF (
.IA(\t1<12>/CY0F_6897 ),
.IB(\t1<12>/CYINIT_6898 ),
.SEL(\t1<12>/CYSELF_6885 ),
.O(\i1/blk00000001/sig00000048 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYMUXF2 (
.IA(\t1<12>/CY0F_6897 ),
.IB(\t1<12>/CY0F_6897 ),
.SEL(\t1<12>/CYSELF_6885 ),
.O(\t1<12>/CYMUXF2_6880 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYINIT (
.I(\i1/blk00000001/sig0000004a ),
.O(\t1<12>/CYINIT_6898 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CY0F (
.I(\i1/blk00000001/sig000000d6 ),
.O(\t1<12>/CY0F_6897 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYSELF (
.I(\i1/blk00000001/sig00000049 ),
.O(\t1<12>/CYSELF_6885 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/YUSED (
.I(\t1<12>/XORG_6887 ),
.O(t1[13])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/XORG (
.I0(\i1/blk00000001/sig00000048 ),
.I1(\i1/blk00000001/sig00000047 ),
.O(\t1<12>/XORG_6887 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/COUTUSED (
.I(\t1<12>/CYMUXFAST_6884 ),
.O(\i1/blk00000001/sig00000046 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/FASTCARRY (
.I(\i1/blk00000001/sig0000004a ),
.O(\t1<12>/FASTCARRY_6882 )
);
X_AND2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYAND (
.I0(\t1<12>/CYSELG_6871 ),
.I1(\t1<12>/CYSELF_6885 ),
.O(\t1<12>/CYAND_6883 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYMUXFAST (
.IA(\t1<12>/CYMUXG2_6881 ),
.IB(\t1<12>/FASTCARRY_6882 ),
.SEL(\t1<12>/CYAND_6883 ),
.O(\t1<12>/CYMUXFAST_6884 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYMUXG2 (
.IA(\t1<12>/CY0G_6879 ),
.IB(\t1<12>/CYMUXF2_6880 ),
.SEL(\t1<12>/CYSELG_6871 ),
.O(\t1<12>/CYMUXG2_6881 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CY0G (
.I(\i1/blk00000001/sig000000d7 ),
.O(\t1<12>/CY0G_6879 )
);
X_BUF #(
.LOC ( "SLICE_X16Y13" ))
\t1<12>/CYSELG (
.I(\i1/blk00000001/sig00000047 ),
.O(\t1<12>/CYSELG_6871 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/XUSED (
.I(\t1<14>/XORF_6938 ),
.O(t1[14])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/XORF (
.I0(\t1<14>/CYINIT_6937 ),
.I1(\i1/blk00000001/sig00000045 ),
.O(\t1<14>/XORF_6938 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYMUXF (
.IA(\t1<14>/CY0F_6936 ),
.IB(\t1<14>/CYINIT_6937 ),
.SEL(\t1<14>/CYSELF_6924 ),
.O(\i1/blk00000001/sig00000044 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYMUXF2 (
.IA(\t1<14>/CY0F_6936 ),
.IB(\t1<14>/CY0F_6936 ),
.SEL(\t1<14>/CYSELF_6924 ),
.O(\t1<14>/CYMUXF2_6919 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYINIT (
.I(\i1/blk00000001/sig00000046 ),
.O(\t1<14>/CYINIT_6937 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CY0F (
.I(\i1/blk00000001/sig000000d8 ),
.O(\t1<14>/CY0F_6936 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYSELF (
.I(\i1/blk00000001/sig00000045 ),
.O(\t1<14>/CYSELF_6924 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/YUSED (
.I(\t1<14>/XORG_6926 ),
.O(t1[15])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/XORG (
.I0(\i1/blk00000001/sig00000044 ),
.I1(\i1/blk00000001/sig00000043 ),
.O(\t1<14>/XORG_6926 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/COUTUSED (
.I(\t1<14>/CYMUXFAST_6923 ),
.O(\i1/blk00000001/sig00000042 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/FASTCARRY (
.I(\i1/blk00000001/sig00000046 ),
.O(\t1<14>/FASTCARRY_6921 )
);
X_AND2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYAND (
.I0(\t1<14>/CYSELG_6910 ),
.I1(\t1<14>/CYSELF_6924 ),
.O(\t1<14>/CYAND_6922 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYMUXFAST (
.IA(\t1<14>/CYMUXG2_6920 ),
.IB(\t1<14>/FASTCARRY_6921 ),
.SEL(\t1<14>/CYAND_6922 ),
.O(\t1<14>/CYMUXFAST_6923 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYMUXG2 (
.IA(\t1<14>/CY0G_6918 ),
.IB(\t1<14>/CYMUXF2_6919 ),
.SEL(\t1<14>/CYSELG_6910 ),
.O(\t1<14>/CYMUXG2_6920 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CY0G (
.I(\i1/blk00000001/sig000000d9 ),
.O(\t1<14>/CY0G_6918 )
);
X_BUF #(
.LOC ( "SLICE_X16Y14" ))
\t1<14>/CYSELG (
.I(\i1/blk00000001/sig00000043 ),
.O(\t1<14>/CYSELG_6910 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/XUSED (
.I(\t1<16>/XORF_6977 ),
.O(t1[16])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/XORF (
.I0(\t1<16>/CYINIT_6976 ),
.I1(\i1/blk00000001/sig00000041 ),
.O(\t1<16>/XORF_6977 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYMUXF (
.IA(\t1<16>/CY0F_6975 ),
.IB(\t1<16>/CYINIT_6976 ),
.SEL(\t1<16>/CYSELF_6963 ),
.O(\i1/blk00000001/sig00000040 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYMUXF2 (
.IA(\t1<16>/CY0F_6975 ),
.IB(\t1<16>/CY0F_6975 ),
.SEL(\t1<16>/CYSELF_6963 ),
.O(\t1<16>/CYMUXF2_6958 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYINIT (
.I(\i1/blk00000001/sig00000042 ),
.O(\t1<16>/CYINIT_6976 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CY0F (
.I(\i1/blk00000001/sig000000da ),
.O(\t1<16>/CY0F_6975 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYSELF (
.I(\i1/blk00000001/sig00000041 ),
.O(\t1<16>/CYSELF_6963 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/YUSED (
.I(\t1<16>/XORG_6965 ),
.O(t1[17])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/XORG (
.I0(\i1/blk00000001/sig00000040 ),
.I1(\i1/blk00000001/sig0000003f ),
.O(\t1<16>/XORG_6965 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/COUTUSED (
.I(\t1<16>/CYMUXFAST_6962 ),
.O(\i1/blk00000001/sig0000003e )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/FASTCARRY (
.I(\i1/blk00000001/sig00000042 ),
.O(\t1<16>/FASTCARRY_6960 )
);
X_AND2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYAND (
.I0(\t1<16>/CYSELG_6949 ),
.I1(\t1<16>/CYSELF_6963 ),
.O(\t1<16>/CYAND_6961 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYMUXFAST (
.IA(\t1<16>/CYMUXG2_6959 ),
.IB(\t1<16>/FASTCARRY_6960 ),
.SEL(\t1<16>/CYAND_6961 ),
.O(\t1<16>/CYMUXFAST_6962 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYMUXG2 (
.IA(\t1<16>/CY0G_6957 ),
.IB(\t1<16>/CYMUXF2_6958 ),
.SEL(\t1<16>/CYSELG_6949 ),
.O(\t1<16>/CYMUXG2_6959 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CY0G (
.I(\i1/blk00000001/sig000000db ),
.O(\t1<16>/CY0G_6957 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\t1<16>/CYSELG (
.I(\i1/blk00000001/sig0000003f ),
.O(\t1<16>/CYSELG_6949 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/XUSED (
.I(\t1<18>/XORF_7016 ),
.O(t1[18])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/XORF (
.I0(\t1<18>/CYINIT_7015 ),
.I1(\i1/blk00000001/sig0000003d ),
.O(\t1<18>/XORF_7016 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYMUXF (
.IA(\t1<18>/CY0F_7014 ),
.IB(\t1<18>/CYINIT_7015 ),
.SEL(\t1<18>/CYSELF_7002 ),
.O(\i1/blk00000001/sig0000003c )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYMUXF2 (
.IA(\t1<18>/CY0F_7014 ),
.IB(\t1<18>/CY0F_7014 ),
.SEL(\t1<18>/CYSELF_7002 ),
.O(\t1<18>/CYMUXF2_6997 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYINIT (
.I(\i1/blk00000001/sig0000003e ),
.O(\t1<18>/CYINIT_7015 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CY0F (
.I(\i1/blk00000001/sig000000dc ),
.O(\t1<18>/CY0F_7014 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYSELF (
.I(\i1/blk00000001/sig0000003d ),
.O(\t1<18>/CYSELF_7002 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/YUSED (
.I(\t1<18>/XORG_7004 ),
.O(t1[19])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/XORG (
.I0(\i1/blk00000001/sig0000003c ),
.I1(\i1/blk00000001/sig0000003b ),
.O(\t1<18>/XORG_7004 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/COUTUSED (
.I(\t1<18>/CYMUXFAST_7001 ),
.O(\i1/blk00000001/sig0000003a )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/FASTCARRY (
.I(\i1/blk00000001/sig0000003e ),
.O(\t1<18>/FASTCARRY_6999 )
);
X_AND2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYAND (
.I0(\t1<18>/CYSELG_6988 ),
.I1(\t1<18>/CYSELF_7002 ),
.O(\t1<18>/CYAND_7000 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYMUXFAST (
.IA(\t1<18>/CYMUXG2_6998 ),
.IB(\t1<18>/FASTCARRY_6999 ),
.SEL(\t1<18>/CYAND_7000 ),
.O(\t1<18>/CYMUXFAST_7001 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYMUXG2 (
.IA(\t1<18>/CY0G_6996 ),
.IB(\t1<18>/CYMUXF2_6997 ),
.SEL(\t1<18>/CYSELG_6988 ),
.O(\t1<18>/CYMUXG2_6998 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CY0G (
.I(\i1/blk00000001/sig000000dd ),
.O(\t1<18>/CY0G_6996 )
);
X_BUF #(
.LOC ( "SLICE_X16Y16" ))
\t1<18>/CYSELG (
.I(\i1/blk00000001/sig0000003b ),
.O(\t1<18>/CYSELG_6988 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/XUSED (
.I(\t1<20>/XORF_7055 ),
.O(t1[20])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/XORF (
.I0(\t1<20>/CYINIT_7054 ),
.I1(\i1/blk00000001/sig00000039 ),
.O(\t1<20>/XORF_7055 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYMUXF (
.IA(\t1<20>/CY0F_7053 ),
.IB(\t1<20>/CYINIT_7054 ),
.SEL(\t1<20>/CYSELF_7041 ),
.O(\i1/blk00000001/sig00000038 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYMUXF2 (
.IA(\t1<20>/CY0F_7053 ),
.IB(\t1<20>/CY0F_7053 ),
.SEL(\t1<20>/CYSELF_7041 ),
.O(\t1<20>/CYMUXF2_7036 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYINIT (
.I(\i1/blk00000001/sig0000003a ),
.O(\t1<20>/CYINIT_7054 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CY0F (
.I(\i1/blk00000001/sig000000de ),
.O(\t1<20>/CY0F_7053 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYSELF (
.I(\i1/blk00000001/sig00000039 ),
.O(\t1<20>/CYSELF_7041 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/YUSED (
.I(\t1<20>/XORG_7043 ),
.O(t1[21])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/XORG (
.I0(\i1/blk00000001/sig00000038 ),
.I1(\i1/blk00000001/sig00000037 ),
.O(\t1<20>/XORG_7043 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/FASTCARRY (
.I(\i1/blk00000001/sig0000003a ),
.O(\t1<20>/FASTCARRY_7038 )
);
X_AND2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYAND (
.I0(\t1<20>/CYSELG_7027 ),
.I1(\t1<20>/CYSELF_7041 ),
.O(\t1<20>/CYAND_7039 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYMUXFAST (
.IA(\t1<20>/CYMUXG2_7037 ),
.IB(\t1<20>/FASTCARRY_7038 ),
.SEL(\t1<20>/CYAND_7039 ),
.O(\t1<20>/CYMUXFAST_7040 )
);
X_MUX2 #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYMUXG2 (
.IA(\t1<20>/CY0G_7035 ),
.IB(\t1<20>/CYMUXF2_7036 ),
.SEL(\t1<20>/CYSELG_7027 ),
.O(\t1<20>/CYMUXG2_7037 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CY0G (
.I(\i1/blk00000001/sig000000de ),
.O(\t1<20>/CY0G_7035 )
);
X_BUF #(
.LOC ( "SLICE_X16Y17" ))
\t1<20>/CYSELG (
.I(\i1/blk00000001/sig00000037 ),
.O(\t1<20>/CYSELG_7027 )
);
X_BUF #(
.LOC ( "SLICE_X16Y18" ))
\t1<22>/XUSED (
.I(\t1<22>/XORF_7070 ),
.O(t1[22])
);
X_XOR2 #(
.LOC ( "SLICE_X16Y18" ))
\t1<22>/XORF (
.I0(\t1<22>/CYINIT_7069 ),
.I1(\i1/blk00000001/sig00000035 ),
.O(\t1<22>/XORF_7070 )
);
X_BUF #(
.LOC ( "SLICE_X16Y18" ))
\t1<22>/CYINIT (
.I(\t1<20>/CYMUXFAST_7040 ),
.O(\t1<22>/CYINIT_7069 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CYMUXF (
.IA(\i1/blk00000001/sig0000006f/CY0F_7100 ),
.IB(\i1/blk00000001/sig0000006f/CYINIT_7101 ),
.SEL(\i1/blk00000001/sig0000006f/CYSELF_7092 ),
.O(\i1/blk00000001/sig00000071 )
);
X_BUF #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CYINIT (
.I(\i1/blk00000001/sig0000006f/BXINV_7090 ),
.O(\i1/blk00000001/sig0000006f/CYINIT_7101 )
);
X_BUF #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CY0F (
.I(\i1/blk00000001/sig000000f9 ),
.O(\i1/blk00000001/sig0000006f/CY0F_7100 )
);
X_BUF #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CYSELF (
.I(\i1/blk00000001/sig00000072 ),
.O(\i1/blk00000001/sig0000006f/CYSELF_7092 )
);
X_BUF #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig0000006f/BXINV_7090 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CYMUXG (
.IA(\i1/blk00000001/sig0000006f/CY0G_7087 ),
.IB(\i1/blk00000001/sig00000071 ),
.SEL(\i1/blk00000001/sig0000006f/CYSELG_7079 ),
.O(\i1/blk00000001/sig0000006f/CYMUXG_7089 )
);
X_BUF #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CY0G (
.I(\i1/blk00000001/sig000000fa ),
.O(\i1/blk00000001/sig0000006f/CY0G_7087 )
);
X_BUF #(
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/sig0000006f/CYSELG (
.I(\i1/blk00000001/sig00000070 ),
.O(\i1/blk00000001/sig0000006f/CYSELG_7079 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CYMUXF2 (
.IA(\i1/blk00000001/sig0000006b/CY0F_7132 ),
.IB(\i1/blk00000001/sig0000006b/CY0F_7132 ),
.SEL(\i1/blk00000001/sig0000006b/CYSELF_7123 ),
.O(\i1/blk00000001/sig0000006b/CYMUXF2_7118 )
);
X_BUF #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CY0F (
.I(\i1/blk00000001/sig000000fb ),
.O(\i1/blk00000001/sig0000006b/CY0F_7132 )
);
X_BUF #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CYSELF (
.I(\i1/blk00000001/sig0000006e ),
.O(\i1/blk00000001/sig0000006b/CYSELF_7123 )
);
X_BUF #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/COUTUSED (
.I(\i1/blk00000001/sig0000006b/CYMUXFAST_7122 ),
.O(\i1/blk00000001/sig0000006b )
);
X_BUF #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/FASTCARRY (
.I(\i1/blk00000001/sig0000006f/CYMUXG_7089 ),
.O(\i1/blk00000001/sig0000006b/FASTCARRY_7120 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CYAND (
.I0(\i1/blk00000001/sig0000006b/CYSELG_7109 ),
.I1(\i1/blk00000001/sig0000006b/CYSELF_7123 ),
.O(\i1/blk00000001/sig0000006b/CYAND_7121 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CYMUXFAST (
.IA(\i1/blk00000001/sig0000006b/CYMUXG2_7119 ),
.IB(\i1/blk00000001/sig0000006b/FASTCARRY_7120 ),
.SEL(\i1/blk00000001/sig0000006b/CYAND_7121 ),
.O(\i1/blk00000001/sig0000006b/CYMUXFAST_7122 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CYMUXG2 (
.IA(\i1/blk00000001/sig0000006b/CY0G_7117 ),
.IB(\i1/blk00000001/sig0000006b/CYMUXF2_7118 ),
.SEL(\i1/blk00000001/sig0000006b/CYSELG_7109 ),
.O(\i1/blk00000001/sig0000006b/CYMUXG2_7119 )
);
X_BUF #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CY0G (
.I(\i1/blk00000001/sig000000fc ),
.O(\i1/blk00000001/sig0000006b/CY0G_7117 )
);
X_BUF #(
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/sig0000006b/CYSELG (
.I(\i1/blk00000001/sig0000006c ),
.O(\i1/blk00000001/sig0000006b/CYSELG_7109 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/XUSED (
.I(\i1/blk00000001/sig000000d2/XORF_7170 ),
.O(\i1/blk00000001/sig000000d2 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/XORF (
.I0(\i1/blk00000001/sig000000d2/CYINIT_7169 ),
.I1(\i1/blk00000001/sig0000006a ),
.O(\i1/blk00000001/sig000000d2/XORF_7170 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYMUXF (
.IA(\i1/blk00000001/sig000000d2/CY0F_7168 ),
.IB(\i1/blk00000001/sig000000d2/CYINIT_7169 ),
.SEL(\i1/blk00000001/sig000000d2/CYSELF_7156 ),
.O(\i1/blk00000001/sig00000069 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYMUXF2 (
.IA(\i1/blk00000001/sig000000d2/CY0F_7168 ),
.IB(\i1/blk00000001/sig000000d2/CY0F_7168 ),
.SEL(\i1/blk00000001/sig000000d2/CYSELF_7156 ),
.O(\i1/blk00000001/sig000000d2/CYMUXF2_7151 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYINIT (
.I(\i1/blk00000001/sig0000006b ),
.O(\i1/blk00000001/sig000000d2/CYINIT_7169 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CY0F (
.I(\i1/blk00000001/sig000000fd ),
.O(\i1/blk00000001/sig000000d2/CY0F_7168 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYSELF (
.I(\i1/blk00000001/sig0000006a ),
.O(\i1/blk00000001/sig000000d2/CYSELF_7156 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/YUSED (
.I(\i1/blk00000001/sig000000d2/XORG_7158 ),
.O(\i1/blk00000001/sig000000d3 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/XORG (
.I0(\i1/blk00000001/sig00000069 ),
.I1(\i1/blk00000001/sig00000068 ),
.O(\i1/blk00000001/sig000000d2/XORG_7158 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/COUTUSED (
.I(\i1/blk00000001/sig000000d2/CYMUXFAST_7155 ),
.O(\i1/blk00000001/sig00000067 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/FASTCARRY (
.I(\i1/blk00000001/sig0000006b ),
.O(\i1/blk00000001/sig000000d2/FASTCARRY_7153 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYAND (
.I0(\i1/blk00000001/sig000000d2/CYSELG_7142 ),
.I1(\i1/blk00000001/sig000000d2/CYSELF_7156 ),
.O(\i1/blk00000001/sig000000d2/CYAND_7154 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYMUXFAST (
.IA(\i1/blk00000001/sig000000d2/CYMUXG2_7152 ),
.IB(\i1/blk00000001/sig000000d2/FASTCARRY_7153 ),
.SEL(\i1/blk00000001/sig000000d2/CYAND_7154 ),
.O(\i1/blk00000001/sig000000d2/CYMUXFAST_7155 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYMUXG2 (
.IA(\i1/blk00000001/sig000000d2/CY0G_7150 ),
.IB(\i1/blk00000001/sig000000d2/CYMUXF2_7151 ),
.SEL(\i1/blk00000001/sig000000d2/CYSELG_7142 ),
.O(\i1/blk00000001/sig000000d2/CYMUXG2_7152 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CY0G (
.I(\i1/blk00000001/sig000000fe ),
.O(\i1/blk00000001/sig000000d2/CY0G_7150 )
);
X_BUF #(
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/sig000000d2/CYSELG (
.I(\i1/blk00000001/sig00000068 ),
.O(\i1/blk00000001/sig000000d2/CYSELG_7142 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/XUSED (
.I(\i1/blk00000001/sig000000d4/XORF_7209 ),
.O(\i1/blk00000001/sig000000d4 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/XORF (
.I0(\i1/blk00000001/sig000000d4/CYINIT_7208 ),
.I1(\i1/blk00000001/sig00000066 ),
.O(\i1/blk00000001/sig000000d4/XORF_7209 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYMUXF (
.IA(\i1/blk00000001/sig000000d4/CY0F_7207 ),
.IB(\i1/blk00000001/sig000000d4/CYINIT_7208 ),
.SEL(\i1/blk00000001/sig000000d4/CYSELF_7195 ),
.O(\i1/blk00000001/sig00000065 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYMUXF2 (
.IA(\i1/blk00000001/sig000000d4/CY0F_7207 ),
.IB(\i1/blk00000001/sig000000d4/CY0F_7207 ),
.SEL(\i1/blk00000001/sig000000d4/CYSELF_7195 ),
.O(\i1/blk00000001/sig000000d4/CYMUXF2_7190 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYINIT (
.I(\i1/blk00000001/sig00000067 ),
.O(\i1/blk00000001/sig000000d4/CYINIT_7208 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CY0F (
.I(\i1/blk00000001/sig000000ff ),
.O(\i1/blk00000001/sig000000d4/CY0F_7207 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYSELF (
.I(\i1/blk00000001/sig00000066 ),
.O(\i1/blk00000001/sig000000d4/CYSELF_7195 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/YUSED (
.I(\i1/blk00000001/sig000000d4/XORG_7197 ),
.O(\i1/blk00000001/sig000000d5 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/XORG (
.I0(\i1/blk00000001/sig00000065 ),
.I1(\i1/blk00000001/sig00000064 ),
.O(\i1/blk00000001/sig000000d4/XORG_7197 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/COUTUSED (
.I(\i1/blk00000001/sig000000d4/CYMUXFAST_7194 ),
.O(\i1/blk00000001/sig00000063 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/FASTCARRY (
.I(\i1/blk00000001/sig00000067 ),
.O(\i1/blk00000001/sig000000d4/FASTCARRY_7192 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYAND (
.I0(\i1/blk00000001/sig000000d4/CYSELG_7181 ),
.I1(\i1/blk00000001/sig000000d4/CYSELF_7195 ),
.O(\i1/blk00000001/sig000000d4/CYAND_7193 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYMUXFAST (
.IA(\i1/blk00000001/sig000000d4/CYMUXG2_7191 ),
.IB(\i1/blk00000001/sig000000d4/FASTCARRY_7192 ),
.SEL(\i1/blk00000001/sig000000d4/CYAND_7193 ),
.O(\i1/blk00000001/sig000000d4/CYMUXFAST_7194 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYMUXG2 (
.IA(\i1/blk00000001/sig000000d4/CY0G_7189 ),
.IB(\i1/blk00000001/sig000000d4/CYMUXF2_7190 ),
.SEL(\i1/blk00000001/sig000000d4/CYSELG_7181 ),
.O(\i1/blk00000001/sig000000d4/CYMUXG2_7191 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CY0G (
.I(\i1/blk00000001/sig00000100 ),
.O(\i1/blk00000001/sig000000d4/CY0G_7189 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/sig000000d4/CYSELG (
.I(\i1/blk00000001/sig00000064 ),
.O(\i1/blk00000001/sig000000d4/CYSELG_7181 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/XUSED (
.I(\i1/blk00000001/sig000000d6/XORF_7248 ),
.O(\i1/blk00000001/sig000000d6 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/XORF (
.I0(\i1/blk00000001/sig000000d6/CYINIT_7247 ),
.I1(\i1/blk00000001/sig00000062 ),
.O(\i1/blk00000001/sig000000d6/XORF_7248 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYMUXF (
.IA(\i1/blk00000001/sig000000d6/CY0F_7246 ),
.IB(\i1/blk00000001/sig000000d6/CYINIT_7247 ),
.SEL(\i1/blk00000001/sig000000d6/CYSELF_7234 ),
.O(\i1/blk00000001/sig00000061 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYMUXF2 (
.IA(\i1/blk00000001/sig000000d6/CY0F_7246 ),
.IB(\i1/blk00000001/sig000000d6/CY0F_7246 ),
.SEL(\i1/blk00000001/sig000000d6/CYSELF_7234 ),
.O(\i1/blk00000001/sig000000d6/CYMUXF2_7229 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYINIT (
.I(\i1/blk00000001/sig00000063 ),
.O(\i1/blk00000001/sig000000d6/CYINIT_7247 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CY0F (
.I(\i1/blk00000001/sig00000101 ),
.O(\i1/blk00000001/sig000000d6/CY0F_7246 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYSELF (
.I(\i1/blk00000001/sig00000062 ),
.O(\i1/blk00000001/sig000000d6/CYSELF_7234 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/YUSED (
.I(\i1/blk00000001/sig000000d6/XORG_7236 ),
.O(\i1/blk00000001/sig000000d7 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/XORG (
.I0(\i1/blk00000001/sig00000061 ),
.I1(\i1/blk00000001/sig00000060 ),
.O(\i1/blk00000001/sig000000d6/XORG_7236 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/COUTUSED (
.I(\i1/blk00000001/sig000000d6/CYMUXFAST_7233 ),
.O(\i1/blk00000001/sig0000005f )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/FASTCARRY (
.I(\i1/blk00000001/sig00000063 ),
.O(\i1/blk00000001/sig000000d6/FASTCARRY_7231 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYAND (
.I0(\i1/blk00000001/sig000000d6/CYSELG_7220 ),
.I1(\i1/blk00000001/sig000000d6/CYSELF_7234 ),
.O(\i1/blk00000001/sig000000d6/CYAND_7232 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYMUXFAST (
.IA(\i1/blk00000001/sig000000d6/CYMUXG2_7230 ),
.IB(\i1/blk00000001/sig000000d6/FASTCARRY_7231 ),
.SEL(\i1/blk00000001/sig000000d6/CYAND_7232 ),
.O(\i1/blk00000001/sig000000d6/CYMUXFAST_7233 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYMUXG2 (
.IA(\i1/blk00000001/sig000000d6/CY0G_7228 ),
.IB(\i1/blk00000001/sig000000d6/CYMUXF2_7229 ),
.SEL(\i1/blk00000001/sig000000d6/CYSELG_7220 ),
.O(\i1/blk00000001/sig000000d6/CYMUXG2_7230 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CY0G (
.I(\i1/blk00000001/sig00000102 ),
.O(\i1/blk00000001/sig000000d6/CY0G_7228 )
);
X_BUF #(
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/sig000000d6/CYSELG (
.I(\i1/blk00000001/sig00000060 ),
.O(\i1/blk00000001/sig000000d6/CYSELG_7220 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/XUSED (
.I(\i1/blk00000001/sig000000d8/XORF_7287 ),
.O(\i1/blk00000001/sig000000d8 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/XORF (
.I0(\i1/blk00000001/sig000000d8/CYINIT_7286 ),
.I1(\i1/blk00000001/sig0000005e ),
.O(\i1/blk00000001/sig000000d8/XORF_7287 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYMUXF (
.IA(\i1/blk00000001/sig000000d8/CY0F_7285 ),
.IB(\i1/blk00000001/sig000000d8/CYINIT_7286 ),
.SEL(\i1/blk00000001/sig000000d8/CYSELF_7273 ),
.O(\i1/blk00000001/sig0000005d )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYMUXF2 (
.IA(\i1/blk00000001/sig000000d8/CY0F_7285 ),
.IB(\i1/blk00000001/sig000000d8/CY0F_7285 ),
.SEL(\i1/blk00000001/sig000000d8/CYSELF_7273 ),
.O(\i1/blk00000001/sig000000d8/CYMUXF2_7268 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYINIT (
.I(\i1/blk00000001/sig0000005f ),
.O(\i1/blk00000001/sig000000d8/CYINIT_7286 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CY0F (
.I(\i1/blk00000001/sig00000103 ),
.O(\i1/blk00000001/sig000000d8/CY0F_7285 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYSELF (
.I(\i1/blk00000001/sig0000005e ),
.O(\i1/blk00000001/sig000000d8/CYSELF_7273 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/YUSED (
.I(\i1/blk00000001/sig000000d8/XORG_7275 ),
.O(\i1/blk00000001/sig000000d9 )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/XORG (
.I0(\i1/blk00000001/sig0000005d ),
.I1(\i1/blk00000001/sig0000005c ),
.O(\i1/blk00000001/sig000000d8/XORG_7275 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/COUTUSED (
.I(\i1/blk00000001/sig000000d8/CYMUXFAST_7272 ),
.O(\i1/blk00000001/sig0000005b )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/FASTCARRY (
.I(\i1/blk00000001/sig0000005f ),
.O(\i1/blk00000001/sig000000d8/FASTCARRY_7270 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYAND (
.I0(\i1/blk00000001/sig000000d8/CYSELG_7259 ),
.I1(\i1/blk00000001/sig000000d8/CYSELF_7273 ),
.O(\i1/blk00000001/sig000000d8/CYAND_7271 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYMUXFAST (
.IA(\i1/blk00000001/sig000000d8/CYMUXG2_7269 ),
.IB(\i1/blk00000001/sig000000d8/FASTCARRY_7270 ),
.SEL(\i1/blk00000001/sig000000d8/CYAND_7271 ),
.O(\i1/blk00000001/sig000000d8/CYMUXFAST_7272 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYMUXG2 (
.IA(\i1/blk00000001/sig000000d8/CY0G_7267 ),
.IB(\i1/blk00000001/sig000000d8/CYMUXF2_7268 ),
.SEL(\i1/blk00000001/sig000000d8/CYSELG_7259 ),
.O(\i1/blk00000001/sig000000d8/CYMUXG2_7269 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CY0G (
.I(\i1/blk00000001/sig00000104 ),
.O(\i1/blk00000001/sig000000d8/CY0G_7267 )
);
X_BUF #(
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/sig000000d8/CYSELG (
.I(\i1/blk00000001/sig0000005c ),
.O(\i1/blk00000001/sig000000d8/CYSELG_7259 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/XUSED (
.I(\i1/blk00000001/sig000000da/XORF_7326 ),
.O(\i1/blk00000001/sig000000da )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/XORF (
.I0(\i1/blk00000001/sig000000da/CYINIT_7325 ),
.I1(\i1/blk00000001/sig0000005a ),
.O(\i1/blk00000001/sig000000da/XORF_7326 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYMUXF (
.IA(\i1/blk00000001/sig000000da/CY0F_7324 ),
.IB(\i1/blk00000001/sig000000da/CYINIT_7325 ),
.SEL(\i1/blk00000001/sig000000da/CYSELF_7312 ),
.O(\i1/blk00000001/sig00000059 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYMUXF2 (
.IA(\i1/blk00000001/sig000000da/CY0F_7324 ),
.IB(\i1/blk00000001/sig000000da/CY0F_7324 ),
.SEL(\i1/blk00000001/sig000000da/CYSELF_7312 ),
.O(\i1/blk00000001/sig000000da/CYMUXF2_7307 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYINIT (
.I(\i1/blk00000001/sig0000005b ),
.O(\i1/blk00000001/sig000000da/CYINIT_7325 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CY0F (
.I(\i1/blk00000001/sig00000104 ),
.O(\i1/blk00000001/sig000000da/CY0F_7324 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYSELF (
.I(\i1/blk00000001/sig0000005a ),
.O(\i1/blk00000001/sig000000da/CYSELF_7312 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/YUSED (
.I(\i1/blk00000001/sig000000da/XORG_7314 ),
.O(\i1/blk00000001/sig000000db )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/XORG (
.I0(\i1/blk00000001/sig00000059 ),
.I1(\i1/blk00000001/sig00000058 ),
.O(\i1/blk00000001/sig000000da/XORG_7314 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/COUTUSED (
.I(\i1/blk00000001/sig000000da/CYMUXFAST_7311 ),
.O(\i1/blk00000001/sig00000057 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/FASTCARRY (
.I(\i1/blk00000001/sig0000005b ),
.O(\i1/blk00000001/sig000000da/FASTCARRY_7309 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYAND (
.I0(\i1/blk00000001/sig000000da/CYSELG_7298 ),
.I1(\i1/blk00000001/sig000000da/CYSELF_7312 ),
.O(\i1/blk00000001/sig000000da/CYAND_7310 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYMUXFAST (
.IA(\i1/blk00000001/sig000000da/CYMUXG2_7308 ),
.IB(\i1/blk00000001/sig000000da/FASTCARRY_7309 ),
.SEL(\i1/blk00000001/sig000000da/CYAND_7310 ),
.O(\i1/blk00000001/sig000000da/CYMUXFAST_7311 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYMUXG2 (
.IA(\i1/blk00000001/sig000000da/CY0G_7306 ),
.IB(\i1/blk00000001/sig000000da/CYMUXF2_7307 ),
.SEL(\i1/blk00000001/sig000000da/CYSELG_7298 ),
.O(\i1/blk00000001/sig000000da/CYMUXG2_7308 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CY0G (
.I(\i1/blk00000001/sig00000104 ),
.O(\i1/blk00000001/sig000000da/CY0G_7306 )
);
X_BUF #(
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/sig000000da/CYSELG (
.I(\i1/blk00000001/sig00000058 ),
.O(\i1/blk00000001/sig000000da/CYSELG_7298 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/XUSED (
.I(\i1/blk00000001/sig000000dc/XORF_7365 ),
.O(\i1/blk00000001/sig000000dc )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/XORF (
.I0(\i1/blk00000001/sig000000dc/CYINIT_7364 ),
.I1(\i1/blk00000001/sig00000056 ),
.O(\i1/blk00000001/sig000000dc/XORF_7365 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYMUXF (
.IA(\i1/blk00000001/sig000000dc/CY0F_7363 ),
.IB(\i1/blk00000001/sig000000dc/CYINIT_7364 ),
.SEL(\i1/blk00000001/sig000000dc/CYSELF_7351 ),
.O(\i1/blk00000001/sig00000055 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYMUXF2 (
.IA(\i1/blk00000001/sig000000dc/CY0F_7363 ),
.IB(\i1/blk00000001/sig000000dc/CY0F_7363 ),
.SEL(\i1/blk00000001/sig000000dc/CYSELF_7351 ),
.O(\i1/blk00000001/sig000000dc/CYMUXF2_7346 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYINIT (
.I(\i1/blk00000001/sig00000057 ),
.O(\i1/blk00000001/sig000000dc/CYINIT_7364 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CY0F (
.I(\i1/blk00000001/sig00000104 ),
.O(\i1/blk00000001/sig000000dc/CY0F_7363 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYSELF (
.I(\i1/blk00000001/sig00000056 ),
.O(\i1/blk00000001/sig000000dc/CYSELF_7351 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/YUSED (
.I(\i1/blk00000001/sig000000dc/XORG_7353 ),
.O(\i1/blk00000001/sig000000dd )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/XORG (
.I0(\i1/blk00000001/sig00000055 ),
.I1(\i1/blk00000001/sig00000054 ),
.O(\i1/blk00000001/sig000000dc/XORG_7353 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/FASTCARRY (
.I(\i1/blk00000001/sig00000057 ),
.O(\i1/blk00000001/sig000000dc/FASTCARRY_7348 )
);
X_AND2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYAND (
.I0(\i1/blk00000001/sig000000dc/CYSELG_7337 ),
.I1(\i1/blk00000001/sig000000dc/CYSELF_7351 ),
.O(\i1/blk00000001/sig000000dc/CYAND_7349 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYMUXFAST (
.IA(\i1/blk00000001/sig000000dc/CYMUXG2_7347 ),
.IB(\i1/blk00000001/sig000000dc/FASTCARRY_7348 ),
.SEL(\i1/blk00000001/sig000000dc/CYAND_7349 ),
.O(\i1/blk00000001/sig000000dc/CYMUXFAST_7350 )
);
X_MUX2 #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYMUXG2 (
.IA(\i1/blk00000001/sig000000dc/CY0G_7345 ),
.IB(\i1/blk00000001/sig000000dc/CYMUXF2_7346 ),
.SEL(\i1/blk00000001/sig000000dc/CYSELG_7337 ),
.O(\i1/blk00000001/sig000000dc/CYMUXG2_7347 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CY0G (
.I(\i1/blk00000001/sig00000104 ),
.O(\i1/blk00000001/sig000000dc/CY0G_7345 )
);
X_BUF #(
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/sig000000dc/CYSELG (
.I(\i1/blk00000001/sig00000054 ),
.O(\i1/blk00000001/sig000000dc/CYSELG_7337 )
);
X_BUF #(
.LOC ( "SLICE_X15Y16" ))
\i1/blk00000001/sig000000de/XUSED (
.I(\i1/blk00000001/sig000000de/XORF_7380 ),
.O(\i1/blk00000001/sig000000de )
);
X_XOR2 #(
.LOC ( "SLICE_X15Y16" ))
\i1/blk00000001/sig000000de/XORF (
.I0(\i1/blk00000001/sig000000de/CYINIT_7379 ),
.I1(\i1/blk00000001/sig00000052 ),
.O(\i1/blk00000001/sig000000de/XORF_7380 )
);
X_BUF #(
.LOC ( "SLICE_X15Y16" ))
\i1/blk00000001/sig000000de/CYINIT (
.I(\i1/blk00000001/sig000000dc/CYMUXFAST_7350 ),
.O(\i1/blk00000001/sig000000de/CYINIT_7379 )
);
X_ONE #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/LOGIC_ONE (
.O(\i1/blk00000001/sig00000185/LOGIC_ONE_7397 )
);
X_BUF #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/XUSED (
.I(\i1/blk00000001/sig00000185/XORF_7413 ),
.O(\i1/blk00000001/sig00000185 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/XORF (
.I0(\i1/blk00000001/sig00000185/CYINIT_7412 ),
.I1(\i1/blk00000001/sig00000185/F ),
.O(\i1/blk00000001/sig00000185/XORF_7413 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/CYMUXF (
.IA(\NLW_i1/blk00000001/sig00000185/CYMUXF_IA_UNCONNECTED ),
.IB(\i1/blk00000001/sig00000185/CYINIT_7412 ),
.SEL(\i1/blk00000001/sig00000185/LOGIC_ONE_7397 ),
.O(\i1/blk00000001/sig000001d7 )
);
X_BUF #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/CYINIT (
.I(\i1/blk00000001/sig00000185/BXINV_7401 ),
.O(\i1/blk00000001/sig00000185/CYINIT_7412 )
);
X_BUF #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/BXINV (
.I(1'b1),
.O(\i1/blk00000001/sig00000185/BXINV_7401 )
);
X_BUF #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/YUSED (
.I(\i1/blk00000001/sig00000185/XORG_7399 ),
.O(\i1/blk00000001/sig00000184 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/XORG (
.I0(\i1/blk00000001/sig000001d7 ),
.I1(\i1/blk00000001/sig00000185/G ),
.O(\i1/blk00000001/sig00000185/XORG_7399 )
);
X_BUF #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/COUTUSED (
.I(\i1/blk00000001/sig00000185/CYMUXG_7398 ),
.O(\i1/blk00000001/sig000001d1 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/CYMUXG (
.IA(\NLW_i1/blk00000001/sig00000185/CYMUXG_IA_UNCONNECTED ),
.IB(\i1/blk00000001/sig000001d7 ),
.SEL(\i1/blk00000001/sig00000185/LOGIC_ONE_7397 ),
.O(\i1/blk00000001/sig00000185/CYMUXG_7398 )
);
X_ONE #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/LOGIC_ONE (
.O(\i1/blk00000001/sig00000179/LOGIC_ONE_7444 )
);
X_BUF #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/XUSED (
.I(\i1/blk00000001/sig00000179/XORF_7445 ),
.O(\i1/blk00000001/sig00000179 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/XORF (
.I0(\i1/blk00000001/sig00000179/CYINIT_7443 ),
.I1(\i1/blk00000001/sig00000179/F ),
.O(\i1/blk00000001/sig00000179/XORF_7445 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/CYMUXF (
.IA(\NLW_i1/blk00000001/sig00000179/CYMUXF_IA_UNCONNECTED ),
.IB(\i1/blk00000001/sig00000179/CYINIT_7443 ),
.SEL(\i1/blk00000001/sig00000179/LOGIC_ONE_7444 ),
.O(\i1/blk00000001/sig000001cb )
);
X_BUF #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/CYINIT (
.I(\i1/blk00000001/sig000001d1 ),
.O(\i1/blk00000001/sig00000179/CYINIT_7443 )
);
X_BUF #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/YUSED (
.I(\i1/blk00000001/sig00000179/XORG_7431 ),
.O(\i1/blk00000001/sig0000016e )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/XORG (
.I0(\i1/blk00000001/sig000001cb ),
.I1(\i1/blk00000001/sig00000179/G ),
.O(\i1/blk00000001/sig00000179/XORG_7431 )
);
X_BUF #(
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/COUTUSED (
.I(\i1/blk00000001/sig000001d1 ),
.O(\i1/blk00000001/sig000001c5 )
);
X_ONE #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/LOGIC_ONE (
.O(\i1/blk00000001/sig00000163/LOGIC_ONE_7476 )
);
X_BUF #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/XUSED (
.I(\i1/blk00000001/sig00000163/XORF_7477 ),
.O(\i1/blk00000001/sig00000163 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/XORF (
.I0(\i1/blk00000001/sig00000163/CYINIT_7475 ),
.I1(\i1/blk00000001/sig00000163/F ),
.O(\i1/blk00000001/sig00000163/XORF_7477 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/CYMUXF (
.IA(\NLW_i1/blk00000001/sig00000163/CYMUXF_IA_UNCONNECTED ),
.IB(\i1/blk00000001/sig00000163/CYINIT_7475 ),
.SEL(\i1/blk00000001/sig00000163/LOGIC_ONE_7476 ),
.O(\i1/blk00000001/sig000001bf )
);
X_BUF #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/CYINIT (
.I(\i1/blk00000001/sig000001c5 ),
.O(\i1/blk00000001/sig00000163/CYINIT_7475 )
);
X_BUF #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/YUSED (
.I(\i1/blk00000001/sig00000163/XORG_7463 ),
.O(\i1/blk00000001/sig00000158 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/XORG (
.I0(\i1/blk00000001/sig000001bf ),
.I1(\i1/blk00000001/sig00000163/G ),
.O(\i1/blk00000001/sig00000163/XORG_7463 )
);
X_BUF #(
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/COUTUSED (
.I(\i1/blk00000001/sig000001c5 ),
.O(\i1/blk00000001/sig000001b9 )
);
X_ONE #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/LOGIC_ONE (
.O(\i1/blk00000001/sig0000014d/LOGIC_ONE_7508 )
);
X_BUF #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/XUSED (
.I(\i1/blk00000001/sig0000014d/XORF_7509 ),
.O(\i1/blk00000001/sig0000014d )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/XORF (
.I0(\i1/blk00000001/sig0000014d/CYINIT_7507 ),
.I1(\i1/blk00000001/sig0000014d/F ),
.O(\i1/blk00000001/sig0000014d/XORF_7509 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/CYMUXF (
.IA(\NLW_i1/blk00000001/sig0000014d/CYMUXF_IA_UNCONNECTED ),
.IB(\i1/blk00000001/sig0000014d/CYINIT_7507 ),
.SEL(\i1/blk00000001/sig0000014d/LOGIC_ONE_7508 ),
.O(\i1/blk00000001/sig000001b3 )
);
X_BUF #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/CYINIT (
.I(\i1/blk00000001/sig000001b9 ),
.O(\i1/blk00000001/sig0000014d/CYINIT_7507 )
);
X_BUF #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/YUSED (
.I(\i1/blk00000001/sig0000014d/XORG_7495 ),
.O(\i1/blk00000001/sig00000142 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/XORG (
.I0(\i1/blk00000001/sig000001b3 ),
.I1(\i1/blk00000001/sig0000014d/G ),
.O(\i1/blk00000001/sig0000014d/XORG_7495 )
);
X_BUF #(
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/COUTUSED (
.I(\i1/blk00000001/sig000001b9 ),
.O(\i1/blk00000001/sig000001ad )
);
X_ONE #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/LOGIC_ONE (
.O(\i1/blk00000001/sig00000137/LOGIC_ONE_7540 )
);
X_BUF #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/XUSED (
.I(\i1/blk00000001/sig00000137/XORF_7541 ),
.O(\i1/blk00000001/sig00000137 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/XORF (
.I0(\i1/blk00000001/sig00000137/CYINIT_7539 ),
.I1(\i1/blk00000001/sig00000137/F ),
.O(\i1/blk00000001/sig00000137/XORF_7541 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/CYMUXF (
.IA(\NLW_i1/blk00000001/sig00000137/CYMUXF_IA_UNCONNECTED ),
.IB(\i1/blk00000001/sig00000137/CYINIT_7539 ),
.SEL(\i1/blk00000001/sig00000137/LOGIC_ONE_7540 ),
.O(\i1/blk00000001/sig000001a7 )
);
X_BUF #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/CYINIT (
.I(\i1/blk00000001/sig000001ad ),
.O(\i1/blk00000001/sig00000137/CYINIT_7539 )
);
X_BUF #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/YUSED (
.I(\i1/blk00000001/sig00000137/XORG_7527 ),
.O(\i1/blk00000001/sig0000012c )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/XORG (
.I0(\i1/blk00000001/sig000001a7 ),
.I1(\i1/blk00000001/sig00000137/G ),
.O(\i1/blk00000001/sig00000137/XORG_7527 )
);
X_BUF #(
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/COUTUSED (
.I(\i1/blk00000001/sig000001ad ),
.O(\i1/blk00000001/sig000001a1 )
);
X_LUT4 #(
.INIT ( 16'h5555 ),
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/blk000001d2 (
.ADR0(x1_8_IBUF_3311),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000e1 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/XUSED (
.I(\i1/blk00000001/sig00000121/XORF_7582 ),
.O(\i1/blk00000001/sig00000121 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/XORF (
.I0(\i1/blk00000001/sig00000121/CYINIT_7581 ),
.I1(\i1/blk00000001/sig000000e1 ),
.O(\i1/blk00000001/sig00000121/XORF_7582 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYMUXF (
.IA(\i1/blk00000001/sig00000121/CY0F_7580 ),
.IB(\i1/blk00000001/sig00000121/CYINIT_7581 ),
.SEL(\i1/blk00000001/sig00000121/CYSELF_7567 ),
.O(\i1/blk00000001/sig0000019b )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYMUXF2 (
.IA(\i1/blk00000001/sig00000121/CY0F_7580 ),
.IB(\i1/blk00000001/sig00000121/CY0F_7580 ),
.SEL(\i1/blk00000001/sig00000121/CYSELF_7567 ),
.O(\i1/blk00000001/sig00000121/CYMUXF2_7562 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYINIT (
.I(\i1/blk00000001/sig000001a1 ),
.O(\i1/blk00000001/sig00000121/CYINIT_7581 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CY0F (
.I(\i1/blk00000001/sig000001ee ),
.O(\i1/blk00000001/sig00000121/CY0F_7580 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000121/FAND/IN1 ),
.O(\i1/blk00000001/sig000001ee )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYSELF (
.I(\i1/blk00000001/sig000000e1 ),
.O(\i1/blk00000001/sig00000121/CYSELF_7567 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/YUSED (
.I(\i1/blk00000001/sig00000121/XORG_7569 ),
.O(\i1/blk00000001/sig00000116 )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/XORG (
.I0(\i1/blk00000001/sig0000019b ),
.I1(\i1/blk00000001/sig000000e0 ),
.O(\i1/blk00000001/sig00000121/XORG_7569 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/FASTCARRY (
.I(\i1/blk00000001/sig000001a1 ),
.O(\i1/blk00000001/sig00000121/FASTCARRY_7564 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYAND (
.I0(\i1/blk00000001/sig00000121/CYSELG_7553 ),
.I1(\i1/blk00000001/sig00000121/CYSELF_7567 ),
.O(\i1/blk00000001/sig00000121/CYAND_7565 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYMUXFAST (
.IA(\i1/blk00000001/sig00000121/CYMUXG2_7563 ),
.IB(\i1/blk00000001/sig00000121/FASTCARRY_7564 ),
.SEL(\i1/blk00000001/sig00000121/CYAND_7565 ),
.O(\i1/blk00000001/sig00000121/CYMUXFAST_7566 )
);
X_MUX2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYMUXG2 (
.IA(\i1/blk00000001/sig00000121/CY0G_7561 ),
.IB(\i1/blk00000001/sig00000121/CYMUXF2_7562 ),
.SEL(\i1/blk00000001/sig00000121/CYSELG_7553 ),
.O(\i1/blk00000001/sig00000121/CYMUXG2_7563 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CY0G (
.I(\i1/blk00000001/sig000001e8 ),
.O(\i1/blk00000001/sig00000121/CY0G_7561 )
);
X_AND2 #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000121/GAND/IN1 ),
.O(\i1/blk00000001/sig000001e8 )
);
X_BUF #(
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/sig00000121/CYSELG (
.I(\i1/blk00000001/sig000000e0 ),
.O(\i1/blk00000001/sig00000121/CYSELG_7553 )
);
X_LUT4 #(
.INIT ( 16'hA5A5 ),
.LOC ( "SLICE_X23Y16" ))
\i1/blk00000001/blk000001d1 (
.ADR0(x1_8_IBUF_3311),
.ADR1(VCC),
.ADR2(x1_9_IBUF_3312),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000e0 )
);
X_BUF #(
.LOC ( "SLICE_X23Y17" ))
\i1/blk00000001/sig0000010b/XUSED (
.I(\i1/blk00000001/sig0000010b/XORF_7597 ),
.O(\i1/blk00000001/sig0000010b )
);
X_XOR2 #(
.LOC ( "SLICE_X23Y17" ))
\i1/blk00000001/sig0000010b/XORF (
.I0(\i1/blk00000001/sig0000010b/CYINIT_7596 ),
.I1(\i1/blk00000001/sig0000023a ),
.O(\i1/blk00000001/sig0000010b/XORF_7597 )
);
X_BUF #(
.LOC ( "SLICE_X23Y17" ))
\i1/blk00000001/sig0000010b/CYINIT (
.I(\i1/blk00000001/sig00000121/CYMUXFAST_7566 ),
.O(\i1/blk00000001/sig0000010b/CYINIT_7596 )
);
X_LUT4 #(
.INIT ( 16'hA5A5 ),
.LOC ( "SLICE_X23Y17" ))
\i1/blk00000001/blk00000223 (
.ADR0(x1_8_IBUF_3311),
.ADR1(VCC),
.ADR2(x1_9_IBUF_3312),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000023a )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/XUSED (
.I(\i1/blk00000001/sig000001da/XORF_7635 ),
.O(\i1/blk00000001/sig000001da )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/XORF (
.I0(\i1/blk00000001/sig000001da/CYINIT_7634 ),
.I1(\i1/blk00000001/sig000001da/F ),
.O(\i1/blk00000001/sig000001da/XORF_7635 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CYMUXF (
.IA(\i1/blk00000001/sig000001da/CY0F_7633 ),
.IB(\i1/blk00000001/sig000001da/CYINIT_7634 ),
.SEL(\i1/blk00000001/sig000001da/CYSELF_7624 ),
.O(\i1/blk00000001/sig000001db )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CYINIT (
.I(\i1/blk00000001/sig000001da/BXINV_7622 ),
.O(\i1/blk00000001/sig000001da/CYINIT_7634 )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CY0F (
.I(\i1/blk00000001/sig0000022c ),
.O(\i1/blk00000001/sig000001da/CY0F_7633 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/FAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig000001da/FAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig0000022c )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CYSELF (
.I(\i1/blk00000001/sig000001da/F ),
.O(\i1/blk00000001/sig000001da/CYSELF_7624 )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000001da/BXINV_7622 )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/YUSED (
.I(\i1/blk00000001/sig000001da/XORG_7620 ),
.O(\i1/blk00000001/sig00000188 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/XORG (
.I0(\i1/blk00000001/sig000001db ),
.I1(\i1/blk00000001/sig000001da/G ),
.O(\i1/blk00000001/sig000001da/XORG_7620 )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/COUTUSED (
.I(\i1/blk00000001/sig000001da/CYMUXG_7619 ),
.O(\i1/blk00000001/sig000001d9 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CYMUXG (
.IA(\i1/blk00000001/sig000001da/CY0G_7617 ),
.IB(\i1/blk00000001/sig000001db ),
.SEL(\i1/blk00000001/sig000001da/CYSELG_7608 ),
.O(\i1/blk00000001/sig000001da/CYMUXG_7619 )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CY0G (
.I(\i1/blk00000001/sig0000022b ),
.O(\i1/blk00000001/sig000001da/CY0G_7617 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/GAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig000001da/GAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig0000022b )
);
X_BUF #(
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/CYSELG (
.I(\i1/blk00000001/sig000001da/G ),
.O(\i1/blk00000001/sig000001da/CYSELG_7608 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/XUSED (
.I(\i1/blk00000001/sig00000186/XORF_7676 ),
.O(\i1/blk00000001/sig00000186 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/XORF (
.I0(\i1/blk00000001/sig00000186/CYINIT_7675 ),
.I1(\i1/blk00000001/sig00000186/F ),
.O(\i1/blk00000001/sig00000186/XORF_7676 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYMUXF (
.IA(\i1/blk00000001/sig00000186/CY0F_7674 ),
.IB(\i1/blk00000001/sig00000186/CYINIT_7675 ),
.SEL(\i1/blk00000001/sig00000186/CYSELF_7661 ),
.O(\i1/blk00000001/sig000001d2 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYMUXF2 (
.IA(\i1/blk00000001/sig00000186/CY0F_7674 ),
.IB(\i1/blk00000001/sig00000186/CY0F_7674 ),
.SEL(\i1/blk00000001/sig00000186/CYSELF_7661 ),
.O(\i1/blk00000001/sig00000186/CYMUXF2_7656 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYINIT (
.I(\i1/blk00000001/sig000001d9 ),
.O(\i1/blk00000001/sig00000186/CYINIT_7675 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CY0F (
.I(\i1/blk00000001/sig00000225 ),
.O(\i1/blk00000001/sig00000186/CY0F_7674 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/FAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig00000186/FAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig00000225 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYSELF (
.I(\i1/blk00000001/sig00000186/F ),
.O(\i1/blk00000001/sig00000186/CYSELF_7661 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/YUSED (
.I(\i1/blk00000001/sig00000186/XORG_7663 ),
.O(\i1/blk00000001/sig0000017a )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/XORG (
.I0(\i1/blk00000001/sig000001d2 ),
.I1(\i1/blk00000001/sig00000186/G ),
.O(\i1/blk00000001/sig00000186/XORG_7663 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/COUTUSED (
.I(\i1/blk00000001/sig00000186/CYMUXFAST_7660 ),
.O(\i1/blk00000001/sig000001cc )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/FASTCARRY (
.I(\i1/blk00000001/sig000001d9 ),
.O(\i1/blk00000001/sig00000186/FASTCARRY_7658 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYAND (
.I0(\i1/blk00000001/sig00000186/CYSELG_7646 ),
.I1(\i1/blk00000001/sig00000186/CYSELF_7661 ),
.O(\i1/blk00000001/sig00000186/CYAND_7659 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYMUXFAST (
.IA(\i1/blk00000001/sig00000186/CYMUXG2_7657 ),
.IB(\i1/blk00000001/sig00000186/FASTCARRY_7658 ),
.SEL(\i1/blk00000001/sig00000186/CYAND_7659 ),
.O(\i1/blk00000001/sig00000186/CYMUXFAST_7660 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYMUXG2 (
.IA(\i1/blk00000001/sig00000186/CY0G_7655 ),
.IB(\i1/blk00000001/sig00000186/CYMUXF2_7656 ),
.SEL(\i1/blk00000001/sig00000186/CYSELG_7646 ),
.O(\i1/blk00000001/sig00000186/CYMUXG2_7657 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CY0G (
.I(\i1/blk00000001/sig0000021f ),
.O(\i1/blk00000001/sig00000186/CY0G_7655 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/GAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig00000186/GAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig0000021f )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/CYSELG (
.I(\i1/blk00000001/sig00000186/G ),
.O(\i1/blk00000001/sig00000186/CYSELG_7646 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/XUSED (
.I(\i1/blk00000001/sig0000016f/XORF_7717 ),
.O(\i1/blk00000001/sig0000016f )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/XORF (
.I0(\i1/blk00000001/sig0000016f/CYINIT_7716 ),
.I1(\i1/blk00000001/sig0000016f/F ),
.O(\i1/blk00000001/sig0000016f/XORF_7717 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYMUXF (
.IA(\i1/blk00000001/sig0000016f/CY0F_7715 ),
.IB(\i1/blk00000001/sig0000016f/CYINIT_7716 ),
.SEL(\i1/blk00000001/sig0000016f/CYSELF_7702 ),
.O(\i1/blk00000001/sig000001c6 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYMUXF2 (
.IA(\i1/blk00000001/sig0000016f/CY0F_7715 ),
.IB(\i1/blk00000001/sig0000016f/CY0F_7715 ),
.SEL(\i1/blk00000001/sig0000016f/CYSELF_7702 ),
.O(\i1/blk00000001/sig0000016f/CYMUXF2_7697 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYINIT (
.I(\i1/blk00000001/sig000001cc ),
.O(\i1/blk00000001/sig0000016f/CYINIT_7716 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CY0F (
.I(\i1/blk00000001/sig00000219 ),
.O(\i1/blk00000001/sig0000016f/CY0F_7715 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000016f/FAND/IN1 ),
.O(\i1/blk00000001/sig00000219 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYSELF (
.I(\i1/blk00000001/sig0000016f/F ),
.O(\i1/blk00000001/sig0000016f/CYSELF_7702 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/YUSED (
.I(\i1/blk00000001/sig0000016f/XORG_7704 ),
.O(\i1/blk00000001/sig00000164 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/XORG (
.I0(\i1/blk00000001/sig000001c6 ),
.I1(\i1/blk00000001/sig0000016f/G ),
.O(\i1/blk00000001/sig0000016f/XORG_7704 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/COUTUSED (
.I(\i1/blk00000001/sig0000016f/CYMUXFAST_7701 ),
.O(\i1/blk00000001/sig000001c0 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/FASTCARRY (
.I(\i1/blk00000001/sig000001cc ),
.O(\i1/blk00000001/sig0000016f/FASTCARRY_7699 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYAND (
.I0(\i1/blk00000001/sig0000016f/CYSELG_7687 ),
.I1(\i1/blk00000001/sig0000016f/CYSELF_7702 ),
.O(\i1/blk00000001/sig0000016f/CYAND_7700 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYMUXFAST (
.IA(\i1/blk00000001/sig0000016f/CYMUXG2_7698 ),
.IB(\i1/blk00000001/sig0000016f/FASTCARRY_7699 ),
.SEL(\i1/blk00000001/sig0000016f/CYAND_7700 ),
.O(\i1/blk00000001/sig0000016f/CYMUXFAST_7701 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYMUXG2 (
.IA(\i1/blk00000001/sig0000016f/CY0G_7696 ),
.IB(\i1/blk00000001/sig0000016f/CYMUXF2_7697 ),
.SEL(\i1/blk00000001/sig0000016f/CYSELG_7687 ),
.O(\i1/blk00000001/sig0000016f/CYMUXG2_7698 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CY0G (
.I(\i1/blk00000001/sig00000213 ),
.O(\i1/blk00000001/sig0000016f/CY0G_7696 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000016f/GAND/IN1 ),
.O(\i1/blk00000001/sig00000213 )
);
X_BUF #(
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/CYSELG (
.I(\i1/blk00000001/sig0000016f/G ),
.O(\i1/blk00000001/sig0000016f/CYSELG_7687 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/XUSED (
.I(\i1/blk00000001/sig00000159/XORF_7758 ),
.O(\i1/blk00000001/sig00000159 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/XORF (
.I0(\i1/blk00000001/sig00000159/CYINIT_7757 ),
.I1(\i1/blk00000001/sig00000159/F ),
.O(\i1/blk00000001/sig00000159/XORF_7758 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYMUXF (
.IA(\i1/blk00000001/sig00000159/CY0F_7756 ),
.IB(\i1/blk00000001/sig00000159/CYINIT_7757 ),
.SEL(\i1/blk00000001/sig00000159/CYSELF_7743 ),
.O(\i1/blk00000001/sig000001ba )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYMUXF2 (
.IA(\i1/blk00000001/sig00000159/CY0F_7756 ),
.IB(\i1/blk00000001/sig00000159/CY0F_7756 ),
.SEL(\i1/blk00000001/sig00000159/CYSELF_7743 ),
.O(\i1/blk00000001/sig00000159/CYMUXF2_7738 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYINIT (
.I(\i1/blk00000001/sig000001c0 ),
.O(\i1/blk00000001/sig00000159/CYINIT_7757 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CY0F (
.I(\i1/blk00000001/sig0000020d ),
.O(\i1/blk00000001/sig00000159/CY0F_7756 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000159/FAND/IN1 ),
.O(\i1/blk00000001/sig0000020d )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYSELF (
.I(\i1/blk00000001/sig00000159/F ),
.O(\i1/blk00000001/sig00000159/CYSELF_7743 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/YUSED (
.I(\i1/blk00000001/sig00000159/XORG_7745 ),
.O(\i1/blk00000001/sig0000014e )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/XORG (
.I0(\i1/blk00000001/sig000001ba ),
.I1(\i1/blk00000001/sig00000159/G ),
.O(\i1/blk00000001/sig00000159/XORG_7745 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/COUTUSED (
.I(\i1/blk00000001/sig00000159/CYMUXFAST_7742 ),
.O(\i1/blk00000001/sig000001b4 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/FASTCARRY (
.I(\i1/blk00000001/sig000001c0 ),
.O(\i1/blk00000001/sig00000159/FASTCARRY_7740 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYAND (
.I0(\i1/blk00000001/sig00000159/CYSELG_7728 ),
.I1(\i1/blk00000001/sig00000159/CYSELF_7743 ),
.O(\i1/blk00000001/sig00000159/CYAND_7741 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYMUXFAST (
.IA(\i1/blk00000001/sig00000159/CYMUXG2_7739 ),
.IB(\i1/blk00000001/sig00000159/FASTCARRY_7740 ),
.SEL(\i1/blk00000001/sig00000159/CYAND_7741 ),
.O(\i1/blk00000001/sig00000159/CYMUXFAST_7742 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYMUXG2 (
.IA(\i1/blk00000001/sig00000159/CY0G_7737 ),
.IB(\i1/blk00000001/sig00000159/CYMUXF2_7738 ),
.SEL(\i1/blk00000001/sig00000159/CYSELG_7728 ),
.O(\i1/blk00000001/sig00000159/CYMUXG2_7739 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CY0G (
.I(\i1/blk00000001/sig00000207 ),
.O(\i1/blk00000001/sig00000159/CY0G_7737 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000159/GAND/IN1 ),
.O(\i1/blk00000001/sig00000207 )
);
X_BUF #(
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/CYSELG (
.I(\i1/blk00000001/sig00000159/G ),
.O(\i1/blk00000001/sig00000159/CYSELG_7728 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/XUSED (
.I(\i1/blk00000001/sig00000143/XORF_7799 ),
.O(\i1/blk00000001/sig00000143 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/XORF (
.I0(\i1/blk00000001/sig00000143/CYINIT_7798 ),
.I1(\i1/blk00000001/sig00000143/F ),
.O(\i1/blk00000001/sig00000143/XORF_7799 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYMUXF (
.IA(\i1/blk00000001/sig00000143/CY0F_7797 ),
.IB(\i1/blk00000001/sig00000143/CYINIT_7798 ),
.SEL(\i1/blk00000001/sig00000143/CYSELF_7784 ),
.O(\i1/blk00000001/sig000001ae )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYMUXF2 (
.IA(\i1/blk00000001/sig00000143/CY0F_7797 ),
.IB(\i1/blk00000001/sig00000143/CY0F_7797 ),
.SEL(\i1/blk00000001/sig00000143/CYSELF_7784 ),
.O(\i1/blk00000001/sig00000143/CYMUXF2_7779 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYINIT (
.I(\i1/blk00000001/sig000001b4 ),
.O(\i1/blk00000001/sig00000143/CYINIT_7798 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CY0F (
.I(\i1/blk00000001/sig00000201 ),
.O(\i1/blk00000001/sig00000143/CY0F_7797 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/FAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig00000143/FAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig00000201 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYSELF (
.I(\i1/blk00000001/sig00000143/F ),
.O(\i1/blk00000001/sig00000143/CYSELF_7784 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/YUSED (
.I(\i1/blk00000001/sig00000143/XORG_7786 ),
.O(\i1/blk00000001/sig00000138 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/XORG (
.I0(\i1/blk00000001/sig000001ae ),
.I1(\i1/blk00000001/sig00000143/G ),
.O(\i1/blk00000001/sig00000143/XORG_7786 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/COUTUSED (
.I(\i1/blk00000001/sig00000143/CYMUXFAST_7783 ),
.O(\i1/blk00000001/sig000001a8 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/FASTCARRY (
.I(\i1/blk00000001/sig000001b4 ),
.O(\i1/blk00000001/sig00000143/FASTCARRY_7781 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYAND (
.I0(\i1/blk00000001/sig00000143/CYSELG_7769 ),
.I1(\i1/blk00000001/sig00000143/CYSELF_7784 ),
.O(\i1/blk00000001/sig00000143/CYAND_7782 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYMUXFAST (
.IA(\i1/blk00000001/sig00000143/CYMUXG2_7780 ),
.IB(\i1/blk00000001/sig00000143/FASTCARRY_7781 ),
.SEL(\i1/blk00000001/sig00000143/CYAND_7782 ),
.O(\i1/blk00000001/sig00000143/CYMUXFAST_7783 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYMUXG2 (
.IA(\i1/blk00000001/sig00000143/CY0G_7778 ),
.IB(\i1/blk00000001/sig00000143/CYMUXF2_7779 ),
.SEL(\i1/blk00000001/sig00000143/CYSELG_7769 ),
.O(\i1/blk00000001/sig00000143/CYMUXG2_7780 )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CY0G (
.I(\i1/blk00000001/sig000001fb ),
.O(\i1/blk00000001/sig00000143/CY0G_7778 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/GAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig00000143/GAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig000001fb )
);
X_BUF #(
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/CYSELG (
.I(\i1/blk00000001/sig00000143/G ),
.O(\i1/blk00000001/sig00000143/CYSELG_7769 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/XUSED (
.I(\i1/blk00000001/sig0000012d/XORF_7840 ),
.O(\i1/blk00000001/sig0000012d )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/XORF (
.I0(\i1/blk00000001/sig0000012d/CYINIT_7839 ),
.I1(\i1/blk00000001/sig0000012d/F ),
.O(\i1/blk00000001/sig0000012d/XORF_7840 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYMUXF (
.IA(\i1/blk00000001/sig0000012d/CY0F_7838 ),
.IB(\i1/blk00000001/sig0000012d/CYINIT_7839 ),
.SEL(\i1/blk00000001/sig0000012d/CYSELF_7826 ),
.O(\i1/blk00000001/sig000001a2 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYMUXF2 (
.IA(\i1/blk00000001/sig0000012d/CY0F_7838 ),
.IB(\i1/blk00000001/sig0000012d/CY0F_7838 ),
.SEL(\i1/blk00000001/sig0000012d/CYSELF_7826 ),
.O(\i1/blk00000001/sig0000012d/CYMUXF2_7821 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYINIT (
.I(\i1/blk00000001/sig000001a8 ),
.O(\i1/blk00000001/sig0000012d/CYINIT_7839 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CY0F (
.I(\i1/blk00000001/sig000001f5 ),
.O(\i1/blk00000001/sig0000012d/CY0F_7838 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/FAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig0000012d/FAND/IN0 ),
.I1(1'b0),
.O(\i1/blk00000001/sig000001f5 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYSELF (
.I(\i1/blk00000001/sig0000012d/F ),
.O(\i1/blk00000001/sig0000012d/CYSELF_7826 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/YUSED (
.I(\i1/blk00000001/sig0000012d/XORG_7828 ),
.O(\i1/blk00000001/sig00000122 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/XORG (
.I0(\i1/blk00000001/sig000001a2 ),
.I1(\i1/blk00000001/sig00000118 ),
.O(\i1/blk00000001/sig0000012d/XORG_7828 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/FASTCARRY (
.I(\i1/blk00000001/sig000001a8 ),
.O(\i1/blk00000001/sig0000012d/FASTCARRY_7823 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYAND (
.I0(\i1/blk00000001/sig0000012d/CYSELG_7812 ),
.I1(\i1/blk00000001/sig0000012d/CYSELF_7826 ),
.O(\i1/blk00000001/sig0000012d/CYAND_7824 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYMUXFAST (
.IA(\i1/blk00000001/sig0000012d/CYMUXG2_7822 ),
.IB(\i1/blk00000001/sig0000012d/FASTCARRY_7823 ),
.SEL(\i1/blk00000001/sig0000012d/CYAND_7824 ),
.O(\i1/blk00000001/sig0000012d/CYMUXFAST_7825 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYMUXG2 (
.IA(\i1/blk00000001/sig0000012d/CY0G_7820 ),
.IB(\i1/blk00000001/sig0000012d/CYMUXF2_7821 ),
.SEL(\i1/blk00000001/sig0000012d/CYSELG_7812 ),
.O(\i1/blk00000001/sig0000012d/CYMUXG2_7822 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CY0G (
.I(\i1/blk00000001/sig000001ef ),
.O(\i1/blk00000001/sig0000012d/CY0G_7820 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000012d/GAND/IN1 ),
.O(\i1/blk00000001/sig000001ef )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/CYSELG (
.I(\i1/blk00000001/sig00000118 ),
.O(\i1/blk00000001/sig0000012d/CYSELG_7812 )
);
X_BUF #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/XUSED (
.I(\i1/blk00000001/sig00000117/XORF_7872 ),
.O(\i1/blk00000001/sig00000117 )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/XORF (
.I0(\i1/blk00000001/sig00000117/CYINIT_7871 ),
.I1(\i1/blk00000001/sig0000010d ),
.O(\i1/blk00000001/sig00000117/XORF_7872 )
);
X_MUX2 #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/CYMUXF (
.IA(\i1/blk00000001/sig00000117/CY0F_7870 ),
.IB(\i1/blk00000001/sig00000117/CYINIT_7871 ),
.SEL(\i1/blk00000001/sig00000117/CYSELF_7862 ),
.O(\i1/blk00000001/sig00000196 )
);
X_BUF #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/CYINIT (
.I(\i1/blk00000001/sig0000012d/CYMUXFAST_7825 ),
.O(\i1/blk00000001/sig00000117/CYINIT_7871 )
);
X_BUF #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/CY0F (
.I(\i1/blk00000001/sig000001e9 ),
.O(\i1/blk00000001/sig00000117/CY0F_7870 )
);
X_AND2 #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000117/FAND/IN1 ),
.O(\i1/blk00000001/sig000001e9 )
);
X_BUF #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/CYSELF (
.I(\i1/blk00000001/sig0000010d ),
.O(\i1/blk00000001/sig00000117/CYSELF_7862 )
);
X_BUF #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/YUSED (
.I(\i1/blk00000001/sig00000117/XORG_7859 ),
.O(\i1/blk00000001/sig0000010c )
);
X_XOR2 #(
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/sig00000117/XORG (
.I0(\i1/blk00000001/sig00000196 ),
.I1(\i1/blk00000001/sig00000106 ),
.O(\i1/blk00000001/sig00000117/XORG_7859 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/XUSED (
.I(\i1/blk00000001/sig000001e3/XORF_7910 ),
.O(\i1/blk00000001/sig000001e3 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/XORF (
.I0(\i1/blk00000001/sig000001e3/CYINIT_7909 ),
.I1(\i1/blk00000001/sig000001e3/F ),
.O(\i1/blk00000001/sig000001e3/XORF_7910 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CYMUXF (
.IA(\i1/blk00000001/sig000001e3/CY0F_7908 ),
.IB(\i1/blk00000001/sig000001e3/CYINIT_7909 ),
.SEL(\i1/blk00000001/sig000001e3/CYSELF_7899 ),
.O(\i1/blk00000001/sig000001e4 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CYINIT (
.I(\i1/blk00000001/sig000001e3/BXINV_7897 ),
.O(\i1/blk00000001/sig000001e3/CYINIT_7909 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CY0F (
.I(\i1/blk00000001/sig00000235 ),
.O(\i1/blk00000001/sig000001e3/CY0F_7908 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/FAND (
.I0(1'b0),
.I1(x1_0_IBUF_3337),
.O(\i1/blk00000001/sig00000235 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CYSELF (
.I(\i1/blk00000001/sig000001e3/F ),
.O(\i1/blk00000001/sig000001e3/CYSELF_7899 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000001e3/BXINV_7897 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/YUSED (
.I(\i1/blk00000001/sig000001e3/XORG_7895 ),
.O(\i1/blk00000001/sig00000191 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/XORG (
.I0(\i1/blk00000001/sig000001e4 ),
.I1(\i1/blk00000001/sig000001e3/G ),
.O(\i1/blk00000001/sig000001e3/XORG_7895 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/COUTUSED (
.I(\i1/blk00000001/sig000001e3/CYMUXG_7894 ),
.O(\i1/blk00000001/sig000001e2 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CYMUXG (
.IA(\i1/blk00000001/sig000001e3/CY0G_7892 ),
.IB(\i1/blk00000001/sig000001e4 ),
.SEL(\i1/blk00000001/sig000001e3/CYSELG_7883 ),
.O(\i1/blk00000001/sig000001e3/CYMUXG_7894 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CY0G (
.I(\i1/blk00000001/sig00000234 ),
.O(\i1/blk00000001/sig000001e3/CY0G_7892 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig000001e3/GAND/IN1 ),
.O(\i1/blk00000001/sig00000234 )
);
X_BUF #(
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/CYSELG (
.I(\i1/blk00000001/sig000001e3/G ),
.O(\i1/blk00000001/sig000001e3/CYSELG_7883 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/XUSED (
.I(\i1/blk00000001/sig0000018f/XORF_7951 ),
.O(\i1/blk00000001/sig0000018f )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/XORF (
.I0(\i1/blk00000001/sig0000018f/CYINIT_7950 ),
.I1(\i1/blk00000001/sig0000018f/F ),
.O(\i1/blk00000001/sig0000018f/XORF_7951 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYMUXF (
.IA(\i1/blk00000001/sig0000018f/CY0F_7949 ),
.IB(\i1/blk00000001/sig0000018f/CYINIT_7950 ),
.SEL(\i1/blk00000001/sig0000018f/CYSELF_7936 ),
.O(\i1/blk00000001/sig000001d5 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYMUXF2 (
.IA(\i1/blk00000001/sig0000018f/CY0F_7949 ),
.IB(\i1/blk00000001/sig0000018f/CY0F_7949 ),
.SEL(\i1/blk00000001/sig0000018f/CYSELF_7936 ),
.O(\i1/blk00000001/sig0000018f/CYMUXF2_7931 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYINIT (
.I(\i1/blk00000001/sig000001e2 ),
.O(\i1/blk00000001/sig0000018f/CYINIT_7950 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CY0F (
.I(\i1/blk00000001/sig00000228 ),
.O(\i1/blk00000001/sig0000018f/CY0F_7949 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000018f/FAND/IN1 ),
.O(\i1/blk00000001/sig00000228 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYSELF (
.I(\i1/blk00000001/sig0000018f/F ),
.O(\i1/blk00000001/sig0000018f/CYSELF_7936 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/YUSED (
.I(\i1/blk00000001/sig0000018f/XORG_7938 ),
.O(\i1/blk00000001/sig00000180 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/XORG (
.I0(\i1/blk00000001/sig000001d5 ),
.I1(\i1/blk00000001/sig0000018f/G ),
.O(\i1/blk00000001/sig0000018f/XORG_7938 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/COUTUSED (
.I(\i1/blk00000001/sig0000018f/CYMUXFAST_7935 ),
.O(\i1/blk00000001/sig000001cf )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/FASTCARRY (
.I(\i1/blk00000001/sig000001e2 ),
.O(\i1/blk00000001/sig0000018f/FASTCARRY_7933 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYAND (
.I0(\i1/blk00000001/sig0000018f/CYSELG_7921 ),
.I1(\i1/blk00000001/sig0000018f/CYSELF_7936 ),
.O(\i1/blk00000001/sig0000018f/CYAND_7934 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYMUXFAST (
.IA(\i1/blk00000001/sig0000018f/CYMUXG2_7932 ),
.IB(\i1/blk00000001/sig0000018f/FASTCARRY_7933 ),
.SEL(\i1/blk00000001/sig0000018f/CYAND_7934 ),
.O(\i1/blk00000001/sig0000018f/CYMUXFAST_7935 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYMUXG2 (
.IA(\i1/blk00000001/sig0000018f/CY0G_7930 ),
.IB(\i1/blk00000001/sig0000018f/CYMUXF2_7931 ),
.SEL(\i1/blk00000001/sig0000018f/CYSELG_7921 ),
.O(\i1/blk00000001/sig0000018f/CYMUXG2_7932 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CY0G (
.I(\i1/blk00000001/sig00000222 ),
.O(\i1/blk00000001/sig0000018f/CY0G_7930 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000018f/GAND/IN1 ),
.O(\i1/blk00000001/sig00000222 )
);
X_BUF #(
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/CYSELG (
.I(\i1/blk00000001/sig0000018f/G ),
.O(\i1/blk00000001/sig0000018f/CYSELG_7921 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/XUSED (
.I(\i1/blk00000001/sig00000175/XORF_7992 ),
.O(\i1/blk00000001/sig00000175 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/XORF (
.I0(\i1/blk00000001/sig00000175/CYINIT_7991 ),
.I1(\i1/blk00000001/sig00000175/F ),
.O(\i1/blk00000001/sig00000175/XORF_7992 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYMUXF (
.IA(\i1/blk00000001/sig00000175/CY0F_7990 ),
.IB(\i1/blk00000001/sig00000175/CYINIT_7991 ),
.SEL(\i1/blk00000001/sig00000175/CYSELF_7977 ),
.O(\i1/blk00000001/sig000001c9 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYMUXF2 (
.IA(\i1/blk00000001/sig00000175/CY0F_7990 ),
.IB(\i1/blk00000001/sig00000175/CY0F_7990 ),
.SEL(\i1/blk00000001/sig00000175/CYSELF_7977 ),
.O(\i1/blk00000001/sig00000175/CYMUXF2_7972 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYINIT (
.I(\i1/blk00000001/sig000001cf ),
.O(\i1/blk00000001/sig00000175/CYINIT_7991 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CY0F (
.I(\i1/blk00000001/sig0000021c ),
.O(\i1/blk00000001/sig00000175/CY0F_7990 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000175/FAND/IN1 ),
.O(\i1/blk00000001/sig0000021c )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYSELF (
.I(\i1/blk00000001/sig00000175/F ),
.O(\i1/blk00000001/sig00000175/CYSELF_7977 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/YUSED (
.I(\i1/blk00000001/sig00000175/XORG_7979 ),
.O(\i1/blk00000001/sig0000016a )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/XORG (
.I0(\i1/blk00000001/sig000001c9 ),
.I1(\i1/blk00000001/sig00000175/G ),
.O(\i1/blk00000001/sig00000175/XORG_7979 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/COUTUSED (
.I(\i1/blk00000001/sig00000175/CYMUXFAST_7976 ),
.O(\i1/blk00000001/sig000001c3 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/FASTCARRY (
.I(\i1/blk00000001/sig000001cf ),
.O(\i1/blk00000001/sig00000175/FASTCARRY_7974 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYAND (
.I0(\i1/blk00000001/sig00000175/CYSELG_7962 ),
.I1(\i1/blk00000001/sig00000175/CYSELF_7977 ),
.O(\i1/blk00000001/sig00000175/CYAND_7975 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYMUXFAST (
.IA(\i1/blk00000001/sig00000175/CYMUXG2_7973 ),
.IB(\i1/blk00000001/sig00000175/FASTCARRY_7974 ),
.SEL(\i1/blk00000001/sig00000175/CYAND_7975 ),
.O(\i1/blk00000001/sig00000175/CYMUXFAST_7976 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYMUXG2 (
.IA(\i1/blk00000001/sig00000175/CY0G_7971 ),
.IB(\i1/blk00000001/sig00000175/CYMUXF2_7972 ),
.SEL(\i1/blk00000001/sig00000175/CYSELG_7962 ),
.O(\i1/blk00000001/sig00000175/CYMUXG2_7973 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CY0G (
.I(\i1/blk00000001/sig00000216 ),
.O(\i1/blk00000001/sig00000175/CY0G_7971 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000175/GAND/IN1 ),
.O(\i1/blk00000001/sig00000216 )
);
X_BUF #(
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/CYSELG (
.I(\i1/blk00000001/sig00000175/G ),
.O(\i1/blk00000001/sig00000175/CYSELG_7962 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/XUSED (
.I(\i1/blk00000001/sig0000015f/XORF_8033 ),
.O(\i1/blk00000001/sig0000015f )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/XORF (
.I0(\i1/blk00000001/sig0000015f/CYINIT_8032 ),
.I1(\i1/blk00000001/sig0000015f/F ),
.O(\i1/blk00000001/sig0000015f/XORF_8033 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYMUXF (
.IA(\i1/blk00000001/sig0000015f/CY0F_8031 ),
.IB(\i1/blk00000001/sig0000015f/CYINIT_8032 ),
.SEL(\i1/blk00000001/sig0000015f/CYSELF_8018 ),
.O(\i1/blk00000001/sig000001bd )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYMUXF2 (
.IA(\i1/blk00000001/sig0000015f/CY0F_8031 ),
.IB(\i1/blk00000001/sig0000015f/CY0F_8031 ),
.SEL(\i1/blk00000001/sig0000015f/CYSELF_8018 ),
.O(\i1/blk00000001/sig0000015f/CYMUXF2_8013 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYINIT (
.I(\i1/blk00000001/sig000001c3 ),
.O(\i1/blk00000001/sig0000015f/CYINIT_8032 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CY0F (
.I(\i1/blk00000001/sig00000210 ),
.O(\i1/blk00000001/sig0000015f/CY0F_8031 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000015f/FAND/IN1 ),
.O(\i1/blk00000001/sig00000210 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYSELF (
.I(\i1/blk00000001/sig0000015f/F ),
.O(\i1/blk00000001/sig0000015f/CYSELF_8018 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/YUSED (
.I(\i1/blk00000001/sig0000015f/XORG_8020 ),
.O(\i1/blk00000001/sig00000154 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/XORG (
.I0(\i1/blk00000001/sig000001bd ),
.I1(\i1/blk00000001/sig0000015f/G ),
.O(\i1/blk00000001/sig0000015f/XORG_8020 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/COUTUSED (
.I(\i1/blk00000001/sig0000015f/CYMUXFAST_8017 ),
.O(\i1/blk00000001/sig000001b7 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/FASTCARRY (
.I(\i1/blk00000001/sig000001c3 ),
.O(\i1/blk00000001/sig0000015f/FASTCARRY_8015 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYAND (
.I0(\i1/blk00000001/sig0000015f/CYSELG_8003 ),
.I1(\i1/blk00000001/sig0000015f/CYSELF_8018 ),
.O(\i1/blk00000001/sig0000015f/CYAND_8016 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYMUXFAST (
.IA(\i1/blk00000001/sig0000015f/CYMUXG2_8014 ),
.IB(\i1/blk00000001/sig0000015f/FASTCARRY_8015 ),
.SEL(\i1/blk00000001/sig0000015f/CYAND_8016 ),
.O(\i1/blk00000001/sig0000015f/CYMUXFAST_8017 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYMUXG2 (
.IA(\i1/blk00000001/sig0000015f/CY0G_8012 ),
.IB(\i1/blk00000001/sig0000015f/CYMUXF2_8013 ),
.SEL(\i1/blk00000001/sig0000015f/CYSELG_8003 ),
.O(\i1/blk00000001/sig0000015f/CYMUXG2_8014 )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CY0G (
.I(\i1/blk00000001/sig0000020a ),
.O(\i1/blk00000001/sig0000015f/CY0G_8012 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000015f/GAND/IN1 ),
.O(\i1/blk00000001/sig0000020a )
);
X_BUF #(
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/CYSELG (
.I(\i1/blk00000001/sig0000015f/G ),
.O(\i1/blk00000001/sig0000015f/CYSELG_8003 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/XUSED (
.I(\i1/blk00000001/sig00000149/XORF_8074 ),
.O(\i1/blk00000001/sig00000149 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/XORF (
.I0(\i1/blk00000001/sig00000149/CYINIT_8073 ),
.I1(\i1/blk00000001/sig00000149/F ),
.O(\i1/blk00000001/sig00000149/XORF_8074 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYMUXF (
.IA(\i1/blk00000001/sig00000149/CY0F_8072 ),
.IB(\i1/blk00000001/sig00000149/CYINIT_8073 ),
.SEL(\i1/blk00000001/sig00000149/CYSELF_8059 ),
.O(\i1/blk00000001/sig000001b1 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYMUXF2 (
.IA(\i1/blk00000001/sig00000149/CY0F_8072 ),
.IB(\i1/blk00000001/sig00000149/CY0F_8072 ),
.SEL(\i1/blk00000001/sig00000149/CYSELF_8059 ),
.O(\i1/blk00000001/sig00000149/CYMUXF2_8054 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYINIT (
.I(\i1/blk00000001/sig000001b7 ),
.O(\i1/blk00000001/sig00000149/CYINIT_8073 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CY0F (
.I(\i1/blk00000001/sig00000204 ),
.O(\i1/blk00000001/sig00000149/CY0F_8072 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000149/FAND/IN1 ),
.O(\i1/blk00000001/sig00000204 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYSELF (
.I(\i1/blk00000001/sig00000149/F ),
.O(\i1/blk00000001/sig00000149/CYSELF_8059 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/YUSED (
.I(\i1/blk00000001/sig00000149/XORG_8061 ),
.O(\i1/blk00000001/sig0000013e )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/XORG (
.I0(\i1/blk00000001/sig000001b1 ),
.I1(\i1/blk00000001/sig00000149/G ),
.O(\i1/blk00000001/sig00000149/XORG_8061 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/COUTUSED (
.I(\i1/blk00000001/sig00000149/CYMUXFAST_8058 ),
.O(\i1/blk00000001/sig000001ab )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/FASTCARRY (
.I(\i1/blk00000001/sig000001b7 ),
.O(\i1/blk00000001/sig00000149/FASTCARRY_8056 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYAND (
.I0(\i1/blk00000001/sig00000149/CYSELG_8044 ),
.I1(\i1/blk00000001/sig00000149/CYSELF_8059 ),
.O(\i1/blk00000001/sig00000149/CYAND_8057 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYMUXFAST (
.IA(\i1/blk00000001/sig00000149/CYMUXG2_8055 ),
.IB(\i1/blk00000001/sig00000149/FASTCARRY_8056 ),
.SEL(\i1/blk00000001/sig00000149/CYAND_8057 ),
.O(\i1/blk00000001/sig00000149/CYMUXFAST_8058 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYMUXG2 (
.IA(\i1/blk00000001/sig00000149/CY0G_8053 ),
.IB(\i1/blk00000001/sig00000149/CYMUXF2_8054 ),
.SEL(\i1/blk00000001/sig00000149/CYSELG_8044 ),
.O(\i1/blk00000001/sig00000149/CYMUXG2_8055 )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CY0G (
.I(\i1/blk00000001/sig000001fe ),
.O(\i1/blk00000001/sig00000149/CY0G_8053 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000149/GAND/IN1 ),
.O(\i1/blk00000001/sig000001fe )
);
X_BUF #(
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/CYSELG (
.I(\i1/blk00000001/sig00000149/G ),
.O(\i1/blk00000001/sig00000149/CYSELG_8044 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/XUSED (
.I(\i1/blk00000001/sig00000133/XORF_8115 ),
.O(\i1/blk00000001/sig00000133 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/XORF (
.I0(\i1/blk00000001/sig00000133/CYINIT_8114 ),
.I1(\i1/blk00000001/sig00000133/F ),
.O(\i1/blk00000001/sig00000133/XORF_8115 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYMUXF (
.IA(\i1/blk00000001/sig00000133/CY0F_8113 ),
.IB(\i1/blk00000001/sig00000133/CYINIT_8114 ),
.SEL(\i1/blk00000001/sig00000133/CYSELF_8101 ),
.O(\i1/blk00000001/sig000001a5 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYMUXF2 (
.IA(\i1/blk00000001/sig00000133/CY0F_8113 ),
.IB(\i1/blk00000001/sig00000133/CY0F_8113 ),
.SEL(\i1/blk00000001/sig00000133/CYSELF_8101 ),
.O(\i1/blk00000001/sig00000133/CYMUXF2_8096 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYINIT (
.I(\i1/blk00000001/sig000001ab ),
.O(\i1/blk00000001/sig00000133/CYINIT_8114 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CY0F (
.I(\i1/blk00000001/sig000001f8 ),
.O(\i1/blk00000001/sig00000133/CY0F_8113 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000133/FAND/IN1 ),
.O(\i1/blk00000001/sig000001f8 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYSELF (
.I(\i1/blk00000001/sig00000133/F ),
.O(\i1/blk00000001/sig00000133/CYSELF_8101 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/YUSED (
.I(\i1/blk00000001/sig00000133/XORG_8103 ),
.O(\i1/blk00000001/sig00000128 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/XORG (
.I0(\i1/blk00000001/sig000001a5 ),
.I1(\i1/blk00000001/sig0000011e ),
.O(\i1/blk00000001/sig00000133/XORG_8103 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/FASTCARRY (
.I(\i1/blk00000001/sig000001ab ),
.O(\i1/blk00000001/sig00000133/FASTCARRY_8098 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYAND (
.I0(\i1/blk00000001/sig00000133/CYSELG_8087 ),
.I1(\i1/blk00000001/sig00000133/CYSELF_8101 ),
.O(\i1/blk00000001/sig00000133/CYAND_8099 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYMUXFAST (
.IA(\i1/blk00000001/sig00000133/CYMUXG2_8097 ),
.IB(\i1/blk00000001/sig00000133/FASTCARRY_8098 ),
.SEL(\i1/blk00000001/sig00000133/CYAND_8099 ),
.O(\i1/blk00000001/sig00000133/CYMUXFAST_8100 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYMUXG2 (
.IA(\i1/blk00000001/sig00000133/CY0G_8095 ),
.IB(\i1/blk00000001/sig00000133/CYMUXF2_8096 ),
.SEL(\i1/blk00000001/sig00000133/CYSELG_8087 ),
.O(\i1/blk00000001/sig00000133/CYMUXG2_8097 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CY0G (
.I(\i1/blk00000001/sig000001f2 ),
.O(\i1/blk00000001/sig00000133/CY0G_8095 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000133/GAND/IN1 ),
.O(\i1/blk00000001/sig000001f2 )
);
X_BUF #(
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/CYSELG (
.I(\i1/blk00000001/sig0000011e ),
.O(\i1/blk00000001/sig00000133/CYSELG_8087 )
);
X_BUF #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/XUSED (
.I(\i1/blk00000001/sig0000011d/XORF_8147 ),
.O(\i1/blk00000001/sig0000011d )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/XORF (
.I0(\i1/blk00000001/sig0000011d/CYINIT_8146 ),
.I1(\i1/blk00000001/sig00000113 ),
.O(\i1/blk00000001/sig0000011d/XORF_8147 )
);
X_MUX2 #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/CYMUXF (
.IA(\i1/blk00000001/sig0000011d/CY0F_8145 ),
.IB(\i1/blk00000001/sig0000011d/CYINIT_8146 ),
.SEL(\i1/blk00000001/sig0000011d/CYSELF_8137 ),
.O(\i1/blk00000001/sig00000199 )
);
X_BUF #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/CYINIT (
.I(\i1/blk00000001/sig00000133/CYMUXFAST_8100 ),
.O(\i1/blk00000001/sig0000011d/CYINIT_8146 )
);
X_BUF #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/CY0F (
.I(\i1/blk00000001/sig000001ec ),
.O(\i1/blk00000001/sig0000011d/CY0F_8145 )
);
X_AND2 #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000011d/FAND/IN1 ),
.O(\i1/blk00000001/sig000001ec )
);
X_BUF #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/CYSELF (
.I(\i1/blk00000001/sig00000113 ),
.O(\i1/blk00000001/sig0000011d/CYSELF_8137 )
);
X_BUF #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/YUSED (
.I(\i1/blk00000001/sig0000011d/XORG_8134 ),
.O(\i1/blk00000001/sig00000112 )
);
X_XOR2 #(
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/sig0000011d/XORG (
.I0(\i1/blk00000001/sig00000199 ),
.I1(\i1/blk00000001/sig00000109 ),
.O(\i1/blk00000001/sig0000011d/XORG_8134 )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/XUSED (
.I(\i1/blk00000001/sig000001dd/XORF_8185 ),
.O(\i1/blk00000001/sig000001dd )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/XORF (
.I0(\i1/blk00000001/sig000001dd/CYINIT_8184 ),
.I1(\i1/blk00000001/sig000001dd/F ),
.O(\i1/blk00000001/sig000001dd/XORF_8185 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CYMUXF (
.IA(\i1/blk00000001/sig000001dd/CY0F_8183 ),
.IB(\i1/blk00000001/sig000001dd/CYINIT_8184 ),
.SEL(\i1/blk00000001/sig000001dd/CYSELF_8174 ),
.O(\i1/blk00000001/sig000001de )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CYINIT (
.I(\i1/blk00000001/sig000001dd/BXINV_8172 ),
.O(\i1/blk00000001/sig000001dd/CYINIT_8184 )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CY0F (
.I(\i1/blk00000001/sig0000022f ),
.O(\i1/blk00000001/sig000001dd/CY0F_8183 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/FAND (
.I0(x1_4_IBUF_3359),
.I1(1'b0),
.O(\i1/blk00000001/sig0000022f )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CYSELF (
.I(\i1/blk00000001/sig000001dd/F ),
.O(\i1/blk00000001/sig000001dd/CYSELF_8174 )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000001dd/BXINV_8172 )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/YUSED (
.I(\i1/blk00000001/sig000001dd/XORG_8170 ),
.O(\i1/blk00000001/sig0000018b )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/XORG (
.I0(\i1/blk00000001/sig000001de ),
.I1(\i1/blk00000001/sig000001dd/G ),
.O(\i1/blk00000001/sig000001dd/XORG_8170 )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/COUTUSED (
.I(\i1/blk00000001/sig000001dd/CYMUXG_8169 ),
.O(\i1/blk00000001/sig000001dc )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CYMUXG (
.IA(\i1/blk00000001/sig000001dd/CY0G_8167 ),
.IB(\i1/blk00000001/sig000001de ),
.SEL(\i1/blk00000001/sig000001dd/CYSELG_8158 ),
.O(\i1/blk00000001/sig000001dd/CYMUXG_8169 )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CY0G (
.I(\i1/blk00000001/sig0000022e ),
.O(\i1/blk00000001/sig000001dd/CY0G_8167 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/GAND (
.I0(x1_5_IBUF_3360),
.I1(1'b0),
.O(\i1/blk00000001/sig0000022e )
);
X_BUF #(
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/CYSELG (
.I(\i1/blk00000001/sig000001dd/G ),
.O(\i1/blk00000001/sig000001dd/CYSELG_8158 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/XUSED (
.I(\i1/blk00000001/sig00000189/XORF_8226 ),
.O(\i1/blk00000001/sig00000189 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/XORF (
.I0(\i1/blk00000001/sig00000189/CYINIT_8225 ),
.I1(\i1/blk00000001/sig00000189/F ),
.O(\i1/blk00000001/sig00000189/XORF_8226 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYMUXF (
.IA(\i1/blk00000001/sig00000189/CY0F_8224 ),
.IB(\i1/blk00000001/sig00000189/CYINIT_8225 ),
.SEL(\i1/blk00000001/sig00000189/CYSELF_8211 ),
.O(\i1/blk00000001/sig000001d3 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYMUXF2 (
.IA(\i1/blk00000001/sig00000189/CY0F_8224 ),
.IB(\i1/blk00000001/sig00000189/CY0F_8224 ),
.SEL(\i1/blk00000001/sig00000189/CYSELF_8211 ),
.O(\i1/blk00000001/sig00000189/CYMUXF2_8206 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYINIT (
.I(\i1/blk00000001/sig000001dc ),
.O(\i1/blk00000001/sig00000189/CYINIT_8225 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CY0F (
.I(\i1/blk00000001/sig00000226 ),
.O(\i1/blk00000001/sig00000189/CY0F_8224 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/FAND (
.I0(x1_5_IBUF_3360),
.I1(1'b0),
.O(\i1/blk00000001/sig00000226 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYSELF (
.I(\i1/blk00000001/sig00000189/F ),
.O(\i1/blk00000001/sig00000189/CYSELF_8211 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/YUSED (
.I(\i1/blk00000001/sig00000189/XORG_8213 ),
.O(\i1/blk00000001/sig0000017c )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/XORG (
.I0(\i1/blk00000001/sig000001d3 ),
.I1(\i1/blk00000001/sig00000189/G ),
.O(\i1/blk00000001/sig00000189/XORG_8213 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/COUTUSED (
.I(\i1/blk00000001/sig00000189/CYMUXFAST_8210 ),
.O(\i1/blk00000001/sig000001cd )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/FASTCARRY (
.I(\i1/blk00000001/sig000001dc ),
.O(\i1/blk00000001/sig00000189/FASTCARRY_8208 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYAND (
.I0(\i1/blk00000001/sig00000189/CYSELG_8196 ),
.I1(\i1/blk00000001/sig00000189/CYSELF_8211 ),
.O(\i1/blk00000001/sig00000189/CYAND_8209 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYMUXFAST (
.IA(\i1/blk00000001/sig00000189/CYMUXG2_8207 ),
.IB(\i1/blk00000001/sig00000189/FASTCARRY_8208 ),
.SEL(\i1/blk00000001/sig00000189/CYAND_8209 ),
.O(\i1/blk00000001/sig00000189/CYMUXFAST_8210 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYMUXG2 (
.IA(\i1/blk00000001/sig00000189/CY0G_8205 ),
.IB(\i1/blk00000001/sig00000189/CYMUXF2_8206 ),
.SEL(\i1/blk00000001/sig00000189/CYSELG_8196 ),
.O(\i1/blk00000001/sig00000189/CYMUXG2_8207 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CY0G (
.I(\i1/blk00000001/sig00000220 ),
.O(\i1/blk00000001/sig00000189/CY0G_8205 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/GAND (
.I0(x1_5_IBUF_3360),
.I1(1'b0),
.O(\i1/blk00000001/sig00000220 )
);
X_BUF #(
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/CYSELG (
.I(\i1/blk00000001/sig00000189/G ),
.O(\i1/blk00000001/sig00000189/CYSELG_8196 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/XUSED (
.I(\i1/blk00000001/sig00000171/XORF_8267 ),
.O(\i1/blk00000001/sig00000171 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/XORF (
.I0(\i1/blk00000001/sig00000171/CYINIT_8266 ),
.I1(\i1/blk00000001/sig00000171/F ),
.O(\i1/blk00000001/sig00000171/XORF_8267 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYMUXF (
.IA(\i1/blk00000001/sig00000171/CY0F_8265 ),
.IB(\i1/blk00000001/sig00000171/CYINIT_8266 ),
.SEL(\i1/blk00000001/sig00000171/CYSELF_8252 ),
.O(\i1/blk00000001/sig000001c7 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYMUXF2 (
.IA(\i1/blk00000001/sig00000171/CY0F_8265 ),
.IB(\i1/blk00000001/sig00000171/CY0F_8265 ),
.SEL(\i1/blk00000001/sig00000171/CYSELF_8252 ),
.O(\i1/blk00000001/sig00000171/CYMUXF2_8247 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYINIT (
.I(\i1/blk00000001/sig000001cd ),
.O(\i1/blk00000001/sig00000171/CYINIT_8266 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CY0F (
.I(\i1/blk00000001/sig0000021a ),
.O(\i1/blk00000001/sig00000171/CY0F_8265 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000171/FAND/IN1 ),
.O(\i1/blk00000001/sig0000021a )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYSELF (
.I(\i1/blk00000001/sig00000171/F ),
.O(\i1/blk00000001/sig00000171/CYSELF_8252 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/YUSED (
.I(\i1/blk00000001/sig00000171/XORG_8254 ),
.O(\i1/blk00000001/sig00000166 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/XORG (
.I0(\i1/blk00000001/sig000001c7 ),
.I1(\i1/blk00000001/sig00000171/G ),
.O(\i1/blk00000001/sig00000171/XORG_8254 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/COUTUSED (
.I(\i1/blk00000001/sig00000171/CYMUXFAST_8251 ),
.O(\i1/blk00000001/sig000001c1 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/FASTCARRY (
.I(\i1/blk00000001/sig000001cd ),
.O(\i1/blk00000001/sig00000171/FASTCARRY_8249 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYAND (
.I0(\i1/blk00000001/sig00000171/CYSELG_8237 ),
.I1(\i1/blk00000001/sig00000171/CYSELF_8252 ),
.O(\i1/blk00000001/sig00000171/CYAND_8250 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYMUXFAST (
.IA(\i1/blk00000001/sig00000171/CYMUXG2_8248 ),
.IB(\i1/blk00000001/sig00000171/FASTCARRY_8249 ),
.SEL(\i1/blk00000001/sig00000171/CYAND_8250 ),
.O(\i1/blk00000001/sig00000171/CYMUXFAST_8251 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYMUXG2 (
.IA(\i1/blk00000001/sig00000171/CY0G_8246 ),
.IB(\i1/blk00000001/sig00000171/CYMUXF2_8247 ),
.SEL(\i1/blk00000001/sig00000171/CYSELG_8237 ),
.O(\i1/blk00000001/sig00000171/CYMUXG2_8248 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CY0G (
.I(\i1/blk00000001/sig00000214 ),
.O(\i1/blk00000001/sig00000171/CY0G_8246 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000171/GAND/IN1 ),
.O(\i1/blk00000001/sig00000214 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/CYSELG (
.I(\i1/blk00000001/sig00000171/G ),
.O(\i1/blk00000001/sig00000171/CYSELG_8237 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/XUSED (
.I(\i1/blk00000001/sig0000015b/XORF_8308 ),
.O(\i1/blk00000001/sig0000015b )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/XORF (
.I0(\i1/blk00000001/sig0000015b/CYINIT_8307 ),
.I1(\i1/blk00000001/sig0000015b/F ),
.O(\i1/blk00000001/sig0000015b/XORF_8308 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYMUXF (
.IA(\i1/blk00000001/sig0000015b/CY0F_8306 ),
.IB(\i1/blk00000001/sig0000015b/CYINIT_8307 ),
.SEL(\i1/blk00000001/sig0000015b/CYSELF_8293 ),
.O(\i1/blk00000001/sig000001bb )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYMUXF2 (
.IA(\i1/blk00000001/sig0000015b/CY0F_8306 ),
.IB(\i1/blk00000001/sig0000015b/CY0F_8306 ),
.SEL(\i1/blk00000001/sig0000015b/CYSELF_8293 ),
.O(\i1/blk00000001/sig0000015b/CYMUXF2_8288 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYINIT (
.I(\i1/blk00000001/sig000001c1 ),
.O(\i1/blk00000001/sig0000015b/CYINIT_8307 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CY0F (
.I(\i1/blk00000001/sig0000020e ),
.O(\i1/blk00000001/sig0000015b/CY0F_8306 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000015b/FAND/IN1 ),
.O(\i1/blk00000001/sig0000020e )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYSELF (
.I(\i1/blk00000001/sig0000015b/F ),
.O(\i1/blk00000001/sig0000015b/CYSELF_8293 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/YUSED (
.I(\i1/blk00000001/sig0000015b/XORG_8295 ),
.O(\i1/blk00000001/sig00000150 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/XORG (
.I0(\i1/blk00000001/sig000001bb ),
.I1(\i1/blk00000001/sig0000015b/G ),
.O(\i1/blk00000001/sig0000015b/XORG_8295 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/COUTUSED (
.I(\i1/blk00000001/sig0000015b/CYMUXFAST_8292 ),
.O(\i1/blk00000001/sig000001b5 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/FASTCARRY (
.I(\i1/blk00000001/sig000001c1 ),
.O(\i1/blk00000001/sig0000015b/FASTCARRY_8290 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYAND (
.I0(\i1/blk00000001/sig0000015b/CYSELG_8278 ),
.I1(\i1/blk00000001/sig0000015b/CYSELF_8293 ),
.O(\i1/blk00000001/sig0000015b/CYAND_8291 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYMUXFAST (
.IA(\i1/blk00000001/sig0000015b/CYMUXG2_8289 ),
.IB(\i1/blk00000001/sig0000015b/FASTCARRY_8290 ),
.SEL(\i1/blk00000001/sig0000015b/CYAND_8291 ),
.O(\i1/blk00000001/sig0000015b/CYMUXFAST_8292 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYMUXG2 (
.IA(\i1/blk00000001/sig0000015b/CY0G_8287 ),
.IB(\i1/blk00000001/sig0000015b/CYMUXF2_8288 ),
.SEL(\i1/blk00000001/sig0000015b/CYSELG_8278 ),
.O(\i1/blk00000001/sig0000015b/CYMUXG2_8289 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CY0G (
.I(\i1/blk00000001/sig00000208 ),
.O(\i1/blk00000001/sig0000015b/CY0G_8287 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000015b/GAND/IN1 ),
.O(\i1/blk00000001/sig00000208 )
);
X_BUF #(
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/CYSELG (
.I(\i1/blk00000001/sig0000015b/G ),
.O(\i1/blk00000001/sig0000015b/CYSELG_8278 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/XUSED (
.I(\i1/blk00000001/sig00000145/XORF_8349 ),
.O(\i1/blk00000001/sig00000145 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/XORF (
.I0(\i1/blk00000001/sig00000145/CYINIT_8348 ),
.I1(\i1/blk00000001/sig00000145/F ),
.O(\i1/blk00000001/sig00000145/XORF_8349 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYMUXF (
.IA(\i1/blk00000001/sig00000145/CY0F_8347 ),
.IB(\i1/blk00000001/sig00000145/CYINIT_8348 ),
.SEL(\i1/blk00000001/sig00000145/CYSELF_8334 ),
.O(\i1/blk00000001/sig000001af )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYMUXF2 (
.IA(\i1/blk00000001/sig00000145/CY0F_8347 ),
.IB(\i1/blk00000001/sig00000145/CY0F_8347 ),
.SEL(\i1/blk00000001/sig00000145/CYSELF_8334 ),
.O(\i1/blk00000001/sig00000145/CYMUXF2_8329 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYINIT (
.I(\i1/blk00000001/sig000001b5 ),
.O(\i1/blk00000001/sig00000145/CYINIT_8348 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CY0F (
.I(\i1/blk00000001/sig00000202 ),
.O(\i1/blk00000001/sig00000145/CY0F_8347 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000145/FAND/IN1 ),
.O(\i1/blk00000001/sig00000202 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYSELF (
.I(\i1/blk00000001/sig00000145/F ),
.O(\i1/blk00000001/sig00000145/CYSELF_8334 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/YUSED (
.I(\i1/blk00000001/sig00000145/XORG_8336 ),
.O(\i1/blk00000001/sig0000013a )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/XORG (
.I0(\i1/blk00000001/sig000001af ),
.I1(\i1/blk00000001/sig00000145/G ),
.O(\i1/blk00000001/sig00000145/XORG_8336 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/COUTUSED (
.I(\i1/blk00000001/sig00000145/CYMUXFAST_8333 ),
.O(\i1/blk00000001/sig000001a9 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/FASTCARRY (
.I(\i1/blk00000001/sig000001b5 ),
.O(\i1/blk00000001/sig00000145/FASTCARRY_8331 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYAND (
.I0(\i1/blk00000001/sig00000145/CYSELG_8319 ),
.I1(\i1/blk00000001/sig00000145/CYSELF_8334 ),
.O(\i1/blk00000001/sig00000145/CYAND_8332 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYMUXFAST (
.IA(\i1/blk00000001/sig00000145/CYMUXG2_8330 ),
.IB(\i1/blk00000001/sig00000145/FASTCARRY_8331 ),
.SEL(\i1/blk00000001/sig00000145/CYAND_8332 ),
.O(\i1/blk00000001/sig00000145/CYMUXFAST_8333 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYMUXG2 (
.IA(\i1/blk00000001/sig00000145/CY0G_8328 ),
.IB(\i1/blk00000001/sig00000145/CYMUXF2_8329 ),
.SEL(\i1/blk00000001/sig00000145/CYSELG_8319 ),
.O(\i1/blk00000001/sig00000145/CYMUXG2_8330 )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CY0G (
.I(\i1/blk00000001/sig000001fc ),
.O(\i1/blk00000001/sig00000145/CY0G_8328 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000145/GAND/IN1 ),
.O(\i1/blk00000001/sig000001fc )
);
X_BUF #(
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/CYSELG (
.I(\i1/blk00000001/sig00000145/G ),
.O(\i1/blk00000001/sig00000145/CYSELG_8319 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/XUSED (
.I(\i1/blk00000001/sig0000012f/XORF_8390 ),
.O(\i1/blk00000001/sig0000012f )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/XORF (
.I0(\i1/blk00000001/sig0000012f/CYINIT_8389 ),
.I1(\i1/blk00000001/sig0000012f/F ),
.O(\i1/blk00000001/sig0000012f/XORF_8390 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYMUXF (
.IA(\i1/blk00000001/sig0000012f/CY0F_8388 ),
.IB(\i1/blk00000001/sig0000012f/CYINIT_8389 ),
.SEL(\i1/blk00000001/sig0000012f/CYSELF_8376 ),
.O(\i1/blk00000001/sig000001a3 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYMUXF2 (
.IA(\i1/blk00000001/sig0000012f/CY0F_8388 ),
.IB(\i1/blk00000001/sig0000012f/CY0F_8388 ),
.SEL(\i1/blk00000001/sig0000012f/CYSELF_8376 ),
.O(\i1/blk00000001/sig0000012f/CYMUXF2_8371 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYINIT (
.I(\i1/blk00000001/sig000001a9 ),
.O(\i1/blk00000001/sig0000012f/CYINIT_8389 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CY0F (
.I(\i1/blk00000001/sig000001f6 ),
.O(\i1/blk00000001/sig0000012f/CY0F_8388 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000012f/FAND/IN1 ),
.O(\i1/blk00000001/sig000001f6 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYSELF (
.I(\i1/blk00000001/sig0000012f/F ),
.O(\i1/blk00000001/sig0000012f/CYSELF_8376 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/YUSED (
.I(\i1/blk00000001/sig0000012f/XORG_8378 ),
.O(\i1/blk00000001/sig00000124 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/XORG (
.I0(\i1/blk00000001/sig000001a3 ),
.I1(\i1/blk00000001/sig0000011a ),
.O(\i1/blk00000001/sig0000012f/XORG_8378 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/FASTCARRY (
.I(\i1/blk00000001/sig000001a9 ),
.O(\i1/blk00000001/sig0000012f/FASTCARRY_8373 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYAND (
.I0(\i1/blk00000001/sig0000012f/CYSELG_8362 ),
.I1(\i1/blk00000001/sig0000012f/CYSELF_8376 ),
.O(\i1/blk00000001/sig0000012f/CYAND_8374 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYMUXFAST (
.IA(\i1/blk00000001/sig0000012f/CYMUXG2_8372 ),
.IB(\i1/blk00000001/sig0000012f/FASTCARRY_8373 ),
.SEL(\i1/blk00000001/sig0000012f/CYAND_8374 ),
.O(\i1/blk00000001/sig0000012f/CYMUXFAST_8375 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYMUXG2 (
.IA(\i1/blk00000001/sig0000012f/CY0G_8370 ),
.IB(\i1/blk00000001/sig0000012f/CYMUXF2_8371 ),
.SEL(\i1/blk00000001/sig0000012f/CYSELG_8362 ),
.O(\i1/blk00000001/sig0000012f/CYMUXG2_8372 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CY0G (
.I(\i1/blk00000001/sig000001f0 ),
.O(\i1/blk00000001/sig0000012f/CY0G_8370 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig0000012f/GAND/IN1 ),
.O(\i1/blk00000001/sig000001f0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/CYSELG (
.I(\i1/blk00000001/sig0000011a ),
.O(\i1/blk00000001/sig0000012f/CYSELG_8362 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/blk000001f3 (
.ADR0(x1_5_IBUF_3360),
.ADR1(VCC),
.ADR2(x1_4_IBUF_3359),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000010f )
);
X_BUF #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/XUSED (
.I(\i1/blk00000001/sig00000119/XORF_8422 ),
.O(\i1/blk00000001/sig00000119 )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/XORF (
.I0(\i1/blk00000001/sig00000119/CYINIT_8421 ),
.I1(\i1/blk00000001/sig0000010f ),
.O(\i1/blk00000001/sig00000119/XORF_8422 )
);
X_MUX2 #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/CYMUXF (
.IA(\i1/blk00000001/sig00000119/CY0F_8420 ),
.IB(\i1/blk00000001/sig00000119/CYINIT_8421 ),
.SEL(\i1/blk00000001/sig00000119/CYSELF_8412 ),
.O(\i1/blk00000001/sig00000197 )
);
X_BUF #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/CYINIT (
.I(\i1/blk00000001/sig0000012f/CYMUXFAST_8375 ),
.O(\i1/blk00000001/sig00000119/CYINIT_8421 )
);
X_BUF #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/CY0F (
.I(\i1/blk00000001/sig000001ea ),
.O(\i1/blk00000001/sig00000119/CY0F_8420 )
);
X_AND2 #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000119/FAND/IN1 ),
.O(\i1/blk00000001/sig000001ea )
);
X_BUF #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/CYSELF (
.I(\i1/blk00000001/sig0000010f ),
.O(\i1/blk00000001/sig00000119/CYSELF_8412 )
);
X_BUF #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/YUSED (
.I(\i1/blk00000001/sig00000119/XORG_8409 ),
.O(\i1/blk00000001/sig0000010e )
);
X_XOR2 #(
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/sig00000119/XORG (
.I0(\i1/blk00000001/sig00000197 ),
.I1(\i1/blk00000001/sig00000107 ),
.O(\i1/blk00000001/sig00000119/XORG_8409 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X12Y6" ))
\i1/blk00000001/blk000001f2 (
.ADR0(x1_4_IBUF_3359),
.ADR1(x1_5_IBUF_3360),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000107 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CYMUXF (
.IA(\i1/blk00000001/sig000001e5/CY0F_8454 ),
.IB(\i1/blk00000001/sig000001e5/CYINIT_8455 ),
.SEL(\i1/blk00000001/sig000001e5/CYSELF_8445 ),
.O(\i1/blk00000001/sig000001e6 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CYINIT (
.I(\i1/blk00000001/sig000001e5/BXINV_8443 ),
.O(\i1/blk00000001/sig000001e5/CYINIT_8455 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CY0F (
.I(\i1/blk00000001/sig00000238 ),
.O(\i1/blk00000001/sig000001e5/CY0F_8454 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000238 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CYSELF (
.I(\i1/blk00000001/sig000001e5/F ),
.O(\i1/blk00000001/sig000001e5/CYSELF_8445 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000001e5/BXINV_8443 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/COUTUSED (
.I(\i1/blk00000001/sig000001e5/CYMUXG_8442 ),
.O(\i1/blk00000001/sig000001e5 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CYMUXG (
.IA(\i1/blk00000001/sig000001e5/CY0G_8440 ),
.IB(\i1/blk00000001/sig000001e6 ),
.SEL(\i1/blk00000001/sig000001e5/CYSELG_8431 ),
.O(\i1/blk00000001/sig000001e5/CYMUXG_8442 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CY0G (
.I(\i1/blk00000001/sig00000237 ),
.O(\i1/blk00000001/sig000001e5/CY0G_8440 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000237 )
);
X_BUF #(
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/CYSELG (
.I(\i1/blk00000001/sig000001e5/G ),
.O(\i1/blk00000001/sig000001e5/CYSELG_8431 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/XUSED (
.I(\i1/blk00000001/sig00000192/XORF_8495 ),
.O(\i1/blk00000001/sig00000192 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/XORF (
.I0(\i1/blk00000001/sig00000192/CYINIT_8494 ),
.I1(\i1/blk00000001/sig00000192/F ),
.O(\i1/blk00000001/sig00000192/XORF_8495 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYMUXF (
.IA(\i1/blk00000001/sig00000192/CY0F_8493 ),
.IB(\i1/blk00000001/sig00000192/CYINIT_8494 ),
.SEL(\i1/blk00000001/sig00000192/CYSELF_8480 ),
.O(\i1/blk00000001/sig000001d6 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYMUXF2 (
.IA(\i1/blk00000001/sig00000192/CY0F_8493 ),
.IB(\i1/blk00000001/sig00000192/CY0F_8493 ),
.SEL(\i1/blk00000001/sig00000192/CYSELF_8480 ),
.O(\i1/blk00000001/sig00000192/CYMUXF2_8475 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYINIT (
.I(\i1/blk00000001/sig000001e5 ),
.O(\i1/blk00000001/sig00000192/CYINIT_8494 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CY0F (
.I(\i1/blk00000001/sig00000229 ),
.O(\i1/blk00000001/sig00000192/CY0F_8493 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000229 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYSELF (
.I(\i1/blk00000001/sig00000192/F ),
.O(\i1/blk00000001/sig00000192/CYSELF_8480 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/YUSED (
.I(\i1/blk00000001/sig00000192/XORG_8482 ),
.O(\i1/blk00000001/sig00000182 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/XORG (
.I0(\i1/blk00000001/sig000001d6 ),
.I1(\i1/blk00000001/sig00000192/G ),
.O(\i1/blk00000001/sig00000192/XORG_8482 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/COUTUSED (
.I(\i1/blk00000001/sig00000192/CYMUXFAST_8479 ),
.O(\i1/blk00000001/sig000001d0 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/FASTCARRY (
.I(\i1/blk00000001/sig000001e5 ),
.O(\i1/blk00000001/sig00000192/FASTCARRY_8477 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYAND (
.I0(\i1/blk00000001/sig00000192/CYSELG_8465 ),
.I1(\i1/blk00000001/sig00000192/CYSELF_8480 ),
.O(\i1/blk00000001/sig00000192/CYAND_8478 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYMUXFAST (
.IA(\i1/blk00000001/sig00000192/CYMUXG2_8476 ),
.IB(\i1/blk00000001/sig00000192/FASTCARRY_8477 ),
.SEL(\i1/blk00000001/sig00000192/CYAND_8478 ),
.O(\i1/blk00000001/sig00000192/CYMUXFAST_8479 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYMUXG2 (
.IA(\i1/blk00000001/sig00000192/CY0G_8474 ),
.IB(\i1/blk00000001/sig00000192/CYMUXF2_8475 ),
.SEL(\i1/blk00000001/sig00000192/CYSELG_8465 ),
.O(\i1/blk00000001/sig00000192/CYMUXG2_8476 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CY0G (
.I(\i1/blk00000001/sig00000223 ),
.O(\i1/blk00000001/sig00000192/CY0G_8474 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000223 )
);
X_BUF #(
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/CYSELG (
.I(\i1/blk00000001/sig00000192/G ),
.O(\i1/blk00000001/sig00000192/CYSELG_8465 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/XUSED (
.I(\i1/blk00000001/sig00000177/XORF_8536 ),
.O(\i1/blk00000001/sig00000177 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/XORF (
.I0(\i1/blk00000001/sig00000177/CYINIT_8535 ),
.I1(\i1/blk00000001/sig00000177/F ),
.O(\i1/blk00000001/sig00000177/XORF_8536 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYMUXF (
.IA(\i1/blk00000001/sig00000177/CY0F_8534 ),
.IB(\i1/blk00000001/sig00000177/CYINIT_8535 ),
.SEL(\i1/blk00000001/sig00000177/CYSELF_8521 ),
.O(\i1/blk00000001/sig000001ca )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYMUXF2 (
.IA(\i1/blk00000001/sig00000177/CY0F_8534 ),
.IB(\i1/blk00000001/sig00000177/CY0F_8534 ),
.SEL(\i1/blk00000001/sig00000177/CYSELF_8521 ),
.O(\i1/blk00000001/sig00000177/CYMUXF2_8516 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYINIT (
.I(\i1/blk00000001/sig000001d0 ),
.O(\i1/blk00000001/sig00000177/CYINIT_8535 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CY0F (
.I(\i1/blk00000001/sig0000021d ),
.O(\i1/blk00000001/sig00000177/CY0F_8534 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig0000021d )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYSELF (
.I(\i1/blk00000001/sig00000177/F ),
.O(\i1/blk00000001/sig00000177/CYSELF_8521 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/YUSED (
.I(\i1/blk00000001/sig00000177/XORG_8523 ),
.O(\i1/blk00000001/sig0000016c )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/XORG (
.I0(\i1/blk00000001/sig000001ca ),
.I1(\i1/blk00000001/sig00000177/G ),
.O(\i1/blk00000001/sig00000177/XORG_8523 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/COUTUSED (
.I(\i1/blk00000001/sig00000177/CYMUXFAST_8520 ),
.O(\i1/blk00000001/sig000001c4 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/FASTCARRY (
.I(\i1/blk00000001/sig000001d0 ),
.O(\i1/blk00000001/sig00000177/FASTCARRY_8518 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYAND (
.I0(\i1/blk00000001/sig00000177/CYSELG_8506 ),
.I1(\i1/blk00000001/sig00000177/CYSELF_8521 ),
.O(\i1/blk00000001/sig00000177/CYAND_8519 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYMUXFAST (
.IA(\i1/blk00000001/sig00000177/CYMUXG2_8517 ),
.IB(\i1/blk00000001/sig00000177/FASTCARRY_8518 ),
.SEL(\i1/blk00000001/sig00000177/CYAND_8519 ),
.O(\i1/blk00000001/sig00000177/CYMUXFAST_8520 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYMUXG2 (
.IA(\i1/blk00000001/sig00000177/CY0G_8515 ),
.IB(\i1/blk00000001/sig00000177/CYMUXF2_8516 ),
.SEL(\i1/blk00000001/sig00000177/CYSELG_8506 ),
.O(\i1/blk00000001/sig00000177/CYMUXG2_8517 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CY0G (
.I(\i1/blk00000001/sig00000217 ),
.O(\i1/blk00000001/sig00000177/CY0G_8515 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000217 )
);
X_BUF #(
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/CYSELG (
.I(\i1/blk00000001/sig00000177/G ),
.O(\i1/blk00000001/sig00000177/CYSELG_8506 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/XUSED (
.I(\i1/blk00000001/sig00000161/XORF_8577 ),
.O(\i1/blk00000001/sig00000161 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/XORF (
.I0(\i1/blk00000001/sig00000161/CYINIT_8576 ),
.I1(\i1/blk00000001/sig00000161/F ),
.O(\i1/blk00000001/sig00000161/XORF_8577 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYMUXF (
.IA(\i1/blk00000001/sig00000161/CY0F_8575 ),
.IB(\i1/blk00000001/sig00000161/CYINIT_8576 ),
.SEL(\i1/blk00000001/sig00000161/CYSELF_8562 ),
.O(\i1/blk00000001/sig000001be )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYMUXF2 (
.IA(\i1/blk00000001/sig00000161/CY0F_8575 ),
.IB(\i1/blk00000001/sig00000161/CY0F_8575 ),
.SEL(\i1/blk00000001/sig00000161/CYSELF_8562 ),
.O(\i1/blk00000001/sig00000161/CYMUXF2_8557 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYINIT (
.I(\i1/blk00000001/sig000001c4 ),
.O(\i1/blk00000001/sig00000161/CYINIT_8576 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CY0F (
.I(\i1/blk00000001/sig00000211 ),
.O(\i1/blk00000001/sig00000161/CY0F_8575 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000211 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYSELF (
.I(\i1/blk00000001/sig00000161/F ),
.O(\i1/blk00000001/sig00000161/CYSELF_8562 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/YUSED (
.I(\i1/blk00000001/sig00000161/XORG_8564 ),
.O(\i1/blk00000001/sig00000156 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/XORG (
.I0(\i1/blk00000001/sig000001be ),
.I1(\i1/blk00000001/sig00000161/G ),
.O(\i1/blk00000001/sig00000161/XORG_8564 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/COUTUSED (
.I(\i1/blk00000001/sig00000161/CYMUXFAST_8561 ),
.O(\i1/blk00000001/sig000001b8 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/FASTCARRY (
.I(\i1/blk00000001/sig000001c4 ),
.O(\i1/blk00000001/sig00000161/FASTCARRY_8559 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYAND (
.I0(\i1/blk00000001/sig00000161/CYSELG_8547 ),
.I1(\i1/blk00000001/sig00000161/CYSELF_8562 ),
.O(\i1/blk00000001/sig00000161/CYAND_8560 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYMUXFAST (
.IA(\i1/blk00000001/sig00000161/CYMUXG2_8558 ),
.IB(\i1/blk00000001/sig00000161/FASTCARRY_8559 ),
.SEL(\i1/blk00000001/sig00000161/CYAND_8560 ),
.O(\i1/blk00000001/sig00000161/CYMUXFAST_8561 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYMUXG2 (
.IA(\i1/blk00000001/sig00000161/CY0G_8556 ),
.IB(\i1/blk00000001/sig00000161/CYMUXF2_8557 ),
.SEL(\i1/blk00000001/sig00000161/CYSELG_8547 ),
.O(\i1/blk00000001/sig00000161/CYMUXG2_8558 )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CY0G (
.I(\i1/blk00000001/sig0000020b ),
.O(\i1/blk00000001/sig00000161/CY0G_8556 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig0000020b )
);
X_BUF #(
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/CYSELG (
.I(\i1/blk00000001/sig00000161/G ),
.O(\i1/blk00000001/sig00000161/CYSELG_8547 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/XUSED (
.I(\i1/blk00000001/sig0000014b/XORF_8618 ),
.O(\i1/blk00000001/sig0000014b )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/XORF (
.I0(\i1/blk00000001/sig0000014b/CYINIT_8617 ),
.I1(\i1/blk00000001/sig0000014b/F ),
.O(\i1/blk00000001/sig0000014b/XORF_8618 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYMUXF (
.IA(\i1/blk00000001/sig0000014b/CY0F_8616 ),
.IB(\i1/blk00000001/sig0000014b/CYINIT_8617 ),
.SEL(\i1/blk00000001/sig0000014b/CYSELF_8603 ),
.O(\i1/blk00000001/sig000001b2 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYMUXF2 (
.IA(\i1/blk00000001/sig0000014b/CY0F_8616 ),
.IB(\i1/blk00000001/sig0000014b/CY0F_8616 ),
.SEL(\i1/blk00000001/sig0000014b/CYSELF_8603 ),
.O(\i1/blk00000001/sig0000014b/CYMUXF2_8598 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYINIT (
.I(\i1/blk00000001/sig000001b8 ),
.O(\i1/blk00000001/sig0000014b/CYINIT_8617 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CY0F (
.I(\i1/blk00000001/sig00000205 ),
.O(\i1/blk00000001/sig0000014b/CY0F_8616 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig00000205 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYSELF (
.I(\i1/blk00000001/sig0000014b/F ),
.O(\i1/blk00000001/sig0000014b/CYSELF_8603 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/YUSED (
.I(\i1/blk00000001/sig0000014b/XORG_8605 ),
.O(\i1/blk00000001/sig00000140 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/XORG (
.I0(\i1/blk00000001/sig000001b2 ),
.I1(\i1/blk00000001/sig0000014b/G ),
.O(\i1/blk00000001/sig0000014b/XORG_8605 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/COUTUSED (
.I(\i1/blk00000001/sig0000014b/CYMUXFAST_8602 ),
.O(\i1/blk00000001/sig000001ac )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/FASTCARRY (
.I(\i1/blk00000001/sig000001b8 ),
.O(\i1/blk00000001/sig0000014b/FASTCARRY_8600 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYAND (
.I0(\i1/blk00000001/sig0000014b/CYSELG_8588 ),
.I1(\i1/blk00000001/sig0000014b/CYSELF_8603 ),
.O(\i1/blk00000001/sig0000014b/CYAND_8601 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYMUXFAST (
.IA(\i1/blk00000001/sig0000014b/CYMUXG2_8599 ),
.IB(\i1/blk00000001/sig0000014b/FASTCARRY_8600 ),
.SEL(\i1/blk00000001/sig0000014b/CYAND_8601 ),
.O(\i1/blk00000001/sig0000014b/CYMUXFAST_8602 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYMUXG2 (
.IA(\i1/blk00000001/sig0000014b/CY0G_8597 ),
.IB(\i1/blk00000001/sig0000014b/CYMUXF2_8598 ),
.SEL(\i1/blk00000001/sig0000014b/CYSELG_8588 ),
.O(\i1/blk00000001/sig0000014b/CYMUXG2_8599 )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CY0G (
.I(\i1/blk00000001/sig000001ff ),
.O(\i1/blk00000001/sig0000014b/CY0G_8597 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig000001ff )
);
X_BUF #(
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/CYSELG (
.I(\i1/blk00000001/sig0000014b/G ),
.O(\i1/blk00000001/sig0000014b/CYSELG_8588 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/XUSED (
.I(\i1/blk00000001/sig00000135/XORF_8659 ),
.O(\i1/blk00000001/sig00000135 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/XORF (
.I0(\i1/blk00000001/sig00000135/CYINIT_8658 ),
.I1(\i1/blk00000001/sig00000135/F ),
.O(\i1/blk00000001/sig00000135/XORF_8659 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYMUXF (
.IA(\i1/blk00000001/sig00000135/CY0F_8657 ),
.IB(\i1/blk00000001/sig00000135/CYINIT_8658 ),
.SEL(\i1/blk00000001/sig00000135/CYSELF_8644 ),
.O(\i1/blk00000001/sig000001a6 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYMUXF2 (
.IA(\i1/blk00000001/sig00000135/CY0F_8657 ),
.IB(\i1/blk00000001/sig00000135/CY0F_8657 ),
.SEL(\i1/blk00000001/sig00000135/CYSELF_8644 ),
.O(\i1/blk00000001/sig00000135/CYMUXF2_8639 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYINIT (
.I(\i1/blk00000001/sig000001ac ),
.O(\i1/blk00000001/sig00000135/CYINIT_8658 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CY0F (
.I(\i1/blk00000001/sig000001f9 ),
.O(\i1/blk00000001/sig00000135/CY0F_8657 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i1/blk00000001/sig000001f9 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYSELF (
.I(\i1/blk00000001/sig00000135/F ),
.O(\i1/blk00000001/sig00000135/CYSELF_8644 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/YUSED (
.I(\i1/blk00000001/sig00000135/XORG_8646 ),
.O(\i1/blk00000001/sig0000012a )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/XORG (
.I0(\i1/blk00000001/sig000001a6 ),
.I1(\i1/blk00000001/sig00000135/G ),
.O(\i1/blk00000001/sig00000135/XORG_8646 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/FASTCARRY (
.I(\i1/blk00000001/sig000001ac ),
.O(\i1/blk00000001/sig00000135/FASTCARRY_8641 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYAND (
.I0(\i1/blk00000001/sig00000135/CYSELG_8629 ),
.I1(\i1/blk00000001/sig00000135/CYSELF_8644 ),
.O(\i1/blk00000001/sig00000135/CYAND_8642 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYMUXFAST (
.IA(\i1/blk00000001/sig00000135/CYMUXG2_8640 ),
.IB(\i1/blk00000001/sig00000135/FASTCARRY_8641 ),
.SEL(\i1/blk00000001/sig00000135/CYAND_8642 ),
.O(\i1/blk00000001/sig00000135/CYMUXFAST_8643 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYMUXG2 (
.IA(\i1/blk00000001/sig00000135/CY0G_8638 ),
.IB(\i1/blk00000001/sig00000135/CYMUXF2_8639 ),
.SEL(\i1/blk00000001/sig00000135/CYSELG_8629 ),
.O(\i1/blk00000001/sig00000135/CYMUXG2_8640 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CY0G (
.I(\i1/blk00000001/sig000001f3 ),
.O(\i1/blk00000001/sig00000135/CY0G_8638 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/GAND (
.I0(1'b1),
.I1(1'b0),
.O(\i1/blk00000001/sig000001f3 )
);
X_BUF #(
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/CYSELG (
.I(\i1/blk00000001/sig00000135/G ),
.O(\i1/blk00000001/sig00000135/CYSELG_8629 )
);
X_BUF #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/XUSED (
.I(\i1/blk00000001/sig0000011f/XORF_8691 ),
.O(\i1/blk00000001/sig0000011f )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/XORF (
.I0(\i1/blk00000001/sig0000011f/CYINIT_8690 ),
.I1(\i1/blk00000001/sig0000011f/F ),
.O(\i1/blk00000001/sig0000011f/XORF_8691 )
);
X_MUX2 #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/CYMUXF (
.IA(\i1/blk00000001/sig0000011f/CY0F_8689 ),
.IB(\i1/blk00000001/sig0000011f/CYINIT_8690 ),
.SEL(\i1/blk00000001/sig0000011f/CYSELF_8680 ),
.O(\i1/blk00000001/sig0000019a )
);
X_BUF #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/CYINIT (
.I(\i1/blk00000001/sig00000135/CYMUXFAST_8643 ),
.O(\i1/blk00000001/sig0000011f/CYINIT_8690 )
);
X_BUF #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/CY0F (
.I(\i1/blk00000001/sig000001ed ),
.O(\i1/blk00000001/sig0000011f/CY0F_8689 )
);
X_AND2 #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/FAND (
.I0(1'b1),
.I1(1'b0),
.O(\i1/blk00000001/sig000001ed )
);
X_BUF #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/CYSELF (
.I(\i1/blk00000001/sig0000011f/F ),
.O(\i1/blk00000001/sig0000011f/CYSELF_8680 )
);
X_BUF #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/YUSED (
.I(\i1/blk00000001/sig0000011f/XORG_8677 ),
.O(\i1/blk00000001/sig00000114 )
);
X_XOR2 #(
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/XORG (
.I0(\i1/blk00000001/sig0000019a ),
.I1(\i1/blk00000001/sig0000011f/G ),
.O(\i1/blk00000001/sig0000011f/XORG_8677 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/XUSED (
.I(\i1/blk00000001/sig000001e0/XORF_8729 ),
.O(\i1/blk00000001/sig000001e0 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/XORF (
.I0(\i1/blk00000001/sig000001e0/CYINIT_8728 ),
.I1(\i1/blk00000001/sig000001e0/F ),
.O(\i1/blk00000001/sig000001e0/XORF_8729 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CYMUXF (
.IA(\i1/blk00000001/sig000001e0/CY0F_8727 ),
.IB(\i1/blk00000001/sig000001e0/CYINIT_8728 ),
.SEL(\i1/blk00000001/sig000001e0/CYSELF_8718 ),
.O(\i1/blk00000001/sig000001e1 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CYINIT (
.I(\i1/blk00000001/sig000001e0/BXINV_8716 ),
.O(\i1/blk00000001/sig000001e0/CYINIT_8728 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CY0F (
.I(\i1/blk00000001/sig00000232 ),
.O(\i1/blk00000001/sig000001e0/CY0F_8727 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/FAND (
.I0(x1_2_IBUF_3399),
.I1(1'b0),
.O(\i1/blk00000001/sig00000232 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CYSELF (
.I(\i1/blk00000001/sig000001e0/F ),
.O(\i1/blk00000001/sig000001e0/CYSELF_8718 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000001e0/BXINV_8716 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/YUSED (
.I(\i1/blk00000001/sig000001e0/XORG_8714 ),
.O(\i1/blk00000001/sig0000018e )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/XORG (
.I0(\i1/blk00000001/sig000001e1 ),
.I1(\i1/blk00000001/sig000001e0/G ),
.O(\i1/blk00000001/sig000001e0/XORG_8714 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/COUTUSED (
.I(\i1/blk00000001/sig000001e0/CYMUXG_8713 ),
.O(\i1/blk00000001/sig000001df )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CYMUXG (
.IA(\i1/blk00000001/sig000001e0/CY0G_8711 ),
.IB(\i1/blk00000001/sig000001e1 ),
.SEL(\i1/blk00000001/sig000001e0/CYSELG_8702 ),
.O(\i1/blk00000001/sig000001e0/CYMUXG_8713 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CY0G (
.I(\i1/blk00000001/sig00000231 ),
.O(\i1/blk00000001/sig000001e0/CY0G_8711 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/GAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig00000231 )
);
X_BUF #(
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/CYSELG (
.I(\i1/blk00000001/sig000001e0/G ),
.O(\i1/blk00000001/sig000001e0/CYSELG_8702 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/XUSED (
.I(\i1/blk00000001/sig0000018c/XORF_8770 ),
.O(\i1/blk00000001/sig0000018c )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/XORF (
.I0(\i1/blk00000001/sig0000018c/CYINIT_8769 ),
.I1(\i1/blk00000001/sig0000018c/F ),
.O(\i1/blk00000001/sig0000018c/XORF_8770 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYMUXF (
.IA(\i1/blk00000001/sig0000018c/CY0F_8768 ),
.IB(\i1/blk00000001/sig0000018c/CYINIT_8769 ),
.SEL(\i1/blk00000001/sig0000018c/CYSELF_8755 ),
.O(\i1/blk00000001/sig000001d4 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYMUXF2 (
.IA(\i1/blk00000001/sig0000018c/CY0F_8768 ),
.IB(\i1/blk00000001/sig0000018c/CY0F_8768 ),
.SEL(\i1/blk00000001/sig0000018c/CYSELF_8755 ),
.O(\i1/blk00000001/sig0000018c/CYMUXF2_8750 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYINIT (
.I(\i1/blk00000001/sig000001df ),
.O(\i1/blk00000001/sig0000018c/CYINIT_8769 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CY0F (
.I(\i1/blk00000001/sig00000227 ),
.O(\i1/blk00000001/sig0000018c/CY0F_8768 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/FAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig00000227 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYSELF (
.I(\i1/blk00000001/sig0000018c/F ),
.O(\i1/blk00000001/sig0000018c/CYSELF_8755 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/YUSED (
.I(\i1/blk00000001/sig0000018c/XORG_8757 ),
.O(\i1/blk00000001/sig0000017e )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/XORG (
.I0(\i1/blk00000001/sig000001d4 ),
.I1(\i1/blk00000001/sig0000018c/G ),
.O(\i1/blk00000001/sig0000018c/XORG_8757 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/COUTUSED (
.I(\i1/blk00000001/sig0000018c/CYMUXFAST_8754 ),
.O(\i1/blk00000001/sig000001ce )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/FASTCARRY (
.I(\i1/blk00000001/sig000001df ),
.O(\i1/blk00000001/sig0000018c/FASTCARRY_8752 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYAND (
.I0(\i1/blk00000001/sig0000018c/CYSELG_8740 ),
.I1(\i1/blk00000001/sig0000018c/CYSELF_8755 ),
.O(\i1/blk00000001/sig0000018c/CYAND_8753 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYMUXFAST (
.IA(\i1/blk00000001/sig0000018c/CYMUXG2_8751 ),
.IB(\i1/blk00000001/sig0000018c/FASTCARRY_8752 ),
.SEL(\i1/blk00000001/sig0000018c/CYAND_8753 ),
.O(\i1/blk00000001/sig0000018c/CYMUXFAST_8754 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYMUXG2 (
.IA(\i1/blk00000001/sig0000018c/CY0G_8749 ),
.IB(\i1/blk00000001/sig0000018c/CYMUXF2_8750 ),
.SEL(\i1/blk00000001/sig0000018c/CYSELG_8740 ),
.O(\i1/blk00000001/sig0000018c/CYMUXG2_8751 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CY0G (
.I(\i1/blk00000001/sig00000221 ),
.O(\i1/blk00000001/sig0000018c/CY0G_8749 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/GAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig00000221 )
);
X_BUF #(
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/CYSELG (
.I(\i1/blk00000001/sig0000018c/G ),
.O(\i1/blk00000001/sig0000018c/CYSELG_8740 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/XUSED (
.I(\i1/blk00000001/sig00000173/XORF_8811 ),
.O(\i1/blk00000001/sig00000173 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/XORF (
.I0(\i1/blk00000001/sig00000173/CYINIT_8810 ),
.I1(\i1/blk00000001/sig00000173/F ),
.O(\i1/blk00000001/sig00000173/XORF_8811 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYMUXF (
.IA(\i1/blk00000001/sig00000173/CY0F_8809 ),
.IB(\i1/blk00000001/sig00000173/CYINIT_8810 ),
.SEL(\i1/blk00000001/sig00000173/CYSELF_8796 ),
.O(\i1/blk00000001/sig000001c8 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYMUXF2 (
.IA(\i1/blk00000001/sig00000173/CY0F_8809 ),
.IB(\i1/blk00000001/sig00000173/CY0F_8809 ),
.SEL(\i1/blk00000001/sig00000173/CYSELF_8796 ),
.O(\i1/blk00000001/sig00000173/CYMUXF2_8791 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYINIT (
.I(\i1/blk00000001/sig000001ce ),
.O(\i1/blk00000001/sig00000173/CYINIT_8810 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CY0F (
.I(\i1/blk00000001/sig0000021b ),
.O(\i1/blk00000001/sig00000173/CY0F_8809 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/FAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig0000021b )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYSELF (
.I(\i1/blk00000001/sig00000173/F ),
.O(\i1/blk00000001/sig00000173/CYSELF_8796 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/YUSED (
.I(\i1/blk00000001/sig00000173/XORG_8798 ),
.O(\i1/blk00000001/sig00000168 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/XORG (
.I0(\i1/blk00000001/sig000001c8 ),
.I1(\i1/blk00000001/sig00000173/G ),
.O(\i1/blk00000001/sig00000173/XORG_8798 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/COUTUSED (
.I(\i1/blk00000001/sig00000173/CYMUXFAST_8795 ),
.O(\i1/blk00000001/sig000001c2 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/FASTCARRY (
.I(\i1/blk00000001/sig000001ce ),
.O(\i1/blk00000001/sig00000173/FASTCARRY_8793 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYAND (
.I0(\i1/blk00000001/sig00000173/CYSELG_8781 ),
.I1(\i1/blk00000001/sig00000173/CYSELF_8796 ),
.O(\i1/blk00000001/sig00000173/CYAND_8794 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYMUXFAST (
.IA(\i1/blk00000001/sig00000173/CYMUXG2_8792 ),
.IB(\i1/blk00000001/sig00000173/FASTCARRY_8793 ),
.SEL(\i1/blk00000001/sig00000173/CYAND_8794 ),
.O(\i1/blk00000001/sig00000173/CYMUXFAST_8795 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYMUXG2 (
.IA(\i1/blk00000001/sig00000173/CY0G_8790 ),
.IB(\i1/blk00000001/sig00000173/CYMUXF2_8791 ),
.SEL(\i1/blk00000001/sig00000173/CYSELG_8781 ),
.O(\i1/blk00000001/sig00000173/CYMUXG2_8792 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CY0G (
.I(\i1/blk00000001/sig00000215 ),
.O(\i1/blk00000001/sig00000173/CY0G_8790 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/GAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig00000215 )
);
X_BUF #(
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/CYSELG (
.I(\i1/blk00000001/sig00000173/G ),
.O(\i1/blk00000001/sig00000173/CYSELG_8781 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/XUSED (
.I(\i1/blk00000001/sig0000015d/XORF_8852 ),
.O(\i1/blk00000001/sig0000015d )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/XORF (
.I0(\i1/blk00000001/sig0000015d/CYINIT_8851 ),
.I1(\i1/blk00000001/sig0000015d/F ),
.O(\i1/blk00000001/sig0000015d/XORF_8852 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYMUXF (
.IA(\i1/blk00000001/sig0000015d/CY0F_8850 ),
.IB(\i1/blk00000001/sig0000015d/CYINIT_8851 ),
.SEL(\i1/blk00000001/sig0000015d/CYSELF_8837 ),
.O(\i1/blk00000001/sig000001bc )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYMUXF2 (
.IA(\i1/blk00000001/sig0000015d/CY0F_8850 ),
.IB(\i1/blk00000001/sig0000015d/CY0F_8850 ),
.SEL(\i1/blk00000001/sig0000015d/CYSELF_8837 ),
.O(\i1/blk00000001/sig0000015d/CYMUXF2_8832 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYINIT (
.I(\i1/blk00000001/sig000001c2 ),
.O(\i1/blk00000001/sig0000015d/CYINIT_8851 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CY0F (
.I(\i1/blk00000001/sig0000020f ),
.O(\i1/blk00000001/sig0000015d/CY0F_8850 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/FAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig0000020f )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYSELF (
.I(\i1/blk00000001/sig0000015d/F ),
.O(\i1/blk00000001/sig0000015d/CYSELF_8837 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/YUSED (
.I(\i1/blk00000001/sig0000015d/XORG_8839 ),
.O(\i1/blk00000001/sig00000152 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/XORG (
.I0(\i1/blk00000001/sig000001bc ),
.I1(\i1/blk00000001/sig0000015d/G ),
.O(\i1/blk00000001/sig0000015d/XORG_8839 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/COUTUSED (
.I(\i1/blk00000001/sig0000015d/CYMUXFAST_8836 ),
.O(\i1/blk00000001/sig000001b6 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/FASTCARRY (
.I(\i1/blk00000001/sig000001c2 ),
.O(\i1/blk00000001/sig0000015d/FASTCARRY_8834 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYAND (
.I0(\i1/blk00000001/sig0000015d/CYSELG_8822 ),
.I1(\i1/blk00000001/sig0000015d/CYSELF_8837 ),
.O(\i1/blk00000001/sig0000015d/CYAND_8835 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYMUXFAST (
.IA(\i1/blk00000001/sig0000015d/CYMUXG2_8833 ),
.IB(\i1/blk00000001/sig0000015d/FASTCARRY_8834 ),
.SEL(\i1/blk00000001/sig0000015d/CYAND_8835 ),
.O(\i1/blk00000001/sig0000015d/CYMUXFAST_8836 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYMUXG2 (
.IA(\i1/blk00000001/sig0000015d/CY0G_8831 ),
.IB(\i1/blk00000001/sig0000015d/CYMUXF2_8832 ),
.SEL(\i1/blk00000001/sig0000015d/CYSELG_8822 ),
.O(\i1/blk00000001/sig0000015d/CYMUXG2_8833 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CY0G (
.I(\i1/blk00000001/sig00000209 ),
.O(\i1/blk00000001/sig0000015d/CY0G_8831 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/GAND (
.I0(x1_3_IBUF_3400),
.I1(1'b0),
.O(\i1/blk00000001/sig00000209 )
);
X_BUF #(
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/CYSELG (
.I(\i1/blk00000001/sig0000015d/G ),
.O(\i1/blk00000001/sig0000015d/CYSELG_8822 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/XUSED (
.I(\i1/blk00000001/sig00000147/XORF_8893 ),
.O(\i1/blk00000001/sig00000147 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/XORF (
.I0(\i1/blk00000001/sig00000147/CYINIT_8892 ),
.I1(\i1/blk00000001/sig00000147/F ),
.O(\i1/blk00000001/sig00000147/XORF_8893 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYMUXF (
.IA(\i1/blk00000001/sig00000147/CY0F_8891 ),
.IB(\i1/blk00000001/sig00000147/CYINIT_8892 ),
.SEL(\i1/blk00000001/sig00000147/CYSELF_8878 ),
.O(\i1/blk00000001/sig000001b0 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYMUXF2 (
.IA(\i1/blk00000001/sig00000147/CY0F_8891 ),
.IB(\i1/blk00000001/sig00000147/CY0F_8891 ),
.SEL(\i1/blk00000001/sig00000147/CYSELF_8878 ),
.O(\i1/blk00000001/sig00000147/CYMUXF2_8873 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYINIT (
.I(\i1/blk00000001/sig000001b6 ),
.O(\i1/blk00000001/sig00000147/CYINIT_8892 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CY0F (
.I(\i1/blk00000001/sig00000203 ),
.O(\i1/blk00000001/sig00000147/CY0F_8891 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000147/FAND/IN1 ),
.O(\i1/blk00000001/sig00000203 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYSELF (
.I(\i1/blk00000001/sig00000147/F ),
.O(\i1/blk00000001/sig00000147/CYSELF_8878 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/YUSED (
.I(\i1/blk00000001/sig00000147/XORG_8880 ),
.O(\i1/blk00000001/sig0000013c )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/XORG (
.I0(\i1/blk00000001/sig000001b0 ),
.I1(\i1/blk00000001/sig00000147/G ),
.O(\i1/blk00000001/sig00000147/XORG_8880 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/COUTUSED (
.I(\i1/blk00000001/sig00000147/CYMUXFAST_8877 ),
.O(\i1/blk00000001/sig000001aa )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/FASTCARRY (
.I(\i1/blk00000001/sig000001b6 ),
.O(\i1/blk00000001/sig00000147/FASTCARRY_8875 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYAND (
.I0(\i1/blk00000001/sig00000147/CYSELG_8863 ),
.I1(\i1/blk00000001/sig00000147/CYSELF_8878 ),
.O(\i1/blk00000001/sig00000147/CYAND_8876 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYMUXFAST (
.IA(\i1/blk00000001/sig00000147/CYMUXG2_8874 ),
.IB(\i1/blk00000001/sig00000147/FASTCARRY_8875 ),
.SEL(\i1/blk00000001/sig00000147/CYAND_8876 ),
.O(\i1/blk00000001/sig00000147/CYMUXFAST_8877 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYMUXG2 (
.IA(\i1/blk00000001/sig00000147/CY0G_8872 ),
.IB(\i1/blk00000001/sig00000147/CYMUXF2_8873 ),
.SEL(\i1/blk00000001/sig00000147/CYSELG_8863 ),
.O(\i1/blk00000001/sig00000147/CYMUXG2_8874 )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CY0G (
.I(\i1/blk00000001/sig000001fd ),
.O(\i1/blk00000001/sig00000147/CY0G_8872 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000147/GAND/IN1 ),
.O(\i1/blk00000001/sig000001fd )
);
X_BUF #(
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/CYSELG (
.I(\i1/blk00000001/sig00000147/G ),
.O(\i1/blk00000001/sig00000147/CYSELG_8863 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/XUSED (
.I(\i1/blk00000001/sig00000131/XORF_8934 ),
.O(\i1/blk00000001/sig00000131 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/XORF (
.I0(\i1/blk00000001/sig00000131/CYINIT_8933 ),
.I1(\i1/blk00000001/sig00000131/F ),
.O(\i1/blk00000001/sig00000131/XORF_8934 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYMUXF (
.IA(\i1/blk00000001/sig00000131/CY0F_8932 ),
.IB(\i1/blk00000001/sig00000131/CYINIT_8933 ),
.SEL(\i1/blk00000001/sig00000131/CYSELF_8920 ),
.O(\i1/blk00000001/sig000001a4 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYMUXF2 (
.IA(\i1/blk00000001/sig00000131/CY0F_8932 ),
.IB(\i1/blk00000001/sig00000131/CY0F_8932 ),
.SEL(\i1/blk00000001/sig00000131/CYSELF_8920 ),
.O(\i1/blk00000001/sig00000131/CYMUXF2_8915 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYINIT (
.I(\i1/blk00000001/sig000001aa ),
.O(\i1/blk00000001/sig00000131/CYINIT_8933 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CY0F (
.I(\i1/blk00000001/sig000001f7 ),
.O(\i1/blk00000001/sig00000131/CY0F_8932 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000131/FAND/IN1 ),
.O(\i1/blk00000001/sig000001f7 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYSELF (
.I(\i1/blk00000001/sig00000131/F ),
.O(\i1/blk00000001/sig00000131/CYSELF_8920 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/YUSED (
.I(\i1/blk00000001/sig00000131/XORG_8922 ),
.O(\i1/blk00000001/sig00000126 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/XORG (
.I0(\i1/blk00000001/sig000001a4 ),
.I1(\i1/blk00000001/sig0000011c ),
.O(\i1/blk00000001/sig00000131/XORG_8922 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/FASTCARRY (
.I(\i1/blk00000001/sig000001aa ),
.O(\i1/blk00000001/sig00000131/FASTCARRY_8917 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYAND (
.I0(\i1/blk00000001/sig00000131/CYSELG_8906 ),
.I1(\i1/blk00000001/sig00000131/CYSELF_8920 ),
.O(\i1/blk00000001/sig00000131/CYAND_8918 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYMUXFAST (
.IA(\i1/blk00000001/sig00000131/CYMUXG2_8916 ),
.IB(\i1/blk00000001/sig00000131/FASTCARRY_8917 ),
.SEL(\i1/blk00000001/sig00000131/CYAND_8918 ),
.O(\i1/blk00000001/sig00000131/CYMUXFAST_8919 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYMUXG2 (
.IA(\i1/blk00000001/sig00000131/CY0G_8914 ),
.IB(\i1/blk00000001/sig00000131/CYMUXF2_8915 ),
.SEL(\i1/blk00000001/sig00000131/CYSELG_8906 ),
.O(\i1/blk00000001/sig00000131/CYMUXG2_8916 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CY0G (
.I(\i1/blk00000001/sig000001f1 ),
.O(\i1/blk00000001/sig00000131/CY0G_8914 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i1/blk00000001/sig00000131/GAND/IN1 ),
.O(\i1/blk00000001/sig000001f1 )
);
X_BUF #(
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/CYSELG (
.I(\i1/blk00000001/sig0000011c ),
.O(\i1/blk00000001/sig00000131/CYSELG_8906 )
);
X_BUF #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/XUSED (
.I(\i1/blk00000001/sig0000011b/XORF_8966 ),
.O(\i1/blk00000001/sig0000011b )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/XORF (
.I0(\i1/blk00000001/sig0000011b/CYINIT_8965 ),
.I1(\i1/blk00000001/sig00000111 ),
.O(\i1/blk00000001/sig0000011b/XORF_8966 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/CYMUXF (
.IA(\i1/blk00000001/sig0000011b/CY0F_8964 ),
.IB(\i1/blk00000001/sig0000011b/CYINIT_8965 ),
.SEL(\i1/blk00000001/sig0000011b/CYSELF_8956 ),
.O(\i1/blk00000001/sig00000198 )
);
X_BUF #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/CYINIT (
.I(\i1/blk00000001/sig00000131/CYMUXFAST_8919 ),
.O(\i1/blk00000001/sig0000011b/CYINIT_8965 )
);
X_BUF #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/CY0F (
.I(\i1/blk00000001/sig000001eb ),
.O(\i1/blk00000001/sig0000011b/CY0F_8964 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/FAND (
.I0(\NlwBufferSignal_i1/blk00000001/sig0000011b/FAND/IN0 ),
.I1(1'b1),
.O(\i1/blk00000001/sig000001eb )
);
X_BUF #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/CYSELF (
.I(\i1/blk00000001/sig00000111 ),
.O(\i1/blk00000001/sig0000011b/CYSELF_8956 )
);
X_BUF #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/YUSED (
.I(\i1/blk00000001/sig0000011b/XORG_8953 ),
.O(\i1/blk00000001/sig00000110 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/sig0000011b/XORG (
.I0(\i1/blk00000001/sig00000198 ),
.I1(\i1/blk00000001/sig00000108 ),
.O(\i1/blk00000001/sig0000011b/XORG_8953 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/XUSED (
.I(\i1/blk00000001/sig000000c4/XORF_9002 ),
.O(\i1/blk00000001/sig000000c4 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/XORF (
.I0(\i1/blk00000001/sig000000c4/CYINIT_9001 ),
.I1(\i1/blk00000001/sig0000008d ),
.O(\i1/blk00000001/sig000000c4/XORF_9002 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CYMUXF (
.IA(\i1/blk00000001/sig000000c4/CY0F_9000 ),
.IB(\i1/blk00000001/sig000000c4/CYINIT_9001 ),
.SEL(\i1/blk00000001/sig000000c4/CYSELF_8992 ),
.O(\i1/blk00000001/sig0000008c )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CYINIT (
.I(\i1/blk00000001/sig000000c4/BXINV_8990 ),
.O(\i1/blk00000001/sig000000c4/CYINIT_9001 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CY0F (
.I(\i1/blk00000001/sig00000186 ),
.O(\i1/blk00000001/sig000000c4/CY0F_9000 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CYSELF (
.I(\i1/blk00000001/sig0000008d ),
.O(\i1/blk00000001/sig000000c4/CYSELF_8992 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000000c4/BXINV_8990 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/YUSED (
.I(\i1/blk00000001/sig000000c4/XORG_8988 ),
.O(\i1/blk00000001/sig000000c5 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/XORG (
.I0(\i1/blk00000001/sig0000008c ),
.I1(\i1/blk00000001/sig0000008b ),
.O(\i1/blk00000001/sig000000c4/XORG_8988 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/COUTUSED (
.I(\i1/blk00000001/sig000000c4/CYMUXG_8987 ),
.O(\i1/blk00000001/sig0000008a )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CYMUXG (
.IA(\i1/blk00000001/sig000000c4/CY0G_8985 ),
.IB(\i1/blk00000001/sig0000008c ),
.SEL(\i1/blk00000001/sig000000c4/CYSELG_8977 ),
.O(\i1/blk00000001/sig000000c4/CYMUXG_8987 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CY0G (
.I(\i1/blk00000001/sig0000017a ),
.O(\i1/blk00000001/sig000000c4/CY0G_8985 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/sig000000c4/CYSELG (
.I(\i1/blk00000001/sig0000008b ),
.O(\i1/blk00000001/sig000000c4/CYSELG_8977 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/XUSED (
.I(\i1/blk00000001/sig000000c6/XORF_9041 ),
.O(\i1/blk00000001/sig000000c6 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/XORF (
.I0(\i1/blk00000001/sig000000c6/CYINIT_9040 ),
.I1(\i1/blk00000001/sig00000089 ),
.O(\i1/blk00000001/sig000000c6/XORF_9041 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYMUXF (
.IA(\i1/blk00000001/sig000000c6/CY0F_9039 ),
.IB(\i1/blk00000001/sig000000c6/CYINIT_9040 ),
.SEL(\i1/blk00000001/sig000000c6/CYSELF_9027 ),
.O(\i1/blk00000001/sig00000088 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYMUXF2 (
.IA(\i1/blk00000001/sig000000c6/CY0F_9039 ),
.IB(\i1/blk00000001/sig000000c6/CY0F_9039 ),
.SEL(\i1/blk00000001/sig000000c6/CYSELF_9027 ),
.O(\i1/blk00000001/sig000000c6/CYMUXF2_9022 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYINIT (
.I(\i1/blk00000001/sig0000008a ),
.O(\i1/blk00000001/sig000000c6/CYINIT_9040 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CY0F (
.I(\i1/blk00000001/sig0000016f ),
.O(\i1/blk00000001/sig000000c6/CY0F_9039 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYSELF (
.I(\i1/blk00000001/sig00000089 ),
.O(\i1/blk00000001/sig000000c6/CYSELF_9027 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/YUSED (
.I(\i1/blk00000001/sig000000c6/XORG_9029 ),
.O(\i1/blk00000001/sig000000c7 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/XORG (
.I0(\i1/blk00000001/sig00000088 ),
.I1(\i1/blk00000001/sig00000087 ),
.O(\i1/blk00000001/sig000000c6/XORG_9029 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/COUTUSED (
.I(\i1/blk00000001/sig000000c6/CYMUXFAST_9026 ),
.O(\i1/blk00000001/sig00000086 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/FASTCARRY (
.I(\i1/blk00000001/sig0000008a ),
.O(\i1/blk00000001/sig000000c6/FASTCARRY_9024 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYAND (
.I0(\i1/blk00000001/sig000000c6/CYSELG_9013 ),
.I1(\i1/blk00000001/sig000000c6/CYSELF_9027 ),
.O(\i1/blk00000001/sig000000c6/CYAND_9025 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYMUXFAST (
.IA(\i1/blk00000001/sig000000c6/CYMUXG2_9023 ),
.IB(\i1/blk00000001/sig000000c6/FASTCARRY_9024 ),
.SEL(\i1/blk00000001/sig000000c6/CYAND_9025 ),
.O(\i1/blk00000001/sig000000c6/CYMUXFAST_9026 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYMUXG2 (
.IA(\i1/blk00000001/sig000000c6/CY0G_9021 ),
.IB(\i1/blk00000001/sig000000c6/CYMUXF2_9022 ),
.SEL(\i1/blk00000001/sig000000c6/CYSELG_9013 ),
.O(\i1/blk00000001/sig000000c6/CYMUXG2_9023 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CY0G (
.I(\i1/blk00000001/sig00000164 ),
.O(\i1/blk00000001/sig000000c6/CY0G_9021 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/sig000000c6/CYSELG (
.I(\i1/blk00000001/sig00000087 ),
.O(\i1/blk00000001/sig000000c6/CYSELG_9013 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/XUSED (
.I(\i1/blk00000001/sig000000c8/XORF_9080 ),
.O(\i1/blk00000001/sig000000c8 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/XORF (
.I0(\i1/blk00000001/sig000000c8/CYINIT_9079 ),
.I1(\i1/blk00000001/sig00000085 ),
.O(\i1/blk00000001/sig000000c8/XORF_9080 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYMUXF (
.IA(\i1/blk00000001/sig000000c8/CY0F_9078 ),
.IB(\i1/blk00000001/sig000000c8/CYINIT_9079 ),
.SEL(\i1/blk00000001/sig000000c8/CYSELF_9066 ),
.O(\i1/blk00000001/sig00000084 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYMUXF2 (
.IA(\i1/blk00000001/sig000000c8/CY0F_9078 ),
.IB(\i1/blk00000001/sig000000c8/CY0F_9078 ),
.SEL(\i1/blk00000001/sig000000c8/CYSELF_9066 ),
.O(\i1/blk00000001/sig000000c8/CYMUXF2_9061 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYINIT (
.I(\i1/blk00000001/sig00000086 ),
.O(\i1/blk00000001/sig000000c8/CYINIT_9079 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CY0F (
.I(\i1/blk00000001/sig00000159 ),
.O(\i1/blk00000001/sig000000c8/CY0F_9078 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYSELF (
.I(\i1/blk00000001/sig00000085 ),
.O(\i1/blk00000001/sig000000c8/CYSELF_9066 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/YUSED (
.I(\i1/blk00000001/sig000000c8/XORG_9068 ),
.O(\i1/blk00000001/sig000000c9 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/XORG (
.I0(\i1/blk00000001/sig00000084 ),
.I1(\i1/blk00000001/sig00000083 ),
.O(\i1/blk00000001/sig000000c8/XORG_9068 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/COUTUSED (
.I(\i1/blk00000001/sig000000c8/CYMUXFAST_9065 ),
.O(\i1/blk00000001/sig00000082 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/FASTCARRY (
.I(\i1/blk00000001/sig00000086 ),
.O(\i1/blk00000001/sig000000c8/FASTCARRY_9063 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYAND (
.I0(\i1/blk00000001/sig000000c8/CYSELG_9052 ),
.I1(\i1/blk00000001/sig000000c8/CYSELF_9066 ),
.O(\i1/blk00000001/sig000000c8/CYAND_9064 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYMUXFAST (
.IA(\i1/blk00000001/sig000000c8/CYMUXG2_9062 ),
.IB(\i1/blk00000001/sig000000c8/FASTCARRY_9063 ),
.SEL(\i1/blk00000001/sig000000c8/CYAND_9064 ),
.O(\i1/blk00000001/sig000000c8/CYMUXFAST_9065 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYMUXG2 (
.IA(\i1/blk00000001/sig000000c8/CY0G_9060 ),
.IB(\i1/blk00000001/sig000000c8/CYMUXF2_9061 ),
.SEL(\i1/blk00000001/sig000000c8/CYSELG_9052 ),
.O(\i1/blk00000001/sig000000c8/CYMUXG2_9062 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CY0G (
.I(\i1/blk00000001/sig0000014e ),
.O(\i1/blk00000001/sig000000c8/CY0G_9060 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/sig000000c8/CYSELG (
.I(\i1/blk00000001/sig00000083 ),
.O(\i1/blk00000001/sig000000c8/CYSELG_9052 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/XUSED (
.I(\i1/blk00000001/sig000000ca/XORF_9119 ),
.O(\i1/blk00000001/sig000000ca )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/XORF (
.I0(\i1/blk00000001/sig000000ca/CYINIT_9118 ),
.I1(\i1/blk00000001/sig00000081 ),
.O(\i1/blk00000001/sig000000ca/XORF_9119 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYMUXF (
.IA(\i1/blk00000001/sig000000ca/CY0F_9117 ),
.IB(\i1/blk00000001/sig000000ca/CYINIT_9118 ),
.SEL(\i1/blk00000001/sig000000ca/CYSELF_9105 ),
.O(\i1/blk00000001/sig00000080 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYMUXF2 (
.IA(\i1/blk00000001/sig000000ca/CY0F_9117 ),
.IB(\i1/blk00000001/sig000000ca/CY0F_9117 ),
.SEL(\i1/blk00000001/sig000000ca/CYSELF_9105 ),
.O(\i1/blk00000001/sig000000ca/CYMUXF2_9100 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYINIT (
.I(\i1/blk00000001/sig00000082 ),
.O(\i1/blk00000001/sig000000ca/CYINIT_9118 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CY0F (
.I(\i1/blk00000001/sig00000143 ),
.O(\i1/blk00000001/sig000000ca/CY0F_9117 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYSELF (
.I(\i1/blk00000001/sig00000081 ),
.O(\i1/blk00000001/sig000000ca/CYSELF_9105 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/YUSED (
.I(\i1/blk00000001/sig000000ca/XORG_9107 ),
.O(\i1/blk00000001/sig000000cb )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/XORG (
.I0(\i1/blk00000001/sig00000080 ),
.I1(\i1/blk00000001/sig0000007f ),
.O(\i1/blk00000001/sig000000ca/XORG_9107 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/COUTUSED (
.I(\i1/blk00000001/sig000000ca/CYMUXFAST_9104 ),
.O(\i1/blk00000001/sig0000007e )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/FASTCARRY (
.I(\i1/blk00000001/sig00000082 ),
.O(\i1/blk00000001/sig000000ca/FASTCARRY_9102 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYAND (
.I0(\i1/blk00000001/sig000000ca/CYSELG_9091 ),
.I1(\i1/blk00000001/sig000000ca/CYSELF_9105 ),
.O(\i1/blk00000001/sig000000ca/CYAND_9103 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYMUXFAST (
.IA(\i1/blk00000001/sig000000ca/CYMUXG2_9101 ),
.IB(\i1/blk00000001/sig000000ca/FASTCARRY_9102 ),
.SEL(\i1/blk00000001/sig000000ca/CYAND_9103 ),
.O(\i1/blk00000001/sig000000ca/CYMUXFAST_9104 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYMUXG2 (
.IA(\i1/blk00000001/sig000000ca/CY0G_9099 ),
.IB(\i1/blk00000001/sig000000ca/CYMUXF2_9100 ),
.SEL(\i1/blk00000001/sig000000ca/CYSELG_9091 ),
.O(\i1/blk00000001/sig000000ca/CYMUXG2_9101 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CY0G (
.I(\i1/blk00000001/sig00000138 ),
.O(\i1/blk00000001/sig000000ca/CY0G_9099 )
);
X_BUF #(
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/sig000000ca/CYSELG (
.I(\i1/blk00000001/sig0000007f ),
.O(\i1/blk00000001/sig000000ca/CYSELG_9091 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/XUSED (
.I(\i1/blk00000001/sig000000cc/XORF_9158 ),
.O(\i1/blk00000001/sig000000cc )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/XORF (
.I0(\i1/blk00000001/sig000000cc/CYINIT_9157 ),
.I1(\i1/blk00000001/sig0000007d ),
.O(\i1/blk00000001/sig000000cc/XORF_9158 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYMUXF (
.IA(\i1/blk00000001/sig000000cc/CY0F_9156 ),
.IB(\i1/blk00000001/sig000000cc/CYINIT_9157 ),
.SEL(\i1/blk00000001/sig000000cc/CYSELF_9144 ),
.O(\i1/blk00000001/sig0000007c )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYMUXF2 (
.IA(\i1/blk00000001/sig000000cc/CY0F_9156 ),
.IB(\i1/blk00000001/sig000000cc/CY0F_9156 ),
.SEL(\i1/blk00000001/sig000000cc/CYSELF_9144 ),
.O(\i1/blk00000001/sig000000cc/CYMUXF2_9139 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYINIT (
.I(\i1/blk00000001/sig0000007e ),
.O(\i1/blk00000001/sig000000cc/CYINIT_9157 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CY0F (
.I(\i1/blk00000001/sig0000012d ),
.O(\i1/blk00000001/sig000000cc/CY0F_9156 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYSELF (
.I(\i1/blk00000001/sig0000007d ),
.O(\i1/blk00000001/sig000000cc/CYSELF_9144 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/YUSED (
.I(\i1/blk00000001/sig000000cc/XORG_9146 ),
.O(\i1/blk00000001/sig000000cd )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/XORG (
.I0(\i1/blk00000001/sig0000007c ),
.I1(\i1/blk00000001/sig0000007b ),
.O(\i1/blk00000001/sig000000cc/XORG_9146 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/COUTUSED (
.I(\i1/blk00000001/sig000000cc/CYMUXFAST_9143 ),
.O(\i1/blk00000001/sig0000007a )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/FASTCARRY (
.I(\i1/blk00000001/sig0000007e ),
.O(\i1/blk00000001/sig000000cc/FASTCARRY_9141 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYAND (
.I0(\i1/blk00000001/sig000000cc/CYSELG_9130 ),
.I1(\i1/blk00000001/sig000000cc/CYSELF_9144 ),
.O(\i1/blk00000001/sig000000cc/CYAND_9142 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYMUXFAST (
.IA(\i1/blk00000001/sig000000cc/CYMUXG2_9140 ),
.IB(\i1/blk00000001/sig000000cc/FASTCARRY_9141 ),
.SEL(\i1/blk00000001/sig000000cc/CYAND_9142 ),
.O(\i1/blk00000001/sig000000cc/CYMUXFAST_9143 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYMUXG2 (
.IA(\i1/blk00000001/sig000000cc/CY0G_9138 ),
.IB(\i1/blk00000001/sig000000cc/CYMUXF2_9139 ),
.SEL(\i1/blk00000001/sig000000cc/CYSELG_9130 ),
.O(\i1/blk00000001/sig000000cc/CYMUXG2_9140 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CY0G (
.I(\i1/blk00000001/sig00000122 ),
.O(\i1/blk00000001/sig000000cc/CY0G_9138 )
);
X_BUF #(
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/sig000000cc/CYSELG (
.I(\i1/blk00000001/sig0000007b ),
.O(\i1/blk00000001/sig000000cc/CYSELG_9130 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/XUSED (
.I(\i1/blk00000001/sig000000ce/XORF_9197 ),
.O(\i1/blk00000001/sig000000ce )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/XORF (
.I0(\i1/blk00000001/sig000000ce/CYINIT_9196 ),
.I1(\i1/blk00000001/sig00000079 ),
.O(\i1/blk00000001/sig000000ce/XORF_9197 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYMUXF (
.IA(\i1/blk00000001/sig000000ce/CY0F_9195 ),
.IB(\i1/blk00000001/sig000000ce/CYINIT_9196 ),
.SEL(\i1/blk00000001/sig000000ce/CYSELF_9183 ),
.O(\i1/blk00000001/sig00000078 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYMUXF2 (
.IA(\i1/blk00000001/sig000000ce/CY0F_9195 ),
.IB(\i1/blk00000001/sig000000ce/CY0F_9195 ),
.SEL(\i1/blk00000001/sig000000ce/CYSELF_9183 ),
.O(\i1/blk00000001/sig000000ce/CYMUXF2_9178 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYINIT (
.I(\i1/blk00000001/sig0000007a ),
.O(\i1/blk00000001/sig000000ce/CYINIT_9196 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CY0F (
.I(\i1/blk00000001/sig00000117 ),
.O(\i1/blk00000001/sig000000ce/CY0F_9195 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYSELF (
.I(\i1/blk00000001/sig00000079 ),
.O(\i1/blk00000001/sig000000ce/CYSELF_9183 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/YUSED (
.I(\i1/blk00000001/sig000000ce/XORG_9185 ),
.O(\i1/blk00000001/sig000000cf )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/XORG (
.I0(\i1/blk00000001/sig00000078 ),
.I1(\i1/blk00000001/sig00000077 ),
.O(\i1/blk00000001/sig000000ce/XORG_9185 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/FASTCARRY (
.I(\i1/blk00000001/sig0000007a ),
.O(\i1/blk00000001/sig000000ce/FASTCARRY_9180 )
);
X_AND2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYAND (
.I0(\i1/blk00000001/sig000000ce/CYSELG_9169 ),
.I1(\i1/blk00000001/sig000000ce/CYSELF_9183 ),
.O(\i1/blk00000001/sig000000ce/CYAND_9181 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYMUXFAST (
.IA(\i1/blk00000001/sig000000ce/CYMUXG2_9179 ),
.IB(\i1/blk00000001/sig000000ce/FASTCARRY_9180 ),
.SEL(\i1/blk00000001/sig000000ce/CYAND_9181 ),
.O(\i1/blk00000001/sig000000ce/CYMUXFAST_9182 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYMUXG2 (
.IA(\i1/blk00000001/sig000000ce/CY0G_9177 ),
.IB(\i1/blk00000001/sig000000ce/CYMUXF2_9178 ),
.SEL(\i1/blk00000001/sig000000ce/CYSELG_9169 ),
.O(\i1/blk00000001/sig000000ce/CYMUXG2_9179 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CY0G (
.I(\i1/blk00000001/sig0000010c ),
.O(\i1/blk00000001/sig000000ce/CY0G_9177 )
);
X_BUF #(
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/sig000000ce/CYSELG (
.I(\i1/blk00000001/sig00000077 ),
.O(\i1/blk00000001/sig000000ce/CYSELG_9169 )
);
X_BUF #(
.LOC ( "SLICE_X19Y17" ))
\i1/blk00000001/sig000000d0/XUSED (
.I(\i1/blk00000001/sig000000d0/XORF_9212 ),
.O(\i1/blk00000001/sig000000d0 )
);
X_XOR2 #(
.LOC ( "SLICE_X19Y17" ))
\i1/blk00000001/sig000000d0/XORF (
.I0(\i1/blk00000001/sig000000d0/CYINIT_9211 ),
.I1(\i1/blk00000001/sig00000075 ),
.O(\i1/blk00000001/sig000000d0/XORF_9212 )
);
X_BUF #(
.LOC ( "SLICE_X19Y17" ))
\i1/blk00000001/sig000000d0/CYINIT (
.I(\i1/blk00000001/sig000000ce/CYMUXFAST_9182 ),
.O(\i1/blk00000001/sig000000d0/CYINIT_9211 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/XUSED (
.I(\i1/blk00000001/sig000000eb/XORF_9248 ),
.O(\i1/blk00000001/sig000000eb )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/XORF (
.I0(\i1/blk00000001/sig000000eb/CYINIT_9247 ),
.I1(\i1/blk00000001/sig000000a8 ),
.O(\i1/blk00000001/sig000000eb/XORF_9248 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CYMUXF (
.IA(\i1/blk00000001/sig000000eb/CY0F_9246 ),
.IB(\i1/blk00000001/sig000000eb/CYINIT_9247 ),
.SEL(\i1/blk00000001/sig000000eb/CYSELF_9238 ),
.O(\i1/blk00000001/sig000000a7 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CYINIT (
.I(\i1/blk00000001/sig000000eb/BXINV_9236 ),
.O(\i1/blk00000001/sig000000eb/CYINIT_9247 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CY0F (
.I(\i1/blk00000001/sig0000018c ),
.O(\i1/blk00000001/sig000000eb/CY0F_9246 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CYSELF (
.I(\i1/blk00000001/sig000000a8 ),
.O(\i1/blk00000001/sig000000eb/CYSELF_9238 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000000eb/BXINV_9236 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/YUSED (
.I(\i1/blk00000001/sig000000eb/XORG_9234 ),
.O(\i1/blk00000001/sig000000ec )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/XORG (
.I0(\i1/blk00000001/sig000000a7 ),
.I1(\i1/blk00000001/sig000000a6 ),
.O(\i1/blk00000001/sig000000eb/XORG_9234 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/COUTUSED (
.I(\i1/blk00000001/sig000000eb/CYMUXG_9233 ),
.O(\i1/blk00000001/sig000000a5 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CYMUXG (
.IA(\i1/blk00000001/sig000000eb/CY0G_9231 ),
.IB(\i1/blk00000001/sig000000a7 ),
.SEL(\i1/blk00000001/sig000000eb/CYSELG_9223 ),
.O(\i1/blk00000001/sig000000eb/CYMUXG_9233 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CY0G (
.I(\i1/blk00000001/sig0000017e ),
.O(\i1/blk00000001/sig000000eb/CY0G_9231 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/sig000000eb/CYSELG (
.I(\i1/blk00000001/sig000000a6 ),
.O(\i1/blk00000001/sig000000eb/CYSELG_9223 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/blk000001a0 (
.ADR0(\i1/blk00000001/sig00000189 ),
.ADR1(\i1/blk00000001/sig00000173 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000a4 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/XUSED (
.I(\i1/blk00000001/sig000000ed/XORF_9287 ),
.O(\i1/blk00000001/sig000000ed )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/XORF (
.I0(\i1/blk00000001/sig000000ed/CYINIT_9286 ),
.I1(\i1/blk00000001/sig000000a4 ),
.O(\i1/blk00000001/sig000000ed/XORF_9287 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYMUXF (
.IA(\i1/blk00000001/sig000000ed/CY0F_9285 ),
.IB(\i1/blk00000001/sig000000ed/CYINIT_9286 ),
.SEL(\i1/blk00000001/sig000000ed/CYSELF_9273 ),
.O(\i1/blk00000001/sig000000a3 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYMUXF2 (
.IA(\i1/blk00000001/sig000000ed/CY0F_9285 ),
.IB(\i1/blk00000001/sig000000ed/CY0F_9285 ),
.SEL(\i1/blk00000001/sig000000ed/CYSELF_9273 ),
.O(\i1/blk00000001/sig000000ed/CYMUXF2_9268 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYINIT (
.I(\i1/blk00000001/sig000000a5 ),
.O(\i1/blk00000001/sig000000ed/CYINIT_9286 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CY0F (
.I(\i1/blk00000001/sig00000173 ),
.O(\i1/blk00000001/sig000000ed/CY0F_9285 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYSELF (
.I(\i1/blk00000001/sig000000a4 ),
.O(\i1/blk00000001/sig000000ed/CYSELF_9273 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/YUSED (
.I(\i1/blk00000001/sig000000ed/XORG_9275 ),
.O(\i1/blk00000001/sig000000ee )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/XORG (
.I0(\i1/blk00000001/sig000000a3 ),
.I1(\i1/blk00000001/sig000000a2 ),
.O(\i1/blk00000001/sig000000ed/XORG_9275 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/COUTUSED (
.I(\i1/blk00000001/sig000000ed/CYMUXFAST_9272 ),
.O(\i1/blk00000001/sig000000a1 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/FASTCARRY (
.I(\i1/blk00000001/sig000000a5 ),
.O(\i1/blk00000001/sig000000ed/FASTCARRY_9270 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYAND (
.I0(\i1/blk00000001/sig000000ed/CYSELG_9259 ),
.I1(\i1/blk00000001/sig000000ed/CYSELF_9273 ),
.O(\i1/blk00000001/sig000000ed/CYAND_9271 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYMUXFAST (
.IA(\i1/blk00000001/sig000000ed/CYMUXG2_9269 ),
.IB(\i1/blk00000001/sig000000ed/FASTCARRY_9270 ),
.SEL(\i1/blk00000001/sig000000ed/CYAND_9271 ),
.O(\i1/blk00000001/sig000000ed/CYMUXFAST_9272 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYMUXG2 (
.IA(\i1/blk00000001/sig000000ed/CY0G_9267 ),
.IB(\i1/blk00000001/sig000000ed/CYMUXF2_9268 ),
.SEL(\i1/blk00000001/sig000000ed/CYSELG_9259 ),
.O(\i1/blk00000001/sig000000ed/CYMUXG2_9269 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CY0G (
.I(\i1/blk00000001/sig00000168 ),
.O(\i1/blk00000001/sig000000ed/CY0G_9267 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/sig000000ed/CYSELG (
.I(\i1/blk00000001/sig000000a2 ),
.O(\i1/blk00000001/sig000000ed/CYSELG_9259 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/blk0000019a (
.ADR0(\i1/blk00000001/sig0000015d ),
.ADR1(\i1/blk00000001/sig00000171 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000a0 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/XUSED (
.I(\i1/blk00000001/sig000000ef/XORF_9326 ),
.O(\i1/blk00000001/sig000000ef )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/XORF (
.I0(\i1/blk00000001/sig000000ef/CYINIT_9325 ),
.I1(\i1/blk00000001/sig000000a0 ),
.O(\i1/blk00000001/sig000000ef/XORF_9326 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYMUXF (
.IA(\i1/blk00000001/sig000000ef/CY0F_9324 ),
.IB(\i1/blk00000001/sig000000ef/CYINIT_9325 ),
.SEL(\i1/blk00000001/sig000000ef/CYSELF_9312 ),
.O(\i1/blk00000001/sig0000009f )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYMUXF2 (
.IA(\i1/blk00000001/sig000000ef/CY0F_9324 ),
.IB(\i1/blk00000001/sig000000ef/CY0F_9324 ),
.SEL(\i1/blk00000001/sig000000ef/CYSELF_9312 ),
.O(\i1/blk00000001/sig000000ef/CYMUXF2_9307 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYINIT (
.I(\i1/blk00000001/sig000000a1 ),
.O(\i1/blk00000001/sig000000ef/CYINIT_9325 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CY0F (
.I(\i1/blk00000001/sig0000015d ),
.O(\i1/blk00000001/sig000000ef/CY0F_9324 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYSELF (
.I(\i1/blk00000001/sig000000a0 ),
.O(\i1/blk00000001/sig000000ef/CYSELF_9312 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/YUSED (
.I(\i1/blk00000001/sig000000ef/XORG_9314 ),
.O(\i1/blk00000001/sig000000f0 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/XORG (
.I0(\i1/blk00000001/sig0000009f ),
.I1(\i1/blk00000001/sig0000009e ),
.O(\i1/blk00000001/sig000000ef/XORG_9314 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/COUTUSED (
.I(\i1/blk00000001/sig000000ef/CYMUXFAST_9311 ),
.O(\i1/blk00000001/sig0000009d )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/FASTCARRY (
.I(\i1/blk00000001/sig000000a1 ),
.O(\i1/blk00000001/sig000000ef/FASTCARRY_9309 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYAND (
.I0(\i1/blk00000001/sig000000ef/CYSELG_9298 ),
.I1(\i1/blk00000001/sig000000ef/CYSELF_9312 ),
.O(\i1/blk00000001/sig000000ef/CYAND_9310 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYMUXFAST (
.IA(\i1/blk00000001/sig000000ef/CYMUXG2_9308 ),
.IB(\i1/blk00000001/sig000000ef/FASTCARRY_9309 ),
.SEL(\i1/blk00000001/sig000000ef/CYAND_9310 ),
.O(\i1/blk00000001/sig000000ef/CYMUXFAST_9311 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYMUXG2 (
.IA(\i1/blk00000001/sig000000ef/CY0G_9306 ),
.IB(\i1/blk00000001/sig000000ef/CYMUXF2_9307 ),
.SEL(\i1/blk00000001/sig000000ef/CYSELG_9298 ),
.O(\i1/blk00000001/sig000000ef/CYMUXG2_9308 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CY0G (
.I(\i1/blk00000001/sig00000152 ),
.O(\i1/blk00000001/sig000000ef/CY0G_9306 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/sig000000ef/CYSELG (
.I(\i1/blk00000001/sig0000009e ),
.O(\i1/blk00000001/sig000000ef/CYSELG_9298 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y12" ))
\i1/blk00000001/blk00000197 (
.ADR0(\i1/blk00000001/sig00000166 ),
.ADR1(\i1/blk00000001/sig00000152 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000009e )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/blk00000191 (
.ADR0(\i1/blk00000001/sig0000013c ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000150 ),
.O(\i1/blk00000001/sig0000009a )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/blk00000194 (
.ADR0(\i1/blk00000001/sig0000015b ),
.ADR1(\i1/blk00000001/sig00000147 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000009c )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/XUSED (
.I(\i1/blk00000001/sig000000f1/XORF_9365 ),
.O(\i1/blk00000001/sig000000f1 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/XORF (
.I0(\i1/blk00000001/sig000000f1/CYINIT_9364 ),
.I1(\i1/blk00000001/sig0000009c ),
.O(\i1/blk00000001/sig000000f1/XORF_9365 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYMUXF (
.IA(\i1/blk00000001/sig000000f1/CY0F_9363 ),
.IB(\i1/blk00000001/sig000000f1/CYINIT_9364 ),
.SEL(\i1/blk00000001/sig000000f1/CYSELF_9351 ),
.O(\i1/blk00000001/sig0000009b )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYMUXF2 (
.IA(\i1/blk00000001/sig000000f1/CY0F_9363 ),
.IB(\i1/blk00000001/sig000000f1/CY0F_9363 ),
.SEL(\i1/blk00000001/sig000000f1/CYSELF_9351 ),
.O(\i1/blk00000001/sig000000f1/CYMUXF2_9346 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYINIT (
.I(\i1/blk00000001/sig0000009d ),
.O(\i1/blk00000001/sig000000f1/CYINIT_9364 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CY0F (
.I(\i1/blk00000001/sig00000147 ),
.O(\i1/blk00000001/sig000000f1/CY0F_9363 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYSELF (
.I(\i1/blk00000001/sig0000009c ),
.O(\i1/blk00000001/sig000000f1/CYSELF_9351 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/YUSED (
.I(\i1/blk00000001/sig000000f1/XORG_9353 ),
.O(\i1/blk00000001/sig000000f2 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/XORG (
.I0(\i1/blk00000001/sig0000009b ),
.I1(\i1/blk00000001/sig0000009a ),
.O(\i1/blk00000001/sig000000f1/XORG_9353 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/COUTUSED (
.I(\i1/blk00000001/sig000000f1/CYMUXFAST_9350 ),
.O(\i1/blk00000001/sig00000099 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/FASTCARRY (
.I(\i1/blk00000001/sig0000009d ),
.O(\i1/blk00000001/sig000000f1/FASTCARRY_9348 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYAND (
.I0(\i1/blk00000001/sig000000f1/CYSELG_9337 ),
.I1(\i1/blk00000001/sig000000f1/CYSELF_9351 ),
.O(\i1/blk00000001/sig000000f1/CYAND_9349 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYMUXFAST (
.IA(\i1/blk00000001/sig000000f1/CYMUXG2_9347 ),
.IB(\i1/blk00000001/sig000000f1/FASTCARRY_9348 ),
.SEL(\i1/blk00000001/sig000000f1/CYAND_9349 ),
.O(\i1/blk00000001/sig000000f1/CYMUXFAST_9350 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYMUXG2 (
.IA(\i1/blk00000001/sig000000f1/CY0G_9345 ),
.IB(\i1/blk00000001/sig000000f1/CYMUXF2_9346 ),
.SEL(\i1/blk00000001/sig000000f1/CYSELG_9337 ),
.O(\i1/blk00000001/sig000000f1/CYMUXG2_9347 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CY0G (
.I(\i1/blk00000001/sig0000013c ),
.O(\i1/blk00000001/sig000000f1/CY0G_9345 )
);
X_BUF #(
.LOC ( "SLICE_X13Y13" ))
\i1/blk00000001/sig000000f1/CYSELG (
.I(\i1/blk00000001/sig0000009a ),
.O(\i1/blk00000001/sig000000f1/CYSELG_9337 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/blk0000018b (
.ADR0(\i1/blk00000001/sig0000013a ),
.ADR1(\i1/blk00000001/sig00000126 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000096 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/XUSED (
.I(\i1/blk00000001/sig000000f3/XORF_9404 ),
.O(\i1/blk00000001/sig000000f3 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/XORF (
.I0(\i1/blk00000001/sig000000f3/CYINIT_9403 ),
.I1(\i1/blk00000001/sig00000098 ),
.O(\i1/blk00000001/sig000000f3/XORF_9404 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYMUXF (
.IA(\i1/blk00000001/sig000000f3/CY0F_9402 ),
.IB(\i1/blk00000001/sig000000f3/CYINIT_9403 ),
.SEL(\i1/blk00000001/sig000000f3/CYSELF_9390 ),
.O(\i1/blk00000001/sig00000097 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYMUXF2 (
.IA(\i1/blk00000001/sig000000f3/CY0F_9402 ),
.IB(\i1/blk00000001/sig000000f3/CY0F_9402 ),
.SEL(\i1/blk00000001/sig000000f3/CYSELF_9390 ),
.O(\i1/blk00000001/sig000000f3/CYMUXF2_9385 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYINIT (
.I(\i1/blk00000001/sig00000099 ),
.O(\i1/blk00000001/sig000000f3/CYINIT_9403 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CY0F (
.I(\i1/blk00000001/sig00000131 ),
.O(\i1/blk00000001/sig000000f3/CY0F_9402 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYSELF (
.I(\i1/blk00000001/sig00000098 ),
.O(\i1/blk00000001/sig000000f3/CYSELF_9390 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/YUSED (
.I(\i1/blk00000001/sig000000f3/XORG_9392 ),
.O(\i1/blk00000001/sig000000f4 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/XORG (
.I0(\i1/blk00000001/sig00000097 ),
.I1(\i1/blk00000001/sig00000096 ),
.O(\i1/blk00000001/sig000000f3/XORG_9392 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/COUTUSED (
.I(\i1/blk00000001/sig000000f3/CYMUXFAST_9389 ),
.O(\i1/blk00000001/sig00000095 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/FASTCARRY (
.I(\i1/blk00000001/sig00000099 ),
.O(\i1/blk00000001/sig000000f3/FASTCARRY_9387 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYAND (
.I0(\i1/blk00000001/sig000000f3/CYSELG_9376 ),
.I1(\i1/blk00000001/sig000000f3/CYSELF_9390 ),
.O(\i1/blk00000001/sig000000f3/CYAND_9388 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYMUXFAST (
.IA(\i1/blk00000001/sig000000f3/CYMUXG2_9386 ),
.IB(\i1/blk00000001/sig000000f3/FASTCARRY_9387 ),
.SEL(\i1/blk00000001/sig000000f3/CYAND_9388 ),
.O(\i1/blk00000001/sig000000f3/CYMUXFAST_9389 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYMUXG2 (
.IA(\i1/blk00000001/sig000000f3/CY0G_9384 ),
.IB(\i1/blk00000001/sig000000f3/CYMUXF2_9385 ),
.SEL(\i1/blk00000001/sig000000f3/CYSELG_9376 ),
.O(\i1/blk00000001/sig000000f3/CYMUXG2_9386 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CY0G (
.I(\i1/blk00000001/sig00000126 ),
.O(\i1/blk00000001/sig000000f3/CY0G_9384 )
);
X_BUF #(
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/sig000000f3/CYSELG (
.I(\i1/blk00000001/sig00000096 ),
.O(\i1/blk00000001/sig000000f3/CYSELG_9376 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y14" ))
\i1/blk00000001/blk0000018e (
.ADR0(\i1/blk00000001/sig00000131 ),
.ADR1(\i1/blk00000001/sig00000145 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000098 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/XUSED (
.I(\i1/blk00000001/sig000000f5/XORF_9443 ),
.O(\i1/blk00000001/sig000000f5 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/XORF (
.I0(\i1/blk00000001/sig000000f5/CYINIT_9442 ),
.I1(\i1/blk00000001/sig00000094 ),
.O(\i1/blk00000001/sig000000f5/XORF_9443 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYMUXF (
.IA(\i1/blk00000001/sig000000f5/CY0F_9441 ),
.IB(\i1/blk00000001/sig000000f5/CYINIT_9442 ),
.SEL(\i1/blk00000001/sig000000f5/CYSELF_9429 ),
.O(\i1/blk00000001/sig00000093 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYMUXF2 (
.IA(\i1/blk00000001/sig000000f5/CY0F_9441 ),
.IB(\i1/blk00000001/sig000000f5/CY0F_9441 ),
.SEL(\i1/blk00000001/sig000000f5/CYSELF_9429 ),
.O(\i1/blk00000001/sig000000f5/CYMUXF2_9424 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYINIT (
.I(\i1/blk00000001/sig00000095 ),
.O(\i1/blk00000001/sig000000f5/CYINIT_9442 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CY0F (
.I(\i1/blk00000001/sig0000011b ),
.O(\i1/blk00000001/sig000000f5/CY0F_9441 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYSELF (
.I(\i1/blk00000001/sig00000094 ),
.O(\i1/blk00000001/sig000000f5/CYSELF_9429 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/YUSED (
.I(\i1/blk00000001/sig000000f5/XORG_9431 ),
.O(\i1/blk00000001/sig000000f6 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/XORG (
.I0(\i1/blk00000001/sig00000093 ),
.I1(\i1/blk00000001/sig00000092 ),
.O(\i1/blk00000001/sig000000f5/XORG_9431 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/FASTCARRY (
.I(\i1/blk00000001/sig00000095 ),
.O(\i1/blk00000001/sig000000f5/FASTCARRY_9426 )
);
X_AND2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYAND (
.I0(\i1/blk00000001/sig000000f5/CYSELG_9415 ),
.I1(\i1/blk00000001/sig000000f5/CYSELF_9429 ),
.O(\i1/blk00000001/sig000000f5/CYAND_9427 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYMUXFAST (
.IA(\i1/blk00000001/sig000000f5/CYMUXG2_9425 ),
.IB(\i1/blk00000001/sig000000f5/FASTCARRY_9426 ),
.SEL(\i1/blk00000001/sig000000f5/CYAND_9427 ),
.O(\i1/blk00000001/sig000000f5/CYMUXFAST_9428 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYMUXG2 (
.IA(\i1/blk00000001/sig000000f5/CY0G_9423 ),
.IB(\i1/blk00000001/sig000000f5/CYMUXF2_9424 ),
.SEL(\i1/blk00000001/sig000000f5/CYSELG_9415 ),
.O(\i1/blk00000001/sig000000f5/CYMUXG2_9425 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CY0G (
.I(\i1/blk00000001/sig00000110 ),
.O(\i1/blk00000001/sig000000f5/CY0G_9423 )
);
X_BUF #(
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/sig000000f5/CYSELG (
.I(\i1/blk00000001/sig00000092 ),
.O(\i1/blk00000001/sig000000f5/CYSELG_9415 )
);
X_BUF #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/XUSED (
.I(\i1/blk00000001/sig000000f7/XORF_9474 ),
.O(\i1/blk00000001/sig000000f7 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/XORF (
.I0(\i1/blk00000001/sig000000f7/CYINIT_9473 ),
.I1(\i1/blk00000001/sig00000090 ),
.O(\i1/blk00000001/sig000000f7/XORF_9474 )
);
X_MUX2 #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/CYMUXF (
.IA(\i1/blk00000001/sig000000f7/CY0F_9472 ),
.IB(\i1/blk00000001/sig000000f7/CYINIT_9473 ),
.SEL(\i1/blk00000001/sig000000f7/CYSELF_9464 ),
.O(\i1/blk00000001/sig0000008f )
);
X_BUF #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/CYINIT (
.I(\i1/blk00000001/sig000000f5/CYMUXFAST_9428 ),
.O(\i1/blk00000001/sig000000f7/CYINIT_9473 )
);
X_BUF #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/CY0F (
.I(\i1/blk00000001/sig00000110 ),
.O(\i1/blk00000001/sig000000f7/CY0F_9472 )
);
X_BUF #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/CYSELF (
.I(\i1/blk00000001/sig00000090 ),
.O(\i1/blk00000001/sig000000f7/CYSELF_9464 )
);
X_BUF #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/YUSED (
.I(\i1/blk00000001/sig000000f7/XORG_9461 ),
.O(\i1/blk00000001/sig000000f8 )
);
X_XOR2 #(
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/sig000000f7/XORG (
.I0(\i1/blk00000001/sig0000008f ),
.I1(\i1/blk00000001/sig0000008e ),
.O(\i1/blk00000001/sig000000f7/XORG_9461 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CYMUXF (
.IA(\i1/blk00000001/sig000000c0/CY0F_9504 ),
.IB(\i1/blk00000001/sig000000c0/CYINIT_9505 ),
.SEL(\i1/blk00000001/sig000000c0/CYSELF_9496 ),
.O(\i1/blk00000001/sig000000c2 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CYINIT (
.I(\i1/blk00000001/sig000000c0/BXINV_9494 ),
.O(\i1/blk00000001/sig000000c0/CYINIT_9505 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CY0F (
.I(\i1/blk00000001/sig00000192 ),
.O(\i1/blk00000001/sig000000c0/CY0F_9504 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CYSELF (
.I(\i1/blk00000001/sig000000c3 ),
.O(\i1/blk00000001/sig000000c0/CYSELF_9496 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/BXINV (
.I(1'b0),
.O(\i1/blk00000001/sig000000c0/BXINV_9494 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/COUTUSED (
.I(\i1/blk00000001/sig000000c0/CYMUXG_9493 ),
.O(\i1/blk00000001/sig000000c0 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CYMUXG (
.IA(\i1/blk00000001/sig000000c0/CY0G_9491 ),
.IB(\i1/blk00000001/sig000000c2 ),
.SEL(\i1/blk00000001/sig000000c0/CYSELG_9483 ),
.O(\i1/blk00000001/sig000000c0/CYMUXG_9493 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CY0G (
.I(\i1/blk00000001/sig00000182 ),
.O(\i1/blk00000001/sig000000c0/CY0G_9491 )
);
X_BUF #(
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/sig000000c0/CYSELG (
.I(\i1/blk00000001/sig000000c1 ),
.O(\i1/blk00000001/sig000000c0/CYSELG_9483 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/XUSED (
.I(\i1/blk00000001/sig000000f9/XORF_9543 ),
.O(\i1/blk00000001/sig000000f9 )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/XORF (
.I0(\i1/blk00000001/sig000000f9/CYINIT_9542 ),
.I1(\i1/blk00000001/sig000000bf ),
.O(\i1/blk00000001/sig000000f9/XORF_9543 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYMUXF (
.IA(\i1/blk00000001/sig000000f9/CY0F_9541 ),
.IB(\i1/blk00000001/sig000000f9/CYINIT_9542 ),
.SEL(\i1/blk00000001/sig000000f9/CYSELF_9529 ),
.O(\i1/blk00000001/sig000000be )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYMUXF2 (
.IA(\i1/blk00000001/sig000000f9/CY0F_9541 ),
.IB(\i1/blk00000001/sig000000f9/CY0F_9541 ),
.SEL(\i1/blk00000001/sig000000f9/CYSELF_9529 ),
.O(\i1/blk00000001/sig000000f9/CYMUXF2_9524 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYINIT (
.I(\i1/blk00000001/sig000000c0 ),
.O(\i1/blk00000001/sig000000f9/CYINIT_9542 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CY0F (
.I(\i1/blk00000001/sig00000177 ),
.O(\i1/blk00000001/sig000000f9/CY0F_9541 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYSELF (
.I(\i1/blk00000001/sig000000bf ),
.O(\i1/blk00000001/sig000000f9/CYSELF_9529 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/YUSED (
.I(\i1/blk00000001/sig000000f9/XORG_9531 ),
.O(\i1/blk00000001/sig000000fa )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/XORG (
.I0(\i1/blk00000001/sig000000be ),
.I1(\i1/blk00000001/sig000000bd ),
.O(\i1/blk00000001/sig000000f9/XORG_9531 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/COUTUSED (
.I(\i1/blk00000001/sig000000f9/CYMUXFAST_9528 ),
.O(\i1/blk00000001/sig000000bc )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/FASTCARRY (
.I(\i1/blk00000001/sig000000c0 ),
.O(\i1/blk00000001/sig000000f9/FASTCARRY_9526 )
);
X_AND2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYAND (
.I0(\i1/blk00000001/sig000000f9/CYSELG_9515 ),
.I1(\i1/blk00000001/sig000000f9/CYSELF_9529 ),
.O(\i1/blk00000001/sig000000f9/CYAND_9527 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYMUXFAST (
.IA(\i1/blk00000001/sig000000f9/CYMUXG2_9525 ),
.IB(\i1/blk00000001/sig000000f9/FASTCARRY_9526 ),
.SEL(\i1/blk00000001/sig000000f9/CYAND_9527 ),
.O(\i1/blk00000001/sig000000f9/CYMUXFAST_9528 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYMUXG2 (
.IA(\i1/blk00000001/sig000000f9/CY0G_9523 ),
.IB(\i1/blk00000001/sig000000f9/CYMUXF2_9524 ),
.SEL(\i1/blk00000001/sig000000f9/CYSELG_9515 ),
.O(\i1/blk00000001/sig000000f9/CYMUXG2_9525 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CY0G (
.I(\i1/blk00000001/sig0000016c ),
.O(\i1/blk00000001/sig000000f9/CY0G_9523 )
);
X_BUF #(
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/sig000000f9/CYSELG (
.I(\i1/blk00000001/sig000000bd ),
.O(\i1/blk00000001/sig000000f9/CYSELG_9515 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/XUSED (
.I(\i1/blk00000001/sig000000fb/XORF_9582 ),
.O(\i1/blk00000001/sig000000fb )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/XORF (
.I0(\i1/blk00000001/sig000000fb/CYINIT_9581 ),
.I1(\i1/blk00000001/sig000000bb ),
.O(\i1/blk00000001/sig000000fb/XORF_9582 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYMUXF (
.IA(\i1/blk00000001/sig000000fb/CY0F_9580 ),
.IB(\i1/blk00000001/sig000000fb/CYINIT_9581 ),
.SEL(\i1/blk00000001/sig000000fb/CYSELF_9568 ),
.O(\i1/blk00000001/sig000000ba )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYMUXF2 (
.IA(\i1/blk00000001/sig000000fb/CY0F_9580 ),
.IB(\i1/blk00000001/sig000000fb/CY0F_9580 ),
.SEL(\i1/blk00000001/sig000000fb/CYSELF_9568 ),
.O(\i1/blk00000001/sig000000fb/CYMUXF2_9563 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYINIT (
.I(\i1/blk00000001/sig000000bc ),
.O(\i1/blk00000001/sig000000fb/CYINIT_9581 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CY0F (
.I(\i1/blk00000001/sig00000161 ),
.O(\i1/blk00000001/sig000000fb/CY0F_9580 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYSELF (
.I(\i1/blk00000001/sig000000bb ),
.O(\i1/blk00000001/sig000000fb/CYSELF_9568 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/YUSED (
.I(\i1/blk00000001/sig000000fb/XORG_9570 ),
.O(\i1/blk00000001/sig000000fc )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/XORG (
.I0(\i1/blk00000001/sig000000ba ),
.I1(\i1/blk00000001/sig000000b9 ),
.O(\i1/blk00000001/sig000000fb/XORG_9570 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/COUTUSED (
.I(\i1/blk00000001/sig000000fb/CYMUXFAST_9567 ),
.O(\i1/blk00000001/sig000000b8 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/FASTCARRY (
.I(\i1/blk00000001/sig000000bc ),
.O(\i1/blk00000001/sig000000fb/FASTCARRY_9565 )
);
X_AND2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYAND (
.I0(\i1/blk00000001/sig000000fb/CYSELG_9554 ),
.I1(\i1/blk00000001/sig000000fb/CYSELF_9568 ),
.O(\i1/blk00000001/sig000000fb/CYAND_9566 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYMUXFAST (
.IA(\i1/blk00000001/sig000000fb/CYMUXG2_9564 ),
.IB(\i1/blk00000001/sig000000fb/FASTCARRY_9565 ),
.SEL(\i1/blk00000001/sig000000fb/CYAND_9566 ),
.O(\i1/blk00000001/sig000000fb/CYMUXFAST_9567 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYMUXG2 (
.IA(\i1/blk00000001/sig000000fb/CY0G_9562 ),
.IB(\i1/blk00000001/sig000000fb/CYMUXF2_9563 ),
.SEL(\i1/blk00000001/sig000000fb/CYSELG_9554 ),
.O(\i1/blk00000001/sig000000fb/CYMUXG2_9564 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CY0G (
.I(\i1/blk00000001/sig00000156 ),
.O(\i1/blk00000001/sig000000fb/CY0G_9562 )
);
X_BUF #(
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/sig000000fb/CYSELG (
.I(\i1/blk00000001/sig000000b9 ),
.O(\i1/blk00000001/sig000000fb/CYSELG_9554 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/XUSED (
.I(\i1/blk00000001/sig000000fd/XORF_9621 ),
.O(\i1/blk00000001/sig000000fd )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/XORF (
.I0(\i1/blk00000001/sig000000fd/CYINIT_9620 ),
.I1(\i1/blk00000001/sig000000b7 ),
.O(\i1/blk00000001/sig000000fd/XORF_9621 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYMUXF (
.IA(\i1/blk00000001/sig000000fd/CY0F_9619 ),
.IB(\i1/blk00000001/sig000000fd/CYINIT_9620 ),
.SEL(\i1/blk00000001/sig000000fd/CYSELF_9607 ),
.O(\i1/blk00000001/sig000000b6 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYMUXF2 (
.IA(\i1/blk00000001/sig000000fd/CY0F_9619 ),
.IB(\i1/blk00000001/sig000000fd/CY0F_9619 ),
.SEL(\i1/blk00000001/sig000000fd/CYSELF_9607 ),
.O(\i1/blk00000001/sig000000fd/CYMUXF2_9602 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYINIT (
.I(\i1/blk00000001/sig000000b8 ),
.O(\i1/blk00000001/sig000000fd/CYINIT_9620 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CY0F (
.I(\i1/blk00000001/sig0000014b ),
.O(\i1/blk00000001/sig000000fd/CY0F_9619 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYSELF (
.I(\i1/blk00000001/sig000000b7 ),
.O(\i1/blk00000001/sig000000fd/CYSELF_9607 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/YUSED (
.I(\i1/blk00000001/sig000000fd/XORG_9609 ),
.O(\i1/blk00000001/sig000000fe )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/XORG (
.I0(\i1/blk00000001/sig000000b6 ),
.I1(\i1/blk00000001/sig000000b5 ),
.O(\i1/blk00000001/sig000000fd/XORG_9609 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/COUTUSED (
.I(\i1/blk00000001/sig000000fd/CYMUXFAST_9606 ),
.O(\i1/blk00000001/sig000000b4 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/FASTCARRY (
.I(\i1/blk00000001/sig000000b8 ),
.O(\i1/blk00000001/sig000000fd/FASTCARRY_9604 )
);
X_AND2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYAND (
.I0(\i1/blk00000001/sig000000fd/CYSELG_9593 ),
.I1(\i1/blk00000001/sig000000fd/CYSELF_9607 ),
.O(\i1/blk00000001/sig000000fd/CYAND_9605 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYMUXFAST (
.IA(\i1/blk00000001/sig000000fd/CYMUXG2_9603 ),
.IB(\i1/blk00000001/sig000000fd/FASTCARRY_9604 ),
.SEL(\i1/blk00000001/sig000000fd/CYAND_9605 ),
.O(\i1/blk00000001/sig000000fd/CYMUXFAST_9606 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYMUXG2 (
.IA(\i1/blk00000001/sig000000fd/CY0G_9601 ),
.IB(\i1/blk00000001/sig000000fd/CYMUXF2_9602 ),
.SEL(\i1/blk00000001/sig000000fd/CYSELG_9593 ),
.O(\i1/blk00000001/sig000000fd/CYMUXG2_9603 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CY0G (
.I(\i1/blk00000001/sig00000140 ),
.O(\i1/blk00000001/sig000000fd/CY0G_9601 )
);
X_BUF #(
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/sig000000fd/CYSELG (
.I(\i1/blk00000001/sig000000b5 ),
.O(\i1/blk00000001/sig000000fd/CYSELG_9593 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/XUSED (
.I(\i1/blk00000001/sig000000ff/XORF_9660 ),
.O(\i1/blk00000001/sig000000ff )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/XORF (
.I0(\i1/blk00000001/sig000000ff/CYINIT_9659 ),
.I1(\i1/blk00000001/sig000000b3 ),
.O(\i1/blk00000001/sig000000ff/XORF_9660 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYMUXF (
.IA(\i1/blk00000001/sig000000ff/CY0F_9658 ),
.IB(\i1/blk00000001/sig000000ff/CYINIT_9659 ),
.SEL(\i1/blk00000001/sig000000ff/CYSELF_9646 ),
.O(\i1/blk00000001/sig000000b2 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYMUXF2 (
.IA(\i1/blk00000001/sig000000ff/CY0F_9658 ),
.IB(\i1/blk00000001/sig000000ff/CY0F_9658 ),
.SEL(\i1/blk00000001/sig000000ff/CYSELF_9646 ),
.O(\i1/blk00000001/sig000000ff/CYMUXF2_9641 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYINIT (
.I(\i1/blk00000001/sig000000b4 ),
.O(\i1/blk00000001/sig000000ff/CYINIT_9659 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CY0F (
.I(\i1/blk00000001/sig00000135 ),
.O(\i1/blk00000001/sig000000ff/CY0F_9658 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYSELF (
.I(\i1/blk00000001/sig000000b3 ),
.O(\i1/blk00000001/sig000000ff/CYSELF_9646 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/YUSED (
.I(\i1/blk00000001/sig000000ff/XORG_9648 ),
.O(\i1/blk00000001/sig00000100 )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/XORG (
.I0(\i1/blk00000001/sig000000b2 ),
.I1(\i1/blk00000001/sig000000b1 ),
.O(\i1/blk00000001/sig000000ff/XORG_9648 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/COUTUSED (
.I(\i1/blk00000001/sig000000ff/CYMUXFAST_9645 ),
.O(\i1/blk00000001/sig000000b0 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/FASTCARRY (
.I(\i1/blk00000001/sig000000b4 ),
.O(\i1/blk00000001/sig000000ff/FASTCARRY_9643 )
);
X_AND2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYAND (
.I0(\i1/blk00000001/sig000000ff/CYSELG_9632 ),
.I1(\i1/blk00000001/sig000000ff/CYSELF_9646 ),
.O(\i1/blk00000001/sig000000ff/CYAND_9644 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYMUXFAST (
.IA(\i1/blk00000001/sig000000ff/CYMUXG2_9642 ),
.IB(\i1/blk00000001/sig000000ff/FASTCARRY_9643 ),
.SEL(\i1/blk00000001/sig000000ff/CYAND_9644 ),
.O(\i1/blk00000001/sig000000ff/CYMUXFAST_9645 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYMUXG2 (
.IA(\i1/blk00000001/sig000000ff/CY0G_9640 ),
.IB(\i1/blk00000001/sig000000ff/CYMUXF2_9641 ),
.SEL(\i1/blk00000001/sig000000ff/CYSELG_9632 ),
.O(\i1/blk00000001/sig000000ff/CYMUXG2_9642 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CY0G (
.I(\i1/blk00000001/sig0000012a ),
.O(\i1/blk00000001/sig000000ff/CY0G_9640 )
);
X_BUF #(
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/sig000000ff/CYSELG (
.I(\i1/blk00000001/sig000000b1 ),
.O(\i1/blk00000001/sig000000ff/CYSELG_9632 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/XUSED (
.I(\i1/blk00000001/sig00000101/XORF_9699 ),
.O(\i1/blk00000001/sig00000101 )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/XORF (
.I0(\i1/blk00000001/sig00000101/CYINIT_9698 ),
.I1(\i1/blk00000001/sig000000af ),
.O(\i1/blk00000001/sig00000101/XORF_9699 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYMUXF (
.IA(\i1/blk00000001/sig00000101/CY0F_9697 ),
.IB(\i1/blk00000001/sig00000101/CYINIT_9698 ),
.SEL(\i1/blk00000001/sig00000101/CYSELF_9685 ),
.O(\i1/blk00000001/sig000000ae )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYMUXF2 (
.IA(\i1/blk00000001/sig00000101/CY0F_9697 ),
.IB(\i1/blk00000001/sig00000101/CY0F_9697 ),
.SEL(\i1/blk00000001/sig00000101/CYSELF_9685 ),
.O(\i1/blk00000001/sig00000101/CYMUXF2_9680 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYINIT (
.I(\i1/blk00000001/sig000000b0 ),
.O(\i1/blk00000001/sig00000101/CYINIT_9698 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CY0F (
.I(\i1/blk00000001/sig0000011f ),
.O(\i1/blk00000001/sig00000101/CY0F_9697 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYSELF (
.I(\i1/blk00000001/sig000000af ),
.O(\i1/blk00000001/sig00000101/CYSELF_9685 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/YUSED (
.I(\i1/blk00000001/sig00000101/XORG_9687 ),
.O(\i1/blk00000001/sig00000102 )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/XORG (
.I0(\i1/blk00000001/sig000000ae ),
.I1(\i1/blk00000001/sig000000ad ),
.O(\i1/blk00000001/sig00000101/XORG_9687 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/FASTCARRY (
.I(\i1/blk00000001/sig000000b0 ),
.O(\i1/blk00000001/sig00000101/FASTCARRY_9682 )
);
X_AND2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYAND (
.I0(\i1/blk00000001/sig00000101/CYSELG_9671 ),
.I1(\i1/blk00000001/sig00000101/CYSELF_9685 ),
.O(\i1/blk00000001/sig00000101/CYAND_9683 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYMUXFAST (
.IA(\i1/blk00000001/sig00000101/CYMUXG2_9681 ),
.IB(\i1/blk00000001/sig00000101/FASTCARRY_9682 ),
.SEL(\i1/blk00000001/sig00000101/CYAND_9683 ),
.O(\i1/blk00000001/sig00000101/CYMUXFAST_9684 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYMUXG2 (
.IA(\i1/blk00000001/sig00000101/CY0G_9679 ),
.IB(\i1/blk00000001/sig00000101/CYMUXF2_9680 ),
.SEL(\i1/blk00000001/sig00000101/CYSELG_9671 ),
.O(\i1/blk00000001/sig00000101/CYMUXG2_9681 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CY0G (
.I(\i1/blk00000001/sig00000114 ),
.O(\i1/blk00000001/sig00000101/CY0G_9679 )
);
X_BUF #(
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/sig00000101/CYSELG (
.I(\i1/blk00000001/sig000000ad ),
.O(\i1/blk00000001/sig00000101/CYSELG_9671 )
);
X_BUF #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/XUSED (
.I(\i1/blk00000001/sig00000103/XORF_9730 ),
.O(\i1/blk00000001/sig00000103 )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/XORF (
.I0(\i1/blk00000001/sig00000103/CYINIT_9729 ),
.I1(\i1/blk00000001/sig000000ab ),
.O(\i1/blk00000001/sig00000103/XORF_9730 )
);
X_MUX2 #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/CYMUXF (
.IA(\i1/blk00000001/sig00000103/CY0F_9728 ),
.IB(\i1/blk00000001/sig00000103/CYINIT_9729 ),
.SEL(\i1/blk00000001/sig00000103/CYSELF_9720 ),
.O(\i1/blk00000001/sig000000aa )
);
X_BUF #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/CYINIT (
.I(\i1/blk00000001/sig00000101/CYMUXFAST_9684 ),
.O(\i1/blk00000001/sig00000103/CYINIT_9729 )
);
X_BUF #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/CY0F (
.I(\i1/blk00000001/sig00000114 ),
.O(\i1/blk00000001/sig00000103/CY0F_9728 )
);
X_BUF #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/CYSELF (
.I(\i1/blk00000001/sig000000ab ),
.O(\i1/blk00000001/sig00000103/CYSELF_9720 )
);
X_BUF #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/YUSED (
.I(\i1/blk00000001/sig00000103/XORG_9717 ),
.O(\i1/blk00000001/sig00000104 )
);
X_XOR2 #(
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/sig00000103/XORG (
.I0(\i1/blk00000001/sig000000aa ),
.I1(\i1/blk00000001/sig000000a9 ),
.O(\i1/blk00000001/sig00000103/XORG_9717 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CYMUXF (
.IA(\i3/blk00000001/sig0000004e/CY0F_9760 ),
.IB(\i3/blk00000001/sig0000004e/CYINIT_9761 ),
.SEL(\i3/blk00000001/sig0000004e/CYSELF_9752 ),
.O(\i3/blk00000001/sig00000050 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CYINIT (
.I(\i3/blk00000001/sig0000004e/BXINV_9750 ),
.O(\i3/blk00000001/sig0000004e/CYINIT_9761 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CY0F (
.I(\i3/blk00000001/sig000000d2 ),
.O(\i3/blk00000001/sig0000004e/CY0F_9760 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CYSELF (
.I(\i3/blk00000001/sig00000051 ),
.O(\i3/blk00000001/sig0000004e/CYSELF_9752 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig0000004e/BXINV_9750 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/COUTUSED (
.I(\i3/blk00000001/sig0000004e/CYMUXG_9749 ),
.O(\i3/blk00000001/sig0000004e )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CYMUXG (
.IA(\i3/blk00000001/sig0000004e/CY0G_9747 ),
.IB(\i3/blk00000001/sig00000050 ),
.SEL(\i3/blk00000001/sig0000004e/CYSELG_9739 ),
.O(\i3/blk00000001/sig0000004e/CYMUXG_9749 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CY0G (
.I(\i3/blk00000001/sig000000d3 ),
.O(\i3/blk00000001/sig0000004e/CY0G_9747 )
);
X_BUF #(
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/sig0000004e/CYSELG (
.I(\i3/blk00000001/sig0000004f ),
.O(\i3/blk00000001/sig0000004e/CYSELG_9739 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYMUXF (
.IA(\t3<11>/CY0F_9796 ),
.IB(\t3<11>/CYINIT_9797 ),
.SEL(\t3<11>/CYSELF_9784 ),
.O(\i3/blk00000001/sig0000004c )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYMUXF2 (
.IA(\t3<11>/CY0F_9796 ),
.IB(\t3<11>/CY0F_9796 ),
.SEL(\t3<11>/CYSELF_9784 ),
.O(\t3<11>/CYMUXF2_9779 )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYINIT (
.I(\i3/blk00000001/sig0000004e ),
.O(\t3<11>/CYINIT_9797 )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CY0F (
.I(\i3/blk00000001/sig000000d4 ),
.O(\t3<11>/CY0F_9796 )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYSELF (
.I(\i3/blk00000001/sig0000004d ),
.O(\t3<11>/CYSELF_9784 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/XORG (
.I0(\i3/blk00000001/sig0000004c ),
.I1(\i3/blk00000001/sig0000004b ),
.O(\t3<11>/XORG_9786 )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/COUTUSED (
.I(\t3<11>/CYMUXFAST_9783 ),
.O(\i3/blk00000001/sig0000004a )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/FASTCARRY (
.I(\i3/blk00000001/sig0000004e ),
.O(\t3<11>/FASTCARRY_9781 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYAND (
.I0(\t3<11>/CYSELG_9770 ),
.I1(\t3<11>/CYSELF_9784 ),
.O(\t3<11>/CYAND_9782 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYMUXFAST (
.IA(\t3<11>/CYMUXG2_9780 ),
.IB(\t3<11>/FASTCARRY_9781 ),
.SEL(\t3<11>/CYAND_9782 ),
.O(\t3<11>/CYMUXFAST_9783 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYMUXG2 (
.IA(\t3<11>/CY0G_9778 ),
.IB(\t3<11>/CYMUXF2_9779 ),
.SEL(\t3<11>/CYSELG_9770 ),
.O(\t3<11>/CYMUXG2_9780 )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CY0G (
.I(\i3/blk00000001/sig000000d5 ),
.O(\t3<11>/CY0G_9778 )
);
X_BUF #(
.LOC ( "SLICE_X27Y19" ))
\t3<11>/CYSELG (
.I(\i3/blk00000001/sig0000004b ),
.O(\t3<11>/CYSELG_9770 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/XUSED (
.I(\t3<12>/XORF_9835 ),
.O(t3[12])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/XORF (
.I0(\t3<12>/CYINIT_9834 ),
.I1(\i3/blk00000001/sig00000049 ),
.O(\t3<12>/XORF_9835 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYMUXF (
.IA(\t3<12>/CY0F_9833 ),
.IB(\t3<12>/CYINIT_9834 ),
.SEL(\t3<12>/CYSELF_9821 ),
.O(\i3/blk00000001/sig00000048 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYMUXF2 (
.IA(\t3<12>/CY0F_9833 ),
.IB(\t3<12>/CY0F_9833 ),
.SEL(\t3<12>/CYSELF_9821 ),
.O(\t3<12>/CYMUXF2_9816 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYINIT (
.I(\i3/blk00000001/sig0000004a ),
.O(\t3<12>/CYINIT_9834 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CY0F (
.I(\i3/blk00000001/sig000000d6 ),
.O(\t3<12>/CY0F_9833 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYSELF (
.I(\i3/blk00000001/sig00000049 ),
.O(\t3<12>/CYSELF_9821 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/YUSED (
.I(\t3<12>/XORG_9823 ),
.O(t3[13])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/XORG (
.I0(\i3/blk00000001/sig00000048 ),
.I1(\i3/blk00000001/sig00000047 ),
.O(\t3<12>/XORG_9823 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/COUTUSED (
.I(\t3<12>/CYMUXFAST_9820 ),
.O(\i3/blk00000001/sig00000046 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/FASTCARRY (
.I(\i3/blk00000001/sig0000004a ),
.O(\t3<12>/FASTCARRY_9818 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYAND (
.I0(\t3<12>/CYSELG_9807 ),
.I1(\t3<12>/CYSELF_9821 ),
.O(\t3<12>/CYAND_9819 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYMUXFAST (
.IA(\t3<12>/CYMUXG2_9817 ),
.IB(\t3<12>/FASTCARRY_9818 ),
.SEL(\t3<12>/CYAND_9819 ),
.O(\t3<12>/CYMUXFAST_9820 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYMUXG2 (
.IA(\t3<12>/CY0G_9815 ),
.IB(\t3<12>/CYMUXF2_9816 ),
.SEL(\t3<12>/CYSELG_9807 ),
.O(\t3<12>/CYMUXG2_9817 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CY0G (
.I(\i3/blk00000001/sig000000d7 ),
.O(\t3<12>/CY0G_9815 )
);
X_BUF #(
.LOC ( "SLICE_X27Y20" ))
\t3<12>/CYSELG (
.I(\i3/blk00000001/sig00000047 ),
.O(\t3<12>/CYSELG_9807 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/XUSED (
.I(\t3<14>/XORF_9874 ),
.O(t3[14])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/XORF (
.I0(\t3<14>/CYINIT_9873 ),
.I1(\i3/blk00000001/sig00000045 ),
.O(\t3<14>/XORF_9874 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYMUXF (
.IA(\t3<14>/CY0F_9872 ),
.IB(\t3<14>/CYINIT_9873 ),
.SEL(\t3<14>/CYSELF_9860 ),
.O(\i3/blk00000001/sig00000044 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYMUXF2 (
.IA(\t3<14>/CY0F_9872 ),
.IB(\t3<14>/CY0F_9872 ),
.SEL(\t3<14>/CYSELF_9860 ),
.O(\t3<14>/CYMUXF2_9855 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYINIT (
.I(\i3/blk00000001/sig00000046 ),
.O(\t3<14>/CYINIT_9873 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CY0F (
.I(\i3/blk00000001/sig000000d8 ),
.O(\t3<14>/CY0F_9872 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYSELF (
.I(\i3/blk00000001/sig00000045 ),
.O(\t3<14>/CYSELF_9860 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/YUSED (
.I(\t3<14>/XORG_9862 ),
.O(t3[15])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/XORG (
.I0(\i3/blk00000001/sig00000044 ),
.I1(\i3/blk00000001/sig00000043 ),
.O(\t3<14>/XORG_9862 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/COUTUSED (
.I(\t3<14>/CYMUXFAST_9859 ),
.O(\i3/blk00000001/sig00000042 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/FASTCARRY (
.I(\i3/blk00000001/sig00000046 ),
.O(\t3<14>/FASTCARRY_9857 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYAND (
.I0(\t3<14>/CYSELG_9846 ),
.I1(\t3<14>/CYSELF_9860 ),
.O(\t3<14>/CYAND_9858 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYMUXFAST (
.IA(\t3<14>/CYMUXG2_9856 ),
.IB(\t3<14>/FASTCARRY_9857 ),
.SEL(\t3<14>/CYAND_9858 ),
.O(\t3<14>/CYMUXFAST_9859 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYMUXG2 (
.IA(\t3<14>/CY0G_9854 ),
.IB(\t3<14>/CYMUXF2_9855 ),
.SEL(\t3<14>/CYSELG_9846 ),
.O(\t3<14>/CYMUXG2_9856 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CY0G (
.I(\i3/blk00000001/sig000000d9 ),
.O(\t3<14>/CY0G_9854 )
);
X_BUF #(
.LOC ( "SLICE_X27Y21" ))
\t3<14>/CYSELG (
.I(\i3/blk00000001/sig00000043 ),
.O(\t3<14>/CYSELG_9846 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/XUSED (
.I(\t3<16>/XORF_9913 ),
.O(t3[16])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/XORF (
.I0(\t3<16>/CYINIT_9912 ),
.I1(\i3/blk00000001/sig00000041 ),
.O(\t3<16>/XORF_9913 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYMUXF (
.IA(\t3<16>/CY0F_9911 ),
.IB(\t3<16>/CYINIT_9912 ),
.SEL(\t3<16>/CYSELF_9899 ),
.O(\i3/blk00000001/sig00000040 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYMUXF2 (
.IA(\t3<16>/CY0F_9911 ),
.IB(\t3<16>/CY0F_9911 ),
.SEL(\t3<16>/CYSELF_9899 ),
.O(\t3<16>/CYMUXF2_9894 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYINIT (
.I(\i3/blk00000001/sig00000042 ),
.O(\t3<16>/CYINIT_9912 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CY0F (
.I(\i3/blk00000001/sig000000da ),
.O(\t3<16>/CY0F_9911 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYSELF (
.I(\i3/blk00000001/sig00000041 ),
.O(\t3<16>/CYSELF_9899 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/YUSED (
.I(\t3<16>/XORG_9901 ),
.O(t3[17])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/XORG (
.I0(\i3/blk00000001/sig00000040 ),
.I1(\i3/blk00000001/sig0000003f ),
.O(\t3<16>/XORG_9901 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/COUTUSED (
.I(\t3<16>/CYMUXFAST_9898 ),
.O(\i3/blk00000001/sig0000003e )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/FASTCARRY (
.I(\i3/blk00000001/sig00000042 ),
.O(\t3<16>/FASTCARRY_9896 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYAND (
.I0(\t3<16>/CYSELG_9885 ),
.I1(\t3<16>/CYSELF_9899 ),
.O(\t3<16>/CYAND_9897 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYMUXFAST (
.IA(\t3<16>/CYMUXG2_9895 ),
.IB(\t3<16>/FASTCARRY_9896 ),
.SEL(\t3<16>/CYAND_9897 ),
.O(\t3<16>/CYMUXFAST_9898 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYMUXG2 (
.IA(\t3<16>/CY0G_9893 ),
.IB(\t3<16>/CYMUXF2_9894 ),
.SEL(\t3<16>/CYSELG_9885 ),
.O(\t3<16>/CYMUXG2_9895 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CY0G (
.I(\i3/blk00000001/sig000000db ),
.O(\t3<16>/CY0G_9893 )
);
X_BUF #(
.LOC ( "SLICE_X27Y22" ))
\t3<16>/CYSELG (
.I(\i3/blk00000001/sig0000003f ),
.O(\t3<16>/CYSELG_9885 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/XUSED (
.I(\t3<18>/XORF_9952 ),
.O(t3[18])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/XORF (
.I0(\t3<18>/CYINIT_9951 ),
.I1(\i3/blk00000001/sig0000003d ),
.O(\t3<18>/XORF_9952 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYMUXF (
.IA(\t3<18>/CY0F_9950 ),
.IB(\t3<18>/CYINIT_9951 ),
.SEL(\t3<18>/CYSELF_9938 ),
.O(\i3/blk00000001/sig0000003c )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYMUXF2 (
.IA(\t3<18>/CY0F_9950 ),
.IB(\t3<18>/CY0F_9950 ),
.SEL(\t3<18>/CYSELF_9938 ),
.O(\t3<18>/CYMUXF2_9933 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYINIT (
.I(\i3/blk00000001/sig0000003e ),
.O(\t3<18>/CYINIT_9951 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CY0F (
.I(\i3/blk00000001/sig000000dc ),
.O(\t3<18>/CY0F_9950 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYSELF (
.I(\i3/blk00000001/sig0000003d ),
.O(\t3<18>/CYSELF_9938 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/YUSED (
.I(\t3<18>/XORG_9940 ),
.O(t3[19])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/XORG (
.I0(\i3/blk00000001/sig0000003c ),
.I1(\i3/blk00000001/sig0000003b ),
.O(\t3<18>/XORG_9940 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/COUTUSED (
.I(\t3<18>/CYMUXFAST_9937 ),
.O(\i3/blk00000001/sig0000003a )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/FASTCARRY (
.I(\i3/blk00000001/sig0000003e ),
.O(\t3<18>/FASTCARRY_9935 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYAND (
.I0(\t3<18>/CYSELG_9924 ),
.I1(\t3<18>/CYSELF_9938 ),
.O(\t3<18>/CYAND_9936 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYMUXFAST (
.IA(\t3<18>/CYMUXG2_9934 ),
.IB(\t3<18>/FASTCARRY_9935 ),
.SEL(\t3<18>/CYAND_9936 ),
.O(\t3<18>/CYMUXFAST_9937 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYMUXG2 (
.IA(\t3<18>/CY0G_9932 ),
.IB(\t3<18>/CYMUXF2_9933 ),
.SEL(\t3<18>/CYSELG_9924 ),
.O(\t3<18>/CYMUXG2_9934 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CY0G (
.I(\i3/blk00000001/sig000000dd ),
.O(\t3<18>/CY0G_9932 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\t3<18>/CYSELG (
.I(\i3/blk00000001/sig0000003b ),
.O(\t3<18>/CYSELG_9924 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/XUSED (
.I(\t3<20>/XORF_9991 ),
.O(t3[20])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/XORF (
.I0(\t3<20>/CYINIT_9990 ),
.I1(\i3/blk00000001/sig00000039 ),
.O(\t3<20>/XORF_9991 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYMUXF (
.IA(\t3<20>/CY0F_9989 ),
.IB(\t3<20>/CYINIT_9990 ),
.SEL(\t3<20>/CYSELF_9977 ),
.O(\i3/blk00000001/sig00000038 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYMUXF2 (
.IA(\t3<20>/CY0F_9989 ),
.IB(\t3<20>/CY0F_9989 ),
.SEL(\t3<20>/CYSELF_9977 ),
.O(\t3<20>/CYMUXF2_9972 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYINIT (
.I(\i3/blk00000001/sig0000003a ),
.O(\t3<20>/CYINIT_9990 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CY0F (
.I(\i3/blk00000001/sig000000de ),
.O(\t3<20>/CY0F_9989 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYSELF (
.I(\i3/blk00000001/sig00000039 ),
.O(\t3<20>/CYSELF_9977 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/YUSED (
.I(\t3<20>/XORG_9979 ),
.O(t3[21])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/XORG (
.I0(\i3/blk00000001/sig00000038 ),
.I1(\i3/blk00000001/sig00000037 ),
.O(\t3<20>/XORG_9979 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/FASTCARRY (
.I(\i3/blk00000001/sig0000003a ),
.O(\t3<20>/FASTCARRY_9974 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYAND (
.I0(\t3<20>/CYSELG_9963 ),
.I1(\t3<20>/CYSELF_9977 ),
.O(\t3<20>/CYAND_9975 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYMUXFAST (
.IA(\t3<20>/CYMUXG2_9973 ),
.IB(\t3<20>/FASTCARRY_9974 ),
.SEL(\t3<20>/CYAND_9975 ),
.O(\t3<20>/CYMUXFAST_9976 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYMUXG2 (
.IA(\t3<20>/CY0G_9971 ),
.IB(\t3<20>/CYMUXF2_9972 ),
.SEL(\t3<20>/CYSELG_9963 ),
.O(\t3<20>/CYMUXG2_9973 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CY0G (
.I(\i3/blk00000001/sig000000de ),
.O(\t3<20>/CY0G_9971 )
);
X_BUF #(
.LOC ( "SLICE_X27Y24" ))
\t3<20>/CYSELG (
.I(\i3/blk00000001/sig00000037 ),
.O(\t3<20>/CYSELG_9963 )
);
X_BUF #(
.LOC ( "SLICE_X27Y25" ))
\t3<22>/XUSED (
.I(\t3<22>/XORF_10006 ),
.O(t3[22])
);
X_XOR2 #(
.LOC ( "SLICE_X27Y25" ))
\t3<22>/XORF (
.I0(\t3<22>/CYINIT_10005 ),
.I1(\i3/blk00000001/sig00000035 ),
.O(\t3<22>/XORF_10006 )
);
X_BUF #(
.LOC ( "SLICE_X27Y25" ))
\t3<22>/CYINIT (
.I(\t3<20>/CYMUXFAST_9976 ),
.O(\t3<22>/CYINIT_10005 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CYMUXF (
.IA(\i3/blk00000001/sig0000006f/CY0F_10036 ),
.IB(\i3/blk00000001/sig0000006f/CYINIT_10037 ),
.SEL(\i3/blk00000001/sig0000006f/CYSELF_10028 ),
.O(\i3/blk00000001/sig00000071 )
);
X_BUF #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CYINIT (
.I(\i3/blk00000001/sig0000006f/BXINV_10026 ),
.O(\i3/blk00000001/sig0000006f/CYINIT_10037 )
);
X_BUF #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CY0F (
.I(\i3/blk00000001/sig000000f9 ),
.O(\i3/blk00000001/sig0000006f/CY0F_10036 )
);
X_BUF #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CYSELF (
.I(\i3/blk00000001/sig00000072 ),
.O(\i3/blk00000001/sig0000006f/CYSELF_10028 )
);
X_BUF #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig0000006f/BXINV_10026 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CYMUXG (
.IA(\i3/blk00000001/sig0000006f/CY0G_10023 ),
.IB(\i3/blk00000001/sig00000071 ),
.SEL(\i3/blk00000001/sig0000006f/CYSELG_10015 ),
.O(\i3/blk00000001/sig0000006f/CYMUXG_10025 )
);
X_BUF #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CY0G (
.I(\i3/blk00000001/sig000000fa ),
.O(\i3/blk00000001/sig0000006f/CY0G_10023 )
);
X_BUF #(
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/sig0000006f/CYSELG (
.I(\i3/blk00000001/sig00000070 ),
.O(\i3/blk00000001/sig0000006f/CYSELG_10015 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CYMUXF2 (
.IA(\i3/blk00000001/sig0000006b/CY0F_10068 ),
.IB(\i3/blk00000001/sig0000006b/CY0F_10068 ),
.SEL(\i3/blk00000001/sig0000006b/CYSELF_10059 ),
.O(\i3/blk00000001/sig0000006b/CYMUXF2_10054 )
);
X_BUF #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CY0F (
.I(\i3/blk00000001/sig000000fb ),
.O(\i3/blk00000001/sig0000006b/CY0F_10068 )
);
X_BUF #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CYSELF (
.I(\i3/blk00000001/sig0000006e ),
.O(\i3/blk00000001/sig0000006b/CYSELF_10059 )
);
X_BUF #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/COUTUSED (
.I(\i3/blk00000001/sig0000006b/CYMUXFAST_10058 ),
.O(\i3/blk00000001/sig0000006b )
);
X_BUF #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/FASTCARRY (
.I(\i3/blk00000001/sig0000006f/CYMUXG_10025 ),
.O(\i3/blk00000001/sig0000006b/FASTCARRY_10056 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CYAND (
.I0(\i3/blk00000001/sig0000006b/CYSELG_10045 ),
.I1(\i3/blk00000001/sig0000006b/CYSELF_10059 ),
.O(\i3/blk00000001/sig0000006b/CYAND_10057 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CYMUXFAST (
.IA(\i3/blk00000001/sig0000006b/CYMUXG2_10055 ),
.IB(\i3/blk00000001/sig0000006b/FASTCARRY_10056 ),
.SEL(\i3/blk00000001/sig0000006b/CYAND_10057 ),
.O(\i3/blk00000001/sig0000006b/CYMUXFAST_10058 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CYMUXG2 (
.IA(\i3/blk00000001/sig0000006b/CY0G_10053 ),
.IB(\i3/blk00000001/sig0000006b/CYMUXF2_10054 ),
.SEL(\i3/blk00000001/sig0000006b/CYSELG_10045 ),
.O(\i3/blk00000001/sig0000006b/CYMUXG2_10055 )
);
X_BUF #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CY0G (
.I(\i3/blk00000001/sig000000fc ),
.O(\i3/blk00000001/sig0000006b/CY0G_10053 )
);
X_BUF #(
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/sig0000006b/CYSELG (
.I(\i3/blk00000001/sig0000006c ),
.O(\i3/blk00000001/sig0000006b/CYSELG_10045 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/blk00000148 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig000000fd ),
.ADR2(\i3/blk00000001/sig000000ed ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000006a )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/XUSED (
.I(\i3/blk00000001/sig000000d2/XORF_10106 ),
.O(\i3/blk00000001/sig000000d2 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/XORF (
.I0(\i3/blk00000001/sig000000d2/CYINIT_10105 ),
.I1(\i3/blk00000001/sig0000006a ),
.O(\i3/blk00000001/sig000000d2/XORF_10106 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYMUXF (
.IA(\i3/blk00000001/sig000000d2/CY0F_10104 ),
.IB(\i3/blk00000001/sig000000d2/CYINIT_10105 ),
.SEL(\i3/blk00000001/sig000000d2/CYSELF_10092 ),
.O(\i3/blk00000001/sig00000069 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYMUXF2 (
.IA(\i3/blk00000001/sig000000d2/CY0F_10104 ),
.IB(\i3/blk00000001/sig000000d2/CY0F_10104 ),
.SEL(\i3/blk00000001/sig000000d2/CYSELF_10092 ),
.O(\i3/blk00000001/sig000000d2/CYMUXF2_10087 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYINIT (
.I(\i3/blk00000001/sig0000006b ),
.O(\i3/blk00000001/sig000000d2/CYINIT_10105 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CY0F (
.I(\i3/blk00000001/sig000000fd ),
.O(\i3/blk00000001/sig000000d2/CY0F_10104 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYSELF (
.I(\i3/blk00000001/sig0000006a ),
.O(\i3/blk00000001/sig000000d2/CYSELF_10092 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/YUSED (
.I(\i3/blk00000001/sig000000d2/XORG_10094 ),
.O(\i3/blk00000001/sig000000d3 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/XORG (
.I0(\i3/blk00000001/sig00000069 ),
.I1(\i3/blk00000001/sig00000068 ),
.O(\i3/blk00000001/sig000000d2/XORG_10094 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/COUTUSED (
.I(\i3/blk00000001/sig000000d2/CYMUXFAST_10091 ),
.O(\i3/blk00000001/sig00000067 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/FASTCARRY (
.I(\i3/blk00000001/sig0000006b ),
.O(\i3/blk00000001/sig000000d2/FASTCARRY_10089 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYAND (
.I0(\i3/blk00000001/sig000000d2/CYSELG_10078 ),
.I1(\i3/blk00000001/sig000000d2/CYSELF_10092 ),
.O(\i3/blk00000001/sig000000d2/CYAND_10090 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYMUXFAST (
.IA(\i3/blk00000001/sig000000d2/CYMUXG2_10088 ),
.IB(\i3/blk00000001/sig000000d2/FASTCARRY_10089 ),
.SEL(\i3/blk00000001/sig000000d2/CYAND_10090 ),
.O(\i3/blk00000001/sig000000d2/CYMUXFAST_10091 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYMUXG2 (
.IA(\i3/blk00000001/sig000000d2/CY0G_10086 ),
.IB(\i3/blk00000001/sig000000d2/CYMUXF2_10087 ),
.SEL(\i3/blk00000001/sig000000d2/CYSELG_10078 ),
.O(\i3/blk00000001/sig000000d2/CYMUXG2_10088 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CY0G (
.I(\i3/blk00000001/sig000000fe ),
.O(\i3/blk00000001/sig000000d2/CY0G_10086 )
);
X_BUF #(
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/sig000000d2/CYSELG (
.I(\i3/blk00000001/sig00000068 ),
.O(\i3/blk00000001/sig000000d2/CYSELG_10078 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X25Y15" ))
\i3/blk00000001/blk00000145 (
.ADR0(\i3/blk00000001/sig000000fe ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig000000ee ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000068 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/blk00000142 (
.ADR0(\i3/blk00000001/sig000000ff ),
.ADR1(\i3/blk00000001/sig000000ef ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000066 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/XUSED (
.I(\i3/blk00000001/sig000000d4/XORF_10145 ),
.O(\i3/blk00000001/sig000000d4 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/XORF (
.I0(\i3/blk00000001/sig000000d4/CYINIT_10144 ),
.I1(\i3/blk00000001/sig00000066 ),
.O(\i3/blk00000001/sig000000d4/XORF_10145 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYMUXF (
.IA(\i3/blk00000001/sig000000d4/CY0F_10143 ),
.IB(\i3/blk00000001/sig000000d4/CYINIT_10144 ),
.SEL(\i3/blk00000001/sig000000d4/CYSELF_10131 ),
.O(\i3/blk00000001/sig00000065 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYMUXF2 (
.IA(\i3/blk00000001/sig000000d4/CY0F_10143 ),
.IB(\i3/blk00000001/sig000000d4/CY0F_10143 ),
.SEL(\i3/blk00000001/sig000000d4/CYSELF_10131 ),
.O(\i3/blk00000001/sig000000d4/CYMUXF2_10126 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYINIT (
.I(\i3/blk00000001/sig00000067 ),
.O(\i3/blk00000001/sig000000d4/CYINIT_10144 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CY0F (
.I(\i3/blk00000001/sig000000ff ),
.O(\i3/blk00000001/sig000000d4/CY0F_10143 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYSELF (
.I(\i3/blk00000001/sig00000066 ),
.O(\i3/blk00000001/sig000000d4/CYSELF_10131 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/YUSED (
.I(\i3/blk00000001/sig000000d4/XORG_10133 ),
.O(\i3/blk00000001/sig000000d5 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/XORG (
.I0(\i3/blk00000001/sig00000065 ),
.I1(\i3/blk00000001/sig00000064 ),
.O(\i3/blk00000001/sig000000d4/XORG_10133 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/COUTUSED (
.I(\i3/blk00000001/sig000000d4/CYMUXFAST_10130 ),
.O(\i3/blk00000001/sig00000063 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/FASTCARRY (
.I(\i3/blk00000001/sig00000067 ),
.O(\i3/blk00000001/sig000000d4/FASTCARRY_10128 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYAND (
.I0(\i3/blk00000001/sig000000d4/CYSELG_10117 ),
.I1(\i3/blk00000001/sig000000d4/CYSELF_10131 ),
.O(\i3/blk00000001/sig000000d4/CYAND_10129 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYMUXFAST (
.IA(\i3/blk00000001/sig000000d4/CYMUXG2_10127 ),
.IB(\i3/blk00000001/sig000000d4/FASTCARRY_10128 ),
.SEL(\i3/blk00000001/sig000000d4/CYAND_10129 ),
.O(\i3/blk00000001/sig000000d4/CYMUXFAST_10130 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYMUXG2 (
.IA(\i3/blk00000001/sig000000d4/CY0G_10125 ),
.IB(\i3/blk00000001/sig000000d4/CYMUXF2_10126 ),
.SEL(\i3/blk00000001/sig000000d4/CYSELG_10117 ),
.O(\i3/blk00000001/sig000000d4/CYMUXG2_10127 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CY0G (
.I(\i3/blk00000001/sig00000100 ),
.O(\i3/blk00000001/sig000000d4/CY0G_10125 )
);
X_BUF #(
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/sig000000d4/CYSELG (
.I(\i3/blk00000001/sig00000064 ),
.O(\i3/blk00000001/sig000000d4/CYSELG_10117 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y16" ))
\i3/blk00000001/blk0000013f (
.ADR0(\i3/blk00000001/sig000000f0 ),
.ADR1(\i3/blk00000001/sig00000100 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000064 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/blk0000013c (
.ADR0(\i3/blk00000001/sig000000f1 ),
.ADR1(\i3/blk00000001/sig00000101 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000062 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/XUSED (
.I(\i3/blk00000001/sig000000d6/XORF_10184 ),
.O(\i3/blk00000001/sig000000d6 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/XORF (
.I0(\i3/blk00000001/sig000000d6/CYINIT_10183 ),
.I1(\i3/blk00000001/sig00000062 ),
.O(\i3/blk00000001/sig000000d6/XORF_10184 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYMUXF (
.IA(\i3/blk00000001/sig000000d6/CY0F_10182 ),
.IB(\i3/blk00000001/sig000000d6/CYINIT_10183 ),
.SEL(\i3/blk00000001/sig000000d6/CYSELF_10170 ),
.O(\i3/blk00000001/sig00000061 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYMUXF2 (
.IA(\i3/blk00000001/sig000000d6/CY0F_10182 ),
.IB(\i3/blk00000001/sig000000d6/CY0F_10182 ),
.SEL(\i3/blk00000001/sig000000d6/CYSELF_10170 ),
.O(\i3/blk00000001/sig000000d6/CYMUXF2_10165 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYINIT (
.I(\i3/blk00000001/sig00000063 ),
.O(\i3/blk00000001/sig000000d6/CYINIT_10183 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CY0F (
.I(\i3/blk00000001/sig00000101 ),
.O(\i3/blk00000001/sig000000d6/CY0F_10182 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYSELF (
.I(\i3/blk00000001/sig00000062 ),
.O(\i3/blk00000001/sig000000d6/CYSELF_10170 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/YUSED (
.I(\i3/blk00000001/sig000000d6/XORG_10172 ),
.O(\i3/blk00000001/sig000000d7 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/XORG (
.I0(\i3/blk00000001/sig00000061 ),
.I1(\i3/blk00000001/sig00000060 ),
.O(\i3/blk00000001/sig000000d6/XORG_10172 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/COUTUSED (
.I(\i3/blk00000001/sig000000d6/CYMUXFAST_10169 ),
.O(\i3/blk00000001/sig0000005f )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/FASTCARRY (
.I(\i3/blk00000001/sig00000063 ),
.O(\i3/blk00000001/sig000000d6/FASTCARRY_10167 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYAND (
.I0(\i3/blk00000001/sig000000d6/CYSELG_10156 ),
.I1(\i3/blk00000001/sig000000d6/CYSELF_10170 ),
.O(\i3/blk00000001/sig000000d6/CYAND_10168 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYMUXFAST (
.IA(\i3/blk00000001/sig000000d6/CYMUXG2_10166 ),
.IB(\i3/blk00000001/sig000000d6/FASTCARRY_10167 ),
.SEL(\i3/blk00000001/sig000000d6/CYAND_10168 ),
.O(\i3/blk00000001/sig000000d6/CYMUXFAST_10169 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYMUXG2 (
.IA(\i3/blk00000001/sig000000d6/CY0G_10164 ),
.IB(\i3/blk00000001/sig000000d6/CYMUXF2_10165 ),
.SEL(\i3/blk00000001/sig000000d6/CYSELG_10156 ),
.O(\i3/blk00000001/sig000000d6/CYMUXG2_10166 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CY0G (
.I(\i3/blk00000001/sig00000102 ),
.O(\i3/blk00000001/sig000000d6/CY0G_10164 )
);
X_BUF #(
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/sig000000d6/CYSELG (
.I(\i3/blk00000001/sig00000060 ),
.O(\i3/blk00000001/sig000000d6/CYSELG_10156 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y17" ))
\i3/blk00000001/blk00000139 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig00000102 ),
.ADR2(\i3/blk00000001/sig000000f2 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000060 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/XUSED (
.I(\i3/blk00000001/sig000000d8/XORF_10223 ),
.O(\i3/blk00000001/sig000000d8 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/XORF (
.I0(\i3/blk00000001/sig000000d8/CYINIT_10222 ),
.I1(\i3/blk00000001/sig0000005e ),
.O(\i3/blk00000001/sig000000d8/XORF_10223 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYMUXF (
.IA(\i3/blk00000001/sig000000d8/CY0F_10221 ),
.IB(\i3/blk00000001/sig000000d8/CYINIT_10222 ),
.SEL(\i3/blk00000001/sig000000d8/CYSELF_10209 ),
.O(\i3/blk00000001/sig0000005d )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYMUXF2 (
.IA(\i3/blk00000001/sig000000d8/CY0F_10221 ),
.IB(\i3/blk00000001/sig000000d8/CY0F_10221 ),
.SEL(\i3/blk00000001/sig000000d8/CYSELF_10209 ),
.O(\i3/blk00000001/sig000000d8/CYMUXF2_10204 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYINIT (
.I(\i3/blk00000001/sig0000005f ),
.O(\i3/blk00000001/sig000000d8/CYINIT_10222 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CY0F (
.I(\i3/blk00000001/sig00000103 ),
.O(\i3/blk00000001/sig000000d8/CY0F_10221 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYSELF (
.I(\i3/blk00000001/sig0000005e ),
.O(\i3/blk00000001/sig000000d8/CYSELF_10209 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/YUSED (
.I(\i3/blk00000001/sig000000d8/XORG_10211 ),
.O(\i3/blk00000001/sig000000d9 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/XORG (
.I0(\i3/blk00000001/sig0000005d ),
.I1(\i3/blk00000001/sig0000005c ),
.O(\i3/blk00000001/sig000000d8/XORG_10211 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/COUTUSED (
.I(\i3/blk00000001/sig000000d8/CYMUXFAST_10208 ),
.O(\i3/blk00000001/sig0000005b )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/FASTCARRY (
.I(\i3/blk00000001/sig0000005f ),
.O(\i3/blk00000001/sig000000d8/FASTCARRY_10206 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYAND (
.I0(\i3/blk00000001/sig000000d8/CYSELG_10195 ),
.I1(\i3/blk00000001/sig000000d8/CYSELF_10209 ),
.O(\i3/blk00000001/sig000000d8/CYAND_10207 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYMUXFAST (
.IA(\i3/blk00000001/sig000000d8/CYMUXG2_10205 ),
.IB(\i3/blk00000001/sig000000d8/FASTCARRY_10206 ),
.SEL(\i3/blk00000001/sig000000d8/CYAND_10207 ),
.O(\i3/blk00000001/sig000000d8/CYMUXFAST_10208 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYMUXG2 (
.IA(\i3/blk00000001/sig000000d8/CY0G_10203 ),
.IB(\i3/blk00000001/sig000000d8/CYMUXF2_10204 ),
.SEL(\i3/blk00000001/sig000000d8/CYSELG_10195 ),
.O(\i3/blk00000001/sig000000d8/CYMUXG2_10205 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CY0G (
.I(\i3/blk00000001/sig00000104 ),
.O(\i3/blk00000001/sig000000d8/CY0G_10203 )
);
X_BUF #(
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/sig000000d8/CYSELG (
.I(\i3/blk00000001/sig0000005c ),
.O(\i3/blk00000001/sig000000d8/CYSELG_10195 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/XUSED (
.I(\i3/blk00000001/sig000000da/XORF_10262 ),
.O(\i3/blk00000001/sig000000da )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/XORF (
.I0(\i3/blk00000001/sig000000da/CYINIT_10261 ),
.I1(\i3/blk00000001/sig0000005a ),
.O(\i3/blk00000001/sig000000da/XORF_10262 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYMUXF (
.IA(\i3/blk00000001/sig000000da/CY0F_10260 ),
.IB(\i3/blk00000001/sig000000da/CYINIT_10261 ),
.SEL(\i3/blk00000001/sig000000da/CYSELF_10248 ),
.O(\i3/blk00000001/sig00000059 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYMUXF2 (
.IA(\i3/blk00000001/sig000000da/CY0F_10260 ),
.IB(\i3/blk00000001/sig000000da/CY0F_10260 ),
.SEL(\i3/blk00000001/sig000000da/CYSELF_10248 ),
.O(\i3/blk00000001/sig000000da/CYMUXF2_10243 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYINIT (
.I(\i3/blk00000001/sig0000005b ),
.O(\i3/blk00000001/sig000000da/CYINIT_10261 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CY0F (
.I(\i3/blk00000001/sig00000104 ),
.O(\i3/blk00000001/sig000000da/CY0F_10260 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYSELF (
.I(\i3/blk00000001/sig0000005a ),
.O(\i3/blk00000001/sig000000da/CYSELF_10248 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/YUSED (
.I(\i3/blk00000001/sig000000da/XORG_10250 ),
.O(\i3/blk00000001/sig000000db )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/XORG (
.I0(\i3/blk00000001/sig00000059 ),
.I1(\i3/blk00000001/sig00000058 ),
.O(\i3/blk00000001/sig000000da/XORG_10250 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/COUTUSED (
.I(\i3/blk00000001/sig000000da/CYMUXFAST_10247 ),
.O(\i3/blk00000001/sig00000057 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/FASTCARRY (
.I(\i3/blk00000001/sig0000005b ),
.O(\i3/blk00000001/sig000000da/FASTCARRY_10245 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYAND (
.I0(\i3/blk00000001/sig000000da/CYSELG_10234 ),
.I1(\i3/blk00000001/sig000000da/CYSELF_10248 ),
.O(\i3/blk00000001/sig000000da/CYAND_10246 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYMUXFAST (
.IA(\i3/blk00000001/sig000000da/CYMUXG2_10244 ),
.IB(\i3/blk00000001/sig000000da/FASTCARRY_10245 ),
.SEL(\i3/blk00000001/sig000000da/CYAND_10246 ),
.O(\i3/blk00000001/sig000000da/CYMUXFAST_10247 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYMUXG2 (
.IA(\i3/blk00000001/sig000000da/CY0G_10242 ),
.IB(\i3/blk00000001/sig000000da/CYMUXF2_10243 ),
.SEL(\i3/blk00000001/sig000000da/CYSELG_10234 ),
.O(\i3/blk00000001/sig000000da/CYMUXG2_10244 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CY0G (
.I(\i3/blk00000001/sig00000104 ),
.O(\i3/blk00000001/sig000000da/CY0G_10242 )
);
X_BUF #(
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/sig000000da/CYSELG (
.I(\i3/blk00000001/sig00000058 ),
.O(\i3/blk00000001/sig000000da/CYSELG_10234 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/blk00000130 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig00000104 ),
.ADR2(\i3/blk00000001/sig000000f5 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000005a )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/XUSED (
.I(\i3/blk00000001/sig000000dc/XORF_10301 ),
.O(\i3/blk00000001/sig000000dc )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/XORF (
.I0(\i3/blk00000001/sig000000dc/CYINIT_10300 ),
.I1(\i3/blk00000001/sig00000056 ),
.O(\i3/blk00000001/sig000000dc/XORF_10301 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYMUXF (
.IA(\i3/blk00000001/sig000000dc/CY0F_10299 ),
.IB(\i3/blk00000001/sig000000dc/CYINIT_10300 ),
.SEL(\i3/blk00000001/sig000000dc/CYSELF_10287 ),
.O(\i3/blk00000001/sig00000055 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYMUXF2 (
.IA(\i3/blk00000001/sig000000dc/CY0F_10299 ),
.IB(\i3/blk00000001/sig000000dc/CY0F_10299 ),
.SEL(\i3/blk00000001/sig000000dc/CYSELF_10287 ),
.O(\i3/blk00000001/sig000000dc/CYMUXF2_10282 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYINIT (
.I(\i3/blk00000001/sig00000057 ),
.O(\i3/blk00000001/sig000000dc/CYINIT_10300 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CY0F (
.I(\i3/blk00000001/sig00000104 ),
.O(\i3/blk00000001/sig000000dc/CY0F_10299 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYSELF (
.I(\i3/blk00000001/sig00000056 ),
.O(\i3/blk00000001/sig000000dc/CYSELF_10287 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/YUSED (
.I(\i3/blk00000001/sig000000dc/XORG_10289 ),
.O(\i3/blk00000001/sig000000dd )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/XORG (
.I0(\i3/blk00000001/sig00000055 ),
.I1(\i3/blk00000001/sig00000054 ),
.O(\i3/blk00000001/sig000000dc/XORG_10289 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/FASTCARRY (
.I(\i3/blk00000001/sig00000057 ),
.O(\i3/blk00000001/sig000000dc/FASTCARRY_10284 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYAND (
.I0(\i3/blk00000001/sig000000dc/CYSELG_10273 ),
.I1(\i3/blk00000001/sig000000dc/CYSELF_10287 ),
.O(\i3/blk00000001/sig000000dc/CYAND_10285 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYMUXFAST (
.IA(\i3/blk00000001/sig000000dc/CYMUXG2_10283 ),
.IB(\i3/blk00000001/sig000000dc/FASTCARRY_10284 ),
.SEL(\i3/blk00000001/sig000000dc/CYAND_10285 ),
.O(\i3/blk00000001/sig000000dc/CYMUXFAST_10286 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYMUXG2 (
.IA(\i3/blk00000001/sig000000dc/CY0G_10281 ),
.IB(\i3/blk00000001/sig000000dc/CYMUXF2_10282 ),
.SEL(\i3/blk00000001/sig000000dc/CYSELG_10273 ),
.O(\i3/blk00000001/sig000000dc/CYMUXG2_10283 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CY0G (
.I(\i3/blk00000001/sig00000104 ),
.O(\i3/blk00000001/sig000000dc/CY0G_10281 )
);
X_BUF #(
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/sig000000dc/CYSELG (
.I(\i3/blk00000001/sig00000054 ),
.O(\i3/blk00000001/sig000000dc/CYSELG_10273 )
);
X_BUF #(
.LOC ( "SLICE_X25Y21" ))
\i3/blk00000001/sig000000de/XUSED (
.I(\i3/blk00000001/sig000000de/XORF_10316 ),
.O(\i3/blk00000001/sig000000de )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y21" ))
\i3/blk00000001/sig000000de/XORF (
.I0(\i3/blk00000001/sig000000de/CYINIT_10315 ),
.I1(\i3/blk00000001/sig00000052 ),
.O(\i3/blk00000001/sig000000de/XORF_10316 )
);
X_BUF #(
.LOC ( "SLICE_X25Y21" ))
\i3/blk00000001/sig000000de/CYINIT (
.I(\i3/blk00000001/sig000000dc/CYMUXFAST_10286 ),
.O(\i3/blk00000001/sig000000de/CYINIT_10315 )
);
X_ONE #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/LOGIC_ONE (
.O(\i3/blk00000001/sig00000185/LOGIC_ONE_10333 )
);
X_BUF #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/XUSED (
.I(\i3/blk00000001/sig00000185/XORF_10349 ),
.O(\i3/blk00000001/sig00000185 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/XORF (
.I0(\i3/blk00000001/sig00000185/CYINIT_10348 ),
.I1(\i3/blk00000001/sig00000185/F ),
.O(\i3/blk00000001/sig00000185/XORF_10349 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/CYMUXF (
.IA(\NLW_i3/blk00000001/sig00000185/CYMUXF_IA_UNCONNECTED ),
.IB(\i3/blk00000001/sig00000185/CYINIT_10348 ),
.SEL(\i3/blk00000001/sig00000185/LOGIC_ONE_10333 ),
.O(\i3/blk00000001/sig000001d7 )
);
X_BUF #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/CYINIT (
.I(\i3/blk00000001/sig00000185/BXINV_10337 ),
.O(\i3/blk00000001/sig00000185/CYINIT_10348 )
);
X_BUF #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/BXINV (
.I(1'b1),
.O(\i3/blk00000001/sig00000185/BXINV_10337 )
);
X_BUF #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/YUSED (
.I(\i3/blk00000001/sig00000185/XORG_10335 ),
.O(\i3/blk00000001/sig00000184 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/XORG (
.I0(\i3/blk00000001/sig000001d7 ),
.I1(\i3/blk00000001/sig00000185/G ),
.O(\i3/blk00000001/sig00000185/XORG_10335 )
);
X_BUF #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/COUTUSED (
.I(\i3/blk00000001/sig00000185/CYMUXG_10334 ),
.O(\i3/blk00000001/sig000001d1 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/CYMUXG (
.IA(\NLW_i3/blk00000001/sig00000185/CYMUXG_IA_UNCONNECTED ),
.IB(\i3/blk00000001/sig000001d7 ),
.SEL(\i3/blk00000001/sig00000185/LOGIC_ONE_10333 ),
.O(\i3/blk00000001/sig00000185/CYMUXG_10334 )
);
X_ONE #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/LOGIC_ONE (
.O(\i3/blk00000001/sig00000179/LOGIC_ONE_10380 )
);
X_BUF #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/XUSED (
.I(\i3/blk00000001/sig00000179/XORF_10381 ),
.O(\i3/blk00000001/sig00000179 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/XORF (
.I0(\i3/blk00000001/sig00000179/CYINIT_10379 ),
.I1(\i3/blk00000001/sig00000179/F ),
.O(\i3/blk00000001/sig00000179/XORF_10381 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/CYMUXF (
.IA(\NLW_i3/blk00000001/sig00000179/CYMUXF_IA_UNCONNECTED ),
.IB(\i3/blk00000001/sig00000179/CYINIT_10379 ),
.SEL(\i3/blk00000001/sig00000179/LOGIC_ONE_10380 ),
.O(\i3/blk00000001/sig000001cb )
);
X_BUF #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/CYINIT (
.I(\i3/blk00000001/sig000001d1 ),
.O(\i3/blk00000001/sig00000179/CYINIT_10379 )
);
X_BUF #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/YUSED (
.I(\i3/blk00000001/sig00000179/XORG_10367 ),
.O(\i3/blk00000001/sig0000016e )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/XORG (
.I0(\i3/blk00000001/sig000001cb ),
.I1(\i3/blk00000001/sig00000179/G ),
.O(\i3/blk00000001/sig00000179/XORG_10367 )
);
X_BUF #(
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/COUTUSED (
.I(\i3/blk00000001/sig000001d1 ),
.O(\i3/blk00000001/sig000001c5 )
);
X_ONE #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/LOGIC_ONE (
.O(\i3/blk00000001/sig00000163/LOGIC_ONE_10412 )
);
X_BUF #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/XUSED (
.I(\i3/blk00000001/sig00000163/XORF_10413 ),
.O(\i3/blk00000001/sig00000163 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/XORF (
.I0(\i3/blk00000001/sig00000163/CYINIT_10411 ),
.I1(\i3/blk00000001/sig00000163/F ),
.O(\i3/blk00000001/sig00000163/XORF_10413 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/CYMUXF (
.IA(\NLW_i3/blk00000001/sig00000163/CYMUXF_IA_UNCONNECTED ),
.IB(\i3/blk00000001/sig00000163/CYINIT_10411 ),
.SEL(\i3/blk00000001/sig00000163/LOGIC_ONE_10412 ),
.O(\i3/blk00000001/sig000001bf )
);
X_BUF #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/CYINIT (
.I(\i3/blk00000001/sig000001c5 ),
.O(\i3/blk00000001/sig00000163/CYINIT_10411 )
);
X_BUF #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/YUSED (
.I(\i3/blk00000001/sig00000163/XORG_10399 ),
.O(\i3/blk00000001/sig00000158 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/XORG (
.I0(\i3/blk00000001/sig000001bf ),
.I1(\i3/blk00000001/sig00000163/G ),
.O(\i3/blk00000001/sig00000163/XORG_10399 )
);
X_BUF #(
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/COUTUSED (
.I(\i3/blk00000001/sig000001c5 ),
.O(\i3/blk00000001/sig000001b9 )
);
X_ONE #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/LOGIC_ONE (
.O(\i3/blk00000001/sig0000014d/LOGIC_ONE_10444 )
);
X_BUF #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/XUSED (
.I(\i3/blk00000001/sig0000014d/XORF_10445 ),
.O(\i3/blk00000001/sig0000014d )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/XORF (
.I0(\i3/blk00000001/sig0000014d/CYINIT_10443 ),
.I1(\i3/blk00000001/sig0000014d/F ),
.O(\i3/blk00000001/sig0000014d/XORF_10445 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/CYMUXF (
.IA(\NLW_i3/blk00000001/sig0000014d/CYMUXF_IA_UNCONNECTED ),
.IB(\i3/blk00000001/sig0000014d/CYINIT_10443 ),
.SEL(\i3/blk00000001/sig0000014d/LOGIC_ONE_10444 ),
.O(\i3/blk00000001/sig000001b3 )
);
X_BUF #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/CYINIT (
.I(\i3/blk00000001/sig000001b9 ),
.O(\i3/blk00000001/sig0000014d/CYINIT_10443 )
);
X_BUF #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/YUSED (
.I(\i3/blk00000001/sig0000014d/XORG_10431 ),
.O(\i3/blk00000001/sig00000142 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/XORG (
.I0(\i3/blk00000001/sig000001b3 ),
.I1(\i3/blk00000001/sig0000014d/G ),
.O(\i3/blk00000001/sig0000014d/XORG_10431 )
);
X_BUF #(
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/COUTUSED (
.I(\i3/blk00000001/sig000001b9 ),
.O(\i3/blk00000001/sig000001ad )
);
X_ONE #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/LOGIC_ONE (
.O(\i3/blk00000001/sig00000137/LOGIC_ONE_10476 )
);
X_BUF #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/XUSED (
.I(\i3/blk00000001/sig00000137/XORF_10477 ),
.O(\i3/blk00000001/sig00000137 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/XORF (
.I0(\i3/blk00000001/sig00000137/CYINIT_10475 ),
.I1(\i3/blk00000001/sig00000137/F ),
.O(\i3/blk00000001/sig00000137/XORF_10477 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/CYMUXF (
.IA(\NLW_i3/blk00000001/sig00000137/CYMUXF_IA_UNCONNECTED ),
.IB(\i3/blk00000001/sig00000137/CYINIT_10475 ),
.SEL(\i3/blk00000001/sig00000137/LOGIC_ONE_10476 ),
.O(\i3/blk00000001/sig000001a7 )
);
X_BUF #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/CYINIT (
.I(\i3/blk00000001/sig000001ad ),
.O(\i3/blk00000001/sig00000137/CYINIT_10475 )
);
X_BUF #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/YUSED (
.I(\i3/blk00000001/sig00000137/XORG_10463 ),
.O(\i3/blk00000001/sig0000012c )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/XORG (
.I0(\i3/blk00000001/sig000001a7 ),
.I1(\i3/blk00000001/sig00000137/G ),
.O(\i3/blk00000001/sig00000137/XORG_10463 )
);
X_BUF #(
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/COUTUSED (
.I(\i3/blk00000001/sig000001ad ),
.O(\i3/blk00000001/sig000001a1 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/XUSED (
.I(\i3/blk00000001/sig00000121/XORF_10518 ),
.O(\i3/blk00000001/sig00000121 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/XORF (
.I0(\i3/blk00000001/sig00000121/CYINIT_10517 ),
.I1(\i3/blk00000001/sig000000e1 ),
.O(\i3/blk00000001/sig00000121/XORF_10518 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYMUXF (
.IA(\i3/blk00000001/sig00000121/CY0F_10516 ),
.IB(\i3/blk00000001/sig00000121/CYINIT_10517 ),
.SEL(\i3/blk00000001/sig00000121/CYSELF_10503 ),
.O(\i3/blk00000001/sig0000019b )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYMUXF2 (
.IA(\i3/blk00000001/sig00000121/CY0F_10516 ),
.IB(\i3/blk00000001/sig00000121/CY0F_10516 ),
.SEL(\i3/blk00000001/sig00000121/CYSELF_10503 ),
.O(\i3/blk00000001/sig00000121/CYMUXF2_10498 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYINIT (
.I(\i3/blk00000001/sig000001a1 ),
.O(\i3/blk00000001/sig00000121/CYINIT_10517 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CY0F (
.I(\i3/blk00000001/sig000001ee ),
.O(\i3/blk00000001/sig00000121/CY0F_10516 )
);
X_AND2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000121/FAND/IN1 ),
.O(\i3/blk00000001/sig000001ee )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYSELF (
.I(\i3/blk00000001/sig000000e1 ),
.O(\i3/blk00000001/sig00000121/CYSELF_10503 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/YUSED (
.I(\i3/blk00000001/sig00000121/XORG_10505 ),
.O(\i3/blk00000001/sig00000116 )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/XORG (
.I0(\i3/blk00000001/sig0000019b ),
.I1(\i3/blk00000001/sig000000e0 ),
.O(\i3/blk00000001/sig00000121/XORG_10505 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/FASTCARRY (
.I(\i3/blk00000001/sig000001a1 ),
.O(\i3/blk00000001/sig00000121/FASTCARRY_10500 )
);
X_AND2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYAND (
.I0(\i3/blk00000001/sig00000121/CYSELG_10489 ),
.I1(\i3/blk00000001/sig00000121/CYSELF_10503 ),
.O(\i3/blk00000001/sig00000121/CYAND_10501 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYMUXFAST (
.IA(\i3/blk00000001/sig00000121/CYMUXG2_10499 ),
.IB(\i3/blk00000001/sig00000121/FASTCARRY_10500 ),
.SEL(\i3/blk00000001/sig00000121/CYAND_10501 ),
.O(\i3/blk00000001/sig00000121/CYMUXFAST_10502 )
);
X_MUX2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYMUXG2 (
.IA(\i3/blk00000001/sig00000121/CY0G_10497 ),
.IB(\i3/blk00000001/sig00000121/CYMUXF2_10498 ),
.SEL(\i3/blk00000001/sig00000121/CYSELG_10489 ),
.O(\i3/blk00000001/sig00000121/CYMUXG2_10499 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CY0G (
.I(\i3/blk00000001/sig000001e8 ),
.O(\i3/blk00000001/sig00000121/CY0G_10497 )
);
X_AND2 #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000121/GAND/IN1 ),
.O(\i3/blk00000001/sig000001e8 )
);
X_BUF #(
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/sig00000121/CYSELG (
.I(\i3/blk00000001/sig000000e0 ),
.O(\i3/blk00000001/sig00000121/CYSELG_10489 )
);
X_BUF #(
.LOC ( "SLICE_X30Y19" ))
\i3/blk00000001/sig0000010b/XUSED (
.I(\i3/blk00000001/sig0000010b/XORF_10533 ),
.O(\i3/blk00000001/sig0000010b )
);
X_XOR2 #(
.LOC ( "SLICE_X30Y19" ))
\i3/blk00000001/sig0000010b/XORF (
.I0(\i3/blk00000001/sig0000010b/CYINIT_10532 ),
.I1(\i3/blk00000001/sig0000023a ),
.O(\i3/blk00000001/sig0000010b/XORF_10533 )
);
X_BUF #(
.LOC ( "SLICE_X30Y19" ))
\i3/blk00000001/sig0000010b/CYINIT (
.I(\i3/blk00000001/sig00000121/CYMUXFAST_10502 ),
.O(\i3/blk00000001/sig0000010b/CYINIT_10532 )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/XUSED (
.I(\i3/blk00000001/sig000001da/XORF_10571 ),
.O(\i3/blk00000001/sig000001da )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/XORF (
.I0(\i3/blk00000001/sig000001da/CYINIT_10570 ),
.I1(\i3/blk00000001/sig000001da/F ),
.O(\i3/blk00000001/sig000001da/XORF_10571 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CYMUXF (
.IA(\i3/blk00000001/sig000001da/CY0F_10569 ),
.IB(\i3/blk00000001/sig000001da/CYINIT_10570 ),
.SEL(\i3/blk00000001/sig000001da/CYSELF_10560 ),
.O(\i3/blk00000001/sig000001db )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CYINIT (
.I(\i3/blk00000001/sig000001da/BXINV_10558 ),
.O(\i3/blk00000001/sig000001da/CYINIT_10570 )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CY0F (
.I(\i3/blk00000001/sig0000022c ),
.O(\i3/blk00000001/sig000001da/CY0F_10569 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig000001da/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig0000022c )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CYSELF (
.I(\i3/blk00000001/sig000001da/F ),
.O(\i3/blk00000001/sig000001da/CYSELF_10560 )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000001da/BXINV_10558 )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/YUSED (
.I(\i3/blk00000001/sig000001da/XORG_10556 ),
.O(\i3/blk00000001/sig00000188 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/XORG (
.I0(\i3/blk00000001/sig000001db ),
.I1(\i3/blk00000001/sig000001da/G ),
.O(\i3/blk00000001/sig000001da/XORG_10556 )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/COUTUSED (
.I(\i3/blk00000001/sig000001da/CYMUXG_10555 ),
.O(\i3/blk00000001/sig000001d9 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CYMUXG (
.IA(\i3/blk00000001/sig000001da/CY0G_10553 ),
.IB(\i3/blk00000001/sig000001db ),
.SEL(\i3/blk00000001/sig000001da/CYSELG_10544 ),
.O(\i3/blk00000001/sig000001da/CYMUXG_10555 )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CY0G (
.I(\i3/blk00000001/sig0000022b ),
.O(\i3/blk00000001/sig000001da/CY0G_10553 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig000001da/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig0000022b )
);
X_BUF #(
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/CYSELG (
.I(\i3/blk00000001/sig000001da/G ),
.O(\i3/blk00000001/sig000001da/CYSELG_10544 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/XUSED (
.I(\i3/blk00000001/sig00000186/XORF_10612 ),
.O(\i3/blk00000001/sig00000186 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/XORF (
.I0(\i3/blk00000001/sig00000186/CYINIT_10611 ),
.I1(\i3/blk00000001/sig00000186/F ),
.O(\i3/blk00000001/sig00000186/XORF_10612 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYMUXF (
.IA(\i3/blk00000001/sig00000186/CY0F_10610 ),
.IB(\i3/blk00000001/sig00000186/CYINIT_10611 ),
.SEL(\i3/blk00000001/sig00000186/CYSELF_10597 ),
.O(\i3/blk00000001/sig000001d2 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYMUXF2 (
.IA(\i3/blk00000001/sig00000186/CY0F_10610 ),
.IB(\i3/blk00000001/sig00000186/CY0F_10610 ),
.SEL(\i3/blk00000001/sig00000186/CYSELF_10597 ),
.O(\i3/blk00000001/sig00000186/CYMUXF2_10592 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYINIT (
.I(\i3/blk00000001/sig000001d9 ),
.O(\i3/blk00000001/sig00000186/CYINIT_10611 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CY0F (
.I(\i3/blk00000001/sig00000225 ),
.O(\i3/blk00000001/sig00000186/CY0F_10610 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000186/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000225 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYSELF (
.I(\i3/blk00000001/sig00000186/F ),
.O(\i3/blk00000001/sig00000186/CYSELF_10597 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/YUSED (
.I(\i3/blk00000001/sig00000186/XORG_10599 ),
.O(\i3/blk00000001/sig0000017a )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/XORG (
.I0(\i3/blk00000001/sig000001d2 ),
.I1(\i3/blk00000001/sig00000186/G ),
.O(\i3/blk00000001/sig00000186/XORG_10599 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/COUTUSED (
.I(\i3/blk00000001/sig00000186/CYMUXFAST_10596 ),
.O(\i3/blk00000001/sig000001cc )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/FASTCARRY (
.I(\i3/blk00000001/sig000001d9 ),
.O(\i3/blk00000001/sig00000186/FASTCARRY_10594 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYAND (
.I0(\i3/blk00000001/sig00000186/CYSELG_10582 ),
.I1(\i3/blk00000001/sig00000186/CYSELF_10597 ),
.O(\i3/blk00000001/sig00000186/CYAND_10595 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYMUXFAST (
.IA(\i3/blk00000001/sig00000186/CYMUXG2_10593 ),
.IB(\i3/blk00000001/sig00000186/FASTCARRY_10594 ),
.SEL(\i3/blk00000001/sig00000186/CYAND_10595 ),
.O(\i3/blk00000001/sig00000186/CYMUXFAST_10596 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYMUXG2 (
.IA(\i3/blk00000001/sig00000186/CY0G_10591 ),
.IB(\i3/blk00000001/sig00000186/CYMUXF2_10592 ),
.SEL(\i3/blk00000001/sig00000186/CYSELG_10582 ),
.O(\i3/blk00000001/sig00000186/CYMUXG2_10593 )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CY0G (
.I(\i3/blk00000001/sig0000021f ),
.O(\i3/blk00000001/sig00000186/CY0G_10591 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000186/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig0000021f )
);
X_BUF #(
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/CYSELG (
.I(\i3/blk00000001/sig00000186/G ),
.O(\i3/blk00000001/sig00000186/CYSELG_10582 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/XUSED (
.I(\i3/blk00000001/sig0000016f/XORF_10653 ),
.O(\i3/blk00000001/sig0000016f )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/XORF (
.I0(\i3/blk00000001/sig0000016f/CYINIT_10652 ),
.I1(\i3/blk00000001/sig0000016f/F ),
.O(\i3/blk00000001/sig0000016f/XORF_10653 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYMUXF (
.IA(\i3/blk00000001/sig0000016f/CY0F_10651 ),
.IB(\i3/blk00000001/sig0000016f/CYINIT_10652 ),
.SEL(\i3/blk00000001/sig0000016f/CYSELF_10638 ),
.O(\i3/blk00000001/sig000001c6 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYMUXF2 (
.IA(\i3/blk00000001/sig0000016f/CY0F_10651 ),
.IB(\i3/blk00000001/sig0000016f/CY0F_10651 ),
.SEL(\i3/blk00000001/sig0000016f/CYSELF_10638 ),
.O(\i3/blk00000001/sig0000016f/CYMUXF2_10633 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYINIT (
.I(\i3/blk00000001/sig000001cc ),
.O(\i3/blk00000001/sig0000016f/CYINIT_10652 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CY0F (
.I(\i3/blk00000001/sig00000219 ),
.O(\i3/blk00000001/sig0000016f/CY0F_10651 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig0000016f/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000219 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYSELF (
.I(\i3/blk00000001/sig0000016f/F ),
.O(\i3/blk00000001/sig0000016f/CYSELF_10638 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/YUSED (
.I(\i3/blk00000001/sig0000016f/XORG_10640 ),
.O(\i3/blk00000001/sig00000164 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/XORG (
.I0(\i3/blk00000001/sig000001c6 ),
.I1(\i3/blk00000001/sig0000016f/G ),
.O(\i3/blk00000001/sig0000016f/XORG_10640 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/COUTUSED (
.I(\i3/blk00000001/sig0000016f/CYMUXFAST_10637 ),
.O(\i3/blk00000001/sig000001c0 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/FASTCARRY (
.I(\i3/blk00000001/sig000001cc ),
.O(\i3/blk00000001/sig0000016f/FASTCARRY_10635 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYAND (
.I0(\i3/blk00000001/sig0000016f/CYSELG_10623 ),
.I1(\i3/blk00000001/sig0000016f/CYSELF_10638 ),
.O(\i3/blk00000001/sig0000016f/CYAND_10636 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYMUXFAST (
.IA(\i3/blk00000001/sig0000016f/CYMUXG2_10634 ),
.IB(\i3/blk00000001/sig0000016f/FASTCARRY_10635 ),
.SEL(\i3/blk00000001/sig0000016f/CYAND_10636 ),
.O(\i3/blk00000001/sig0000016f/CYMUXFAST_10637 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYMUXG2 (
.IA(\i3/blk00000001/sig0000016f/CY0G_10632 ),
.IB(\i3/blk00000001/sig0000016f/CYMUXF2_10633 ),
.SEL(\i3/blk00000001/sig0000016f/CYSELG_10623 ),
.O(\i3/blk00000001/sig0000016f/CYMUXG2_10634 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CY0G (
.I(\i3/blk00000001/sig00000213 ),
.O(\i3/blk00000001/sig0000016f/CY0G_10632 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig0000016f/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000213 )
);
X_BUF #(
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/CYSELG (
.I(\i3/blk00000001/sig0000016f/G ),
.O(\i3/blk00000001/sig0000016f/CYSELG_10623 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/XUSED (
.I(\i3/blk00000001/sig00000159/XORF_10694 ),
.O(\i3/blk00000001/sig00000159 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/XORF (
.I0(\i3/blk00000001/sig00000159/CYINIT_10693 ),
.I1(\i3/blk00000001/sig00000159/F ),
.O(\i3/blk00000001/sig00000159/XORF_10694 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYMUXF (
.IA(\i3/blk00000001/sig00000159/CY0F_10692 ),
.IB(\i3/blk00000001/sig00000159/CYINIT_10693 ),
.SEL(\i3/blk00000001/sig00000159/CYSELF_10679 ),
.O(\i3/blk00000001/sig000001ba )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYMUXF2 (
.IA(\i3/blk00000001/sig00000159/CY0F_10692 ),
.IB(\i3/blk00000001/sig00000159/CY0F_10692 ),
.SEL(\i3/blk00000001/sig00000159/CYSELF_10679 ),
.O(\i3/blk00000001/sig00000159/CYMUXF2_10674 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYINIT (
.I(\i3/blk00000001/sig000001c0 ),
.O(\i3/blk00000001/sig00000159/CYINIT_10693 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CY0F (
.I(\i3/blk00000001/sig0000020d ),
.O(\i3/blk00000001/sig00000159/CY0F_10692 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000159/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig0000020d )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYSELF (
.I(\i3/blk00000001/sig00000159/F ),
.O(\i3/blk00000001/sig00000159/CYSELF_10679 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/YUSED (
.I(\i3/blk00000001/sig00000159/XORG_10681 ),
.O(\i3/blk00000001/sig0000014e )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/XORG (
.I0(\i3/blk00000001/sig000001ba ),
.I1(\i3/blk00000001/sig00000159/G ),
.O(\i3/blk00000001/sig00000159/XORG_10681 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/COUTUSED (
.I(\i3/blk00000001/sig00000159/CYMUXFAST_10678 ),
.O(\i3/blk00000001/sig000001b4 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/FASTCARRY (
.I(\i3/blk00000001/sig000001c0 ),
.O(\i3/blk00000001/sig00000159/FASTCARRY_10676 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYAND (
.I0(\i3/blk00000001/sig00000159/CYSELG_10664 ),
.I1(\i3/blk00000001/sig00000159/CYSELF_10679 ),
.O(\i3/blk00000001/sig00000159/CYAND_10677 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYMUXFAST (
.IA(\i3/blk00000001/sig00000159/CYMUXG2_10675 ),
.IB(\i3/blk00000001/sig00000159/FASTCARRY_10676 ),
.SEL(\i3/blk00000001/sig00000159/CYAND_10677 ),
.O(\i3/blk00000001/sig00000159/CYMUXFAST_10678 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYMUXG2 (
.IA(\i3/blk00000001/sig00000159/CY0G_10673 ),
.IB(\i3/blk00000001/sig00000159/CYMUXF2_10674 ),
.SEL(\i3/blk00000001/sig00000159/CYSELG_10664 ),
.O(\i3/blk00000001/sig00000159/CYMUXG2_10675 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CY0G (
.I(\i3/blk00000001/sig00000207 ),
.O(\i3/blk00000001/sig00000159/CY0G_10673 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000159/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000207 )
);
X_BUF #(
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/CYSELG (
.I(\i3/blk00000001/sig00000159/G ),
.O(\i3/blk00000001/sig00000159/CYSELG_10664 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/XUSED (
.I(\i3/blk00000001/sig00000143/XORF_10735 ),
.O(\i3/blk00000001/sig00000143 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/XORF (
.I0(\i3/blk00000001/sig00000143/CYINIT_10734 ),
.I1(\i3/blk00000001/sig00000143/F ),
.O(\i3/blk00000001/sig00000143/XORF_10735 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYMUXF (
.IA(\i3/blk00000001/sig00000143/CY0F_10733 ),
.IB(\i3/blk00000001/sig00000143/CYINIT_10734 ),
.SEL(\i3/blk00000001/sig00000143/CYSELF_10720 ),
.O(\i3/blk00000001/sig000001ae )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYMUXF2 (
.IA(\i3/blk00000001/sig00000143/CY0F_10733 ),
.IB(\i3/blk00000001/sig00000143/CY0F_10733 ),
.SEL(\i3/blk00000001/sig00000143/CYSELF_10720 ),
.O(\i3/blk00000001/sig00000143/CYMUXF2_10715 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYINIT (
.I(\i3/blk00000001/sig000001b4 ),
.O(\i3/blk00000001/sig00000143/CYINIT_10734 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CY0F (
.I(\i3/blk00000001/sig00000201 ),
.O(\i3/blk00000001/sig00000143/CY0F_10733 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000143/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000201 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYSELF (
.I(\i3/blk00000001/sig00000143/F ),
.O(\i3/blk00000001/sig00000143/CYSELF_10720 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/YUSED (
.I(\i3/blk00000001/sig00000143/XORG_10722 ),
.O(\i3/blk00000001/sig00000138 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/XORG (
.I0(\i3/blk00000001/sig000001ae ),
.I1(\i3/blk00000001/sig00000143/G ),
.O(\i3/blk00000001/sig00000143/XORG_10722 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/COUTUSED (
.I(\i3/blk00000001/sig00000143/CYMUXFAST_10719 ),
.O(\i3/blk00000001/sig000001a8 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/FASTCARRY (
.I(\i3/blk00000001/sig000001b4 ),
.O(\i3/blk00000001/sig00000143/FASTCARRY_10717 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYAND (
.I0(\i3/blk00000001/sig00000143/CYSELG_10705 ),
.I1(\i3/blk00000001/sig00000143/CYSELF_10720 ),
.O(\i3/blk00000001/sig00000143/CYAND_10718 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYMUXFAST (
.IA(\i3/blk00000001/sig00000143/CYMUXG2_10716 ),
.IB(\i3/blk00000001/sig00000143/FASTCARRY_10717 ),
.SEL(\i3/blk00000001/sig00000143/CYAND_10718 ),
.O(\i3/blk00000001/sig00000143/CYMUXFAST_10719 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYMUXG2 (
.IA(\i3/blk00000001/sig00000143/CY0G_10714 ),
.IB(\i3/blk00000001/sig00000143/CYMUXF2_10715 ),
.SEL(\i3/blk00000001/sig00000143/CYSELG_10705 ),
.O(\i3/blk00000001/sig00000143/CYMUXG2_10716 )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CY0G (
.I(\i3/blk00000001/sig000001fb ),
.O(\i3/blk00000001/sig00000143/CY0G_10714 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000143/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig000001fb )
);
X_BUF #(
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/CYSELG (
.I(\i3/blk00000001/sig00000143/G ),
.O(\i3/blk00000001/sig00000143/CYSELG_10705 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/XUSED (
.I(\i3/blk00000001/sig0000012d/XORF_10776 ),
.O(\i3/blk00000001/sig0000012d )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/XORF (
.I0(\i3/blk00000001/sig0000012d/CYINIT_10775 ),
.I1(\i3/blk00000001/sig0000012d/F ),
.O(\i3/blk00000001/sig0000012d/XORF_10776 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYMUXF (
.IA(\i3/blk00000001/sig0000012d/CY0F_10774 ),
.IB(\i3/blk00000001/sig0000012d/CYINIT_10775 ),
.SEL(\i3/blk00000001/sig0000012d/CYSELF_10762 ),
.O(\i3/blk00000001/sig000001a2 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYMUXF2 (
.IA(\i3/blk00000001/sig0000012d/CY0F_10774 ),
.IB(\i3/blk00000001/sig0000012d/CY0F_10774 ),
.SEL(\i3/blk00000001/sig0000012d/CYSELF_10762 ),
.O(\i3/blk00000001/sig0000012d/CYMUXF2_10757 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYINIT (
.I(\i3/blk00000001/sig000001a8 ),
.O(\i3/blk00000001/sig0000012d/CYINIT_10775 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CY0F (
.I(\i3/blk00000001/sig000001f5 ),
.O(\i3/blk00000001/sig0000012d/CY0F_10774 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000012d/FAND/IN1 ),
.O(\i3/blk00000001/sig000001f5 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYSELF (
.I(\i3/blk00000001/sig0000012d/F ),
.O(\i3/blk00000001/sig0000012d/CYSELF_10762 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/YUSED (
.I(\i3/blk00000001/sig0000012d/XORG_10764 ),
.O(\i3/blk00000001/sig00000122 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/XORG (
.I0(\i3/blk00000001/sig000001a2 ),
.I1(\i3/blk00000001/sig00000118 ),
.O(\i3/blk00000001/sig0000012d/XORG_10764 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/FASTCARRY (
.I(\i3/blk00000001/sig000001a8 ),
.O(\i3/blk00000001/sig0000012d/FASTCARRY_10759 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYAND (
.I0(\i3/blk00000001/sig0000012d/CYSELG_10748 ),
.I1(\i3/blk00000001/sig0000012d/CYSELF_10762 ),
.O(\i3/blk00000001/sig0000012d/CYAND_10760 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYMUXFAST (
.IA(\i3/blk00000001/sig0000012d/CYMUXG2_10758 ),
.IB(\i3/blk00000001/sig0000012d/FASTCARRY_10759 ),
.SEL(\i3/blk00000001/sig0000012d/CYAND_10760 ),
.O(\i3/blk00000001/sig0000012d/CYMUXFAST_10761 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYMUXG2 (
.IA(\i3/blk00000001/sig0000012d/CY0G_10756 ),
.IB(\i3/blk00000001/sig0000012d/CYMUXF2_10757 ),
.SEL(\i3/blk00000001/sig0000012d/CYSELG_10748 ),
.O(\i3/blk00000001/sig0000012d/CYMUXG2_10758 )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CY0G (
.I(\i3/blk00000001/sig000001ef ),
.O(\i3/blk00000001/sig0000012d/CY0G_10756 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000012d/GAND/IN1 ),
.O(\i3/blk00000001/sig000001ef )
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/CYSELG (
.I(\i3/blk00000001/sig00000118 ),
.O(\i3/blk00000001/sig0000012d/CYSELG_10748 )
);
X_BUF #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/XUSED (
.I(\i3/blk00000001/sig00000117/XORF_10808 ),
.O(\i3/blk00000001/sig00000117 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/XORF (
.I0(\i3/blk00000001/sig00000117/CYINIT_10807 ),
.I1(\i3/blk00000001/sig0000010d ),
.O(\i3/blk00000001/sig00000117/XORF_10808 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/CYMUXF (
.IA(\i3/blk00000001/sig00000117/CY0F_10806 ),
.IB(\i3/blk00000001/sig00000117/CYINIT_10807 ),
.SEL(\i3/blk00000001/sig00000117/CYSELF_10798 ),
.O(\i3/blk00000001/sig00000196 )
);
X_BUF #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/CYINIT (
.I(\i3/blk00000001/sig0000012d/CYMUXFAST_10761 ),
.O(\i3/blk00000001/sig00000117/CYINIT_10807 )
);
X_BUF #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/CY0F (
.I(\i3/blk00000001/sig000001e9 ),
.O(\i3/blk00000001/sig00000117/CY0F_10806 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000117/FAND/IN1 ),
.O(\i3/blk00000001/sig000001e9 )
);
X_BUF #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/CYSELF (
.I(\i3/blk00000001/sig0000010d ),
.O(\i3/blk00000001/sig00000117/CYSELF_10798 )
);
X_BUF #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/YUSED (
.I(\i3/blk00000001/sig00000117/XORG_10795 ),
.O(\i3/blk00000001/sig0000010c )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/sig00000117/XORG (
.I0(\i3/blk00000001/sig00000196 ),
.I1(\i3/blk00000001/sig00000106 ),
.O(\i3/blk00000001/sig00000117/XORG_10795 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/XUSED (
.I(\i3/blk00000001/sig000001e3/XORF_10846 ),
.O(\i3/blk00000001/sig000001e3 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/XORF (
.I0(\i3/blk00000001/sig000001e3/CYINIT_10845 ),
.I1(\i3/blk00000001/sig000001e3/F ),
.O(\i3/blk00000001/sig000001e3/XORF_10846 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CYMUXF (
.IA(\i3/blk00000001/sig000001e3/CY0F_10844 ),
.IB(\i3/blk00000001/sig000001e3/CYINIT_10845 ),
.SEL(\i3/blk00000001/sig000001e3/CYSELF_10835 ),
.O(\i3/blk00000001/sig000001e4 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CYINIT (
.I(\i3/blk00000001/sig000001e3/BXINV_10833 ),
.O(\i3/blk00000001/sig000001e3/CYINIT_10845 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CY0F (
.I(\i3/blk00000001/sig00000235 ),
.O(\i3/blk00000001/sig000001e3/CY0F_10844 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig000001e3/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000235 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CYSELF (
.I(\i3/blk00000001/sig000001e3/F ),
.O(\i3/blk00000001/sig000001e3/CYSELF_10835 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000001e3/BXINV_10833 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/YUSED (
.I(\i3/blk00000001/sig000001e3/XORG_10831 ),
.O(\i3/blk00000001/sig00000191 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/XORG (
.I0(\i3/blk00000001/sig000001e4 ),
.I1(\i3/blk00000001/sig000001e3/G ),
.O(\i3/blk00000001/sig000001e3/XORG_10831 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/COUTUSED (
.I(\i3/blk00000001/sig000001e3/CYMUXG_10830 ),
.O(\i3/blk00000001/sig000001e2 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CYMUXG (
.IA(\i3/blk00000001/sig000001e3/CY0G_10828 ),
.IB(\i3/blk00000001/sig000001e4 ),
.SEL(\i3/blk00000001/sig000001e3/CYSELG_10819 ),
.O(\i3/blk00000001/sig000001e3/CYMUXG_10830 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CY0G (
.I(\i3/blk00000001/sig00000234 ),
.O(\i3/blk00000001/sig000001e3/CY0G_10828 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig000001e3/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000234 )
);
X_BUF #(
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/CYSELG (
.I(\i3/blk00000001/sig000001e3/G ),
.O(\i3/blk00000001/sig000001e3/CYSELG_10819 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/XUSED (
.I(\i3/blk00000001/sig0000018f/XORF_10887 ),
.O(\i3/blk00000001/sig0000018f )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/XORF (
.I0(\i3/blk00000001/sig0000018f/CYINIT_10886 ),
.I1(\i3/blk00000001/sig0000018f/F ),
.O(\i3/blk00000001/sig0000018f/XORF_10887 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYMUXF (
.IA(\i3/blk00000001/sig0000018f/CY0F_10885 ),
.IB(\i3/blk00000001/sig0000018f/CYINIT_10886 ),
.SEL(\i3/blk00000001/sig0000018f/CYSELF_10872 ),
.O(\i3/blk00000001/sig000001d5 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYMUXF2 (
.IA(\i3/blk00000001/sig0000018f/CY0F_10885 ),
.IB(\i3/blk00000001/sig0000018f/CY0F_10885 ),
.SEL(\i3/blk00000001/sig0000018f/CYSELF_10872 ),
.O(\i3/blk00000001/sig0000018f/CYMUXF2_10867 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYINIT (
.I(\i3/blk00000001/sig000001e2 ),
.O(\i3/blk00000001/sig0000018f/CYINIT_10886 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CY0F (
.I(\i3/blk00000001/sig00000228 ),
.O(\i3/blk00000001/sig0000018f/CY0F_10885 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000018f/FAND/IN1 ),
.O(\i3/blk00000001/sig00000228 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYSELF (
.I(\i3/blk00000001/sig0000018f/F ),
.O(\i3/blk00000001/sig0000018f/CYSELF_10872 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/YUSED (
.I(\i3/blk00000001/sig0000018f/XORG_10874 ),
.O(\i3/blk00000001/sig00000180 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/XORG (
.I0(\i3/blk00000001/sig000001d5 ),
.I1(\i3/blk00000001/sig0000018f/G ),
.O(\i3/blk00000001/sig0000018f/XORG_10874 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/COUTUSED (
.I(\i3/blk00000001/sig0000018f/CYMUXFAST_10871 ),
.O(\i3/blk00000001/sig000001cf )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/FASTCARRY (
.I(\i3/blk00000001/sig000001e2 ),
.O(\i3/blk00000001/sig0000018f/FASTCARRY_10869 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYAND (
.I0(\i3/blk00000001/sig0000018f/CYSELG_10857 ),
.I1(\i3/blk00000001/sig0000018f/CYSELF_10872 ),
.O(\i3/blk00000001/sig0000018f/CYAND_10870 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYMUXFAST (
.IA(\i3/blk00000001/sig0000018f/CYMUXG2_10868 ),
.IB(\i3/blk00000001/sig0000018f/FASTCARRY_10869 ),
.SEL(\i3/blk00000001/sig0000018f/CYAND_10870 ),
.O(\i3/blk00000001/sig0000018f/CYMUXFAST_10871 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYMUXG2 (
.IA(\i3/blk00000001/sig0000018f/CY0G_10866 ),
.IB(\i3/blk00000001/sig0000018f/CYMUXF2_10867 ),
.SEL(\i3/blk00000001/sig0000018f/CYSELG_10857 ),
.O(\i3/blk00000001/sig0000018f/CYMUXG2_10868 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CY0G (
.I(\i3/blk00000001/sig00000222 ),
.O(\i3/blk00000001/sig0000018f/CY0G_10866 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000018f/GAND/IN1 ),
.O(\i3/blk00000001/sig00000222 )
);
X_BUF #(
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/CYSELG (
.I(\i3/blk00000001/sig0000018f/G ),
.O(\i3/blk00000001/sig0000018f/CYSELG_10857 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/XUSED (
.I(\i3/blk00000001/sig00000175/XORF_10928 ),
.O(\i3/blk00000001/sig00000175 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/XORF (
.I0(\i3/blk00000001/sig00000175/CYINIT_10927 ),
.I1(\i3/blk00000001/sig00000175/F ),
.O(\i3/blk00000001/sig00000175/XORF_10928 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYMUXF (
.IA(\i3/blk00000001/sig00000175/CY0F_10926 ),
.IB(\i3/blk00000001/sig00000175/CYINIT_10927 ),
.SEL(\i3/blk00000001/sig00000175/CYSELF_10913 ),
.O(\i3/blk00000001/sig000001c9 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYMUXF2 (
.IA(\i3/blk00000001/sig00000175/CY0F_10926 ),
.IB(\i3/blk00000001/sig00000175/CY0F_10926 ),
.SEL(\i3/blk00000001/sig00000175/CYSELF_10913 ),
.O(\i3/blk00000001/sig00000175/CYMUXF2_10908 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYINIT (
.I(\i3/blk00000001/sig000001cf ),
.O(\i3/blk00000001/sig00000175/CYINIT_10927 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CY0F (
.I(\i3/blk00000001/sig0000021c ),
.O(\i3/blk00000001/sig00000175/CY0F_10926 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000175/FAND/IN1 ),
.O(\i3/blk00000001/sig0000021c )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYSELF (
.I(\i3/blk00000001/sig00000175/F ),
.O(\i3/blk00000001/sig00000175/CYSELF_10913 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/YUSED (
.I(\i3/blk00000001/sig00000175/XORG_10915 ),
.O(\i3/blk00000001/sig0000016a )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/XORG (
.I0(\i3/blk00000001/sig000001c9 ),
.I1(\i3/blk00000001/sig00000175/G ),
.O(\i3/blk00000001/sig00000175/XORG_10915 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/COUTUSED (
.I(\i3/blk00000001/sig00000175/CYMUXFAST_10912 ),
.O(\i3/blk00000001/sig000001c3 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/FASTCARRY (
.I(\i3/blk00000001/sig000001cf ),
.O(\i3/blk00000001/sig00000175/FASTCARRY_10910 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYAND (
.I0(\i3/blk00000001/sig00000175/CYSELG_10898 ),
.I1(\i3/blk00000001/sig00000175/CYSELF_10913 ),
.O(\i3/blk00000001/sig00000175/CYAND_10911 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYMUXFAST (
.IA(\i3/blk00000001/sig00000175/CYMUXG2_10909 ),
.IB(\i3/blk00000001/sig00000175/FASTCARRY_10910 ),
.SEL(\i3/blk00000001/sig00000175/CYAND_10911 ),
.O(\i3/blk00000001/sig00000175/CYMUXFAST_10912 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYMUXG2 (
.IA(\i3/blk00000001/sig00000175/CY0G_10907 ),
.IB(\i3/blk00000001/sig00000175/CYMUXF2_10908 ),
.SEL(\i3/blk00000001/sig00000175/CYSELG_10898 ),
.O(\i3/blk00000001/sig00000175/CYMUXG2_10909 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CY0G (
.I(\i3/blk00000001/sig00000216 ),
.O(\i3/blk00000001/sig00000175/CY0G_10907 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000175/GAND/IN1 ),
.O(\i3/blk00000001/sig00000216 )
);
X_BUF #(
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/CYSELG (
.I(\i3/blk00000001/sig00000175/G ),
.O(\i3/blk00000001/sig00000175/CYSELG_10898 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/XUSED (
.I(\i3/blk00000001/sig0000015f/XORF_10969 ),
.O(\i3/blk00000001/sig0000015f )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/XORF (
.I0(\i3/blk00000001/sig0000015f/CYINIT_10968 ),
.I1(\i3/blk00000001/sig0000015f/F ),
.O(\i3/blk00000001/sig0000015f/XORF_10969 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYMUXF (
.IA(\i3/blk00000001/sig0000015f/CY0F_10967 ),
.IB(\i3/blk00000001/sig0000015f/CYINIT_10968 ),
.SEL(\i3/blk00000001/sig0000015f/CYSELF_10954 ),
.O(\i3/blk00000001/sig000001bd )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYMUXF2 (
.IA(\i3/blk00000001/sig0000015f/CY0F_10967 ),
.IB(\i3/blk00000001/sig0000015f/CY0F_10967 ),
.SEL(\i3/blk00000001/sig0000015f/CYSELF_10954 ),
.O(\i3/blk00000001/sig0000015f/CYMUXF2_10949 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYINIT (
.I(\i3/blk00000001/sig000001c3 ),
.O(\i3/blk00000001/sig0000015f/CYINIT_10968 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CY0F (
.I(\i3/blk00000001/sig00000210 ),
.O(\i3/blk00000001/sig0000015f/CY0F_10967 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000015f/FAND/IN1 ),
.O(\i3/blk00000001/sig00000210 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYSELF (
.I(\i3/blk00000001/sig0000015f/F ),
.O(\i3/blk00000001/sig0000015f/CYSELF_10954 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/YUSED (
.I(\i3/blk00000001/sig0000015f/XORG_10956 ),
.O(\i3/blk00000001/sig00000154 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/XORG (
.I0(\i3/blk00000001/sig000001bd ),
.I1(\i3/blk00000001/sig0000015f/G ),
.O(\i3/blk00000001/sig0000015f/XORG_10956 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/COUTUSED (
.I(\i3/blk00000001/sig0000015f/CYMUXFAST_10953 ),
.O(\i3/blk00000001/sig000001b7 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/FASTCARRY (
.I(\i3/blk00000001/sig000001c3 ),
.O(\i3/blk00000001/sig0000015f/FASTCARRY_10951 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYAND (
.I0(\i3/blk00000001/sig0000015f/CYSELG_10939 ),
.I1(\i3/blk00000001/sig0000015f/CYSELF_10954 ),
.O(\i3/blk00000001/sig0000015f/CYAND_10952 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYMUXFAST (
.IA(\i3/blk00000001/sig0000015f/CYMUXG2_10950 ),
.IB(\i3/blk00000001/sig0000015f/FASTCARRY_10951 ),
.SEL(\i3/blk00000001/sig0000015f/CYAND_10952 ),
.O(\i3/blk00000001/sig0000015f/CYMUXFAST_10953 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYMUXG2 (
.IA(\i3/blk00000001/sig0000015f/CY0G_10948 ),
.IB(\i3/blk00000001/sig0000015f/CYMUXF2_10949 ),
.SEL(\i3/blk00000001/sig0000015f/CYSELG_10939 ),
.O(\i3/blk00000001/sig0000015f/CYMUXG2_10950 )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CY0G (
.I(\i3/blk00000001/sig0000020a ),
.O(\i3/blk00000001/sig0000015f/CY0G_10948 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000015f/GAND/IN1 ),
.O(\i3/blk00000001/sig0000020a )
);
X_BUF #(
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/CYSELG (
.I(\i3/blk00000001/sig0000015f/G ),
.O(\i3/blk00000001/sig0000015f/CYSELG_10939 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/XUSED (
.I(\i3/blk00000001/sig00000149/XORF_11010 ),
.O(\i3/blk00000001/sig00000149 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/XORF (
.I0(\i3/blk00000001/sig00000149/CYINIT_11009 ),
.I1(\i3/blk00000001/sig00000149/F ),
.O(\i3/blk00000001/sig00000149/XORF_11010 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYMUXF (
.IA(\i3/blk00000001/sig00000149/CY0F_11008 ),
.IB(\i3/blk00000001/sig00000149/CYINIT_11009 ),
.SEL(\i3/blk00000001/sig00000149/CYSELF_10995 ),
.O(\i3/blk00000001/sig000001b1 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYMUXF2 (
.IA(\i3/blk00000001/sig00000149/CY0F_11008 ),
.IB(\i3/blk00000001/sig00000149/CY0F_11008 ),
.SEL(\i3/blk00000001/sig00000149/CYSELF_10995 ),
.O(\i3/blk00000001/sig00000149/CYMUXF2_10990 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYINIT (
.I(\i3/blk00000001/sig000001b7 ),
.O(\i3/blk00000001/sig00000149/CYINIT_11009 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CY0F (
.I(\i3/blk00000001/sig00000204 ),
.O(\i3/blk00000001/sig00000149/CY0F_11008 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000149/FAND/IN1 ),
.O(\i3/blk00000001/sig00000204 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYSELF (
.I(\i3/blk00000001/sig00000149/F ),
.O(\i3/blk00000001/sig00000149/CYSELF_10995 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/YUSED (
.I(\i3/blk00000001/sig00000149/XORG_10997 ),
.O(\i3/blk00000001/sig0000013e )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/XORG (
.I0(\i3/blk00000001/sig000001b1 ),
.I1(\i3/blk00000001/sig00000149/G ),
.O(\i3/blk00000001/sig00000149/XORG_10997 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/COUTUSED (
.I(\i3/blk00000001/sig00000149/CYMUXFAST_10994 ),
.O(\i3/blk00000001/sig000001ab )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/FASTCARRY (
.I(\i3/blk00000001/sig000001b7 ),
.O(\i3/blk00000001/sig00000149/FASTCARRY_10992 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYAND (
.I0(\i3/blk00000001/sig00000149/CYSELG_10980 ),
.I1(\i3/blk00000001/sig00000149/CYSELF_10995 ),
.O(\i3/blk00000001/sig00000149/CYAND_10993 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYMUXFAST (
.IA(\i3/blk00000001/sig00000149/CYMUXG2_10991 ),
.IB(\i3/blk00000001/sig00000149/FASTCARRY_10992 ),
.SEL(\i3/blk00000001/sig00000149/CYAND_10993 ),
.O(\i3/blk00000001/sig00000149/CYMUXFAST_10994 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYMUXG2 (
.IA(\i3/blk00000001/sig00000149/CY0G_10989 ),
.IB(\i3/blk00000001/sig00000149/CYMUXF2_10990 ),
.SEL(\i3/blk00000001/sig00000149/CYSELG_10980 ),
.O(\i3/blk00000001/sig00000149/CYMUXG2_10991 )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CY0G (
.I(\i3/blk00000001/sig000001fe ),
.O(\i3/blk00000001/sig00000149/CY0G_10989 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000149/GAND/IN1 ),
.O(\i3/blk00000001/sig000001fe )
);
X_BUF #(
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/CYSELG (
.I(\i3/blk00000001/sig00000149/G ),
.O(\i3/blk00000001/sig00000149/CYSELG_10980 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/XUSED (
.I(\i3/blk00000001/sig00000133/XORF_11051 ),
.O(\i3/blk00000001/sig00000133 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/XORF (
.I0(\i3/blk00000001/sig00000133/CYINIT_11050 ),
.I1(\i3/blk00000001/sig00000133/F ),
.O(\i3/blk00000001/sig00000133/XORF_11051 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYMUXF (
.IA(\i3/blk00000001/sig00000133/CY0F_11049 ),
.IB(\i3/blk00000001/sig00000133/CYINIT_11050 ),
.SEL(\i3/blk00000001/sig00000133/CYSELF_11037 ),
.O(\i3/blk00000001/sig000001a5 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYMUXF2 (
.IA(\i3/blk00000001/sig00000133/CY0F_11049 ),
.IB(\i3/blk00000001/sig00000133/CY0F_11049 ),
.SEL(\i3/blk00000001/sig00000133/CYSELF_11037 ),
.O(\i3/blk00000001/sig00000133/CYMUXF2_11032 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYINIT (
.I(\i3/blk00000001/sig000001ab ),
.O(\i3/blk00000001/sig00000133/CYINIT_11050 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CY0F (
.I(\i3/blk00000001/sig000001f8 ),
.O(\i3/blk00000001/sig00000133/CY0F_11049 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000133/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig000001f8 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYSELF (
.I(\i3/blk00000001/sig00000133/F ),
.O(\i3/blk00000001/sig00000133/CYSELF_11037 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/YUSED (
.I(\i3/blk00000001/sig00000133/XORG_11039 ),
.O(\i3/blk00000001/sig00000128 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/XORG (
.I0(\i3/blk00000001/sig000001a5 ),
.I1(\i3/blk00000001/sig0000011e ),
.O(\i3/blk00000001/sig00000133/XORG_11039 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/FASTCARRY (
.I(\i3/blk00000001/sig000001ab ),
.O(\i3/blk00000001/sig00000133/FASTCARRY_11034 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYAND (
.I0(\i3/blk00000001/sig00000133/CYSELG_11023 ),
.I1(\i3/blk00000001/sig00000133/CYSELF_11037 ),
.O(\i3/blk00000001/sig00000133/CYAND_11035 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYMUXFAST (
.IA(\i3/blk00000001/sig00000133/CYMUXG2_11033 ),
.IB(\i3/blk00000001/sig00000133/FASTCARRY_11034 ),
.SEL(\i3/blk00000001/sig00000133/CYAND_11035 ),
.O(\i3/blk00000001/sig00000133/CYMUXFAST_11036 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYMUXG2 (
.IA(\i3/blk00000001/sig00000133/CY0G_11031 ),
.IB(\i3/blk00000001/sig00000133/CYMUXF2_11032 ),
.SEL(\i3/blk00000001/sig00000133/CYSELG_11023 ),
.O(\i3/blk00000001/sig00000133/CYMUXG2_11033 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CY0G (
.I(\i3/blk00000001/sig000001f2 ),
.O(\i3/blk00000001/sig00000133/CY0G_11031 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000133/GAND/IN1 ),
.O(\i3/blk00000001/sig000001f2 )
);
X_BUF #(
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/CYSELG (
.I(\i3/blk00000001/sig0000011e ),
.O(\i3/blk00000001/sig00000133/CYSELG_11023 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/blk0000020e (
.ADR0(x3_1_IBUF_3550),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x3_0_IBUF_3549),
.O(\i3/blk00000001/sig0000011e )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/blk0000020d (
.ADR0(x3_1_IBUF_3550),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x3_0_IBUF_3549),
.O(\i3/blk00000001/sig00000113 )
);
X_BUF #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/XUSED (
.I(\i3/blk00000001/sig0000011d/XORF_11083 ),
.O(\i3/blk00000001/sig0000011d )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/XORF (
.I0(\i3/blk00000001/sig0000011d/CYINIT_11082 ),
.I1(\i3/blk00000001/sig00000113 ),
.O(\i3/blk00000001/sig0000011d/XORF_11083 )
);
X_MUX2 #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/CYMUXF (
.IA(\i3/blk00000001/sig0000011d/CY0F_11081 ),
.IB(\i3/blk00000001/sig0000011d/CYINIT_11082 ),
.SEL(\i3/blk00000001/sig0000011d/CYSELF_11073 ),
.O(\i3/blk00000001/sig00000199 )
);
X_BUF #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/CYINIT (
.I(\i3/blk00000001/sig00000133/CYMUXFAST_11036 ),
.O(\i3/blk00000001/sig0000011d/CYINIT_11082 )
);
X_BUF #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/CY0F (
.I(\i3/blk00000001/sig000001ec ),
.O(\i3/blk00000001/sig0000011d/CY0F_11081 )
);
X_AND2 #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000011d/FAND/IN1 ),
.O(\i3/blk00000001/sig000001ec )
);
X_BUF #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/CYSELF (
.I(\i3/blk00000001/sig00000113 ),
.O(\i3/blk00000001/sig0000011d/CYSELF_11073 )
);
X_BUF #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/YUSED (
.I(\i3/blk00000001/sig0000011d/XORG_11070 ),
.O(\i3/blk00000001/sig00000112 )
);
X_XOR2 #(
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/sig0000011d/XORG (
.I0(\i3/blk00000001/sig00000199 ),
.I1(\i3/blk00000001/sig00000109 ),
.O(\i3/blk00000001/sig0000011d/XORG_11070 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X28Y15" ))
\i3/blk00000001/blk0000020c (
.ADR0(x3_1_IBUF_3550),
.ADR1(x3_0_IBUF_3549),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000109 )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/XUSED (
.I(\i3/blk00000001/sig000001dd/XORF_11121 ),
.O(\i3/blk00000001/sig000001dd )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/XORF (
.I0(\i3/blk00000001/sig000001dd/CYINIT_11120 ),
.I1(\i3/blk00000001/sig000001dd/F ),
.O(\i3/blk00000001/sig000001dd/XORF_11121 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CYMUXF (
.IA(\i3/blk00000001/sig000001dd/CY0F_11119 ),
.IB(\i3/blk00000001/sig000001dd/CYINIT_11120 ),
.SEL(\i3/blk00000001/sig000001dd/CYSELF_11110 ),
.O(\i3/blk00000001/sig000001de )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CYINIT (
.I(\i3/blk00000001/sig000001dd/BXINV_11108 ),
.O(\i3/blk00000001/sig000001dd/CYINIT_11120 )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CY0F (
.I(\i3/blk00000001/sig0000022f ),
.O(\i3/blk00000001/sig000001dd/CY0F_11119 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig000001dd/FAND/IN1 ),
.O(\i3/blk00000001/sig0000022f )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CYSELF (
.I(\i3/blk00000001/sig000001dd/F ),
.O(\i3/blk00000001/sig000001dd/CYSELF_11110 )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000001dd/BXINV_11108 )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/YUSED (
.I(\i3/blk00000001/sig000001dd/XORG_11106 ),
.O(\i3/blk00000001/sig0000018b )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/XORG (
.I0(\i3/blk00000001/sig000001de ),
.I1(\i3/blk00000001/sig000001dd/G ),
.O(\i3/blk00000001/sig000001dd/XORG_11106 )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/COUTUSED (
.I(\i3/blk00000001/sig000001dd/CYMUXG_11105 ),
.O(\i3/blk00000001/sig000001dc )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CYMUXG (
.IA(\i3/blk00000001/sig000001dd/CY0G_11103 ),
.IB(\i3/blk00000001/sig000001de ),
.SEL(\i3/blk00000001/sig000001dd/CYSELG_11094 ),
.O(\i3/blk00000001/sig000001dd/CYMUXG_11105 )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CY0G (
.I(\i3/blk00000001/sig0000022e ),
.O(\i3/blk00000001/sig000001dd/CY0G_11103 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig000001dd/GAND/IN1 ),
.O(\i3/blk00000001/sig0000022e )
);
X_BUF #(
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/CYSELG (
.I(\i3/blk00000001/sig000001dd/G ),
.O(\i3/blk00000001/sig000001dd/CYSELG_11094 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/XUSED (
.I(\i3/blk00000001/sig00000189/XORF_11162 ),
.O(\i3/blk00000001/sig00000189 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/XORF (
.I0(\i3/blk00000001/sig00000189/CYINIT_11161 ),
.I1(\i3/blk00000001/sig00000189/F ),
.O(\i3/blk00000001/sig00000189/XORF_11162 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYMUXF (
.IA(\i3/blk00000001/sig00000189/CY0F_11160 ),
.IB(\i3/blk00000001/sig00000189/CYINIT_11161 ),
.SEL(\i3/blk00000001/sig00000189/CYSELF_11147 ),
.O(\i3/blk00000001/sig000001d3 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYMUXF2 (
.IA(\i3/blk00000001/sig00000189/CY0F_11160 ),
.IB(\i3/blk00000001/sig00000189/CY0F_11160 ),
.SEL(\i3/blk00000001/sig00000189/CYSELF_11147 ),
.O(\i3/blk00000001/sig00000189/CYMUXF2_11142 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYINIT (
.I(\i3/blk00000001/sig000001dc ),
.O(\i3/blk00000001/sig00000189/CYINIT_11161 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CY0F (
.I(\i3/blk00000001/sig00000226 ),
.O(\i3/blk00000001/sig00000189/CY0F_11160 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000189/FAND/IN1 ),
.O(\i3/blk00000001/sig00000226 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYSELF (
.I(\i3/blk00000001/sig00000189/F ),
.O(\i3/blk00000001/sig00000189/CYSELF_11147 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/YUSED (
.I(\i3/blk00000001/sig00000189/XORG_11149 ),
.O(\i3/blk00000001/sig0000017c )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/XORG (
.I0(\i3/blk00000001/sig000001d3 ),
.I1(\i3/blk00000001/sig00000189/G ),
.O(\i3/blk00000001/sig00000189/XORG_11149 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/COUTUSED (
.I(\i3/blk00000001/sig00000189/CYMUXFAST_11146 ),
.O(\i3/blk00000001/sig000001cd )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/FASTCARRY (
.I(\i3/blk00000001/sig000001dc ),
.O(\i3/blk00000001/sig00000189/FASTCARRY_11144 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYAND (
.I0(\i3/blk00000001/sig00000189/CYSELG_11132 ),
.I1(\i3/blk00000001/sig00000189/CYSELF_11147 ),
.O(\i3/blk00000001/sig00000189/CYAND_11145 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYMUXFAST (
.IA(\i3/blk00000001/sig00000189/CYMUXG2_11143 ),
.IB(\i3/blk00000001/sig00000189/FASTCARRY_11144 ),
.SEL(\i3/blk00000001/sig00000189/CYAND_11145 ),
.O(\i3/blk00000001/sig00000189/CYMUXFAST_11146 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYMUXG2 (
.IA(\i3/blk00000001/sig00000189/CY0G_11141 ),
.IB(\i3/blk00000001/sig00000189/CYMUXF2_11142 ),
.SEL(\i3/blk00000001/sig00000189/CYSELG_11132 ),
.O(\i3/blk00000001/sig00000189/CYMUXG2_11143 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CY0G (
.I(\i3/blk00000001/sig00000220 ),
.O(\i3/blk00000001/sig00000189/CY0G_11141 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000189/GAND/IN1 ),
.O(\i3/blk00000001/sig00000220 )
);
X_BUF #(
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/CYSELG (
.I(\i3/blk00000001/sig00000189/G ),
.O(\i3/blk00000001/sig00000189/CYSELG_11132 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/XUSED (
.I(\i3/blk00000001/sig00000171/XORF_11203 ),
.O(\i3/blk00000001/sig00000171 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/XORF (
.I0(\i3/blk00000001/sig00000171/CYINIT_11202 ),
.I1(\i3/blk00000001/sig00000171/F ),
.O(\i3/blk00000001/sig00000171/XORF_11203 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYMUXF (
.IA(\i3/blk00000001/sig00000171/CY0F_11201 ),
.IB(\i3/blk00000001/sig00000171/CYINIT_11202 ),
.SEL(\i3/blk00000001/sig00000171/CYSELF_11188 ),
.O(\i3/blk00000001/sig000001c7 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYMUXF2 (
.IA(\i3/blk00000001/sig00000171/CY0F_11201 ),
.IB(\i3/blk00000001/sig00000171/CY0F_11201 ),
.SEL(\i3/blk00000001/sig00000171/CYSELF_11188 ),
.O(\i3/blk00000001/sig00000171/CYMUXF2_11183 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYINIT (
.I(\i3/blk00000001/sig000001cd ),
.O(\i3/blk00000001/sig00000171/CYINIT_11202 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CY0F (
.I(\i3/blk00000001/sig0000021a ),
.O(\i3/blk00000001/sig00000171/CY0F_11201 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000171/FAND/IN1 ),
.O(\i3/blk00000001/sig0000021a )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYSELF (
.I(\i3/blk00000001/sig00000171/F ),
.O(\i3/blk00000001/sig00000171/CYSELF_11188 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/YUSED (
.I(\i3/blk00000001/sig00000171/XORG_11190 ),
.O(\i3/blk00000001/sig00000166 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/XORG (
.I0(\i3/blk00000001/sig000001c7 ),
.I1(\i3/blk00000001/sig00000171/G ),
.O(\i3/blk00000001/sig00000171/XORG_11190 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/COUTUSED (
.I(\i3/blk00000001/sig00000171/CYMUXFAST_11187 ),
.O(\i3/blk00000001/sig000001c1 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/FASTCARRY (
.I(\i3/blk00000001/sig000001cd ),
.O(\i3/blk00000001/sig00000171/FASTCARRY_11185 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYAND (
.I0(\i3/blk00000001/sig00000171/CYSELG_11173 ),
.I1(\i3/blk00000001/sig00000171/CYSELF_11188 ),
.O(\i3/blk00000001/sig00000171/CYAND_11186 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYMUXFAST (
.IA(\i3/blk00000001/sig00000171/CYMUXG2_11184 ),
.IB(\i3/blk00000001/sig00000171/FASTCARRY_11185 ),
.SEL(\i3/blk00000001/sig00000171/CYAND_11186 ),
.O(\i3/blk00000001/sig00000171/CYMUXFAST_11187 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYMUXG2 (
.IA(\i3/blk00000001/sig00000171/CY0G_11182 ),
.IB(\i3/blk00000001/sig00000171/CYMUXF2_11183 ),
.SEL(\i3/blk00000001/sig00000171/CYSELG_11173 ),
.O(\i3/blk00000001/sig00000171/CYMUXG2_11184 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CY0G (
.I(\i3/blk00000001/sig00000214 ),
.O(\i3/blk00000001/sig00000171/CY0G_11182 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000171/GAND/IN1 ),
.O(\i3/blk00000001/sig00000214 )
);
X_BUF #(
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/CYSELG (
.I(\i3/blk00000001/sig00000171/G ),
.O(\i3/blk00000001/sig00000171/CYSELG_11173 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/XUSED (
.I(\i3/blk00000001/sig0000015b/XORF_11244 ),
.O(\i3/blk00000001/sig0000015b )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/XORF (
.I0(\i3/blk00000001/sig0000015b/CYINIT_11243 ),
.I1(\i3/blk00000001/sig0000015b/F ),
.O(\i3/blk00000001/sig0000015b/XORF_11244 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYMUXF (
.IA(\i3/blk00000001/sig0000015b/CY0F_11242 ),
.IB(\i3/blk00000001/sig0000015b/CYINIT_11243 ),
.SEL(\i3/blk00000001/sig0000015b/CYSELF_11229 ),
.O(\i3/blk00000001/sig000001bb )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYMUXF2 (
.IA(\i3/blk00000001/sig0000015b/CY0F_11242 ),
.IB(\i3/blk00000001/sig0000015b/CY0F_11242 ),
.SEL(\i3/blk00000001/sig0000015b/CYSELF_11229 ),
.O(\i3/blk00000001/sig0000015b/CYMUXF2_11224 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYINIT (
.I(\i3/blk00000001/sig000001c1 ),
.O(\i3/blk00000001/sig0000015b/CYINIT_11243 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CY0F (
.I(\i3/blk00000001/sig0000020e ),
.O(\i3/blk00000001/sig0000015b/CY0F_11242 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig0000015b/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig0000020e )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYSELF (
.I(\i3/blk00000001/sig0000015b/F ),
.O(\i3/blk00000001/sig0000015b/CYSELF_11229 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/YUSED (
.I(\i3/blk00000001/sig0000015b/XORG_11231 ),
.O(\i3/blk00000001/sig00000150 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/XORG (
.I0(\i3/blk00000001/sig000001bb ),
.I1(\i3/blk00000001/sig0000015b/G ),
.O(\i3/blk00000001/sig0000015b/XORG_11231 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/COUTUSED (
.I(\i3/blk00000001/sig0000015b/CYMUXFAST_11228 ),
.O(\i3/blk00000001/sig000001b5 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/FASTCARRY (
.I(\i3/blk00000001/sig000001c1 ),
.O(\i3/blk00000001/sig0000015b/FASTCARRY_11226 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYAND (
.I0(\i3/blk00000001/sig0000015b/CYSELG_11214 ),
.I1(\i3/blk00000001/sig0000015b/CYSELF_11229 ),
.O(\i3/blk00000001/sig0000015b/CYAND_11227 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYMUXFAST (
.IA(\i3/blk00000001/sig0000015b/CYMUXG2_11225 ),
.IB(\i3/blk00000001/sig0000015b/FASTCARRY_11226 ),
.SEL(\i3/blk00000001/sig0000015b/CYAND_11227 ),
.O(\i3/blk00000001/sig0000015b/CYMUXFAST_11228 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYMUXG2 (
.IA(\i3/blk00000001/sig0000015b/CY0G_11223 ),
.IB(\i3/blk00000001/sig0000015b/CYMUXF2_11224 ),
.SEL(\i3/blk00000001/sig0000015b/CYSELG_11214 ),
.O(\i3/blk00000001/sig0000015b/CYMUXG2_11225 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CY0G (
.I(\i3/blk00000001/sig00000208 ),
.O(\i3/blk00000001/sig0000015b/CY0G_11223 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig0000015b/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000208 )
);
X_BUF #(
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/CYSELG (
.I(\i3/blk00000001/sig0000015b/G ),
.O(\i3/blk00000001/sig0000015b/CYSELG_11214 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/XUSED (
.I(\i3/blk00000001/sig00000145/XORF_11285 ),
.O(\i3/blk00000001/sig00000145 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/XORF (
.I0(\i3/blk00000001/sig00000145/CYINIT_11284 ),
.I1(\i3/blk00000001/sig00000145/F ),
.O(\i3/blk00000001/sig00000145/XORF_11285 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYMUXF (
.IA(\i3/blk00000001/sig00000145/CY0F_11283 ),
.IB(\i3/blk00000001/sig00000145/CYINIT_11284 ),
.SEL(\i3/blk00000001/sig00000145/CYSELF_11270 ),
.O(\i3/blk00000001/sig000001af )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYMUXF2 (
.IA(\i3/blk00000001/sig00000145/CY0F_11283 ),
.IB(\i3/blk00000001/sig00000145/CY0F_11283 ),
.SEL(\i3/blk00000001/sig00000145/CYSELF_11270 ),
.O(\i3/blk00000001/sig00000145/CYMUXF2_11265 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYINIT (
.I(\i3/blk00000001/sig000001b5 ),
.O(\i3/blk00000001/sig00000145/CYINIT_11284 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CY0F (
.I(\i3/blk00000001/sig00000202 ),
.O(\i3/blk00000001/sig00000145/CY0F_11283 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/FAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000145/FAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig00000202 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYSELF (
.I(\i3/blk00000001/sig00000145/F ),
.O(\i3/blk00000001/sig00000145/CYSELF_11270 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/YUSED (
.I(\i3/blk00000001/sig00000145/XORG_11272 ),
.O(\i3/blk00000001/sig0000013a )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/XORG (
.I0(\i3/blk00000001/sig000001af ),
.I1(\i3/blk00000001/sig00000145/G ),
.O(\i3/blk00000001/sig00000145/XORG_11272 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/COUTUSED (
.I(\i3/blk00000001/sig00000145/CYMUXFAST_11269 ),
.O(\i3/blk00000001/sig000001a9 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/FASTCARRY (
.I(\i3/blk00000001/sig000001b5 ),
.O(\i3/blk00000001/sig00000145/FASTCARRY_11267 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYAND (
.I0(\i3/blk00000001/sig00000145/CYSELG_11255 ),
.I1(\i3/blk00000001/sig00000145/CYSELF_11270 ),
.O(\i3/blk00000001/sig00000145/CYAND_11268 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYMUXFAST (
.IA(\i3/blk00000001/sig00000145/CYMUXG2_11266 ),
.IB(\i3/blk00000001/sig00000145/FASTCARRY_11267 ),
.SEL(\i3/blk00000001/sig00000145/CYAND_11268 ),
.O(\i3/blk00000001/sig00000145/CYMUXFAST_11269 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYMUXG2 (
.IA(\i3/blk00000001/sig00000145/CY0G_11264 ),
.IB(\i3/blk00000001/sig00000145/CYMUXF2_11265 ),
.SEL(\i3/blk00000001/sig00000145/CYSELG_11255 ),
.O(\i3/blk00000001/sig00000145/CYMUXG2_11266 )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CY0G (
.I(\i3/blk00000001/sig000001fc ),
.O(\i3/blk00000001/sig00000145/CY0G_11264 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/GAND (
.I0(\NlwBufferSignal_i3/blk00000001/sig00000145/GAND/IN0 ),
.I1(1'b0),
.O(\i3/blk00000001/sig000001fc )
);
X_BUF #(
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/CYSELG (
.I(\i3/blk00000001/sig00000145/G ),
.O(\i3/blk00000001/sig00000145/CYSELG_11255 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/XUSED (
.I(\i3/blk00000001/sig0000012f/XORF_11326 ),
.O(\i3/blk00000001/sig0000012f )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/XORF (
.I0(\i3/blk00000001/sig0000012f/CYINIT_11325 ),
.I1(\i3/blk00000001/sig0000012f/F ),
.O(\i3/blk00000001/sig0000012f/XORF_11326 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYMUXF (
.IA(\i3/blk00000001/sig0000012f/CY0F_11324 ),
.IB(\i3/blk00000001/sig0000012f/CYINIT_11325 ),
.SEL(\i3/blk00000001/sig0000012f/CYSELF_11312 ),
.O(\i3/blk00000001/sig000001a3 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYMUXF2 (
.IA(\i3/blk00000001/sig0000012f/CY0F_11324 ),
.IB(\i3/blk00000001/sig0000012f/CY0F_11324 ),
.SEL(\i3/blk00000001/sig0000012f/CYSELF_11312 ),
.O(\i3/blk00000001/sig0000012f/CYMUXF2_11307 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYINIT (
.I(\i3/blk00000001/sig000001a9 ),
.O(\i3/blk00000001/sig0000012f/CYINIT_11325 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CY0F (
.I(\i3/blk00000001/sig000001f6 ),
.O(\i3/blk00000001/sig0000012f/CY0F_11324 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000012f/FAND/IN1 ),
.O(\i3/blk00000001/sig000001f6 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYSELF (
.I(\i3/blk00000001/sig0000012f/F ),
.O(\i3/blk00000001/sig0000012f/CYSELF_11312 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/YUSED (
.I(\i3/blk00000001/sig0000012f/XORG_11314 ),
.O(\i3/blk00000001/sig00000124 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/XORG (
.I0(\i3/blk00000001/sig000001a3 ),
.I1(\i3/blk00000001/sig0000011a ),
.O(\i3/blk00000001/sig0000012f/XORG_11314 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/FASTCARRY (
.I(\i3/blk00000001/sig000001a9 ),
.O(\i3/blk00000001/sig0000012f/FASTCARRY_11309 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYAND (
.I0(\i3/blk00000001/sig0000012f/CYSELG_11298 ),
.I1(\i3/blk00000001/sig0000012f/CYSELF_11312 ),
.O(\i3/blk00000001/sig0000012f/CYAND_11310 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYMUXFAST (
.IA(\i3/blk00000001/sig0000012f/CYMUXG2_11308 ),
.IB(\i3/blk00000001/sig0000012f/FASTCARRY_11309 ),
.SEL(\i3/blk00000001/sig0000012f/CYAND_11310 ),
.O(\i3/blk00000001/sig0000012f/CYMUXFAST_11311 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYMUXG2 (
.IA(\i3/blk00000001/sig0000012f/CY0G_11306 ),
.IB(\i3/blk00000001/sig0000012f/CYMUXF2_11307 ),
.SEL(\i3/blk00000001/sig0000012f/CYSELG_11298 ),
.O(\i3/blk00000001/sig0000012f/CYMUXG2_11308 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CY0G (
.I(\i3/blk00000001/sig000001f0 ),
.O(\i3/blk00000001/sig0000012f/CY0G_11306 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000012f/GAND/IN1 ),
.O(\i3/blk00000001/sig000001f0 )
);
X_BUF #(
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/CYSELG (
.I(\i3/blk00000001/sig0000011a ),
.O(\i3/blk00000001/sig0000012f/CYSELG_11298 )
);
X_BUF #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/XUSED (
.I(\i3/blk00000001/sig00000119/XORF_11358 ),
.O(\i3/blk00000001/sig00000119 )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/XORF (
.I0(\i3/blk00000001/sig00000119/CYINIT_11357 ),
.I1(\i3/blk00000001/sig0000010f ),
.O(\i3/blk00000001/sig00000119/XORF_11358 )
);
X_MUX2 #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/CYMUXF (
.IA(\i3/blk00000001/sig00000119/CY0F_11356 ),
.IB(\i3/blk00000001/sig00000119/CYINIT_11357 ),
.SEL(\i3/blk00000001/sig00000119/CYSELF_11348 ),
.O(\i3/blk00000001/sig00000197 )
);
X_BUF #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/CYINIT (
.I(\i3/blk00000001/sig0000012f/CYMUXFAST_11311 ),
.O(\i3/blk00000001/sig00000119/CYINIT_11357 )
);
X_BUF #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/CY0F (
.I(\i3/blk00000001/sig000001ea ),
.O(\i3/blk00000001/sig00000119/CY0F_11356 )
);
X_AND2 #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000119/FAND/IN1 ),
.O(\i3/blk00000001/sig000001ea )
);
X_BUF #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/CYSELF (
.I(\i3/blk00000001/sig0000010f ),
.O(\i3/blk00000001/sig00000119/CYSELF_11348 )
);
X_BUF #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/YUSED (
.I(\i3/blk00000001/sig00000119/XORG_11345 ),
.O(\i3/blk00000001/sig0000010e )
);
X_XOR2 #(
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/sig00000119/XORG (
.I0(\i3/blk00000001/sig00000197 ),
.I1(\i3/blk00000001/sig00000107 ),
.O(\i3/blk00000001/sig00000119/XORG_11345 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CYMUXF (
.IA(\i3/blk00000001/sig000001e5/CY0F_11390 ),
.IB(\i3/blk00000001/sig000001e5/CYINIT_11391 ),
.SEL(\i3/blk00000001/sig000001e5/CYSELF_11381 ),
.O(\i3/blk00000001/sig000001e6 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CYINIT (
.I(\i3/blk00000001/sig000001e5/BXINV_11379 ),
.O(\i3/blk00000001/sig000001e5/CYINIT_11391 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CY0F (
.I(\i3/blk00000001/sig00000238 ),
.O(\i3/blk00000001/sig000001e5/CY0F_11390 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000238 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CYSELF (
.I(\i3/blk00000001/sig000001e5/F ),
.O(\i3/blk00000001/sig000001e5/CYSELF_11381 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000001e5/BXINV_11379 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/COUTUSED (
.I(\i3/blk00000001/sig000001e5/CYMUXG_11378 ),
.O(\i3/blk00000001/sig000001e5 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CYMUXG (
.IA(\i3/blk00000001/sig000001e5/CY0G_11376 ),
.IB(\i3/blk00000001/sig000001e6 ),
.SEL(\i3/blk00000001/sig000001e5/CYSELG_11367 ),
.O(\i3/blk00000001/sig000001e5/CYMUXG_11378 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CY0G (
.I(\i3/blk00000001/sig00000237 ),
.O(\i3/blk00000001/sig000001e5/CY0G_11376 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000237 )
);
X_BUF #(
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/CYSELG (
.I(\i3/blk00000001/sig000001e5/G ),
.O(\i3/blk00000001/sig000001e5/CYSELG_11367 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/XUSED (
.I(\i3/blk00000001/sig00000192/XORF_11431 ),
.O(\i3/blk00000001/sig00000192 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/XORF (
.I0(\i3/blk00000001/sig00000192/CYINIT_11430 ),
.I1(\i3/blk00000001/sig00000192/F ),
.O(\i3/blk00000001/sig00000192/XORF_11431 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYMUXF (
.IA(\i3/blk00000001/sig00000192/CY0F_11429 ),
.IB(\i3/blk00000001/sig00000192/CYINIT_11430 ),
.SEL(\i3/blk00000001/sig00000192/CYSELF_11416 ),
.O(\i3/blk00000001/sig000001d6 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYMUXF2 (
.IA(\i3/blk00000001/sig00000192/CY0F_11429 ),
.IB(\i3/blk00000001/sig00000192/CY0F_11429 ),
.SEL(\i3/blk00000001/sig00000192/CYSELF_11416 ),
.O(\i3/blk00000001/sig00000192/CYMUXF2_11411 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYINIT (
.I(\i3/blk00000001/sig000001e5 ),
.O(\i3/blk00000001/sig00000192/CYINIT_11430 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CY0F (
.I(\i3/blk00000001/sig00000229 ),
.O(\i3/blk00000001/sig00000192/CY0F_11429 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000229 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYSELF (
.I(\i3/blk00000001/sig00000192/F ),
.O(\i3/blk00000001/sig00000192/CYSELF_11416 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/YUSED (
.I(\i3/blk00000001/sig00000192/XORG_11418 ),
.O(\i3/blk00000001/sig00000182 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/XORG (
.I0(\i3/blk00000001/sig000001d6 ),
.I1(\i3/blk00000001/sig00000192/G ),
.O(\i3/blk00000001/sig00000192/XORG_11418 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/COUTUSED (
.I(\i3/blk00000001/sig00000192/CYMUXFAST_11415 ),
.O(\i3/blk00000001/sig000001d0 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/FASTCARRY (
.I(\i3/blk00000001/sig000001e5 ),
.O(\i3/blk00000001/sig00000192/FASTCARRY_11413 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYAND (
.I0(\i3/blk00000001/sig00000192/CYSELG_11401 ),
.I1(\i3/blk00000001/sig00000192/CYSELF_11416 ),
.O(\i3/blk00000001/sig00000192/CYAND_11414 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYMUXFAST (
.IA(\i3/blk00000001/sig00000192/CYMUXG2_11412 ),
.IB(\i3/blk00000001/sig00000192/FASTCARRY_11413 ),
.SEL(\i3/blk00000001/sig00000192/CYAND_11414 ),
.O(\i3/blk00000001/sig00000192/CYMUXFAST_11415 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYMUXG2 (
.IA(\i3/blk00000001/sig00000192/CY0G_11410 ),
.IB(\i3/blk00000001/sig00000192/CYMUXF2_11411 ),
.SEL(\i3/blk00000001/sig00000192/CYSELG_11401 ),
.O(\i3/blk00000001/sig00000192/CYMUXG2_11412 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CY0G (
.I(\i3/blk00000001/sig00000223 ),
.O(\i3/blk00000001/sig00000192/CY0G_11410 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000223 )
);
X_BUF #(
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/CYSELG (
.I(\i3/blk00000001/sig00000192/G ),
.O(\i3/blk00000001/sig00000192/CYSELG_11401 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/XUSED (
.I(\i3/blk00000001/sig00000177/XORF_11472 ),
.O(\i3/blk00000001/sig00000177 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/XORF (
.I0(\i3/blk00000001/sig00000177/CYINIT_11471 ),
.I1(\i3/blk00000001/sig00000177/F ),
.O(\i3/blk00000001/sig00000177/XORF_11472 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYMUXF (
.IA(\i3/blk00000001/sig00000177/CY0F_11470 ),
.IB(\i3/blk00000001/sig00000177/CYINIT_11471 ),
.SEL(\i3/blk00000001/sig00000177/CYSELF_11457 ),
.O(\i3/blk00000001/sig000001ca )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYMUXF2 (
.IA(\i3/blk00000001/sig00000177/CY0F_11470 ),
.IB(\i3/blk00000001/sig00000177/CY0F_11470 ),
.SEL(\i3/blk00000001/sig00000177/CYSELF_11457 ),
.O(\i3/blk00000001/sig00000177/CYMUXF2_11452 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYINIT (
.I(\i3/blk00000001/sig000001d0 ),
.O(\i3/blk00000001/sig00000177/CYINIT_11471 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CY0F (
.I(\i3/blk00000001/sig0000021d ),
.O(\i3/blk00000001/sig00000177/CY0F_11470 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig0000021d )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYSELF (
.I(\i3/blk00000001/sig00000177/F ),
.O(\i3/blk00000001/sig00000177/CYSELF_11457 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/YUSED (
.I(\i3/blk00000001/sig00000177/XORG_11459 ),
.O(\i3/blk00000001/sig0000016c )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/XORG (
.I0(\i3/blk00000001/sig000001ca ),
.I1(\i3/blk00000001/sig00000177/G ),
.O(\i3/blk00000001/sig00000177/XORG_11459 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/COUTUSED (
.I(\i3/blk00000001/sig00000177/CYMUXFAST_11456 ),
.O(\i3/blk00000001/sig000001c4 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/FASTCARRY (
.I(\i3/blk00000001/sig000001d0 ),
.O(\i3/blk00000001/sig00000177/FASTCARRY_11454 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYAND (
.I0(\i3/blk00000001/sig00000177/CYSELG_11442 ),
.I1(\i3/blk00000001/sig00000177/CYSELF_11457 ),
.O(\i3/blk00000001/sig00000177/CYAND_11455 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYMUXFAST (
.IA(\i3/blk00000001/sig00000177/CYMUXG2_11453 ),
.IB(\i3/blk00000001/sig00000177/FASTCARRY_11454 ),
.SEL(\i3/blk00000001/sig00000177/CYAND_11455 ),
.O(\i3/blk00000001/sig00000177/CYMUXFAST_11456 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYMUXG2 (
.IA(\i3/blk00000001/sig00000177/CY0G_11451 ),
.IB(\i3/blk00000001/sig00000177/CYMUXF2_11452 ),
.SEL(\i3/blk00000001/sig00000177/CYSELG_11442 ),
.O(\i3/blk00000001/sig00000177/CYMUXG2_11453 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CY0G (
.I(\i3/blk00000001/sig00000217 ),
.O(\i3/blk00000001/sig00000177/CY0G_11451 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000217 )
);
X_BUF #(
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/CYSELG (
.I(\i3/blk00000001/sig00000177/G ),
.O(\i3/blk00000001/sig00000177/CYSELG_11442 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/XUSED (
.I(\i3/blk00000001/sig00000161/XORF_11513 ),
.O(\i3/blk00000001/sig00000161 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/XORF (
.I0(\i3/blk00000001/sig00000161/CYINIT_11512 ),
.I1(\i3/blk00000001/sig00000161/F ),
.O(\i3/blk00000001/sig00000161/XORF_11513 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYMUXF (
.IA(\i3/blk00000001/sig00000161/CY0F_11511 ),
.IB(\i3/blk00000001/sig00000161/CYINIT_11512 ),
.SEL(\i3/blk00000001/sig00000161/CYSELF_11498 ),
.O(\i3/blk00000001/sig000001be )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYMUXF2 (
.IA(\i3/blk00000001/sig00000161/CY0F_11511 ),
.IB(\i3/blk00000001/sig00000161/CY0F_11511 ),
.SEL(\i3/blk00000001/sig00000161/CYSELF_11498 ),
.O(\i3/blk00000001/sig00000161/CYMUXF2_11493 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYINIT (
.I(\i3/blk00000001/sig000001c4 ),
.O(\i3/blk00000001/sig00000161/CYINIT_11512 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CY0F (
.I(\i3/blk00000001/sig00000211 ),
.O(\i3/blk00000001/sig00000161/CY0F_11511 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000211 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYSELF (
.I(\i3/blk00000001/sig00000161/F ),
.O(\i3/blk00000001/sig00000161/CYSELF_11498 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/YUSED (
.I(\i3/blk00000001/sig00000161/XORG_11500 ),
.O(\i3/blk00000001/sig00000156 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/XORG (
.I0(\i3/blk00000001/sig000001be ),
.I1(\i3/blk00000001/sig00000161/G ),
.O(\i3/blk00000001/sig00000161/XORG_11500 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/COUTUSED (
.I(\i3/blk00000001/sig00000161/CYMUXFAST_11497 ),
.O(\i3/blk00000001/sig000001b8 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/FASTCARRY (
.I(\i3/blk00000001/sig000001c4 ),
.O(\i3/blk00000001/sig00000161/FASTCARRY_11495 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYAND (
.I0(\i3/blk00000001/sig00000161/CYSELG_11483 ),
.I1(\i3/blk00000001/sig00000161/CYSELF_11498 ),
.O(\i3/blk00000001/sig00000161/CYAND_11496 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYMUXFAST (
.IA(\i3/blk00000001/sig00000161/CYMUXG2_11494 ),
.IB(\i3/blk00000001/sig00000161/FASTCARRY_11495 ),
.SEL(\i3/blk00000001/sig00000161/CYAND_11496 ),
.O(\i3/blk00000001/sig00000161/CYMUXFAST_11497 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYMUXG2 (
.IA(\i3/blk00000001/sig00000161/CY0G_11492 ),
.IB(\i3/blk00000001/sig00000161/CYMUXF2_11493 ),
.SEL(\i3/blk00000001/sig00000161/CYSELG_11483 ),
.O(\i3/blk00000001/sig00000161/CYMUXG2_11494 )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CY0G (
.I(\i3/blk00000001/sig0000020b ),
.O(\i3/blk00000001/sig00000161/CY0G_11492 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig0000020b )
);
X_BUF #(
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/CYSELG (
.I(\i3/blk00000001/sig00000161/G ),
.O(\i3/blk00000001/sig00000161/CYSELG_11483 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/XUSED (
.I(\i3/blk00000001/sig0000014b/XORF_11554 ),
.O(\i3/blk00000001/sig0000014b )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/XORF (
.I0(\i3/blk00000001/sig0000014b/CYINIT_11553 ),
.I1(\i3/blk00000001/sig0000014b/F ),
.O(\i3/blk00000001/sig0000014b/XORF_11554 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYMUXF (
.IA(\i3/blk00000001/sig0000014b/CY0F_11552 ),
.IB(\i3/blk00000001/sig0000014b/CYINIT_11553 ),
.SEL(\i3/blk00000001/sig0000014b/CYSELF_11539 ),
.O(\i3/blk00000001/sig000001b2 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYMUXF2 (
.IA(\i3/blk00000001/sig0000014b/CY0F_11552 ),
.IB(\i3/blk00000001/sig0000014b/CY0F_11552 ),
.SEL(\i3/blk00000001/sig0000014b/CYSELF_11539 ),
.O(\i3/blk00000001/sig0000014b/CYMUXF2_11534 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYINIT (
.I(\i3/blk00000001/sig000001b8 ),
.O(\i3/blk00000001/sig0000014b/CYINIT_11553 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CY0F (
.I(\i3/blk00000001/sig00000205 ),
.O(\i3/blk00000001/sig0000014b/CY0F_11552 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig00000205 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYSELF (
.I(\i3/blk00000001/sig0000014b/F ),
.O(\i3/blk00000001/sig0000014b/CYSELF_11539 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/YUSED (
.I(\i3/blk00000001/sig0000014b/XORG_11541 ),
.O(\i3/blk00000001/sig00000140 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/XORG (
.I0(\i3/blk00000001/sig000001b2 ),
.I1(\i3/blk00000001/sig0000014b/G ),
.O(\i3/blk00000001/sig0000014b/XORG_11541 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/COUTUSED (
.I(\i3/blk00000001/sig0000014b/CYMUXFAST_11538 ),
.O(\i3/blk00000001/sig000001ac )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/FASTCARRY (
.I(\i3/blk00000001/sig000001b8 ),
.O(\i3/blk00000001/sig0000014b/FASTCARRY_11536 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYAND (
.I0(\i3/blk00000001/sig0000014b/CYSELG_11524 ),
.I1(\i3/blk00000001/sig0000014b/CYSELF_11539 ),
.O(\i3/blk00000001/sig0000014b/CYAND_11537 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYMUXFAST (
.IA(\i3/blk00000001/sig0000014b/CYMUXG2_11535 ),
.IB(\i3/blk00000001/sig0000014b/FASTCARRY_11536 ),
.SEL(\i3/blk00000001/sig0000014b/CYAND_11537 ),
.O(\i3/blk00000001/sig0000014b/CYMUXFAST_11538 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYMUXG2 (
.IA(\i3/blk00000001/sig0000014b/CY0G_11533 ),
.IB(\i3/blk00000001/sig0000014b/CYMUXF2_11534 ),
.SEL(\i3/blk00000001/sig0000014b/CYSELG_11524 ),
.O(\i3/blk00000001/sig0000014b/CYMUXG2_11535 )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CY0G (
.I(\i3/blk00000001/sig000001ff ),
.O(\i3/blk00000001/sig0000014b/CY0G_11533 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/GAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig000001ff )
);
X_BUF #(
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/CYSELG (
.I(\i3/blk00000001/sig0000014b/G ),
.O(\i3/blk00000001/sig0000014b/CYSELG_11524 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/XUSED (
.I(\i3/blk00000001/sig00000135/XORF_11595 ),
.O(\i3/blk00000001/sig00000135 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/XORF (
.I0(\i3/blk00000001/sig00000135/CYINIT_11594 ),
.I1(\i3/blk00000001/sig00000135/F ),
.O(\i3/blk00000001/sig00000135/XORF_11595 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYMUXF (
.IA(\i3/blk00000001/sig00000135/CY0F_11593 ),
.IB(\i3/blk00000001/sig00000135/CYINIT_11594 ),
.SEL(\i3/blk00000001/sig00000135/CYSELF_11580 ),
.O(\i3/blk00000001/sig000001a6 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYMUXF2 (
.IA(\i3/blk00000001/sig00000135/CY0F_11593 ),
.IB(\i3/blk00000001/sig00000135/CY0F_11593 ),
.SEL(\i3/blk00000001/sig00000135/CYSELF_11580 ),
.O(\i3/blk00000001/sig00000135/CYMUXF2_11575 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYINIT (
.I(\i3/blk00000001/sig000001ac ),
.O(\i3/blk00000001/sig00000135/CYINIT_11594 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CY0F (
.I(\i3/blk00000001/sig000001f9 ),
.O(\i3/blk00000001/sig00000135/CY0F_11593 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/FAND (
.I0(1'b0),
.I1(1'b0),
.O(\i3/blk00000001/sig000001f9 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYSELF (
.I(\i3/blk00000001/sig00000135/F ),
.O(\i3/blk00000001/sig00000135/CYSELF_11580 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/YUSED (
.I(\i3/blk00000001/sig00000135/XORG_11582 ),
.O(\i3/blk00000001/sig0000012a )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/XORG (
.I0(\i3/blk00000001/sig000001a6 ),
.I1(\i3/blk00000001/sig00000135/G ),
.O(\i3/blk00000001/sig00000135/XORG_11582 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/FASTCARRY (
.I(\i3/blk00000001/sig000001ac ),
.O(\i3/blk00000001/sig00000135/FASTCARRY_11577 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYAND (
.I0(\i3/blk00000001/sig00000135/CYSELG_11565 ),
.I1(\i3/blk00000001/sig00000135/CYSELF_11580 ),
.O(\i3/blk00000001/sig00000135/CYAND_11578 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYMUXFAST (
.IA(\i3/blk00000001/sig00000135/CYMUXG2_11576 ),
.IB(\i3/blk00000001/sig00000135/FASTCARRY_11577 ),
.SEL(\i3/blk00000001/sig00000135/CYAND_11578 ),
.O(\i3/blk00000001/sig00000135/CYMUXFAST_11579 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYMUXG2 (
.IA(\i3/blk00000001/sig00000135/CY0G_11574 ),
.IB(\i3/blk00000001/sig00000135/CYMUXF2_11575 ),
.SEL(\i3/blk00000001/sig00000135/CYSELG_11565 ),
.O(\i3/blk00000001/sig00000135/CYMUXG2_11576 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CY0G (
.I(\i3/blk00000001/sig000001f3 ),
.O(\i3/blk00000001/sig00000135/CY0G_11574 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/GAND (
.I0(1'b1),
.I1(1'b0),
.O(\i3/blk00000001/sig000001f3 )
);
X_BUF #(
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/CYSELG (
.I(\i3/blk00000001/sig00000135/G ),
.O(\i3/blk00000001/sig00000135/CYSELG_11565 )
);
X_BUF #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/XUSED (
.I(\i3/blk00000001/sig0000011f/XORF_11627 ),
.O(\i3/blk00000001/sig0000011f )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/XORF (
.I0(\i3/blk00000001/sig0000011f/CYINIT_11626 ),
.I1(\i3/blk00000001/sig0000011f/F ),
.O(\i3/blk00000001/sig0000011f/XORF_11627 )
);
X_MUX2 #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/CYMUXF (
.IA(\i3/blk00000001/sig0000011f/CY0F_11625 ),
.IB(\i3/blk00000001/sig0000011f/CYINIT_11626 ),
.SEL(\i3/blk00000001/sig0000011f/CYSELF_11616 ),
.O(\i3/blk00000001/sig0000019a )
);
X_BUF #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/CYINIT (
.I(\i3/blk00000001/sig00000135/CYMUXFAST_11579 ),
.O(\i3/blk00000001/sig0000011f/CYINIT_11626 )
);
X_BUF #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/CY0F (
.I(\i3/blk00000001/sig000001ed ),
.O(\i3/blk00000001/sig0000011f/CY0F_11625 )
);
X_AND2 #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/FAND (
.I0(1'b1),
.I1(1'b0),
.O(\i3/blk00000001/sig000001ed )
);
X_BUF #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/CYSELF (
.I(\i3/blk00000001/sig0000011f/F ),
.O(\i3/blk00000001/sig0000011f/CYSELF_11616 )
);
X_BUF #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/YUSED (
.I(\i3/blk00000001/sig0000011f/XORG_11613 ),
.O(\i3/blk00000001/sig00000114 )
);
X_XOR2 #(
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/XORG (
.I0(\i3/blk00000001/sig0000019a ),
.I1(\i3/blk00000001/sig0000011f/G ),
.O(\i3/blk00000001/sig0000011f/XORG_11613 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/XUSED (
.I(\i3/blk00000001/sig000001e0/XORF_11665 ),
.O(\i3/blk00000001/sig000001e0 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/XORF (
.I0(\i3/blk00000001/sig000001e0/CYINIT_11664 ),
.I1(\i3/blk00000001/sig000001e0/F ),
.O(\i3/blk00000001/sig000001e0/XORF_11665 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CYMUXF (
.IA(\i3/blk00000001/sig000001e0/CY0F_11663 ),
.IB(\i3/blk00000001/sig000001e0/CYINIT_11664 ),
.SEL(\i3/blk00000001/sig000001e0/CYSELF_11654 ),
.O(\i3/blk00000001/sig000001e1 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CYINIT (
.I(\i3/blk00000001/sig000001e0/BXINV_11652 ),
.O(\i3/blk00000001/sig000001e0/CYINIT_11664 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CY0F (
.I(\i3/blk00000001/sig00000232 ),
.O(\i3/blk00000001/sig000001e0/CY0F_11663 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig000001e0/FAND/IN1 ),
.O(\i3/blk00000001/sig00000232 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CYSELF (
.I(\i3/blk00000001/sig000001e0/F ),
.O(\i3/blk00000001/sig000001e0/CYSELF_11654 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000001e0/BXINV_11652 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/YUSED (
.I(\i3/blk00000001/sig000001e0/XORG_11650 ),
.O(\i3/blk00000001/sig0000018e )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/XORG (
.I0(\i3/blk00000001/sig000001e1 ),
.I1(\i3/blk00000001/sig000001e0/G ),
.O(\i3/blk00000001/sig000001e0/XORG_11650 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/COUTUSED (
.I(\i3/blk00000001/sig000001e0/CYMUXG_11649 ),
.O(\i3/blk00000001/sig000001df )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CYMUXG (
.IA(\i3/blk00000001/sig000001e0/CY0G_11647 ),
.IB(\i3/blk00000001/sig000001e1 ),
.SEL(\i3/blk00000001/sig000001e0/CYSELG_11638 ),
.O(\i3/blk00000001/sig000001e0/CYMUXG_11649 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CY0G (
.I(\i3/blk00000001/sig00000231 ),
.O(\i3/blk00000001/sig000001e0/CY0G_11647 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig000001e0/GAND/IN1 ),
.O(\i3/blk00000001/sig00000231 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/CYSELG (
.I(\i3/blk00000001/sig000001e0/G ),
.O(\i3/blk00000001/sig000001e0/CYSELG_11638 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/XUSED (
.I(\i3/blk00000001/sig0000018c/XORF_11706 ),
.O(\i3/blk00000001/sig0000018c )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/XORF (
.I0(\i3/blk00000001/sig0000018c/CYINIT_11705 ),
.I1(\i3/blk00000001/sig0000018c/F ),
.O(\i3/blk00000001/sig0000018c/XORF_11706 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYMUXF (
.IA(\i3/blk00000001/sig0000018c/CY0F_11704 ),
.IB(\i3/blk00000001/sig0000018c/CYINIT_11705 ),
.SEL(\i3/blk00000001/sig0000018c/CYSELF_11691 ),
.O(\i3/blk00000001/sig000001d4 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYMUXF2 (
.IA(\i3/blk00000001/sig0000018c/CY0F_11704 ),
.IB(\i3/blk00000001/sig0000018c/CY0F_11704 ),
.SEL(\i3/blk00000001/sig0000018c/CYSELF_11691 ),
.O(\i3/blk00000001/sig0000018c/CYMUXF2_11686 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYINIT (
.I(\i3/blk00000001/sig000001df ),
.O(\i3/blk00000001/sig0000018c/CYINIT_11705 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CY0F (
.I(\i3/blk00000001/sig00000227 ),
.O(\i3/blk00000001/sig0000018c/CY0F_11704 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000018c/FAND/IN1 ),
.O(\i3/blk00000001/sig00000227 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYSELF (
.I(\i3/blk00000001/sig0000018c/F ),
.O(\i3/blk00000001/sig0000018c/CYSELF_11691 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/YUSED (
.I(\i3/blk00000001/sig0000018c/XORG_11693 ),
.O(\i3/blk00000001/sig0000017e )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/XORG (
.I0(\i3/blk00000001/sig000001d4 ),
.I1(\i3/blk00000001/sig0000018c/G ),
.O(\i3/blk00000001/sig0000018c/XORG_11693 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/COUTUSED (
.I(\i3/blk00000001/sig0000018c/CYMUXFAST_11690 ),
.O(\i3/blk00000001/sig000001ce )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/FASTCARRY (
.I(\i3/blk00000001/sig000001df ),
.O(\i3/blk00000001/sig0000018c/FASTCARRY_11688 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYAND (
.I0(\i3/blk00000001/sig0000018c/CYSELG_11676 ),
.I1(\i3/blk00000001/sig0000018c/CYSELF_11691 ),
.O(\i3/blk00000001/sig0000018c/CYAND_11689 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYMUXFAST (
.IA(\i3/blk00000001/sig0000018c/CYMUXG2_11687 ),
.IB(\i3/blk00000001/sig0000018c/FASTCARRY_11688 ),
.SEL(\i3/blk00000001/sig0000018c/CYAND_11689 ),
.O(\i3/blk00000001/sig0000018c/CYMUXFAST_11690 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYMUXG2 (
.IA(\i3/blk00000001/sig0000018c/CY0G_11685 ),
.IB(\i3/blk00000001/sig0000018c/CYMUXF2_11686 ),
.SEL(\i3/blk00000001/sig0000018c/CYSELG_11676 ),
.O(\i3/blk00000001/sig0000018c/CYMUXG2_11687 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CY0G (
.I(\i3/blk00000001/sig00000221 ),
.O(\i3/blk00000001/sig0000018c/CY0G_11685 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000018c/GAND/IN1 ),
.O(\i3/blk00000001/sig00000221 )
);
X_BUF #(
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/CYSELG (
.I(\i3/blk00000001/sig0000018c/G ),
.O(\i3/blk00000001/sig0000018c/CYSELG_11676 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/XUSED (
.I(\i3/blk00000001/sig00000173/XORF_11747 ),
.O(\i3/blk00000001/sig00000173 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/XORF (
.I0(\i3/blk00000001/sig00000173/CYINIT_11746 ),
.I1(\i3/blk00000001/sig00000173/F ),
.O(\i3/blk00000001/sig00000173/XORF_11747 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYMUXF (
.IA(\i3/blk00000001/sig00000173/CY0F_11745 ),
.IB(\i3/blk00000001/sig00000173/CYINIT_11746 ),
.SEL(\i3/blk00000001/sig00000173/CYSELF_11732 ),
.O(\i3/blk00000001/sig000001c8 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYMUXF2 (
.IA(\i3/blk00000001/sig00000173/CY0F_11745 ),
.IB(\i3/blk00000001/sig00000173/CY0F_11745 ),
.SEL(\i3/blk00000001/sig00000173/CYSELF_11732 ),
.O(\i3/blk00000001/sig00000173/CYMUXF2_11727 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYINIT (
.I(\i3/blk00000001/sig000001ce ),
.O(\i3/blk00000001/sig00000173/CYINIT_11746 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CY0F (
.I(\i3/blk00000001/sig0000021b ),
.O(\i3/blk00000001/sig00000173/CY0F_11745 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000173/FAND/IN1 ),
.O(\i3/blk00000001/sig0000021b )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYSELF (
.I(\i3/blk00000001/sig00000173/F ),
.O(\i3/blk00000001/sig00000173/CYSELF_11732 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/YUSED (
.I(\i3/blk00000001/sig00000173/XORG_11734 ),
.O(\i3/blk00000001/sig00000168 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/XORG (
.I0(\i3/blk00000001/sig000001c8 ),
.I1(\i3/blk00000001/sig00000173/G ),
.O(\i3/blk00000001/sig00000173/XORG_11734 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/COUTUSED (
.I(\i3/blk00000001/sig00000173/CYMUXFAST_11731 ),
.O(\i3/blk00000001/sig000001c2 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/FASTCARRY (
.I(\i3/blk00000001/sig000001ce ),
.O(\i3/blk00000001/sig00000173/FASTCARRY_11729 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYAND (
.I0(\i3/blk00000001/sig00000173/CYSELG_11717 ),
.I1(\i3/blk00000001/sig00000173/CYSELF_11732 ),
.O(\i3/blk00000001/sig00000173/CYAND_11730 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYMUXFAST (
.IA(\i3/blk00000001/sig00000173/CYMUXG2_11728 ),
.IB(\i3/blk00000001/sig00000173/FASTCARRY_11729 ),
.SEL(\i3/blk00000001/sig00000173/CYAND_11730 ),
.O(\i3/blk00000001/sig00000173/CYMUXFAST_11731 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYMUXG2 (
.IA(\i3/blk00000001/sig00000173/CY0G_11726 ),
.IB(\i3/blk00000001/sig00000173/CYMUXF2_11727 ),
.SEL(\i3/blk00000001/sig00000173/CYSELG_11717 ),
.O(\i3/blk00000001/sig00000173/CYMUXG2_11728 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CY0G (
.I(\i3/blk00000001/sig00000215 ),
.O(\i3/blk00000001/sig00000173/CY0G_11726 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000173/GAND/IN1 ),
.O(\i3/blk00000001/sig00000215 )
);
X_BUF #(
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/CYSELG (
.I(\i3/blk00000001/sig00000173/G ),
.O(\i3/blk00000001/sig00000173/CYSELG_11717 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/XUSED (
.I(\i3/blk00000001/sig0000015d/XORF_11788 ),
.O(\i3/blk00000001/sig0000015d )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/XORF (
.I0(\i3/blk00000001/sig0000015d/CYINIT_11787 ),
.I1(\i3/blk00000001/sig0000015d/F ),
.O(\i3/blk00000001/sig0000015d/XORF_11788 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYMUXF (
.IA(\i3/blk00000001/sig0000015d/CY0F_11786 ),
.IB(\i3/blk00000001/sig0000015d/CYINIT_11787 ),
.SEL(\i3/blk00000001/sig0000015d/CYSELF_11773 ),
.O(\i3/blk00000001/sig000001bc )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYMUXF2 (
.IA(\i3/blk00000001/sig0000015d/CY0F_11786 ),
.IB(\i3/blk00000001/sig0000015d/CY0F_11786 ),
.SEL(\i3/blk00000001/sig0000015d/CYSELF_11773 ),
.O(\i3/blk00000001/sig0000015d/CYMUXF2_11768 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYINIT (
.I(\i3/blk00000001/sig000001c2 ),
.O(\i3/blk00000001/sig0000015d/CYINIT_11787 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CY0F (
.I(\i3/blk00000001/sig0000020f ),
.O(\i3/blk00000001/sig0000015d/CY0F_11786 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000015d/FAND/IN1 ),
.O(\i3/blk00000001/sig0000020f )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYSELF (
.I(\i3/blk00000001/sig0000015d/F ),
.O(\i3/blk00000001/sig0000015d/CYSELF_11773 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/YUSED (
.I(\i3/blk00000001/sig0000015d/XORG_11775 ),
.O(\i3/blk00000001/sig00000152 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/XORG (
.I0(\i3/blk00000001/sig000001bc ),
.I1(\i3/blk00000001/sig0000015d/G ),
.O(\i3/blk00000001/sig0000015d/XORG_11775 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/COUTUSED (
.I(\i3/blk00000001/sig0000015d/CYMUXFAST_11772 ),
.O(\i3/blk00000001/sig000001b6 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/FASTCARRY (
.I(\i3/blk00000001/sig000001c2 ),
.O(\i3/blk00000001/sig0000015d/FASTCARRY_11770 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYAND (
.I0(\i3/blk00000001/sig0000015d/CYSELG_11758 ),
.I1(\i3/blk00000001/sig0000015d/CYSELF_11773 ),
.O(\i3/blk00000001/sig0000015d/CYAND_11771 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYMUXFAST (
.IA(\i3/blk00000001/sig0000015d/CYMUXG2_11769 ),
.IB(\i3/blk00000001/sig0000015d/FASTCARRY_11770 ),
.SEL(\i3/blk00000001/sig0000015d/CYAND_11771 ),
.O(\i3/blk00000001/sig0000015d/CYMUXFAST_11772 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYMUXG2 (
.IA(\i3/blk00000001/sig0000015d/CY0G_11767 ),
.IB(\i3/blk00000001/sig0000015d/CYMUXF2_11768 ),
.SEL(\i3/blk00000001/sig0000015d/CYSELG_11758 ),
.O(\i3/blk00000001/sig0000015d/CYMUXG2_11769 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CY0G (
.I(\i3/blk00000001/sig00000209 ),
.O(\i3/blk00000001/sig0000015d/CY0G_11767 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000015d/GAND/IN1 ),
.O(\i3/blk00000001/sig00000209 )
);
X_BUF #(
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/CYSELG (
.I(\i3/blk00000001/sig0000015d/G ),
.O(\i3/blk00000001/sig0000015d/CYSELG_11758 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/XUSED (
.I(\i3/blk00000001/sig00000147/XORF_11829 ),
.O(\i3/blk00000001/sig00000147 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/XORF (
.I0(\i3/blk00000001/sig00000147/CYINIT_11828 ),
.I1(\i3/blk00000001/sig00000147/F ),
.O(\i3/blk00000001/sig00000147/XORF_11829 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYMUXF (
.IA(\i3/blk00000001/sig00000147/CY0F_11827 ),
.IB(\i3/blk00000001/sig00000147/CYINIT_11828 ),
.SEL(\i3/blk00000001/sig00000147/CYSELF_11814 ),
.O(\i3/blk00000001/sig000001b0 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYMUXF2 (
.IA(\i3/blk00000001/sig00000147/CY0F_11827 ),
.IB(\i3/blk00000001/sig00000147/CY0F_11827 ),
.SEL(\i3/blk00000001/sig00000147/CYSELF_11814 ),
.O(\i3/blk00000001/sig00000147/CYMUXF2_11809 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYINIT (
.I(\i3/blk00000001/sig000001b6 ),
.O(\i3/blk00000001/sig00000147/CYINIT_11828 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CY0F (
.I(\i3/blk00000001/sig00000203 ),
.O(\i3/blk00000001/sig00000147/CY0F_11827 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000147/FAND/IN1 ),
.O(\i3/blk00000001/sig00000203 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYSELF (
.I(\i3/blk00000001/sig00000147/F ),
.O(\i3/blk00000001/sig00000147/CYSELF_11814 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/YUSED (
.I(\i3/blk00000001/sig00000147/XORG_11816 ),
.O(\i3/blk00000001/sig0000013c )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/XORG (
.I0(\i3/blk00000001/sig000001b0 ),
.I1(\i3/blk00000001/sig00000147/G ),
.O(\i3/blk00000001/sig00000147/XORG_11816 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/COUTUSED (
.I(\i3/blk00000001/sig00000147/CYMUXFAST_11813 ),
.O(\i3/blk00000001/sig000001aa )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/FASTCARRY (
.I(\i3/blk00000001/sig000001b6 ),
.O(\i3/blk00000001/sig00000147/FASTCARRY_11811 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYAND (
.I0(\i3/blk00000001/sig00000147/CYSELG_11799 ),
.I1(\i3/blk00000001/sig00000147/CYSELF_11814 ),
.O(\i3/blk00000001/sig00000147/CYAND_11812 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYMUXFAST (
.IA(\i3/blk00000001/sig00000147/CYMUXG2_11810 ),
.IB(\i3/blk00000001/sig00000147/FASTCARRY_11811 ),
.SEL(\i3/blk00000001/sig00000147/CYAND_11812 ),
.O(\i3/blk00000001/sig00000147/CYMUXFAST_11813 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYMUXG2 (
.IA(\i3/blk00000001/sig00000147/CY0G_11808 ),
.IB(\i3/blk00000001/sig00000147/CYMUXF2_11809 ),
.SEL(\i3/blk00000001/sig00000147/CYSELG_11799 ),
.O(\i3/blk00000001/sig00000147/CYMUXG2_11810 )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CY0G (
.I(\i3/blk00000001/sig000001fd ),
.O(\i3/blk00000001/sig00000147/CY0G_11808 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/GAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000147/GAND/IN1 ),
.O(\i3/blk00000001/sig000001fd )
);
X_BUF #(
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/CYSELG (
.I(\i3/blk00000001/sig00000147/G ),
.O(\i3/blk00000001/sig00000147/CYSELG_11799 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/XUSED (
.I(\i3/blk00000001/sig00000131/XORF_11870 ),
.O(\i3/blk00000001/sig00000131 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/XORF (
.I0(\i3/blk00000001/sig00000131/CYINIT_11869 ),
.I1(\i3/blk00000001/sig00000131/F ),
.O(\i3/blk00000001/sig00000131/XORF_11870 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYMUXF (
.IA(\i3/blk00000001/sig00000131/CY0F_11868 ),
.IB(\i3/blk00000001/sig00000131/CYINIT_11869 ),
.SEL(\i3/blk00000001/sig00000131/CYSELF_11856 ),
.O(\i3/blk00000001/sig000001a4 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYMUXF2 (
.IA(\i3/blk00000001/sig00000131/CY0F_11868 ),
.IB(\i3/blk00000001/sig00000131/CY0F_11868 ),
.SEL(\i3/blk00000001/sig00000131/CYSELF_11856 ),
.O(\i3/blk00000001/sig00000131/CYMUXF2_11851 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYINIT (
.I(\i3/blk00000001/sig000001aa ),
.O(\i3/blk00000001/sig00000131/CYINIT_11869 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CY0F (
.I(\i3/blk00000001/sig000001f7 ),
.O(\i3/blk00000001/sig00000131/CY0F_11868 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/FAND (
.I0(1'b0),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000131/FAND/IN1 ),
.O(\i3/blk00000001/sig000001f7 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYSELF (
.I(\i3/blk00000001/sig00000131/F ),
.O(\i3/blk00000001/sig00000131/CYSELF_11856 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/YUSED (
.I(\i3/blk00000001/sig00000131/XORG_11858 ),
.O(\i3/blk00000001/sig00000126 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/XORG (
.I0(\i3/blk00000001/sig000001a4 ),
.I1(\i3/blk00000001/sig0000011c ),
.O(\i3/blk00000001/sig00000131/XORG_11858 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/FASTCARRY (
.I(\i3/blk00000001/sig000001aa ),
.O(\i3/blk00000001/sig00000131/FASTCARRY_11853 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYAND (
.I0(\i3/blk00000001/sig00000131/CYSELG_11842 ),
.I1(\i3/blk00000001/sig00000131/CYSELF_11856 ),
.O(\i3/blk00000001/sig00000131/CYAND_11854 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYMUXFAST (
.IA(\i3/blk00000001/sig00000131/CYMUXG2_11852 ),
.IB(\i3/blk00000001/sig00000131/FASTCARRY_11853 ),
.SEL(\i3/blk00000001/sig00000131/CYAND_11854 ),
.O(\i3/blk00000001/sig00000131/CYMUXFAST_11855 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYMUXG2 (
.IA(\i3/blk00000001/sig00000131/CY0G_11850 ),
.IB(\i3/blk00000001/sig00000131/CYMUXF2_11851 ),
.SEL(\i3/blk00000001/sig00000131/CYSELG_11842 ),
.O(\i3/blk00000001/sig00000131/CYMUXG2_11852 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CY0G (
.I(\i3/blk00000001/sig000001f1 ),
.O(\i3/blk00000001/sig00000131/CY0G_11850 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/GAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig00000131/GAND/IN1 ),
.O(\i3/blk00000001/sig000001f1 )
);
X_BUF #(
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/CYSELG (
.I(\i3/blk00000001/sig0000011c ),
.O(\i3/blk00000001/sig00000131/CYSELG_11842 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/blk00000200 (
.ADR0(x3_3_IBUF_3612),
.ADR1(VCC),
.ADR2(x3_2_IBUF_3611),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000111 )
);
X_BUF #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/XUSED (
.I(\i3/blk00000001/sig0000011b/XORF_11902 ),
.O(\i3/blk00000001/sig0000011b )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/XORF (
.I0(\i3/blk00000001/sig0000011b/CYINIT_11901 ),
.I1(\i3/blk00000001/sig00000111 ),
.O(\i3/blk00000001/sig0000011b/XORF_11902 )
);
X_MUX2 #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/CYMUXF (
.IA(\i3/blk00000001/sig0000011b/CY0F_11900 ),
.IB(\i3/blk00000001/sig0000011b/CYINIT_11901 ),
.SEL(\i3/blk00000001/sig0000011b/CYSELF_11892 ),
.O(\i3/blk00000001/sig00000198 )
);
X_BUF #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/CYINIT (
.I(\i3/blk00000001/sig00000131/CYMUXFAST_11855 ),
.O(\i3/blk00000001/sig0000011b/CYINIT_11901 )
);
X_BUF #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/CY0F (
.I(\i3/blk00000001/sig000001eb ),
.O(\i3/blk00000001/sig0000011b/CY0F_11900 )
);
X_AND2 #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/FAND (
.I0(1'b1),
.I1(\NlwBufferSignal_i3/blk00000001/sig0000011b/FAND/IN1 ),
.O(\i3/blk00000001/sig000001eb )
);
X_BUF #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/CYSELF (
.I(\i3/blk00000001/sig00000111 ),
.O(\i3/blk00000001/sig0000011b/CYSELF_11892 )
);
X_BUF #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/YUSED (
.I(\i3/blk00000001/sig0000011b/XORG_11889 ),
.O(\i3/blk00000001/sig00000110 )
);
X_XOR2 #(
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/sig0000011b/XORG (
.I0(\i3/blk00000001/sig00000198 ),
.I1(\i3/blk00000001/sig00000108 ),
.O(\i3/blk00000001/sig0000011b/XORG_11889 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y12" ))
\i3/blk00000001/blk000001ff (
.ADR0(x3_2_IBUF_3611),
.ADR1(x3_3_IBUF_3612),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000108 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/blk0000017d (
.ADR0(\i3/blk00000001/sig00000186 ),
.ADR1(\i3/blk00000001/sig00000185 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000008d )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/XUSED (
.I(\i3/blk00000001/sig000000c4/XORF_11938 ),
.O(\i3/blk00000001/sig000000c4 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/XORF (
.I0(\i3/blk00000001/sig000000c4/CYINIT_11937 ),
.I1(\i3/blk00000001/sig0000008d ),
.O(\i3/blk00000001/sig000000c4/XORF_11938 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CYMUXF (
.IA(\i3/blk00000001/sig000000c4/CY0F_11936 ),
.IB(\i3/blk00000001/sig000000c4/CYINIT_11937 ),
.SEL(\i3/blk00000001/sig000000c4/CYSELF_11928 ),
.O(\i3/blk00000001/sig0000008c )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CYINIT (
.I(\i3/blk00000001/sig000000c4/BXINV_11926 ),
.O(\i3/blk00000001/sig000000c4/CYINIT_11937 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CY0F (
.I(\i3/blk00000001/sig00000186 ),
.O(\i3/blk00000001/sig000000c4/CY0F_11936 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CYSELF (
.I(\i3/blk00000001/sig0000008d ),
.O(\i3/blk00000001/sig000000c4/CYSELF_11928 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000000c4/BXINV_11926 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/YUSED (
.I(\i3/blk00000001/sig000000c4/XORG_11924 ),
.O(\i3/blk00000001/sig000000c5 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/XORG (
.I0(\i3/blk00000001/sig0000008c ),
.I1(\i3/blk00000001/sig0000008b ),
.O(\i3/blk00000001/sig000000c4/XORG_11924 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/COUTUSED (
.I(\i3/blk00000001/sig000000c4/CYMUXG_11923 ),
.O(\i3/blk00000001/sig0000008a )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CYMUXG (
.IA(\i3/blk00000001/sig000000c4/CY0G_11921 ),
.IB(\i3/blk00000001/sig0000008c ),
.SEL(\i3/blk00000001/sig000000c4/CYSELG_11913 ),
.O(\i3/blk00000001/sig000000c4/CYMUXG_11923 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CY0G (
.I(\i3/blk00000001/sig0000017a ),
.O(\i3/blk00000001/sig000000c4/CY0G_11921 )
);
X_BUF #(
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/sig000000c4/CYSELG (
.I(\i3/blk00000001/sig0000008b ),
.O(\i3/blk00000001/sig000000c4/CYSELG_11913 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X29Y16" ))
\i3/blk00000001/blk0000017a (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig0000017a ),
.ADR2(\i3/blk00000001/sig00000184 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000008b )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/blk00000177 (
.ADR0(\i3/blk00000001/sig0000016f ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig00000179 ),
.O(\i3/blk00000001/sig00000089 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/XUSED (
.I(\i3/blk00000001/sig000000c6/XORF_11977 ),
.O(\i3/blk00000001/sig000000c6 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/XORF (
.I0(\i3/blk00000001/sig000000c6/CYINIT_11976 ),
.I1(\i3/blk00000001/sig00000089 ),
.O(\i3/blk00000001/sig000000c6/XORF_11977 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYMUXF (
.IA(\i3/blk00000001/sig000000c6/CY0F_11975 ),
.IB(\i3/blk00000001/sig000000c6/CYINIT_11976 ),
.SEL(\i3/blk00000001/sig000000c6/CYSELF_11963 ),
.O(\i3/blk00000001/sig00000088 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYMUXF2 (
.IA(\i3/blk00000001/sig000000c6/CY0F_11975 ),
.IB(\i3/blk00000001/sig000000c6/CY0F_11975 ),
.SEL(\i3/blk00000001/sig000000c6/CYSELF_11963 ),
.O(\i3/blk00000001/sig000000c6/CYMUXF2_11958 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYINIT (
.I(\i3/blk00000001/sig0000008a ),
.O(\i3/blk00000001/sig000000c6/CYINIT_11976 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CY0F (
.I(\i3/blk00000001/sig0000016f ),
.O(\i3/blk00000001/sig000000c6/CY0F_11975 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYSELF (
.I(\i3/blk00000001/sig00000089 ),
.O(\i3/blk00000001/sig000000c6/CYSELF_11963 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/YUSED (
.I(\i3/blk00000001/sig000000c6/XORG_11965 ),
.O(\i3/blk00000001/sig000000c7 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/XORG (
.I0(\i3/blk00000001/sig00000088 ),
.I1(\i3/blk00000001/sig00000087 ),
.O(\i3/blk00000001/sig000000c6/XORG_11965 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/COUTUSED (
.I(\i3/blk00000001/sig000000c6/CYMUXFAST_11962 ),
.O(\i3/blk00000001/sig00000086 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/FASTCARRY (
.I(\i3/blk00000001/sig0000008a ),
.O(\i3/blk00000001/sig000000c6/FASTCARRY_11960 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYAND (
.I0(\i3/blk00000001/sig000000c6/CYSELG_11949 ),
.I1(\i3/blk00000001/sig000000c6/CYSELF_11963 ),
.O(\i3/blk00000001/sig000000c6/CYAND_11961 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYMUXFAST (
.IA(\i3/blk00000001/sig000000c6/CYMUXG2_11959 ),
.IB(\i3/blk00000001/sig000000c6/FASTCARRY_11960 ),
.SEL(\i3/blk00000001/sig000000c6/CYAND_11961 ),
.O(\i3/blk00000001/sig000000c6/CYMUXFAST_11962 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYMUXG2 (
.IA(\i3/blk00000001/sig000000c6/CY0G_11957 ),
.IB(\i3/blk00000001/sig000000c6/CYMUXF2_11958 ),
.SEL(\i3/blk00000001/sig000000c6/CYSELG_11949 ),
.O(\i3/blk00000001/sig000000c6/CYMUXG2_11959 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CY0G (
.I(\i3/blk00000001/sig00000164 ),
.O(\i3/blk00000001/sig000000c6/CY0G_11957 )
);
X_BUF #(
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/sig000000c6/CYSELG (
.I(\i3/blk00000001/sig00000087 ),
.O(\i3/blk00000001/sig000000c6/CYSELG_11949 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y17" ))
\i3/blk00000001/blk00000174 (
.ADR0(\i3/blk00000001/sig00000164 ),
.ADR1(\i3/blk00000001/sig0000016e ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000087 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/blk00000171 (
.ADR0(\i3/blk00000001/sig00000159 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig00000163 ),
.O(\i3/blk00000001/sig00000085 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/XUSED (
.I(\i3/blk00000001/sig000000c8/XORF_12016 ),
.O(\i3/blk00000001/sig000000c8 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/XORF (
.I0(\i3/blk00000001/sig000000c8/CYINIT_12015 ),
.I1(\i3/blk00000001/sig00000085 ),
.O(\i3/blk00000001/sig000000c8/XORF_12016 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYMUXF (
.IA(\i3/blk00000001/sig000000c8/CY0F_12014 ),
.IB(\i3/blk00000001/sig000000c8/CYINIT_12015 ),
.SEL(\i3/blk00000001/sig000000c8/CYSELF_12002 ),
.O(\i3/blk00000001/sig00000084 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYMUXF2 (
.IA(\i3/blk00000001/sig000000c8/CY0F_12014 ),
.IB(\i3/blk00000001/sig000000c8/CY0F_12014 ),
.SEL(\i3/blk00000001/sig000000c8/CYSELF_12002 ),
.O(\i3/blk00000001/sig000000c8/CYMUXF2_11997 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYINIT (
.I(\i3/blk00000001/sig00000086 ),
.O(\i3/blk00000001/sig000000c8/CYINIT_12015 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CY0F (
.I(\i3/blk00000001/sig00000159 ),
.O(\i3/blk00000001/sig000000c8/CY0F_12014 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYSELF (
.I(\i3/blk00000001/sig00000085 ),
.O(\i3/blk00000001/sig000000c8/CYSELF_12002 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/YUSED (
.I(\i3/blk00000001/sig000000c8/XORG_12004 ),
.O(\i3/blk00000001/sig000000c9 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/XORG (
.I0(\i3/blk00000001/sig00000084 ),
.I1(\i3/blk00000001/sig00000083 ),
.O(\i3/blk00000001/sig000000c8/XORG_12004 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/COUTUSED (
.I(\i3/blk00000001/sig000000c8/CYMUXFAST_12001 ),
.O(\i3/blk00000001/sig00000082 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/FASTCARRY (
.I(\i3/blk00000001/sig00000086 ),
.O(\i3/blk00000001/sig000000c8/FASTCARRY_11999 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYAND (
.I0(\i3/blk00000001/sig000000c8/CYSELG_11988 ),
.I1(\i3/blk00000001/sig000000c8/CYSELF_12002 ),
.O(\i3/blk00000001/sig000000c8/CYAND_12000 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYMUXFAST (
.IA(\i3/blk00000001/sig000000c8/CYMUXG2_11998 ),
.IB(\i3/blk00000001/sig000000c8/FASTCARRY_11999 ),
.SEL(\i3/blk00000001/sig000000c8/CYAND_12000 ),
.O(\i3/blk00000001/sig000000c8/CYMUXFAST_12001 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYMUXG2 (
.IA(\i3/blk00000001/sig000000c8/CY0G_11996 ),
.IB(\i3/blk00000001/sig000000c8/CYMUXF2_11997 ),
.SEL(\i3/blk00000001/sig000000c8/CYSELG_11988 ),
.O(\i3/blk00000001/sig000000c8/CYMUXG2_11998 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CY0G (
.I(\i3/blk00000001/sig0000014e ),
.O(\i3/blk00000001/sig000000c8/CY0G_11996 )
);
X_BUF #(
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/sig000000c8/CYSELG (
.I(\i3/blk00000001/sig00000083 ),
.O(\i3/blk00000001/sig000000c8/CYSELG_11988 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y18" ))
\i3/blk00000001/blk0000016e (
.ADR0(\i3/blk00000001/sig0000014e ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig00000158 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000083 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/XUSED (
.I(\i3/blk00000001/sig000000ca/XORF_12055 ),
.O(\i3/blk00000001/sig000000ca )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/XORF (
.I0(\i3/blk00000001/sig000000ca/CYINIT_12054 ),
.I1(\i3/blk00000001/sig00000081 ),
.O(\i3/blk00000001/sig000000ca/XORF_12055 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYMUXF (
.IA(\i3/blk00000001/sig000000ca/CY0F_12053 ),
.IB(\i3/blk00000001/sig000000ca/CYINIT_12054 ),
.SEL(\i3/blk00000001/sig000000ca/CYSELF_12041 ),
.O(\i3/blk00000001/sig00000080 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYMUXF2 (
.IA(\i3/blk00000001/sig000000ca/CY0F_12053 ),
.IB(\i3/blk00000001/sig000000ca/CY0F_12053 ),
.SEL(\i3/blk00000001/sig000000ca/CYSELF_12041 ),
.O(\i3/blk00000001/sig000000ca/CYMUXF2_12036 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYINIT (
.I(\i3/blk00000001/sig00000082 ),
.O(\i3/blk00000001/sig000000ca/CYINIT_12054 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CY0F (
.I(\i3/blk00000001/sig00000143 ),
.O(\i3/blk00000001/sig000000ca/CY0F_12053 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYSELF (
.I(\i3/blk00000001/sig00000081 ),
.O(\i3/blk00000001/sig000000ca/CYSELF_12041 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/YUSED (
.I(\i3/blk00000001/sig000000ca/XORG_12043 ),
.O(\i3/blk00000001/sig000000cb )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/XORG (
.I0(\i3/blk00000001/sig00000080 ),
.I1(\i3/blk00000001/sig0000007f ),
.O(\i3/blk00000001/sig000000ca/XORG_12043 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/COUTUSED (
.I(\i3/blk00000001/sig000000ca/CYMUXFAST_12040 ),
.O(\i3/blk00000001/sig0000007e )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/FASTCARRY (
.I(\i3/blk00000001/sig00000082 ),
.O(\i3/blk00000001/sig000000ca/FASTCARRY_12038 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYAND (
.I0(\i3/blk00000001/sig000000ca/CYSELG_12027 ),
.I1(\i3/blk00000001/sig000000ca/CYSELF_12041 ),
.O(\i3/blk00000001/sig000000ca/CYAND_12039 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYMUXFAST (
.IA(\i3/blk00000001/sig000000ca/CYMUXG2_12037 ),
.IB(\i3/blk00000001/sig000000ca/FASTCARRY_12038 ),
.SEL(\i3/blk00000001/sig000000ca/CYAND_12039 ),
.O(\i3/blk00000001/sig000000ca/CYMUXFAST_12040 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYMUXG2 (
.IA(\i3/blk00000001/sig000000ca/CY0G_12035 ),
.IB(\i3/blk00000001/sig000000ca/CYMUXF2_12036 ),
.SEL(\i3/blk00000001/sig000000ca/CYSELG_12027 ),
.O(\i3/blk00000001/sig000000ca/CYMUXG2_12037 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CY0G (
.I(\i3/blk00000001/sig00000138 ),
.O(\i3/blk00000001/sig000000ca/CY0G_12035 )
);
X_BUF #(
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/sig000000ca/CYSELG (
.I(\i3/blk00000001/sig0000007f ),
.O(\i3/blk00000001/sig000000ca/CYSELG_12027 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/XUSED (
.I(\i3/blk00000001/sig000000cc/XORF_12094 ),
.O(\i3/blk00000001/sig000000cc )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/XORF (
.I0(\i3/blk00000001/sig000000cc/CYINIT_12093 ),
.I1(\i3/blk00000001/sig0000007d ),
.O(\i3/blk00000001/sig000000cc/XORF_12094 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYMUXF (
.IA(\i3/blk00000001/sig000000cc/CY0F_12092 ),
.IB(\i3/blk00000001/sig000000cc/CYINIT_12093 ),
.SEL(\i3/blk00000001/sig000000cc/CYSELF_12080 ),
.O(\i3/blk00000001/sig0000007c )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYMUXF2 (
.IA(\i3/blk00000001/sig000000cc/CY0F_12092 ),
.IB(\i3/blk00000001/sig000000cc/CY0F_12092 ),
.SEL(\i3/blk00000001/sig000000cc/CYSELF_12080 ),
.O(\i3/blk00000001/sig000000cc/CYMUXF2_12075 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYINIT (
.I(\i3/blk00000001/sig0000007e ),
.O(\i3/blk00000001/sig000000cc/CYINIT_12093 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CY0F (
.I(\i3/blk00000001/sig0000012d ),
.O(\i3/blk00000001/sig000000cc/CY0F_12092 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYSELF (
.I(\i3/blk00000001/sig0000007d ),
.O(\i3/blk00000001/sig000000cc/CYSELF_12080 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/YUSED (
.I(\i3/blk00000001/sig000000cc/XORG_12082 ),
.O(\i3/blk00000001/sig000000cd )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/XORG (
.I0(\i3/blk00000001/sig0000007c ),
.I1(\i3/blk00000001/sig0000007b ),
.O(\i3/blk00000001/sig000000cc/XORG_12082 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/COUTUSED (
.I(\i3/blk00000001/sig000000cc/CYMUXFAST_12079 ),
.O(\i3/blk00000001/sig0000007a )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/FASTCARRY (
.I(\i3/blk00000001/sig0000007e ),
.O(\i3/blk00000001/sig000000cc/FASTCARRY_12077 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYAND (
.I0(\i3/blk00000001/sig000000cc/CYSELG_12066 ),
.I1(\i3/blk00000001/sig000000cc/CYSELF_12080 ),
.O(\i3/blk00000001/sig000000cc/CYAND_12078 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYMUXFAST (
.IA(\i3/blk00000001/sig000000cc/CYMUXG2_12076 ),
.IB(\i3/blk00000001/sig000000cc/FASTCARRY_12077 ),
.SEL(\i3/blk00000001/sig000000cc/CYAND_12078 ),
.O(\i3/blk00000001/sig000000cc/CYMUXFAST_12079 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYMUXG2 (
.IA(\i3/blk00000001/sig000000cc/CY0G_12074 ),
.IB(\i3/blk00000001/sig000000cc/CYMUXF2_12075 ),
.SEL(\i3/blk00000001/sig000000cc/CYSELG_12066 ),
.O(\i3/blk00000001/sig000000cc/CYMUXG2_12076 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CY0G (
.I(\i3/blk00000001/sig00000122 ),
.O(\i3/blk00000001/sig000000cc/CY0G_12074 )
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/sig000000cc/CYSELG (
.I(\i3/blk00000001/sig0000007b ),
.O(\i3/blk00000001/sig000000cc/CYSELG_12066 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/XUSED (
.I(\i3/blk00000001/sig000000ce/XORF_12133 ),
.O(\i3/blk00000001/sig000000ce )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/XORF (
.I0(\i3/blk00000001/sig000000ce/CYINIT_12132 ),
.I1(\i3/blk00000001/sig00000079 ),
.O(\i3/blk00000001/sig000000ce/XORF_12133 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYMUXF (
.IA(\i3/blk00000001/sig000000ce/CY0F_12131 ),
.IB(\i3/blk00000001/sig000000ce/CYINIT_12132 ),
.SEL(\i3/blk00000001/sig000000ce/CYSELF_12119 ),
.O(\i3/blk00000001/sig00000078 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYMUXF2 (
.IA(\i3/blk00000001/sig000000ce/CY0F_12131 ),
.IB(\i3/blk00000001/sig000000ce/CY0F_12131 ),
.SEL(\i3/blk00000001/sig000000ce/CYSELF_12119 ),
.O(\i3/blk00000001/sig000000ce/CYMUXF2_12114 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYINIT (
.I(\i3/blk00000001/sig0000007a ),
.O(\i3/blk00000001/sig000000ce/CYINIT_12132 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CY0F (
.I(\i3/blk00000001/sig00000117 ),
.O(\i3/blk00000001/sig000000ce/CY0F_12131 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYSELF (
.I(\i3/blk00000001/sig00000079 ),
.O(\i3/blk00000001/sig000000ce/CYSELF_12119 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/YUSED (
.I(\i3/blk00000001/sig000000ce/XORG_12121 ),
.O(\i3/blk00000001/sig000000cf )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/XORG (
.I0(\i3/blk00000001/sig00000078 ),
.I1(\i3/blk00000001/sig00000077 ),
.O(\i3/blk00000001/sig000000ce/XORG_12121 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/FASTCARRY (
.I(\i3/blk00000001/sig0000007a ),
.O(\i3/blk00000001/sig000000ce/FASTCARRY_12116 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYAND (
.I0(\i3/blk00000001/sig000000ce/CYSELG_12105 ),
.I1(\i3/blk00000001/sig000000ce/CYSELF_12119 ),
.O(\i3/blk00000001/sig000000ce/CYAND_12117 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYMUXFAST (
.IA(\i3/blk00000001/sig000000ce/CYMUXG2_12115 ),
.IB(\i3/blk00000001/sig000000ce/FASTCARRY_12116 ),
.SEL(\i3/blk00000001/sig000000ce/CYAND_12117 ),
.O(\i3/blk00000001/sig000000ce/CYMUXFAST_12118 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYMUXG2 (
.IA(\i3/blk00000001/sig000000ce/CY0G_12113 ),
.IB(\i3/blk00000001/sig000000ce/CYMUXF2_12114 ),
.SEL(\i3/blk00000001/sig000000ce/CYSELG_12105 ),
.O(\i3/blk00000001/sig000000ce/CYMUXG2_12115 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CY0G (
.I(\i3/blk00000001/sig0000010c ),
.O(\i3/blk00000001/sig000000ce/CY0G_12113 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/sig000000ce/CYSELG (
.I(\i3/blk00000001/sig00000077 ),
.O(\i3/blk00000001/sig000000ce/CYSELG_12105 )
);
X_BUF #(
.LOC ( "SLICE_X29Y22" ))
\i3/blk00000001/sig000000d0/XUSED (
.I(\i3/blk00000001/sig000000d0/XORF_12148 ),
.O(\i3/blk00000001/sig000000d0 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y22" ))
\i3/blk00000001/sig000000d0/XORF (
.I0(\i3/blk00000001/sig000000d0/CYINIT_12147 ),
.I1(\i3/blk00000001/sig00000075 ),
.O(\i3/blk00000001/sig000000d0/XORF_12148 )
);
X_BUF #(
.LOC ( "SLICE_X29Y22" ))
\i3/blk00000001/sig000000d0/CYINIT (
.I(\i3/blk00000001/sig000000ce/CYMUXFAST_12118 ),
.O(\i3/blk00000001/sig000000d0/CYINIT_12147 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/XUSED (
.I(\i3/blk00000001/sig000000eb/XORF_12184 ),
.O(\i3/blk00000001/sig000000eb )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/XORF (
.I0(\i3/blk00000001/sig000000eb/CYINIT_12183 ),
.I1(\i3/blk00000001/sig000000a8 ),
.O(\i3/blk00000001/sig000000eb/XORF_12184 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CYMUXF (
.IA(\i3/blk00000001/sig000000eb/CY0F_12182 ),
.IB(\i3/blk00000001/sig000000eb/CYINIT_12183 ),
.SEL(\i3/blk00000001/sig000000eb/CYSELF_12174 ),
.O(\i3/blk00000001/sig000000a7 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CYINIT (
.I(\i3/blk00000001/sig000000eb/BXINV_12172 ),
.O(\i3/blk00000001/sig000000eb/CYINIT_12183 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CY0F (
.I(\i3/blk00000001/sig0000018c ),
.O(\i3/blk00000001/sig000000eb/CY0F_12182 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CYSELF (
.I(\i3/blk00000001/sig000000a8 ),
.O(\i3/blk00000001/sig000000eb/CYSELF_12174 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000000eb/BXINV_12172 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/YUSED (
.I(\i3/blk00000001/sig000000eb/XORG_12170 ),
.O(\i3/blk00000001/sig000000ec )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/XORG (
.I0(\i3/blk00000001/sig000000a7 ),
.I1(\i3/blk00000001/sig000000a6 ),
.O(\i3/blk00000001/sig000000eb/XORG_12170 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/COUTUSED (
.I(\i3/blk00000001/sig000000eb/CYMUXG_12169 ),
.O(\i3/blk00000001/sig000000a5 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CYMUXG (
.IA(\i3/blk00000001/sig000000eb/CY0G_12167 ),
.IB(\i3/blk00000001/sig000000a7 ),
.SEL(\i3/blk00000001/sig000000eb/CYSELG_12159 ),
.O(\i3/blk00000001/sig000000eb/CYMUXG_12169 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CY0G (
.I(\i3/blk00000001/sig0000017e ),
.O(\i3/blk00000001/sig000000eb/CY0G_12167 )
);
X_BUF #(
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/sig000000eb/CYSELG (
.I(\i3/blk00000001/sig000000a6 ),
.O(\i3/blk00000001/sig000000eb/CYSELG_12159 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/XUSED (
.I(\i3/blk00000001/sig000000ed/XORF_12223 ),
.O(\i3/blk00000001/sig000000ed )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/XORF (
.I0(\i3/blk00000001/sig000000ed/CYINIT_12222 ),
.I1(\i3/blk00000001/sig000000a4 ),
.O(\i3/blk00000001/sig000000ed/XORF_12223 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYMUXF (
.IA(\i3/blk00000001/sig000000ed/CY0F_12221 ),
.IB(\i3/blk00000001/sig000000ed/CYINIT_12222 ),
.SEL(\i3/blk00000001/sig000000ed/CYSELF_12209 ),
.O(\i3/blk00000001/sig000000a3 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYMUXF2 (
.IA(\i3/blk00000001/sig000000ed/CY0F_12221 ),
.IB(\i3/blk00000001/sig000000ed/CY0F_12221 ),
.SEL(\i3/blk00000001/sig000000ed/CYSELF_12209 ),
.O(\i3/blk00000001/sig000000ed/CYMUXF2_12204 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYINIT (
.I(\i3/blk00000001/sig000000a5 ),
.O(\i3/blk00000001/sig000000ed/CYINIT_12222 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CY0F (
.I(\i3/blk00000001/sig00000173 ),
.O(\i3/blk00000001/sig000000ed/CY0F_12221 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYSELF (
.I(\i3/blk00000001/sig000000a4 ),
.O(\i3/blk00000001/sig000000ed/CYSELF_12209 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/YUSED (
.I(\i3/blk00000001/sig000000ed/XORG_12211 ),
.O(\i3/blk00000001/sig000000ee )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/XORG (
.I0(\i3/blk00000001/sig000000a3 ),
.I1(\i3/blk00000001/sig000000a2 ),
.O(\i3/blk00000001/sig000000ed/XORG_12211 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/COUTUSED (
.I(\i3/blk00000001/sig000000ed/CYMUXFAST_12208 ),
.O(\i3/blk00000001/sig000000a1 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/FASTCARRY (
.I(\i3/blk00000001/sig000000a5 ),
.O(\i3/blk00000001/sig000000ed/FASTCARRY_12206 )
);
X_AND2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYAND (
.I0(\i3/blk00000001/sig000000ed/CYSELG_12195 ),
.I1(\i3/blk00000001/sig000000ed/CYSELF_12209 ),
.O(\i3/blk00000001/sig000000ed/CYAND_12207 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYMUXFAST (
.IA(\i3/blk00000001/sig000000ed/CYMUXG2_12205 ),
.IB(\i3/blk00000001/sig000000ed/FASTCARRY_12206 ),
.SEL(\i3/blk00000001/sig000000ed/CYAND_12207 ),
.O(\i3/blk00000001/sig000000ed/CYMUXFAST_12208 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYMUXG2 (
.IA(\i3/blk00000001/sig000000ed/CY0G_12203 ),
.IB(\i3/blk00000001/sig000000ed/CYMUXF2_12204 ),
.SEL(\i3/blk00000001/sig000000ed/CYSELG_12195 ),
.O(\i3/blk00000001/sig000000ed/CYMUXG2_12205 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CY0G (
.I(\i3/blk00000001/sig00000168 ),
.O(\i3/blk00000001/sig000000ed/CY0G_12203 )
);
X_BUF #(
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/sig000000ed/CYSELG (
.I(\i3/blk00000001/sig000000a2 ),
.O(\i3/blk00000001/sig000000ed/CYSELG_12195 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/XUSED (
.I(\i3/blk00000001/sig000000ef/XORF_12262 ),
.O(\i3/blk00000001/sig000000ef )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/XORF (
.I0(\i3/blk00000001/sig000000ef/CYINIT_12261 ),
.I1(\i3/blk00000001/sig000000a0 ),
.O(\i3/blk00000001/sig000000ef/XORF_12262 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYMUXF (
.IA(\i3/blk00000001/sig000000ef/CY0F_12260 ),
.IB(\i3/blk00000001/sig000000ef/CYINIT_12261 ),
.SEL(\i3/blk00000001/sig000000ef/CYSELF_12248 ),
.O(\i3/blk00000001/sig0000009f )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYMUXF2 (
.IA(\i3/blk00000001/sig000000ef/CY0F_12260 ),
.IB(\i3/blk00000001/sig000000ef/CY0F_12260 ),
.SEL(\i3/blk00000001/sig000000ef/CYSELF_12248 ),
.O(\i3/blk00000001/sig000000ef/CYMUXF2_12243 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYINIT (
.I(\i3/blk00000001/sig000000a1 ),
.O(\i3/blk00000001/sig000000ef/CYINIT_12261 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CY0F (
.I(\i3/blk00000001/sig0000015d ),
.O(\i3/blk00000001/sig000000ef/CY0F_12260 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYSELF (
.I(\i3/blk00000001/sig000000a0 ),
.O(\i3/blk00000001/sig000000ef/CYSELF_12248 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/YUSED (
.I(\i3/blk00000001/sig000000ef/XORG_12250 ),
.O(\i3/blk00000001/sig000000f0 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/XORG (
.I0(\i3/blk00000001/sig0000009f ),
.I1(\i3/blk00000001/sig0000009e ),
.O(\i3/blk00000001/sig000000ef/XORG_12250 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/COUTUSED (
.I(\i3/blk00000001/sig000000ef/CYMUXFAST_12247 ),
.O(\i3/blk00000001/sig0000009d )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/FASTCARRY (
.I(\i3/blk00000001/sig000000a1 ),
.O(\i3/blk00000001/sig000000ef/FASTCARRY_12245 )
);
X_AND2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYAND (
.I0(\i3/blk00000001/sig000000ef/CYSELG_12234 ),
.I1(\i3/blk00000001/sig000000ef/CYSELF_12248 ),
.O(\i3/blk00000001/sig000000ef/CYAND_12246 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYMUXFAST (
.IA(\i3/blk00000001/sig000000ef/CYMUXG2_12244 ),
.IB(\i3/blk00000001/sig000000ef/FASTCARRY_12245 ),
.SEL(\i3/blk00000001/sig000000ef/CYAND_12246 ),
.O(\i3/blk00000001/sig000000ef/CYMUXFAST_12247 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYMUXG2 (
.IA(\i3/blk00000001/sig000000ef/CY0G_12242 ),
.IB(\i3/blk00000001/sig000000ef/CYMUXF2_12243 ),
.SEL(\i3/blk00000001/sig000000ef/CYSELG_12234 ),
.O(\i3/blk00000001/sig000000ef/CYMUXG2_12244 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CY0G (
.I(\i3/blk00000001/sig00000152 ),
.O(\i3/blk00000001/sig000000ef/CY0G_12242 )
);
X_BUF #(
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/sig000000ef/CYSELG (
.I(\i3/blk00000001/sig0000009e ),
.O(\i3/blk00000001/sig000000ef/CYSELG_12234 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/XUSED (
.I(\i3/blk00000001/sig000000f1/XORF_12301 ),
.O(\i3/blk00000001/sig000000f1 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/XORF (
.I0(\i3/blk00000001/sig000000f1/CYINIT_12300 ),
.I1(\i3/blk00000001/sig0000009c ),
.O(\i3/blk00000001/sig000000f1/XORF_12301 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYMUXF (
.IA(\i3/blk00000001/sig000000f1/CY0F_12299 ),
.IB(\i3/blk00000001/sig000000f1/CYINIT_12300 ),
.SEL(\i3/blk00000001/sig000000f1/CYSELF_12287 ),
.O(\i3/blk00000001/sig0000009b )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYMUXF2 (
.IA(\i3/blk00000001/sig000000f1/CY0F_12299 ),
.IB(\i3/blk00000001/sig000000f1/CY0F_12299 ),
.SEL(\i3/blk00000001/sig000000f1/CYSELF_12287 ),
.O(\i3/blk00000001/sig000000f1/CYMUXF2_12282 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYINIT (
.I(\i3/blk00000001/sig0000009d ),
.O(\i3/blk00000001/sig000000f1/CYINIT_12300 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CY0F (
.I(\i3/blk00000001/sig00000147 ),
.O(\i3/blk00000001/sig000000f1/CY0F_12299 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYSELF (
.I(\i3/blk00000001/sig0000009c ),
.O(\i3/blk00000001/sig000000f1/CYSELF_12287 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/YUSED (
.I(\i3/blk00000001/sig000000f1/XORG_12289 ),
.O(\i3/blk00000001/sig000000f2 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/XORG (
.I0(\i3/blk00000001/sig0000009b ),
.I1(\i3/blk00000001/sig0000009a ),
.O(\i3/blk00000001/sig000000f1/XORG_12289 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/COUTUSED (
.I(\i3/blk00000001/sig000000f1/CYMUXFAST_12286 ),
.O(\i3/blk00000001/sig00000099 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/FASTCARRY (
.I(\i3/blk00000001/sig0000009d ),
.O(\i3/blk00000001/sig000000f1/FASTCARRY_12284 )
);
X_AND2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYAND (
.I0(\i3/blk00000001/sig000000f1/CYSELG_12273 ),
.I1(\i3/blk00000001/sig000000f1/CYSELF_12287 ),
.O(\i3/blk00000001/sig000000f1/CYAND_12285 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYMUXFAST (
.IA(\i3/blk00000001/sig000000f1/CYMUXG2_12283 ),
.IB(\i3/blk00000001/sig000000f1/FASTCARRY_12284 ),
.SEL(\i3/blk00000001/sig000000f1/CYAND_12285 ),
.O(\i3/blk00000001/sig000000f1/CYMUXFAST_12286 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYMUXG2 (
.IA(\i3/blk00000001/sig000000f1/CY0G_12281 ),
.IB(\i3/blk00000001/sig000000f1/CYMUXF2_12282 ),
.SEL(\i3/blk00000001/sig000000f1/CYSELG_12273 ),
.O(\i3/blk00000001/sig000000f1/CYMUXG2_12283 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CY0G (
.I(\i3/blk00000001/sig0000013c ),
.O(\i3/blk00000001/sig000000f1/CY0G_12281 )
);
X_BUF #(
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/sig000000f1/CYSELG (
.I(\i3/blk00000001/sig0000009a ),
.O(\i3/blk00000001/sig000000f1/CYSELG_12273 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/XUSED (
.I(\i3/blk00000001/sig000000f3/XORF_12340 ),
.O(\i3/blk00000001/sig000000f3 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/XORF (
.I0(\i3/blk00000001/sig000000f3/CYINIT_12339 ),
.I1(\i3/blk00000001/sig00000098 ),
.O(\i3/blk00000001/sig000000f3/XORF_12340 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYMUXF (
.IA(\i3/blk00000001/sig000000f3/CY0F_12338 ),
.IB(\i3/blk00000001/sig000000f3/CYINIT_12339 ),
.SEL(\i3/blk00000001/sig000000f3/CYSELF_12326 ),
.O(\i3/blk00000001/sig00000097 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYMUXF2 (
.IA(\i3/blk00000001/sig000000f3/CY0F_12338 ),
.IB(\i3/blk00000001/sig000000f3/CY0F_12338 ),
.SEL(\i3/blk00000001/sig000000f3/CYSELF_12326 ),
.O(\i3/blk00000001/sig000000f3/CYMUXF2_12321 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYINIT (
.I(\i3/blk00000001/sig00000099 ),
.O(\i3/blk00000001/sig000000f3/CYINIT_12339 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CY0F (
.I(\i3/blk00000001/sig00000131 ),
.O(\i3/blk00000001/sig000000f3/CY0F_12338 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYSELF (
.I(\i3/blk00000001/sig00000098 ),
.O(\i3/blk00000001/sig000000f3/CYSELF_12326 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/YUSED (
.I(\i3/blk00000001/sig000000f3/XORG_12328 ),
.O(\i3/blk00000001/sig000000f4 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/XORG (
.I0(\i3/blk00000001/sig00000097 ),
.I1(\i3/blk00000001/sig00000096 ),
.O(\i3/blk00000001/sig000000f3/XORG_12328 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/COUTUSED (
.I(\i3/blk00000001/sig000000f3/CYMUXFAST_12325 ),
.O(\i3/blk00000001/sig00000095 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/FASTCARRY (
.I(\i3/blk00000001/sig00000099 ),
.O(\i3/blk00000001/sig000000f3/FASTCARRY_12323 )
);
X_AND2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYAND (
.I0(\i3/blk00000001/sig000000f3/CYSELG_12312 ),
.I1(\i3/blk00000001/sig000000f3/CYSELF_12326 ),
.O(\i3/blk00000001/sig000000f3/CYAND_12324 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYMUXFAST (
.IA(\i3/blk00000001/sig000000f3/CYMUXG2_12322 ),
.IB(\i3/blk00000001/sig000000f3/FASTCARRY_12323 ),
.SEL(\i3/blk00000001/sig000000f3/CYAND_12324 ),
.O(\i3/blk00000001/sig000000f3/CYMUXFAST_12325 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYMUXG2 (
.IA(\i3/blk00000001/sig000000f3/CY0G_12320 ),
.IB(\i3/blk00000001/sig000000f3/CYMUXF2_12321 ),
.SEL(\i3/blk00000001/sig000000f3/CYSELG_12312 ),
.O(\i3/blk00000001/sig000000f3/CYMUXG2_12322 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CY0G (
.I(\i3/blk00000001/sig00000126 ),
.O(\i3/blk00000001/sig000000f3/CY0G_12320 )
);
X_BUF #(
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/sig000000f3/CYSELG (
.I(\i3/blk00000001/sig00000096 ),
.O(\i3/blk00000001/sig000000f3/CYSELG_12312 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/XUSED (
.I(\i3/blk00000001/sig000000f5/XORF_12379 ),
.O(\i3/blk00000001/sig000000f5 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/XORF (
.I0(\i3/blk00000001/sig000000f5/CYINIT_12378 ),
.I1(\i3/blk00000001/sig00000094 ),
.O(\i3/blk00000001/sig000000f5/XORF_12379 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYMUXF (
.IA(\i3/blk00000001/sig000000f5/CY0F_12377 ),
.IB(\i3/blk00000001/sig000000f5/CYINIT_12378 ),
.SEL(\i3/blk00000001/sig000000f5/CYSELF_12365 ),
.O(\i3/blk00000001/sig00000093 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYMUXF2 (
.IA(\i3/blk00000001/sig000000f5/CY0F_12377 ),
.IB(\i3/blk00000001/sig000000f5/CY0F_12377 ),
.SEL(\i3/blk00000001/sig000000f5/CYSELF_12365 ),
.O(\i3/blk00000001/sig000000f5/CYMUXF2_12360 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYINIT (
.I(\i3/blk00000001/sig00000095 ),
.O(\i3/blk00000001/sig000000f5/CYINIT_12378 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CY0F (
.I(\i3/blk00000001/sig0000011b ),
.O(\i3/blk00000001/sig000000f5/CY0F_12377 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYSELF (
.I(\i3/blk00000001/sig00000094 ),
.O(\i3/blk00000001/sig000000f5/CYSELF_12365 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/YUSED (
.I(\i3/blk00000001/sig000000f5/XORG_12367 ),
.O(\i3/blk00000001/sig000000f6 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/XORG (
.I0(\i3/blk00000001/sig00000093 ),
.I1(\i3/blk00000001/sig00000092 ),
.O(\i3/blk00000001/sig000000f5/XORG_12367 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/FASTCARRY (
.I(\i3/blk00000001/sig00000095 ),
.O(\i3/blk00000001/sig000000f5/FASTCARRY_12362 )
);
X_AND2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYAND (
.I0(\i3/blk00000001/sig000000f5/CYSELG_12351 ),
.I1(\i3/blk00000001/sig000000f5/CYSELF_12365 ),
.O(\i3/blk00000001/sig000000f5/CYAND_12363 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYMUXFAST (
.IA(\i3/blk00000001/sig000000f5/CYMUXG2_12361 ),
.IB(\i3/blk00000001/sig000000f5/FASTCARRY_12362 ),
.SEL(\i3/blk00000001/sig000000f5/CYAND_12363 ),
.O(\i3/blk00000001/sig000000f5/CYMUXFAST_12364 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYMUXG2 (
.IA(\i3/blk00000001/sig000000f5/CY0G_12359 ),
.IB(\i3/blk00000001/sig000000f5/CYMUXF2_12360 ),
.SEL(\i3/blk00000001/sig000000f5/CYSELG_12351 ),
.O(\i3/blk00000001/sig000000f5/CYMUXG2_12361 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CY0G (
.I(\i3/blk00000001/sig00000110 ),
.O(\i3/blk00000001/sig000000f5/CY0G_12359 )
);
X_BUF #(
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/sig000000f5/CYSELG (
.I(\i3/blk00000001/sig00000092 ),
.O(\i3/blk00000001/sig000000f5/CYSELG_12351 )
);
X_BUF #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/XUSED (
.I(\i3/blk00000001/sig000000f7/XORF_12410 ),
.O(\i3/blk00000001/sig000000f7 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/XORF (
.I0(\i3/blk00000001/sig000000f7/CYINIT_12409 ),
.I1(\i3/blk00000001/sig00000090 ),
.O(\i3/blk00000001/sig000000f7/XORF_12410 )
);
X_MUX2 #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/CYMUXF (
.IA(\i3/blk00000001/sig000000f7/CY0F_12408 ),
.IB(\i3/blk00000001/sig000000f7/CYINIT_12409 ),
.SEL(\i3/blk00000001/sig000000f7/CYSELF_12400 ),
.O(\i3/blk00000001/sig0000008f )
);
X_BUF #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/CYINIT (
.I(\i3/blk00000001/sig000000f5/CYMUXFAST_12364 ),
.O(\i3/blk00000001/sig000000f7/CYINIT_12409 )
);
X_BUF #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/CY0F (
.I(\i3/blk00000001/sig00000110 ),
.O(\i3/blk00000001/sig000000f7/CY0F_12408 )
);
X_BUF #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/CYSELF (
.I(\i3/blk00000001/sig00000090 ),
.O(\i3/blk00000001/sig000000f7/CYSELF_12400 )
);
X_BUF #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/YUSED (
.I(\i3/blk00000001/sig000000f7/XORG_12397 ),
.O(\i3/blk00000001/sig000000f8 )
);
X_XOR2 #(
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/sig000000f7/XORG (
.I0(\i3/blk00000001/sig0000008f ),
.I1(\i3/blk00000001/sig0000008e ),
.O(\i3/blk00000001/sig000000f7/XORG_12397 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CYMUXF (
.IA(\i3/blk00000001/sig000000c0/CY0F_12440 ),
.IB(\i3/blk00000001/sig000000c0/CYINIT_12441 ),
.SEL(\i3/blk00000001/sig000000c0/CYSELF_12432 ),
.O(\i3/blk00000001/sig000000c2 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CYINIT (
.I(\i3/blk00000001/sig000000c0/BXINV_12430 ),
.O(\i3/blk00000001/sig000000c0/CYINIT_12441 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CY0F (
.I(\i3/blk00000001/sig00000192 ),
.O(\i3/blk00000001/sig000000c0/CY0F_12440 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CYSELF (
.I(\i3/blk00000001/sig000000c3 ),
.O(\i3/blk00000001/sig000000c0/CYSELF_12432 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/BXINV (
.I(1'b0),
.O(\i3/blk00000001/sig000000c0/BXINV_12430 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/COUTUSED (
.I(\i3/blk00000001/sig000000c0/CYMUXG_12429 ),
.O(\i3/blk00000001/sig000000c0 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CYMUXG (
.IA(\i3/blk00000001/sig000000c0/CY0G_12427 ),
.IB(\i3/blk00000001/sig000000c2 ),
.SEL(\i3/blk00000001/sig000000c0/CYSELG_12419 ),
.O(\i3/blk00000001/sig000000c0/CYMUXG_12429 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CY0G (
.I(\i3/blk00000001/sig00000182 ),
.O(\i3/blk00000001/sig000000c0/CY0G_12427 )
);
X_BUF #(
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/sig000000c0/CYSELG (
.I(\i3/blk00000001/sig000000c1 ),
.O(\i3/blk00000001/sig000000c0/CYSELG_12419 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/XUSED (
.I(\i3/blk00000001/sig000000f9/XORF_12479 ),
.O(\i3/blk00000001/sig000000f9 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/XORF (
.I0(\i3/blk00000001/sig000000f9/CYINIT_12478 ),
.I1(\i3/blk00000001/sig000000bf ),
.O(\i3/blk00000001/sig000000f9/XORF_12479 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYMUXF (
.IA(\i3/blk00000001/sig000000f9/CY0F_12477 ),
.IB(\i3/blk00000001/sig000000f9/CYINIT_12478 ),
.SEL(\i3/blk00000001/sig000000f9/CYSELF_12465 ),
.O(\i3/blk00000001/sig000000be )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYMUXF2 (
.IA(\i3/blk00000001/sig000000f9/CY0F_12477 ),
.IB(\i3/blk00000001/sig000000f9/CY0F_12477 ),
.SEL(\i3/blk00000001/sig000000f9/CYSELF_12465 ),
.O(\i3/blk00000001/sig000000f9/CYMUXF2_12460 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYINIT (
.I(\i3/blk00000001/sig000000c0 ),
.O(\i3/blk00000001/sig000000f9/CYINIT_12478 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CY0F (
.I(\i3/blk00000001/sig00000177 ),
.O(\i3/blk00000001/sig000000f9/CY0F_12477 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYSELF (
.I(\i3/blk00000001/sig000000bf ),
.O(\i3/blk00000001/sig000000f9/CYSELF_12465 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/YUSED (
.I(\i3/blk00000001/sig000000f9/XORG_12467 ),
.O(\i3/blk00000001/sig000000fa )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/XORG (
.I0(\i3/blk00000001/sig000000be ),
.I1(\i3/blk00000001/sig000000bd ),
.O(\i3/blk00000001/sig000000f9/XORG_12467 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/COUTUSED (
.I(\i3/blk00000001/sig000000f9/CYMUXFAST_12464 ),
.O(\i3/blk00000001/sig000000bc )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/FASTCARRY (
.I(\i3/blk00000001/sig000000c0 ),
.O(\i3/blk00000001/sig000000f9/FASTCARRY_12462 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYAND (
.I0(\i3/blk00000001/sig000000f9/CYSELG_12451 ),
.I1(\i3/blk00000001/sig000000f9/CYSELF_12465 ),
.O(\i3/blk00000001/sig000000f9/CYAND_12463 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYMUXFAST (
.IA(\i3/blk00000001/sig000000f9/CYMUXG2_12461 ),
.IB(\i3/blk00000001/sig000000f9/FASTCARRY_12462 ),
.SEL(\i3/blk00000001/sig000000f9/CYAND_12463 ),
.O(\i3/blk00000001/sig000000f9/CYMUXFAST_12464 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYMUXG2 (
.IA(\i3/blk00000001/sig000000f9/CY0G_12459 ),
.IB(\i3/blk00000001/sig000000f9/CYMUXF2_12460 ),
.SEL(\i3/blk00000001/sig000000f9/CYSELG_12451 ),
.O(\i3/blk00000001/sig000000f9/CYMUXG2_12461 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CY0G (
.I(\i3/blk00000001/sig0000016c ),
.O(\i3/blk00000001/sig000000f9/CY0G_12459 )
);
X_BUF #(
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/sig000000f9/CYSELG (
.I(\i3/blk00000001/sig000000bd ),
.O(\i3/blk00000001/sig000000f9/CYSELG_12451 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/XUSED (
.I(\i3/blk00000001/sig000000fb/XORF_12518 ),
.O(\i3/blk00000001/sig000000fb )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/XORF (
.I0(\i3/blk00000001/sig000000fb/CYINIT_12517 ),
.I1(\i3/blk00000001/sig000000bb ),
.O(\i3/blk00000001/sig000000fb/XORF_12518 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYMUXF (
.IA(\i3/blk00000001/sig000000fb/CY0F_12516 ),
.IB(\i3/blk00000001/sig000000fb/CYINIT_12517 ),
.SEL(\i3/blk00000001/sig000000fb/CYSELF_12504 ),
.O(\i3/blk00000001/sig000000ba )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYMUXF2 (
.IA(\i3/blk00000001/sig000000fb/CY0F_12516 ),
.IB(\i3/blk00000001/sig000000fb/CY0F_12516 ),
.SEL(\i3/blk00000001/sig000000fb/CYSELF_12504 ),
.O(\i3/blk00000001/sig000000fb/CYMUXF2_12499 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYINIT (
.I(\i3/blk00000001/sig000000bc ),
.O(\i3/blk00000001/sig000000fb/CYINIT_12517 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CY0F (
.I(\i3/blk00000001/sig00000161 ),
.O(\i3/blk00000001/sig000000fb/CY0F_12516 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYSELF (
.I(\i3/blk00000001/sig000000bb ),
.O(\i3/blk00000001/sig000000fb/CYSELF_12504 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/YUSED (
.I(\i3/blk00000001/sig000000fb/XORG_12506 ),
.O(\i3/blk00000001/sig000000fc )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/XORG (
.I0(\i3/blk00000001/sig000000ba ),
.I1(\i3/blk00000001/sig000000b9 ),
.O(\i3/blk00000001/sig000000fb/XORG_12506 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/COUTUSED (
.I(\i3/blk00000001/sig000000fb/CYMUXFAST_12503 ),
.O(\i3/blk00000001/sig000000b8 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/FASTCARRY (
.I(\i3/blk00000001/sig000000bc ),
.O(\i3/blk00000001/sig000000fb/FASTCARRY_12501 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYAND (
.I0(\i3/blk00000001/sig000000fb/CYSELG_12490 ),
.I1(\i3/blk00000001/sig000000fb/CYSELF_12504 ),
.O(\i3/blk00000001/sig000000fb/CYAND_12502 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYMUXFAST (
.IA(\i3/blk00000001/sig000000fb/CYMUXG2_12500 ),
.IB(\i3/blk00000001/sig000000fb/FASTCARRY_12501 ),
.SEL(\i3/blk00000001/sig000000fb/CYAND_12502 ),
.O(\i3/blk00000001/sig000000fb/CYMUXFAST_12503 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYMUXG2 (
.IA(\i3/blk00000001/sig000000fb/CY0G_12498 ),
.IB(\i3/blk00000001/sig000000fb/CYMUXF2_12499 ),
.SEL(\i3/blk00000001/sig000000fb/CYSELG_12490 ),
.O(\i3/blk00000001/sig000000fb/CYMUXG2_12500 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CY0G (
.I(\i3/blk00000001/sig00000156 ),
.O(\i3/blk00000001/sig000000fb/CY0G_12498 )
);
X_BUF #(
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/sig000000fb/CYSELG (
.I(\i3/blk00000001/sig000000b9 ),
.O(\i3/blk00000001/sig000000fb/CYSELG_12490 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/XUSED (
.I(\i3/blk00000001/sig000000fd/XORF_12557 ),
.O(\i3/blk00000001/sig000000fd )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/XORF (
.I0(\i3/blk00000001/sig000000fd/CYINIT_12556 ),
.I1(\i3/blk00000001/sig000000b7 ),
.O(\i3/blk00000001/sig000000fd/XORF_12557 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYMUXF (
.IA(\i3/blk00000001/sig000000fd/CY0F_12555 ),
.IB(\i3/blk00000001/sig000000fd/CYINIT_12556 ),
.SEL(\i3/blk00000001/sig000000fd/CYSELF_12543 ),
.O(\i3/blk00000001/sig000000b6 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYMUXF2 (
.IA(\i3/blk00000001/sig000000fd/CY0F_12555 ),
.IB(\i3/blk00000001/sig000000fd/CY0F_12555 ),
.SEL(\i3/blk00000001/sig000000fd/CYSELF_12543 ),
.O(\i3/blk00000001/sig000000fd/CYMUXF2_12538 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYINIT (
.I(\i3/blk00000001/sig000000b8 ),
.O(\i3/blk00000001/sig000000fd/CYINIT_12556 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CY0F (
.I(\i3/blk00000001/sig0000014b ),
.O(\i3/blk00000001/sig000000fd/CY0F_12555 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYSELF (
.I(\i3/blk00000001/sig000000b7 ),
.O(\i3/blk00000001/sig000000fd/CYSELF_12543 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/YUSED (
.I(\i3/blk00000001/sig000000fd/XORG_12545 ),
.O(\i3/blk00000001/sig000000fe )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/XORG (
.I0(\i3/blk00000001/sig000000b6 ),
.I1(\i3/blk00000001/sig000000b5 ),
.O(\i3/blk00000001/sig000000fd/XORG_12545 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/COUTUSED (
.I(\i3/blk00000001/sig000000fd/CYMUXFAST_12542 ),
.O(\i3/blk00000001/sig000000b4 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/FASTCARRY (
.I(\i3/blk00000001/sig000000b8 ),
.O(\i3/blk00000001/sig000000fd/FASTCARRY_12540 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYAND (
.I0(\i3/blk00000001/sig000000fd/CYSELG_12529 ),
.I1(\i3/blk00000001/sig000000fd/CYSELF_12543 ),
.O(\i3/blk00000001/sig000000fd/CYAND_12541 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYMUXFAST (
.IA(\i3/blk00000001/sig000000fd/CYMUXG2_12539 ),
.IB(\i3/blk00000001/sig000000fd/FASTCARRY_12540 ),
.SEL(\i3/blk00000001/sig000000fd/CYAND_12541 ),
.O(\i3/blk00000001/sig000000fd/CYMUXFAST_12542 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYMUXG2 (
.IA(\i3/blk00000001/sig000000fd/CY0G_12537 ),
.IB(\i3/blk00000001/sig000000fd/CYMUXF2_12538 ),
.SEL(\i3/blk00000001/sig000000fd/CYSELG_12529 ),
.O(\i3/blk00000001/sig000000fd/CYMUXG2_12539 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CY0G (
.I(\i3/blk00000001/sig00000140 ),
.O(\i3/blk00000001/sig000000fd/CY0G_12537 )
);
X_BUF #(
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/sig000000fd/CYSELG (
.I(\i3/blk00000001/sig000000b5 ),
.O(\i3/blk00000001/sig000000fd/CYSELG_12529 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/XUSED (
.I(\i3/blk00000001/sig000000ff/XORF_12596 ),
.O(\i3/blk00000001/sig000000ff )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/XORF (
.I0(\i3/blk00000001/sig000000ff/CYINIT_12595 ),
.I1(\i3/blk00000001/sig000000b3 ),
.O(\i3/blk00000001/sig000000ff/XORF_12596 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYMUXF (
.IA(\i3/blk00000001/sig000000ff/CY0F_12594 ),
.IB(\i3/blk00000001/sig000000ff/CYINIT_12595 ),
.SEL(\i3/blk00000001/sig000000ff/CYSELF_12582 ),
.O(\i3/blk00000001/sig000000b2 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYMUXF2 (
.IA(\i3/blk00000001/sig000000ff/CY0F_12594 ),
.IB(\i3/blk00000001/sig000000ff/CY0F_12594 ),
.SEL(\i3/blk00000001/sig000000ff/CYSELF_12582 ),
.O(\i3/blk00000001/sig000000ff/CYMUXF2_12577 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYINIT (
.I(\i3/blk00000001/sig000000b4 ),
.O(\i3/blk00000001/sig000000ff/CYINIT_12595 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CY0F (
.I(\i3/blk00000001/sig00000135 ),
.O(\i3/blk00000001/sig000000ff/CY0F_12594 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYSELF (
.I(\i3/blk00000001/sig000000b3 ),
.O(\i3/blk00000001/sig000000ff/CYSELF_12582 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/YUSED (
.I(\i3/blk00000001/sig000000ff/XORG_12584 ),
.O(\i3/blk00000001/sig00000100 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/XORG (
.I0(\i3/blk00000001/sig000000b2 ),
.I1(\i3/blk00000001/sig000000b1 ),
.O(\i3/blk00000001/sig000000ff/XORG_12584 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/COUTUSED (
.I(\i3/blk00000001/sig000000ff/CYMUXFAST_12581 ),
.O(\i3/blk00000001/sig000000b0 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/FASTCARRY (
.I(\i3/blk00000001/sig000000b4 ),
.O(\i3/blk00000001/sig000000ff/FASTCARRY_12579 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYAND (
.I0(\i3/blk00000001/sig000000ff/CYSELG_12568 ),
.I1(\i3/blk00000001/sig000000ff/CYSELF_12582 ),
.O(\i3/blk00000001/sig000000ff/CYAND_12580 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYMUXFAST (
.IA(\i3/blk00000001/sig000000ff/CYMUXG2_12578 ),
.IB(\i3/blk00000001/sig000000ff/FASTCARRY_12579 ),
.SEL(\i3/blk00000001/sig000000ff/CYAND_12580 ),
.O(\i3/blk00000001/sig000000ff/CYMUXFAST_12581 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYMUXG2 (
.IA(\i3/blk00000001/sig000000ff/CY0G_12576 ),
.IB(\i3/blk00000001/sig000000ff/CYMUXF2_12577 ),
.SEL(\i3/blk00000001/sig000000ff/CYSELG_12568 ),
.O(\i3/blk00000001/sig000000ff/CYMUXG2_12578 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CY0G (
.I(\i3/blk00000001/sig0000012a ),
.O(\i3/blk00000001/sig000000ff/CY0G_12576 )
);
X_BUF #(
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/sig000000ff/CYSELG (
.I(\i3/blk00000001/sig000000b1 ),
.O(\i3/blk00000001/sig000000ff/CYSELG_12568 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/XUSED (
.I(\i3/blk00000001/sig00000101/XORF_12635 ),
.O(\i3/blk00000001/sig00000101 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/XORF (
.I0(\i3/blk00000001/sig00000101/CYINIT_12634 ),
.I1(\i3/blk00000001/sig000000af ),
.O(\i3/blk00000001/sig00000101/XORF_12635 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYMUXF (
.IA(\i3/blk00000001/sig00000101/CY0F_12633 ),
.IB(\i3/blk00000001/sig00000101/CYINIT_12634 ),
.SEL(\i3/blk00000001/sig00000101/CYSELF_12621 ),
.O(\i3/blk00000001/sig000000ae )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYMUXF2 (
.IA(\i3/blk00000001/sig00000101/CY0F_12633 ),
.IB(\i3/blk00000001/sig00000101/CY0F_12633 ),
.SEL(\i3/blk00000001/sig00000101/CYSELF_12621 ),
.O(\i3/blk00000001/sig00000101/CYMUXF2_12616 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYINIT (
.I(\i3/blk00000001/sig000000b0 ),
.O(\i3/blk00000001/sig00000101/CYINIT_12634 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CY0F (
.I(\i3/blk00000001/sig0000011f ),
.O(\i3/blk00000001/sig00000101/CY0F_12633 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYSELF (
.I(\i3/blk00000001/sig000000af ),
.O(\i3/blk00000001/sig00000101/CYSELF_12621 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/YUSED (
.I(\i3/blk00000001/sig00000101/XORG_12623 ),
.O(\i3/blk00000001/sig00000102 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/XORG (
.I0(\i3/blk00000001/sig000000ae ),
.I1(\i3/blk00000001/sig000000ad ),
.O(\i3/blk00000001/sig00000101/XORG_12623 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/FASTCARRY (
.I(\i3/blk00000001/sig000000b0 ),
.O(\i3/blk00000001/sig00000101/FASTCARRY_12618 )
);
X_AND2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYAND (
.I0(\i3/blk00000001/sig00000101/CYSELG_12607 ),
.I1(\i3/blk00000001/sig00000101/CYSELF_12621 ),
.O(\i3/blk00000001/sig00000101/CYAND_12619 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYMUXFAST (
.IA(\i3/blk00000001/sig00000101/CYMUXG2_12617 ),
.IB(\i3/blk00000001/sig00000101/FASTCARRY_12618 ),
.SEL(\i3/blk00000001/sig00000101/CYAND_12619 ),
.O(\i3/blk00000001/sig00000101/CYMUXFAST_12620 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYMUXG2 (
.IA(\i3/blk00000001/sig00000101/CY0G_12615 ),
.IB(\i3/blk00000001/sig00000101/CYMUXF2_12616 ),
.SEL(\i3/blk00000001/sig00000101/CYSELG_12607 ),
.O(\i3/blk00000001/sig00000101/CYMUXG2_12617 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CY0G (
.I(\i3/blk00000001/sig00000114 ),
.O(\i3/blk00000001/sig00000101/CY0G_12615 )
);
X_BUF #(
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/sig00000101/CYSELG (
.I(\i3/blk00000001/sig000000ad ),
.O(\i3/blk00000001/sig00000101/CYSELG_12607 )
);
X_BUF #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/XUSED (
.I(\i3/blk00000001/sig00000103/XORF_12666 ),
.O(\i3/blk00000001/sig00000103 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/XORF (
.I0(\i3/blk00000001/sig00000103/CYINIT_12665 ),
.I1(\i3/blk00000001/sig000000ab ),
.O(\i3/blk00000001/sig00000103/XORF_12666 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/CYMUXF (
.IA(\i3/blk00000001/sig00000103/CY0F_12664 ),
.IB(\i3/blk00000001/sig00000103/CYINIT_12665 ),
.SEL(\i3/blk00000001/sig00000103/CYSELF_12656 ),
.O(\i3/blk00000001/sig000000aa )
);
X_BUF #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/CYINIT (
.I(\i3/blk00000001/sig00000101/CYMUXFAST_12620 ),
.O(\i3/blk00000001/sig00000103/CYINIT_12665 )
);
X_BUF #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/CY0F (
.I(\i3/blk00000001/sig00000114 ),
.O(\i3/blk00000001/sig00000103/CY0F_12664 )
);
X_BUF #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/CYSELF (
.I(\i3/blk00000001/sig000000ab ),
.O(\i3/blk00000001/sig00000103/CYSELF_12656 )
);
X_BUF #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/YUSED (
.I(\i3/blk00000001/sig00000103/XORG_12653 ),
.O(\i3/blk00000001/sig00000104 )
);
X_XOR2 #(
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/sig00000103/XORG (
.I0(\i3/blk00000001/sig000000aa ),
.I1(\i3/blk00000001/sig000000a9 ),
.O(\i3/blk00000001/sig00000103/XORG_12653 )
);
X_OPAD #(
.LOC ( "PAD102" ))
\y<0>/PAD (
.PAD(y[0])
);
X_OBUF #(
.LOC ( "PAD102" ))
y_0_OBUF (
.I(\y<0>/O ),
.O(y[0])
);
X_OPAD #(
.LOC ( "PAD101" ))
\y<1>/PAD (
.PAD(y[1])
);
X_OBUF #(
.LOC ( "PAD101" ))
y_1_OBUF (
.I(\y<1>/O ),
.O(y[1])
);
X_OPAD #(
.LOC ( "PAD91" ))
\y<2>/PAD (
.PAD(y[2])
);
X_OBUF #(
.LOC ( "PAD91" ))
y_2_OBUF (
.I(\y<2>/O ),
.O(y[2])
);
X_OPAD #(
.LOC ( "PAD97" ))
\y<3>/PAD (
.PAD(y[3])
);
X_OBUF #(
.LOC ( "PAD97" ))
y_3_OBUF (
.I(\y<3>/O ),
.O(y[3])
);
X_OPAD #(
.LOC ( "PAD92" ))
\y<4>/PAD (
.PAD(y[4])
);
X_OBUF #(
.LOC ( "PAD92" ))
y_4_OBUF (
.I(\y<4>/O ),
.O(y[4])
);
X_OPAD #(
.LOC ( "PAD99" ))
\y<5>/PAD (
.PAD(y[5])
);
X_OBUF #(
.LOC ( "PAD99" ))
y_5_OBUF (
.I(\y<5>/O ),
.O(y[5])
);
X_OPAD #(
.LOC ( "PAD98" ))
\y<6>/PAD (
.PAD(y[6])
);
X_OBUF #(
.LOC ( "PAD98" ))
y_6_OBUF (
.I(\y<6>/O ),
.O(y[6])
);
X_OPAD #(
.LOC ( "PAD37" ))
\y<7>/PAD (
.PAD(y[7])
);
X_OBUF #(
.LOC ( "PAD37" ))
y_7_OBUF (
.I(\y<7>/O ),
.O(y[7])
);
X_OPAD #(
.LOC ( "PAD18" ))
\y<8>/PAD (
.PAD(y[8])
);
X_OBUF #(
.LOC ( "PAD18" ))
y_8_OBUF (
.I(\y<8>/O ),
.O(y[8])
);
X_OPAD #(
.LOC ( "PAD35" ))
\y<9>/PAD (
.PAD(y[9])
);
X_OBUF #(
.LOC ( "PAD35" ))
y_9_OBUF (
.I(\y<9>/O ),
.O(y[9])
);
X_IPAD #(
.LOC ( "PAD79" ))
\x1<0>/PAD (
.PAD(x1[0])
);
X_BUF #(
.LOC ( "PAD79" ))
x1_0_IBUF (
.I(x1[0]),
.O(\x1<0>/INBUF )
);
X_IPAD #(
.LOC ( "PAD78" ))
\x1<1>/PAD (
.PAD(x1[1])
);
X_BUF #(
.LOC ( "PAD78" ))
x1_1_IBUF (
.I(x1[1]),
.O(\x1<1>/INBUF )
);
X_BUF #(
.LOC ( "PAD76" ))
\x1<2>/IFF/IMUX (
.I(\x1<2>/INBUF ),
.O(x1_2_IBUF_3399)
);
X_IPAD #(
.LOC ( "PAD76" ))
\x1<2>/PAD (
.PAD(x1[2])
);
X_BUF #(
.LOC ( "PAD76" ))
x1_2_IBUF (
.I(x1[2]),
.O(\x1<2>/INBUF )
);
X_BUF #(
.LOC ( "PAD75" ))
\x1<3>/IFF/IMUX (
.I(\x1<3>/INBUF ),
.O(x1_3_IBUF_3400)
);
X_IPAD #(
.LOC ( "PAD75" ))
\x1<3>/PAD (
.PAD(x1[3])
);
X_BUF #(
.LOC ( "PAD75" ))
x1_3_IBUF (
.I(x1[3]),
.O(\x1<3>/INBUF )
);
X_BUF #(
.LOC ( "PAD103" ))
\x2<0>/IFF/IMUX (
.I(\x2<0>/INBUF ),
.O(x2_0_IBUF_3076)
);
X_IPAD #(
.LOC ( "PAD103" ))
\x2<0>/PAD (
.PAD(x2[0])
);
X_BUF #(
.LOC ( "PAD103" ))
x2_0_IBUF (
.I(x2[0]),
.O(\x2<0>/INBUF )
);
X_BUF #(
.LOC ( "PAD70" ))
\x1<4>/IFF/IMUX (
.I(\x1<4>/INBUF ),
.O(x1_4_IBUF_3359)
);
X_IPAD #(
.LOC ( "PAD70" ))
\x1<4>/PAD (
.PAD(x1[4])
);
X_BUF #(
.LOC ( "PAD70" ))
x1_4_IBUF (
.I(x1[4]),
.O(\x1<4>/INBUF )
);
X_BUF #(
.LOC ( "PAD96" ))
\x2<1>/IFF/IMUX (
.I(\x2<1>/INBUF ),
.O(x2_1_IBUF_3077)
);
X_IPAD #(
.LOC ( "PAD96" ))
\x2<1>/PAD (
.PAD(x2[1])
);
X_BUF #(
.LOC ( "PAD96" ))
x2_1_IBUF (
.I(x2[1]),
.O(\x2<1>/INBUF )
);
X_BUF #(
.LOC ( "IPAD73" ))
\x1<5>/IFF/IMUX (
.I(\x1<5>/INBUF ),
.O(x1_5_IBUF_3360)
);
X_IPAD #(
.LOC ( "IPAD73" ))
\x1<5>/PAD (
.PAD(x1[5])
);
X_BUF #(
.LOC ( "IPAD73" ))
x1_5_IBUF (
.I(x1[5]),
.O(\x1<5>/INBUF )
);
X_BUF #(
.LOC ( "IPAD100" ))
\x2<2>/IFF/IMUX (
.I(\x2<2>/INBUF ),
.O(x2_2_IBUF_3138)
);
X_IPAD #(
.LOC ( "IPAD100" ))
\x2<2>/PAD (
.PAD(x2[2])
);
X_BUF #(
.LOC ( "IPAD100" ))
x2_2_IBUF (
.I(x2[2]),
.O(\x2<2>/INBUF )
);
X_BUF #(
.LOC ( "PAD71" ))
\x1<6>/IFF/IMUX (
.I(\x1<6>/INBUF ),
.O(x1_6_IBUF_3317)
);
X_IPAD #(
.LOC ( "PAD71" ))
\x1<6>/PAD (
.PAD(x1[6])
);
X_BUF #(
.LOC ( "PAD71" ))
x1_6_IBUF (
.I(x1[6]),
.O(\x1<6>/INBUF )
);
X_BUF #(
.LOC ( "PAD84" ))
\x2<3>/IFF/IMUX (
.I(\x2<3>/INBUF ),
.O(x2_3_IBUF_3139)
);
X_IPAD #(
.LOC ( "PAD84" ))
\x2<3>/PAD (
.PAD(x2[3])
);
X_BUF #(
.LOC ( "PAD84" ))
x2_3_IBUF (
.I(x2[3]),
.O(\x2<3>/INBUF )
);
X_BUF #(
.LOC ( "PAD72" ))
\x1<7>/IFF/IMUX (
.I(\x1<7>/INBUF ),
.O(x1_7_IBUF_3318)
);
X_IPAD #(
.LOC ( "PAD72" ))
\x1<7>/PAD (
.PAD(x1[7])
);
X_BUF #(
.LOC ( "PAD72" ))
x1_7_IBUF (
.I(x1[7]),
.O(\x1<7>/INBUF )
);
X_BUF #(
.LOC ( "PAD64" ))
\x3<0>/IFF/IMUX (
.I(\x3<0>/INBUF ),
.O(x3_0_IBUF_3549)
);
X_IPAD #(
.LOC ( "PAD64" ))
\x3<0>/PAD (
.PAD(x3[0])
);
X_BUF #(
.LOC ( "PAD64" ))
x3_0_IBUF (
.I(x3[0]),
.O(\x3<0>/INBUF )
);
X_IPAD #(
.LOC ( "IPAD3" ))
\x2<4>/PAD (
.PAD(x2[4])
);
X_BUF #(
.LOC ( "IPAD3" ))
x2_4_IBUF (
.I(x2[4]),
.O(\x2<4>/INBUF )
);
X_IPAD #(
.LOC ( "IPAD66" ))
\x1<8>/PAD (
.PAD(x1[8])
);
X_BUF #(
.LOC ( "IPAD66" ))
x1_8_IBUF (
.I(x1[8]),
.O(\x1<8>/INBUF )
);
X_BUF #(
.LOC ( "IPAD66" ))
\x1<8>/IFF/IMUX (
.I(\x1<8>/INBUF ),
.O(x1_8_IBUF_3311)
);
X_IPAD #(
.LOC ( "PAD69" ))
\x3<1>/PAD (
.PAD(x3[1])
);
X_BUF #(
.LOC ( "PAD69" ))
x3_1_IBUF (
.I(x3[1]),
.O(\x3<1>/INBUF )
);
X_BUF #(
.LOC ( "PAD69" ))
\x3<1>/IFF/IMUX (
.I(\x3<1>/INBUF ),
.O(x3_1_IBUF_3550)
);
X_IPAD #(
.LOC ( "PAD82" ))
\x2<5>/PAD (
.PAD(x2[5])
);
X_BUF #(
.LOC ( "PAD82" ))
x2_5_IBUF (
.I(x2[5]),
.O(\x2<5>/INBUF )
);
X_BUF #(
.LOC ( "PAD82" ))
\x2<5>/IFF/IMUX (
.I(\x2<5>/INBUF ),
.O(x2_5_IBUF_3099)
);
X_IPAD #(
.LOC ( "PAD68" ))
\x1<9>/PAD (
.PAD(x1[9])
);
X_BUF #(
.LOC ( "PAD68" ))
x1_9_IBUF (
.I(x1[9]),
.O(\x1<9>/INBUF )
);
X_BUF #(
.LOC ( "PAD68" ))
\x1<9>/IFF/IMUX (
.I(\x1<9>/INBUF ),
.O(x1_9_IBUF_3312)
);
X_IPAD #(
.LOC ( "PAD65" ))
\x3<2>/PAD (
.PAD(x3[2])
);
X_BUF #(
.LOC ( "PAD65" ))
x3_2_IBUF (
.I(x3[2]),
.O(\x3<2>/INBUF )
);
X_BUF #(
.LOC ( "PAD65" ))
\x3<2>/IFF/IMUX (
.I(\x3<2>/INBUF ),
.O(x3_2_IBUF_3611)
);
X_IPAD #(
.LOC ( "IPAD86" ))
\x2<6>/PAD (
.PAD(x2[6])
);
X_BUF #(
.LOC ( "IPAD86" ))
x2_6_IBUF (
.I(x2[6]),
.O(\x2<6>/INBUF )
);
X_BUF #(
.LOC ( "IPAD86" ))
\x2<6>/IFF/IMUX (
.I(\x2<6>/INBUF ),
.O(x2_6_IBUF_3056)
);
X_IPAD #(
.LOC ( "IPAD67" ))
\x3<3>/PAD (
.PAD(x3[3])
);
X_BUF #(
.LOC ( "IPAD67" ))
x3_3_IBUF (
.I(x3[3]),
.O(\x3<3>/INBUF )
);
X_IPAD #(
.LOC ( "PAD83" ))
\x2<7>/PAD (
.PAD(x2[7])
);
X_BUF #(
.LOC ( "PAD83" ))
x2_7_IBUF (
.I(x2[7]),
.O(\x2<7>/INBUF )
);
X_BUF #(
.LOC ( "PAD83" ))
\x2<7>/IFF/IMUX (
.I(\x2<7>/INBUF ),
.O(x2_7_IBUF_3057)
);
X_IPAD #(
.LOC ( "PAD63" ))
\x3<4>/PAD (
.PAD(x3[4])
);
X_BUF #(
.LOC ( "PAD63" ))
x3_4_IBUF (
.I(x3[4]),
.O(\x3<4>/INBUF )
);
X_IPAD #(
.LOC ( "PAD87" ))
\x2<8>/PAD (
.PAD(x2[8])
);
X_BUF #(
.LOC ( "PAD87" ))
x2_8_IBUF (
.I(x2[8]),
.O(\x2<8>/INBUF )
);
X_IPAD #(
.LOC ( "PAD62" ))
\x3<5>/PAD (
.PAD(x3[5])
);
X_BUF #(
.LOC ( "PAD62" ))
x3_5_IBUF (
.I(x3[5]),
.O(\x3<5>/INBUF )
);
X_IPAD #(
.LOC ( "PAD85" ))
\x2<9>/PAD (
.PAD(x2[9])
);
X_BUF #(
.LOC ( "PAD85" ))
x2_9_IBUF (
.I(x2[9]),
.O(\x2<9>/INBUF )
);
X_IPAD #(
.LOC ( "IPAD60" ))
\x3<6>/PAD (
.PAD(x3[6])
);
X_BUF #(
.LOC ( "IPAD60" ))
x3_6_IBUF (
.I(x3[6]),
.O(\x3<6>/INBUF )
);
X_IPAD #(
.LOC ( "PAD61" ))
\x3<7>/PAD (
.PAD(x3[7])
);
X_BUF #(
.LOC ( "PAD61" ))
x3_7_IBUF (
.I(x3[7]),
.O(\x3<7>/INBUF )
);
X_IPAD #(
.LOC ( "PAD42" ))
\x3<8>/PAD (
.PAD(x3[8])
);
X_BUF #(
.LOC ( "PAD42" ))
x3_8_IBUF (
.I(x3[8]),
.O(\x3<8>/INBUF )
);
X_IPAD #(
.LOC ( "PAD58" ))
\x3<9>/PAD (
.PAD(x3[9])
);
X_BUF #(
.LOC ( "PAD58" ))
x3_9_IBUF (
.I(x3[9]),
.O(\x3<9>/INBUF )
);
X_BUF #(
.LOC ( "SLICE_X22Y31" ))
\N10/XUSED (
.I(N10),
.O(N10_0)
);
X_BUF #(
.LOC ( "SLICE_X21Y25" ))
\Madd_s2C/XUSED (
.I(Madd_s2C),
.O(Madd_s2C_0)
);
X_BUF #(
.LOC ( "SLICE_X21Y27" ))
\Madd_s2C1/XUSED (
.I(Madd_s2C1_12961),
.O(Madd_s2C1_0)
);
X_BUF #(
.LOC ( "SLICE_X23Y27" ))
\Madd_s2C2/XUSED (
.I(Madd_s2C2),
.O(Madd_s2C2_0)
);
X_BUF #(
.LOC ( "SLICE_X21Y26" ))
\Madd_s2C3/XUSED (
.I(Madd_s2C3),
.O(Madd_s2C3_0)
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\Madd_s2C4/XUSED (
.I(Madd_s2C4),
.O(Madd_s2C4_0)
);
X_BUF #(
.LOC ( "SLICE_X18Y29" ))
\Madd_s2C5/XUSED (
.I(Madd_s2C5),
.O(Madd_s2C5_0)
);
X_BUF #(
.LOC ( "SLICE_X22Y28" ))
\Madd_s2C6/XUSED (
.I(Madd_s2C6),
.O(Madd_s2C6_0)
);
X_BUF #(
.LOC ( "SLICE_X21Y28" ))
\Madd_s2C7/XUSED (
.I(Madd_s2C7),
.O(Madd_s2C7_0)
);
X_BUF #(
.LOC ( "SLICE_X22Y29" ))
\Madd_s2C8/XUSED (
.I(Madd_s2C8),
.O(Madd_s2C8_0)
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/blk0000013c (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000101 ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000000f1 ),
.O(\i2/blk00000001/sig00000062 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/blk00000127 (
.ADR0(\i2/blk00000001/sig00000104 ),
.ADR1(\i2/blk00000001/sig000000f8 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000054 )
);
X_LUT4 #(
.INIT ( 16'h0F0F ),
.LOC ( "SLICE_X3Y31" ))
\i2/blk00000001/blk000001d1 (
.ADR0(x2_8_IBUF_3048),
.ADR1(GND),
.ADR2(x2_9_IBUF_3049),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000e0 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y27" ))
\i2/blk00000001/blk0000016e (
.ADR0(\i2/blk00000001/sig0000014e ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000158 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000083 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/blk00000177 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig0000016f ),
.ADR2(\i2/blk00000001/sig00000179 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000089 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X17Y26" ))
\i2/blk00000001/blk00000174 (
.ADR0(\i2/blk00000001/sig0000016e ),
.ADR1(\i2/blk00000001/sig00000164 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000087 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/blk0000017d (
.ADR0(\i2/blk00000001/sig00000186 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000185 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000008d )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y25" ))
\i2/blk00000001/blk0000017a (
.ADR0(\i2/blk00000001/sig0000017a ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000184 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000008b )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y28" ))
\Madd_s2_Madd_lut<6> (
.ADR0(t2[17]),
.ADR1(Madd_s2C4_0),
.ADR2(t3[17]),
.ADR3(t1[17]),
.O(\Madd_s2_Madd_lut[6] )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y28" ))
\Madd_s2_Madd_lut<7> (
.ADR0(Madd_s2C5_0),
.ADR1(t2[18]),
.ADR2(t3[18]),
.ADR3(t1[18]),
.O(\Madd_s2_Madd_lut[7] )
);
X_LUT4 #(
.INIT ( 16'h6996 ),
.LOC ( "SLICE_X19Y27" ))
\Madd_s2_Madd_lut<4> (
.ADR0(Madd_s2C2_0),
.ADR1(t2[15]),
.ADR2(t1[15]),
.ADR3(t3[15]),
.O(\Madd_s2_Madd_lut[4] )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/blk000001f4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(VCC),
.ADR2(x1_4_IBUF_3359),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000011a )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X13Y11" ))
\i1/blk00000001/blk0000019d (
.ADR0(\i1/blk00000001/sig00000168 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig0000017c ),
.O(\i1/blk00000001/sig000000a2 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/blk000001a6 (
.ADR0(\i1/blk00000001/sig0000018c ),
.ADR1(\i1/blk00000001/sig000001dd ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000a8 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X13Y10" ))
\i1/blk00000001/blk000001a3 (
.ADR0(\i1/blk00000001/sig0000017e ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig0000018b ),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000a6 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X19Y17" ))
\i1/blk00000001/blk00000159 (
.ADR0(\i1/blk00000001/sig0000010c ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig0000010b ),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000075 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/blk00000185 (
.ADR0(\i1/blk00000001/sig00000110 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000124 ),
.O(\i1/blk00000001/sig00000092 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y19" ))
\i3/blk00000001/blk0000012d (
.ADR0(\i3/blk00000001/sig00000104 ),
.ADR1(\i3/blk00000001/sig000000f6 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000058 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/blk00000136 (
.ADR0(\i3/blk00000001/sig000000f3 ),
.ADR1(\i3/blk00000001/sig00000103 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000005e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y18" ))
\i3/blk00000001/blk00000133 (
.ADR0(\i3/blk00000001/sig000000f4 ),
.ADR1(\i3/blk00000001/sig00000104 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000005c )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/blk00000201 (
.ADR0(x3_3_IBUF_3612),
.ADR1(VCC),
.ADR2(x3_2_IBUF_3611),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000011c )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/blk00000168 (
.ADR0(\i3/blk00000001/sig00000138 ),
.ADR1(\i3/blk00000001/sig00000142 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000007f )
);
X_BUF #(
.LOC ( "IPAD67" ))
\x3<3>/IFF/IMUX (
.I(\x3<3>/INBUF ),
.O(x3_3_IBUF_3612)
);
X_BUF #(
.LOC ( "PAD78" ))
\x1<1>/IFF/IMUX (
.I(\x1<1>/INBUF ),
.O(x1_1_IBUF_3338)
);
X_BUF #(
.LOC ( "PAD79" ))
\x1<0>/IFF/IMUX (
.I(\x1<0>/INBUF ),
.O(x1_0_IBUF_3337)
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/blk0000011f (
.ADR0(\i2/blk00000001/sig000000d3 ),
.ADR1(\i2/blk00000001/sig00000188 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000004f )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X23Y28" ))
\i2/blk00000001/blk00000122 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000d2 ),
.ADR2(\i2/blk00000001/sig000001da ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000051 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y29" ))
\i2/blk00000001/blk00000119 (
.ADR0(\i2/blk00000001/sig000000d5 ),
.ADR1(\i2/blk00000001/sig000000c5 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000004b )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y29" ))
\i2/blk00000001/blk0000011c (
.ADR0(\i2/blk00000001/sig000000c4 ),
.ADR1(\i2/blk00000001/sig000000d4 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000004d )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y30" ))
\i2/blk00000001/blk00000113 (
.ADR0(\i2/blk00000001/sig000000d7 ),
.ADR1(\i2/blk00000001/sig000000c7 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000047 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y30" ))
\i2/blk00000001/blk00000116 (
.ADR0(\i2/blk00000001/sig000000c6 ),
.ADR1(\i2/blk00000001/sig000000d6 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000049 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X23Y31" ))
\i2/blk00000001/blk00000110 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000d8 ),
.ADR2(\i2/blk00000001/sig000000c8 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000045 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y32" ))
\i2/blk00000001/blk00000107 (
.ADR0(\i2/blk00000001/sig000000db ),
.ADR1(\i2/blk00000001/sig000000cb ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000003f )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y33" ))
\i2/blk00000001/blk00000101 (
.ADR0(\i2/blk00000001/sig000000cd ),
.ADR1(\i2/blk00000001/sig000000dd ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000003b )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X23Y33" ))
\i2/blk00000001/blk00000104 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000dc ),
.ADR2(\i2/blk00000001/sig000000cc ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000003d )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y34" ))
\i2/blk00000001/blk000000fb (
.ADR0(\i2/blk00000001/sig000000de ),
.ADR1(\i2/blk00000001/sig000000cf ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000037 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X23Y34" ))
\i2/blk00000001/blk000000fe (
.ADR0(\i2/blk00000001/sig000000de ),
.ADR1(\i2/blk00000001/sig000000ce ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000039 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/blk00000151 (
.ADR0(\i2/blk00000001/sig000000fa ),
.ADR1(\i2/blk00000001/sig0000018e ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000070 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y27" ))
\i2/blk00000001/blk00000154 (
.ADR0(\i2/blk00000001/sig000000f9 ),
.ADR1(\i2/blk00000001/sig000001e0 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000072 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y28" ))
\i2/blk00000001/blk0000014b (
.ADR0(\i2/blk00000001/sig000000ec ),
.ADR1(\i2/blk00000001/sig000000fc ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000006c )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/blk00000145 (
.ADR0(\i2/blk00000001/sig000000fe ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000000ee ),
.O(\i2/blk00000001/sig00000068 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X25Y29" ))
\i2/blk00000001/blk00000148 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000fd ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000000ed ),
.O(\i2/blk00000001/sig0000006a )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y30" ))
\i2/blk00000001/blk00000142 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig000000ff ),
.ADR2(\i2/blk00000001/sig000000ef ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000066 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X25Y31" ))
\i2/blk00000001/blk00000139 (
.ADR0(\i2/blk00000001/sig00000102 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000000f2 ),
.O(\i2/blk00000001/sig00000060 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/blk00000133 (
.ADR0(\i2/blk00000001/sig00000104 ),
.ADR1(\i2/blk00000001/sig000000f4 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000005c )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y32" ))
\i2/blk00000001/blk00000136 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000103 ),
.ADR2(\i2/blk00000001/sig000000f3 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000005e )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/blk0000012d (
.ADR0(\i2/blk00000001/sig00000104 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000000f6 ),
.O(\i2/blk00000001/sig00000058 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X25Y33" ))
\i2/blk00000001/blk00000130 (
.ADR0(\i2/blk00000001/sig00000104 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000000f5 ),
.O(\i2/blk00000001/sig0000005a )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X25Y34" ))
\i2/blk00000001/blk0000012a (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000104 ),
.ADR2(\i2/blk00000001/sig000000f7 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000056 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y35" ))
\i2/blk00000001/blk00000124 (
.ADR0(\i2/blk00000001/sig00000104 ),
.ADR1(\i2/blk00000001/sig000000f8 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000052 )
);
X_LUT4 #(
.INIT ( 16'h0F0F ),
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/blk000001d9 (
.ADR0(x2_8_IBUF_3048),
.ADR1(GND),
.ADR2(x2_9_IBUF_3049),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000e2 )
);
X_LUT4 #(
.INIT ( 16'h5555 ),
.LOC ( "SLICE_X3Y30" ))
\i2/blk00000001/blk000001d4 (
.ADR0(x2_8_IBUF_3048),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000e3 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X17Y28" ))
\i2/blk00000001/blk0000016b (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000143 ),
.ADR2(\i2/blk00000001/sig0000014d ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000081 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/blk00000162 (
.ADR0(\i2/blk00000001/sig00000122 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig0000012c ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000007b )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y29" ))
\i2/blk00000001/blk00000165 (
.ADR0(\i2/blk00000001/sig0000012d ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000137 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000007d )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/blk0000015c (
.ADR0(\i2/blk00000001/sig0000010c ),
.ADR1(\i2/blk00000001/sig00000116 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000077 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X17Y30" ))
\i2/blk00000001/blk0000015f (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000117 ),
.ADR2(\i2/blk00000001/sig00000121 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000079 )
);
X_LUT4 #(
.INIT ( 16'h9999 ),
.LOC ( "SLICE_X17Y31" ))
\i2/blk00000001/blk00000159 (
.ADR0(\i2/blk00000001/sig00000195 ),
.ADR1(\i2/blk00000001/sig0000010c ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000075 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/blk000001a3 (
.ADR0(\i2/blk00000001/sig0000017e ),
.ADR1(\i2/blk00000001/sig0000018b ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000a6 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X13Y35" ))
\i2/blk00000001/blk000001a6 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig0000018c ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000001dd ),
.O(\i2/blk00000001/sig000000a8 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/blk0000019d (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000168 ),
.ADR2(\i2/blk00000001/sig0000017c ),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000a2 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X13Y36" ))
\i2/blk00000001/blk000001a0 (
.ADR0(\i2/blk00000001/sig00000173 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000189 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000a4 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/blk00000197 (
.ADR0(\i2/blk00000001/sig00000152 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000166 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000009e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y37" ))
\i2/blk00000001/blk0000019a (
.ADR0(\i2/blk00000001/sig00000171 ),
.ADR1(\i2/blk00000001/sig0000015d ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000a0 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/blk00000191 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig0000013c ),
.ADR2(\i2/blk00000001/sig00000150 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000009a )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X13Y38" ))
\i2/blk00000001/blk00000194 (
.ADR0(\i2/blk00000001/sig00000147 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig0000015b ),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000009c )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/blk0000018b (
.ADR0(\i2/blk00000001/sig00000126 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig0000013a ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000096 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y39" ))
\i2/blk00000001/blk0000018e (
.ADR0(\i2/blk00000001/sig00000145 ),
.ADR1(\i2/blk00000001/sig00000131 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000098 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/blk00000185 (
.ADR0(\i2/blk00000001/sig00000110 ),
.ADR1(\i2/blk00000001/sig00000124 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000092 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y40" ))
\i2/blk00000001/blk00000188 (
.ADR0(\i2/blk00000001/sig0000012f ),
.ADR1(\i2/blk00000001/sig0000011b ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000094 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/blk0000017f (
.ADR0(\i2/blk00000001/sig00000110 ),
.ADR1(\i2/blk00000001/sig0000010e ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000008e )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X13Y41" ))
\i2/blk00000001/blk00000182 (
.ADR0(\i2/blk00000001/sig00000110 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000119 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000090 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/blk000001cc (
.ADR0(\i2/blk00000001/sig00000191 ),
.ADR1(\i2/blk00000001/sig00000182 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000c1 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X21Y29" ))
\i2/blk00000001/blk000001cf (
.ADR0(\i2/blk00000001/sig00000192 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig000001e3 ),
.O(\i2/blk00000001/sig000000c3 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/blk000001c6 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig0000016c ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig00000180 ),
.O(\i2/blk00000001/sig000000bd )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X21Y30" ))
\i2/blk00000001/blk000001c9 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000177 ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig0000018f ),
.O(\i2/blk00000001/sig000000bf )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/blk000001c0 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000156 ),
.ADR2(\i2/blk00000001/sig0000016a ),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000b9 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X21Y31" ))
\i2/blk00000001/blk000001c3 (
.ADR0(\i2/blk00000001/sig00000175 ),
.ADR1(\i2/blk00000001/sig00000161 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000bb )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/blk000001ba (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000140 ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig00000154 ),
.O(\i2/blk00000001/sig000000b5 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X21Y32" ))
\i2/blk00000001/blk000001bd (
.ADR0(\i2/blk00000001/sig0000014b ),
.ADR1(\i2/blk00000001/sig0000015f ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000b7 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/blk000001b4 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig0000012a ),
.ADR2(\i2/blk00000001/sig0000013e ),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000b1 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X21Y33" ))
\i2/blk00000001/blk000001b7 (
.ADR0(\i2/blk00000001/sig00000135 ),
.ADR1(VCC),
.ADR2(\i2/blk00000001/sig00000149 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000b3 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/blk000001ae (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000114 ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig00000128 ),
.O(\i2/blk00000001/sig000000ad )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X21Y34" ))
\i2/blk00000001/blk000001b1 (
.ADR0(\i2/blk00000001/sig0000011f ),
.ADR1(\i2/blk00000001/sig00000133 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000af )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/blk000001a8 (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000114 ),
.ADR2(\i2/blk00000001/sig00000112 ),
.ADR3(VCC),
.O(\i2/blk00000001/sig000000a9 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X21Y35" ))
\i2/blk00000001/blk000001ab (
.ADR0(VCC),
.ADR1(\i2/blk00000001/sig00000114 ),
.ADR2(VCC),
.ADR3(\i2/blk00000001/sig0000011d ),
.O(\i2/blk00000001/sig000000ab )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X16Y11" ))
\i1/blk00000001/blk00000122 (
.ADR0(\i1/blk00000001/sig000000d2 ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig000001da ),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000051 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X16Y12" ))
\i1/blk00000001/blk00000119 (
.ADR0(\i1/blk00000001/sig000000c5 ),
.ADR1(\i1/blk00000001/sig000000d5 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000004b )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X16Y12" ))
\i1/blk00000001/blk0000011c (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000d4 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000c4 ),
.O(\i1/blk00000001/sig0000004d )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X16Y13" ))
\i1/blk00000001/blk00000113 (
.ADR0(\i1/blk00000001/sig000000d7 ),
.ADR1(\i1/blk00000001/sig000000c7 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000047 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X16Y13" ))
\i1/blk00000001/blk00000116 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000d6 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000c6 ),
.O(\i1/blk00000001/sig00000049 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X16Y14" ))
\i1/blk00000001/blk0000010d (
.ADR0(\i1/blk00000001/sig000000d9 ),
.ADR1(\i1/blk00000001/sig000000c9 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000043 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X16Y14" ))
\i1/blk00000001/blk00000110 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000d8 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000c8 ),
.O(\i1/blk00000001/sig00000045 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X16Y15" ))
\i1/blk00000001/blk00000107 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000db ),
.ADR2(\i1/blk00000001/sig000000cb ),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000003f )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X16Y15" ))
\i1/blk00000001/blk0000010a (
.ADR0(\i1/blk00000001/sig000000da ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig000000ca ),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000041 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X16Y16" ))
\i1/blk00000001/blk00000101 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000dd ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000cd ),
.O(\i1/blk00000001/sig0000003b )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X16Y16" ))
\i1/blk00000001/blk00000104 (
.ADR0(\i1/blk00000001/sig000000cc ),
.ADR1(\i1/blk00000001/sig000000dc ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000003d )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X16Y17" ))
\i1/blk00000001/blk000000fb (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000de ),
.ADR2(\i1/blk00000001/sig000000cf ),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000037 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X16Y17" ))
\i1/blk00000001/blk000000fe (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000de ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000ce ),
.O(\i1/blk00000001/sig00000039 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X16Y18" ))
\i1/blk00000001/blk000000f8 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig000000de ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000d0 ),
.O(\i1/blk00000001/sig00000035 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/blk00000151 (
.ADR0(\i1/blk00000001/sig0000018e ),
.ADR1(\i1/blk00000001/sig000000fa ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000070 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y8" ))
\i1/blk00000001/blk00000154 (
.ADR0(\i1/blk00000001/sig000001e0 ),
.ADR1(\i1/blk00000001/sig000000f9 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000072 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/blk0000014b (
.ADR0(\i1/blk00000001/sig000000fc ),
.ADR1(\i1/blk00000001/sig000000ec ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000006c )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X15Y9" ))
\i1/blk00000001/blk0000014e (
.ADR0(\i1/blk00000001/sig000000fb ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000eb ),
.O(\i1/blk00000001/sig0000006e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/blk00000145 (
.ADR0(\i1/blk00000001/sig000000fe ),
.ADR1(\i1/blk00000001/sig000000ee ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000068 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y10" ))
\i1/blk00000001/blk00000148 (
.ADR0(\i1/blk00000001/sig000000ed ),
.ADR1(\i1/blk00000001/sig000000fd ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000006a )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/blk0000013f (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000100 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000f0 ),
.O(\i1/blk00000001/sig00000064 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y11" ))
\i1/blk00000001/blk00000142 (
.ADR0(\i1/blk00000001/sig000000ff ),
.ADR1(\i1/blk00000001/sig000000ef ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000066 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/blk00000139 (
.ADR0(\i1/blk00000001/sig00000102 ),
.ADR1(\i1/blk00000001/sig000000f2 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000060 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y12" ))
\i1/blk00000001/blk0000013c (
.ADR0(\i1/blk00000001/sig000000f1 ),
.ADR1(\i1/blk00000001/sig00000101 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000062 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/blk00000133 (
.ADR0(\i1/blk00000001/sig00000104 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000f4 ),
.O(\i1/blk00000001/sig0000005c )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y13" ))
\i1/blk00000001/blk00000136 (
.ADR0(\i1/blk00000001/sig00000103 ),
.ADR1(\i1/blk00000001/sig000000f3 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000005e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/blk0000012d (
.ADR0(\i1/blk00000001/sig00000104 ),
.ADR1(\i1/blk00000001/sig000000f6 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000058 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y14" ))
\i1/blk00000001/blk00000130 (
.ADR0(\i1/blk00000001/sig000000f5 ),
.ADR1(\i1/blk00000001/sig00000104 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000005a )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/blk00000127 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000104 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig000000f8 ),
.O(\i1/blk00000001/sig00000054 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y15" ))
\i1/blk00000001/blk0000012a (
.ADR0(\i1/blk00000001/sig00000104 ),
.ADR1(\i1/blk00000001/sig000000f7 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000056 )
);
X_LUT4 #(
.INIT ( 16'h0FF0 ),
.LOC ( "SLICE_X15Y16" ))
\i1/blk00000001/blk00000124 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig000000f8 ),
.ADR3(\i1/blk00000001/sig00000104 ),
.O(\i1/blk00000001/sig00000052 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/blk000001e7 (
.ADR0(x1_7_IBUF_3318),
.ADR1(VCC),
.ADR2(x1_6_IBUF_3317),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000118 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/blk000001e5 (
.ADR0(x1_7_IBUF_3318),
.ADR1(x1_6_IBUF_3317),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000106 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X17Y16" ))
\i1/blk00000001/blk000001e6 (
.ADR0(x1_7_IBUF_3318),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x1_6_IBUF_3317),
.O(\i1/blk00000001/sig0000010d )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/blk0000020e (
.ADR0(x1_1_IBUF_3338),
.ADR1(VCC),
.ADR2(x1_0_IBUF_3337),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000011e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/blk0000020c (
.ADR0(x1_0_IBUF_3337),
.ADR1(x1_1_IBUF_3338),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000109 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X1Y9" ))
\i1/blk00000001/blk0000020d (
.ADR0(x1_1_IBUF_3338),
.ADR1(VCC),
.ADR2(x1_0_IBUF_3337),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000113 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y19" ))
\i3/blk00000001/blk0000016b (
.ADR0(\i3/blk00000001/sig00000143 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig0000014d ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000081 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/blk00000162 (
.ADR0(\i3/blk00000001/sig00000122 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig0000012c ),
.O(\i3/blk00000001/sig0000007b )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X29Y20" ))
\i3/blk00000001/blk00000165 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig0000012d ),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig00000137 ),
.O(\i3/blk00000001/sig0000007d )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/blk0000015c (
.ADR0(\i3/blk00000001/sig0000010c ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig00000116 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000077 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X29Y21" ))
\i3/blk00000001/blk0000015f (
.ADR0(\i3/blk00000001/sig00000117 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig00000121 ),
.O(\i3/blk00000001/sig00000079 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y22" ))
\i3/blk00000001/blk00000159 (
.ADR0(\i3/blk00000001/sig0000010c ),
.ADR1(\i3/blk00000001/sig0000010b ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000075 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/blk000001a3 (
.ADR0(\i3/blk00000001/sig0000018b ),
.ADR1(\i3/blk00000001/sig0000017e ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000a6 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y9" ))
\i3/blk00000001/blk000001a6 (
.ADR0(\i3/blk00000001/sig0000018c ),
.ADR1(\i3/blk00000001/sig000001dd ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000a8 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/blk0000019d (
.ADR0(\i3/blk00000001/sig00000168 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig0000017c ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000a2 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X26Y10" ))
\i3/blk00000001/blk000001a0 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig00000173 ),
.ADR2(\i3/blk00000001/sig00000189 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000a4 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/blk00000197 (
.ADR0(\i3/blk00000001/sig00000166 ),
.ADR1(\i3/blk00000001/sig00000152 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000009e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y11" ))
\i3/blk00000001/blk0000019a (
.ADR0(\i3/blk00000001/sig0000015d ),
.ADR1(\i3/blk00000001/sig00000171 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000a0 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/blk00000191 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig0000013c ),
.ADR2(\i3/blk00000001/sig00000150 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000009a )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X26Y12" ))
\i3/blk00000001/blk00000194 (
.ADR0(\i3/blk00000001/sig00000147 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig0000015b ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000009c )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/blk0000018b (
.ADR0(\i3/blk00000001/sig0000013a ),
.ADR1(\i3/blk00000001/sig00000126 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000096 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y13" ))
\i3/blk00000001/blk0000018e (
.ADR0(\i3/blk00000001/sig00000131 ),
.ADR1(\i3/blk00000001/sig00000145 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000098 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/blk00000185 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig00000110 ),
.ADR2(\i3/blk00000001/sig00000124 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000092 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X26Y14" ))
\i3/blk00000001/blk00000188 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig0000011b ),
.ADR2(\i3/blk00000001/sig0000012f ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000094 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/blk0000017f (
.ADR0(\i3/blk00000001/sig0000010e ),
.ADR1(\i3/blk00000001/sig00000110 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000008e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X26Y15" ))
\i3/blk00000001/blk00000182 (
.ADR0(\i3/blk00000001/sig00000110 ),
.ADR1(\i3/blk00000001/sig00000119 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000090 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/blk000001cc (
.ADR0(\i3/blk00000001/sig00000182 ),
.ADR1(\i3/blk00000001/sig00000191 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000c1 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y8" ))
\i3/blk00000001/blk000001cf (
.ADR0(\i3/blk00000001/sig00000192 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig000001e3 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000c3 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/blk000001c6 (
.ADR0(\i3/blk00000001/sig0000016c ),
.ADR1(\i3/blk00000001/sig00000180 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000bd )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X29Y9" ))
\i3/blk00000001/blk000001c9 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig00000177 ),
.ADR2(\i3/blk00000001/sig0000018f ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000bf )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/blk000001c0 (
.ADR0(\i3/blk00000001/sig00000156 ),
.ADR1(\i3/blk00000001/sig0000016a ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000b9 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y10" ))
\i3/blk00000001/blk000001c3 (
.ADR0(\i3/blk00000001/sig00000161 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig00000175 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000bb )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/blk000001ba (
.ADR0(\i3/blk00000001/sig00000154 ),
.ADR1(\i3/blk00000001/sig00000140 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000b5 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X29Y11" ))
\i3/blk00000001/blk000001bd (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig0000014b ),
.ADR2(\i3/blk00000001/sig0000015f ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000b7 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/blk000001b4 (
.ADR0(\i3/blk00000001/sig0000012a ),
.ADR1(\i3/blk00000001/sig0000013e ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000b1 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y12" ))
\i3/blk00000001/blk000001b7 (
.ADR0(\i3/blk00000001/sig00000135 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig00000149 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000b3 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/blk000001ae (
.ADR0(\i3/blk00000001/sig00000128 ),
.ADR1(\i3/blk00000001/sig00000114 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000ad )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X29Y13" ))
\i3/blk00000001/blk000001b1 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig0000011f ),
.ADR2(\i3/blk00000001/sig00000133 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000af )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/blk000001a8 (
.ADR0(\i3/blk00000001/sig00000114 ),
.ADR1(\i3/blk00000001/sig00000112 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000a9 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X29Y14" ))
\i3/blk00000001/blk000001ab (
.ADR0(\i3/blk00000001/sig00000114 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig0000011d ),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000ab )
);
X_BUF #(
.LOC ( "IPAD3" ))
\x2<4>/IFF/IMUX (
.I(\x2<4>/INBUF ),
.O(x2_4_IBUF_3098)
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/blk00000201 (
.ADR0(x1_3_IBUF_3400),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x1_2_IBUF_3399),
.O(\i1/blk00000001/sig0000011c )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/blk000001ff (
.ADR0(x1_2_IBUF_3399),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000108 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X13Y6" ))
\i1/blk00000001/blk00000200 (
.ADR0(VCC),
.ADR1(x1_3_IBUF_3400),
.ADR2(x1_2_IBUF_3399),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000111 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/blk0000017a (
.ADR0(\i1/blk00000001/sig00000184 ),
.ADR1(\i1/blk00000001/sig0000017a ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000008b )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X19Y11" ))
\i1/blk00000001/blk0000017d (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000186 ),
.ADR2(\i1/blk00000001/sig00000185 ),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000008d )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/blk00000174 (
.ADR0(\i1/blk00000001/sig00000164 ),
.ADR1(\i1/blk00000001/sig0000016e ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000087 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X19Y12" ))
\i1/blk00000001/blk00000177 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig0000016f ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000179 ),
.O(\i1/blk00000001/sig00000089 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/blk0000016e (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig0000014e ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000158 ),
.O(\i1/blk00000001/sig00000083 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X19Y13" ))
\i1/blk00000001/blk00000171 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000159 ),
.ADR2(\i1/blk00000001/sig00000163 ),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000085 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/blk00000168 (
.ADR0(\i1/blk00000001/sig00000138 ),
.ADR1(\i1/blk00000001/sig00000142 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000007f )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X19Y14" ))
\i1/blk00000001/blk0000016b (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000143 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig0000014d ),
.O(\i1/blk00000001/sig00000081 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/blk00000162 (
.ADR0(\i1/blk00000001/sig00000122 ),
.ADR1(\i1/blk00000001/sig0000012c ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000007b )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X19Y15" ))
\i1/blk00000001/blk00000165 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig0000012d ),
.ADR2(\i1/blk00000001/sig00000137 ),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000007d )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/blk0000015c (
.ADR0(\i1/blk00000001/sig0000010c ),
.ADR1(\i1/blk00000001/sig00000116 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000077 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X19Y16" ))
\i1/blk00000001/blk0000015f (
.ADR0(\i1/blk00000001/sig00000117 ),
.ADR1(\i1/blk00000001/sig00000121 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000079 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X13Y15" ))
\i1/blk00000001/blk00000188 (
.ADR0(\i1/blk00000001/sig0000012f ),
.ADR1(\i1/blk00000001/sig0000011b ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000094 )
);
X_LUT4 #(
.INIT ( 16'h0FF0 ),
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/blk0000017f (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig0000010e ),
.ADR3(\i1/blk00000001/sig00000110 ),
.O(\i1/blk00000001/sig0000008e )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X13Y16" ))
\i1/blk00000001/blk00000182 (
.ADR0(\i1/blk00000001/sig00000110 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000119 ),
.O(\i1/blk00000001/sig00000090 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/blk000001cc (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000182 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000191 ),
.O(\i1/blk00000001/sig000000c1 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X2Y5" ))
\i1/blk00000001/blk000001cf (
.ADR0(\i1/blk00000001/sig000001e3 ),
.ADR1(\i1/blk00000001/sig00000192 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000c3 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/blk000001c6 (
.ADR0(\i1/blk00000001/sig0000016c ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig00000180 ),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000bd )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X2Y6" ))
\i1/blk00000001/blk000001c9 (
.ADR0(\i1/blk00000001/sig00000177 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig0000018f ),
.O(\i1/blk00000001/sig000000bf )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/blk000001c0 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000156 ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig0000016a ),
.O(\i1/blk00000001/sig000000b9 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X2Y7" ))
\i1/blk00000001/blk000001c3 (
.ADR0(\i1/blk00000001/sig00000175 ),
.ADR1(\i1/blk00000001/sig00000161 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000bb )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/blk000001ba (
.ADR0(\i1/blk00000001/sig00000140 ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig00000154 ),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000b5 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X2Y8" ))
\i1/blk00000001/blk000001bd (
.ADR0(\i1/blk00000001/sig0000014b ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig0000015f ),
.O(\i1/blk00000001/sig000000b7 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/blk000001b4 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig0000012a ),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig0000013e ),
.O(\i1/blk00000001/sig000000b1 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X2Y9" ))
\i1/blk00000001/blk000001b7 (
.ADR0(\i1/blk00000001/sig00000149 ),
.ADR1(\i1/blk00000001/sig00000135 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000b3 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/blk000001ae (
.ADR0(\i1/blk00000001/sig00000114 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000128 ),
.O(\i1/blk00000001/sig000000ad )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X2Y10" ))
\i1/blk00000001/blk000001b1 (
.ADR0(\i1/blk00000001/sig0000011f ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i1/blk00000001/sig00000133 ),
.O(\i1/blk00000001/sig000000af )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/blk000001a8 (
.ADR0(VCC),
.ADR1(\i1/blk00000001/sig00000112 ),
.ADR2(\i1/blk00000001/sig00000114 ),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000a9 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X2Y11" ))
\i1/blk00000001/blk000001ab (
.ADR0(\i1/blk00000001/sig00000114 ),
.ADR1(VCC),
.ADR2(\i1/blk00000001/sig0000011d ),
.ADR3(VCC),
.O(\i1/blk00000001/sig000000ab )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/blk0000011f (
.ADR0(\i3/blk00000001/sig000000d3 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig00000188 ),
.O(\i3/blk00000001/sig0000004f )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X27Y18" ))
\i3/blk00000001/blk00000122 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig000000d2 ),
.ADR2(\i3/blk00000001/sig000001da ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000051 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y19" ))
\i3/blk00000001/blk00000119 (
.ADR0(\i3/blk00000001/sig000000c5 ),
.ADR1(\i3/blk00000001/sig000000d5 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000004b )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X27Y19" ))
\i3/blk00000001/blk0000011c (
.ADR0(\i3/blk00000001/sig000000d4 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig000000c4 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000004d )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X27Y20" ))
\i3/blk00000001/blk00000113 (
.ADR0(\i3/blk00000001/sig000000d7 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig000000c7 ),
.O(\i3/blk00000001/sig00000047 )
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X27Y20" ))
\i3/blk00000001/blk00000116 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig000000d6 ),
.ADR2(\i3/blk00000001/sig000000c6 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000049 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X27Y21" ))
\i3/blk00000001/blk0000010d (
.ADR0(\i3/blk00000001/sig000000d9 ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig000000c9 ),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000043 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y21" ))
\i3/blk00000001/blk00000110 (
.ADR0(\i3/blk00000001/sig000000d8 ),
.ADR1(\i3/blk00000001/sig000000c8 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000045 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X27Y22" ))
\i3/blk00000001/blk00000107 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig000000db ),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig000000cb ),
.O(\i3/blk00000001/sig0000003f )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y22" ))
\i3/blk00000001/blk0000010a (
.ADR0(\i3/blk00000001/sig000000da ),
.ADR1(\i3/blk00000001/sig000000ca ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000041 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X27Y23" ))
\i3/blk00000001/blk00000101 (
.ADR0(\i3/blk00000001/sig000000dd ),
.ADR1(VCC),
.ADR2(\i3/blk00000001/sig000000cd ),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000003b )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y23" ))
\i3/blk00000001/blk00000104 (
.ADR0(\i3/blk00000001/sig000000dc ),
.ADR1(\i3/blk00000001/sig000000cc ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000003d )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X27Y24" ))
\i3/blk00000001/blk000000fb (
.ADR0(\i3/blk00000001/sig000000de ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig000000cf ),
.O(\i3/blk00000001/sig00000037 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y24" ))
\i3/blk00000001/blk000000fe (
.ADR0(\i3/blk00000001/sig000000de ),
.ADR1(\i3/blk00000001/sig000000ce ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000039 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y25" ))
\i3/blk00000001/blk000000f8 (
.ADR0(\i3/blk00000001/sig000000d0 ),
.ADR1(\i3/blk00000001/sig000000de ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000035 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/blk00000151 (
.ADR0(\i3/blk00000001/sig0000018e ),
.ADR1(\i3/blk00000001/sig000000fa ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000070 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X25Y13" ))
\i3/blk00000001/blk00000154 (
.ADR0(VCC),
.ADR1(\i3/blk00000001/sig000000f9 ),
.ADR2(VCC),
.ADR3(\i3/blk00000001/sig000001e0 ),
.O(\i3/blk00000001/sig00000072 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/blk0000014b (
.ADR0(\i3/blk00000001/sig000000ec ),
.ADR1(\i3/blk00000001/sig000000fc ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000006c )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y14" ))
\i3/blk00000001/blk0000014e (
.ADR0(\i3/blk00000001/sig000000eb ),
.ADR1(\i3/blk00000001/sig000000fb ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000006e )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/blk00000127 (
.ADR0(\i3/blk00000001/sig000000f8 ),
.ADR1(\i3/blk00000001/sig00000104 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000054 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y20" ))
\i3/blk00000001/blk0000012a (
.ADR0(\i3/blk00000001/sig000000f7 ),
.ADR1(\i3/blk00000001/sig00000104 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000056 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X25Y21" ))
\i3/blk00000001/blk00000124 (
.ADR0(\i3/blk00000001/sig000000f8 ),
.ADR1(\i3/blk00000001/sig00000104 ),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000052 )
);
X_LUT4 #(
.INIT ( 16'hAA55 ),
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/blk000001d1 (
.ADR0(x3_8_IBUF_3523),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x3_9_IBUF_3524),
.O(\i3/blk00000001/sig000000e0 )
);
X_LUT4 #(
.INIT ( 16'h5555 ),
.LOC ( "SLICE_X30Y18" ))
\i3/blk00000001/blk000001d2 (
.ADR0(x3_8_IBUF_3523),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000000e1 )
);
X_LUT4 #(
.INIT ( 16'hCC33 ),
.LOC ( "SLICE_X30Y19" ))
\i3/blk00000001/blk00000223 (
.ADR0(VCC),
.ADR1(x3_8_IBUF_3523),
.ADR2(VCC),
.ADR3(x3_9_IBUF_3524),
.O(\i3/blk00000001/sig0000023a )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/blk000001e7 (
.ADR0(x3_7_IBUF_3530),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x3_6_IBUF_3529),
.O(\i3/blk00000001/sig00000118 )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/blk000001e5 (
.ADR0(x3_7_IBUF_3530),
.ADR1(x3_6_IBUF_3529),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000106 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X31Y19" ))
\i3/blk00000001/blk000001e6 (
.ADR0(x3_7_IBUF_3530),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(x3_6_IBUF_3529),
.O(\i3/blk00000001/sig0000010d )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/blk000001f4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(VCC),
.ADR2(x3_4_IBUF_3571),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000011a )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/blk000001f2 (
.ADR0(x3_5_IBUF_3572),
.ADR1(x3_4_IBUF_3571),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000107 )
);
X_LUT4 #(
.INIT ( 16'h5A5A ),
.LOC ( "SLICE_X27Y11" ))
\i3/blk00000001/blk000001f3 (
.ADR0(x3_5_IBUF_3572),
.ADR1(VCC),
.ADR2(x3_4_IBUF_3571),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000010f )
);
X_BUF #(
.LOC ( "PAD63" ))
\x3<4>/IFF/IMUX (
.I(\x3<4>/INBUF ),
.O(x3_4_IBUF_3571)
);
X_BUF #(
.LOC ( "PAD87" ))
\x2<8>/IFF/IMUX (
.I(\x2<8>/INBUF ),
.O(x2_8_IBUF_3048)
);
X_BUF #(
.LOC ( "PAD62" ))
\x3<5>/IFF/IMUX (
.I(\x3<5>/INBUF ),
.O(x3_5_IBUF_3572)
);
X_BUF #(
.LOC ( "PAD85" ))
\x2<9>/IFF/IMUX (
.I(\x2<9>/INBUF ),
.O(x2_9_IBUF_3049)
);
X_BUF #(
.LOC ( "IPAD60" ))
\x3<6>/IFF/IMUX (
.I(\x3<6>/INBUF ),
.O(x3_6_IBUF_3529)
);
X_BUF #(
.LOC ( "PAD61" ))
\x3<7>/IFF/IMUX (
.I(\x3<7>/INBUF ),
.O(x3_7_IBUF_3530)
);
X_BUF #(
.LOC ( "PAD42" ))
\x3<8>/IFF/IMUX (
.I(\x3<8>/INBUF ),
.O(x3_8_IBUF_3523)
);
X_BUF #(
.LOC ( "PAD58" ))
\x3<9>/IFF/IMUX (
.I(\x3<9>/INBUF ),
.O(x3_9_IBUF_3524)
);
X_LUT4 #(
.INIT ( 16'h1717 ),
.LOC ( "SLICE_X22Y31" ))
\Madd_s2_Madd_lut<11>_SW0 (
.ADR0(t3[21]),
.ADR1(t2[21]),
.ADR2(t1[21]),
.ADR3(VCC),
.O(N10)
);
X_LUT4 #(
.INIT ( 16'hEE88 ),
.LOC ( "SLICE_X21Y25" ))
Madd_s2C1 (
.ADR0(t1[12]),
.ADR1(t2[12]),
.ADR2(VCC),
.ADR3(t3[12]),
.O(Madd_s2C)
);
X_LUT4 #(
.INIT ( 16'hEE88 ),
.LOC ( "SLICE_X21Y27" ))
Madd_s2C11 (
.ADR0(t2[13]),
.ADR1(t3[13]),
.ADR2(VCC),
.ADR3(t1[13]),
.O(Madd_s2C1_12961)
);
X_LUT4 #(
.INIT ( 16'hFAA0 ),
.LOC ( "SLICE_X23Y27" ))
Madd_s2C21 (
.ADR0(t2[14]),
.ADR1(VCC),
.ADR2(t3[14]),
.ADR3(t1[14]),
.O(Madd_s2C2)
);
X_LUT4 #(
.INIT ( 16'hEE88 ),
.LOC ( "SLICE_X21Y26" ))
Madd_s2C31 (
.ADR0(t1[15]),
.ADR1(t2[15]),
.ADR2(VCC),
.ADR3(t3[15]),
.O(Madd_s2C3)
);
X_LUT4 #(
.INIT ( 16'hFCC0 ),
.LOC ( "SLICE_X23Y25" ))
Madd_s2C41 (
.ADR0(VCC),
.ADR1(t2[16]),
.ADR2(t1[16]),
.ADR3(t3[16]),
.O(Madd_s2C4)
);
X_LUT4 #(
.INIT ( 16'hEE88 ),
.LOC ( "SLICE_X18Y29" ))
Madd_s2C51 (
.ADR0(t1[17]),
.ADR1(t3[17]),
.ADR2(VCC),
.ADR3(t2[17]),
.O(Madd_s2C5)
);
X_LUT4 #(
.INIT ( 16'hFCC0 ),
.LOC ( "SLICE_X22Y28" ))
Madd_s2C61 (
.ADR0(VCC),
.ADR1(t2[18]),
.ADR2(t1[18]),
.ADR3(t3[18]),
.O(Madd_s2C6)
);
X_LUT4 #(
.INIT ( 16'hE8E8 ),
.LOC ( "SLICE_X21Y28" ))
Madd_s2C71 (
.ADR0(t3[19]),
.ADR1(t2[19]),
.ADR2(t1[19]),
.ADR3(VCC),
.O(Madd_s2C7)
);
X_LUT4 #(
.INIT ( 16'hEE88 ),
.LOC ( "SLICE_X22Y29" ))
Madd_s2C81 (
.ADR0(t3[20]),
.ADR1(t2[20]),
.ADR2(VCC),
.ADR3(t1[20]),
.O(Madd_s2C8)
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000185/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y26" ))
\i2/blk00000001/sig00000185/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000185/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000179/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y27" ))
\i2/blk00000001/sig00000179/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000179/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000163/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y28" ))
\i2/blk00000001/sig00000163/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000163/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000014d/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X3Y29" ))
\i2/blk00000001/sig0000014d/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000014d/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/F/X_LUT4 (
.ADR0(x2_6_IBUF_3056),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001da/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y27" ))
\i2/blk00000001/sig000001da/G/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001da/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/F/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000186/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y28" ))
\i2/blk00000001/sig00000186/G/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000186/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/F/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000016f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y29" ))
\i2/blk00000001/sig0000016f/G/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000016f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/F/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000159/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y30" ))
\i2/blk00000001/sig00000159/G/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000159/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/F/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x2_6_IBUF_3056),
.O(\i2/blk00000001/sig00000143/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X15Y31" ))
\i2/blk00000001/sig00000143/G/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000143/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/F/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x2_6_IBUF_3056),
.O(\i2/blk00000001/sig0000012d/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X15Y32" ))
\i2/blk00000001/sig0000012d/G/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000012d/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/F/X_LUT4 (
.ADR0(x2_7_IBUF_3057),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000117/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X15Y33" ))
\i2/blk00000001/sig00000117/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000117/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/F/X_LUT4 (
.ADR0(GND),
.ADR1(x2_0_IBUF_3076),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001e3/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y37" ))
\i2/blk00000001/sig000001e3/G/X_LUT4 (
.ADR0(GND),
.ADR1(x2_1_IBUF_3077),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001e3/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/F/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000018f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y38" ))
\i2/blk00000001/sig0000018f/G/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000018f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/F/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000175/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y39" ))
\i2/blk00000001/sig00000175/G/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000175/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/F/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000015f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y40" ))
\i2/blk00000001/sig0000015f/G/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000015f/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/F/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x2_0_IBUF_3076),
.O(\i2/blk00000001/sig00000149/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X12Y41" ))
\i2/blk00000001/sig00000149/G/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000149/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/F/X_LUT4 (
.ADR0(GND),
.ADR1(x2_1_IBUF_3077),
.ADR2(VCC),
.ADR3(x2_0_IBUF_3076),
.O(\i2/blk00000001/sig00000133/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X12Y42" ))
\i2/blk00000001/sig00000133/G/X_LUT4 (
.ADR0(x2_1_IBUF_3077),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000133/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/F/X_LUT4 (
.ADR0(GND),
.ADR1(x2_1_IBUF_3077),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000011d/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y43" ))
\i2/blk00000001/sig0000011d/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000011d/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/F/X_LUT4 (
.ADR0(x2_4_IBUF_3098),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001dd/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y33" ))
\i2/blk00000001/sig000001dd/G/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001dd/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/F/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000189/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y34" ))
\i2/blk00000001/sig00000189/G/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000189/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/F/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000171/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y35" ))
\i2/blk00000001/sig00000171/G/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000171/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/F/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000015b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y36" ))
\i2/blk00000001/sig0000015b/G/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000015b/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/F/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x2_4_IBUF_3098),
.O(\i2/blk00000001/sig00000145/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X3Y37" ))
\i2/blk00000001/sig00000145/G/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000145/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/F/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x2_4_IBUF_3098),
.O(\i2/blk00000001/sig0000012f/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X3Y38" ))
\i2/blk00000001/sig0000012f/G/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000012f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/F/X_LUT4 (
.ADR0(x2_5_IBUF_3099),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000119/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y39" ))
\i2/blk00000001/sig00000119/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000119/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001e5/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y28" ))
\i2/blk00000001/sig000001e5/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001e5/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000192/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y29" ))
\i2/blk00000001/sig00000192/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000192/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000177/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y30" ))
\i2/blk00000001/sig00000177/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000177/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000161/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y31" ))
\i2/blk00000001/sig00000161/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000161/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000014b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y32" ))
\i2/blk00000001/sig0000014b/G/X_LUT4 (
.ADR0(GND),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000014b/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000135/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y33" ))
\i2/blk00000001/sig00000135/G/X_LUT4 (
.ADR0(GND),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000135/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000011f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y34" ))
\i2/blk00000001/sig0000011f/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000011f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/F/X_LUT4 (
.ADR0(GND),
.ADR1(x2_2_IBUF_3138),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001e0/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y31" ))
\i2/blk00000001/sig000001e0/G/X_LUT4 (
.ADR0(GND),
.ADR1(x2_3_IBUF_3139),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig000001e0/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/F/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000018c/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y32" ))
\i2/blk00000001/sig0000018c/G/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000018c/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/F/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000173/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y33" ))
\i2/blk00000001/sig00000173/G/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000173/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/F/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000015d/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y34" ))
\i2/blk00000001/sig0000015d/G/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000015d/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/F/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(x2_2_IBUF_3138),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000147/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X1Y35" ))
\i2/blk00000001/sig00000147/G/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000147/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/F/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(x2_2_IBUF_3138),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000131/F )
);
X_LUT4 #(
.INIT ( 16'hAAAA ),
.LOC ( "SLICE_X1Y36" ))
\i2/blk00000001/sig00000131/G/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig00000131/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/F/X_LUT4 (
.ADR0(x2_3_IBUF_3139),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000011b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y37" ))
\i2/blk00000001/sig0000011b/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i2/blk00000001/sig0000011b/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000185/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y11" ))
\i1/blk00000001/sig00000185/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000185/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000179/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y12" ))
\i1/blk00000001/sig00000179/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000179/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000163/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y13" ))
\i1/blk00000001/sig00000163/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000163/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000014d/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y14" ))
\i1/blk00000001/sig0000014d/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000014d/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000137/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X23Y15" ))
\i1/blk00000001/sig00000137/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000137/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_6_IBUF_3317),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001da/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y10" ))
\i1/blk00000001/sig000001da/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_7_IBUF_3318),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001da/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_7_IBUF_3318),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000186/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y11" ))
\i1/blk00000001/sig00000186/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_7_IBUF_3318),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000186/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/F/X_LUT4 (
.ADR0(x1_7_IBUF_3318),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000016f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y12" ))
\i1/blk00000001/sig0000016f/G/X_LUT4 (
.ADR0(x1_7_IBUF_3318),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000016f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/F/X_LUT4 (
.ADR0(x1_7_IBUF_3318),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000159/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y13" ))
\i1/blk00000001/sig00000159/G/X_LUT4 (
.ADR0(x1_7_IBUF_3318),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000159/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_7_IBUF_3318),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000143/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X17Y14" ))
\i1/blk00000001/sig00000143/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_7_IBUF_3318),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000143/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X17Y15" ))
\i1/blk00000001/sig0000012d/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_7_IBUF_3318),
.ADR2(x1_6_IBUF_3317),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000012d/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/F/X_LUT4 (
.ADR0(x1_0_IBUF_3337),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001e3/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y3" ))
\i1/blk00000001/sig000001e3/G/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001e3/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/F/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000018f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y4" ))
\i1/blk00000001/sig0000018f/G/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000018f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/F/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000175/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y5" ))
\i1/blk00000001/sig00000175/G/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000175/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/F/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000015f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y6" ))
\i1/blk00000001/sig0000015f/G/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000015f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/F/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000149/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X1Y7" ))
\i1/blk00000001/sig00000149/G/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000149/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X1Y8" ))
\i1/blk00000001/sig00000133/F/X_LUT4 (
.ADR0(x1_1_IBUF_3338),
.ADR1(GND),
.ADR2(x1_0_IBUF_3337),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000133/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_4_IBUF_3359),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001dd/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y0" ))
\i1/blk00000001/sig000001dd/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_5_IBUF_3360),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001dd/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_5_IBUF_3360),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000189/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y1" ))
\i1/blk00000001/sig00000189/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_5_IBUF_3360),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000189/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/F/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000171/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y2" ))
\i1/blk00000001/sig00000171/G/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000171/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/F/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000015b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y3" ))
\i1/blk00000001/sig0000015b/G/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000015b/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/F/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000145/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X12Y4" ))
\i1/blk00000001/sig00000145/G/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000145/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X12Y5" ))
\i1/blk00000001/sig0000012f/F/X_LUT4 (
.ADR0(x1_5_IBUF_3360),
.ADR1(GND),
.ADR2(x1_4_IBUF_3359),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000012f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001e5/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y3" ))
\i1/blk00000001/sig000001e5/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001e5/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000192/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y4" ))
\i1/blk00000001/sig00000192/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000192/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000177/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y5" ))
\i1/blk00000001/sig00000177/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000177/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000161/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y6" ))
\i1/blk00000001/sig00000161/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000161/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000014b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y7" ))
\i1/blk00000001/sig0000014b/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000014b/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000135/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y8" ))
\i1/blk00000001/sig00000135/G/X_LUT4 (
.ADR0(GND),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000135/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/F/X_LUT4 (
.ADR0(GND),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000011f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X3Y9" ))
\i1/blk00000001/sig0000011f/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000011f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_2_IBUF_3399),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001e0/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y0" ))
\i1/blk00000001/sig000001e0/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig000001e0/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000018c/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y1" ))
\i1/blk00000001/sig0000018c/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000018c/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000173/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y2" ))
\i1/blk00000001/sig00000173/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000173/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/F/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000015d/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y3" ))
\i1/blk00000001/sig0000015d/G/X_LUT4 (
.ADR0(GND),
.ADR1(x1_3_IBUF_3400),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig0000015d/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/F/X_LUT4 (
.ADR0(x1_3_IBUF_3400),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000147/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X13Y4" ))
\i1/blk00000001/sig00000147/G/X_LUT4 (
.ADR0(x1_3_IBUF_3400),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i1/blk00000001/sig00000147/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X13Y5" ))
\i1/blk00000001/sig00000131/F/X_LUT4 (
.ADR0(x1_3_IBUF_3400),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x1_2_IBUF_3399),
.O(\i1/blk00000001/sig00000131/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000185/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y13" ))
\i3/blk00000001/sig00000185/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000185/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000179/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y14" ))
\i3/blk00000001/sig00000179/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000179/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000163/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y15" ))
\i3/blk00000001/sig00000163/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000163/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000014d/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y16" ))
\i3/blk00000001/sig0000014d/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000014d/G )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/F/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000137/F )
);
X_LUT4 #(
.INIT ( 16'hFFFF ),
.LOC ( "SLICE_X30Y17" ))
\i3/blk00000001/sig00000137/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000137/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_6_IBUF_3529),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001da/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y13" ))
\i3/blk00000001/sig000001da/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001da/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000186/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y14" ))
\i3/blk00000001/sig00000186/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000186/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000016f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y15" ))
\i3/blk00000001/sig0000016f/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000016f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000159/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y16" ))
\i3/blk00000001/sig00000159/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000159/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000143/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y17" ))
\i3/blk00000001/sig00000143/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_7_IBUF_3530),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000143/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X31Y18" ))
\i3/blk00000001/sig0000012d/F/X_LUT4 (
.ADR0(x3_7_IBUF_3530),
.ADR1(GND),
.ADR2(VCC),
.ADR3(x3_6_IBUF_3529),
.O(\i3/blk00000001/sig0000012d/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_0_IBUF_3549),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001e3/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y9" ))
\i3/blk00000001/sig000001e3/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_1_IBUF_3550),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001e3/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/F/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000018f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y10" ))
\i3/blk00000001/sig0000018f/G/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000018f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/F/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000175/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y11" ))
\i3/blk00000001/sig00000175/G/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000175/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/F/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000015f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y12" ))
\i3/blk00000001/sig0000015f/G/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000015f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/F/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000149/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X28Y13" ))
\i3/blk00000001/sig00000149/G/X_LUT4 (
.ADR0(x3_1_IBUF_3550),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000149/G )
);
X_LUT4 #(
.INIT ( 16'hFF00 ),
.LOC ( "SLICE_X28Y14" ))
\i3/blk00000001/sig00000133/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_1_IBUF_3550),
.ADR2(VCC),
.ADR3(x3_0_IBUF_3549),
.O(\i3/blk00000001/sig00000133/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/F/X_LUT4 (
.ADR0(x3_4_IBUF_3571),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001dd/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y5" ))
\i3/blk00000001/sig000001dd/G/X_LUT4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001dd/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/F/X_LUT4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000189/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y6" ))
\i3/blk00000001/sig00000189/G/X_LUT4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000189/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/F/X_LUT4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000171/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y7" ))
\i3/blk00000001/sig00000171/G/X_LUT4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000171/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_5_IBUF_3572),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000015b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y8" ))
\i3/blk00000001/sig0000015b/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_5_IBUF_3572),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000015b/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/F/X_LUT4 (
.ADR0(GND),
.ADR1(x3_5_IBUF_3572),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000145/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X27Y9" ))
\i3/blk00000001/sig00000145/G/X_LUT4 (
.ADR0(GND),
.ADR1(x3_5_IBUF_3572),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000145/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X27Y10" ))
\i3/blk00000001/sig0000012f/F/X_LUT4 (
.ADR0(x3_5_IBUF_3572),
.ADR1(GND),
.ADR2(x3_4_IBUF_3571),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000012f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001e5/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y6" ))
\i3/blk00000001/sig000001e5/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001e5/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000192/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y7" ))
\i3/blk00000001/sig00000192/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000192/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000177/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y8" ))
\i3/blk00000001/sig00000177/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000177/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000161/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y9" ))
\i3/blk00000001/sig00000161/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000161/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000014b/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y10" ))
\i3/blk00000001/sig0000014b/G/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000014b/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/F/X_LUT4 (
.ADR0(GND),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000135/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y11" ))
\i3/blk00000001/sig00000135/G/X_LUT4 (
.ADR0(GND),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000135/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/F/X_LUT4 (
.ADR0(GND),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000011f/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X31Y12" ))
\i3/blk00000001/sig0000011f/G/X_LUT4 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000011f/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/F/X_LUT4 (
.ADR0(x3_2_IBUF_3611),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001e0/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y6" ))
\i3/blk00000001/sig000001e0/G/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig000001e0/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/F/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000018c/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y7" ))
\i3/blk00000001/sig0000018c/G/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000018c/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/F/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000173/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y8" ))
\i3/blk00000001/sig00000173/G/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000173/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/F/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000015d/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y9" ))
\i3/blk00000001/sig0000015d/G/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig0000015d/G )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/F/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000147/F )
);
X_LUT4 #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X25Y10" ))
\i3/blk00000001/sig00000147/G/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(VCC),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000147/G )
);
X_LUT4 #(
.INIT ( 16'hF0F0 ),
.LOC ( "SLICE_X25Y11" ))
\i3/blk00000001/sig00000131/F/X_LUT4 (
.ADR0(x3_3_IBUF_3612),
.ADR1(GND),
.ADR2(x3_2_IBUF_3611),
.ADR3(VCC),
.O(\i3/blk00000001/sig00000131/F )
);
X_BUF #(
.LOC ( "PAD102" ))
\y<0>/OUTPUT/OFF/OMUX (
.I(\y_0_OBUF/XORF_6646 ),
.O(\y<0>/O )
);
X_BUF #(
.LOC ( "PAD101" ))
\y<1>/OUTPUT/OFF/OMUX (
.I(\y_0_OBUF/XORG_6636 ),
.O(\y<1>/O )
);
X_BUF #(
.LOC ( "PAD91" ))
\y<2>/OUTPUT/OFF/OMUX (
.I(\y_2_OBUF/XORF_6685 ),
.O(\y<2>/O )
);
X_BUF #(
.LOC ( "PAD97" ))
\y<3>/OUTPUT/OFF/OMUX (
.I(\y_2_OBUF/XORG_6675 ),
.O(\y<3>/O )
);
X_BUF #(
.LOC ( "PAD92" ))
\y<4>/OUTPUT/OFF/OMUX (
.I(\y_4_OBUF/XORF_6724 ),
.O(\y<4>/O )
);
X_BUF #(
.LOC ( "PAD99" ))
\y<5>/OUTPUT/OFF/OMUX (
.I(\y_4_OBUF/XORG_6714 ),
.O(\y<5>/O )
);
X_BUF #(
.LOC ( "PAD98" ))
\y<6>/OUTPUT/OFF/OMUX (
.I(\y_6_OBUF/XORF_6763 ),
.O(\y<6>/O )
);
X_BUF #(
.LOC ( "PAD37" ))
\y<7>/OUTPUT/OFF/OMUX (
.I(\y_6_OBUF/XORG_6753 ),
.O(\y<7>/O )
);
X_BUF #(
.LOC ( "PAD18" ))
\y<8>/OUTPUT/OFF/OMUX (
.I(\y_8_OBUF/XORF_6794 ),
.O(\y<8>/O )
);
X_BUF #(
.LOC ( "PAD35" ))
\y<9>/OUTPUT/OFF/OMUX (
.I(\y_8_OBUF/XORG_6783 ),
.O(\y<9>/O )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000137/FAND/IN1 (
.I(x2_8_IBUF_3048),
.O(\NlwBufferSignal_i2/blk00000001/sig00000137/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000137/GAND/IN1 (
.I(x2_8_IBUF_3048),
.O(\NlwBufferSignal_i2/blk00000001/sig00000137/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000121/FAND/IN1 (
.I(x2_8_IBUF_3048),
.O(\NlwBufferSignal_i2/blk00000001/sig00000121/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000121/GAND/IN1 (
.I(x2_8_IBUF_3048),
.O(\NlwBufferSignal_i2/blk00000001/sig00000121/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001da/FAND/IN1 (
.I(x2_6_IBUF_3056),
.O(\NlwBufferSignal_i2/blk00000001/sig000001da/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001da/GAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig000001da/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000186/FAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000186/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000186/GAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000186/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000016f/FAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig0000016f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000016f/GAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig0000016f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000159/FAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000159/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000159/GAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000159/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000143/FAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000143/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000143/GAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000143/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000012d/FAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig0000012d/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000012d/GAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig0000012d/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000117/FAND/IN1 (
.I(x2_7_IBUF_3057),
.O(\NlwBufferSignal_i2/blk00000001/sig00000117/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001e3/FAND/IN0 (
.I(x2_0_IBUF_3076),
.O(\NlwBufferSignal_i2/blk00000001/sig000001e3/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001e3/GAND/IN0 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig000001e3/GAND/IN0 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000018f/FAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig0000018f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000018f/GAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig0000018f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000175/FAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig00000175/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000175/GAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig00000175/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000015f/FAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig0000015f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000015f/GAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig0000015f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000149/FAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig00000149/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000149/GAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig00000149/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000133/FAND/IN0 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig00000133/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000133/GAND/IN1 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig00000133/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000011d/FAND/IN0 (
.I(x2_1_IBUF_3077),
.O(\NlwBufferSignal_i2/blk00000001/sig0000011d/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001dd/FAND/IN1 (
.I(x2_4_IBUF_3098),
.O(\NlwBufferSignal_i2/blk00000001/sig000001dd/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001dd/GAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig000001dd/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000189/FAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000189/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000189/GAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000189/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000171/FAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000171/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000171/GAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000171/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000015b/FAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig0000015b/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000015b/GAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig0000015b/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000145/FAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000145/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000145/GAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000145/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000012f/FAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig0000012f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000012f/GAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig0000012f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000119/FAND/IN1 (
.I(x2_5_IBUF_3099),
.O(\NlwBufferSignal_i2/blk00000001/sig00000119/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig000001e0/GAND/IN0 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig000001e0/GAND/IN0 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000018c/FAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig0000018c/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000018c/GAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig0000018c/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000173/FAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig00000173/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000173/GAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig00000173/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000015d/FAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig0000015d/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000015d/GAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig0000015d/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000147/FAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig00000147/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000147/GAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig00000147/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000131/FAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig00000131/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig00000131/GAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig00000131/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i2/blk00000001/sig0000011b/FAND/IN1 (
.I(x2_3_IBUF_3139),
.O(\NlwBufferSignal_i2/blk00000001/sig0000011b/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000121/FAND/IN1 (
.I(x1_8_IBUF_3311),
.O(\NlwBufferSignal_i1/blk00000001/sig00000121/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000121/GAND/IN1 (
.I(x1_8_IBUF_3311),
.O(\NlwBufferSignal_i1/blk00000001/sig00000121/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig000001da/FAND/IN0 (
.I(x1_6_IBUF_3317),
.O(\NlwBufferSignal_i1/blk00000001/sig000001da/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig000001da/GAND/IN0 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig000001da/GAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000186/FAND/IN0 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000186/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000186/GAND/IN0 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000186/GAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000016f/FAND/IN1 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig0000016f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000016f/GAND/IN1 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig0000016f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000159/FAND/IN1 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000159/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000159/GAND/IN1 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000159/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000143/FAND/IN0 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000143/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000143/GAND/IN0 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000143/GAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000012d/FAND/IN0 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig0000012d/FAND/IN0 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000012d/GAND/IN1 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig0000012d/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000117/FAND/IN1 (
.I(x1_7_IBUF_3318),
.O(\NlwBufferSignal_i1/blk00000001/sig00000117/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig000001e3/GAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig000001e3/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000018f/FAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig0000018f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000018f/GAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig0000018f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000175/FAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig00000175/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000175/GAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig00000175/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000015f/FAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig0000015f/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig0000015f/GAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig0000015f/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000149/FAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig00000149/FAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000149/GAND/IN1 (
.I(x1_1_IBUF_3338),
.O(\NlwBufferSignal_i1/blk00000001/sig00000149/GAND/IN1 )
);
X_BUF \NlwBufferBlock_i1/blk00000001/sig00000133/FAND/IN1 (
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X_ONE NlwBlock_lab3dpath_VCC (
.O(VCC)
);
X_ZERO NlwBlock_lab3dpath_GND (
.O(GND)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:58:00 10/31/2016
// Module Name: I_EXECUTE
// Project Name: MIPS
// Description: The MIPS EX_MEM register implementation.
//
// Dependencies: None.
//
////////////////////////////////////////////////////////////////////////////////
module EX_MEM(input clk,
input [1:0] ctlwb_out,
input [2:0] ctlm_out,
input [31:0] adder_out,
input aluzero,
input [31:0] aluout,
input [31:0] readdat2,
input [4:0] muxout,
output reg [1:0] wb_ctlout,
output reg [2:0] m_ctlout,
output reg [31:0] add_result,
output reg zero,
output reg [31:0] alu_result,
output reg [31:0] rdata2out,
output reg [4:0] five_bit_muxout);
// Initialize.
initial begin
wb_ctlout <= 0;
m_ctlout <= 0;
add_result <= 0;
zero <= 0;
alu_result <= 0;
rdata2out <= 0;
five_bit_muxout <= 0;
end
// Update.
always @ (posedge clk)
begin
wb_ctlout <= ctlwb_out;
m_ctlout <= ctlm_out;
add_result <= adder_out;
zero <= aluzero;
alu_result <= aluout;
rdata2out <= readdat2;
five_bit_muxout <= muxout;
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 1G Ethernet MAC with TX and RX FIFOs
*/
module eth_mac_1g_fifo #
(
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Control
*/
input wire rx_clk_enable,
input wire tx_clk_enable,
input wire rx_mii_select,
input wire tx_mii_select,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.rx_clk_enable(rx_clk_enable),
.tx_clk_enable(tx_clk_enable),
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
`resetall
|
`timescale 1ns / 1ps
module posCounter (
input wire clk,
output reg [15:0] pos1, // Use for speed calculation
output reg [15:0] pos2, // Use for position control
input wire sensor, // Sensor input signal
input wire [1:0] clear, // clear[0] for pos1, clear[1] for pos2
input wire subtract, // subtract distance from pos2
input wire [15:0] distance // Ammount to reduce pos2 when subtract is true
);
reg sensor_prev;
initial begin
pos1 = 16'b0;
pos2 = 16'b0;
sensor_prev = 1'b0;
end
always @ (posedge clk) begin
if (clear[1] | clear[0]) begin
if (clear[0]) pos1 <= 16'b0;
if (clear[1]) pos2 <= 16'b0;
end else if (subtract) begin
pos2 <= pos2 - distance;
end else if (~sensor_prev & sensor) begin
pos1 <= pos1 + 1'b1;
pos2 <= pos2 + 1'b1;
end
sensor_prev <= sensor;
end
endmodule
module posCounter_testbench ();
reg clk;
wire [15:0] pos1;
wire [15:0] pos2;
reg sensor;
reg [1:0] clear;
reg subtract;
wire [15:0] distance;
posCounter dut (
.clk(clk),
.pos1(pos1),
.pos2(pos2),
.sensor(sensor),
.clear(clear),
.subtract(subtract),
.distance(distance)
);
parameter CLOCK_PERIOD = 10;
initial begin
clk <= 0;
forever #(CLOCK_PERIOD / 2) clk <= ~clk;
end
assign distance = 16'b111;
integer i;
initial begin
sensor <= 0; clear <= 2'b00; subtract <= 0; @(posedge clk);
clear <= 2'b01; @(posedge clk);
sensor <= 1; clear <= 2'b00; @(posedge clk);
sensor <= 0; @(posedge clk);
for (i = 0; i < 10; i = i + 1) begin
sensor <= 1; @(posedge clk);
sensor <= 0; @(posedge clk);
end
subtract <= 1; @(posedge clk);
subtract <= 0; @(posedge clk);
for (i = 0; i < 6; i = i + 1) begin
sensor <= 1; @(posedge clk);
sensor <= 0; @(posedge clk);
end
clear <= 2'b10; @(posedge clk);
clear <= 2'b00; @(posedge clk);
for (i = 0; i < 6; i = i + 1) begin
sensor <= 1; @(posedge clk);
sensor <= 0; @(posedge clk);
end
clear <= 2'b11; @(posedge clk);
clear <= 2'b00; @(posedge clk);
$stop;
end
endmodule
|
`default_nettype none
//`include "gci_std_display_parameter.h"
module gci_std_display_top #(
parameter P_VRAM_SIZE = 307200,
parameter P_VRAM_INDEX = 0,
parameter P_AREA_H = 640,
parameter P_AREA_V = 480,
parameter P_AREAA_HV_N = 19,
parameter P_MEM_ADDR_N = 23
)(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Display Clock
input wire iDISP_CLOCK,
//Write Reqest
input wire iIF_WR_REQ,
output wire oIF_WR_BUSY,
input wire iIF_WR_RW,
input wire [31:0] iIF_WR_ADDR,
input wire [31:0] iIF_WR_DATA,
//Read
output wire oIF_RD_VALID,
input wire iIF_RD_BUSY,
output wire oIF_RD_DATA,
//VRAM IF
output wire oVRAM_ARBIT_REQ,
input wire iVRAM_ARBIT_ACK,
output wire oVRAM_ARBIT_FINISH,
output wire oVRAM_ENA,
input wire iVRAM_BUSY,
output wire oVRAM_RW,
output wire [P_MEM_ADDR_N-1:0] oVRAM_ADDR,
output wire [31:0] oVRAM_DATA,
input wire iVRAM_VALID,
output wire oVRAM_BUSY,
input wire [31:0] iVRAM_DATA,
//Display
output wire oDISP_CLOCK,
output wire onDISP_RESET,
output wire oDISP_ENA,
output wire oDISP_BLANK,
output wire onDISP_HSYNC,
output wire onDISP_VSYNC,
output wire [9:0] oDISP_DATA_R,
output wire [9:0] oDISP_DATA_G,
output wire [9:0] oDISP_DATA_B
);
/****************************************************************
Hub Interface Controller
****************************************************************/
gci_std_display_hub_interface HUB_IF_CTRL(
//System
.iCLOCK(),
.inRESET(),
.iRESET_SYNC(),
//HUB(Reqest/Write)
.iHUB_REQ(),
.oHUB_BUSY(),
.iHUB_RW(),
.iHUB_ADDR(),
.iHUB_DATA(),
//HUB(Read)
.oHUB_VALID(),
.iHUB_BUSY(),
.oHUB_DATA(),
//Register(Request/Write)
.oREG_ENA(),
.oREG_RW(),
.oREG_ADDR(),
.oREG_DATA(),
//Register(Read)
.iREG_VALID(),
.oREG_BUSY(),
.iREG_DATA(),
//Command(Request/Write)
.oCOMM_VALID(),
.oCOMM_SEQ(),
.iCOMM_BUSY(),
.oCOMM_RW(),
.oCOMM_ADDR(),
.oCOMM_DATA(),
//Command(Read)
.iCOMM_VALID(),
.oCOMM_BUSY(),
.iCOMM_ADDR(),
.iCOMM_DATA()
);
/****************************************************************
Display Struct Register
****************************************************************/
wire register_info_charactor;
wire [1:0] register_info_color;
gci_std_display_register #(P_VRAM_SIZE) REGISTER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//Write
.iWR_VALID(register_ctrl_condition && !register_busy_condition && iIF_WR_RW),
.iWR_ADDR(iIF_WR_ADDR[3:0]),
.iWR_DATA(iIF_WR_DATA),
//Read
.iRD_VALID(register_ctrl_condition && !register_busy_condition && !iIF_WR_RW),
.oRD_BUSY(),
.iRD_ADDR(iIF_WR_ADDR[3:0]),
.oRD_VALID(),
.iRD_BUSY(),
.oRD_DATA(),
//Info
.oINFO_CHARACTER(register_info_charactor),
.oINFO_COLOR(register_info_color)
);
/****************************************************************
Display Command Decoder
****************************************************************/
wire command2request_valid;
wire request2command_busy;
wire [P_MEM_ADDR_N:0] command2request_addr;
wire [23:0] command2request_data;
gci_std_display_command #(
P_AREA_H,
P_AREA_V,
P_AREAA_HV_N,
P_MEM_ADDR_N
)COMMAND(
.iCLOCK(),
.inRESET(),
//Register
.iREG_MODE(register_info_charactor), //[0]Bitmap | [1]Charactor
//BUS
.iIF_VALID(display_ctrl_condition && !display_busy_condition || sequence_ctrl_condition && !sequence_busy_condition),
.iIF_SEQ(sequence_ctrl_condition),
.oIF_BUSY(),
.iIF_RW(),
.iIF_ADDR(),
.iIF_DATA(),
//Output
.oIF_VALID(command2request_valid),
.iIF_BUSY(request2command_busy),
.oIF_ADDR(command2request_addr),
.oIF_DATA(command2request_data)
);
/****************************************************************
Display Write/Read Controller
****************************************************************/
wire request2vramif_req;
wire vramif2request_ack;
wire request2vramif_finish;
wire vramif2request_break;
wire vramif2request_busy;
wire request2vramif_ena;
wire request2vramif_rw;
wire [P_MEM_ADDR_N-1:0] request2vramif_addr;
wire [7:0] request2vramif_r;
wire [7:0] request2vramif_g;
wire [7:0] request2vramif_b;
wire vramif2request_valid;
wire request2vramif_busy;
wire [31:0] vramif2request_data;
gci_std_display_request_controller #(
P_AREA_H,
P_AREA_V,
P_AREAA_HV_N,
P_MEM_ADDR_N
)(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//BUS
.iRQ_VALID(command2request_valid),
.oRQ_BUSY(request2command_busy),
.iRQ_ADDR(command2request_addr),
.iRQ_DATA(command2request_data),
//VRAM
.oRQ_VALID(),
.oRQ_BUSY(),
.oRQ_DATA(),
//VRAM IF
.oIF_REQ(request2vramif_req),
.iIF_ACK(vramif2request_ack),
.oIF_FINISH(request2vramif_finish),
.iIF_BREAK(vramif2request_break),
.iIF_BUSY(vramif2request_busy),
.oIF_ENA(request2vramif_ena),
.oIF_RW(request2vramif_rw),
.oIF_ADDR(request2vramif_addr),
.oIF_R(request2vramif_r),
.oIF_G(request2vramif_g),
.oIF_B(request2vramif_b),
.iIF_VALID(vramif2request_valid),
.oIF_BUSY(request2vramif_busy),
.iIF_DATA(vramif2request_data)
);
/****************************************************************
Vram Interface Controller
****************************************************************/
gci_std_display_vram_interface VRAM_IF_CTRL(
.iGCI_CLOCK(iGCI_CLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//IF0 (Priority IF0>IF1)
.iIF0_REQ(vramread2vramif_req),
.oIF0_ACK(vramif2vramread_ack),
.iIF0_FINISH(vramread2vramif_finish),
.iIF0_ENA(vramread2vramif_ena),
.oIF0_BUSY(vramif2vramread_busy),
.iIF0_RW(1'b0),
.iIF0_ADDR(vramread2vramif_addr + P_VRAM_INDEX),
.iIF0_DATA(32'h0),
.oIF0_VALID(vramif2vramread_valid),
.iIF0_BUSY(1'b0),
.oIF0_DATA(vramif2vramread_data),
//IF1
.iIF1_REQ(request2vramif_req),
.oIF1_ACK(vramif2request_ack),
.iIF1_FINISH(request2vramif_finish),
.oIF1_BREAK(vramif2request_break),
.iIF1_ENA(request2vramif_ena),
.oIF1_BUSY(vramif2request_busy),
.iIF1_RW(request2vramif_rw),
.iIF1_ADDR(request2vramif_addr + P_VRAM_INDEX),
.iIF1_DATA(request2vramif_data),
.oIF1_VALID(vramif2request_valid),
.iIF1_BUSY(request2vramif_busy),
.oIF1_DATA(vramif2request_data),
//Vram Interface
.oVRAM_ARBIT_REQ(oVRAM_ARBIT_REQ),
.iVRAM_ARBIT_ACK(iVRAM_ARBIT_ACK),
.oVRAM_ARBIT_FINISH(oVRAM_ARBIT_FINISH),
.oVRAM_ENA(oVRAM_ENA),
.iVRAM_BUSY(iVRAM_BUSY),
.oVRAM_RW(oVRAM_RW),
.oVRAM_ADDR(oVRAM_ADDR),
.oVRAM_DATA(oVRAM_DATA),
.iVRAM_VALID(iVRAM_VALID),
.oVRAM_BUSY(oVRAM_BUSY),
.iVRAM_DATA(iVRAM_DATAs)
);
/****************************************************************
Display Data Read Controller
****************************************************************/
wire vramread2vramif_req;
wire vramif2vramread_ack;
wire vramread2vramif_finish;
wire vramread2vramif_ena;
wire vramif2vramread_busy;
wire [P_MEM_ADDR_N-:0] vramread2vramif_addr;
wire vramif2vramread_valid;
wire [31:0] vramif2vramread_data;
gci_std_display_data_read VRAM_READ_CTRL(
.iGCI_CLOCK(iGCI_CLOCK),
.iDISP_CLOCK(iDISP_CLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//Read Request
.iRD_ENA(disptiming_data_req),
.iRD_SYNC(disptiming_data_sync),
.oRD_VALID(),
.oRD_DATA_R(oDISP_DATA_R),
.oRD_DATA_G(oDISP_DATA_G),
.oRD_DATA_B(oDISP_DATA_B),
//Memory IF
.oIF_REQ(vramread2vramif_req),
.iIF_ACK(vramif2vramread_ack),
.oIF_FINISH(vramread2vramif_finish),
.oIF_ENA(vramread2vramif_ena),
.iIF_BUSY(vramif2vramread_busy),
.oIF_ADDR(vramread2vramif_addr),
.iIF_VALID(vramif2vramread_valid),
.iIF_DATA(vramif2vramread_data)
);
/****************************************************************
Display Timing Generator
****************************************************************/
//Display timing
gci_std_display_timing_generator DISPLAY_TIMING(
.iDISP_CLOCK(iDISP_CLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
.oDATA_REQ(disptiming_data_req),
.oDATA_SYNC(disptiming_data_sync),
.onDISP_RESET(onDISP_RESET),
.oDISP_ENA(oDISP_ENA),
.oDISP_BLANK(oDISP_BLANK),
.onDISP_VSYNC(onDISP_VSYNC),
.onDISP_HSYNC(onDISP_HSYNC)
);
//Assign
assign oDISP_CLOCK = iDISP_CLOCK;
assign oIF_WR_BUSY = bus_req_wait;
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_TB_V
`define SKY130_FD_SC_LP__A32O_TB_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a32o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// wb_master_model.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - [email protected] (Miha Dolenc) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "wb_model_defines.v"
module wb_master_model
(
wb_rst_i ,
wb_clk_i ,
wbm_cyc_o ,
wbm_cti_o ,
wbm_bte_o ,
wbm_stb_o ,
wbm_we_o ,
wbm_adr_o ,
wbm_sel_o ,
wbm_dat_o ,
wbm_dat_i ,
wbm_ack_i ,
wbm_err_i ,
wbm_rty_i
);
// set the parameters to impossible values, so errors will be detected at compile time
parameter wb_dat_width = 1 ;
parameter wb_adr_width = 1 ;
parameter wb_sel_width = 1 ;
real Tperiod ;
input wb_rst_i ,
wb_clk_i ;
output wbm_cyc_o ;
reg wbm_cyc_o ;
output [ 2: 0] wbm_cti_o ;
reg [ 2: 0] wbm_cti_o ;
output [ 1: 0] wbm_bte_o ;
reg [ 1: 0] wbm_bte_o ;
output wbm_stb_o ;
reg wbm_stb_o ;
output wbm_we_o ;
reg wbm_we_o ;
output [wb_adr_width - 1:0] wbm_adr_o ;
reg [wb_adr_width - 1:0] wbm_adr_o ;
output [wb_sel_width - 1:0] wbm_sel_o ;
reg [wb_sel_width - 1:0] wbm_sel_o ;
output [wb_dat_width - 1:0] wbm_dat_o ;
reg [wb_dat_width - 1:0] wbm_dat_o ;
input [wb_dat_width - 1:0] wbm_dat_i ;
input wbm_ack_i ;
input wbm_err_i ;
input wbm_rty_i ;
event write_transfer ;
event read_transfer ;
reg [wb_adr_width - 1:0] write_adr ;
reg [wb_sel_width - 1:0] write_sel ;
reg [wb_dat_width - 1:0] write_dat ;
reg [wb_adr_width - 1:0] read_adr ;
reg [wb_sel_width - 1:0] read_sel ;
reg [wb_dat_width - 1:0] read_dat ;
reg [wb_adr_width - 1:0] next_write_adr ;
reg [wb_sel_width - 1:0] next_write_sel ;
reg [wb_dat_width - 1:0] next_write_dat ;
reg [ 2: 0] next_write_cti ;
reg [ 1: 0] next_write_bte ;
event write_accepted ;
event write_request ;
reg [wb_adr_width - 1:0] next_read_adr ;
reg [wb_sel_width - 1:0] next_read_sel ;
reg [ 2: 0] next_read_cti ;
reg [ 1: 0] next_read_bte ;
event read_accepted ;
event read_request ;
real Tsetup ;
real Thold ;
initial Tsetup = 0.0 ;
initial Thold = 0.0 ;
reg reset_done ;
initial reset_done = 1'b0 ;
event error_event ;
reg [ 799: 0] error_message ;
initial
fork
begin
forever
begin
@(wb_rst_i) ;
if ((wb_rst_i ^ wb_rst_i) !== 1'b0)
begin
reset_done = 1'b0 ;
error_message = "Invalid WISHBONE reset line value detected" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
begin
reset_done = 1'b0 ;
end
end
end
begin
forever
begin
@(wb_rst_i) ;
if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
begin
@(posedge wb_clk_i or wb_rst_i) ;
if (wb_rst_i !== `WB_MODEL_RST_ACTIVE)
begin
error_message = "Reset de-activated prior to at least one positive clock transition" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
else
begin
reset_done = 1'b1 ;
end
end
end
end
join
always@(wb_rst_i)
begin
if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
wbm_cyc_o <= 1'b0 ;
end
reg access_in_progress ;
initial access_in_progress = 1'b0 ;
task start_write ;
input `WBM_MODEL_WRITE_IN_TYPE write_stim_i ;
output `WBM_MODEL_WRITE_OUT_TYPE write_res_o ;
reg [31: 0] num_of_slave_waits ;
reg end_access ;
begin:main
write_res_o = 'h0 ;
if (access_in_progress === 1'b1)
begin
error_message = "Task called when some other access was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ;
disable main ;
end
if (reset_done !== 1'b1)
begin
error_message = "Task called before reset was applied to the design" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ;
disable main ;
end
access_in_progress = 1'b1 ;
end_access = write_stim_i`WBM_MODEL_WRITE_LAST ;
if (write_stim_i`WBM_MODEL_WRITE_FAST_B2B !== 1'b1)
@(posedge wb_clk_i) ;
wbm_cyc_o <= #(Tperiod - Tsetup) 1'b1 ;
insert_waits(write_stim_i`WBM_MODEL_WRITE_WAITS, 'h0, num_of_slave_waits) ;
if ((num_of_slave_waits ^ num_of_slave_waits) === 'h0)
begin
error_message = "Slave responded to initial write access" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
num_of_slave_waits = 0 ;
wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ;
wbm_we_o <= #(Tperiod - Tsetup) 1'b1 ;
wbm_adr_o <= #(Tperiod - Tsetup) next_write_adr ;
wbm_dat_o <= #(Tperiod - Tsetup) get_write_dat(next_write_dat, next_write_sel) ;
wbm_sel_o <= #(Tperiod - Tsetup) next_write_sel ;
wbm_cti_o <= #(Tperiod - Tsetup) next_write_cti ;
wbm_bte_o <= #(Tperiod - Tsetup) next_write_bte ;
-> write_accepted ;
@(posedge wb_clk_i) ;
while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < write_stim_i`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS))
begin
num_of_slave_waits = num_of_slave_waits + 1'b1 ;
write_adr = wbm_adr_o ;
write_sel = wbm_sel_o ;
write_dat = wbm_dat_o ;
-> write_request ;
@(posedge wb_clk_i) ;
end
if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0))
begin
error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ;
end
else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1)
begin
error_message = "Cycle terminated because invalid slave response was received" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ;
end
else
begin
write_res_o`WBM_MODEL_WRITE_SLAVE_WAITS = num_of_slave_waits ;
write_res_o`WBM_MODEL_WRITE_SLAVE_ACK = wbm_ack_i ;
write_res_o`WBM_MODEL_WRITE_SLAVE_ERR = wbm_err_i ;
write_res_o`WBM_MODEL_WRITE_SLAVE_RTY = wbm_rty_i ;
if (wbm_ack_i === 1'b1)
begin
write_adr = wbm_adr_o ;
write_dat = wbm_dat_o ;
write_sel = wbm_sel_o ;
-> write_transfer ;
end
end
if (end_access)
begin
wbm_cyc_o <= #(Thold) 1'b0 ;
wbm_stb_o <= #(Thold) 1'bx ;
wbm_we_o <= #(Thold) 1'bx ;
wbm_sel_o <= #(Thold) 'hx ;
wbm_adr_o <= #(Thold) 'hx ;
wbm_dat_o <= #(Thold) 'hx ;
wbm_cti_o <= #(Thold) 'hx ;
wbm_bte_o <= #(Thold) 'hx ;
access_in_progress = 1'b0 ;
end
end
endtask // start_write
task subsequent_write ;
input `WBM_MODEL_WRITE_IN_TYPE write_stim_i ;
output `WBM_MODEL_WRITE_OUT_TYPE write_res_o ;
reg [31: 0] num_of_slave_waits ;
reg end_access ;
begin:main
write_res_o = 'h0 ;
if (access_in_progress !== 1'b1)
begin
error_message = "Task called when no access was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ;
disable main ;
end
end_access = write_stim_i`WBM_MODEL_WRITE_LAST ;
insert_waits(write_stim_i`WBM_MODEL_WRITE_WAITS, 'h0, num_of_slave_waits) ;
if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0)
begin
num_of_slave_waits = write_stim_i`WBM_MODEL_WRITE_WAITS ;
end
wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ;
wbm_we_o <= #(Tperiod - Tsetup) 1'b1 ;
wbm_adr_o <= #(Tperiod - Tsetup) next_write_adr ;
wbm_dat_o <= #(Tperiod - Tsetup) get_write_dat(next_write_dat, next_write_sel) ;
wbm_sel_o <= #(Tperiod - Tsetup) next_write_sel ;
wbm_cti_o <= #(Tperiod - Tsetup) next_write_cti ;
wbm_bte_o <= #(Tperiod - Tsetup) next_write_bte ;
-> write_accepted ;
@(posedge wb_clk_i) ;
while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < write_stim_i`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS))
begin
num_of_slave_waits = num_of_slave_waits + 1'b1 ;
write_adr = wbm_adr_o ;
write_sel = wbm_sel_o ;
write_dat = wbm_dat_o ;
-> write_request ;
@(posedge wb_clk_i) ;
end
if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0))
begin
error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ;
end
else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1)
begin
error_message = "Cycle terminated because invalid slave response was received" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ;
end
else
begin
write_res_o`WBM_MODEL_WRITE_SLAVE_WAITS = num_of_slave_waits ;
write_res_o`WBM_MODEL_WRITE_SLAVE_ACK = wbm_ack_i ;
write_res_o`WBM_MODEL_WRITE_SLAVE_ERR = wbm_err_i ;
write_res_o`WBM_MODEL_WRITE_SLAVE_RTY = wbm_rty_i ;
if (wbm_ack_i === 1'b1)
begin
write_adr = wbm_adr_o ;
write_dat = wbm_dat_o ;
write_sel = wbm_sel_o ;
-> write_transfer ;
end
end
if (end_access)
begin
wbm_cyc_o <= #(Thold) 1'b0 ;
wbm_stb_o <= #(Thold) 1'bx ;
wbm_we_o <= #(Thold) 1'bx ;
wbm_sel_o <= #(Thold) 'hx ;
wbm_adr_o <= #(Thold) 'hx ;
wbm_dat_o <= #(Thold) 'hx ;
wbm_cti_o <= #(Thold) 'hx ;
wbm_bte_o <= #(Thold) 'hx ;
access_in_progress = 1'b0 ;
end
end
endtask // subsequent_write
task start_read ;
input `WBM_MODEL_READ_IN_TYPE read_stim_i ;
output `WBM_MODEL_READ_OUT_TYPE read_res_o ;
reg [31: 0] num_of_slave_waits ;
reg end_access ;
begin:main
read_res_o = 'h0 ;
if (access_in_progress === 1'b1)
begin
error_message = "Task called when some other access was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
read_res_o`WBM_MODEL_READ_STIM_ERR = 1'b1 ;
disable main ;
end
if (reset_done !== 1'b1)
begin
error_message = "Task called before reset was applied to the design" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
read_res_o`WBM_MODEL_READ_STIM_ERR = 1'b1 ;
disable main ;
end
access_in_progress = 1'b1 ;
end_access = read_stim_i`WBM_MODEL_READ_LAST ;
if (read_stim_i`WBM_MODEL_READ_FAST_B2B !== 1'b1)
@(posedge wb_clk_i) ;
wbm_cyc_o <= #(Tperiod - Tsetup) 1'b1 ;
insert_waits(read_stim_i`WBM_MODEL_READ_WAITS, 'h0, num_of_slave_waits) ;
if ((num_of_slave_waits ^ num_of_slave_waits) === 'h0)
begin
error_message = "Slave responded to initial read access" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
num_of_slave_waits = 0 ;
wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ;
wbm_we_o <= #(Tperiod - Tsetup) 1'b0 ;
wbm_adr_o <= #(Tperiod - Tsetup) next_read_adr ;
wbm_sel_o <= #(Tperiod - Tsetup) next_read_sel ;
wbm_cti_o <= #(Tperiod - Tsetup) next_read_cti ;
wbm_bte_o <= #(Tperiod - Tsetup) next_read_bte ;
-> read_accepted ;
@(posedge wb_clk_i) ;
while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < read_stim_i`WBM_MODEL_READ_ALLOWED_SLAVE_WAITS))
begin
num_of_slave_waits = num_of_slave_waits + 1'b1 ;
read_adr = wbm_adr_o ;
read_sel = wbm_sel_o ;
-> read_request ;
@(posedge wb_clk_i) ;
end
if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0))
begin
error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
read_res_o`WBM_MODEL_READ_DESIGN_ERR = 1'b1 ;
end
else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1)
begin
error_message = "Cycle terminated because invalid slave response was received" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
read_res_o`WBM_MODEL_READ_DESIGN_ERR = 1'b1 ;
end
else
begin
read_res_o`WBM_MODEL_READ_SLAVE_WAITS = num_of_slave_waits ;
read_res_o`WBM_MODEL_READ_SLAVE_ACK = wbm_ack_i ;
read_res_o`WBM_MODEL_READ_SLAVE_ERR = wbm_err_i ;
read_res_o`WBM_MODEL_READ_SLAVE_RTY = wbm_rty_i ;
if (wbm_ack_i === 1'b1)
begin
read_adr = wbm_adr_o ;
read_dat = wbm_dat_i ;
read_sel = wbm_sel_o ;
-> read_transfer ;
end
end
if (end_access)
begin
wbm_cyc_o <= #(Thold) 1'b0 ;
wbm_stb_o <= #(Thold) 1'bx ;
wbm_we_o <= #(Thold) 1'bx ;
wbm_sel_o <= #(Thold) 'hx ;
wbm_adr_o <= #(Thold) 'hx ;
wbm_cti_o <= #(Thold) 'hx ;
wbm_bte_o <= #(Thold) 'hx ;
access_in_progress = 1'b0 ;
end
end
endtask // start_read
task subsequent_read ;
input `WBM_MODEL_READ_IN_TYPE read_stim_i ;
output `WBM_MODEL_READ_OUT_TYPE read_res_o ;
reg [31: 0] num_of_slave_waits ;
reg end_access ;
begin:main
read_res_o = 'h0 ;
if (access_in_progress !== 1'b1)
begin
error_message = "Task called when no access was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
read_res_o`WBM_MODEL_READ_STIM_ERR = 1'b1 ;
disable main ;
end
end_access = read_stim_i`WBM_MODEL_READ_LAST ;
insert_waits(read_stim_i`WBM_MODEL_READ_WAITS, 'h1, num_of_slave_waits) ;
if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0)
begin
num_of_slave_waits = read_stim_i`WBM_MODEL_READ_WAITS ;
end
wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ;
wbm_we_o <= #(Tperiod - Tsetup) 1'b0 ;
wbm_adr_o <= #(Tperiod - Tsetup) next_read_adr ;
wbm_sel_o <= #(Tperiod - Tsetup) next_read_sel ;
wbm_cti_o <= #(Tperiod - Tsetup) next_read_cti ;
wbm_bte_o <= #(Tperiod - Tsetup) next_read_bte ;
-> read_accepted ;
@(posedge wb_clk_i) ;
while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < read_stim_i`WBM_MODEL_READ_ALLOWED_SLAVE_WAITS))
begin
num_of_slave_waits = num_of_slave_waits + 1'b1 ;
read_adr = wbm_adr_o ;
read_sel = wbm_sel_o ;
-> read_request ;
@(posedge wb_clk_i) ;
end
if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0))
begin
error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
read_res_o`WBM_MODEL_READ_DESIGN_ERR = 1'b1 ;
end
else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1)
begin
error_message = "Cycle terminated because invalid slave response was received" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end_access = 1'b1 ;
read_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ;
end
else
begin
read_res_o`WBM_MODEL_READ_SLAVE_WAITS = num_of_slave_waits ;
read_res_o`WBM_MODEL_READ_SLAVE_ACK = wbm_ack_i ;
read_res_o`WBM_MODEL_READ_SLAVE_ERR = wbm_err_i ;
read_res_o`WBM_MODEL_READ_SLAVE_RTY = wbm_rty_i ;
if (wbm_ack_i === 1'b1)
begin
read_adr = wbm_adr_o ;
read_dat = wbm_dat_i ;
read_sel = wbm_sel_o ;
-> read_transfer ;
end
end
if (end_access)
begin
wbm_cyc_o <= #(Thold) 1'b0 ;
wbm_stb_o <= #(Thold) 1'bx ;
wbm_we_o <= #(Thold) 1'bx ;
wbm_sel_o <= #(Thold) 'hx ;
wbm_adr_o <= #(Thold) 'hx ;
wbm_cti_o <= #(Thold) 'hx ;
wbm_bte_o <= #(Thold) 'hx ;
access_in_progress = 1'b0 ;
end
end
endtask // subsequent_read
task insert_waits ;
input [31: 0] num_of_waits_i ;
input read_req_on_wait_i ;
output [31: 0] num_of_slave_waits ;
reg [31: 0] cur_num_of_waits ;
begin
num_of_slave_waits = 'hx ;
for (cur_num_of_waits = 0 ; cur_num_of_waits < num_of_waits_i ; cur_num_of_waits = cur_num_of_waits + 1'b1)
begin
wbm_stb_o <= #(Thold) 1'b0 ;
wbm_adr_o <= #(Thold) 'hx ;
wbm_sel_o <= #(Thold) 'hx ;
wbm_we_o <= #(Thold) 'hx ;
wbm_dat_o <= #(Thold) 'hx ;
wbm_cti_o <= #(Thold) 'hx ;
wbm_bte_o <= #(Thold) 'hx ;
@(posedge wb_clk_i) ;
if (read_req_on_wait_i)
begin
if ( (wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) )
begin
if ( (next_read_cti === 'h1) | (next_read_cti === 'h2) | (next_read_cti === 'h7) )
begin
read_adr = next_read_adr ;
read_sel = next_read_sel ;
-> read_request ;
end
end
end
if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0)
begin
if ((wbm_ack_i !== 1'b0) | (wbm_err_i !== 1'b0) | (wbm_rty_i !== 1'b0))
num_of_slave_waits = cur_num_of_waits ;
end
end
end
endtask
always@(posedge wb_clk_i)
begin:wb_monitoring_blk
reg burst_in_progress ;
reg ack_prev ;
reg rty_prev ;
reg err_prev ;
reg stb_prev ;
reg cyc_prev ;
reg [wb_dat_width - 1:0] sdat_prev ;
ack_prev <= wbm_ack_i ;
rty_prev <= wbm_rty_i ;
err_prev <= wbm_err_i ;
stb_prev <= wbm_stb_o ;
cyc_prev <= wbm_cyc_o ;
sdat_prev <= wbm_dat_i ;
if (wb_rst_i === `WB_MODEL_RST_ACTIVE)
begin
if (wbm_ack_i !== 1'b0)
begin
error_message = "ACK input signal was not de-asserted while reset was asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if (wbm_err_i !== 1'b0)
begin
error_message = "ERR input signal was not de-asserted while reset was asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if (wbm_rty_i !== 1'b0)
begin
error_message = "RTY input signal was not de-asserted while reset was asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
burst_in_progress <= 1'b0 ;
end
else
begin
if (wbm_cyc_o !== 1'b1)
begin
if (wbm_ack_i !== 1'b0)
begin
error_message = "ACK input signal was asserted while no cycle was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if (wbm_err_i !== 1'b0)
begin
error_message = "ERR input signal was asserted while no cycle was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if (wbm_rty_i !== 1'b0)
begin
error_message = "RTY input signal was asserted while no cycle was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
end
else
begin
if (burst_in_progress !== 1'b1)
begin
if ((wbm_ack_i !== 1'b0) & (wbm_stb_o !== 1'b1))
begin
error_message = "ACK input signal was asserted while STB was de-asserted and no burst was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if ((wbm_err_i !== 1'b0) & (wbm_stb_o !== 1'b1))
begin
error_message = "ERR input signal was asserted while STB was de-asserted and no burst was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if ((wbm_rty_i !== 1'b0) & (wbm_stb_o !== 1'b1))
begin
error_message = "RTY input signal was asserted while STB was de-asserted and no burst was in progress" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
end
else
begin
if ((ack_prev !== 1'b0) & (stb_prev !== 1'b1))
begin
if (wbm_ack_i !== 1'b1)
begin
error_message = "Slave de-asserted ACK signal during burst cycle without receiving STB asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if (wbm_we_o !== 'b1)
begin
if (sdat_prev !== wbm_dat_i)
begin
error_message = "Slave changed the value of data output bus during burst cycle without receiving STB asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
end
end
if ((rty_prev !== 1'b0) & (stb_prev !== 1'b1) & (wbm_rty_i !== 1'b1))
begin
error_message = "Slave de-asserted RTY signal during burst cycle without receiving STB asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
if ((err_prev !== 1'b0) & (stb_prev !== 1'b1) & (wbm_err_i !== 1'b1))
begin
error_message = "Slave de-asserted ERR signal during burst cycle without receiving STB asserted" ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
end
if (wbm_stb_o === 1'b1)
begin
case (wbm_cti_o)
3'b000:burst_in_progress <= 1'b0 ;
3'b001:burst_in_progress <= 1'b1 ;
3'b010:burst_in_progress <= 1'b1 ;
3'b011:burst_in_progress <= 1'b0 ;
3'b100:burst_in_progress <= 1'b0 ;
3'b101:burst_in_progress <= 1'b0 ;
3'b110:burst_in_progress <= 1'b0 ;
3'b111:if (wbm_ack_i === 1'b1) burst_in_progress <= 1'b0 ;
default:
begin
error_message = "WISHBONE master sent invalid cycle type identifier" ;
burst_in_progress <= 1'bx ;
`WB_MODEL_ERR_MSG(error_message) ;
-> error_event ;
end
endcase
if (wbm_err_i === 1'b1)
burst_in_progress <= 1'b0 ;
if (wbm_rty_i === 1'b1)
burst_in_progress <= 1'b0 ;
end
end
end
end
function [wb_dat_width - 1:0] get_write_dat ;
input [wb_dat_width - 1:0] dat_i ;
input [wb_sel_width - 1:0] sel_i ;
integer cur_bit ;
reg [wb_dat_width - 1:0] dat_o ;
begin
for (cur_bit = 0 ; cur_bit < wb_dat_width ; cur_bit = cur_bit + 1'b1)
begin
if (sel_i[cur_bit >> 3] === 1'b1)
dat_o[cur_bit] = dat_i[cur_bit] ;
else
dat_o[cur_bit] = 1'bx ;
end
get_write_dat = dat_o ;
end
endfunction // get_write_dat
endmodule
|
module ram0 #(
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 8,
parameter MAX_ADDRESS = 1023
) (
// Write port
input wrclk,
input [DATA_WIDTH-1:0] di,
input wren,
input [ADDR_WIDTH-1:0] wraddr,
// Read port
input rdclk,
input rden,
input [ADDR_WIDTH-1:0] rdaddr,
output reg [DATA_WIDTH-1:0] do);
(* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram[0:MAX_ADDRESS];
always @ (posedge wrclk) begin
if (wren == 1) begin
ram[wraddr] <= di;
end
end
always @ (posedge rdclk) begin
if (rden == 1) begin
do <= ram[rdaddr];
end
end
endmodule
module bram_test #(
parameter ADDR_WIDTH = 10,
parameter DATA_WIDTH = 8,
parameter ADDRESS_STEP = 1,
parameter MAX_ADDRESS = 1023
) (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [ADDR_WIDTH-1:0] write_address;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
wire [DATA_WIDTH-1:0] write_data;
wire write_enable;
wire read_enable = !write_enable;
wire [ADDR_WIDTH-1:0] rom_read_address;
wire [DATA_WIDTH-1:0] rom_read_data = 16'b0;
//assign rom_read_data[9:0] = rom_read_address;
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [ADDR_WIDTH-1:0] error_address;
wire [DATA_WIDTH-1:0] expected_data;
wire [DATA_WIDTH-1:0] actual_data;
RAM_TEST #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.IS_DUAL_PORT(1),
.ADDRESS_STEP(ADDRESS_STEP),
.MAX_ADDRESS(MAX_ADDRESS)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.write_data(write_data),
.write_enable(write_enable),
.read_address(read_address),
.write_address(write_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
ram0 #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.MAX_ADDRESS(MAX_ADDRESS)
) bram (
// Write port
.wrclk(clk),
.di(write_data),
.wren(write_enable),
.wraddr(write_address),
// Read port
.rdclk(clk),
.rden(read_enable),
.rdaddr(read_address),
.do(read_data)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) output_logic (
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_BLACKBOX_V
|
// Fixed delay shift registed made of various configurations of chained SRL16s
// and SRL32s.
`ifndef __ICARUS__
`include "srlc16e.v"
`endif
module srl_chain_mixed #
(
parameter [0:0] BEGIN_WITH_SRL16 = 0, // Start with SRL16.
parameter [1:0] NUM_SRL32 = 0, // SRL32 count in the middle.
parameter [0:0] END_WITH_SRL16 = 0, // End on SRL16.
parameter SITE = "" // Site to LOC all bels to
)
(
input wire CLK,
input wire CE,
input wire D,
output wire Q
);
// ============================================================================
// SRL16 at the beginning
wire d;
generate if (BEGIN_WITH_SRL16) begin
// Use SRL16
(* KEEP, DONT_TOUCH *)
SRLC16E beg_srl16
(
.CLK (CLK),
.CE (CE),
.D (D),
.A0 (0),
.A1 (0),
.A2 (0),
.A3 (0),
.Q15 (d)
);
end else begin
// No SRL16
assign d = D;
end endgenerate
// ============================================================================
// Chain of 0 or more SRL32s
wire q;
genvar i;
generate if (NUM_SRL32 > 0) begin
wire [NUM_SRL32-1:0] srl_d;
wire [NUM_SRL32-1:0] srl_q31;
assign srl_d[0] = d;
for(i=0; i<NUM_SRL32; i=i+1) begin
(* KEEP, DONT_TOUCH *)
SRLC32E srl
(
.CLK (CLK),
.CE (CE),
.A (5'd0),
.D (srl_d[i]),
.Q31 (srl_q31[i])
);
if (i > 0) begin
assign srl_d[i] = srl_q31[i-1];
end
end
assign q = srl_q31[NUM_SRL32-1];
end else begin
// No SRL32s
assign q = d;
end endgenerate
// ============================================================================
// SRL16 at the end
generate if (END_WITH_SRL16) begin
// Use SRL16
(* KEEP, DONT_TOUCH *)
SRLC16E end_srl16
(
.CLK (CLK),
.CE (CE),
.D (q),
.A0 (0),
.A1 (0),
.A2 (0),
.A3 (0),
.Q15 (Q)
);
end else begin
// No SRL16
assign Q = q;
end endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire u_vpwr_vgnd1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , u_vpwr_vgnd1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_intp2_2 (
clk,
data,
// outputs
intp2_0,
intp2_1);
input clk;
input [15:0] data;
// outputs
output [15:0] intp2_0;
output [15:0] intp2_1;
// internal registers
reg [15:0] data_s0 = 'd0;
reg [15:0] data_s1 = 'd0;
reg [15:0] data_s2 = 'd0;
reg [15:0] data_s3 = 'd0;
reg [15:0] data_s4 = 'd0;
reg [15:0] data_s5 = 'd0;
// delay registers
always @(posedge clk) begin
data_s0 <= data_s1;
data_s1 <= data_s2;
data_s2 <= data_s3;
data_s3 <= data_s4;
data_s4 <= data_s5;
data_s5 <= data;
end
// mac (fir filter)
ad_mac_1 i_mac_1 (
.clk (clk),
.data_s0 (data_s0),
.data_s1 (data_s1),
.data_s2 (data_s2),
.data_s3 (data_s3),
.data_s4 (data_s4),
.data_s5 (data_s5),
.mac_data_0 (intp2_0),
.mac_data_1 (intp2_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Hybrid PWM / Sigma Delta converter
//
// Uses 5-bit PWM, wrapped within a 10-bit Sigma Delta, with the intention of
// increasing the pulse width, since narrower pulses seem to equate to more noise
module hybrid_pwm_sd
(
input clk,
input n_reset,
input [15:0] din,
output dout
);
reg [4:0] pwmcounter;
reg [4:0] pwmthreshold;
reg [33:0] scaledin;
reg [15:0] sigma;
reg out;
assign dout=out;
always @(posedge clk, negedge n_reset) // FIXME reset logic;
begin
if(!n_reset)
begin
sigma<=16'b00000100_00000000;
pwmthreshold<=5'b10000;
pwmcounter<=5'd0;
scaledin<=34'd0;
end
else
begin
pwmcounter<=pwmcounter+1;
if(pwmcounter==pwmthreshold)
out<=1'b0;
if(pwmcounter==5'b11111) // Update threshold when pwmcounter reaches zero
begin
// Pick a new PWM threshold using a Sigma Delta
scaledin<=33'd134217728 // (1<<(16-5))<<16, offset to keep centre aligned.
+({1'b0,din}*61440); // 30<<(16-5)-1;
sigma<=scaledin[31:16]+{5'b000000,sigma[10:0]}; // Will use previous iteration's scaledin value
pwmthreshold<=sigma[15:11]; // Will lag 2 cycles behind, but shouldn't matter.
out<=1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_1_V
`define SKY130_FD_SC_HD__O2111A_1_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111a_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:43:18 02/23/2016
// Design Name: DebugUnit
// Module Name: C:/Users/Juanjo/Documents/Juanjo/Facu/Arquitectura/Trabajo Final/finalArquitectura/TestDatapathPart1/PipeAndDebug/debugUnit_test.v
// Project Name: PipeAndDebug
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DebugUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module debugUnit_test;
// Inputs
reg clock;
reg reset;
reg endOfProgram;
reg [7:0] uartFifoDataIn;
reg uartDataAvailable;
reg [7:0] FE_pc;
reg [31:0] IF_ID_instruction;
reg [7:0] IF_ID_pcNext;
reg [3:0] ID_EX_aluOperation;
reg [31:0] ID_EX_sigExt;
reg [31:0] ID_EX_readData1;
reg [31:0] ID_EX_readData2;
reg ID_EX_aluSrc;
reg ID_EX_aluShiftImm;
reg [3:0] ID_EX_memWrite;
reg ID_EX_memToReg;
reg [1:0] ID_EX_memReadWidth;
reg [4:0] ID_EX_rs;
reg [4:0] ID_EX_rt;
reg [4:0] ID_EX_rd;
reg [4:0] ID_EX_sa;
reg ID_EX_regDst;
reg ID_EX_loadImm;
reg ID_EX_regWrite;
reg [4:0] EX_MEM_writeRegister;
reg [31:0] EX_MEM_writeData;
reg [31:0] EX_MEM_aluOut;
reg EX_MEM_regWrite;
reg EX_MEM_memToReg;
reg [3:0] EX_MEM_memWrite;
reg [1:0] EX_MEM_memReadWidth;
reg [4:0] MEM_WB_writeRegister;
reg [31:0] MEM_WB_aluOut;
reg [31:0] MEM_WB_memoryOut;
reg MEM_WB_regWrite;
reg MEM_WB_memToReg;
// Outputs
wire [7:0] dataToUartOutFifo;
wire readFifoFlag;
wire writeFifoFlag;
wire pipeEnable;
wire pipeReset;
wire ledStep;
wire ledCont;
wire ledIdle;
wire ledSend;
// Instantiate the Unit Under Test (UUT)
DebugUnit uut (
.clock(clock),
.reset(reset),
.endOfProgram(endOfProgram),
.uartFifoDataIn(uartFifoDataIn),
.uartDataAvailable(uartDataAvailable),
.FE_pc(FE_pc),
.IF_ID_instruction(IF_ID_instruction),
.IF_ID_pcNext(IF_ID_pcNext),
.ID_EX_aluOperation(ID_EX_aluOperation),
.ID_EX_sigExt(ID_EX_sigExt),
.ID_EX_readData1(ID_EX_readData1),
.ID_EX_readData2(ID_EX_readData2),
.ID_EX_aluSrc(ID_EX_aluSrc),
.ID_EX_aluShiftImm(ID_EX_aluShiftImm),
.ID_EX_memWrite(ID_EX_memWrite),
.ID_EX_memToReg(ID_EX_memToReg),
.ID_EX_memReadWidth(ID_EX_memReadWidth),
.ID_EX_rs(ID_EX_rs),
.ID_EX_rt(ID_EX_rt),
.ID_EX_rd(ID_EX_rd),
.ID_EX_sa(ID_EX_sa),
.ID_EX_regDst(ID_EX_regDst),
.ID_EX_loadImm(ID_EX_loadImm),
.ID_EX_regWrite(ID_EX_regWrite),
.EX_MEM_writeRegister(EX_MEM_writeRegister),
.EX_MEM_writeData(EX_MEM_writeData),
.EX_MEM_aluOut(EX_MEM_aluOut),
.EX_MEM_regWrite(EX_MEM_regWrite),
.EX_MEM_memToReg(EX_MEM_memToReg),
.EX_MEM_memWrite(EX_MEM_memWrite),
.EX_MEM_memReadWidth(EX_MEM_memReadWidth),
.MEM_WB_writeRegister(MEM_WB_writeRegister),
.MEM_WB_aluOut(MEM_WB_aluOut),
.MEM_WB_memoryOut(MEM_WB_memoryOut),
.MEM_WB_regWrite(MEM_WB_regWrite),
.MEM_WB_memToReg(MEM_WB_memToReg),
.dataToUartOutFifo(dataToUartOutFifo),
.readFifoFlag(readFifoFlag),
.writeFifoFlag(writeFifoFlag),
.pipeEnable(pipeEnable),
.pipeReset(pipeReset),
.ledStep(ledStep),
.ledCont(ledCont),
.ledIdle(ledIdle),
.ledSend(ledSend)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
endOfProgram = 0;
uartFifoDataIn = 0;
uartDataAvailable = 0;
FE_pc = 0;
IF_ID_instruction = 0;
IF_ID_pcNext = 0;
ID_EX_aluOperation = 0;
ID_EX_sigExt = 0;
ID_EX_readData1 = 0;
ID_EX_readData2 = 0;
ID_EX_aluSrc = 0;
ID_EX_aluShiftImm = 0;
ID_EX_memWrite = 0;
ID_EX_memToReg = 0;
ID_EX_memReadWidth = 0;
ID_EX_rs = 0;
ID_EX_rt = 0;
ID_EX_rd = 0;
ID_EX_sa = 0;
ID_EX_regDst = 0;
ID_EX_loadImm = 0;
ID_EX_regWrite = 0;
EX_MEM_writeRegister = 0;
EX_MEM_writeData = 0;
EX_MEM_aluOut = 0;
EX_MEM_regWrite = 0;
EX_MEM_memToReg = 0;
EX_MEM_memWrite = 0;
EX_MEM_memReadWidth = 0;
MEM_WB_writeRegister = 0;
MEM_WB_aluOut = 0;
MEM_WB_memoryOut = 0;
MEM_WB_regWrite = 0;
MEM_WB_memToReg = 0;
// Wait 100 ns for global reset to finish
#10;
reset = 1;
#4;
reset = 0;
#4;
uartFifoDataIn = "s";
#4;
uartDataAvailable = 1;
#4;
uartDataAvailable = 0;
#4;
uartFifoDataIn = "n";
uartDataAvailable = 1;
#4;
// Add stimulus here
end
always begin
clock = ~clock;
#1;
end
endmodule
|
module stack(DataIO, Reset, Push, Pop,
SP, Full, Empty, Err);
// declare input, output and inout ports
inout [3:0] DataIO;
input Push, Pop, Reset;
output Full, Empty, Err;
output [2:0] SP;
// Declare registers
reg Full, Empty, Err;
reg [2:0] SP;
reg [3:0] Stack [7:0];
reg [3:0] DataR;
//Continous assignment of DataIO to DataR register, with delay 0
wire [3:0] #(0) DataIO = DataR;
always @(posedge Push or posedge Pop or posedge Reset)
begin
if (Push == 1)
begin
//WHen the stack is empty
if (Empty == 1)
begin
Stack[SP] = DataIO;
Empty = 0;
if (Err == 1)
Err = 0;
end
else if (Full == 1) //When the stack is full
begin
Stack[SP] = DataIO;
Err = 1;
end
else
begin
SP = SP + 1;
Stack[SP] = DataIO;
if (SP == 3'b111)
Full = 1;
end
end
if (Pop == 1) //if SP indicates the last location but
begin // the stack is not empty
if ((SP == 3'b000) && (Empty != 1))
begin
DataR = Stack[SP];
Empty = 1;
end
else if (Empty == 1) //When the stack is empty
begin
DataR = Stack[SP];
Err = 1;
end
else
begin
DataR = Stack[SP];
if (SP != 3'b000)
SP = SP - 1;
//if the stack is full
if (Err == 1) Err = 0;
if (Full == 1) Full = 0;
end
end
if (Reset == 1)
begin
DataR = 4'bzzzz;
SP = 3'b0;
Full = 0;
Empty = 0;
Err = 0;
end
end
always @(negedge Pop)
begin
DataR = 4'bzzzz;
end
endmodule // stack |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:44:51 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_0_stub.v
// Design : led_controller_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_4_V
`define SKY130_FD_SC_HDLL__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_4_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_fifo (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [C_DATA_WIDTH-1:0] m_axis_data,
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [C_DATA_WIDTH-1:0] s_axis_data,
output s_axis_empty
);
parameter C_DATA_WIDTH = 64;
parameter C_CLKS_ASYNC = 1;
parameter C_ADDRESS_WIDTH = 4;
generate if (C_ADDRESS_WIDTH == 0) begin
reg [C_DATA_WIDTH-1:0] ram;
reg s_axis_waddr = 1'b0;
reg m_axis_raddr = 1'b0;
wire m_axis_waddr;
wire s_axis_raddr;
sync_bits #(
.NUM_BITS(1),
.CLK_ASYNC(C_CLKS_ASYNC)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(s_axis_waddr),
.out(m_axis_waddr)
);
sync_bits #(
.NUM_BITS(1),
.CLK_ASYNC(C_CLKS_ASYNC)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(m_axis_raddr),
.out(s_axis_raddr)
);
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
assign s_axis_empty = s_axis_raddr == s_axis_waddr;
always @(posedge s_axis_aclk) begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
ram <= s_axis_data;
end
end
end
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
m_axis_raddr <= 1'b0;
end else begin
if (m_axis_valid & m_axis_ready)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
assign m_axis_data = ram;
end else begin
reg [C_DATA_WIDTH-1:0] ram[0:2**C_ADDRESS_WIDTH-1];
wire [C_ADDRESS_WIDTH-1:0] s_axis_waddr;
wire [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next;
if (C_CLKS_ASYNC == 1) begin
fifo_address_gray_pipelined #(
.C_ADDRESS_WIDTH(C_ADDRESS_WIDTH)
) i_address_gray (
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_raddr_next(m_axis_raddr_next),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr)
);
end else begin
/*
reg [C_ADDRESS_WIDTH-1:0] s_axis_waddr_d1;
assign s_axis_raddr = m_axis_raddr;
assign m_axis_waddr = s_axis_waddr_d1;
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr_d1 <= 'h00;
end else begin
s_axis_waddr_d1 <= s_axis_waddr;
end
end
//assign m_axis_valid = m_axis_raddr != m_axis_waddr;
//assign s_axis_ready = s_axis_raddr != s_axis_waddr + 1'b1;
*/
end
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
ram[s_axis_waddr] <= s_axis_data;
end
reg [C_DATA_WIDTH-1:0] data;
always @(posedge m_axis_aclk) begin
data <= ram[m_axis_raddr_next];
end
assign m_axis_data = data;
end endgenerate
endmodule
|
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