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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_2_V
`define SKY130_FD_SC_LP__OR4B_2_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_8_V
`define SKY130_FD_SC_LS__DECAP_8_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decap_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_8_V
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "../framework_defines.vh"
module user_tx_rd_if #(parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
input wire reset_interface,
input wire set_if_mem_pipelined,
input wire set_if_direct_pipelined,
input wire [57:0] mem_pipeline_addr,
input wire [3:0] mem_pipeline_addr_code,
input wire [3:0] direct_pipeline_addr_code,
input wire reads_finished,
//--------------------- User RD Request -----------------------------//
// User Module TX RD
input wire [57:0] um_tx_rd_addr,
input wire [USER_TAG-1:0] um_tx_rd_tag,
input wire um_tx_rd_valid,
output wire um_tx_rd_ready,
// User Module RX RD
output wire [USER_TAG-1:0] um_rx_rd_tag,
output wire [511:0] um_rx_data,
output wire um_rx_rd_valid,
input wire um_rx_rd_ready,
//-------------------- to Fthread Controller ------------------------//
output wire usr_arb_tx_rd_valid,
output wire [57:0] usr_arb_tx_rd_addr,
output wire [`IF_TAG-1:0] usr_arb_tx_rd_tag,
input wire usr_arb_tx_rd_ready,
input wire usr_arb_rx_rd_valid,
input wire [`IF_TAG-1:0] usr_arb_rx_rd_tag,
input wire [511:0] usr_arb_rx_data,
output wire [57:0] rif_tx_wr_addr,
output wire [`IF_TAG-1:0] rif_tx_wr_tag,
output wire rif_tx_wr_valid,
output wire [511:0] rif_tx_data,
input wire rif_tx_wr_ready,
input wire [`IF_TAG-1:0] rif_rx_wr_tag,
input wire rif_rx_wr_valid,
//-------------------- To pipeline writer ---------------------------//
output wire usr_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] usr_pipe_tx_rd_tag,
input wire usr_pipe_tx_rd_ready,
input wire usr_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] usr_pipe_rx_rd_tag,
input wire [511:0] usr_pipe_rx_data,
output wire usr_pipe_rx_rd_ready
);
wire [57+USER_TAG:0] tx_rd_fifo_dout;
wire tx_rd_fifo_valid;
wire tx_rd_fifo_full;
wire tx_rd_fifo_re;
wire ord_tx_rd_ready;
// RX RD
reg [`IF_TAG-1:0] rx_rd_tag_reg;
reg [511:0] rx_data_reg;
reg rx_rd_valid_reg;
wire tx_rd_ready;
wire tx_rd_valid;
wire [57:0] tx_rd_addr;
wire [`IF_TAG-1:0] tx_rd_tag;
wire usr_tx_rd_ready;
wire usr_tx_rd_valid;
wire [57:0] usr_tx_rd_addr;
wire [USER_TAG+1:0] usr_tx_rd_tag;
wire [USER_TAG+1:0] usr_rx_rd_tag;
wire usr_rx_rd_valid;
wire [511:0] usr_rx_data;
reg [57:0] fifo_base_addr;
reg [3:0] fifo_addr_code;
reg [3:0] direct_pipeline_code;
reg direct_pipeline_code_valid;
reg in_memory_pipeline;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Pipelining Control Flags ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (~rst_n | reset_interface | reads_finished) begin
in_memory_pipeline <= 0;
fifo_base_addr <= 0;
fifo_addr_code <= 0;
direct_pipeline_code <= 0;
direct_pipeline_code_valid <= 1'b0;
end
else begin
if(set_if_mem_pipelined) begin
in_memory_pipeline <= 1'b1;
fifo_base_addr <= mem_pipeline_addr;
fifo_addr_code <= mem_pipeline_addr_code;
end
if(set_if_direct_pipelined) begin
direct_pipeline_code <= direct_pipeline_addr_code;
direct_pipeline_code_valid <= 1'b1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Reader Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(58 + USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n & ~reset_interface),
.din ({um_tx_rd_tag, um_tx_rd_addr}),
.we (um_tx_rd_valid),
.re (tx_rd_fifo_re),
.dout (tx_rd_fifo_dout),
.empty (),
.valid (tx_rd_fifo_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
assign um_tx_rd_ready = ~tx_rd_fifo_full;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Through SW FIFO Reader /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Arbiter TX RD
//(direct_pipeline_code_valid)?(tx_rd_addr[57:54] != direct_pipeline_code) & tx_rd_valid : tx_rd_valid;
// Pass through in-memory FIFO
sw_fifo_reader #(.USER_TAG(USER_TAG) )
sw_fifo_reader(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
.fifo_base_addr (fifo_base_addr),
.fifo_addr_code (fifo_addr_code),
.setup_fifo (in_memory_pipeline),
.reads_finished (reads_finished),
//--------------------- FIFO to QPI ----------------//
// TX RD
.fifo_tx_wr_addr (rif_tx_wr_addr),
.fifo_tx_wr_tag (rif_tx_wr_tag),
.fifo_tx_wr_valid (rif_tx_wr_valid),
.fifo_tx_data (rif_tx_data),
.fifo_tx_wr_ready (rif_tx_wr_ready),
// TX RD
.fifo_tx_rd_addr (usr_tx_rd_addr),
.fifo_tx_rd_tag (usr_tx_rd_tag),
.fifo_tx_rd_valid (usr_tx_rd_valid),
.fifo_tx_rd_ready (usr_tx_rd_ready),
// RX RD
.fifo_rx_wr_tag (rif_rx_wr_tag),
.fifo_rx_wr_valid (rif_rx_wr_valid),
// RX WR
.fifo_rx_rd_valid (usr_rx_rd_valid),
.fifo_rx_rd_tag (usr_rx_rd_tag),
.fifo_rx_data (usr_rx_data),
.fifo_rx_rd_ready (usr_rx_rd_ready),
///////////////////////// User Logic Interface ////////////////////
.usr_tx_rd_tag (tx_rd_fifo_dout[57+USER_TAG:58]),
.usr_tx_rd_valid (tx_rd_fifo_valid),
.usr_tx_rd_addr (tx_rd_fifo_dout[57:0]),
.usr_tx_rd_ready (tx_rd_fifo_re),
.usr_rx_rd_tag (um_rx_rd_tag),
.usr_rx_rd_valid (um_rx_rd_valid),
.usr_rx_data (um_rx_data),
.usr_rx_rd_ready (um_rx_rd_ready)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Requests Ordering Module ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
order_module_backpressure #(
.TAG_WIDTH(7),
.OUT_TAG_WIDTH(`IF_TAG),
.USER_TAG_WIDTH(USER_TAG+2))
omodule(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
// input requests
.usr_tx_rd_addr (usr_tx_rd_addr),
.usr_tx_rd_tag (usr_tx_rd_tag),
.usr_tx_rd_valid (usr_tx_rd_valid),
.usr_tx_rd_free (usr_tx_rd_ready),
// TX RD
.ord_tx_rd_addr (tx_rd_addr),
.ord_tx_rd_tag (tx_rd_tag),
.ord_tx_rd_valid (tx_rd_valid),
.ord_tx_rd_free (tx_rd_ready),
// RX RD
.ord_rx_rd_tag (rx_rd_tag_reg[6:0]),
.ord_rx_rd_data (rx_data_reg),
.ord_rx_rd_valid (rx_rd_valid_reg),
//
.usr_rx_rd_tag (usr_rx_rd_tag),
.usr_rx_rd_data (usr_rx_data),
.usr_rx_rd_valid (usr_rx_rd_valid),
.usr_rx_rd_ready (usr_rx_rd_ready)
);
//--------------------------------------------//
assign tx_rd_ready = ((tx_rd_addr[57:54] == direct_pipeline_code) & direct_pipeline_code_valid)? usr_pipe_tx_rd_ready : usr_arb_tx_rd_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Accesses To Main Memory /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Arbiter TX RD
assign usr_arb_tx_rd_addr = tx_rd_addr;
assign usr_arb_tx_rd_tag = tx_rd_tag;
assign usr_arb_tx_rd_valid = (direct_pipeline_code_valid)?(tx_rd_addr[57:54] != direct_pipeline_code) & tx_rd_valid : tx_rd_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Direct AFU-AFU Pipeline /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------//
// Pipe TX RD
assign usr_pipe_tx_rd_tag = tx_rd_tag;
assign usr_pipe_tx_rd_valid = (tx_rd_addr[57:54] == direct_pipeline_code) & direct_pipeline_code_valid & tx_rd_valid;
assign usr_pipe_rx_rd_ready = ~usr_arb_rx_rd_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Read Request Responses /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------//
// order module rd rx
// data
always @(posedge clk) begin
if(usr_arb_rx_rd_valid) begin
rx_data_reg <= usr_arb_rx_data;
end
else begin
rx_data_reg <= usr_pipe_rx_data;
end
end
// valid
always @(posedge clk) begin
if (~rst_n | reset_interface) begin
rx_rd_tag_reg <= 0;
rx_rd_valid_reg <= 0;
end
else begin
if(usr_arb_rx_rd_valid) begin
rx_rd_tag_reg <= usr_arb_rx_rd_tag;
rx_rd_valid_reg <= 1'b1;
end
else begin
rx_rd_tag_reg <= usr_pipe_rx_rd_tag;
rx_rd_valid_reg <= usr_pipe_rx_rd_valid;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKBUF_TB_V
`define SKY130_FD_SC_HS__CLKBUF_TB_V
/**
* clkbuf: Clock tree buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKBUF_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_8_V
`define SKY130_FD_SC_HDLL__AND2_8_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_8 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_8 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_TB_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_TB_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv5sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkdlyinv5sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_TB_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_solo_pio_0 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule
|
//-----------------------------------------------------
// Design Name : datapath
// File Name : datapath.v
// Function : This program designs an One-Pulse Generator.
// Coder : hydai
//-----------------------------------------------------
module datapath (
output reg [291:0] snapshot,
input [25:0] control,
input [15:0] constant,
input [15:0] data,
input clk,
input rst_n
);
reg [15:0] R [0:15];
reg [15:0] BUSD, BUSB, BUSA;
reg [3:0] DA, AA, BA, FS, SS;
reg [2:0] SA;
reg MB, MD, RW, V, C, N, Z;
reg [15:0] MUXB, FUResult;
reg [15:0] tmp16bit, tmp16bit1, tmp16bit2;
// get all signal
assign {DA, AA, BA, MB, FS, SS, SA, MD, RW} = control;
// Register files
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (integer i = 0; i < 16; i = i + 1) begin
R[i] <= 0;
end
end else begin
if (RW) begin
R[DA] <= BUSD;
end else begin
R[DA] <= R[DA];
end
end // end of if-else block
end // end of always
// MUX B
always @(*) begin
if (MB) begin
MUXB <= constant;
end else begin
MUXB <= R[BA];
end
end
// BUS A
always @(*) begin
if (!rst_n) begin
BUSA <= 0;
end else begin
BUSA <= R[AA];
end
end
// MUX D
always @(*) begin
if (MD) begin
BUSD <= data;
end else begin
BUSD <= FUResult;
end
end
// Barrel shifter
always @(*) begin
if (!rst_n) begin
BUSB <= 0;
end else begin
case(SS)
// B >> (SA) bits
3'b000: begin
BUSB <= MUXB >> SA;
end
// B << (SA) bits
3'b001: begin
BUSB <= MUXB << SA;
end
// B right rotating by (SA) bits
3'b010: begin
if (SA == 0) begin
BUSB <= MUXB;
end else begin
tmp16bit <= MUXB >> SA;
tmp16bit1 <= MUXB << (15 - SA);
BUSB <= tmp16bit | tmp16bit1;
end
end
// B left rotating by (SA) bits
3'b011: begin
if (SA == 0) begin
BUSB <= MUXB;
end else begin
tmp16bit <= MUXB << SA;
tmp16bit1 <= MUXB >> (15 - SA);
BUSB <= tmp16bit | tmp16bit1;
end
end
// B arithmetic-right-shift by (SA) bits
3'b100: begin
BUSB <= MUXB >>> SA;
end
// Other cases
default: begin
BUSB <= MUXB;
end
endcase
end
end
// Function Unit
always @(*) begin
/*
if (!rst_n) begin
C <= 0;
V <= 0;
end else begin
*/
C <= 0;
V <= 0;
//end
case (FS)
// F <- A
4'b0000: begin
FUResult <= BUSA;
end
// F <- A+1
4'b0001: begin
{C, FUResult} <= BUSA + 1;
if (BUSA[15] == FUResult[15]) begin
V <= 0;
end else begin
V <= 1;
end
end
// F <- A+B
4'b0010: begin
{C, FUResult} <= BUSA + BUSB;
if (BUSA[15] == BUSB[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <- A+B+1
4'b0011: begin
{C, FUResult} <= BUSA + BUSB + 1;
if (BUSA[15] == BUSB[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <= A + !B
4'b0100: begin
tmp16bit <= ~BUSB;
{C, FUResult} <= BUSA + tmp16bit;
if (BUSA[15] == tmp16bit[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <= A + !B + 1
4'b0101: begin
tmp16bit <= ~BUSB;
{C, FUResult} <= BUSA + tmp16bit + 1;
if (BUSA[15] == tmp16bit[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <= A - 1
4'b0110: begin
{C, FUResult} <= BUSA - 1;
if (BUSA[15] == FUResult[15]) begin
V <= 0;
end else begin
V <= 1;
end
end
// F <= A
4'b0111: begin
FUResult <= BUSA;
end
// F <= A AND B
4'b1000: begin
FUResult <= BUSA & BUSB;
end
// F <= A OR B
4'b1001: begin
FUResult <= BUSA | BUSB;
end
// F <= A XOR B
4'b1010: begin
FUResult <= BUSA ^ BUSB;
end
// F <= !A
4'b1011: begin
FUResult <= ~BUSA;
end
4'b1100: begin
FUResult <= BUSB;
end
default: begin
FUResult <= 0;
end
endcase
end
// Detect Negtive
always @(*) begin
if (!rst_n) begin
N <= 0;
end else begin
if (FUResult[15] == 1) begin
N <= 1;
end else begin
N <= 0;
end
end
end
// Detect Zero
always @(*) begin
if (!rst_n) begin
Z <= 0;
end else begin
if (FUResult == 0) begin
Z <= 1;
end else begin
Z <= 0;
end
end
end
// Deal with output
assign snapshot = {V, C, N, Z, R[0], R[1], R[2], R[3], R[4], R[5], R[6], R[7], R[8], R[9], R[10], R[11], R[12], R[13], R[14], R[15], BUSA, BUSB};
endmodule // endmodule of datapath
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// main top-level module
module main(
clk_fpga, // clocks
clk_24mhz, //
clksel0, // clock selection
clksel1, //
warmres_n, // warm reset
d, // Z80 data bus
a, // Z80 address bus
iorq_n, // Z80 control signals
mreq_n, //
rd_n, //
wr_n, //
m1_n, //
int_n, //
nmi_n, //
busrq_n, //
busak_n, //
z80res_n, //
mema14, // memory control
mema15, //
mema16, //
mema17, //
mema18, //
ram0cs_n, //
ram1cs_n, //
ram2cs_n, //
ram3cs_n, //
romcs_n, //
memoe_n, //
memwe_n, //
zxid, // zxbus signals
zxa, //
zxa14, //
zxa15, //
zxiorq_n, //
zxmreq_n, //
zxrd_n, //
zxwr_n, //
zxcsrom_n, //
zxblkiorq_n, //
zxblkrom_n, //
zxgenwait_n, //
zxbusin, //
zxbusena_n, //
dac_bitck, // audio-DAC signals
dac_lrck, //
dac_dat, //
sd_clk, // SD card interface
sd_cs, //
sd_do, //
sd_di, //
sd_wp, //
sd_det, //
ma_clk, // control interface of MP3 chip
ma_cs,
ma_do,
ma_di,
mp3_xreset, // data interface of MP3 chip
mp3_req, //
mp3_clk, //
mp3_dat, //
mp3_sync, //
led_diag // LED driver
);
// input-output description
input clk_fpga;
input clk_24mhz;
output clksel0;
output clksel1;
input warmres_n;
inout reg [7:0] d;
inout reg [15:0] a;
input iorq_n;
input mreq_n;
input rd_n;
input wr_n;
input m1_n;
output int_n;
output nmi_n;
output busrq_n;
input busak_n;
output reg z80res_n;
output reg mema14;
output reg mema15;
output reg mema16;
output reg mema17;
output reg mema18;
output reg ram0cs_n;
output reg ram1cs_n;
output reg ram2cs_n;
output reg ram3cs_n;
output reg romcs_n;
output reg memoe_n;
output reg memwe_n;
inout [7:0] zxid;
input [7:0] zxa;
input zxa14;
input zxa15;
input zxiorq_n;
input zxmreq_n;
input zxrd_n;
input zxwr_n;
input zxcsrom_n;
output zxblkiorq_n;
output zxblkrom_n;
output zxgenwait_n;
output zxbusin;
output zxbusena_n;
output dac_bitck;
output dac_lrck;
output dac_dat;
output sd_clk;
output sd_cs;
output sd_do;
input sd_di;
input sd_wp;
input sd_det;
output ma_clk;
output ma_cs;
output ma_do;
input ma_di;
output mp3_xreset;
input mp3_req;
output mp3_clk;
output mp3_dat;
output mp3_sync;
output led_diag;
// global signals
wire internal_reset_n; // internal reset for everything
// zxbus-ports interconnection
wire rst_from_zx_n; // internal z80 reset
wire [7:0] command_zx2gs;
wire [7:0] data_zx2gs;
wire [7:0] data_gs2zx;
wire command_bit_2gs;
wire command_bit_2zx;
wire command_bit_wr;
wire data_bit_2gs;
wire data_bit_2zx;
wire data_bit_wr;
// memmap-bus interconnection
wire [18:14] memmap_a;
wire [3:0] memmap_ramcs_n;
wire memmap_romcs_n;
wire memmap_memoe_n;
wire memmap_memwe_n;
// dma-bus interconnection
wire [20:0] mem_dma_addr;
wire [7:0] mem_dma_wd;
wire mem_dma_bus;
wire mem_dma_rnw;
wire mem_dma_oe;
wire mem_dma_we;
wire dma_takeover_enabled;
wire dma_ack;
wire dma_end;
wire dma_req;
wire [20:0] dma_addr;
wire dma_rnw;
wire [7:0] dma_rd;
wire [7:0] dma_wd;
wire zx_dmaread,zx_dmawrite;
wire zx_wait_ena;
wire [7:0] dma_zxrd_data;
wire [7:0] dma_zxwr_data;
wire [7:0] dma_dout_zx;
wire dma_on_zx;
wire dma_select_zx;
wire [7:0] dma_din_modules;
wire [1:0] dma_regsel;
wire dma_wrstb;
// ports-memmap interconnection
wire mode_ramro,mode_norom;
wire [6:0] mode_pg0,mode_pg1;
// ports databus
wire [7:0] ports_dout;
wire ports_busin;
// ports-sound interconnection
wire snd_wrtoggle;
wire snd_datnvol;
wire [2:0] snd_addr;
wire [7:0] snd_data;
wire mode_8chans;
wire mode_pan4ch;
// ports-SPIs interconnection
wire [7:0] md_din;
wire [7:0] mc_din;
wire [7:0] mc_dout;
wire [7:0] sd_din;
wire [7:0] sd_dout;
wire mc_start;
wire [1:0] mc_speed;
wire mc_rdy;
wire md_start;
wire md_halfspeed;
wire sd_start;
// LED related
wire led_toggle;
// CODE STARTS
// reset handling
resetter my_rst( .clk(clk_fpga),
.rst_in1_n( warmres_n ), .rst_in2_n( rst_from_zx_n ),
.rst_out_n( internal_reset_n ) );
always @* // reset for Z80
begin
if( internal_reset_n == 1'b0 )
z80res_n <= 1'b0;
else
z80res_n <= 1'bZ;
end
// control Z80 busses & memory signals
// data bus:
assign dma_takeover_enabled = (~busak_n) & mem_dma_bus;
always @*
begin
if( dma_takeover_enabled )
begin
if( mem_dma_rnw )
d <= 8'bZZZZZZZZ;
else
d <= mem_dma_wd;
end
else if( (!m1_n) && (!iorq_n) )
begin
d <= 8'hFF;
end
else
begin
if( ports_busin==1'b1 ) // FPGA inputs on data bus
d <= 8'bZZZZZZZZ;
else // FPGA outputs
d <= ports_dout;
end
end
// address bus (both Z80 and memmap module)
always @*
begin
a[15:14] <= 2'bZZ;
if( dma_takeover_enabled )
begin
a[13:0] <= mem_dma_addr[13:0];
{mema18,mema17,mema16,mema15,mema14} <= mem_dma_addr[18:14];
{ram3cs_n,ram2cs_n,ram1cs_n,ram0cs_n} <= ~( 4'b0001<<mem_dma_addr[20:19] );
romcs_n <= 1'b1;
memoe_n <= mem_dma_oe;
memwe_n <= mem_dma_we;
end
else
begin
a[13:0] <= 14'bZZ_ZZZZ_ZZZZ_ZZZZ;
{mema18,mema17,mema16,mema15,mema14} <= memmap_a[18:14];
ram0cs_n <= memmap_ramcs_n[0];
ram1cs_n <= memmap_ramcs_n[1];
ram2cs_n <= memmap_ramcs_n[2];
ram3cs_n <= memmap_ramcs_n[3];
romcs_n <= memmap_romcs_n;
memoe_n <= memmap_memoe_n;
memwe_n <= memmap_memwe_n;
end
end
// ZXBUS module
zxbus my_zxbus( .cpu_clock(clk_fpga),
.rst_n(internal_reset_n),
.rst_from_zx_n(rst_from_zx_n),
.nmi_n(nmi_n),
.zxid(zxid),
.zxa(zxa),
.zxa14(zxa14),
.zxa15(zxa15),
.zxiorq_n(zxiorq_n),
.zxmreq_n(zxmreq_n),
.zxrd_n(zxrd_n),
.zxwr_n(zxwr_n),
.zxblkiorq_n(zxblkiorq_n),
.zxblkrom_n(zxblkrom_n),
.zxcsrom_n(zxcsrom_n),
.zxgenwait_n(zxgenwait_n),
.zxbusin(zxbusin),
.zxbusena_n(zxbusena_n),
.command_reg_out(command_zx2gs),
.data_reg_out(data_zx2gs),
.data_reg_in(data_gs2zx),
.command_bit(command_bit_2gs),
.command_bit_in(command_bit_2zx),
.command_bit_wr(command_bit_wr),
.data_bit(data_bit_2gs),
.data_bit_in(data_bit_2zx),
.data_bit_wr(data_bit_wr),
.wait_ena(zx_wait_ena),
.dma_on(dma_on_zx),
.dmaread(zx_dmaread),
.dmawrite(zx_dmawrite),
.dma_data_written(dma_zxwr_data),
.dma_data_toberead(dma_zxrd_data),
.led_toggle(led_toggle) );
// DMA modules
dma_access my_dma( .clk(clk_fpga),
.rst_n(internal_reset_n),
.busrq_n(busrq_n),
.busak_n(busak_n),
.mem_dma_addr(mem_dma_addr),
.mem_dma_wd(mem_dma_wd),
.mem_dma_rd(d),
.mem_dma_bus(mem_dma_bus),
.mem_dma_rnw(mem_dma_rnw),
.mem_dma_oe(mem_dma_oe),
.mem_dma_we(mem_dma_we),
.dma_req(dma_req),
.dma_ack(dma_ack),
.dma_end(dma_end),
.dma_rnw(dma_rnw),
.dma_rd(dma_rd),
.dma_wd(dma_wd),
.dma_addr(dma_addr) );
dma_zx zxdma( .clk(clk_fpga),
.rst_n(internal_reset_n),
.module_select(dma_select_zx),
.write_strobe(dma_wrstb),
.regsel(dma_regsel),
.din(dma_din_modules),
.dout(dma_dout_zx),
.wait_ena(zx_wait_ena),
.dma_on(dma_on_zx),
.zxdmaread(zx_dmaread),
.zxdmawrite(zx_dmawrite),
.dma_wr_data(dma_zxwr_data),
.dma_rd_data(dma_zxrd_data),
.dma_req(dma_req),
.dma_ack(dma_ack),
.dma_end(dma_end),
.dma_rnw(dma_rnw),
.dma_rd(dma_rd),
.dma_wd(dma_wd),
.dma_addr(dma_addr) );
// MEMMAP module
memmap my_memmap( .a14(a[14]),
.a15(a[15]),
.mreq_n(mreq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.mema14(memmap_a[14]),
.mema15(memmap_a[15]),
.mema16(memmap_a[16]),
.mema17(memmap_a[17]),
.mema18(memmap_a[18]),
.ram0cs_n(memmap_ramcs_n[0]),
.ram1cs_n(memmap_ramcs_n[1]),
.ram2cs_n(memmap_ramcs_n[2]),
.ram3cs_n(memmap_ramcs_n[3]),
.romcs_n(memmap_romcs_n),
.memoe_n(memmap_memoe_n),
.memwe_n(memmap_memwe_n),
.mode_ramro(mode_ramro),
.mode_norom(mode_norom),
.mode_pg0(mode_pg0),
.mode_pg1(mode_pg1) );
// PORTS module
ports my_ports( .dout(ports_dout),
.din(d),
.busin(ports_busin),
.a(a),
.iorq_n(iorq_n),
.mreq_n(mreq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rst_n(internal_reset_n),
.cpu_clock(clk_fpga),
.clksel0(clksel0),
.clksel1(clksel1),
.snd_wrtoggle(snd_wrtoggle),
.snd_datnvol(snd_datnvol),
.snd_addr(snd_addr),
.snd_data(snd_data),
.mode_8chans(mode_8chans),
.mode_pan4ch(mode_pan4ch),
.command_port_input(command_zx2gs),
.command_bit_input(command_bit_2gs),
.command_bit_output(command_bit_2zx),
.command_bit_wr(command_bit_wr),
.data_port_input(data_zx2gs),
.data_port_output(data_gs2zx),
.data_bit_input(data_bit_2gs),
.data_bit_output(data_bit_2zx),
.data_bit_wr(data_bit_wr),
.mode_ramro(mode_ramro),
.mode_norom(mode_norom),
.mode_pg0(mode_pg0),
.mode_pg1(mode_pg1),
.md_din(md_din),
.md_start(md_start),
.md_dreq(mp3_req),
.md_halfspeed(md_halfspeed),
.mc_ncs(ma_cs),
.mc_xrst(mp3_xreset),
.mc_dout(mc_dout),
.mc_din(mc_din),
.mc_start(mc_start),
.mc_speed(mc_speed),
.mc_rdy(mc_rdy),
.sd_ncs(sd_cs),
.sd_wp(sd_wp),
.sd_det(sd_det),
.sd_din(sd_din),
.sd_dout(sd_dout),
.sd_start(sd_start),
.dma_din_modules(dma_din_modules),
.dma_regsel(dma_regsel),
.dma_wrstb(dma_wrstb),
//
.dma_dout_zx(dma_dout_zx),
.dma_select_zx(dma_select_zx),
.led(led_diag),
.led_toggle(led_toggle)
);
// SOUND_MAIN module
sound_main my_sound_main( .clock(clk_24mhz),
.mode_8chans(mode_8chans),
.mode_pan4ch(mode_pan4ch),
.in_wrtoggle(snd_wrtoggle),
.in_datnvol(snd_datnvol),
.in_wraddr(snd_addr),
.in_data(snd_data),
.dac_clock(dac_bitck),
.dac_leftright(dac_lrck),
.dac_data(dac_dat) );
// INTERRUPTS module
interrupts my_interrupts( .clk_24mhz(clk_24mhz),
.clk_z80(clk_fpga),
.m1_n(m1_n),
.iorq_n(iorq_n),
.int_n(int_n) );
// MP3, SDcard spi modules
spi2 spi_mp3_data( .clock(clk_fpga),
.sck(mp3_clk),
.sdo(mp3_dat),
.bsync(mp3_sync),
.din(md_din),
.start(md_start),
.speed( {1'b0,md_halfspeed} ),
.sdi(1'b0) );
spi2 spi_mp3_control( .clock(clk_fpga),
.sck(ma_clk),
.sdo(ma_do),
.sdi(ma_di),
.din(mc_din),
.dout(mc_dout),
.start(mc_start),
.rdy(mc_rdy),
.speed(mc_speed) );
spi2 spi_sd( .clock(clk_fpga),
.sck(sd_clk),
.sdo(sd_do),
.sdi(sd_di),
.din(sd_din),
.dout(sd_dout),
.start(sd_start),
.speed(2'b00) );
endmodule
|
module tx (
clk,
reset_,
baud,
txdata,
tx_enable,
tx_ready,
tx);
input clk;
input reset_;
input baud; // Baud enable
input [7:0] txdata; // Parallel data to transmit
input tx_enable; // When asserted, txdata is sampled for transmission
output tx_ready; // Asserted when transmit complete (ready for next byte)
output tx; // Serial transmit data
reg tx;
reg [1:0] state;
reg [7:0] txdata_sampled;
reg [2:0] txpos;
// Transmitter states
parameter ST_IDLE = 2'd0;
parameter ST_TXSTART = 2'd1;
parameter ST_TXDATA = 2'd2;
parameter ST_TXSTOP = 2'd3;
assign tx_ready = state == ST_IDLE;
// State machine
always@ (posedge clk or negedge reset_)
if (!reset_)
state <= ST_IDLE;
else if (state == ST_IDLE && tx_enable)
state <= ST_TXSTART;
else if (state == ST_TXSTART && baud)
state <= ST_TXDATA;
else if (state == ST_TXDATA && baud && txpos == 3'd7)
state <= ST_TXSTOP;
else if (state == ST_TXSTOP && baud)
state <= ST_IDLE;
// Serial transmit data
always@ (posedge clk or negedge reset_)
if (!reset_)
tx <= 1'b1;
else if (state == ST_TXSTART && baud)
tx <= 1'b0;
else if (state == ST_TXDATA && baud)
tx <= txdata_sampled[txpos];
else if (state == ST_TXSTOP && baud)
tx <= 1'b1;
// Transmit position (bit of txdata being sent)
always@ (posedge clk or negedge reset_)
if (!reset_)
txpos <= 3'd0;
else if (state == ST_IDLE)
txpos <= 3'd0;
else if (state == ST_TXDATA && baud)
txpos <= txpos + 3'd1;
// Local copy of txdata
always@ (posedge clk or negedge reset_)
if (!reset_)
txdata_sampled <= 8'h0;
else if (tx_enable && tx_ready)
txdata_sampled <= txdata;
endmodule
|
//Alan Achtenberg
//Lab 6 part 5
//Multiplexer
module mux_4x1(Out, In, Select);
output Out; //only one output
reg Out;
input [3:0] In; //input to be selection
input [1:0] Select; //2bit selection
always @ (In or Select)
case (Select)
2'b00: Out=In[0];
2'b01: Out=In[1];
2'b10: Out=In[2];
2'b11: Out=In[3];
endcase
endmodule
module full_adder_mux(S, Cout,A,B,Cin);
input A, B;
input Cin;
output S;
output Cout;
reg [3:0] input1, input2;
reg [1:0] select1,select2;
always @ (A or B or Cin) begin
input1[0]=A;
input1[1]=~A;
input1[2]=~A;
input1[3]=A;
select1[0]=Cin;
select1[1]=B;
input2[0]=1'b0;
input2[1]=A;
input2[2]=A;
input2[3]=1'b1;
select2[0]=Cin;
select2[1]=B;
end
mux_4x1 sum(S, input1, select1);
mux_4x1 carry(Cout, input2, select1);
endmodule
//testbench for full adder
module full_adder_test(); /* test bench module for first_module() */
reg a, b, cin;
wire S, Cout;
full_adder_mux test(S,Cout,a,b,cin);
initial begin
$monitor ($time,"\ta=%b\tb=%b\tcin=%b\tsum=%b\tcarry=%b",a,b,cin, S, Cout);
a = 0; b = 0; cin=0;
#1
a = 0; b = 0; cin=1;
#1
a = 0; b = 1; cin=0;
#1
a = 0; b = 1; cin=1;
#1
a = 1; b = 0; cin=0;
#1
a = 1; b = 0; cin=1;
#1
a = 1; b = 1; cin=0;
#1
a = 1; b = 1; cin=1;
#1
$finish;
end
endmodule
|
`default_nettype none
module thinpad_top(/*autoport*/
//inout
base_ram_data,
ext_ram_data,
flash_data,
sl811_data,
dm9k_data,
//output
base_ram_addr,
base_ram_be_n,
base_ram_ce_n,
base_ram_oe_n,
base_ram_we_n,
ext_ram_addr,
ext_ram_be_n,
ext_ram_ce_n,
ext_ram_oe_n,
ext_ram_we_n,
txd,
flash_address,
flash_rp_n,
flash_vpen,
flash_oe_n,
flash_ce,
flash_byte_n,
flash_we_n,
sl811_a0,
sl811_we_n,
sl811_rd_n,
sl811_cs_n,
sl811_rst_n,
sl811_drq,
dm9k_cmd,
dm9k_we_n,
dm9k_rd_n,
dm9k_cs_n,
dm9k_rst_n,
leds,
vga_pixel,
vga_hsync,
vga_vsync,
vga_clk,
vga_de,
//input
clk_in,
clk_uart_in,
rxd,
sl811_dack,
sl811_int,
dm9k_int,
dip_sw,
touch_btn);
input wire clk_in; //50MHz main clock input
input wire clk_uart_in; //11.0592MHz clock for UART
//Base memory signals
inout wire[31:0] base_ram_data;
output wire[19:0] base_ram_addr;
output wire[3:0] base_ram_be_n;
output wire base_ram_ce_n;
output wire base_ram_oe_n;
output wire base_ram_we_n;
assign base_ram_be_n=4'b0; //leave ByteEnable zero if you don't know what it is
//Extension memory signals
inout wire[31:0] ext_ram_data;
output wire[19:0] ext_ram_addr;
output wire[3:0] ext_ram_be_n;
output wire ext_ram_ce_n;
output wire ext_ram_oe_n;
output wire ext_ram_we_n;
assign ext_ram_be_n=4'b0;
//Serial port signals
output wire txd;
input wire rxd;
//Flash memory, JS28F640
output wire [21:0]flash_address;
output wire flash_rp_n;
output wire flash_vpen;
output wire flash_oe_n;
inout wire [15:0]flash_data;
output wire flash_ce;
output wire flash_byte_n;
output wire flash_we_n;
//SL811 USB controller signals
output wire sl811_a0;
inout wire[7:0] sl811_data;
output wire sl811_we_n;
output wire sl811_rd_n;
output wire sl811_cs_n;
output wire sl811_rst_n;
input wire sl811_dack;
input wire sl811_int;
output wire sl811_drq;
//DM9000 Ethernet controller signals
output wire dm9k_cmd;
inout wire[15:0] dm9k_data;
output wire dm9k_we_n;
output wire dm9k_rd_n;
output wire dm9k_cs_n;
output wire dm9k_rst_n;
input wire dm9k_int;
//LED, SegDisp, DIP SW, and BTN1~6
output wire[31:0] leds;
input wire[31:0] dip_sw;
input wire[5:0] touch_btn;
//Video output
output wire[7:0] vga_pixel;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_clk;
output wire vga_de;
//LED & DIP switches test
reg[23:0] counter;
reg[15:0] led_bits;
always@(posedge clk_in) begin
if(touch_btn[5])begin //reset
counter<=0;
led_bits[15:0] <= dip_sw[15:0]^dip_sw[31:16];
end
else begin
counter<= counter+1;
if(&counter)
led_bits[15:0] <= {led_bits[14:0],led_bits[15]};
end
end
assign leds[15:0] = led_bits;
//Serial port receive and transmit, 115200 baudrate, no parity
wire [7:0] RxD_data;
wire RxD_data_ready;
async_receiver #(.ClkFrequency(11059200),.Baud(115200))
uart_r(.clk(clk_uart_in),.RxD(rxd),.RxD_data_ready(RxD_data_ready),.RxD_data(RxD_data));
async_transmitter #(.ClkFrequency(11059200),.Baud(115200))
uart_t(.clk(clk_uart_in),.TxD(txd),.TxD_start(RxD_data_ready),.TxD_data(RxD_data)); //transmit data back
// 7-Segment display decoder
reg[7:0] number;
SEG7_LUT segL(.oSEG1({leds[23:22],leds[19:17],leds[20],leds[21],leds[16]}), .iDIG(number[3:0]));
SEG7_LUT segH(.oSEG1({leds[31:30],leds[27:25],leds[28],leds[29],leds[24]}), .iDIG(number[7:4]));
always @(posedge clk_uart_in) begin
if(RxD_data_ready)
number <= RxD_data; //show received data on segment display
end
//VGA display pattern generation
wire [2:0] red,green;
wire [1:0] blue;
assign vga_pixel = {red,green,blue};
assign vga_clk = clk_in;
vga #(12, 800, 856, 976, 1040, 600, 637, 643, 666, 1, 1) vga800x600at75 (
.clk(clk_in),
.hdata(red),
.vdata({blue,green}),
.hsync(vga_hsync),
.vsync(vga_vsync),
.data_enable(vga_de)
);
endmodule
|
//
// usb 3.0 rx descrambling and alignment
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_descramble (
input wire clock,
input wire local_clk,
input wire reset_n,
input wire enable,
input wire [1:0] raw_valid,
input wire [5:0] raw_status,
input wire [1:0] raw_phy_status,
input wire [3:0] raw_datak,
input wire [31:0] raw_data,
//output reg [1:0] proc_valid,
//output reg [5:0] proc_status,
//output reg [1:0] proc_phy_status,
output reg [3:0] proc_datak,
output reg [31:0] proc_data,
output reg proc_active,
output reg err_skp_unexpected
);
`include "usb3_const.v"
// what this module does is filtering of the input symbol stream
// to remove everything that >PHY layer is not interested in.
//
// example: scrambled stream with skip padding
// BE40A73C3C3CE62CD3E2B20702772A (D)
// 000000111111000000000000000000 (K)
// >
// 000000000000000000000000 (D)
// 000000000000000000000000 (K)
//
// this would be fairly trivial if we could clock this module at 500mhz
// and only process 1 symbol at a time. however, due to timing constraints
// it's working at 125mhz instead, and on 4 symbols at once. this is where
// symbol alignment gets sticky, and why there are so many cases.
//
// 10/08/13 - edge case discovered where SKP immediately following the end of a
// packet on the next cycle will cause a 1 cycle deassertion of ACTIVE, and
// push the last word of the packet onto the following cycle where ACTIVE
// is asserted again.
// indicates presence of SKP at any symbol position
wire [3:0] skip = { (raw_data[31:24] == 8'h3C) & raw_datak[3], (raw_data[23:16] == 8'h3C) & raw_datak[2],
(raw_data[15:8] == 8'h3C) & raw_datak[1], (raw_data[7:0] == 8'h3C) & raw_datak[0] };
// indicates presence of COM at any symbol position (K28.5)
wire [3:0] comma = { (coll_data[31:24] == 8'hBC) & coll_datak[3], (coll_data[23:16] == 8'hBC) & coll_datak[2],
(coll_data[15:8] == 8'hBC) & coll_datak[1], (coll_data[7:0] == 8'hBC) & coll_datak[0] };
// step 1.
// collapse incoming stream to remove all SKP symbols.
// these may be sent as 0x3C, 0x3C3C, 0x3C3C3C and so on.
//reg [5:0] skr_status;
reg [31:0] skr_data;
reg [3:0] skr_datak;
reg [2:0] skr_num;
reg [1:0] skr_valid;
always @(posedge local_clk) begin
case(skip)
4'b0000: begin
skr_data <= raw_data;
skr_datak <= raw_datak; end
4'b0001: begin
skr_data <= raw_data[31:8];
skr_datak <= raw_datak[3:1]; end
4'b0010: begin
skr_data <= {raw_data[31:16], raw_data[7:0]};
skr_datak <= {raw_datak[3:2], raw_datak[0]}; end
4'b0011: begin
skr_data <= raw_data[31:16];
skr_datak <= raw_datak[3:2]; end
4'b0100: begin
skr_data <= {raw_data[31:24], raw_data[15:0]};
skr_datak <= {raw_datak[3], raw_datak[1:0]}; end
4'b0110: begin
skr_data <= {raw_data[31:24], raw_data[7:0]};
skr_datak <= {raw_datak[3], raw_datak[0]}; end
4'b0111: begin
skr_data <= raw_data[31:24];
skr_datak <= raw_datak[3]; end
4'b1110: begin
skr_data <= raw_data[7:0];
skr_datak <= raw_datak[0]; end
4'b1100: begin
skr_data <= raw_data[15:0];
skr_datak <= raw_datak[1:0]; end
4'b1000: begin
skr_data <= raw_data[23:0];
skr_datak <= raw_datak[2:0]; end
4'b1111: begin
skr_data <= 0;
skr_datak <= 0; end
default: begin
//{skr_status, skr_data, skr_datak} <= 0;
{skr_data, skr_datak} <= 0;
err_skp_unexpected <= 1;
end
endcase
// count valid symbols
skr_num <= 3'h4 - (skip[3] + skip[2] + skip[1] + skip[0]);
//skr_status <= raw_status;
skr_valid <= raw_valid;
if(~reset_n) begin
err_skp_unexpected <= 0;
end
end
// step 2.
// accumulate these fragments and then squeeze them out
// 32bits at a time.
reg [5:0] acc_status;
reg [63:0] acc_data;
reg [7:0] acc_datak;
reg [2:0] acc_depth;
always @(posedge local_clk) begin
// take in either 8, 16, 24, or 32 bits of data from the prior stage
case(skr_num)
0: begin end
1: begin
acc_data <= {acc_data[55:0], skr_data[7:0]};
acc_datak <= {acc_datak[6:0], skr_datak[0:0]};
acc_depth <= acc_depth + 3'd1;
end
2: begin
acc_data <= {acc_data[47:0], skr_data[15:0]};
acc_datak <= {acc_datak[5:0], skr_datak[1:0]};
acc_depth <= acc_depth + 3'd2;
end
3: begin
acc_data <= {acc_data[39:0], skr_data[23:0]};
acc_datak <= {acc_datak[4:0], skr_datak[2:0]};
acc_depth <= acc_depth + 3'd3;
end
4: begin
acc_data <= {acc_data[31:0], skr_data[31:0]};
acc_datak <= {acc_datak[3:0], skr_datak[3:0]};
acc_depth <= acc_depth + 3'd4;
end
endcase
// pick off 32bits and decrement the accumulator
coll_valid <= skr_valid;
coll_active <= (acc_depth > 3);
case(acc_depth)
4: begin
{coll_data, coll_datak} <= {acc_data[31:0], acc_datak[3:0]};
acc_depth <= 3'd0 + skr_num;
end
5: begin
{coll_data, coll_datak} <= {acc_data[39:8], acc_datak[4:1]};
acc_depth <= 3'd1 + skr_num;
end
6: begin
{coll_data, coll_datak} <= {acc_data[47:16], acc_datak[5:2]};
acc_depth <= 3'd2 + skr_num;
end
7: begin
{coll_data, coll_datak} <= {acc_data[55:24], acc_datak[6:3]};
acc_depth <= 3'd3 + skr_num;
end
endcase
if(~reset_n) begin
acc_depth <= 0;
end
end
// step 3.
// handle descrambling LFSR, resetting upon COM with
// proper symbol alignment.
reg [31:0] coll_data ;
reg [3:0] coll_datak;
reg coll_active;
reg [1:0] coll_valid;
reg [2:0] ds_align;
reg [2:0] scr_defer;
always @(posedge local_clk) begin
if(scr_defer < 3) scr_defer <= scr_defer + 1'b1;
if(|comma) scr_defer <= 0;
case(comma)
4'b1111: begin
ds_align <= 0;
end
4'b1110: begin
ds_align <= 1;
end
4'b1100: begin
ds_align <= 2;
end
4'b1000: begin
ds_align <= 3;
end
endcase
if(coll_active) begin
// only apply descrambling to data, not K-symbols
next_data[31:24] <= coll_data[31:24] ^ (coll_datak[3] ? 8'h0 : ds_delay[31:24]);
next_data[23:16] <= coll_data[23:16] ^ (coll_datak[2] ? 8'h0 : ds_delay[23:16]);
next_data[15:8] <= coll_data[15:8] ^ (coll_datak[1] ? 8'h0 : ds_delay[15:8]);
next_data[7:0] <= coll_data[7:0] ^ (coll_datak[0] ? 8'h0 : ds_delay[7:0]);
next_datak <= coll_datak;
// match incoming alignment
case(ds_align)
0: ds_delay <= {ds_last};
1: ds_delay <= {ds_last[23:0], ds_out[31:24]};
2: ds_delay <= {ds_last[15:0], ds_out[31:16]};
3: ds_delay <= {ds_last[7:0], ds_out[31:8]};
endcase
ds_last <= ds_out;
end
next_active <= coll_active;
// squelch invalids
if(~coll_valid || ~coll_active) begin
next_data <= 32'h0;
next_datak <= 4'b0;
next_active <= 0;
end
end
// step 4.
// pipeline data to relax timing
reg [31:0] next_data;
reg [3:0] next_datak;
reg next_active;
always @(posedge local_clk) begin
proc_data <= next_data;
proc_datak <= next_datak;
proc_active <= next_active;
end
//
// data de-scrambling for RX
//
reg [31:0] ds_delay;
reg [31:0] ds_last;
wire ds_suppress = |comma || (scr_defer < 3);
wire ds_enable = enable && !ds_suppress;
wire [31:0] ds_out_swap;
wire [31:0] ds_out = ds_enable ?
{ds_out_swap[7:0], ds_out_swap[15:8], ds_out_swap[23:16], ds_out_swap[31:24]}
: 0;
usb3_lfsr iu3srx(
.clock ( local_clk ),
.reset_n ( reset_n ),
.data_in ( 32'h0 ),
.scram_en ( coll_active ),
.scram_rst ( |comma ),
.scram_init ( 16'h7DBD ), // reset to FFFF + 3 cycles
.data_out_reg ( ds_out_swap )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_PP_SYMBOL_V
|
// soc_system_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 190 at 2017.03.21.23:05:07
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_1 (
output wire [7:0] hps_0_f2h_axi_slave_awid, // hps_0_f2h_axi_slave.awid
output wire [31:0] hps_0_f2h_axi_slave_awaddr, // .awaddr
output wire [3:0] hps_0_f2h_axi_slave_awlen, // .awlen
output wire [2:0] hps_0_f2h_axi_slave_awsize, // .awsize
output wire [1:0] hps_0_f2h_axi_slave_awburst, // .awburst
output wire [1:0] hps_0_f2h_axi_slave_awlock, // .awlock
output wire [3:0] hps_0_f2h_axi_slave_awcache, // .awcache
output wire [2:0] hps_0_f2h_axi_slave_awprot, // .awprot
output wire [4:0] hps_0_f2h_axi_slave_awuser, // .awuser
output wire hps_0_f2h_axi_slave_awvalid, // .awvalid
input wire hps_0_f2h_axi_slave_awready, // .awready
output wire [7:0] hps_0_f2h_axi_slave_wid, // .wid
output wire [127:0] hps_0_f2h_axi_slave_wdata, // .wdata
output wire [15:0] hps_0_f2h_axi_slave_wstrb, // .wstrb
output wire hps_0_f2h_axi_slave_wlast, // .wlast
output wire hps_0_f2h_axi_slave_wvalid, // .wvalid
input wire hps_0_f2h_axi_slave_wready, // .wready
input wire [7:0] hps_0_f2h_axi_slave_bid, // .bid
input wire [1:0] hps_0_f2h_axi_slave_bresp, // .bresp
input wire hps_0_f2h_axi_slave_bvalid, // .bvalid
output wire hps_0_f2h_axi_slave_bready, // .bready
output wire [7:0] hps_0_f2h_axi_slave_arid, // .arid
output wire [31:0] hps_0_f2h_axi_slave_araddr, // .araddr
output wire [3:0] hps_0_f2h_axi_slave_arlen, // .arlen
output wire [2:0] hps_0_f2h_axi_slave_arsize, // .arsize
output wire [1:0] hps_0_f2h_axi_slave_arburst, // .arburst
output wire [1:0] hps_0_f2h_axi_slave_arlock, // .arlock
output wire [3:0] hps_0_f2h_axi_slave_arcache, // .arcache
output wire [2:0] hps_0_f2h_axi_slave_arprot, // .arprot
output wire [4:0] hps_0_f2h_axi_slave_aruser, // .aruser
output wire hps_0_f2h_axi_slave_arvalid, // .arvalid
input wire hps_0_f2h_axi_slave_arready, // .arready
input wire [7:0] hps_0_f2h_axi_slave_rid, // .rid
input wire [127:0] hps_0_f2h_axi_slave_rdata, // .rdata
input wire [1:0] hps_0_f2h_axi_slave_rresp, // .rresp
input wire hps_0_f2h_axi_slave_rlast, // .rlast
input wire hps_0_f2h_axi_slave_rvalid, // .rvalid
output wire hps_0_f2h_axi_slave_rready, // .rready
input wire pll_0_outclk0_clk, // pll_0_outclk0.clk
input wire hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
input wire hps_only_master_clk_reset_reset_bridge_in_reset_reset, // hps_only_master_clk_reset_reset_bridge_in_reset.reset
input wire hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] hps_only_master_master_address, // hps_only_master_master.address
output wire hps_only_master_master_waitrequest, // .waitrequest
input wire [3:0] hps_only_master_master_byteenable, // .byteenable
input wire hps_only_master_master_read, // .read
output wire [31:0] hps_only_master_master_readdata, // .readdata
output wire hps_only_master_master_readdatavalid, // .readdatavalid
input wire hps_only_master_master_write, // .write
input wire [31:0] hps_only_master_master_writedata // .writedata
);
wire hps_only_master_master_translator_avalon_universal_master_0_waitrequest; // hps_only_master_master_agent:av_waitrequest -> hps_only_master_master_translator:uav_waitrequest
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_readdata; // hps_only_master_master_agent:av_readdata -> hps_only_master_master_translator:uav_readdata
wire hps_only_master_master_translator_avalon_universal_master_0_debugaccess; // hps_only_master_master_translator:uav_debugaccess -> hps_only_master_master_agent:av_debugaccess
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_address; // hps_only_master_master_translator:uav_address -> hps_only_master_master_agent:av_address
wire hps_only_master_master_translator_avalon_universal_master_0_read; // hps_only_master_master_translator:uav_read -> hps_only_master_master_agent:av_read
wire [3:0] hps_only_master_master_translator_avalon_universal_master_0_byteenable; // hps_only_master_master_translator:uav_byteenable -> hps_only_master_master_agent:av_byteenable
wire hps_only_master_master_translator_avalon_universal_master_0_readdatavalid; // hps_only_master_master_agent:av_readdatavalid -> hps_only_master_master_translator:uav_readdatavalid
wire hps_only_master_master_translator_avalon_universal_master_0_lock; // hps_only_master_master_translator:uav_lock -> hps_only_master_master_agent:av_lock
wire hps_only_master_master_translator_avalon_universal_master_0_write; // hps_only_master_master_translator:uav_write -> hps_only_master_master_agent:av_write
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_writedata; // hps_only_master_master_translator:uav_writedata -> hps_only_master_master_agent:av_writedata
wire [2:0] hps_only_master_master_translator_avalon_universal_master_0_burstcount; // hps_only_master_master_translator:uav_burstcount -> hps_only_master_master_agent:av_burstcount
wire hps_only_master_master_agent_cp_valid; // hps_only_master_master_agent:cp_valid -> router:sink_valid
wire [119:0] hps_only_master_master_agent_cp_data; // hps_only_master_master_agent:cp_data -> router:sink_data
wire hps_only_master_master_agent_cp_ready; // router:sink_ready -> hps_only_master_master_agent:cp_ready
wire hps_only_master_master_agent_cp_startofpacket; // hps_only_master_master_agent:cp_startofpacket -> router:sink_startofpacket
wire hps_only_master_master_agent_cp_endofpacket; // hps_only_master_master_agent:cp_endofpacket -> router:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_valid; // hps_0_f2h_axi_slave_agent:write_rp_valid -> router_001:sink_valid
wire [227:0] hps_0_f2h_axi_slave_agent_write_rp_data; // hps_0_f2h_axi_slave_agent:write_rp_data -> router_001:sink_data
wire hps_0_f2h_axi_slave_agent_write_rp_ready; // router_001:sink_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
wire hps_0_f2h_axi_slave_agent_write_rp_startofpacket; // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> router_001:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_endofpacket; // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> router_001:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_valid; // hps_0_f2h_axi_slave_agent:read_rp_valid -> router_002:sink_valid
wire [227:0] hps_0_f2h_axi_slave_agent_read_rp_data; // hps_0_f2h_axi_slave_agent:read_rp_data -> router_002:sink_data
wire hps_0_f2h_axi_slave_agent_read_rp_ready; // router_002:sink_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
wire hps_0_f2h_axi_slave_agent_read_rp_startofpacket; // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> router_002:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_endofpacket; // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> router_002:sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_only_master_master_limiter:cmd_sink_valid
wire [119:0] router_src_data; // router:src_data -> hps_only_master_master_limiter:cmd_sink_data
wire router_src_ready; // hps_only_master_master_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> hps_only_master_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> hps_only_master_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> hps_only_master_master_limiter:cmd_sink_endofpacket
wire [119:0] hps_only_master_master_limiter_cmd_src_data; // hps_only_master_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire hps_only_master_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_only_master_master_limiter:cmd_src_ready
wire [1:0] hps_only_master_master_limiter_cmd_src_channel; // hps_only_master_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_only_master_master_limiter_cmd_src_startofpacket; // hps_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire hps_only_master_master_limiter_cmd_src_endofpacket; // hps_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_only_master_master_limiter:rsp_sink_valid
wire [119:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_only_master_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // hps_only_master_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_only_master_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_only_master_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_only_master_master_limiter:rsp_sink_endofpacket
wire hps_only_master_master_limiter_rsp_src_valid; // hps_only_master_master_limiter:rsp_src_valid -> hps_only_master_master_agent:rp_valid
wire [119:0] hps_only_master_master_limiter_rsp_src_data; // hps_only_master_master_limiter:rsp_src_data -> hps_only_master_master_agent:rp_data
wire hps_only_master_master_limiter_rsp_src_ready; // hps_only_master_master_agent:rp_ready -> hps_only_master_master_limiter:rsp_src_ready
wire [1:0] hps_only_master_master_limiter_rsp_src_channel; // hps_only_master_master_limiter:rsp_src_channel -> hps_only_master_master_agent:rp_channel
wire hps_only_master_master_limiter_rsp_src_startofpacket; // hps_only_master_master_limiter:rsp_src_startofpacket -> hps_only_master_master_agent:rp_startofpacket
wire hps_only_master_master_limiter_rsp_src_endofpacket; // hps_only_master_master_limiter:rsp_src_endofpacket -> hps_only_master_master_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [119:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [119:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [119:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [119:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
wire [227:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:write_cp_data
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:write_cp_ready -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_data
wire cmd_mux_001_src_ready; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
wire [227:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:read_cp_data
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:read_cp_ready -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_valid
wire [227:0] router_001_src_data; // router_001:src_data -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_data
wire router_001_src_ready; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [119:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_valid
wire [227:0] router_002_src_data; // router_002:src_data -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_data
wire router_002_src_ready; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire [119:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire [1:0] hps_only_master_master_limiter_cmd_valid_data; // hps_only_master_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) hps_only_master_master_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hps_only_master_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (hps_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (hps_only_master_master_translator_avalon_universal_master_0_read), // .read
.uav_write (hps_only_master_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (hps_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (hps_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (hps_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (hps_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (hps_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (hps_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (hps_only_master_master_address), // avalon_anti_master_0.address
.av_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.av_byteenable (hps_only_master_master_byteenable), // .byteenable
.av_read (hps_only_master_master_read), // .read
.av_readdata (hps_only_master_master_readdata), // .readdata
.av_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.av_write (hps_only_master_master_write), // .write
.av_writedata (hps_only_master_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_QOS_H (104),
.PKT_QOS_L (104),
.PKT_DATA_SIDEBAND_H (102),
.PKT_DATA_SIDEBAND_L (102),
.PKT_ADDR_SIDEBAND_H (101),
.PKT_ADDR_SIDEBAND_L (97),
.PKT_BURST_TYPE_H (96),
.PKT_BURST_TYPE_L (95),
.PKT_CACHE_H (114),
.PKT_CACHE_L (111),
.PKT_THREAD_ID_H (107),
.PKT_THREAD_ID_L (107),
.PKT_BURST_SIZE_H (94),
.PKT_BURST_SIZE_L (92),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (103),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (91),
.PKT_BURSTWRAP_L (83),
.PKT_BYTE_CNT_H (82),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (105),
.PKT_SRC_ID_L (105),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (106),
.ST_DATA_W (120),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (511),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hps_only_master_master_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (hps_only_master_master_translator_avalon_universal_master_0_address), // av.address
.av_write (hps_only_master_master_translator_avalon_universal_master_0_write), // .write
.av_read (hps_only_master_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (hps_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (hps_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (hps_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (hps_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (hps_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (hps_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (hps_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (hps_only_master_master_agent_cp_valid), // cp.valid
.cp_data (hps_only_master_master_agent_cp_data), // .data
.cp_startofpacket (hps_only_master_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (hps_only_master_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (hps_only_master_master_agent_cp_ready), // .ready
.rp_valid (hps_only_master_master_limiter_rsp_src_valid), // rp.valid
.rp_data (hps_only_master_master_limiter_rsp_src_data), // .data
.rp_channel (hps_only_master_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (hps_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (hps_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (hps_only_master_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_slave_ni #(
.PKT_QOS_H (212),
.PKT_QOS_L (212),
.PKT_THREAD_ID_H (215),
.PKT_THREAD_ID_L (215),
.PKT_RESPONSE_STATUS_H (224),
.PKT_RESPONSE_STATUS_L (223),
.PKT_BEGIN_BURST (211),
.PKT_CACHE_H (222),
.PKT_CACHE_L (219),
.PKT_DATA_SIDEBAND_H (210),
.PKT_DATA_SIDEBAND_L (210),
.PKT_ADDR_SIDEBAND_H (209),
.PKT_ADDR_SIDEBAND_L (205),
.PKT_BURST_TYPE_H (204),
.PKT_BURST_TYPE_L (203),
.PKT_PROTECTION_H (218),
.PKT_PROTECTION_L (216),
.PKT_BURST_SIZE_H (202),
.PKT_BURST_SIZE_L (200),
.PKT_BURSTWRAP_H (199),
.PKT_BURSTWRAP_L (191),
.PKT_BYTE_CNT_H (190),
.PKT_BYTE_CNT_L (182),
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_TRANS_EXCLUSIVE (181),
.PKT_TRANS_LOCK (180),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_POSTED (177),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.PKT_DATA_H (127),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_SRC_ID_H (213),
.PKT_SRC_ID_L (213),
.PKT_DEST_ID_H (214),
.PKT_DEST_ID_L (214),
.PKT_ORI_BURST_SIZE_L (225),
.PKT_ORI_BURST_SIZE_H (227),
.ADDR_USER_WIDTH (5),
.DATA_USER_WIDTH (1),
.ST_DATA_W (228),
.ADDR_WIDTH (32),
.RDATA_WIDTH (128),
.WDATA_WIDTH (128),
.ST_CHANNEL_W (2),
.AXI_SLAVE_ID_W (8),
.PASS_ID_TO_SLAVE (0),
.AXI_VERSION ("AXI3"),
.WRITE_ACCEPTANCE_CAPABILITY (8),
.READ_ACCEPTANCE_CAPABILITY (8)
) hps_0_f2h_axi_slave_agent (
.aclk (pll_0_outclk0_clk), // clock_sink.clk
.aresetn (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // reset_sink.reset_n
.read_cp_valid (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid), // read_cp.valid
.read_cp_ready (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready), // .ready
.read_cp_data (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data), // .data
.read_cp_channel (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel), // .channel
.read_cp_startofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket), // .endofpacket
.write_cp_ready (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready), // write_cp.ready
.write_cp_valid (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid), // .valid
.write_cp_data (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data), // .data
.write_cp_channel (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel), // .channel
.write_cp_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // read_rp.ready
.read_rp_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.read_rp_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.read_rp_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.write_rp_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // write_rp.ready
.write_rp_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.write_rp_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.awid (hps_0_f2h_axi_slave_awid), // altera_axi_master.awid
.awaddr (hps_0_f2h_axi_slave_awaddr), // .awaddr
.awlen (hps_0_f2h_axi_slave_awlen), // .awlen
.awsize (hps_0_f2h_axi_slave_awsize), // .awsize
.awburst (hps_0_f2h_axi_slave_awburst), // .awburst
.awlock (hps_0_f2h_axi_slave_awlock), // .awlock
.awcache (hps_0_f2h_axi_slave_awcache), // .awcache
.awprot (hps_0_f2h_axi_slave_awprot), // .awprot
.awuser (hps_0_f2h_axi_slave_awuser), // .awuser
.awvalid (hps_0_f2h_axi_slave_awvalid), // .awvalid
.awready (hps_0_f2h_axi_slave_awready), // .awready
.wid (hps_0_f2h_axi_slave_wid), // .wid
.wdata (hps_0_f2h_axi_slave_wdata), // .wdata
.wstrb (hps_0_f2h_axi_slave_wstrb), // .wstrb
.wlast (hps_0_f2h_axi_slave_wlast), // .wlast
.wvalid (hps_0_f2h_axi_slave_wvalid), // .wvalid
.wready (hps_0_f2h_axi_slave_wready), // .wready
.bid (hps_0_f2h_axi_slave_bid), // .bid
.bresp (hps_0_f2h_axi_slave_bresp), // .bresp
.bvalid (hps_0_f2h_axi_slave_bvalid), // .bvalid
.bready (hps_0_f2h_axi_slave_bready), // .bready
.arid (hps_0_f2h_axi_slave_arid), // .arid
.araddr (hps_0_f2h_axi_slave_araddr), // .araddr
.arlen (hps_0_f2h_axi_slave_arlen), // .arlen
.arsize (hps_0_f2h_axi_slave_arsize), // .arsize
.arburst (hps_0_f2h_axi_slave_arburst), // .arburst
.arlock (hps_0_f2h_axi_slave_arlock), // .arlock
.arcache (hps_0_f2h_axi_slave_arcache), // .arcache
.arprot (hps_0_f2h_axi_slave_arprot), // .arprot
.aruser (hps_0_f2h_axi_slave_aruser), // .aruser
.arvalid (hps_0_f2h_axi_slave_arvalid), // .arvalid
.arready (hps_0_f2h_axi_slave_arready), // .arready
.rid (hps_0_f2h_axi_slave_rid), // .rid
.rdata (hps_0_f2h_axi_slave_rdata), // .rdata
.rresp (hps_0_f2h_axi_slave_rresp), // .rresp
.rlast (hps_0_f2h_axi_slave_rlast), // .rlast
.rvalid (hps_0_f2h_axi_slave_rvalid), // .rvalid
.rready (hps_0_f2h_axi_slave_rready) // .rready
);
soc_system_mm_interconnect_1_router router (
.sink_ready (hps_only_master_master_agent_cp_ready), // sink.ready
.sink_valid (hps_only_master_master_agent_cp_valid), // .valid
.sink_data (hps_only_master_master_agent_cp_data), // .data
.sink_startofpacket (hps_only_master_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_only_master_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_001 router_001 (
.sink_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_001 router_002 (
.sink_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (106),
.PKT_SRC_ID_H (105),
.PKT_SRC_ID_L (105),
.PKT_BYTE_CNT_H (82),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (16),
.PIPELINED (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (1),
.REORDER (0)
) hps_only_master_master_limiter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_only_master_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_only_master_master_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_only_master_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_only_master_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_only_master_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_only_master_master_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_only_master_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_only_master_master_limiter_cmd_valid_data) // cmd_valid.data
);
soc_system_mm_interconnect_1_cmd_demux cmd_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_only_master_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_only_master_master_limiter_cmd_src_channel), // .channel
.sink_data (hps_only_master_master_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_only_master_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel), // .channel
.sink_data (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel), // .channel
.sink_data (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_mux rsp_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (82),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (91),
.IN_PKT_BURSTWRAP_L (83),
.IN_PKT_BURST_SIZE_H (94),
.IN_PKT_BURST_SIZE_L (92),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (96),
.IN_PKT_BURST_TYPE_L (95),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (190),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (202),
.OUT_PKT_BURST_SIZE_L (200),
.OUT_PKT_RESPONSE_STATUS_H (224),
.OUT_PKT_RESPONSE_STATUS_L (223),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (204),
.OUT_PKT_BURST_TYPE_L (203),
.OUT_PKT_ORI_BURST_SIZE_L (225),
.OUT_PKT_ORI_BURST_SIZE_H (227),
.OUT_ST_DATA_W (228),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_wr_cmd_width_adapter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (82),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (91),
.IN_PKT_BURSTWRAP_L (83),
.IN_PKT_BURST_SIZE_H (94),
.IN_PKT_BURST_SIZE_L (92),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (96),
.IN_PKT_BURST_TYPE_L (95),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (190),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (202),
.OUT_PKT_BURST_SIZE_L (200),
.OUT_PKT_RESPONSE_STATUS_H (224),
.OUT_PKT_RESPONSE_STATUS_L (223),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (204),
.OUT_PKT_BURST_TYPE_L (203),
.OUT_PKT_ORI_BURST_SIZE_L (225),
.OUT_PKT_ORI_BURST_SIZE_H (227),
.OUT_ST_DATA_W (228),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_rd_cmd_width_adapter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (190),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_BURSTWRAP_H (199),
.IN_PKT_BURSTWRAP_L (191),
.IN_PKT_BURST_SIZE_H (202),
.IN_PKT_BURST_SIZE_L (200),
.IN_PKT_RESPONSE_STATUS_H (224),
.IN_PKT_RESPONSE_STATUS_L (223),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (204),
.IN_PKT_BURST_TYPE_L (203),
.IN_PKT_ORI_BURST_SIZE_L (225),
.IN_PKT_ORI_BURST_SIZE_H (227),
.IN_ST_DATA_W (228),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (82),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (94),
.OUT_PKT_BURST_SIZE_L (92),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (96),
.OUT_PKT_BURST_TYPE_L (95),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_wr_rsp_width_adapter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (190),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_BURSTWRAP_H (199),
.IN_PKT_BURSTWRAP_L (191),
.IN_PKT_BURST_SIZE_H (202),
.IN_PKT_BURST_SIZE_L (200),
.IN_PKT_RESPONSE_STATUS_H (224),
.IN_PKT_RESPONSE_STATUS_L (223),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (204),
.IN_PKT_BURST_TYPE_L (203),
.IN_PKT_ORI_BURST_SIZE_L (225),
.IN_PKT_ORI_BURST_SIZE_H (227),
.IN_ST_DATA_W (228),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (82),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (94),
.OUT_PKT_BURST_SIZE_L (92),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (96),
.OUT_PKT_BURST_TYPE_L (95),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_rd_rsp_width_adapter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_2_V
`define SKY130_FD_SC_HD__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_2_V
|
/****************************************
Exception Manager
Make : 2010/12/07
Update :
****************************************/
//Forced to exit and microcode branch instruction is executed.
`include "core.h"
`include "global.h"
`default_nettype none
/**********Main State**********/
`define STT_MAIN_IDLE 3'h0
`define STT_MAIN_ALU_BRANCH 3'h1
`define STT_MAIN_AUTO_CTXT_SW 3'h2
`define STT_MAIN_IRQ_SET 3'h3
`define STT_MAIN_IRQ_RET 3'h4
`define STT_MAIN_IDTR_SET 3'h5
/**********Sub State**********/
//Core Branch
`define STT_SUB_ALU_BRANCH_COMMIT_WAIT 3'h0
//Auto Context Switch
`define STT_SUB_AUTO_TSW_COMMIT_WAIT 3'h0
`define STT_SUB_AUTO_TSW_STORE_MCODE 3'h1
`define STT_SUB_AUTO_TSW_STORE_COMMIT_WAIT 3'h2
`define STT_SUB_AUTO_TSW_SRCTHASK_MCODE 3'h3
`define STT_SUB_AUTO_TSW_SRCTHASK_COMMIT_WAIT 3'h4
`define STT_SUB_AUTO_TSW_LOAD_MCODE 3'h5
`define STT_SUB_AUTO_TSW_LOAD_COMMIT_WAIT 3'h6
//IRQ_SET
`define STT_SUB_SET_IRQ_CORE_FREE_REQ 3'h0
`define STT_SUB_SET_IRQ_VECTOR_LOAD_REQ 3'h1
`define STT_SUB_SET_IRQ_VECTOR_LOAD_GETWAIT 3'h2
`define STT_SUB_SET_IRQ_USER_SPR_WRITE 3'h3
`define STT_SUB_SET_IRQ_KERNEL_SPR_REQ 3'h4
`define STT_SUB_SET_IRQ_KERNEL_SPR_GETWAIT 3'h5
`define STT_SUB_SET_IRQ_JUMP_HUNDLER 3'h6
//IRQ_RET
`define STT_SUB_RET_IRQ_COMMIT_WAIT 3'h0
`define STT_SUB_RET_IRQ_KERNEL_SPR_WRITE 3'h1
`define STT_SUB_RET_IRQ_USER_SPR_REQ 3'h2
`define STT_SUB_RET_IRQ_USER_SPR_GETWAIT 3'h3
`define STT_SUB_RET_IRQ_JUMP_PPCR 3'h4
//IDTR Set
`define STT_SUB_SET_IDTR_COMMIT_WAIT 3'h0
`define STT_SUB_SET_IDTR_LOAD_IDT_REQ 3'h1
`define STT_SUB_SET_IDTR_LOAD_IDT_GETWAIT 3'h2
/**********Fetch Re-Start Mode**********/
`define FETCH_NORMAL_MODE 2'h0
`define FETCH_SET_IRQ_MODE 2'h1
`define FETCH_RET_IRQ_MODE 2'h2
/**********Microcode Size**********/
`define CONTEXT_STORE_MCODE_SIZE 32'h10
`define CONTEXT_LOAD_MCODE_SIZE 32'h10
`define TASK_SEARCH_MCODE_SIZE 32'h10
`define GET_HUNDLE_MCODE_SIZE 32'h10
/**********IDT Set State**********/
`define IDT_STT_REQ_WAIT 1'h0
`define IDT_STT_LOAD 1'h1
`define KSPR_STT_REQ_WAIT 1'b0
`define KSPR_STT_LOAD 1'b1
`define USPR_STT_REQ_WAIT 1'b0
`define USPR_STT_LOAD 1'b1
module exception_manager(
input wire iCLOCK,
input wire inRESET,
/*********************************
Core
*********************************/
//Commit & Regist Info
input wire [5:0] iCOREINFO_COMMIT_COUNTER,
input wire iCOREINFO_EXCEPTION_PROTECT,
//Scheduler1
input wire [31:0] iCOREINFO_CURRENT_PC,
//Free
output wire oCOREINFO_FREE_INST_DISCARD,
output wire oCOREINFO_FREE_EVENT,
output wire [5:0] oCOREINFO_FREE_COMMIT_TAG,
output wire oCOREINFO_FREE_ADDR_SET,
output wire [31:0] oCOREINFO_FREE_ADDR,
output wire oCOREINFO_FREE_RESTART,
output wire [31:0] oCOREINFO_FREE_CURRENT_PC,
output wire oCOREINFO_FREE_SET_IRQ_MODE,
output wire oCOREINFO_FREE_CLR_IRQ_MODE,
//output wire [31:0] oCOREINFO_FREE_NEW_PSR,
output wire oCOREINFO_FREE_NEW_SPR_VALID,
output wire [31:0] oCOREINFO_FREE_NEW_SPR,
//Order
output wire oCOREINFO_MCODE0_VALID,
output wire [31/*mitei*/:0] oCOREINFO_MCODE0,
output wire oCOREINFO_MCODE1_VALID,
output wire [31/*mitei*/:0] oCOREINFO_MCODE1,
input wire iCODEINFO_MCODE_LOCK,
//System Register Info
input wire [31:0] iCOREINFO_SYSREG_IDTR,
input wire [31:0] iCOREINFO_SYSREG_TISR,
input wire [31:0] iCOREINFO_SYSREG_TIDR,
input wire [31:0] iCOREINFO_SYSREG_PSR,
input wire [31:0] iCOREINFO_SYSREG_PPSR,
input wire [31:0] iCOREINFO_SYSREG_PPCR,
input wire [31:0] iCOREINFO_SYSREG_SPR,
//IO Port
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_TID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA,
/*********************************
Interrupt Configlation
*********************************/
//GCI Interrupt Configlation Table
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
//Interrupt COnfiglation Table
output wire oICT_REQ,
output wire [5:0] oICT_ENTRY,
output wire oICT_CONF_MASK,
output wire oICT_CONF_VALID,
output wire [1:0] oICT_CONF_LEVEL,
/*********************************
Exeption Source
*********************************/
//ALU Branch
input wire iALU_BRANCH_REQ,
input wire [31:0] iALU_BRANCH_ADDR,
input wire [5:0] iALU_BRANCH_COMMIT_TAG,
//IRQ-Ret
input wire iALU_INTRET_REQ,
input wire [31:0] iALU_INTRET_ADDR,
input wire [5:0] iALU_INTRET_COMMIT_TAG,
//IDT Set
input wire iIDT_SET_REQ,
input wire [31:0] iIDT_SET_R_ADDR,
input wire [5:0] iIDT_SET_COMMIT_TAG,
input wire [31:0] iIDT_SET_IDTR,
//Hardware Task Switch
input wire iHW_TS_REQ,
input wire [31:0] iHW_TS_ADDR,
output wire oHW_TS_BUSY,
//IRQ-Set
input wire iIRQ_REQ,
input wire [6:0] iIRQ_NUM,
output wire oIRQ_ACK,
output wire oIRQ_BUSY
);
//Main State
reg [2:0] b_main_state;
reg [2:0] b_sub_state;
reg [2:0] b_req_state;
reg [31:0] b_branch_addr;
reg [5:0] b_restart_commit_tag;
reg b_fetch_restart;
reg [1:0] b_fetch_restart_mode;
reg [31:0] b_microcode_addr;
reg b_new_spr_write_req;
reg [31:0] b_new_spr;
reg b_idt_read_req;
reg b_inthundl_read_req;
reg b_kspr_read_req;
reg b_uspr_read_req;
reg b_spr_mem_write_req;
reg [31:0] b_spr_mem_write_addr;
reg [31:0] b_spr_mem_write_spr;
reg [6:0] b_irq_num;
//IDT Read State
reg [6:0] b_idt_read_counter;
reg [6:0] b_idt_get_counter;
reg b_idt_readend;
reg b_idt_read_state;
reg b_idt_idt_data_valid;
reg [31:0] b_idt_idt_data;
wire [31:0] idt_read_addr = iCOREINFO_SYSREG_IDTR + {b_idt_get_counter, 3'h0};
wire idt_read_condition = (b_idt_read_state == `IDT_STT_LOAD) && (b_idt_read_counter < (7'd64 + 7'h1)) && !iLDST_BUSY;
//Hundler Get
wire [31:0] inthundle_read_addr = iCOREINFO_SYSREG_IDTR + {b_irq_num, 3'h0} + 32'h4;
reg b_inthundl_read_state;
reg b_inthundl_read;
reg b_inthundl_readend;
reg [31:0] b_inthundl_idt_data;
//Kernel Spr Read
reg b_kspr_read_state;
reg b_kspr_read;
reg b_kspr_readend;
reg [31:0] b_kspr_idt_data;
wire [31:0] kspr_read_addr = iCOREINFO_SYSREG_TISR + {iCOREINFO_SYSREG_TIDR[13:0], 8'h0} + `TST_KSPR;
//User Spr Read
reg b_uspr_read_state;
reg b_uspr_read;
reg b_uspr_readend;
reg [31:0] b_uspr_idt_data;
wire [31:0] uspr_read_addr = iCOREINFO_SYSREG_TISR + {iCOREINFO_SYSREG_TIDR[13:0], 8'h0} + `TST_USPR;
//Debug
reg [31:0] b_debug_branch_counter;
//Lock
wire microcode_request_lock_cc = iCODEINFO_MCODE_LOCK;
wire exception_request_lock_cc = iCOREINFO_EXCEPTION_PROTECT && (b_main_state != `STT_MAIN_IDLE);
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= `STT_MAIN_IDLE;
b_sub_state <= 3'h0;
b_fetch_restart <= 1'b0;
b_microcode_addr <= 32'h0;
b_new_spr_write_req <= 1'b0;
b_spr_mem_write_req <= 1'b0;
if(`PROCESSOR_DATA_RESET_EN)begin
b_debug_branch_counter <= 32'h0; //debug
b_req_state <= `STT_MAIN_IDLE;
b_branch_addr <= {32{1'b0}};
b_restart_commit_tag <= 6'h0;
b_new_spr <= {32{1'b0}};
b_fetch_restart_mode <= `FETCH_NORMAL_MODE;
b_spr_mem_write_addr <= 32'h0;
b_spr_mem_write_spr <= 32'h0;
end
b_idt_read_req <= 1'b0;
b_inthundl_read_req <= 1'b0;
b_kspr_read_req <= 1'b0;
b_irq_num <= 7'h00;
end
else begin
case(b_main_state)
`STT_MAIN_IDLE:
begin
b_fetch_restart <= 1'b0;
b_new_spr_write_req <= 1'b0;
b_sub_state <= 3'h0;
b_spr_mem_write_req <= 1'b0;
//Core Branch
if(iALU_BRANCH_REQ)begin
b_main_state <= `STT_MAIN_ALU_BRANCH;
b_req_state <= `STT_MAIN_ALU_BRANCH;
b_branch_addr <= iALU_BRANCH_ADDR;
b_restart_commit_tag <= iALU_BRANCH_COMMIT_TAG;
b_fetch_restart_mode <= `FETCH_NORMAL_MODE;
b_debug_branch_counter <= 32'h1 + b_debug_branch_counter; //debug
end
//IDTR SET
else if(iIDT_SET_REQ)begin
b_main_state <= `STT_MAIN_IDTR_SET;
b_req_state <= `STT_MAIN_IDTR_SET;
b_branch_addr <= iIDT_SET_R_ADDR;
b_restart_commit_tag <= iIDT_SET_COMMIT_TAG;
b_fetch_restart_mode <= `FETCH_RET_IRQ_MODE;
end
//IRQ-Ret
else if(iALU_INTRET_REQ)begin
b_main_state <= `STT_MAIN_IRQ_RET;
b_req_state <= `STT_MAIN_IRQ_RET;
b_restart_commit_tag <= iALU_INTRET_COMMIT_TAG;
b_fetch_restart_mode <= `FETCH_RET_IRQ_MODE;
end
//Hardware Task Switch
else if(iHW_TS_REQ && !exception_request_lock_cc)begin
b_main_state <= `STT_MAIN_AUTO_CTXT_SW;
b_req_state <= `STT_MAIN_AUTO_CTXT_SW;
end
//IRQ-Set
else if(iIRQ_REQ && !exception_request_lock_cc)begin
b_main_state <= `STT_MAIN_IRQ_SET;
b_req_state <= `STT_MAIN_IRQ_SET;
b_fetch_restart_mode <= `FETCH_SET_IRQ_MODE;
b_irq_num <= iIRQ_NUM;
b_restart_commit_tag <= iCOREINFO_COMMIT_COUNTER;
end
end
`STT_MAIN_ALU_BRANCH:
begin
case(b_sub_state)
`STT_SUB_ALU_BRANCH_COMMIT_WAIT:
begin
if(iCOREINFO_COMMIT_COUNTER == b_restart_commit_tag)begin
b_main_state <= `STT_MAIN_IDLE;
b_sub_state <= 3'h0;
b_fetch_restart <= 1'b1;
b_fetch_restart_mode <= `FETCH_NORMAL_MODE;
end
end
default:
begin
$display("ERROR : exception_manager.v STT_MAIN_ALU_BRANCH->b_sub_state Error");
b_sub_state <= `STT_SUB_ALU_BRANCH_COMMIT_WAIT;
end
endcase
end
`STT_MAIN_IRQ_SET:
begin
case(b_sub_state)
`STT_SUB_SET_IRQ_CORE_FREE_REQ:
begin
if(!iCOREINFO_EXCEPTION_PROTECT)begin
b_sub_state <= `STT_SUB_SET_IRQ_VECTOR_LOAD_REQ;
end
end
`STT_SUB_SET_IRQ_VECTOR_LOAD_REQ:
begin
b_inthundl_read_req <= 1'b1;
b_sub_state <= `STT_SUB_SET_IRQ_VECTOR_LOAD_GETWAIT;
end
`STT_SUB_SET_IRQ_VECTOR_LOAD_GETWAIT:
begin
b_inthundl_read_req <= 1'b0;
//Next Condition Check
if(b_inthundl_readend)begin
b_branch_addr <= b_inthundl_idt_data;
if(iCOREINFO_SYSREG_PSR[6:5] == `CORE_MODE_KERNEL)begin
//Hundler Jump
b_sub_state <= `STT_SUB_SET_IRQ_JUMP_HUNDLER;
end
else begin
//Kernel SPR Read
b_sub_state <= `STT_SUB_SET_IRQ_USER_SPR_WRITE;
end
end
end
`STT_SUB_SET_IRQ_USER_SPR_WRITE:
begin
if(!iLDST_BUSY)begin
b_sub_state <= `STT_SUB_SET_IRQ_KERNEL_SPR_REQ;
b_spr_mem_write_req <= 1'b1;
b_spr_mem_write_addr <= iCOREINFO_SYSREG_TISR + {iCOREINFO_SYSREG_TIDR[13:0], 8'h0} + `TST_USPR;
b_spr_mem_write_spr <= iCOREINFO_SYSREG_SPR;
end
end
`STT_SUB_SET_IRQ_KERNEL_SPR_REQ:
begin
b_spr_mem_write_req <= 1'b0;
b_kspr_read_req <= 1'b1;
b_sub_state <= `STT_SUB_SET_IRQ_KERNEL_SPR_GETWAIT;
end
`STT_SUB_SET_IRQ_KERNEL_SPR_GETWAIT:
begin
b_kspr_read_req <= 1'b0;
if(b_kspr_readend)begin
b_sub_state <= `STT_SUB_SET_IRQ_JUMP_HUNDLER;
b_new_spr_write_req <= 1'b1;
b_new_spr <= b_kspr_idt_data;
end
end
`STT_SUB_SET_IRQ_JUMP_HUNDLER:
begin
b_main_state <= `STT_MAIN_IDLE;
b_sub_state <= 3'h0;
b_fetch_restart <= 1'b1;
b_fetch_restart_mode <= `FETCH_SET_IRQ_MODE;
end
default:
begin
//$display("ERROR : exception_manager.v STT_MAIN_IRQ_SET->b_sub_state Error :b_sub_state = %x", b_sub_state);
b_sub_state <= `STT_SUB_SET_IRQ_CORE_FREE_REQ;
end
endcase
end
`STT_MAIN_IRQ_RET:
begin
case(b_sub_state)
`STT_SUB_RET_IRQ_COMMIT_WAIT:
begin
if(iCOREINFO_COMMIT_COUNTER == b_restart_commit_tag)begin
b_branch_addr <= iCOREINFO_SYSREG_PPCR;
if(iCOREINFO_SYSREG_PPSR[6:5] == `CORE_MODE_USER)begin
b_sub_state <= `STT_SUB_RET_IRQ_KERNEL_SPR_WRITE;
end
else begin
b_sub_state <= `STT_SUB_RET_IRQ_JUMP_PPCR;
end
end
end
//spr set check
`STT_SUB_RET_IRQ_KERNEL_SPR_WRITE:
begin
if(!iLDST_BUSY)begin
b_sub_state <= `STT_SUB_RET_IRQ_USER_SPR_REQ;
b_spr_mem_write_req <= 1'b1;
b_spr_mem_write_addr <= iCOREINFO_SYSREG_TISR + {iCOREINFO_SYSREG_TIDR[13:0], 8'h0} + `TST_KSPR;
b_spr_mem_write_spr <= iCOREINFO_SYSREG_SPR;
end
end
`STT_SUB_RET_IRQ_USER_SPR_REQ:
begin
b_spr_mem_write_req <= 1'b0;
b_uspr_read_req <= 1'b1;
b_sub_state <= `STT_SUB_RET_IRQ_USER_SPR_GETWAIT;
end
`STT_SUB_RET_IRQ_USER_SPR_GETWAIT:
begin
b_uspr_read_req <= 1'b0;
if(b_uspr_readend)begin
b_sub_state <= `STT_SUB_RET_IRQ_JUMP_PPCR;
b_new_spr_write_req <= 1'b1;
b_new_spr <= b_uspr_idt_data;
end
end
`STT_SUB_RET_IRQ_JUMP_PPCR:
begin
b_main_state <= `STT_MAIN_IDLE;
b_sub_state <= 3'h0;
b_fetch_restart <= 1'b1;
b_fetch_restart_mode <= `FETCH_RET_IRQ_MODE;
end
default:
begin
$display("ERROR : exception_manager.v STT_MAIN_IRQ_RET->b_sub_state Error");
b_sub_state <= `STT_SUB_RET_IRQ_COMMIT_WAIT;
end
endcase
end
`STT_MAIN_IDTR_SET:
begin
case(b_sub_state)
`STT_SUB_SET_IDTR_COMMIT_WAIT:
begin
if(iCOREINFO_COMMIT_COUNTER == b_restart_commit_tag)begin
b_sub_state <= `STT_SUB_SET_IDTR_LOAD_IDT_REQ;
end
end
`STT_SUB_SET_IDTR_LOAD_IDT_REQ:
begin
b_sub_state <= `STT_SUB_SET_IDTR_LOAD_IDT_GETWAIT;
b_idt_read_req <= 1'b1;
end
`STT_SUB_SET_IDTR_LOAD_IDT_GETWAIT:
begin
b_idt_read_req <= 1'b0;
if(b_idt_readend)begin
b_main_state <= `STT_MAIN_IDLE;
b_sub_state <= 3'h0;
b_fetch_restart <= 1'b1;
b_fetch_restart_mode <= `FETCH_NORMAL_MODE;
end
end
endcase
end
endcase
end
end
/****************************************
IDT Read
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_idt_read_state <= `IDT_STT_REQ_WAIT;
b_idt_read_counter <= 7'h0;
b_idt_get_counter <= 7'h0;
b_idt_readend <= 1'b0;
b_idt_idt_data_valid <= 1'b0;
b_idt_idt_data <= {32{1'b0}};
end
else begin
case(b_idt_read_state)
`IDT_STT_REQ_WAIT:
begin
if(b_idt_read_req)begin
b_idt_read_state <= `IDT_STT_LOAD;
b_idt_read_counter <= 7'h0;
b_idt_get_counter <= 7'h0;
end
b_idt_readend <= 1'b0;
b_idt_idt_data_valid <= 1'b0;
b_idt_idt_data <= {32{1'b0}};
end
`IDT_STT_LOAD:
begin
if(b_idt_read_counter < 7'd64 + 7'h1)begin
//Request Check
if(!iLDST_BUSY)begin
b_idt_read_counter <= b_idt_read_counter + 7'h1;
end
end
//Get Check
if(b_idt_get_counter < 7'd64 + 7'h1)begin
if(iLDST_REQ)begin
b_idt_get_counter <= b_idt_get_counter + 7'h1;
b_idt_idt_data_valid <= iLDST_REQ;
b_idt_idt_data <= iLDST_DATA;
end
end
else begin
b_idt_readend <= 1'b1;
b_idt_read_state <= `IDT_STT_REQ_WAIT;
end
end
endcase
end
end
/****************************************
Interrupt Hundler Get
****************************************/
`define INTHUNDL_STT_REQ_WAIT 1'b0
`define INTHUNDL_STT_LOAD 1'b1
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_inthundl_read_state <= `INTHUNDL_STT_REQ_WAIT;
b_inthundl_read <= 1'b0;
b_inthundl_readend <= 1'b0;
b_inthundl_idt_data <= 32'h0;
end
else begin
case(b_inthundl_read_state)
`INTHUNDL_STT_REQ_WAIT:
begin
if(b_inthundl_read_req)begin
b_inthundl_read_state <= `INTHUNDL_STT_LOAD;
b_inthundl_read <= 1'b1;
end
else begin
b_inthundl_read <= 1'b0;
end
b_inthundl_readend <= 1'b0;
end
`INTHUNDL_STT_LOAD:
begin
//Read Request
if(!iLDST_BUSY && b_inthundl_read)begin
b_inthundl_read <= 1'b0;
end
//Get Check
if(iLDST_REQ)begin
b_inthundl_readend <= 1'b1;
b_inthundl_read_state <= `INTHUNDL_STT_REQ_WAIT;
b_inthundl_idt_data <= iLDST_DATA;
end
end
endcase
end
end
/****************************************
Kernel Spr Read
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_kspr_read_state <= `KSPR_STT_REQ_WAIT;
b_kspr_read <= 1'b0;
b_kspr_readend <= 1'b0;
b_kspr_idt_data <= 32'h0;
end
else begin
case(b_kspr_read_state)
`KSPR_STT_REQ_WAIT:
begin
if(b_kspr_read_req)begin
b_kspr_read_state <= `KSPR_STT_LOAD;
b_kspr_read <= 1'b1;
end
else begin
b_kspr_read <= 1'b0;
end
b_kspr_readend <= 1'b0;
b_kspr_idt_data <= {32{1'b0}};
end
`KSPR_STT_LOAD:
begin
//Read Request
if(!iLDST_BUSY && b_kspr_read)begin
b_kspr_read <= 1'b0;
end
//Get Check
if(iLDST_REQ)begin
b_kspr_readend <= 1'b1;
b_kspr_read_state <= `KSPR_STT_REQ_WAIT;
b_kspr_idt_data <= iLDST_DATA;
end
end
endcase
end
end
/****************************************
User Spr Read
****************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_uspr_read_state <= `USPR_STT_REQ_WAIT;
b_uspr_read <= 1'b0;
b_uspr_readend <= 1'b0;
b_uspr_idt_data <= 32'h0;
end
else begin
case(b_uspr_read_state)
`USPR_STT_REQ_WAIT:
begin
if(b_uspr_read_req)begin
b_uspr_read_state <= `USPR_STT_LOAD;
b_uspr_read <= 1'b1;
end
else begin
b_uspr_read <= 1'b0;
end
b_uspr_readend <= 1'b0;
b_uspr_idt_data <= {32{1'b0}};
end
`USPR_STT_LOAD:
begin
//Read Request
if(!iLDST_BUSY && b_uspr_read)begin
b_uspr_read <= 1'b0;
end
//Get Check
if(iLDST_REQ)begin
b_uspr_readend <= 1'b1;
b_uspr_read_state <= `USPR_STT_REQ_WAIT;
b_uspr_idt_data <= iLDST_DATA;
end
end
endcase
end
end
/********************************************************************
Micro Code
********************************************************************/
//Damy
assign oCOREINFO_MCODE0_VALID = 1'b0;
assign oCOREINFO_MCODE0 = {32{1'b0}};
assign oCOREINFO_MCODE1_VALID = 1'b0;
assign oCOREINFO_MCODE1 = {32{1'b0}};
/********************************************************************
Load Store
********************************************************************/
assign oLDST_USE = (b_main_state != `STT_MAIN_IDLE) || iALU_BRANCH_REQ || iIDT_SET_REQ;
assign oLDST_REQ = (b_main_state != `STT_MAIN_IDLE) && (b_main_state != `STT_MAIN_ALU_BRANCH) && !iLDST_BUSY && (b_uspr_read || b_kspr_read || b_inthundl_read || idt_read_condition || b_spr_mem_write_req);
assign oLDST_ORDER = 2'b10;//Word Order
assign oLDST_RW = b_spr_mem_write_req;
assign oLDST_TID = iCOREINFO_SYSREG_TIDR[13:0];
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = (b_uspr_read)? uspr_read_addr : (
(b_kspr_read)? kspr_read_addr : (
(b_inthundl_read)? inthundle_read_addr : (
(idt_read_condition)? idt_read_addr : b_spr_mem_write_addr
)
)
);
assign oLDST_DATA = b_spr_mem_write_spr;
/********************************************************************
GCI-Interrupt Configlation Table
********************************************************************/
assign oIO_IRQ_CONFIG_TABLE_REQ = b_idt_idt_data_valid;
assign oIO_IRQ_CONFIG_TABLE_ENTRY = b_idt_get_counter[5:0] - 6'h1;
assign oIO_IRQ_CONFIG_TABLE_FLAG_MASK = b_idt_idt_data[1];
assign oIO_IRQ_CONFIG_TABLE_FLAG_VALID = b_idt_idt_data[0];
assign oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL = b_idt_idt_data[17:16];
/********************************************************************
Core-Interrupt Configlation Table
********************************************************************/
assign oICT_REQ = b_idt_idt_data_valid;
assign oICT_ENTRY = b_idt_get_counter[5:0] - 6'h1;
assign oICT_CONF_MASK = b_idt_idt_data[1];
assign oICT_CONF_VALID = b_idt_idt_data[0];
assign oICT_CONF_LEVEL = b_idt_idt_data[17:16];
/********************************************************************
Core Free
********************************************************************/
assign oCOREINFO_FREE_NEW_SPR_VALID = b_new_spr_write_req;
assign oCOREINFO_FREE_NEW_SPR = b_new_spr;
assign oCOREINFO_FREE_SET_IRQ_MODE = (b_fetch_restart_mode == `FETCH_SET_IRQ_MODE)? b_fetch_restart : 1'b0;
assign oCOREINFO_FREE_CLR_IRQ_MODE = (b_fetch_restart_mode == `FETCH_RET_IRQ_MODE)? b_fetch_restart : 1'b0;
assign oCOREINFO_FREE_INST_DISCARD = (b_main_state != `STT_MAIN_IDLE)? /*1'b1*/(
(b_main_state == `STT_MAIN_IRQ_SET && b_sub_state == `STT_SUB_SET_IRQ_CORE_FREE_REQ)? !iCOREINFO_EXCEPTION_PROTECT : 1'b1) :
b_main_state == `STT_MAIN_IRQ_SET && b_sub_state == `STT_SUB_SET_IRQ_CORE_FREE_REQ && !iCOREINFO_EXCEPTION_PROTECT;//(b_main_state != `STT_MAIN_IDLE)? 1'b1 : 1'b0;
assign oCOREINFO_FREE_EVENT = (
(b_main_state == `STT_MAIN_IDLE && (iALU_BRANCH_REQ || iALU_INTRET_REQ || iIDT_SET_REQ || (iIRQ_REQ && !iCOREINFO_EXCEPTION_PROTECT) || iHW_TS_REQ)) ||
(b_main_state == `STT_MAIN_IRQ_SET && b_sub_state == `STT_SUB_SET_IRQ_CORE_FREE_REQ && !iCOREINFO_EXCEPTION_PROTECT) ||
(b_main_state == `STT_MAIN_IRQ_RET && b_sub_state == `STT_SUB_RET_IRQ_COMMIT_WAIT) ||
(b_main_state == `STT_MAIN_IDTR_SET && b_sub_state == `STT_SUB_SET_IDTR_COMMIT_WAIT)
);
/*!iCOREINFO_EXCEPTION_PROTECT && (
(b_main_state == `STT_MAIN_IDLE && (iALU_BRANCH_REQ || iALU_INTRET_REQ || iIDT_SET_REQ || iIRQ_REQ || iHW_TS_REQ)) ||
(b_main_state == `STT_MAIN_IRQ_SET && b_sub_state == `STT_SUB_SET_IRQ_CORE_FREE_REQ) ||
(b_main_state == `STT_MAIN_IRQ_RET && b_sub_state == `STT_SUB_RET_IRQ_COMMIT_WAIT) ||
(b_main_state == `STT_MAIN_IDTR_SET && b_sub_state == `STT_SUB_SET_IDTR_COMMIT_WAIT)
);*/
assign oCOREINFO_FREE_COMMIT_TAG = (b_main_state == `STT_MAIN_IDLE && iALU_BRANCH_REQ)? iALU_BRANCH_COMMIT_TAG : b_restart_commit_tag;
assign oCOREINFO_FREE_ADDR_SET = b_fetch_restart;
assign oCOREINFO_FREE_ADDR = b_branch_addr;
assign oCOREINFO_FREE_RESTART = b_fetch_restart;
assign oCOREINFO_FREE_CURRENT_PC = iCOREINFO_CURRENT_PC;
/********************************************************************
Interrupt
********************************************************************/
assign oHW_TS_BUSY = 1'b0;
assign oIRQ_ACK = (b_fetch_restart_mode == `FETCH_SET_IRQ_MODE)? b_fetch_restart : 1'b0; //(b_main_state == `STT_MAIN_IRQ_SET && b_sub_state == `STT_SUB_SET_IRQ_JUMP_HUNDLER)? 1'b1 : 1'b0;
assign oIRQ_BUSY = (b_main_state != `STT_MAIN_IDLE)? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Everything here was verified on a MV4 board
// Todo: Check phase relations between 12M, 68KCLK and 68KCLKB
// Todo: Check cycle right after nRESETP goes high, real hw might have an important delay added
module clocks(
input CLK_24M,
input nRESETP,
output CLK_12M,
output reg CLK_68KCLK = 1'b0, // Real hw doesn't clearly init DFF, this needs to be checked
output CLK_68KCLKB,
output CLK_6MB,
output reg CLK_1MB
);
reg [2:0] CLK_DIV;
wire CLK_3M;
// MV4 C4:A
always @(posedge CLK_24M)
CLK_68KCLK <= ~CLK_68KCLK;
assign CLK_68KCLKB = ~CLK_68KCLK;
always @(negedge CLK_24M or negedge nRESETP)
begin
if (!nRESETP)
CLK_DIV <= 3'b100;
else
CLK_DIV <= CLK_DIV + 1'b1;
end
assign CLK_12M = CLK_DIV[0];
assign CLK_6MB = ~CLK_DIV[1];
assign CLK_3M = CLK_DIV[2];
// MV4 C4:B
always @(posedge CLK_12M)
CLK_1MB <= ~CLK_3M;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_outputcontrol.v,v $
// Revision 1.2 2005/12/13 12:54:49 maverickist
// first simulation passed
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= 1'b0;
MdoEn_d <= 1'b0;
MdoEn <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
MdoEn_d <= MdoEn_2d;
MdoEn <= MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= 1'b0;
Mdo_d <= 1'b0;
Mdo <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= ~SerialEn & BitCounter<32;
Mdo_d <= ShiftedBit | Mdo_2d;
Mdo <= Mdo_d;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/18/2016 10:23:41 PM
// Design Name:
// Module Name: nextRC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef CARPOOL_LK_AHEAD_RC_PS
module nextRC(
dst,
dstList,
mc,
indir,
nextPPV
);
input mc;
input [`DST_WIDTH-1:0] dst;
input [`DST_LIST_WIDTH-1:0] dstList;
input [`PC_INDEX_WIDTH-1:0] indir;
output [`NUM_PORT * 4 -1:0] nextPPV;
wire [`PC_INDEX_WIDTH - 2:0] target_outdir_0_plus1, target_outdir_1_plus2, target_outdir_2_plus3, target_outdir_3;
// Notation:
// the target outdir is either 0/1/2/3 for local flit or +1/+2/+3 for non-local flit
assign target_outdir_0_plus1 = (indir == 4) ? 2'd0 : ((indir + 2'd1) % 4);
assign target_outdir_1_plus2 = (indir == 4) ? 2'd1 : ((indir + 2'd2) % 4);
assign target_outdir_2_plus3 = (indir == 4) ? 2'd2 : ((indir + 2'd3) % 4);
assign target_outdir_3 = (indir == 4) ? 2'd3 : indir; // TODO: not sure what will result
wire [`NUM_PORT-1:0] w_ppv_0, w_ppv_1, w_ppv_2, w_ppv_3;
rc rc0(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_0_plus1),
.mc (mc),
.preferPortVector (w_ppv_0)
);
rc rc1(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_1_plus2),
.mc (mc),
.preferPortVector (w_ppv_1)
);
rc rc2(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_2_plus3),
.mc (mc),
.preferPortVector (w_ppv_2)
);
rc rc3(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_3),
.mc (mc),
.preferPortVector (w_ppv_3)
);
assign nextPPV = (indir == 4) ? {w_ppv_0, w_ppv_1, w_ppv_2, w_ppv_3} :
(indir == 3) ? {w_ppv_0, w_ppv_1, w_ppv_2, `NUM_PORT'h0} :
(indir == 2) ? {w_ppv_0, w_ppv_1, `NUM_PORT'h0, w_ppv_3} :
(indir == 1) ? {w_ppv_0, `NUM_PORT'h0, w_ppv_2, w_ppv_3} :
{`NUM_PORT'h0, w_ppv_1, w_ppv_2, w_ppv_3};
endmodule
`endif // CARPOOL_LK_AHEAD_RC_PS |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_4_V
`define SKY130_FD_SC_LP__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_FUNCTIONAL_PP_V |
`timescale 1ns / 1ns
module udp_rx
(input c,
input [7:0] eth_d,
input eth_dv,
input eth_stop,
output [7:0] udp_d,
output udp_dv,
output udp_last, // only signaled for valid UDP packets
output [15:0] udp_port
);
localparam SW = 3, CW = 1;
localparam ST_IDLE = 3'd0;
localparam ST_ETH_HEADER = 3'd1;
localparam ST_IP_HEADER = 3'd2;
localparam ST_UDP_HEADER = 3'd3;
localparam ST_UDP_PAYLOAD = 3'd4;
localparam ST_FCS_CHECK = 3'd5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [11:0] rx_cnt;
wire rx_cnt_rst;
r #(12) rx_cnt_r(.c(c), .rst(rx_cnt_rst), .en(eth_dv),
.d(rx_cnt + 1'b1), .q(rx_cnt));
wire ignore_pkt, ignore_pkt_en;
r ignore_pkt_r(.c(c), .rst(state == ST_IDLE), .en(ignore_pkt_en),
.d(1'b1), .q(ignore_pkt));
wire eth_stop_d3, eth_stop_d2, eth_stop_d1;
d1 eth_stop_d1_r(.c(c), .d(eth_stop ), .q(eth_stop_d1));
d1 eth_stop_d2_r(.c(c), .d(eth_stop_d1), .q(eth_stop_d2));
d1 eth_stop_d3_r(.c(c), .d(eth_stop_d2), .q(eth_stop_d3));
always @* begin
case (state)
ST_IDLE:
if (eth_dv) ctrl = { ST_ETH_HEADER , 1'b0};
else ctrl = { ST_IDLE , 1'b1};
ST_ETH_HEADER:
if (eth_stop) ctrl = { ST_IDLE , 1'b0};
else if (rx_cnt == 12'd13 & eth_dv) ctrl = { ST_IP_HEADER , 1'b1};
else ctrl = { ST_ETH_HEADER , 1'b0};
ST_IP_HEADER:
if (eth_stop) ctrl = { ST_IDLE , 1'b0};
else if (rx_cnt == 12'd19 & eth_dv) ctrl = { ST_UDP_HEADER , 1'b1};
else ctrl = { ST_IP_HEADER , 1'b0};
ST_UDP_HEADER:
if (eth_stop) ctrl = { ST_IDLE , 1'b0};
else if (rx_cnt == 12'd7 & eth_dv) ctrl = { ST_UDP_PAYLOAD, 1'b1};
else ctrl = { ST_UDP_HEADER , 1'b0};
ST_UDP_PAYLOAD:
if (eth_stop_d3) ctrl = { ST_FCS_CHECK , 1'b0};
else ctrl = { ST_UDP_PAYLOAD, 1'b0};
ST_FCS_CHECK: ctrl = { ST_IDLE , 1'b1};
default: ctrl = { ST_IDLE , 1'b1};
endcase
end
assign rx_cnt_rst = ctrl[0];
wire [47:0] rx_shifter;
r #(48) rx_shifter_r(.c(c), .en(eth_dv), .rst(1'b0),
.d({rx_shifter[39:0], eth_d}), .q(rx_shifter));
wire [47:0] dmac = rx_shifter;
wire dmac_valid = (state == ST_ETH_HEADER) & (rx_cnt == 12'd6);
wire dmac_ignore = dmac_valid &
(dmac[47:24] != 24'h01005e) & // multicast
(dmac[47:0] != 48'hffffffffffff); // broadcast
wire [47:0] smac = rx_shifter;
wire smac_valid = (state == ST_ETH_HEADER) & (rx_cnt == 12'd12);
wire [15:0] ethertype = rx_shifter[15:0];
wire ethertype_valid = (state == ST_IP_HEADER) & (rx_cnt == 12'd0);
wire ethertype_ignore = ethertype_valid & (ethertype != 16'h0800); // IPv4
wire [3:0] ip_ver = rx_shifter[7:4];
wire ip_ver_valid = state == ST_IP_HEADER & rx_cnt == 12'd1;
wire [3:0] ihl = rx_shifter[3:0];
wire ihl_ver_valid = state == ST_IP_HEADER & rx_cnt == 12'd1;
wire ip_fmt_ignore = ip_ver_valid & (ip_ver != 4'd4 | ihl != 4'd5);
wire [15:0] ip_len;
wire ip_len_valid = state == ST_IP_HEADER & (rx_cnt == 12'd4);
r #(16) ip_len_r(.c(c), .rst(state == ST_IDLE), .en(ip_len_valid),
.d(rx_shifter[15:0]), .q(ip_len));
wire [2:0] ip_flags = rx_shifter[7:5];
wire ip_flags_valid = state == ST_IP_HEADER & rx_cnt == 12'd7;
wire ip_flags_ignore = ip_flags_valid & ip_flags[0]; // more fragment flag
wire [7:0] ip_proto = rx_shifter[7:0];
wire ip_proto_valid = state == ST_IP_HEADER & rx_cnt == 12'ha;
wire ip_proto_ignore = ip_proto_valid & ip_proto != 8'h11;
wire [31:0] source_ip;
r #(32) source_ip_r(.c(c), .rst(state == ST_IDLE),
.en(state == ST_IP_HEADER & rx_cnt == 12'h10),
.d(rx_shifter[31:0]), .q(source_ip));
wire [31:0] dest_ip;
r #(32) dest_ip_r(.c(c), .rst(state == ST_IDLE),
.en(state == ST_UDP_HEADER & rx_cnt == 12'd0),
.d(rx_shifter[31:0]), .q(dest_ip));
wire [19:0] local_ip_header_sum;
r #(20) local_ip_header_sum_r
(.c(c), .rst(state == ST_IDLE),
.en(state == ST_IP_HEADER & rx_cnt[0] & eth_dv),
.d(local_ip_header_sum + {4'h0, rx_shifter[7:0], eth_d}),
.q(local_ip_header_sum));
wire [15:0] local_ip_header_csum = local_ip_header_sum[15:0] +
{12'h0, local_ip_header_sum[19:16]};
wire local_ip_header_csum_valid = state == ST_UDP_HEADER;
wire ip_header_bad_csum = local_ip_header_csum_valid & ~&local_ip_header_csum;
wire [15:0] source_port, dest_port, udp_len;
r #(16) source_port_r(.c(c), .rst(state == ST_IDLE),
.en(state == ST_UDP_HEADER & rx_cnt == 12'd2),
.d(rx_shifter[15:0]), .q(source_port));
r #(16) dest_port_r(.c(c), .rst(state == ST_IDLE),
.en(state == ST_UDP_HEADER & rx_cnt == 12'd4),
.d(rx_shifter[15:0]), .q(dest_port));
r #(16) udp_len_r(.c(c), .rst(state == ST_IDLE),
.en(state == ST_UDP_HEADER & rx_cnt == 12'd6),
.d(rx_shifter[15:0]), .q(udp_len));
wire udp_len_ignore = state == ST_UDP_PAYLOAD & udp_len > 16'd1500;
wire [31:0] fcs;
eth_crc32 crc32_calc
(.c(c), .r(state == ST_IDLE), .dv(eth_dv), .d(eth_d), .crc(fcs));
wire eth_dv_d1;
d1 eth_dv_d1_r(.c(c), .d(eth_dv), .q(eth_dv_d1));
wire [159:0] fcs_shift;
r #(160) fcs_shift_r
(.c(c), .rst(1'b0), .en(eth_dv_d1),
.d({fcs_shift[127:0], fcs}), .q(fcs_shift));
wire [31:0] current_fcs = fcs_shift[159:128];
assign ignore_pkt_en = dmac_ignore | ethertype_ignore | ip_fmt_ignore |
ip_flags_ignore | ip_proto_ignore | ip_header_bad_csum |
udp_len_ignore;
wire [31:0] rx_fcs = rx_shifter[31:0];
wire fcs_match = eth_stop_d3 & (current_fcs == rx_fcs);
// register this, since it can't seem to meet timing otherwise...
wire [15:0] expected_udp_payload_len;
r #(16) expected_udp_payload_len_r
(.c(c), .rst(state == ST_IDLE), .en(1'b1),
.d(udp_len - 16'd8), .q(expected_udp_payload_len));
// deal with short packets. linux seems to pad 4 fewer bytes than windows ?
wire normal_len_match = rx_cnt == expected_udp_payload_len + 16'h4; // FCS = 4
wire short_len_match_unix = expected_udp_payload_len < 16'h12 &
rx_cnt == 16'h16;
wire short_len_match_windows = expected_udp_payload_len < 16'h16 &
rx_cnt == 16'h1a;
wire len_match = eth_stop_d3 & (normal_len_match |
short_len_match_unix |
short_len_match_windows);
wire udp_payload_end = ~ignore_pkt & eth_stop_d3;
wire udp_payload_valid = udp_payload_end & fcs_match & len_match;
// register this; it can't meet timing otherwise...
wire udp_in_padding;
r udp_in_padding_r
(.c(c), .rst(state == ST_IDLE), .en(eth_dv),
.d(rx_cnt >= expected_udp_payload_len + 3'd4), .q(udp_in_padding));
assign udp_port = dest_port;
assign udp_d = rx_shifter[39:32];
assign udp_dv = ~ignore_pkt &
(state == ST_UDP_PAYLOAD & rx_cnt > 4) &
~udp_in_padding & (eth_dv | eth_stop_d3);
assign udp_last = udp_payload_valid;
endmodule
|
// Ken Eguro
// Alpha version - 2/11/09
// Version 1.0 - 1/4/10
// Version 1.0.1 - 5/7/10
// Version 1.1 - 8/1/11
//
// To use this code, please refer to the README document for information regarding generating
// the necessary modules from COREgen and setting the MAC address of the FPGA.
// When replacing the default "user circuit" with their own, the user will probably need to:
// 1) set input and output block memory parameters in the "system" module (IN/OUTMEM_USER_BYTE_WIDTH, IN/OUTMEM_USER_ADDRESS_WIDTH, INMEM_USER_REGISTER)
// 2) if any of the parameters are changed from their default values, update the .xco and regenerate input and/or output memories in COREGen
// 3) set desired MAC address for the FPGA in the "system" module (MAC_ADDRESS parameter)
// 4) if something other than a 167MHz user circuit clock is desired, edit the "clkBPLL" module/system.ucf appropriately or add a new clock module
// (hints are given below, search for "USER CLOCK")
// 5) determine if they want to disable the physical whole-system reset button on the board itself
// (hints are given below, search for "DISABLE RESET")
// 6) replace simpleTestModule with their own code
`timescale 1ns / 1ps
`default_nettype none
module system #(
//************ Input and output block memory parameters
//The user's circuit communicates with the input and output memories as N-byte chunks
//These should be defined as {1, 2, 4, 8, 16, 32} corresponding to an 8, 16, 32, 64, 128, or 256-bit interface.
//If this value is changed, reflect the changes in the input/output memory .xco and regenerate the core.
//Note that if more than 1 byte is used by the user, the organization of the bytes are little endian. For example if N=4,
// address 32-bit word 0 = {b3:b2:b1:b0}
// address 32-bit word 1 = {b7:b6:b5:b4}...
parameter INMEM_USER_BYTE_WIDTH = 1,
parameter OUTMEM_USER_BYTE_WIDTH = 1,
//How many address lines are required by the input and output buffers?
//Stated another way, the "BYTE_WIDTH" parameter determined the width of the words,
// the "ADDRESS_WIDTH" parameter determines the 2^M word height of buffer.
//If this value is changed, reflect the changes in the input/output memory .xco and regenerate the core.
parameter INMEM_USER_ADDRESS_WIDTH = 17,
parameter OUTMEM_USER_ADDRESS_WIDTH = 13,
//Was the input memory generated with the "Register Port B Output of Memory Core" box checked?
//This should be 0 if not, 1 if so. If this value is changed, reflect the modification in the
// input memory .xco and regenerate the core. Technically, it is also possible to account for selecting the
// "Register Port B Output of Memory Primitives" option. Either way, the value of this parameter should be equal
// to the value reported by COREGen in the "Latency Added by Output register(s)", "Port B:" field.
parameter INMEM_USER_REGISTER = 1,
//What MAC address should the FPGA use?
//This value is set within the project and does *not* require regeneration of the ethernet core.
parameter MAC_ADDRESS = 48'hAAAAAAAAAAAA
)(
input wire CLK_100, // Primary 100 MHz clock input
input wire RESET, // Active low reset from board-level button - resets everything on the board, from the
// user's circuit to the API controller to the ethernet PHY & clock generation circuits.
// Should not normally need to be used. Try the software command sendReset() instead.
// However, in the worst-case situation where the board stops responding to all
// ethernet commands, it is available to reset everything including the PHY
//GMII PHY interface for EMAC0
output wire [7:0] GMII_TXD_0, //GMII TX data output
output wire GMII_TX_EN_0, //GMII TX enable output
output wire GMII_TX_ER_0, //GMII TX error output
output wire GMII_GTX_CLK_0, //GMII GTX clock output - notice, this is not the same as the GMII_TX_CLK input!
input wire [7:0] GMII_RXD_0, //GMII RX data input
input wire GMII_RX_DV_0, //GMII RX data valid input
input wire GMII_RX_ER_0, //GMII RX error input
input wire GMII_RX_CLK_0, //GMII RX clock input
output wire GMII_RESET_B, //GMII reset (active low)
//SystemACE interface
input wire sysACE_CLK, //33 MHz clock
output wire [6:0] sysACE_MPADD, //SystemACE Address
inout wire [15:0] sysACE_MPDATA, //SystemACE Data
output wire sysACE_MPCE, //SystemACE active low chip enable
output wire sysACE_MPWE, //SystemACE active low write enable
output wire sysACE_MPOE, //SystemACE active low output enable
//input wire sysACE_MPBRDY, //SystemACE active high buffer ready signal - currently unused
//input wire sysACE_MPIRQ, //SystemACE active high interrupt request - currently unused
output wire [7:0] LED, //8 optional LEDs for visual feedback & debugging
/////
input wire RST,
input wire start,
input wire sw
/////
);
//************Handle global asynchronous reset from physical switch on board
// Buffer active low reset signal from board.
wire hard_reset_low;
//************DISABLE RESET
//If a physical reset switch is not desired, uncomment the next line and commenting out the IBUF declaration on the following line
//assign hard_reset_low = 1'b1;
IBUF reset_ibuf (.I(RESET), .O(hard_reset_low));
//************Generate a 200 MHz reference clock, a 125MHz ethernet clock and the user circuit clock from the 100 MHz clock provided
// 200 = 100 * 10 / 5
// 125 = 100 * 10 / 8
wire clk_200_i; //200 MHz clock from PLL
wire clk_200; //200 MHz clock after buffering
wire clk_125_eth_i; //125 MHz clock from PLL
wire clk_125_eth; //125 MHz clock after buffering
wire pllFB; //PLL feedback
wire pllLock; //PLL locked signal
//************USER CLOCK
//This is the clock for the user's interface to which the input/output buffers, register file and soft reset are synchronized.
wire clk_user_interface_i; //User clock directly from PLL
wire clk_user_interface; //Buffered version of user clock
PLL_BASE #(
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(10), // Multiplication factor for all output clocks - 1000 = 100 * 10 / 1
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.REF_JITTER(0.100), // Input reference jitter (0.000 to 0.999 UI%)
.CLKIN_PERIOD(10.0), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(5), // Division factor - 200 = 1000 / 5
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) (0.0 to 360.0)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle (0.01 to 0.99)
.CLKOUT1_DIVIDE(8), // Division factor - 125 = 1000 / 8
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) (0.0 to 360.0)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle (0.01 to 0.99)
//************USER CLOCK
//If a 167 MHz clock is not appropriate for the interface to the user's circuit, make changes here or
// comment out the following 3 lines and create a new PLL
//Also, don't forget to update system.ucf!
.CLKOUT2_DIVIDE(6), // Division factor - 167 = 1000/6
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) (0.0 to 360.0)
.CLKOUT2_DUTY_CYCLE(0.5) // Duty cycle (0.01 to 0.99)
) clkBPLL (
.CLKOUT0(clk_200_i), // 200 MHz
.CLKOUT1(clk_125_eth_i), // 125 MHz
//************USER CLOCK
//If the user's circuit requires a different PLL, comment out the following line
.CLKOUT2(clk_user_interface_i), //167MHz
.CLKFBOUT(pllFB), // Clock feedback output
.CLKIN(CLK_100), // Clock input
.CLKFBIN(pllFB), // Clock feedback input
.LOCKED(pllLock), // Active high PLL lock signal
.RST(~hard_reset_low) // The only thing that will reset the PLL is the physical reset button
);
//Buffer clock signals coming out of PLL
BUFG bufCLK_200 (.O(clk_200), .I(clk_200_i));
BUFG bufCLK_125 (.O(clk_125_eth), .I(clk_125_eth_i));
BUFG bufCLK_user (.O(clk_user_interface), .I(clk_user_interface_i));
//************Instantiate ethernet communication controller
//This is a line that tells that user's circuit to reset.
//Notice, this is not a reset for the entire system, just the user's circuit
wire userLogicReset;
//Wires from the user design to the communication controller
wire userRunValue; //Read run register value
wire userRunClear; //Reset run register
//Interface to parameter register file
wire register32CmdReq; //Parameter register handshaking request signal
wire register32CmdAck; //Parameter register handshaking acknowledgment signal
wire [31:0] register32WriteData; //Parameter register write data
wire [7:0] register32Address; //Parameter register address
wire register32WriteEn; //Parameter register write enable
wire register32ReadDataValid; //Indicates that a read request has returned with data
wire [31:0] register32ReadData; //Parameter register read data
//Interface to input memory
wire inputMemoryReadReq; //Input memory handshaking request signal
wire inputMemoryReadAck; //Input memory handshaking acknowledgment signal
wire [(INMEM_USER_ADDRESS_WIDTH - 1):0] inputMemoryReadAdd; //Input memory read address line
wire inputMemoryReadDataValid; //Indicates that a read request has returned with data
wire [((INMEM_USER_BYTE_WIDTH * 8) - 1):0] inputMemoryReadData; //Input memory read data line
//Interface to output memory
wire outputMemoryWriteReq; //Output memory handshaking request signal
wire outputMemoryWriteAck; //Output memory handshaking acknowledgment signal
wire [(OUTMEM_USER_ADDRESS_WIDTH - 1):0] outputMemoryWriteAdd; //Output memory write address line
wire [((OUTMEM_USER_BYTE_WIDTH * 8) - 1):0] outputMemoryWriteData; //Output memory write data line
wire [(OUTMEM_USER_BYTE_WIDTH - 1):0] outputMemoryWriteByteMask; //Output memory write byte mask
ethernet2BlockMem #(
//Forward parameters to controller
.INMEM_USER_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
.OUTMEM_USER_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
.INMEM_USER_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
.OUTMEM_USER_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH),
.INMEM_USER_REGISTER(INMEM_USER_REGISTER),
.MAC_ADDRESS(MAC_ADDRESS)
) E2M(
.refClock(clk_200), //This should be a 200 Mhz reference clock
.clockLock(pllLock), //This line from the clock generator indicates when the clocks are stable
.hardResetLow(hard_reset_low), //If this line goes low, the physical button told us to reset everything.
.ethClock(clk_125_eth), //This should be a 125 MHz source clock
// GMII Interface - EMAC0
.GMII_TXD(GMII_TXD_0), //GMII TX data output
.GMII_TX_EN(GMII_TX_EN_0), //GMII TX enable output
.GMII_TX_ER(GMII_TX_ER_0), //GMII TX error output
.GMII_GTX_CLK(GMII_GTX_CLK_0), //GMII GTX clock output - notice, this is not the same as the GMII_TX_CLK input!
.GMII_RXD(GMII_RXD_0), //GMII RX data input
.GMII_RX_DV(GMII_RX_DV_0), //GMII RX data valid input
.GMII_RX_ER(GMII_RX_ER_0), //GMII RX error input
.GMII_RX_CLK(GMII_RX_CLK_0), //GMII RX clock input
.GMII_RESET_B(GMII_RESET_B), //GMII reset (active low)
//SystemACE Interface
.sysACE_CLK(sysACE_CLK), //33 MHz clock
.sysACE_MPADD(sysACE_MPADD), //SystemACE Address
.sysACE_MPDATA(sysACE_MPDATA), //SystemACE Data in/out
.sysACE_MPCE(sysACE_MPCE), //SystemACE active low chip enable
.sysACE_MPWE(sysACE_MPWE), //SystemACE active low write enable
.sysACE_MPOE(sysACE_MPOE), //SystemACE active low output enable
//.sysACE_MPBRDY(sysACE_MPBRDY), //SystemACE active high buffer ready signal - currently unused
//.sysACE_MPIRQ(sysACE_MPIRQ), //SystemACE active high interrupt request - currently unused
//************User-side interface
.userInterfaceClk(clk_user_interface), //This is the clock to which the user's interface to the controller is synchronized (register file, i/o buffers & reset)
.userLogicReset(userLogicReset), //This signal should be used to reset the user's circuit
//This will be asserted at configuration time, when the physical button is pressed or when the
// sendReset command is received over the Ethernet.
.userRunValue(userRunValue), //Read run register value
.userRunClear(userRunClear), //Reset run register (active high)
//User interface to parameter register file
.register32CmdReq(register32CmdReq), //Parameter register handshaking request signal
.register32CmdAck(register32CmdAck), //Parameter register handshaking acknowledgment signal
.register32WriteData(register32WriteData), //Parameter register write data
.register32Address(register32Address), //Parameter register address
.register32WriteEn(register32WriteEn), //Parameter register write enable
.register32ReadDataValid(register32ReadDataValid), //Indicates that a read request has returned with data
.register32ReadData(register32ReadData), //Parameter register read data
//User interface to input memory
.inputMemoryReadReq(inputMemoryReadReq), //Input memory handshaking request signal
.inputMemoryReadAck(inputMemoryReadAck), //Input memory handshaking acknowledgment signal
.inputMemoryReadAdd(inputMemoryReadAdd), //Input memory read address line
.inputMemoryReadDataValid(inputMemoryReadDataValid), //Indicates that a read request has returned with data
.inputMemoryReadData(inputMemoryReadData), //Input memory read data line
//User interface to output memory
.outputMemoryWriteReq(outputMemoryWriteReq), //Output memory handshaking request signal
.outputMemoryWriteAck(outputMemoryWriteAck), //Output memory handshaking acknowledgment signal
.outputMemoryWriteAdd(outputMemoryWriteAdd), //Output memory write address line
.outputMemoryWriteData(outputMemoryWriteData), //Output memory write data line
.outputMemoryWriteByteMask(outputMemoryWriteByteMask) //Output memory write byte mask
);
//************Instantiate user module
SircHandler #(
//Forward parameters to user circuit
.INMEM_BYTE_WIDTH(INMEM_USER_BYTE_WIDTH),
.OUTMEM_BYTE_WIDTH(OUTMEM_USER_BYTE_WIDTH),
.INMEM_ADDRESS_WIDTH(INMEM_USER_ADDRESS_WIDTH),
.OUTMEM_ADDRESS_WIDTH(OUTMEM_USER_ADDRESS_WIDTH)
) sh(
.clk(clk_user_interface), //For simplicity sake (although it doesn't have to), the entire user circuit can run off of the same
// clock used to synchronize the interface.
.reset(userLogicReset), //When this signal is asserted (it is synchronous to userInterfaceClk), the user's circuit should reset
.userRunValue(userRunValue), //Read run register value - when this is asserted, the user's circuit has control over the i/o buffers & register file
.userRunClear(userRunClear), //Reset run register - assert this signal for 1 clock cycle to indicate that the user's circuit has completed computation and
// wishes to return control over the i/o buffers and register file back to the controller
//User interface to parameter register file
.register32CmdReq(register32CmdReq), //Parameter register handshaking request signal
.register32CmdAck(register32CmdAck), //Parameter register handshaking acknowledgment signal
.register32WriteData(register32WriteData), //Parameter register write data
.register32Address(register32Address), //Parameter register address
.register32WriteEn(register32WriteEn), //Parameter register write enable
.register32ReadDataValid(register32ReadDataValid), //Indicates that a read request has returned with data
.register32ReadData(register32ReadData), //Parameter register read data
//User interface to input memory
.inputMemoryReadReq(inputMemoryReadReq), //Input memory handshaking request signal - assert to begin a read request
.inputMemoryReadAck(inputMemoryReadAck), //Input memory handshaking acknowledgement signal - when the req and ack are both true for 1 clock cycle, the request has been accepted
.inputMemoryReadAdd(inputMemoryReadAdd), //Input memory read address - can be set the same cycle that the req line is asserted
.inputMemoryReadDataValid(inputMemoryReadDataValid), //After a read request is accepted, this line indicates that the read has returned and that the data is ready
.inputMemoryReadData(inputMemoryReadData), //Input memory read data
//User interface to output memory
.outputMemoryWriteReq(outputMemoryWriteReq), //Output memory handshaking request signal - assert to begin a write request
.outputMemoryWriteAck(outputMemoryWriteAck), //Output memory handshaking acknowledgement signal - when the req and ack are both true for 1 clock cycle, the request has been accepted
.outputMemoryWriteAdd(outputMemoryWriteAdd), //Output memory write address - can be set the same cycle that the req line is asserted
.outputMemoryWriteData(outputMemoryWriteData), //Output memory write data
.outputMemoryWriteByteMask(outputMemoryWriteByteMask), //Allows byte-wise writes when multibyte words are used - each of the OUTMEM_USER_BYTE_WIDTH line can be 0 (do not write byte) or 1 (write byte)
//Optional connection to 8 LEDs for debugging, etc.
.LED(LED),
.RST(RST),
.start(start),
.sw(sw)
);
endmodule |
(** * Equiv: Program Equivalence *)
Require Export Imp.
(** *** Some general advice for working on exercises:
- Most of the Coq proofs we ask you to do are similar to proofs
that we've provided. Before starting to work on the homework
problems, take the time to work through our proofs (both
informally, on paper, and in Coq) and make sure you understand
them in detail. This will save you a lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by random
experimentation or "following your nose." You need to start
with an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one. Alternately, grab a friend and try to
convince them that the theorem is true; then try to formalize
your explanation.
- Use automation to save work! Some of the proofs in this
chapter's exercises are pretty long if you try to write out all
the cases explicitly. *)
(* ####################################################### *)
(** * Behavioral Equivalence *)
(** In the last chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it _means_ for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To go further and talk about the correctness of program
transformations in the full Imp language, we need to consider the
role of variables and state. *)
(* ####################################################### *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say
that two [aexp]s or [bexp]s are _behaviorally equivalent_ if they
evaluate to the same result _in every state_. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands (in some starting
states) don't terminate in any final state at all! What we need
instead is this: two commands are behaviorally equivalent if, for
any given starting state, they either both diverge or both
terminate in the same final state. A compact way to express this
is "if the first one terminates in a particular state then so does
the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st || st') <-> (c2 / st || st').
(** **** Exercise: 2 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in [Imp]. For example, if you think programs (a)
through (h) are all equivalent to each other, but not to (i), your
answer should look like this: {a,b,c,d,e,f,g,h} {i}.
(a)
WHILE X > 0 DO
X ::= X + 1
END
(b)
IFB X = 0 THEN
X ::= X + 1;;
Y ::= 1
ELSE
Y ::= 0
FI;;
X ::= X - Y;;
Y ::= 0
(c)
SKIP
(d)
WHILE X <> 0 DO
X ::= X * Y + 1
END
(e)
Y ::= 0
(f)
Y ::= X + 1;;
WHILE X <> Y DO
Y ::= X + 1
END
(g)
WHILE TRUE DO
SKIP
END
(h)
WHILE X <> X DO
X ::= X + 1
END
(i)
WHILE X <> Y DO
X ::= Y + 1
END
(* {a} {b e} {c h} {d} {f g} {i} *)
[] *)
(* ####################################################### *)
(** ** Examples *)
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. omega.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv
(SKIP;; c)
c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
assumption.
Case "<-".
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
(** Prove that adding a SKIP after a command results in an equivalent
program *)
Theorem skip_right: forall c,
cequiv
(c;; SKIP)
c.
Proof. intros.
split; intros H.
Case "→". inversion H; subst. inversion H5; subst. assumption.
Case "←". eapply E_Seq. apply H. constructor.
Qed.
(** [] *)
(** Similarly, here is a simple transformations that simplifies [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
Case "->". inversion H; subst. assumption. inversion H5.
Case "<-". apply E_IfTrue. reflexivity. assumption.
Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true:
_Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1].
*)
(** *** *)
(**
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st || st'] then [c1 / st || st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st || st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st || st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st || st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st || st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st || st'].
Recall that [b] is equivalent to [BTrue], i.e. forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
|| st'] then [IFB b THEN c1 ELSE c2 FI / st || st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st || st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st || st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
SCase "b evaluates to true".
assumption.
SCase "b evaluates to false (contradiction)".
unfold bequiv in Hb. simpl in Hb.
rewrite Hb in H5. inversion H5.
Case "<-".
apply E_IfTrue; try assumption.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb. reflexivity.
Qed.
(** **** Exercise: 2 stars (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
intros. split; [Case "->" | Case "<-"]; intros; unfold bequiv in H; simpl in *.
Case "->". inversion H0; subst.
SCase "B is true". rewrite H in H6. discriminate.
SCase "B is false". assumption.
Case "<-". eapply E_IfFalse. apply H. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
(** Show that we can swap the branches of an IF by negating its
condition *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof. split; intros; [Case "->" | Case "<-"].
Case "->".
inversion H; subst; [apply E_IfFalse | apply E_IfTrue];
simpl; try rewrite H5; auto.
Case "<-".
assert (forall a b', negb a = b' -> a = negb b').
intros; destruct a; destruct b'; auto.
inversion H; subst; try inversion H6; subst;
[eapply E_IfFalse; [replace false with (negb true)|] |
eapply E_IfTrue; [replace true with (negb false)| ]];
try eapply H0; try assumption; reflexivity.
Qed.
(** [] *)
(** *** *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
Case "->".
inversion H; subst.
SCase "E_WhileEnd".
apply E_Skip.
SCase "E_WhileLoop".
rewrite Hb in H2. inversion H2.
Case "<-".
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars, advanced, optional (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* FILL IN HERE *)
[]
*)
(** *** *)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate:
_Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st || st'].
_Proof_: Suppose that [(WHILE b DO c END) / st || st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st || st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st || st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st || st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st || st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw eqn:Heqcw.
ceval_cases (induction H) Case;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
Case "E_WhileEnd". (* contradictory -- b is always true! *)
unfold bequiv in Hb.
(* [rewrite] is able to instantiate the quantifier in [st] *)
rewrite Hb in H. inversion H.
Case "E_WhileLoop". (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (WHILE_true) *)
(** Prove the following theorem. _Hint_: You'll want to use
[WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof. split; intros.
Case "->".
remember (WHILE b DO c END) as cw eqn:ecw.
ceval_cases (induction H0) SCase; inversion ecw; subst; clear ecw.
SCase "E_WhileEnd". unfold bequiv in *.
rewrite H in H0. inversion H0.
SCase "E_WhileLoop".
exfalso. eapply WHILE_true_nonterm. apply H. apply H0_0.
Case "<-".
exfalso. eapply WHILE_true_nonterm.
assert (bequiv BTrue BTrue). unfold bequiv. auto.
apply H1. apply H0.
Qed.
(** [] *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c;; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
Case "->".
inversion Hce; subst.
SCase "loop doesn't run".
apply E_IfFalse. assumption. apply E_Skip.
SCase "loop runs".
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
Case "<-".
inversion Hce; subst.
SCase "loop runs".
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
SCase "loop doesn't run".
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;;c2);;c3) (c1;;(c2;;c3)).
Proof. intros.
split; [Case "->" | Case "<-"]; intros; repeat constructor.
Case "->".
remember ((c1 ;; c2) ;; c3) as c;
ceval_cases (induction H) SCase; inversion Heqc; subst; clear Heqc.
SCase "E_Seq".
inversion H; subst. repeat eapply E_Seq.
apply H3. apply H6. assumption.
Case "<-".
remember (c1;; c2;; c3) as c;
ceval_cases (induction H) SCase; inversion Heqc; subst; clear Heqc.
SCase "E_Seq".
inversion H0; subst; repeat eapply E_Seq.
apply H. apply H3. apply H6.
Qed.
(** [] *)
(** ** The Functional Equivalence Axiom *)
(** Finally, let's look at simple equivalences involving assignments.
For example, we might expect to be able to show that [X ::= AId X]
is equivalent to [SKIP]. However, when we try to show it, we get
stuck in an interesting way. *)
Theorem identity_assignment_first_try : forall X,
cequiv (X ::= AId X) SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
(* Stuck... *) Abort.
(** Here we're stuck. The goal looks reasonable, but in fact it is not
provable! If we look back at the set of lemmas we proved about
[update] in the last chapter, we can see that lemma [update_same]
almost does the job, but not quite: it says that the original and
updated states agree at all values, but this is not the same thing
as saying that they are [=] in Coq's sense! *)
(** What is going on here? Recall that our states are just
functions from identifiers to values. For Coq, functions are only
equal when their definitions are syntactically the same, modulo
simplification. (This is the only way we can legally apply the
[refl_equal] constructor of the inductively defined proposition
[eq]!) In practice, for functions built up by repeated uses of the
[update] operation, this means that two functions can be proven
equal only if they were constructed using the _same_ [update]
operations, applied in the same order. In the theorem above, the
sequence of updates on the first parameter [cequiv] is one longer
than for the second parameter, so it is no wonder that the
equality doesn't hold. *)
(** *** *)
(** This problem is actually quite general. If we try to prove other
simple facts, such as
cequiv (X ::= X + 1;;
X ::= X + 1)
(X ::= X + 2)
or
cequiv (X ::= 1;; Y ::= 2)
(y ::= 2;; X ::= 1)
we'll get stuck in the same way: we'll have two functions that
behave the same way on all inputs, but cannot be proven to be [eq]
to each other.
The reasoning principle we would like to use in these situations
is called _functional extensionality_:
forall x, f x = g x
-------------------
f = g
Although this principle is not derivable in Coq's built-in logic,
it is safe to add it as an additional _axiom_. *)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(** It can be shown that adding this axiom doesn't introduce any
inconsistencies into Coq. (In this way, it is similar to adding
one of the classical logic axioms, such as [excluded_middle].) *)
(** With the benefit of this axiom we can prove our theorem. *)
Theorem identity_assignment : forall X,
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
assert (st' = (update st' X (st' X))).
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
rewrite H0 at 2.
constructor. reflexivity.
Qed.
(** **** Exercise: 2 stars (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof. split; intros; [Case "->" | Case "<-"]; unfold aequiv in *.
Case "->".
inversion H0. subst.
assert (st' = update st' X (st' X)).
apply functional_extensionality; intros;
rewrite update_same; reflexivity.
rewrite H1 at 2. constructor.
symmetry. rewrite <- H. reflexivity.
Case "<-".
inversion H0; subst; rewrite <- H in *.
assert (st = update st X (aeval st (AId X))).
apply functional_extensionality; intros;
rewrite update_same; reflexivity.
rewrite <- H1; constructor.
Qed.
(** [] *)
(* ####################################################### *)
(** * Properties of Behavioral Equivalence *)
(** We now turn to developing some of the properties of the program
equivalences we have defined. *)
(* ####################################################### *)
(** ** Behavioral Equivalence is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive. The proofs are all easy. *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st || st' <-> c2 / st || st') as H'.
SCase "Proof of assertion". apply H.
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st || st'). apply H12. apply H23. Qed.
(* ######################################################## *)
(** ** Behavioral Equivalence is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;;c2) (c1';;c2')
...and so on.
(Note that we are using the inference rule notation here not as
part of a definition, but simply to write down some valid
implications in a readable format. We prove these implications
below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
Case "->".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
Case "<-".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st || st'] iff [WHILE b1' DO c1' END / st
|| st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st || st'] implies
[WHILE b1' DO c1' END / st || st'], by induction on a
derivation of [WHILE b1 DO c1 END / st || st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st || st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st || st'0] and [WHILE b1 DO c1
END / st'0 || st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 ||
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st || st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st || st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
Case "->".
remember (WHILE b1 DO c1 END) as cwhile eqn:Heqcwhile.
induction Hce; inversion Heqcwhile; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite <- Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite <- Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity.
Case "<-".
remember (WHILE b1' DO c1' END) as c'while eqn:Heqc'while.
induction Hce; inversion Heqc'while; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite -> Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite -> Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;;c2) (c1';;c2').
Proof. unfold cequiv; split; intros; inversion H1; subst;
apply H in H4; apply H0 in H7; eapply E_Seq; try apply H4; apply H7.
Qed.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI) (IFB b' THEN c1' ELSE c2' FI).
Proof. unfold cequiv, bequiv; split; intros.
Case "->"; inversion H2; subst; rewrite H in *.
apply E_IfTrue. apply H8. apply H0. apply H9.
apply E_IfFalse. apply H8. apply H1. apply H9.
Case "<-"; inversion H2; subst; rewrite <- H in *.
apply E_IfTrue. apply H8. apply H0. apply H9.
apply E_IfFalse. apply H8. apply H1. apply H9.
Qed.
(** [] *)
(** *** *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(* Program 1: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(* Program 2: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(* ####################################################### *)
(** * Program Transformations *)
(** A _program transformation_ is a function that takes a program
as input and produces some variant of the program as its
output. Compiler optimizations such as constant folding are
a canonical example, but there are many others. *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program.
We can define a notion of soundness for translations of
[aexp]s, [bexp]s, and [com]s. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ######################################################## *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6)) (AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** *** *)
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases), we can also find constant _boolean_
expressions and reduce them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1) (ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** *** *)
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ;; c2 =>
(fold_constants_com c1) ;; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
(** *** *)
Example fold_com_ex1 :
fold_constants_com
(* Original program: *)
(X ::= APlus (ANum 4) (ANum 5);;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;;
IFB BLe (ANum 0) (AMinus (ANum 4) (APlus (ANum 2) (ANum 1))) THEN
Y ::= ANum 0
ELSE
SKIP
FI;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END)
= (* After constant folding: *)
(X ::= ANum 9;;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;;
Y ::= ANum 0;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ################################################### *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. *)
(** Here's the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
aexp_cases (induction a) Case; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_Eq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
bexp_cases (induction b) Case;
(* BTrue and BFalse are immediate *)
try reflexivity.
Case "BEq".
(* Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context. *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
Case "BLe".
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1'.
remember (fold_constants_aexp a2) as a2'.
replace (aeval st a1) with (aeval st a1') by
(subst; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
simpl. destruct (ble_nat n n0); reflexivity.
Case "BNot".
simpl. remember (fold_constants_bexp b) as b' eqn:Heqb'.
rewrite IHb.
destruct b'; reflexivity.
Case "BAnd".
simpl.
remember (fold_constants_bexp b1) as b1' eqn:Heqb1'.
remember (fold_constants_bexp b2) as b2' eqn:Heqb2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case; simpl.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply fold_constants_aexp_sound.
Case ";;". apply CSeq_congruence; assumption.
Case "IFB".
assert (bequiv b (fold_constants_bexp b)).
SCase "Pf of assertion". apply fold_constants_bexp_sound.
destruct (fold_constants_bexp b) eqn:Heqb;
(* If the optimization doesn't eliminate the if, then the result
is easy to prove from the IH and fold_constants_bexp_sound *)
try (apply CIf_congruence; assumption).
SCase "b always true".
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
SCase "b always false".
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
Case "WHILE".
assert (bequiv b (fold_constants_bexp b)) by apply fold_constants_bexp_sound.
split; [SCase "->" | SCase "<-"]; intros.
SCase "->".
remember (WHILE b DO c END);
ceval_cases (destruct H0) SSCase; subst;
inversion Heqc0; subst; clear Heqc0.
SSCase "E_WhileEnd".
rewrite H in H0.
destruct (fold_constants_bexp b); inversion H0; subst; try constructor;
try assumption.
SSCase "E_WhileLoop".
bexp_cases (induction (fold_constants_bexp b)) SSSCase.
SSSCase "BTrue".
exfalso. eapply WHILE_true_nonterm. apply H. apply H0_0.
SSSCase "BFalse". rewrite H in H0. inversion H0.
SSSCase "BEq".
eapply CWhile_congruence.
apply sym_bequiv. apply H.
apply sym_cequiv. apply IHc.
apply loop_unrolling.
constructor. apply H0.
eapply E_Seq. apply H0_. apply H0_0.
SSSCase "BLe".
eapply CWhile_congruence.
apply sym_bequiv. apply H.
apply sym_cequiv. apply IHc.
apply loop_unrolling.
constructor. apply H0.
eapply E_Seq. apply H0_. apply H0_0.
SSSCase "BNot".
eapply CWhile_congruence.
apply sym_bequiv. apply H.
apply sym_cequiv. apply IHc.
apply loop_unrolling.
constructor. apply H0.
eapply E_Seq. apply H0_. apply H0_0.
SSSCase "BAnd".
eapply CWhile_congruence.
apply sym_bequiv. apply H.
apply sym_cequiv. apply IHc.
apply loop_unrolling.
constructor. apply H0.
eapply E_Seq. apply H0_. apply H0_0.
SCase "<-".
bexp_cases (destruct (fold_constants_bexp b)) SSCase.
SSCase "BTrue".
exfalso. eapply WHILE_true_nonterm. apply refl_bequiv. apply H0.
SSCase "BFalse".
eapply CWhile_congruence. apply H. apply IHc.
inversion H0; subst. constructor; reflexivity.
SSCase "BEq".
eapply CWhile_congruence. apply H. apply IHc. apply H0.
SSCase "BLe".
eapply CWhile_congruence. apply H. apply IHc. apply H0.
SSCase "BNot".
eapply CWhile_congruence. apply H. apply IHc. apply H0.
SSCase "BAnd".
eapply CWhile_congruence. apply H. apply IHc. apply H0.
Qed.
(** [] *)
(* ########################################################## *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, advanced, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from Imp.v:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
and analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. (Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] -- otherwise it will be _long_!)
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
Fixpoint optimize0_aexp (e : aexp) : aexp :=
match e with
| APlus e1 e2 => match optimize0_aexp e1, optimize0_aexp e2 with
| ANum 0, e' => e'
| e', ANum 0 => e'
| e1', e2' => APlus e1' e2'
end
| AMinus e1 e2 => match optimize0_aexp e1, optimize0_aexp e2 with
| e1', ANum 0 => e1'
| e1', e2' => AMinus e1' e2'
end
| AMult e1 e2 => match optimize0_aexp e1, optimize0_aexp e2 with
| ANum 0, _ => ANum 0
| _, ANum 0 => ANum 0
| e1', e2' => AMult e1' e2'
end
| _ => e
end.
Fixpoint optimize0_bexp (b : bexp) : bexp :=
match b with
| BLe e1 e2 => match optimize0_aexp e1, optimize0_aexp e2 with
| ANum 0, _ => BTrue
| e1', e2' => BLe e1' e2'
end
| BNot b => BNot (optimize0_bexp b)
| BAnd b1 b2 => BAnd (optimize0_bexp b1) (optimize0_bexp b2)
| _ => b
end.
Fixpoint optimize0_com (c : com) : com :=
match c with
| CAss i e => CAss i (optimize0_aexp e)
| CSeq c1 c2 => CSeq (optimize0_com c1) (optimize0_com c2)
| CIf b c1 c2 => CIf (optimize0_bexp b) (optimize0_com c1) (optimize0_com c2)
| CWhile b c => CWhile (optimize0_bexp b) (optimize0_com c)
| _ => c
end.
Theorem optimize0_aexp_sound : forall a, aequiv a (optimize0_aexp a).
Proof. unfold aequiv; intros.
aexp_cases (induction a) Case; try reflexivity;
aexp_cases (destruct (optimize0_aexp a1) eqn:oa1) SCase;
aexp_cases (destruct (optimize0_aexp a2) eqn:oa2) SSCase;
simpl;
try destruct n; try destruct n0;
try rewrite oa1; try rewrite oa2;
try rewrite IHa1; try rewrite IHa2; simpl;
try rewrite Nat.sub_0_r; try rewrite Nat.mul_0_r;
auto.
Qed.
Theorem optimize0_bexp_sound : forall b, bequiv b (optimize0_bexp b).
Proof. unfold bequiv; intros.
bexp_cases (induction b) Case; try reflexivity.
Case "BLe".
simpl.
aexp_cases (destruct (optimize0_aexp a) eqn:eqa) SCase;
aexp_cases (destruct (optimize0_aexp a0) eqn:eqa0) SSCase;
rewrite (optimize0_aexp_sound a); rewrite (optimize0_aexp_sound a0);
rewrite eqa; rewrite eqa0; try (destruct n; reflexivity); try reflexivity.
Case "BNot".
simpl. rewrite IHb. reflexivity.
Case "BAnd".
simpl. rewrite IHb1. rewrite IHb2. reflexivity.
Qed.
Theorem optimize0_com_sound_p1 : forall c st1 st2,
c / st1 || st2 ->
optimize0_com c / st1 || st2.
Proof.
intros; ceval_cases (induction H) SCase; simpl;
try apply E_Skip; try apply E_Ass;
repeat rewrite <- optimize0_aexp_sound;
repeat rewrite <- optimize0_bexp_sound;
try assumption.
SCase "E_Seq". simpl. eapply E_Seq. apply IHceval1. apply IHceval2.
SCase "E_IfTrue". simpl. eapply E_IfTrue.
rewrite <- optimize0_bexp_sound. apply H.
apply IHceval.
SCase "E_IfFalse". eapply E_IfFalse.
rewrite <- optimize0_bexp_sound. apply H.
apply IHceval.
SCase "E_WhileEnd". eapply E_WhileEnd.
rewrite <- optimize0_bexp_sound. apply H.
SCase "E_WhileLoop". eapply E_WhileLoop.
rewrite <- optimize0_bexp_sound. apply H.
apply IHceval1.
simpl in IHceval2. apply IHceval2.
Qed.
Theorem optimize0_com_sound_p2 : forall c st1 st2,
optimize0_com c / st1 || st2 ->
c / st1 || st2.
Proof. com_cases (induction c) SCase; intros; simpl;
try apply E_Skip; try apply E_Ass; simpl in *;
try assumption.
SCase "::=". eapply CAss_congruence.
apply optimize0_aexp_sound. apply H.
SCase ";;". inversion H; subst.
eapply E_Seq.
apply IHc1. apply H2.
apply IHc2. apply H5.
SCase "IFB".
inversion H; subst; [eapply E_IfTrue | eapply E_IfFalse];
try rewrite optimize0_bexp_sound; try apply H5;
try apply IHc1; try apply IHc2; apply H6.
SCase "WHILE".
inversion H; subst; [eapply E_WhileEnd | eapply E_WhileLoop].
rewrite optimize0_bexp_sound. apply H4.
rewrite optimize0_bexp_sound. apply H2.
apply IHc. apply H3.
eapply CWhile_congruence.
apply optimize0_bexp_sound.
split. apply optimize0_com_sound_p1. apply IHc.
apply H6.
Qed.
Theorem optimize0_com_sound : forall c, cequiv c (optimize0_com c).
Proof. split. apply optimize0_com_sound_p1. apply optimize0_com_sound_p2. Qed.
(** [] *)
(* ####################################################### *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1;; Y ::= a2]
and [c2] is the command [X ::= a1;; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;;
Y ::= Y + X)
c2 = (X ::= 42 + 53;;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** Here, formally, is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i' => if eq_id_dec i i' then u else AId i'
| APlus a1 a2 => APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 => AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 => AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53)) (APlus (AId Y) (AId X)) =
(APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(** *** *)
(** Sadly, the property does _not_ always hold.
_Theorem_: It is not the case that, for all [i1], [i2], [a1],
and [a2],
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
]]
_Proof_: Suppose, for a contradiction, that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1);; Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
/ empty_state || st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By our assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
where [st2 = { X |-> 1, Y |-> 2 }]. Note that [st1 <> st2]; this
is a contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (update (update empty_state X 1) Y 1) as st1.
remember (update (update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state || st1);
assert (H2: c2 / empty_state || st2);
try (subst;
apply E_Seq with (st' := (update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (update st i ni) a = aeval st a.
Proof. intros.
aexp_cases (induction a) Case; inversion H; subst; simpl;
try apply IHa1 in H2; try apply IHa2 in H3;
try rewrite H2; try rewrite H3; try reflexivity.
Case "AId". apply update_neq. apply H1.
Qed.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
Lemma update_same_id : forall st i n, update st i n i = n.
Proof. intros. unfold update. apply eq_id. Qed.
Theorem subst_aexp_equiv : forall i a1 a2 st,
aeval st (subst_aexp i a2 a1) = aeval (update st i (aeval st a2)) a1.
Proof. aexp_cases (induction a1) Case; intros; try reflexivity; simpl;
try destruct (eq_id_dec i i0); subst;
try rewrite update_eq; try rewrite update_neq; try assumption;
try rewrite IHa1_1; try rewrite IHa1_2; reflexivity.
Qed.
Theorem update_shadow_id : forall st i n1 n2,
update (update st i n1) i n2 = update st i n2.
Proof. intros. apply functional_extensionality; intros.
unfold update; destruct (eq_id_dec i x); auto. Qed.
Theorem update_elim : forall st i1 i2,
update st i1 (update st i1 (st i2) i2) = update st i1 (st i2).
Proof. intros. apply functional_extensionality. intros. unfold update.
destruct (eq_id_dec i1 x); destruct (eq_id_dec i1 i2); auto. Qed.
Theorem subst_noapp_aexp_equiv : forall i st n a2,
var_not_used_in_aexp i a2 ->
aeval (update st i n) a2 = aeval st a2.
Proof. intros. induction H; auto; simpl;
try rewrite IHvar_not_used_in_aexp1; try rewrite IHvar_not_used_in_aexp2;
unfold update; destruct (eq_id_dec i Y); firstorder.
Qed.
Theorem subst_equiv : forall i1 i2 a1 a2,
var_not_used_in_aexp i1 a1 ->
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Proof. split; intros;
inversion H0; subst; inversion H3; subst;
eapply E_Seq; try apply H3;
inversion H6; eapply E_Ass;
rewrite subst_aexp_equiv in *; rewrite update_shadow_id in *;
rewrite (subst_noapp_aexp_equiv i1 st (aeval st a1) a1) in *;
try apply H7; try apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (inequiv_exercise) *)
(** Prove that an infinite loop is not equivalent to [SKIP] *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof. unfold cequiv. intro.
eapply WHILE_true_nonterm.
apply refl_bequiv.
apply H. apply E_Skip.
Grab Existential Variables. constructor.
Qed.
(** [] *)
(** * Extended exercise: Non-deterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the Imp
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;;
f(++x, x)
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
non-deterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
non-deterministically. For example, after executing the program:
HAVOC Y;;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the _probabilities_ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this non-deterministic code.
In a sense a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in the C programming language. After
the [HAVOC] the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
(**
Module Himp.
(** To formalize the language, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall st st', HAVOC / st || st'.
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state || update empty_state X 0.
Proof.
(* FILL IN HERE *) Admitted.
Example havoc_example2 :
(SKIP;; HAVOC Z) / empty_state || update empty_state Z 42.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st || st' <-> c2 / st || st'.
(** This definition still makes perfect sense in the case of always
terminating programs, so let's apply it to prove some
non-deterministic programs equivalent or non-equivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X;; HAVOC Y.
Definition pYX :=
HAVOC Y;; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~cequiv pXY pYX.
Proof. (* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, optional (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X;; HAVOC Y.
Definition pcopy :=
HAVOC X;; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with non-determinism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
non-deterministically terminate in some runs and diverge in
others. The final part of the following exercise illustrates this
phenomenon.
*)
(** **** Exercise: 5 stars, advanced (p1_p2_equiv) *)
(** Prove that p1 and p2 are equivalent. In this and the following
exercises, try to understand why the [cequiv] definition has the
behavior it has on these examples. *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
(** Intuitively, the programs have the same termination
behavior: either they loop forever, or they terminate in the
same state they started in. We can capture the termination
behavior of p1 and p2 individually with these lemmas: *)
Lemma p1_may_diverge : forall st st', st X <> 0 ->
~ p1 / st || st'.
Proof. (* FILL IN HERE *) Admitted.
Lemma p2_may_diverge : forall st st', st X <> 0 ->
~ p2 / st || st'.
Proof.
(* FILL IN HERE *) Admitted.
(** You should use these lemmas to prove that p1 and p2 are actually
equivalent. *)
Theorem p1_p2_equiv : cequiv p1 p2.
Proof. (* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced (p3_p4_inquiv) *)
(** Prove that the following programs are _not_ equivalent. *)
Definition p3 : com :=
Z ::= ANum 1;;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);;
Z ::= (ANum 1).
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof. (* FILL IN HERE *) Admitted.
(** **** Exercise: 5 stars, advanced, optional (p5_p6_equiv) *)
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
Theorem p5_p6_equiv : cequiv p5 p6.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
End Himp.
*)
(** weird glitches in the implementation here, I'm going to skip it for now *)
(* ####################################################### *)
(** * Doing Without Extensionality (Optional) *)
(** Purists might object to using the [functional_extensionality]
axiom. In general, it can be quite dangerous to add axioms,
particularly several at once (as they may be mutually
inconsistent). In fact, [functional_extensionality] and
[excluded_middle] can both be assumed without any problems, but
some Coq users prefer to avoid such "heavyweight" general
techniques, and instead craft solutions for specific problems that
stay within Coq's standard logic.
For our particular problem here, rather than extending the
definition of equality to do what we want on functions
representing states, we could instead give an explicit notion of
_equivalence_ on states. For example: *)
Definition stequiv (st1 st2 : state) : Prop :=
forall (X:id), st1 X = st2 X.
Notation "st1 ~~ st2" := (stequiv st1 st2) (at level 30).
(** It is easy to prove that [stequiv] is an _equivalence_ (i.e., it
is reflexive, symmetric, and transitive), so it partitions the set
of all states into equivalence classes. *)
(** **** Exercise: 1 star, optional (stequiv_refl) *)
Lemma stequiv_refl : forall (st : state),
st ~~ st.
Proof. intros. intro. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_sym) *)
Lemma stequiv_sym : forall (st1 st2 : state),
st1 ~~ st2 ->
st2 ~~ st1.
Proof. intros. intro. rewrite H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_trans) *)
Lemma stequiv_trans : forall (st1 st2 st3 : state),
st1 ~~ st2 ->
st2 ~~ st3 ->
st1 ~~ st3.
Proof. intros. intro. rewrite H. apply H0. Qed.
(** Another useful fact... *)
(** **** Exercise: 1 star, optional (stequiv_update) *)
Lemma stequiv_update : forall (st1 st2 : state),
st1 ~~ st2 ->
forall (X:id) (n:nat),
update st1 X n ~~ update st2 X n.
Proof. intros. intro. unfold update. rewrite H. reflexivity. Qed.
(** [] *)
(** It is then straightforward to show that [aeval] and [beval] behave
uniformly on all members of an equivalence class: *)
(** **** Exercise: 2 stars, optional (stequiv_aeval) *)
Lemma stequiv_aeval : forall (st1 st2 : state),
st1 ~~ st2 ->
forall (a:aexp), aeval st1 a = aeval st2 a.
Proof. intros. induction a; auto; simpl; try apply H;
rewrite IHa1; rewrite IHa2; reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (stequiv_beval) *)
Lemma stequiv_beval : forall (st1 st2 : state),
st1 ~~ st2 ->
forall (b:bexp), beval st1 b = beval st2 b.
Proof. intros. induction b; auto; simpl;
repeat rewrite (stequiv_aeval st1 st2); try assumption;
try rewrite IHb; try rewrite IHb1; try rewrite IHb2;
try reflexivity. Qed.
(** [] *)
(** We can also characterize the behavior of [ceval] on equivalent
states (this result is a bit more complicated to write down
because [ceval] is a relation). *)
Lemma stequiv_ceval: forall (st1 st2 : state),
st1 ~~ st2 ->
forall (c: com) (st1': state),
(c / st1 || st1') ->
exists st2' : state,
((c / st2 || st2') /\ st1' ~~ st2').
Proof.
intros st1 st2 STEQV c st1' CEV1. generalize dependent st2.
induction CEV1; intros st2 STEQV.
Case "SKIP".
exists st2. split.
constructor.
assumption.
Case ":=".
exists (update st2 x n). split.
constructor. rewrite <- H. symmetry. apply stequiv_aeval.
assumption. apply stequiv_update. assumption.
Case ";".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_Seq with st2'; assumption.
assumption.
Case "IfTrue".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfTrue. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "IfFalse".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfFalse. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "WhileEnd".
exists st2. split.
apply E_WhileEnd. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption.
Case "WhileLoop".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_WhileLoop with st2'. rewrite <- H. symmetry.
apply stequiv_beval. assumption. assumption. assumption.
assumption.
Qed.
(** Now we need to redefine [cequiv] to use [~] instead of [=]. It is
not completely trivial to do this in a way that keeps the
definition simple and symmetric, but here is one approach (thanks
to Andrew McCreight). We first define a looser variant of [||]
that "folds in" the notion of equivalence. *)
Reserved Notation "c1 '/' st '||'' st'" (at level 40, st at level 39).
Inductive ceval' : com -> state -> state -> Prop :=
| E_equiv : forall c st st' st'',
c / st || st' ->
st' ~~ st'' ->
c / st ||' st''
where "c1 '/' st '||'' st'" := (ceval' c1 st st').
(** Now the revised definition of [cequiv'] looks familiar: *)
Definition cequiv' (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st ||' st') <-> (c2 / st ||' st').
(** A sanity check shows that the original notion of command
equivalence is at least as strong as this new one. (The converse
is not true, naturally.) *)
Lemma cequiv__cequiv' : forall (c1 c2: com),
cequiv c1 c2 -> cequiv' c1 c2.
Proof.
unfold cequiv, cequiv'; split; intros.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0); assumption. assumption.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0). assumption. assumption.
Qed.
(** **** Exercise: 2 stars, optional (identity_assignment') *)
(** Finally, here is our example once more... (You can complete the
proof.) *)
Example identity_assignment' :
cequiv' SKIP (X ::= AId X).
Proof.
unfold cequiv'. intros. split; intros.
Case "->".
inversion H; subst; clear H. inversion H0; subst.
apply E_equiv with (update st'0 X (st'0 X)).
constructor. reflexivity. apply stequiv_trans with st'0.
unfold stequiv. intros. apply update_same.
reflexivity. assumption.
Case "<-".
inversion H; inversion H0; subst; simpl in *.
eapply E_equiv. constructor.
apply stequiv_trans with (st2 := update st X (st X)).
intro. symmetry; apply update_same; auto.
apply H1.
Qed.
(** [] *)
(** On the whole, this explicit equivalence approach is considerably
harder to work with than relying on functional
extensionality. (Coq does have an advanced mechanism called
"setoids" that makes working with equivalences somewhat easier, by
allowing them to be registered with the system so that standard
rewriting tactics work for them almost as well as for equalities.)
But it is worth knowing about, because it applies even in
situations where the equivalence in question is _not_ over
functions. For example, if we chose to represent state mappings
as binary search trees, we would need to use an explicit
equivalence of this kind. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
Imp.v, where you were asked to extend the language of commands
with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1;; l2 ::= a2)
(l2 ::= a2;; l1 ::= a1).
Proof.
(* Hint: You'll need [functional_extensionality] *)
(* FILL IN HERE *) Admitted.
(** [] *)
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 4
*/
// Testbench for behavioral model for the register file
// Import the modules that will be tested for in this testbench
`include "regfile.v"
// IMPORTANT: To run this, try: ncverilog -f regfile.f +gui
module tb_regfile();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & out_valid output signals
wire [WIDTH-1:0] d_out;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren
reg clock,wr_en;
// data_in
reg [WIDTH-1:0] d_in;
// wraddr, rdaddr
reg [DEPTH-1:0] w_addr,r_addr ;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
regfile rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,d_in,w_addr,r_addr,wr_en,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
d_in=8'd6;
w_addr=3'd0;
r_addr=3'd0;
wr_en=1;
#10
d_in=8'd7;
w_addr=3'd0;
r_addr=3'd0;
wr_en=0;
// Write...
#10
d_in=8'd6;
w_addr=3'd2;
r_addr=3'd0;
wr_en=1;
#10
d_in=8'd5;
w_addr=3'd3;
r_addr=3'd1;
wr_en=1;
#10
d_in=8'd100;
w_addr=3'd4;
r_addr=3'd7;
wr_en=1;
#10
d_in=8'd200;
w_addr=3'd5;
r_addr=3'd6;
wr_en=1;
// Read...
#10
d_in=8'd3;
w_addr=3'd4;
r_addr=3'd2;
wr_en=0;
#10
d_in=8'd2;
w_addr=3'd5;
r_addr=3'd3;
wr_en=0;
#10
d_in=8'd1;
w_addr=3'd6;
r_addr=3'd4;
wr_en=0;
#10
d_in=8'd0;
w_addr=3'd7;
r_addr=3'd5;
wr_en=0;
#10
d_in=8'd5;
w_addr=3'd7;
r_addr=3'd1;
wr_en=1;
#10
d_in=8'd0;
w_addr=3'd2;
r_addr=3'd7;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:10:24 11/22/2016
// Design Name:
// Module Name: mouse_out
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mouse_out(
input wire [9:0] mouse_x,
input wire [8:0] mouse_y,
input btnm,
output reg [4:0]code
);
reg [1:0] row;
reg [2:0] column;
always @(*)
begin
if (mouse_y >= 204 && mouse_y < 228) //fila 0
begin
row = 0;
end
else if(mouse_y >= 248 && mouse_y < 272) //fila 1
begin
row = 1;
end
else if(mouse_y >= 292 && mouse_y < 316) //fila 2
begin
row = 2; //ninguna fila
end
else
begin
row = 3;
end
if (mouse_x >= 220 && mouse_x < 244) //columna 0
begin
column = 0;
end
else if(mouse_x >= 264 && mouse_x < 288) //columna 1
begin
column = 1;
end
else if(mouse_x >= 308 && mouse_x < 332) //columna 2
begin
column = 2;
end
else if(mouse_x >= 352 && mouse_x < 376) //columna 3
begin
column = 3;
end
else if(mouse_x >= 396 && mouse_x < 420) //columna 4
begin
column = 4;
end
else if(mouse_x >= 440 && mouse_x < 462) //columna 5
begin
column = 5;
end
else //ninguna fila
begin
column = 6;
end
end
always @(*)
begin
if(btnm && row < 3 && column < 6)
begin
code = {(row * 6) + column}[4:0];
end
else
begin
code = 5'b10010;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_1_V
`define SKY130_FD_SC_HVL__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_1_V
|
module EP2C5(clk50M, key0, led0, led1, led2, MIDI_IN,
vcf_out, n_vcf_out,
//iis
DAT, MCK, SCK, LRCK,
//PWM out
PWM
);
//ports
input wire clk50M, key0, MIDI_IN;
output wire led0, led1, led2;
output wire vcf_out, n_vcf_out;
//iis
output wire DAT, MCK, SCK, LRCK;
//PWM
output wire PWM;
//генератор сброса
wire rst;
powerup_reset res_gen(.clk(clk50M), .key(~key0), .rst(rst));
//synth
//MIDI вход
wire [3:0] CH_MESSAGE;
wire [3:0] CHAN;
wire [6:0] NOTE;
wire [6:0] LSB;
wire [6:0] MSB;
midi_in midi_in_0(.clk(clk50M),
.rst(rst),
.midi_in(MIDI_IN),
.chan(CHAN),
.ch_message(CH_MESSAGE),
.lsb(LSB),
.msb(MSB),
.note(NOTE));
//ловим ноту на любом
wire NOTE_ON = (CH_MESSAGE==4'b1001); //строб признак появления сообщения note on
wire NOTE_OFF = (CH_MESSAGE==4'b1000); //строб признак появления сообщения note off
wire GATE; // сигнал GATE в единице между note on и note off
//wire [6:0] LAST_NOTE; //последняя полученная нота
//масштабирование
wire [31:0] add_value;
lin2exp_t exp(.data_in(MSB), .data_out(add_value));
//ADSR
//A1
wire [13:0] A1;
wire A1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd016))||rst; // control change & 16 control - LSB
wire [13:0] A1_value = (rst) ? 14'd07540 : add_value[13:0];
reg14w A1reg(clk50M, A1_lsb, A1_value, A1);
//D1
wire [13:0] D1;
wire D1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd017))||rst; // control change & 17 control - LSB
wire [13:0] D1_value = (rst) ? 14'd07540 : add_value[13:0];
reg14w D1reg(clk50M, D1_lsb, D1_value, D1);
//S1
wire [6:0] S1;
wire S1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd018))||rst; // control change & 18 control - LSB
wire [6:0] S1_value = (rst) ? 7'b1111111 : MSB;
reg7 S1reg(clk50M, S1_lsb, S1_value, S1);
//R1
wire [13:0] R1;
wire R1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd019))||rst; // control change & 19 control - LSB
wire [13:0] R1_value = (rst) ? 14'd07540 : add_value[13:0];
reg14w R1reg(clk50M, R1_lsb, R1_value, R1);
//c1 gen for vcf
wire [6:0] C1;
wire C1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd055))||rst; // control change & 55 control - LSB
wire [6:0] C1_value = (rst) ? 7'd00 : MSB;
reg7 C1_reg(clk50M, C1_lsb, C1_value, C1);
wire [31:0] vcfg_out;
reg [31:0] vcf_adder; initial vcf_adder <=32'd2748779;
always @(posedge clk50M) begin
//vcf_adder <= 32'd2748779 + C1 * 24'd272129;
vcf_adder <= 32'd1374389 + C1 * 24'd600000;
end
dds #(.WIDTH(32)) lvcf_osc1(.clk(clk50M), .adder(vcf_adder), .signal_out(vcfg_out));
assign vcf_out = vcfg_out[31];//(hi_out<8'd64);
assign n_vcf_out = ~vcfg_out[31];//(hi_out>8'd127)&&(hi_out<=8'd255);
reg note_on_reg; initial note_on_reg <= 1'b0;
wire [31:0] adder_val;
reg [6:0] LAST_NOTE; initial LAST_NOTE <= 7'd0;
note2dds transl1(.clk(clk50M),
.note(LAST_NOTE),
.adder(adder_val));
always @(posedge clk50M) begin
if (NOTE_ON) begin
note_on_reg <= 1'b1;
LAST_NOTE <= NOTE;
end else if (NOTE_OFF) begin
note_on_reg <= 1'b0;
end
end
assign led0 = MIDI_IN;
assign led1 = ~note_on_reg;
assign led2 = 1'b1;
wire [31:0] saw_out;
dds #(.WIDTH(32)) osc1(.clk(clk50M), .adder(adder_val), .signal_out(saw_out));
//PWM
wire [7:0] saw_out_8bit = (note_on_reg) ? saw_out[31:31-7] : 8'd127;
pwm8dac1 dac1(.clk(clk50M),
.in_data(saw_out_8bit),
.sout(PWM));
//wire [31:0] us_data_left = data_left + 32'b10000000000000000000000000000000; //signed data in unsigned register. this is conversion
wire [31:0] l_data = (note_on_reg) ? saw_out - 32'b10000000000000000000000000000000 : 32'b10000000000000000000000000000000;
wire [31:0] r_data = (note_on_reg) ? saw_out - 32'b10000000000000000000000000000000 : 32'b10000000000000000000000000000000;
i2s_dco #(.DATA_WIDTH(32)) iis_tx(
.clk(clk50M),
.adder(adder_val),
.note_on(note_on_reg),
.sdata(DAT),
.mck(MCK),
.sck(SCK),
.lrclk(LRCK)
);
endmodule
|
/*
* This file was generated by the scsynth tool, and is availablefor use under
* the MIT license. More information can be found at
* https://github.com/arminalaghi/scsynth/
*/
module MReSC_example( //the stochastic core of an ReSC
input [2:0] x_1, //independent copies of x_1
input [4:0] x_2, //independent copies of x_2
input [1:0] x_3, //independent copies of x_3
input [71:0] w, //Bernstein coefficients
output reg z //output bitsream
);
wire [1:0] sum_1; //sum of x values for mux
assign sum_1 = x_1[0] + x_1[1] + x_1[2];
wire [2:0] sum_2; //sum of x values for mux
assign sum_2 = x_2[0] + x_2[1] + x_2[2] + x_2[3] + x_2[4];
wire [0:0] sum_3; //sum of x values for mux
assign sum_3 = x_3[0] + x_3[1];
always @(*) begin
case(sum_1)
2'd0: case(sum_2)
3'd0: case(sum_3)
1'd0: z = w[0];
1'd1: z = w[1];
1'd2: z = w[2];
default: z = 0;
endcase
3'd1: case(sum_3)
1'd0: z = w[3];
1'd1: z = w[4];
1'd2: z = w[5];
default: z = 0;
endcase
3'd2: case(sum_3)
1'd0: z = w[6];
1'd1: z = w[7];
1'd2: z = w[8];
default: z = 0;
endcase
3'd3: case(sum_3)
1'd0: z = w[9];
1'd1: z = w[10];
1'd2: z = w[11];
default: z = 0;
endcase
3'd4: case(sum_3)
1'd0: z = w[12];
1'd1: z = w[13];
1'd2: z = w[14];
default: z = 0;
endcase
3'd5: case(sum_3)
1'd0: z = w[15];
1'd1: z = w[16];
1'd2: z = w[17];
default: z = 0;
endcase
default: z = 0;
endcase
2'd1: case(sum_2)
3'd0: case(sum_3)
1'd0: z = w[18];
1'd1: z = w[19];
1'd2: z = w[20];
default: z = 0;
endcase
3'd1: case(sum_3)
1'd0: z = w[21];
1'd1: z = w[22];
1'd2: z = w[23];
default: z = 0;
endcase
3'd2: case(sum_3)
1'd0: z = w[24];
1'd1: z = w[25];
1'd2: z = w[26];
default: z = 0;
endcase
3'd3: case(sum_3)
1'd0: z = w[27];
1'd1: z = w[28];
1'd2: z = w[29];
default: z = 0;
endcase
3'd4: case(sum_3)
1'd0: z = w[30];
1'd1: z = w[31];
1'd2: z = w[32];
default: z = 0;
endcase
3'd5: case(sum_3)
1'd0: z = w[33];
1'd1: z = w[34];
1'd2: z = w[35];
default: z = 0;
endcase
default: z = 0;
endcase
2'd2: case(sum_2)
3'd0: case(sum_3)
1'd0: z = w[36];
1'd1: z = w[37];
1'd2: z = w[38];
default: z = 0;
endcase
3'd1: case(sum_3)
1'd0: z = w[39];
1'd1: z = w[40];
1'd2: z = w[41];
default: z = 0;
endcase
3'd2: case(sum_3)
1'd0: z = w[42];
1'd1: z = w[43];
1'd2: z = w[44];
default: z = 0;
endcase
3'd3: case(sum_3)
1'd0: z = w[45];
1'd1: z = w[46];
1'd2: z = w[47];
default: z = 0;
endcase
3'd4: case(sum_3)
1'd0: z = w[48];
1'd1: z = w[49];
1'd2: z = w[50];
default: z = 0;
endcase
3'd5: case(sum_3)
1'd0: z = w[51];
1'd1: z = w[52];
1'd2: z = w[53];
default: z = 0;
endcase
default: z = 0;
endcase
2'd3: case(sum_2)
3'd0: case(sum_3)
1'd0: z = w[54];
1'd1: z = w[55];
1'd2: z = w[56];
default: z = 0;
endcase
3'd1: case(sum_3)
1'd0: z = w[57];
1'd1: z = w[58];
1'd2: z = w[59];
default: z = 0;
endcase
3'd2: case(sum_3)
1'd0: z = w[60];
1'd1: z = w[61];
1'd2: z = w[62];
default: z = 0;
endcase
3'd3: case(sum_3)
1'd0: z = w[63];
1'd1: z = w[64];
1'd2: z = w[65];
default: z = 0;
endcase
3'd4: case(sum_3)
1'd0: z = w[66];
1'd1: z = w[67];
1'd2: z = w[68];
default: z = 0;
endcase
3'd5: case(sum_3)
1'd0: z = w[69];
1'd1: z = w[70];
1'd2: z = w[71];
default: z = 0;
endcase
default: z = 0;
endcase
default: z = 0;
endcase
end
endmodule
|
// File: clock.v
// Generated by MyHDL 0.8.1
// Date: Sun May 15 22:24:35 2016
`timescale 500ms/1ms
module clock (
clk,
fast_clk,
rst,
en,
sec,
pm,
io_seg,
io_sel
);
input clk;
input fast_clk;
input rst;
input en;
output [7:0] sec;
reg [7:0] sec;
output [17:0] pm;
reg [17:0] pm;
output [7:0] io_seg;
wire [7:0] io_seg;
output [3:0] io_sel; // Digit select on IO Shield
wire [3:0] io_sel;
reg [3:0] count [0:6-1];
reg [1:0] i, j;
// CLOCK_DECODER 74LS247
assign io_seg[0] = (((count[i+2][0] && (!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3])) || ((!count[i+2][0]) && (!count[i+2][1]) && count[i+2][2]) || (count[i+2][1] && count[i+2][3])) != 0);
assign io_seg[1] = (((count[i+2][0] && (!count[i+2][1]) && count[i+2][2]) || ((!count[i+2][0]) && count[i+2][1] && count[i+2][2]) || (count[i+2][1] && count[i+2][3])) != 0);
assign io_seg[2] = ((((!count[i+2][0]) && count[i+2][1] && (!count[i+2][2])) || (count[i+2][2] && count[i+2][3])) != 0);
assign io_seg[3] = (((count[i+2][0] && (!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3])) || (count[i+2][0] && count[i+2][1] && count[i+2][2]) || ((!count[i+2][0]) && (!count[i+2][1]) && count[i+2][2])) != 0);
assign io_seg[4] = ((count[i+2][0] || ((!count[i+2][1]) && count[i+2][2])) != 0);
assign io_seg[5] = (((count[i+2][0] && (!count[i+2][2]) && (!count[i+2][3])) || (count[i+2][0] && count[i+2][1]) || (count[i+2][1] && (!count[i+2][2]))) != 0);
assign io_seg[6] = (((count[i+2][0] && count[i+2][1] && count[i+2][2]) || ((!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3]))) != 0);
assign io_seg[7] = 1'b1 && ~(~i[0] && i[1]);
// Select 7-segment display to show digit
assign io_sel[0] = ~(~i[0] && ~i[1]);
assign io_sel[1] = ~(i[0] && ~i[1]);
assign io_sel[2] = ~(~i[0] && i[1]);
assign io_sel[3] = ~(i[0] && i[1]) || (count[5] == 0);
always @(i) begin
j = i + 1'b1;
end
always @(posedge fast_clk, negedge fast_clk) begin
if (rst) begin
i <= 1'b0;
end else begin
i <= j;
end
end
always @(posedge clk, posedge rst) begin: CLOCK_COUNTER
if (rst) begin
count[0] <= 0;
count[1] <= 0;
count[2] <= 0;
count[3] <= 0;
count[4] <= 0;
end else if (en) begin
count[0] <= ((count[0] + 1) % 10);
count[1] <= ((count[1] + (count[0] == 9)) % 6);
count[2] <= ((count[2] + ((count[0] == 9) && (count[1] == 5))) % 10);
count[3] <= ((count[3] + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9))) % 6);
count[4] <= (((count[4] + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5))) % (10 - (7 * count[5]))) + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 2) && (count[5] != 0)));
end
end
always @(posedge clk, posedge rst) begin: CLOCK_TFF
if (rst) begin
count[5] <= 0;
pm <= 18'b0;
sec <= 8'b0;
end else if (en) begin
count[5] <= ((count[5] != 0) ^ (((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 9)) || ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 2) && (count[5] != 0))));
pm <= {18{(pm[0] ^ ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 1) && (count[5] != 0)))}};
sec <= (count[0]+10*count[1]+1) % 60;
end
end
endmodule |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fb_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fb_ram (
address_a,
address_b,
data_a,
data_b,
inclock,
outclock,
wren_a,
wren_b,
q_a,
q_b);
input [15:0] address_a;
input [15:0] address_b;
input [7:0] data_a;
input [7:0] data_b;
input inclock;
input outclock;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 inclock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (inclock),
.clock1 (outclock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.numwords_b = 65536,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK1",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "2"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "524288"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 16 0 INPUT NODEFVAL "address_a[15..0]"
// Retrieval info: USED_PORT: address_b 0 0 16 0 INPUT NODEFVAL "address_b[15..0]"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC "inclock"
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL "outclock"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address_a 0 0 16 0
// Retrieval info: CONNECT: @address_b 0 0 16 0 address_b 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fb_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_2_V
`define SKY130_FD_SC_HS__XNOR2_2_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor2_2 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_2_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_s_r_channel.v
// Version : v1.0
// Description: slave interface read channel.Read requests are processed to
// output the desired read data.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
//Specific WARNINGs moved to INFO by Vivado Synthesis Tool
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_s_r_channel
# (
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_ZERO_INVALID = 1 ,
parameter C_NO_EXCL = 0 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_S_AXI_ARUSER_WIDTH = 8 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
//AR
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input [7:0] arlen_s ,
input [2:0] arsize_s ,
input [1:0] arburst_s ,
input [0:0] arlock_s ,
input [3:0] arcache_s ,
input [2:0] arprot_s ,
input [3:0] arqos_s ,
input [C_S_AXI_ARUSER_WIDTH-1:0] aruser_s ,
input arvalid_s ,
output arready_s ,
//R
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
// Register block
input reg1_sgl_slv_rd ,
output [15:0] rd_reg_decode ,
input [31:0] rd_reg_data_raw ,
input reg1_disallow_excl ,
output reg rddec6_valid_ff ,
//sw channel
output reg [71:0] slv_ex_info0_ff ,
input slv_ex_valid0_ff ,
output reg [71:0] slv_ex_info1_ff ,
output[71:0] slv_ex_info1 ,
input slv_ex_valid1_ff ,
output reg slv_ex_toggle_ff ,
output slv_ex_new_valid0 ,
output slv_ex_new_valid1 ,
output [15:0] ar_agen_addr ,
input [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ,
//axi addressram
input [31:0] addrram_rd_out ,
//axi_traffic_gen_v2_0_7_cmdram input
output [15:0] ar_agen0_addr ,
output ar_agen0_valid_out ,
output arfifo_valid ,
output [71:0] arfifo_out ,
input [127:0] cmd_out_mr_i
);
wire [31:0] base_addr = C_BASEADDR;
wire [31:0] high_addr = C_HIGHADDR;
wire [31:0] addr_mask = base_addr[31:0] ^ high_addr[31:0];
//wire [7:0] arlen8_s = arlen_s[7:0] | { 4'h0, arlen3_s[3:0] };
wire [7:0] arlen8_s = arlen_s[7:0] ;
wire [31:0] ar_addr_masked = araddr_s[31:0] & addr_mask[31:0];
//Address re-mapped
//wire ar_isslvram = (ar_addr_masked[22:16] != 'h0);
wire ar_isslvram = (ar_addr_masked[15:14] == 2'b11);
wire ar_iscmd = ~ar_isslvram && araddr_s[15] && ~araddr_s[13];
wire [15:0] arbuf_id = arid_s[C_S_AXI_ID_WIDTH-1:0];
wire [71:0] arbuf_data = {
arbuf_id[15:0], //71:56
ar_isslvram, ar_iscmd, arprot_s[2:0], arsize_s[2:0], //55:48
arburst_s[1:0], 1'b0,arlock_s[0:0], arcache_s[3:0], //47:40 //arlock made 1-bit
arlen8_s[7:0], //39:32
araddr_s[31:0] }; //31:0
wire ar_agen0_valid, ar_agen1_valid, ar_agen2_valid, ar_agen3_valid;
wire arfifo_notfull;
wire arfifo_push = arvalid_s && arready_s;
wire arfifo_pop;
assign ar_agen0_valid_out = ar_agen0_valid;
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (72),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Arfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (arbuf_data[71:0] ),
.in_push (arfifo_push ),
.in_pop (arfifo_pop ),
.out_data (arfifo_out[71:0] ),
.is_full ( ),
.is_notfull (arfifo_notfull ),
.is_empty ( ),
.out_valid (arfifo_valid ),
.ex_fifo_dbgout ( )
);
assign arready_s = arfifo_notfull;
wire [1:0] arfifo_out_lock = arfifo_out[45:44];
wire [71:0] slv_new_ex_info = arfifo_out[71:0];
wire slv_ex_new_valid ;
wire slv_ex_must_wr0 ;
wire slv_ex_must_wr1 ;
wire slv_ex_use_toggle ;
wire slv_ex_choose1 ;
wire slv_ex_toggle ;
wire [71:0] slv_ex_info0 ;
wire [1:0] ar_calc_resp ;
generate if(C_NO_EXCL == 0) begin : S_R_EXCL_0
assign slv_ex_new_valid = arfifo_valid && (arfifo_out_lock[1:0] == 2'b01) &&
(C_NO_EXCL == 0);
assign slv_ex_must_wr0 = ~slv_ex_valid0_ff ||
(slv_ex_info0_ff[71:56] == slv_new_ex_info[71:56]);
assign slv_ex_must_wr1 = ~slv_ex_valid1_ff ||
(slv_ex_info1_ff[71:56] == slv_new_ex_info[71:56]);
assign slv_ex_use_toggle = ~slv_ex_must_wr0 && ~slv_ex_must_wr1;
assign slv_ex_choose1 = (slv_ex_use_toggle) ? slv_ex_toggle_ff :
slv_ex_must_wr1;
assign slv_ex_new_valid0 = slv_ex_new_valid && ~slv_ex_choose1;
assign slv_ex_new_valid1 = slv_ex_new_valid && slv_ex_choose1;
assign slv_ex_toggle = (slv_ex_use_toggle && slv_ex_new_valid) ?
~slv_ex_toggle_ff : slv_ex_toggle_ff;
assign slv_ex_info0 = (slv_ex_new_valid0) ? slv_new_ex_info[71:0] :
slv_ex_info0_ff[71:0];
assign slv_ex_info1 = (slv_ex_new_valid1) ? slv_new_ex_info[71:0] :
slv_ex_info1_ff[71:0];
assign ar_calc_resp = (arfifo_out_lock[1:0] == 2'b01) ? 2'b01 : 2'b00;
end
endgenerate
generate if(C_NO_EXCL == 1) begin : S_R_EXCL_1
assign slv_ex_info0 = 72'h0;
assign slv_ex_info1 = 72'h0;
assign slv_ex_toggle = 1'b0;
assign slv_ex_new_valid0 = 1'b0;
assign slv_ex_new_valid1 = 1'b0;
assign ar_calc_resp = 2'b00;
end
endgenerate
wire ar_agen0_pop, ar_agen1_pop, ar_agen2_pop, ar_agen3_pop;
wire ar_agen0_done, ar_agen1_done, ar_agen2_done, ar_agen3_done;
wire [3:0] artrk_fifo_num;
wire [C_S_AXI_ID_WIDTH-1:0] artrk_in_push_id = arfifo_out[71:56];
wire ar_agen0_eff_valid = ar_agen0_valid && ~(ar_agen0_done && ar_agen0_pop);
wire ar_agen1_eff_valid = ar_agen1_valid && ~(ar_agen1_done && ar_agen1_pop);
wire ar_agen2_eff_valid = ar_agen2_valid && ~(ar_agen2_done && ar_agen2_pop);
wire ar_agen3_eff_valid = ar_agen3_valid && ~(ar_agen3_done && ar_agen3_pop);
wire [3:0] ar_agen_eff_valid = { ar_agen3_eff_valid, ar_agen2_eff_valid,
ar_agen1_eff_valid, ar_agen0_eff_valid };
wire [3:0] ar_agen_push = ~ar_agen_eff_valid[3:0] & artrk_fifo_num[3:0];
wire [3:0] artrk_clear_pos = ~ar_agen_eff_valid[3:0];
assign arfifo_pop = arfifo_valid && (ar_agen_push[3:0] != 4'h0);
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_R_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_R_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
axi_traffic_gen_v2_0_7_id_track #(
.ID_WIDTH(C_S_AXI_ID_WIDTH)
) Ar_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (artrk_in_push_id[C_S_AXI_ID_WIDTH-1:0]),
.in_push (arfifo_valid ),
.in_search_id ({ C_S_AXI_ID_WIDTH { 1'b0 } } ),
.in_clear_pos (artrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (artrk_fifo_num[3:0] ),
.out_search_hit( ),
.out_free ( )
);
wire [3:0] arbuf_wrsel = (arfifo_pop) ? ar_agen_push[3:0] : 4'h0;
wire [15:0] ar_agen0_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen0_be;
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[0] ),
.in_pop (ar_agen0_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen0_addr[15:0] ),
.out_be (ar_agen0_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen0_id[15:0] ),
.out_done (ar_agen0_done ),
.out_valid (ar_agen0_valid )
);
wire [15:0] ar_agen1_addr, ar_agen1_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen1_be;
wire [15:0] ar_agen2_addr, ar_agen2_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen2_be;
wire [15:0] ar_agen3_addr, ar_agen3_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen3_be;
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_R_OOO_F_NO
assign ar_agen1_done = 1'b0;
assign ar_agen2_done = 1'b0;
assign ar_agen3_done = 1'b0;
assign ar_agen1_valid = 1'b0;
assign ar_agen2_valid = 1'b0;
assign ar_agen3_valid = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_R_OOO_F_YES
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[1] ),
.in_pop (ar_agen1_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen1_addr[15:0] ),
.out_be (ar_agen1_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen1_id[15:0] ),
.out_done (ar_agen1_done ),
.out_valid (ar_agen1_valid )
);
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[2] ),
.in_pop (ar_agen2_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen2_addr[15:0] ),
.out_be (ar_agen2_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen2_id[15:0] ),
.out_done (ar_agen2_done ),
.out_valid (ar_agen2_valid )
);
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[3] ),
.in_pop (ar_agen3_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen3_addr[15:0] ),
.out_be (ar_agen3_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen3_id[15:0] ),
.out_done (ar_agen3_done ),
.out_valid (ar_agen3_valid )
);
end
endgenerate
wire [3:0] ar_agen_sel ;
wire [15:0] ar_agen_id ;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen_be ;
wire ar_agen_done ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_R1_OOO_F_YES
assign ar_agen_sel = (ar_agen3_valid) ? 4'h8 :
(ar_agen2_valid) ? 4'h4 :
(ar_agen1_valid) ? 4'h2 :
(ar_agen0_valid) ? 4'h1 : 4'h0;
assign ar_agen_addr = ((ar_agen_sel[0]) ? ar_agen0_addr[15:0] : 16'h0) |
((ar_agen_sel[1]) ? ar_agen1_addr[15:0] : 16'h0) |
((ar_agen_sel[2]) ? ar_agen2_addr[15:0] : 16'h0) |
((ar_agen_sel[3]) ? ar_agen3_addr[15:0] : 16'h0);
assign ar_agen_id = ((ar_agen_sel[0]) ? ar_agen0_id[15:0] : 16'h0) |
((ar_agen_sel[1]) ? ar_agen1_id[15:0] : 16'h0) |
((ar_agen_sel[2]) ? ar_agen2_id[15:0] : 16'h0) |
((ar_agen_sel[3]) ? ar_agen3_id[15:0] : 16'h0);
assign ar_agen_be =
((ar_agen_sel[0]) ? ar_agen0_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) |
((ar_agen_sel[1]) ? ar_agen1_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) |
((ar_agen_sel[2]) ? ar_agen2_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) |
((ar_agen_sel[3]) ? ar_agen3_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) ;
assign ar_agen_done = ((ar_agen_sel[0]) ? ar_agen0_done : 1'b0) |
((ar_agen_sel[1]) ? ar_agen1_done : 1'b0) |
((ar_agen_sel[2]) ? ar_agen2_done : 1'b0) |
((ar_agen_sel[3]) ? ar_agen3_done : 1'b0);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_R1_OOO_F_NO
assign ar_agen_sel = (ar_agen0_valid) ? 4'h1 : 4'h0;
assign ar_agen_addr = ((ar_agen_sel[0]) ? ar_agen0_addr[15:0] : 16'h0) ;
assign ar_agen_id = ((ar_agen_sel[0]) ? ar_agen0_id[15:0] : 16'h0) ;
assign ar_agen_be =
((ar_agen_sel[0]) ? ar_agen0_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) ;
assign ar_agen_done = ((ar_agen_sel[0]) ? ar_agen0_done : 1'b0) ;
end
endgenerate
assign rd_reg_decode = 16'h1 << ar_agen_addr[5:2];
wire rd_reg_err = (ar_agen_addr[15:14] == 2'b00) && rd_reg_decode[13] &&
ar_agen_addr[7];
wire [1:0] rd_reg_rresp = (reg1_disallow_excl) ? 2'b00 :
(rd_reg_err) ? 2'b10 : ar_agen_id[15:14];
wire [56+C_S_AXI_DATA_WIDTH/8-1:0] rd_reg_data = { ar_agen_be[C_S_AXI_DATA_WIDTH/8-1:0], //63:56
ar_agen_id[15:0], //55:40
ar_agen_addr[15:14], ar_agen_addr[3:2], //39:36
1'b0, ar_agen_done, rd_reg_rresp[1:0], //35:32
rd_reg_data_raw[31:0] }; //31:0
wire rdataout_full;
wire [C_S_AXI_DATA_WIDTH+24-1:0] rdata_pre;
reg rd_reg_valid_ff;
assign ar_agen0_pop = ar_agen_sel[0] && ~rdataout_full ;
assign ar_agen1_pop = ar_agen_sel[1] && ~rdataout_full ;
assign ar_agen2_pop = ar_agen_sel[2] && ~rdataout_full ;
assign ar_agen3_pop = ar_agen_sel[3] && ~rdataout_full ;
wire rd_reg_valid = ar_agen0_pop || ar_agen1_pop || ar_agen2_pop || ar_agen3_pop;
wire rddec6_valid = rd_reg_valid && rd_reg_decode[6] &&
(rd_reg_data[39:38] == 2'b00) && (ar_agen_addr[13] == 1'b0);
reg [56+C_S_AXI_DATA_WIDTH/8-1:0] rd_reg_data_ff;
reg addrram_sel;
always @(posedge Clk) begin
rd_reg_data_ff <= (rst_l) ? rd_reg_data : 'h0;
addrram_sel <= (rst_l) ? ar_agen_addr[13] : 'h0;
rd_reg_valid_ff <= (rst_l) ? rd_reg_valid : 1'b0;
rddec6_valid_ff <= (rst_l) ? rddec6_valid : 1'b0;
slv_ex_info0_ff[71:0] <= (rst_l) ? slv_ex_info0[71:0] : 72'h0;
slv_ex_info1_ff[71:0] <= (rst_l) ? slv_ex_info1[71:0] : 72'h0;
slv_ex_toggle_ff <= (rst_l) ? slv_ex_toggle : 1'b0;
end
wire [31:0] cmdram_rd_out =
((rd_reg_data_ff[37:36] == 2'b00) ? cmd_out_mr_i[31:0] : 32'h0) |
((rd_reg_data_ff[37:36] == 2'b01) ? cmd_out_mr_i[63:32] : 32'h0) |
((rd_reg_data_ff[37:36] == 2'b10) ? cmd_out_mr_i[95:64] : 32'h0) |
((rd_reg_data_ff[37:36] == 2'b11) ? cmd_out_mr_i[127:96] : 32'h0);
wire [C_S_AXI_DATA_WIDTH-1:0] rd_data_muxed ;
assign rd_data_muxed =
(rd_reg_data_ff[39] && ~addrram_sel) ? slvram_rd_out[C_S_AXI_DATA_WIDTH-1:0] :
(rd_reg_data_ff[38] && ~addrram_sel) ? { 2 { cmdram_rd_out[31:0] } } :
(addrram_sel) ? { 2 { addrram_rd_out[31:0] } } :
{ 2 { rd_reg_data_ff[31:0] } };
wire [C_S_AXI_DATA_WIDTH/8-1:0] rd_data_be = rd_reg_data_ff[56+C_S_AXI_DATA_WIDTH/8-1:
56];
wire [C_S_AXI_DATA_WIDTH-1:0] rd_data_mask ;
generate if(C_S_AXI_DATA_WIDTH == 32) begin : S_R_BE_32
assign rd_data_mask = {
{ 8 { rd_data_be[3] } }, { 8 { rd_data_be[2] } },
{ 8 { rd_data_be[1] } }, { 8 { rd_data_be[0] } }
};
end
endgenerate
generate if(C_S_AXI_DATA_WIDTH == 64) begin : S_R_BE_64
assign rd_data_mask = {
{ 8 { rd_data_be[7] } }, { 8 { rd_data_be[6] } },
{ 8 { rd_data_be[5] } }, { 8 { rd_data_be[4] } },
{ 8 { rd_data_be[3] } }, { 8 { rd_data_be[2] } },
{ 8 { rd_data_be[1] } }, { 8 { rd_data_be[0] } }
};
end
endgenerate
wire [C_S_AXI_DATA_WIDTH-1:0] rd_data_masked =
rd_data_muxed[C_S_AXI_DATA_WIDTH-1:0] ;
//
//Timing improvement
//
reg [C_S_AXI_DATA_WIDTH+24-1:0] Rdataout_in_data_ff;
reg Rdataout_in_push_ff;
always @ (posedge Clk) begin
Rdataout_in_data_ff <= (rst_l) ? ({ rd_reg_data_ff[55:32], rd_data_masked[C_S_AXI_DATA_WIDTH-1:0] }) : {(C_S_AXI_DATA_WIDTH+24){1'b0}};
Rdataout_in_push_ff <= (rst_l) ? rd_reg_valid_ff : 1'b0;
end
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (C_S_AXI_DATA_WIDTH+24 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.ZERO_INVALID(C_ZERO_INVALID ),
.HEADREG (1 ),
.FULL_LEVEL (6 )
) Rdataout (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (Rdataout_in_data_ff ),
.in_push (Rdataout_in_push_ff ),
.in_pop ((rvalid_s && rready_s )),
.out_data (rdata_pre[C_S_AXI_DATA_WIDTH+24-1:0] ),
.is_full (rdataout_full ),
.is_notfull ( ),
.is_empty ( ),
.out_valid (rvalid_s ),
.ex_fifo_dbgout ( )
);
assign rdata_s[C_S_AXI_DATA_WIDTH-1:0] = rdata_pre[C_S_AXI_DATA_WIDTH-1:0];
assign rresp_s[1:0] = rdata_pre[C_S_AXI_DATA_WIDTH+2-1:C_S_AXI_DATA_WIDTH];
assign rlast_s = rdata_pre[C_S_AXI_DATA_WIDTH+2];
assign rid_s[C_S_AXI_ID_WIDTH-1:0] =
rdata_pre[C_S_AXI_DATA_WIDTH+23:C_S_AXI_DATA_WIDTH+8];
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_112x256_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_112x256_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [111:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [111:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [111:0] sub_wire3;
wire sub_wire4;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [111:0] q = sub_wire3[111:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 192,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 112,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "112"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "112"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "192"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "112"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 112 0 INPUT NODEFVAL "data[111..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 112 0 OUTPUT NODEFVAL "q[111..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 112 0 data 0 0 112 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 112 0 @q 0 0 112 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP cache
*/
module arp_cache #(
parameter CACHE_ADDR_WIDTH = 9
)
(
input wire clk,
input wire rst,
/*
* Cache query
*/
input wire query_request_valid,
output wire query_request_ready,
input wire [31:0] query_request_ip,
output wire query_response_valid,
input wire query_response_ready,
output wire query_response_error,
output wire [47:0] query_response_mac,
/*
* Cache write
*/
input wire write_request_valid,
output wire write_request_ready,
input wire [31:0] write_request_ip,
input wire [47:0] write_request_mac,
/*
* Configuration
*/
input wire clear_cache
);
reg mem_write = 0;
reg store_query = 0;
reg store_write = 0;
reg query_ip_valid_reg = 0, query_ip_valid_next;
reg [31:0] query_ip_reg = 0;
reg write_ip_valid_reg = 0, write_ip_valid_next;
reg [31:0] write_ip_reg = 0;
reg [47:0] write_mac_reg = 0;
reg clear_cache_reg = 0, clear_cache_next;
reg [CACHE_ADDR_WIDTH-1:0] wr_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, wr_ptr_next;
reg [CACHE_ADDR_WIDTH-1:0] rd_ptr_reg = {CACHE_ADDR_WIDTH{1'b0}}, rd_ptr_next;
reg valid_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg query_request_ready_reg = 0, query_request_ready_next;
reg query_response_valid_reg = 0, query_response_valid_next;
reg query_response_error_reg = 0, query_response_error_next;
reg [47:0] query_response_mac_reg = 0;
reg write_request_ready_reg = 0, write_request_ready_next;
wire [31:0] query_request_hash;
wire [31:0] write_request_hash;
assign query_request_ready = query_request_ready_reg;
assign query_response_valid = query_response_valid_reg;
assign query_response_error = query_response_error_reg;
assign query_response_mac = query_response_mac_reg;
assign write_request_ready = write_request_ready_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
rd_hash (
.data_in(query_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(query_request_hash)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
wr_hash (
.data_in(write_request_ip),
.state_in(32'hffffffff),
.data_out(),
.state_out(write_request_hash)
);
integer i;
initial begin
for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
valid_mem[i] = 1'b0;
ip_addr_mem[i] = 32'd0;
mac_addr_mem[i] = 48'd0;
end
end
always @* begin
mem_write = 1'b0;
store_query = 1'b0;
store_write = 1'b0;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
clear_cache_next = clear_cache_reg | clear_cache;
query_ip_valid_next = query_ip_valid_reg;
query_request_ready_next = (~query_ip_valid_reg || ~query_request_valid || query_response_ready) && !clear_cache_next;
query_response_valid_next = query_response_valid_reg & ~query_response_ready;
query_response_error_next = query_response_error_reg;
if (query_ip_valid_reg && (~query_request_valid || query_response_ready)) begin
query_response_valid_next = 1;
query_ip_valid_next = 0;
if (valid_mem[rd_ptr_reg] && ip_addr_mem[rd_ptr_reg] == query_ip_reg) begin
query_response_error_next = 0;
end else begin
query_response_error_next = 1;
end
end
if (query_request_valid && query_request_ready && (~query_ip_valid_reg || ~query_request_valid || query_response_ready)) begin
store_query = 1;
query_ip_valid_next = 1;
rd_ptr_next = query_request_hash[CACHE_ADDR_WIDTH-1:0];
end
write_ip_valid_next = write_ip_valid_reg;
write_request_ready_next = !clear_cache_next;
if (write_ip_valid_reg) begin
write_ip_valid_next = 0;
mem_write = 1;
end
if (write_request_valid && write_request_ready) begin
store_write = 1;
write_ip_valid_next = 1;
wr_ptr_next = write_request_hash[CACHE_ADDR_WIDTH-1:0];
end
if (clear_cache) begin
clear_cache_next = 1'b1;
wr_ptr_next = 0;
end else if (clear_cache_reg) begin
wr_ptr_next = wr_ptr_reg + 1;
clear_cache_next = wr_ptr_next != 0;
mem_write = 1;
end
end
always @(posedge clk) begin
if (rst) begin
query_ip_valid_reg <= 1'b0;
query_request_ready_reg <= 1'b0;
query_response_valid_reg <= 1'b0;
write_ip_valid_reg <= 1'b0;
write_request_ready_reg <= 1'b0;
clear_cache_reg <= 1'b1;
wr_ptr_reg <= 0;
end else begin
query_ip_valid_reg <= query_ip_valid_next;
query_request_ready_reg <= query_request_ready_next;
query_response_valid_reg <= query_response_valid_next;
write_ip_valid_reg <= write_ip_valid_next;
write_request_ready_reg <= write_request_ready_next;
clear_cache_reg <= clear_cache_next;
wr_ptr_reg <= wr_ptr_next;
end
query_response_error_reg <= query_response_error_next;
if (store_query) begin
query_ip_reg <= query_request_ip;
end
if (store_write) begin
write_ip_reg <= write_request_ip;
write_mac_reg <= write_request_mac;
end
rd_ptr_reg <= rd_ptr_next;
query_response_mac_reg <= mac_addr_mem[rd_ptr_reg];
if (mem_write) begin
valid_mem[wr_ptr_reg] <= !clear_cache_reg;
ip_addr_mem[wr_ptr_reg] <= write_ip_reg;
mac_addr_mem[wr_ptr_reg] <= write_mac_reg;
end
end
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_1_V
`define SKY130_FD_SC_HS__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_1_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`include "sd_host_defines.v"
`include "sd_host_stack_defines.v"
module sd_cmd_layer (
input clk,
input rst,
output o_sd_ready,
input i_crc_enable_flag,
input i_card_detect,
input [15:0] i_timeout,
input [31:0] i_block_sleep_count,
output reg o_error_flag,
output reg [7:0] o_error,
//User Command/Response Interface
input i_cmd_en,
output reg o_cmd_finished_en,
input [5:0] i_cmd,
input [31:0] i_cmd_arg,
//Flags
input i_rsp_long,
output [127:0] o_rsp,
//User control side
input i_data_txrx,
input i_data_write_flag,
input [23:0] i_data_size,
output reg o_data_txrx_finished,
input i_data_write_stb,
input i_data_read_stb,
input [2:0] i_func_addr,
input i_data_block_mode,
input [23:0] i_f0_block_size,
input [23:0] i_f1_block_size,
input [23:0] i_f2_block_size,
input [23:0] i_f3_block_size,
input [23:0] i_f4_block_size,
input [23:0] i_f5_block_size,
input [23:0] i_f6_block_size,
input [23:0] i_f7_block_size,
input [23:0] i_mem_block_size,
//Interrupt From the Card
output o_interrupt,
//PHY Layer
output reg o_phy_cmd_en ,
output reg [39:0] o_phy_cmd,
output [7:0] o_phy_cmd_len,
input i_phy_rsp_finished_en,
input [135:0] i_phy_rsp,
output [7:0] o_phy_rsp_len,
input i_phy_crc_bad,
output reg o_data_txrx_activate,
input i_data_txrx_finished,
output [11:0] o_data_byte_count,
output o_data_write_flag,
input i_data_crc_read_err
);
//local parameters
localparam IDLE = 4'h0;
localparam TXRX_BLOCK = 4'h1;
localparam WAIT_RESPONSE = 4'h2;
localparam BLOCK_SLEEP = 4'h3;
localparam FINISHED = 4'h4;
//registes/wires
reg [3:0] state;
reg [3:0] data_state;
reg [23:0] count;
reg infinite_data_txrx;
reg [23:0] transfer_count;
reg [23:0] block_count;
wire [23:0] func_block_size [0:7];
//submodules
//asynchronous logic
assign o_phy_cmd_len = 8'd40;
assign o_rsp = i_phy_rsp[127:0];
//assign o_data_byte_count = i_data_size[11:0];
assign o_data_byte_count = transfer_count[11:0];
assign o_data_write_flag = i_data_write_flag;
assign func_block_size[0] = i_f0_block_size;
assign func_block_size[1] = i_f1_block_size;
assign func_block_size[2] = i_f2_block_size;
assign func_block_size[3] = i_f3_block_size;
assign func_block_size[4] = i_f4_block_size;
assign func_block_size[5] = i_f5_block_size;
assign func_block_size[6] = i_f6_block_size;
assign func_block_size[7] = i_f7_block_size;
assign o_phy_rsp_len = i_rsp_long ? 8'd136 : 8'd40;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_phy_cmd_en <= 0;
if (rst) begin
state <= IDLE;
o_phy_cmd <= 0;
o_error <= `ERROR_NO_ERROR;
o_cmd_finished_en <= 0;
end
else begin
case (state)
IDLE: begin
o_phy_cmd_en <= 0;
o_cmd_finished_en <= 0;
o_error <= `ERROR_NO_ERROR;
if (i_cmd_en) begin
o_phy_cmd[39:38] <= 2'b01;
o_phy_cmd[37:32] <= i_cmd;
o_phy_cmd[31:0] <= i_cmd_arg;
o_phy_cmd_en <= 1;
state <= WAIT_RESPONSE;
end
end
WAIT_RESPONSE: begin
o_phy_cmd_en <= 1;
if (i_phy_rsp_finished_en) begin
if (i_crc_enable_flag && i_phy_crc_bad) begin
o_error <= `ERROR_CRC_FAIL;
end
o_phy_cmd_en <= 0;
state <= FINISHED;
end
end
FINISHED: begin
o_cmd_finished_en <= 1;
end
default: begin
end
endcase
//Whenever the host de-asserts command enable go back to IDLE, this way we
//Won't get stuck if something goes buggered
if (!i_cmd_en) begin
state <= IDLE;
end
end
end
always @ (posedge clk) begin
if (rst) begin
o_data_txrx_finished <= 0;
o_data_txrx_activate <= 0;
data_state <= IDLE;
count <= 0;
transfer_count <= 0;
infinite_data_txrx <= 0;
block_count <= 0;
end
else begin
case (data_state)
IDLE: begin
infinite_data_txrx <= 0;
o_data_txrx_finished <= 0;
o_data_txrx_activate <= 0;
count <= 0;
block_count <= 0;
if (i_data_txrx) begin
data_state <= TXRX_BLOCK;
if (i_data_block_mode) begin
if (i_data_size == 0) begin
infinite_data_txrx <= 1;
end
transfer_count <= func_block_size[i_func_addr];
end
else begin
transfer_count <= i_data_size;
end
end
end
TXRX_BLOCK: begin
count <= 0;
o_data_txrx_activate <= 1;
data_state <= WAIT_RESPONSE;
block_count <= block_count + 1;
end
WAIT_RESPONSE: begin
//if (i_data_write_stb || i_data_read_stb) begin
// count <= count + 1;
//end
if (i_data_txrx_finished) begin
o_data_txrx_activate <= 0;
if (i_data_block_mode) begin
if (infinite_data_txrx || (block_count < i_data_size)) begin
data_state <= BLOCK_SLEEP;
end
else begin
count <= 0;
data_state <= FINISHED;
end
end
else begin
data_state <= FINISHED;
end
end
end
BLOCK_SLEEP: begin
if (count < i_block_sleep_count) begin
count <= count + 1;
end
else begin
data_state <= TXRX_BLOCK;
end
end
FINISHED: begin
o_data_txrx_finished <= 1;
end
default: begin
end
endcase
if (!i_data_txrx) begin
data_state <= IDLE;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Add_Subtract_Function #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) FPADDSUB (
.clk (clk),
.rst (rst),
.beg_FSM (beg_FSM),
.ack_FSM (ack_FSM),
.Data_X (Data_X),
.Data_Y (Data_Y),
.add_subt (add_subt),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
//Abre el archivo testbench
// FileSaveData = $fopen("vector/add_single/ResultadoXilinxFLM.txt","w");
// $readmemh("vector/add_single/Hexadecimal_A.txt", Array_IN_1);
// $readmemh("vector/add_single/Hexadecimal_B.txt", Array_IN_2);
add_subt = 0;
FileSaveData = $fopen("ResultadoXilinxFLM_SUMA.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
add_subt = 1;
FileSaveData = $fopen("ResultadoXilinxFLM_RESTA.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
beg_FSM = 0;
ack_FSM = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_X = Array_IN_1[contador];
Data_Y = Array_IN_2[contador];
#(PERIOD/4) beg_FSM = 1;
//Wait for the operation ready
@(posedge ready) begin
#(PERIOD+2);
ack_FSM = 1;
#4;
$fwrite(FDataO,"%h\n",final_result_ieee);
end
@(negedge clk) begin
ack_FSM = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
//# 17 inputs
//# 5 outputs
//# 74 D-type flipflops
//# 167 inverters
//# 490 gates (197 ANDs + 64 NANDs + 137 ORs + 92 NORs)
module s1423(GND,VDD,CK,G0,G1,G10,G11,G12,G13,G14,G15,G16,G2,G3,G4,G5,G6,G7,
G701BF,G702,G726,G727,G729,G8,G9);
input GND,VDD,CK,G0,G1,G2,G3,G4,G5,G6,G7,G8,G9,G10,G11,G12,G13,G14,G15,G16;
output G726,G729,G702,G727,G701BF;
wire G22,G332BF,G23,G328BF,G24,G109,G25,G113,G26,G118,G27,G125,G28,G129,G29,
G140,G30,G144,G31,G149,G32,G154,G33,G159,G34,G166,G35,G175,G36,G189,G37,
G193,G38,G198,G39,G208,G40,G214,G41,G218,G42,G237,G43,G242,G44,G247,G45,
G252,G46,G260,G47,G303,G48,G309,G49,G315,G50,G321,G51,G360,G52,G365,G53,
G373,G54,G379,G55,G384,G56,G392,G57,G397,G58,G405,G59,G408,G60,G416,G61,
G424,G62,G427,G63,G438,G64,G441,G65,G447,G66,G451,G67,G459,G68,G464,G69,
G469,G70,G477,G71,G494,G72,G498,G73,G503,G74,G526,G75,G531,G76,G536,G77,
G541,G78,G548,G79,G565,G80,G569,G81,G573,G82,G577,G83,G590,G84,G608,G85,
G613,G86,G657,G87,G663,G88,G669,G89,G675,G90,G682,G91,G687,G92,G693,G93,
G705,G94,G707,G95,G713,II1,G332,II12,G328,G108,G712,G111,G112,G117,G124,
G127,G128,G139,G142,G143,G148,G153,G158,G165,G174,G176,G178,G179,G180,G188,
G191,G192,G197,G204,G207,G210,G213,G216,G217,G236,G259,G241,G246,G251,G258,
G296,G297,G302,G305,G324,G308,G311,G314,G317,G320,G323,G336,G355,G339,G343,
G348,G347,G351,G645,G354,G359,G372,G364,G371,G378,G391,G383,G390,G396,G404,
G403,G407,G415,G423,G422,G426,G437,G440,G445,G446,G449,G450,G455,G456,G458,
G476,G463,G468,G475,G486,G491,G500,G495,G499,G504,G511,G507,G510,G525,G589,
G530,G535,G540,G547,G562,G610,G566,G570,G574,G588,G595,G593,G596,G597,G600,
G601,G605,G609,G614,G615,G616,G617,G620,G623,G626,G629,G632,G635,G638,G641,
G644,G656,G658,G659,II1162,G661,G662,G665,G678,G668,G671,G674,G677,II1183,
G685,G696,G689,G695,II1203,G701,II1211,G704,G706,G711,G714,II1227,G715,
II1230,G716,II1233,G717,II1236,G718,II1239,G719,II1242,G720,II1245,G721,
II1248,G722,II1251,G723,II1254,G724,II1257,G725,II1260,II1264,G728,II1267,
G101,G630,G631,G102,G633,G634,G103,G636,G637,G104,G639,G640,G105,G642,G643,
G106,G114,G116,G133,G119,G121,G134,G122,G130,G132,G136,G700,G135,G137,G145,
G147,G168,G150,G152,G169,G155,G157,G170,G160,G162,G171,G163,G177,G172,G173,
G185,G181,G182,G186,G194,G196,G202,G199,G201,G203,G522,G205,G211,G219,G221,
G223,G222,G183,G224,G225,G226,G227,G228,G229,G432,G238,G240,G299,G243,G245,
G262,G248,G250,G263,G253,G255,G264,G624,G625,G256,G261,G265,G271,G275,G266,
G272,G276,G277,G273,G278,G279,G274,G280,G281,G304,G306,G307,G310,G312,G313,
G316,G318,G319,G322,G325,G326,G329,G331,G330,G335,G337,G338,G342,G344,G345,
G346,G349,G350,G358,G523,G361,G363,G366,G368,G375,G369,G374,G376,G377,G380,
G382,G385,G387,G394,G388,G393,G395,G398,G400,G401,G406,G412,G409,G411,G413,
G414,G417,G419,G420,G425,G431,G428,G430,G433,G356,G357,G435,G340,G341,G436,
G352,G353,G439,G442,G443,G448,G452,G453,G457,G460,G462,G434,G465,G467,G479,
G470,G472,G480,G473,G478,G481,G488,G505,G506,G489,G508,G509,G490,G512,G513,
G492,G493,G496,G497,G501,G502,G527,G529,G604,G532,G534,G550,G537,G539,G551,
G542,G544,G552,G545,G549,G553,G563,G564,G567,G568,G571,G572,G575,G576,G627,
G628,G591,G592,G594,G621,G622,G524,G606,G607,G611,G612,G648,G646,G647,G649,
G618,G619,G650,G651,G652,G653,G654,G655,G664,G666,G667,G670,G672,G673,G676,
G679,G680,G683,G684,G688,G690,G691,G694,G697,G698,G703,G230,G708,G709,G599,
G110,G126,G141,G167,G184,G190,G209,G215,G235,G233,G267,G268,G269,G282,G283,
G270,G291,G292,G293,G294,G295,G300,G333,G334,G301,G518,G519,G520,G521,G487,
G554,G555,G583,G584,G585,G586,G587,G561,G602,G603,G96,G97,G98,G99,G100,
G681,G699,G686,G692,G107,G123,G138,G164,G187,G206,G212,G234,G231,G232,G298,
G286,G287,G288,G284,G285,G289,G290,G482,G514,G483,G515,G484,G516,G485,G517,
G556,G557,G558,G559,G560,G578,G579,G580,G581,G582,G598,G115,G120,G131,G146,
G151,G156,G161,G195,G200,G220,G239,G244,G249,G254,G257,G327,G362,G367,G370,
G381,G386,G389,G399,G402,G410,G418,G421,G429,G444,G454,G461,G466,G471,G474,
G528,G533,G538,G543,G546,G660,G710;
dff DFF_0(CK,G22,G332BF);
dff DFF_1(CK,G23,G328BF);
dff DFF_2(CK,G24,G109);
dff DFF_3(CK,G25,G113);
dff DFF_4(CK,G26,G118);
dff DFF_5(CK,G27,G125);
dff DFF_6(CK,G28,G129);
dff DFF_7(CK,G29,G140);
dff DFF_8(CK,G30,G144);
dff DFF_9(CK,G31,G149);
dff DFF_10(CK,G32,G154);
dff DFF_11(CK,G33,G159);
dff DFF_12(CK,G34,G166);
dff DFF_13(CK,G35,G175);
dff DFF_14(CK,G36,G189);
dff DFF_15(CK,G37,G193);
dff DFF_16(CK,G38,G198);
dff DFF_17(CK,G39,G208);
dff DFF_18(CK,G40,G214);
dff DFF_19(CK,G41,G218);
dff DFF_20(CK,G42,G237);
dff DFF_21(CK,G43,G242);
dff DFF_22(CK,G44,G247);
dff DFF_23(CK,G45,G252);
dff DFF_24(CK,G46,G260);
dff DFF_25(CK,G47,G303);
dff DFF_26(CK,G48,G309);
dff DFF_27(CK,G49,G315);
dff DFF_28(CK,G50,G321);
dff DFF_29(CK,G51,G360);
dff DFF_30(CK,G52,G365);
dff DFF_31(CK,G53,G373);
dff DFF_32(CK,G54,G379);
dff DFF_33(CK,G55,G384);
dff DFF_34(CK,G56,G392);
dff DFF_35(CK,G57,G397);
dff DFF_36(CK,G58,G405);
dff DFF_37(CK,G59,G408);
dff DFF_38(CK,G60,G416);
dff DFF_39(CK,G61,G424);
dff DFF_40(CK,G62,G427);
dff DFF_41(CK,G63,G438);
dff DFF_42(CK,G64,G441);
dff DFF_43(CK,G65,G447);
dff DFF_44(CK,G66,G451);
dff DFF_45(CK,G67,G459);
dff DFF_46(CK,G68,G464);
dff DFF_47(CK,G69,G469);
dff DFF_48(CK,G70,G477);
dff DFF_49(CK,G71,G494);
dff DFF_50(CK,G72,G498);
dff DFF_51(CK,G73,G503);
dff DFF_52(CK,G74,G526);
dff DFF_53(CK,G75,G531);
dff DFF_54(CK,G76,G536);
dff DFF_55(CK,G77,G541);
dff DFF_56(CK,G78,G548);
dff DFF_57(CK,G79,G565);
dff DFF_58(CK,G80,G569);
dff DFF_59(CK,G81,G573);
dff DFF_60(CK,G82,G577);
dff DFF_61(CK,G83,G590);
dff DFF_62(CK,G84,G608);
dff DFF_63(CK,G85,G613);
dff DFF_64(CK,G86,G657);
dff DFF_65(CK,G87,G663);
dff DFF_66(CK,G88,G669);
dff DFF_67(CK,G89,G675);
dff DFF_68(CK,G90,G682);
dff DFF_69(CK,G91,G687);
dff DFF_70(CK,G92,G693);
dff DFF_71(CK,G93,G705);
dff DFF_72(CK,G94,G707);
dff DFF_73(CK,G95,G713);
not NOT_0(II1,G332);
not NOT_1(G332BF,II1);
not NOT_2(II12,G328);
not NOT_3(G328BF,II12);
not NOT_4(G108,G712);
not NOT_5(G111,G24);
not NOT_6(G112,G712);
not NOT_7(G117,G712);
not NOT_8(G124,G712);
not NOT_9(G127,G27);
not NOT_10(G128,G712);
not NOT_11(G139,G712);
not NOT_12(G142,G29);
not NOT_13(G143,G712);
not NOT_14(G148,G712);
not NOT_15(G153,G712);
not NOT_16(G158,G712);
not NOT_17(G165,G712);
not NOT_18(G174,G712);
not NOT_19(G176,G35);
not NOT_20(G178,G34);
not NOT_21(G179,G180);
not NOT_22(G180,G92);
not NOT_23(G188,G712);
not NOT_24(G191,G36);
not NOT_25(G192,G712);
not NOT_26(G197,G712);
not NOT_27(G204,G38);
not NOT_28(G207,G712);
not NOT_29(G210,G39);
not NOT_30(G213,G712);
not NOT_31(G216,G40);
not NOT_32(G217,G712);
not NOT_33(G236,G259);
not NOT_34(G241,G259);
not NOT_35(G246,G259);
not NOT_36(G251,G259);
not NOT_37(G258,G259);
not NOT_38(G296,G297);
not NOT_39(G302,G712);
not NOT_40(G305,G324);
not NOT_41(G308,G712);
not NOT_42(G311,G324);
not NOT_43(G314,G712);
not NOT_44(G317,G324);
not NOT_45(G320,G712);
not NOT_46(G323,G324);
not NOT_47(G336,G355);
not NOT_48(G339,G355);
not NOT_49(G343,G348);
not NOT_50(G347,G348);
not NOT_51(G348,G91);
not NOT_52(G351,G645);
not NOT_53(G354,G355);
not NOT_54(G359,G372);
not NOT_55(G364,G372);
not NOT_56(G371,G372);
not NOT_57(G378,G391);
not NOT_58(G383,G391);
not NOT_59(G390,G391);
not NOT_60(G396,G404);
not NOT_61(G403,G404);
not NOT_62(G407,G712);
not NOT_63(G415,G423);
not NOT_64(G422,G423);
not NOT_65(G426,G712);
not NOT_66(G437,G712);
not NOT_67(G440,G712);
not NOT_68(G445,G65);
not NOT_69(G446,G712);
not NOT_70(G449,G66);
not NOT_71(G450,G712);
not NOT_72(G455,G456);
not NOT_73(G458,G476);
not NOT_74(G463,G476);
not NOT_75(G468,G476);
not NOT_76(G475,G476);
not NOT_77(G486,G712);
not NOT_78(G491,G500);
not NOT_79(G495,G500);
not NOT_80(G499,G500);
not NOT_81(G504,G511);
not NOT_82(G507,G511);
not NOT_83(G510,G511);
not NOT_84(G511,G63);
not NOT_85(G525,G589);
not NOT_86(G530,G589);
not NOT_87(G535,G589);
not NOT_88(G540,G589);
not NOT_89(G547,G589);
not NOT_90(G562,G610);
not NOT_91(G566,G610);
not NOT_92(G570,G610);
not NOT_93(G574,G610);
not NOT_94(G588,G589);
not NOT_95(G595,G593);
not NOT_96(G596,G597);
not NOT_97(G600,G601);
not NOT_98(G605,G610);
not NOT_99(G609,G610);
not NOT_100(G614,G64);
not NOT_101(G615,G616);
not NOT_102(G617,G645);
not NOT_103(G620,G645);
not NOT_104(G623,G645);
not NOT_105(G626,G645);
not NOT_106(G629,G645);
not NOT_107(G632,G645);
not NOT_108(G635,G645);
not NOT_109(G638,G645);
not NOT_110(G641,G645);
not NOT_111(G644,G645);
not NOT_112(G645,G90);
not NOT_113(G656,G712);
not NOT_114(G658,G659);
not NOT_115(II1162,G13);
not NOT_116(G659,II1162);
not NOT_117(G661,G94);
not NOT_118(G662,G712);
not NOT_119(G665,G678);
not NOT_120(G668,G712);
not NOT_121(G671,G678);
not NOT_122(G674,G712);
not NOT_123(G677,G678);
not NOT_124(II1183,G11);
not NOT_125(G678,II1183);
not NOT_126(G685,G696);
not NOT_127(G689,G696);
not NOT_128(G695,G696);
not NOT_129(II1203,G10);
not NOT_130(G696,II1203);
not NOT_131(G701,G15);
not NOT_132(II1211,G701);
not NOT_133(G701BF,II1211);
not NOT_134(G704,G712);
not NOT_135(G706,G712);
not NOT_136(G711,G712);
not NOT_137(G712,G14);
not NOT_138(G714,G701);
not NOT_139(II1227,G6);
not NOT_140(G715,II1227);
not NOT_141(II1230,G7);
not NOT_142(G716,II1230);
not NOT_143(II1233,G8);
not NOT_144(G717,II1233);
not NOT_145(II1236,G9);
not NOT_146(G718,II1236);
not NOT_147(II1239,G12);
not NOT_148(G719,II1239);
not NOT_149(II1242,G0);
not NOT_150(G720,II1242);
not NOT_151(II1245,G1);
not NOT_152(G721,II1245);
not NOT_153(II1248,G2);
not NOT_154(G722,II1248);
not NOT_155(II1251,G3);
not NOT_156(G723,II1251);
not NOT_157(II1254,G4);
not NOT_158(G724,II1254);
not NOT_159(II1257,G5);
not NOT_160(G725,II1257);
not NOT_161(II1260,G93);
not NOT_162(G726,II1260);
not NOT_163(II1264,G16);
not NOT_164(G728,II1264);
not NOT_165(II1267,G95);
not NOT_166(G729,II1267);
and AND2_0(G101,G630,G631);
and AND2_1(G102,G633,G634);
and AND2_2(G103,G636,G637);
and AND2_3(G104,G639,G640);
and AND2_4(G105,G642,G643);
and AND2_5(G109,G106,G108);
and AND2_6(G113,G114,G112);
and AND2_7(G116,G133,G25);
and AND2_8(G118,G119,G117);
and AND2_9(G121,G134,G26);
and AND2_10(G125,G122,G124);
and AND2_11(G129,G130,G128);
and AND2_12(G132,G136,G28);
and AND2_13(G133,G700,G111);
and AND2_14(G134,G133,G25);
and AND2_15(G135,G134,G26);
and AND2_16(G136,G135,G127);
and AND2_17(G140,G137,G139);
and AND2_18(G144,G145,G143);
and AND2_19(G147,G168,G30);
and AND2_20(G149,G150,G148);
and AND2_21(G152,G169,G31);
and AND2_22(G154,G155,G153);
and AND2_23(G157,G170,G32);
and AND2_24(G159,G160,G158);
and AND2_25(G162,G171,G33);
and AND2_26(G166,G163,G165);
and AND2_27(G168,G177,G142);
and AND2_28(G169,G168,G30);
and AND2_29(G170,G169,G31);
and AND2_30(G171,G170,G32);
and AND2_31(G172,G171,G33);
and AND2_32(G173,G172,G34);
and AND2_33(G175,G176,G174);
and AND2_34(G185,G181,G182);
and AND2_35(G189,G186,G188);
and AND2_36(G193,G194,G192);
and AND2_37(G196,G202,G37);
and AND2_38(G198,G199,G197);
and AND2_39(G201,G203,G38);
and AND2_40(G202,G522,G191);
and AND2_41(G203,G202,G37);
and AND2_42(G208,G205,G207);
and AND2_43(G214,G211,G213);
and AND2_44(G218,G219,G217);
and AND2_45(G221,G223,G41);
and AND2_46(G222,G183,G210);
and AND2_47(G223,G222,G216);
and AND2_48(G224,G203,G38);
and AND2_49(G225,G204,G203);
and AND2_50(G226,G136,G28);
and AND2_51(G227,G172,G178);
and AND2_52(G228,G223,G41);
and AND2_53(G229,G432,G62);
and AND2_54(G237,G238,G236);
and AND2_55(G240,G299,G42);
and AND2_56(G242,G243,G241);
and AND2_57(G245,G262,G43);
and AND2_58(G247,G248,G246);
and AND2_59(G250,G263,G44);
and AND2_60(G252,G253,G251);
and AND2_61(G255,G264,G45);
and AND2_62(G259,G624,G625);
and AND2_63(G260,G256,G258);
and AND2_64(G261,G265,G46);
and AND2_65(G262,G299,G42);
and AND2_66(G263,G262,G43);
and AND2_67(G264,G263,G44);
and AND2_68(G265,G264,G45);
and AND2_69(G271,G275,G266);
and AND2_70(G272,G276,G277);
and AND2_71(G273,G278,G279);
and AND2_72(G274,G280,G281);
and AND2_73(G303,G304,G302);
and AND2_74(G304,G306,G307);
and AND2_75(G309,G310,G308);
and AND2_76(G310,G312,G313);
and AND2_77(G315,G316,G314);
and AND2_78(G316,G318,G319);
and AND2_79(G321,G322,G320);
and AND2_80(G322,G325,G326);
and AND2_81(G329,G331,G714);
and AND2_82(G330,G332,G714);
and AND2_83(G335,G337,G338);
and AND2_84(G342,G344,G345);
and AND2_85(G346,G349,G350);
and AND2_86(G358,G523,G53);
and AND2_87(G360,G361,G359);
and AND2_88(G363,G523,G51);
and AND2_89(G365,G366,G364);
and AND2_90(G368,G375,G52);
and AND2_91(G373,G369,G371);
and AND2_92(G374,G376,G53);
and AND2_93(G375,G523,G51);
and AND2_94(G376,G375,G52);
and AND3_0(G377,G183,G54,G56);
and AND2_95(G379,G380,G378);
and AND2_96(G382,G183,G54);
and AND2_97(G384,G385,G383);
and AND2_98(G387,G394,G55);
and AND2_99(G392,G388,G390);
and AND2_100(G393,G395,G56);
and AND2_101(G394,G183,G54);
and AND2_102(G395,G394,G55);
and AND2_103(G397,G398,G396);
and AND2_104(G400,G335,G57);
and AND2_105(G405,G401,G403);
and AND2_106(G406,G412,G58);
and AND2_107(G408,G409,G407);
and AND2_108(G411,G413,G59);
and AND2_109(G412,G335,G57);
and AND2_110(G413,G335,G58);
and AND2_111(G414,G413,G59);
and AND2_112(G416,G417,G415);
and AND2_113(G419,G358,G60);
and AND2_114(G424,G420,G422);
and AND2_115(G425,G431,G61);
and AND2_116(G427,G428,G426);
and AND2_117(G430,G432,G62);
and AND2_118(G431,G358,G60);
and AND2_119(G432,G358,G61);
and AND2_120(G433,G356,G357);
and AND2_121(G435,G340,G341);
and AND2_122(G436,G352,G353);
and AND2_123(G438,G439,G437);
and AND2_124(G441,G442,G440);
and AND2_125(G443,G615,G511);
and AND2_126(G447,G448,G446);
and AND2_127(G451,G452,G450);
and AND2_128(G453,G615,G445);
and AND3_1(G457,G455,G449,G728);
and AND2_129(G459,G460,G458);
and AND2_130(G462,G434,G67);
and AND2_131(G464,G465,G463);
and AND2_132(G467,G479,G68);
and AND2_133(G469,G470,G468);
and AND2_134(G472,G480,G69);
and AND2_135(G477,G473,G475);
and AND2_136(G478,G481,G70);
and AND2_137(G479,G434,G67);
and AND2_138(G480,G479,G68);
and AND2_139(G481,G480,G69);
and AND2_140(G488,G505,G506);
and AND2_141(G489,G508,G509);
and AND2_142(G490,G512,G513);
and AND2_143(G494,G492,G493);
and AND2_144(G498,G496,G497);
and AND2_145(G503,G501,G502);
and AND2_146(G526,G527,G525);
and AND2_147(G529,G604,G74);
and AND2_148(G531,G532,G530);
and AND2_149(G534,G550,G75);
and AND2_150(G536,G537,G535);
and AND2_151(G539,G551,G76);
and AND2_152(G541,G542,G540);
and AND2_153(G544,G552,G77);
and AND2_154(G548,G545,G547);
and AND2_155(G549,G553,G78);
and AND2_156(G550,G604,G74);
and AND2_157(G551,G550,G75);
and AND2_158(G552,G551,G76);
and AND2_159(G553,G552,G77);
and AND2_160(G565,G563,G564);
and AND2_161(G569,G567,G568);
and AND2_162(G573,G571,G572);
and AND2_163(G577,G575,G576);
and AND2_164(G589,G627,G628);
and AND2_165(G590,G591,G588);
and AND2_166(G592,G594,G595);
and AND2_167(G601,G621,G622);
and AND2_168(G604,G433,G524);
and AND2_169(G608,G606,G607);
and AND2_170(G613,G611,G612);
and AND2_171(G648,G646,G647);
and AND2_172(G649,G618,G619);
and AND2_173(G650,G226,G661);
and AND2_174(G651,G227,G87);
and AND2_175(G652,G228,G88);
and AND2_176(G653,G229,G89);
and AND2_177(G654,G90,G476);
and AND2_178(G655,G91,G476);
and AND2_179(G657,G659,G656);
and AND2_180(G663,G664,G662);
and AND2_181(G664,G666,G667);
and AND2_182(G669,G670,G668);
and AND2_183(G670,G672,G673);
and AND2_184(G675,G676,G674);
and AND2_185(G676,G679,G680);
and AND2_186(G683,G684,G685);
and AND2_187(G688,G690,G691);
and AND2_188(G694,G697,G698);
and AND2_189(G702,G703,G645);
and AND2_190(G705,G230,G704);
and AND2_191(G707,G708,G706);
and AND2_192(G709,G678,G89);
and AND2_193(G713,G599,G711);
and AND2_194(G727,G476,G645);
or OR2_0(G110,G700,G111);
or OR2_1(G126,G135,G127);
or OR2_2(G141,G177,G142);
or OR2_3(G167,G172,G178);
or OR2_4(G177,G180,G226);
or OR2_5(G181,G178,G180);
or OR2_6(G182,G35,G179);
or OR2_7(G183,G180,G227);
or OR2_8(G184,G180,G173);
or OR2_9(G190,G522,G191);
or OR2_10(G209,G183,G210);
or OR2_11(G215,G222,G216);
or OR2_12(G235,G649,G233);
or OR2_13(G275,G101,G42);
or OR2_14(G276,G102,G43);
or OR2_15(G277,G267,G271);
or OR2_16(G278,G103,G44);
or OR2_17(G279,G268,G272);
or OR2_18(G280,G104,G45);
or OR2_19(G281,G269,G273);
or OR2_20(G282,G105,G46);
or OR2_21(G283,G270,G274);
or OR2_22(G291,G42,G101);
or OR2_23(G292,G43,G102);
or OR2_24(G293,G44,G103);
or OR2_25(G294,G45,G104);
or OR2_26(G295,G46,G105);
or OR4_0(G300,G50,G49,G48,G47);
or OR2_27(G306,G47,G324);
or OR2_28(G307,G719,G305);
or OR2_29(G312,G48,G324);
or OR2_30(G313,G47,G311);
or OR2_31(G318,G49,G324);
or OR2_32(G319,G48,G317);
or OR2_33(G324,G377,G348);
or OR2_34(G325,G50,G324);
or OR2_35(G326,G49,G323);
or OR2_36(G333,G300,G714);
or OR2_37(G334,G301,G714);
or OR2_38(G337,G224,G355);
or OR2_39(G338,G183,G336);
or OR2_40(G340,G38,G355);
or OR2_41(G341,G185,G339);
or OR2_42(G344,G229,G348);
or OR2_43(G345,G414,G343);
or OR2_44(G349,G62,G348);
or OR2_45(G350,G59,G347);
or OR2_46(G352,G346,G645);
or OR2_47(G353,G35,G351);
or OR2_48(G355,G457,G645);
or OR2_49(G356,G225,G355);
or OR2_50(G357,G184,G354);
or OR2_51(G372,G712,G358);
or OR2_52(G391,G712,G377);
or OR2_53(G404,G712,G413);
or OR2_54(G423,G712,G432);
or OR2_55(G434,G342,G645);
or OR2_56(G439,G435,G63);
or OR2_57(G448,G615,G65);
or OR2_58(G456,G83,G524);
or OR2_59(G492,G71,G500);
or OR2_60(G493,G488,G491);
or OR2_61(G496,G72,G500);
or OR2_62(G497,G489,G495);
or OR2_63(G500,G654,G712);
or OR2_64(G501,G73,G500);
or OR2_65(G502,G490,G499);
or OR2_66(G505,G723,G511);
or OR2_67(G506,G720,G504);
or OR2_68(G508,G724,G511);
or OR2_69(G509,G721,G507);
or OR2_70(G512,G725,G511);
or OR2_71(G513,G722,G510);
or OR2_72(G518,G71,G67);
or OR2_73(G519,G72,G68);
or OR2_74(G520,G73,G69);
or OR2_75(G521,G487,G70);
or OR2_76(G522,G348,G228);
or OR2_77(G523,G348,G414);
or OR2_78(G524,G554,G555);
or OR2_79(G563,G79,G610);
or OR2_80(G564,G715,G562);
or OR2_81(G567,G80,G610);
or OR2_82(G568,G716,G566);
or OR2_83(G571,G81,G610);
or OR2_84(G572,G717,G570);
or OR2_85(G575,G82,G610);
or OR2_86(G576,G718,G574);
or OR2_87(G583,G79,G74);
or OR2_88(G584,G80,G75);
or OR2_89(G585,G81,G76);
or OR2_90(G586,G82,G77);
or OR2_91(G587,G561,G78);
or OR2_92(G591,G592,G604);
or OR2_93(G594,G83,G593);
or OR2_94(G602,G85,G601);
or OR2_95(G603,G600,G84);
or OR2_96(G606,G84,G610);
or OR2_97(G607,G696,G605);
or OR2_98(G610,G655,G712);
or OR2_99(G611,G85,G610);
or OR2_100(G612,G678,G609);
or OR2_101(G618,G457,G645);
or OR2_102(G619,G715,G617);
or OR2_103(G621,G614,G645);
or OR2_104(G622,G717,G620);
or OR2_105(G624,G476,G645);
or OR2_106(G625,G716,G623);
or OR2_107(G627,G476,G645);
or OR2_108(G628,G718,G626);
or OR2_109(G630,G96,G645);
or OR2_110(G631,G720,G629);
or OR2_111(G633,G97,G645);
or OR2_112(G634,G721,G632);
or OR2_113(G636,G98,G645);
or OR2_114(G637,G722,G635);
or OR2_115(G639,G99,G645);
or OR2_116(G640,G723,G638);
or OR2_117(G642,G100,G645);
or OR2_118(G643,G724,G641);
or OR2_119(G646,G456,G645);
or OR2_120(G647,G725,G644);
or OR2_121(G666,G87,G678);
or OR2_122(G667,G661,G665);
or OR2_123(G672,G88,G678);
or OR2_124(G673,G87,G671);
or OR2_125(G679,G89,G678);
or OR2_126(G680,G88,G677);
or OR2_127(G682,G681,G699);
or OR2_128(G684,G645,G696);
or OR2_129(G687,G686,G699);
or OR2_130(G690,G348,G696);
or OR2_131(G691,G645,G689);
or OR2_132(G693,G692,G699);
or OR2_133(G697,G180,G696);
or OR2_134(G698,G348,G695);
or OR2_135(G699,G658,G712);
nand NAND2_0(G96,G74,G596);
nand NAND2_1(G97,G75,G596);
nand NAND2_2(G98,G76,G596);
nand NAND2_3(G99,G77,G596);
nand NAND2_4(G100,G78,G596);
nand NAND2_5(G106,G107,G110);
nand NAND2_6(G107,G700,G111);
nand NAND2_7(G122,G123,G126);
nand NAND2_8(G123,G135,G127);
nand NAND2_9(G137,G138,G141);
nand NAND2_10(G138,G177,G142);
nand NAND2_11(G163,G164,G167);
nand NAND2_12(G164,G172,G178);
nand NAND2_13(G186,G187,G190);
nand NAND2_14(G187,G522,G191);
nand NAND2_15(G205,G206,G209);
nand NAND2_16(G206,G183,G210);
nand NAND2_17(G211,G212,G215);
nand NAND2_18(G212,G222,G216);
nand NAND2_19(G230,G234,G235);
nand NAND2_20(G231,G435,G648);
nand NAND3_0(G232,G296,G298,G435);
nand NAND3_1(G233,G700,G232,G231);
nand NAND2_21(G234,G649,G436);
nand NAND2_22(G266,G286,G291);
nand NAND2_23(G267,G287,G292);
nand NAND2_24(G268,G288,G293);
nand NAND2_25(G269,G284,G294);
nand NAND2_26(G270,G285,G295);
nand NAND2_27(G284,G45,G104);
nand NAND2_28(G285,G46,G105);
nand NAND2_29(G286,G42,G101);
nand NAND2_30(G287,G43,G102);
nand NAND2_31(G288,G44,G103);
nand NAND2_32(G297,G289,G290);
nand NAND2_33(G298,G297,G700);
nand NAND4_0(G301,G50,G49,G48,G47);
nand NAND2_34(G331,G333,G22);
nand NAND2_35(G332,G334,G331);
nand NAND2_36(G476,G486,G616);
nand NAND2_37(G482,G514,G518);
nand NAND2_38(G483,G515,G519);
nand NAND2_39(G484,G516,G520);
nand NAND2_40(G485,G517,G521);
nand NAND2_41(G514,G71,G67);
nand NAND2_42(G515,G72,G68);
nand NAND2_43(G516,G73,G69);
nand NAND2_44(G517,G487,G70);
nand NAND3_2(G554,G556,G557,G558);
nand NAND2_45(G555,G559,G560);
nand NAND2_46(G556,G578,G583);
nand NAND2_47(G557,G579,G584);
nand NAND2_48(G558,G580,G585);
nand NAND2_49(G559,G581,G586);
nand NAND2_50(G560,G582,G587);
nand NAND2_51(G578,G79,G74);
nand NAND2_52(G579,G80,G75);
nand NAND2_53(G580,G81,G76);
nand NAND2_54(G581,G82,G77);
nand NAND2_55(G582,G561,G78);
nand NAND2_56(G597,G602,G603);
nand NAND2_57(G598,G435,G83);
nand NAND4_1(G616,G482,G483,G484,G485);
nand NAND2_58(G700,G282,G283);
nor NOR2_0(G114,G115,G116);
nor NOR2_1(G115,G133,G25);
nor NOR2_2(G119,G120,G121);
nor NOR2_3(G120,G134,G26);
nor NOR2_4(G130,G131,G132);
nor NOR2_5(G131,G136,G28);
nor NOR2_6(G145,G146,G147);
nor NOR2_7(G146,G168,G30);
nor NOR2_8(G150,G151,G152);
nor NOR2_9(G151,G169,G31);
nor NOR2_10(G155,G156,G157);
nor NOR2_11(G156,G170,G32);
nor NOR2_12(G160,G161,G162);
nor NOR2_13(G161,G171,G33);
nor NOR2_14(G194,G195,G196);
nor NOR2_15(G195,G202,G37);
nor NOR2_16(G199,G200,G201);
nor NOR2_17(G200,G203,G38);
nor NOR2_18(G219,G220,G221);
nor NOR2_19(G220,G223,G41);
nor NOR2_20(G238,G239,G240);
nor NOR2_21(G239,G299,G42);
nor NOR2_22(G243,G244,G245);
nor NOR2_23(G244,G262,G43);
nor NOR2_24(G248,G249,G250);
nor NOR2_25(G249,G263,G44);
nor NOR2_26(G253,G254,G255);
nor NOR2_27(G254,G264,G45);
nor NOR2_28(G256,G257,G261);
nor NOR2_29(G257,G265,G46);
nor NOR3_0(G289,G270,G269,G268);
nor NOR2_30(G290,G267,G266);
nor NOR2_31(G299,G301,G328);
nor NOR2_32(G327,G330,G23);
nor NOR2_33(G328,G329,G327);
nor NOR2_34(G361,G362,G363);
nor NOR2_35(G362,G523,G51);
nor NOR2_36(G366,G367,G368);
nor NOR2_37(G367,G375,G52);
nor NOR2_38(G369,G370,G374);
nor NOR2_39(G370,G376,G53);
nor NOR2_40(G380,G381,G382);
nor NOR2_41(G381,G183,G54);
nor NOR2_42(G385,G386,G387);
nor NOR2_43(G386,G394,G55);
nor NOR2_44(G388,G389,G393);
nor NOR2_45(G389,G395,G56);
nor NOR2_46(G398,G399,G400);
nor NOR2_47(G399,G335,G57);
nor NOR2_48(G401,G402,G406);
nor NOR2_49(G402,G412,G58);
nor NOR2_50(G409,G410,G411);
nor NOR2_51(G410,G413,G59);
nor NOR2_52(G417,G418,G419);
nor NOR2_53(G418,G358,G60);
nor NOR2_54(G420,G421,G425);
nor NOR2_55(G421,G431,G61);
nor NOR2_56(G428,G429,G430);
nor NOR2_57(G429,G432,G62);
nor NOR2_58(G442,G443,G444);
nor NOR2_59(G444,G615,G64);
nor NOR2_60(G452,G453,G454);
nor NOR2_61(G454,G615,G66);
nor NOR2_62(G460,G461,G462);
nor NOR2_63(G461,G434,G67);
nor NOR2_64(G465,G466,G467);
nor NOR2_65(G466,G479,G68);
nor NOR2_66(G470,G471,G472);
nor NOR2_67(G471,G480,G69);
nor NOR2_68(G473,G474,G478);
nor NOR2_69(G474,G481,G70);
nor NOR3_1(G487,G71,G72,G73);
nor NOR2_70(G527,G528,G529);
nor NOR2_71(G528,G604,G74);
nor NOR2_72(G532,G533,G534);
nor NOR2_73(G533,G550,G75);
nor NOR2_74(G537,G538,G539);
nor NOR2_75(G538,G551,G76);
nor NOR2_76(G542,G543,G544);
nor NOR2_77(G543,G552,G77);
nor NOR2_78(G545,G546,G549);
nor NOR2_79(G546,G553,G78);
nor NOR4_0(G561,G79,G80,G81,G82);
nor NOR2_80(G593,G435,G524);
nor NOR2_81(G599,G598,G597);
nor NOR2_82(G660,G658,G86);
nor NOR2_83(G681,G683,G660);
nor NOR2_84(G686,G688,G660);
nor NOR2_85(G692,G694,G660);
nor NOR4_1(G703,G650,G651,G652,G653);
nor NOR2_86(G708,G709,G710);
nor NOR2_87(G710,G678,G94);
endmodule
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter AXIS_STROBE_WIDTH = (AXIS_WIDTH / 8),
parameter FRAME_WIDTH = 480,
parameter FRAME_HEIGHT = 272
)(
input clk,
input rst,
//Write Address Channel
input AXIML_AWVALID,
input [ADDR_WIDTH - 1: 0] AXIML_AWADDR,
output AXIML_AWREADY,
//Write Data Channel
input AXIML_WVALID,
output AXIML_WREADY,
input [STROBE_WIDTH - 1:0] AXIML_WSTRB,
input [DATA_WIDTH - 1: 0] AXIML_WDATA,
//Write Response Channel
output AXIML_BVALID,
input AXIML_BREADY,
output [1:0] AXIML_BRESP,
//Read Address Channel
input AXIML_ARVALID,
output AXIML_ARREADY,
input [ADDR_WIDTH - 1: 0] AXIML_ARADDR,
//Read Data Channel
output AXIML_RVALID,
input AXIML_RREADY,
output [1:0] AXIML_RRESP,
output [DATA_WIDTH - 1: 0] AXIML_RDATA,
output [AXIS_WIDTH - 1:0] AXISS_TDATA,
input AXISS_TREADY,
output AXISS_TVALID,
output AXISS_TLAST,
output [AXIS_STROBE_WIDTH - 1: 0] AXISS_TKEEP,
output [AXIS_STROBE_WIDTH - 1: 0] AXISS_TSTRB,
output [3:0] AXISS_TID,
output [31:0] AXISS_TDEST,
output [3:0] AXISS_TUSER
);
//Local Parameters
//Registers
reg r_rst;
reg r_axiss_tready;
always @ (*) r_rst = rst;
always @ (*) r_axiss_tready = AXISS_TREADY;
reg [3:0] test_id = 0;
//submodules
axi_nes #(
.AXIS_WIDTH (AXIS_WIDTH ),
.INVERT_AXI_RESET (0 ),
.INVERT_AXIS_RESET (0 ),
.FRAME_WIDTH (FRAME_WIDTH ),
.FRAME_HEIGHT (FRAME_HEIGHT )
) dut (
.clk (clk ),
.rst (r_rst ),
//AXI Lite Interface
.i_awvalid (AXIML_AWVALID ),
.i_awaddr (AXIML_AWADDR ),
.o_awready (AXIML_AWREADY ),
.i_wvalid (AXIML_WVALID ),
.o_wready (AXIML_WREADY ),
.i_wstrb (AXIML_WSTRB ),
.i_wdata (AXIML_WDATA ),
.o_bvalid (AXIML_BVALID ),
.i_bready (AXIML_BREADY ),
.o_bresp (AXIML_BRESP ),
.i_arvalid (AXIML_ARVALID ),
.o_arready (AXIML_ARREADY ),
.i_araddr (AXIML_ARADDR ),
.o_rvalid (AXIML_RVALID ),
.i_rready (AXIML_RREADY ),
.o_rresp (AXIML_RRESP ),
.o_rdata (AXIML_RDATA ),
//AXI Stream
.i_axis_clk (clk ),
.i_axis_rst (r_rst ),
.o_axis_user (AXISS_TUSER ),
.i_axis_ready (r_axiss_tready ),
.o_axis_data (AXISS_TDATA ),
.o_axis_last (AXISS_TLAST ),
.o_axis_valid (AXISS_TVALID )
);
//asynchronus logic
//synchronous logic
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
//
// Copyright 2016,2017 International Business Machines
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions AND
// limitations under the License.
//
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module action_wrapper #(
// Parameters of Axi Master Bus Interface AXI_CARD_MEM0 ; to DDR memory
parameter C_M_AXI_CARD_MEM0_ID_WIDTH = 4,
parameter C_M_AXI_CARD_MEM0_ADDR_WIDTH = 33,
parameter C_M_AXI_CARD_MEM0_DATA_WIDTH = 512,
parameter C_M_AXI_CARD_MEM0_AWUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_ARUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_WUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_RUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_BUSER_WIDTH = 1,
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = 512,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = 1,
parameter INT_BITS = 3,
parameter CONTEXT_BITS = 8
)
(
input ap_clk ,
input ap_rst_n ,
output interrupt ,
output [INT_BITS-2 : 0] interrupt_src ,
output [CONTEXT_BITS-1 : 0] interrupt_ctx ,
input interrupt_ack ,
//
/*
// AXI SDRAM Interface
output [C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 : 0 ] m_axi_card_mem0_araddr ,
output [1 : 0 ] m_axi_card_mem0_arburst ,
output [3 : 0 ] m_axi_card_mem0_arcache ,
output [C_M_AXI_CARD_MEM0_ID_WIDTH-1 : 0 ] m_axi_card_mem0_arid ,
output [7 : 0 ] m_axi_card_mem0_arlen ,
output [1 : 0 ] m_axi_card_mem0_arlock ,
output [2 : 0 ] m_axi_card_mem0_arprot ,
output [3 : 0 ] m_axi_card_mem0_arqos ,
input m_axi_card_mem0_arready ,
output [3 : 0 ] m_axi_card_mem0_arregion ,
output [2 : 0 ] m_axi_card_mem0_arsize ,
output [C_M_AXI_CARD_MEM0_ARUSER_WIDTH-1 : 0 ] m_axi_card_mem0_aruser ,
output m_axi_card_mem0_arvalid ,
output [C_M_AXI_CARD_MEM0_ADDR_WIDTH-1 : 0 ] m_axi_card_mem0_awaddr ,
output [1 : 0 ] m_axi_card_mem0_awburst ,
output [3 : 0 ] m_axi_card_mem0_awcache ,
output [C_M_AXI_CARD_MEM0_ID_WIDTH-1 : 0 ] m_axi_card_mem0_awid ,
output [7 : 0 ] m_axi_card_mem0_awlen ,
output [1 : 0 ] m_axi_card_mem0_awlock ,
output [2 : 0 ] m_axi_card_mem0_awprot ,
output [3 : 0 ] m_axi_card_mem0_awqos ,
input m_axi_card_mem0_awready ,
output [3 : 0 ] m_axi_card_mem0_awregion ,
output [2 : 0 ] m_axi_card_mem0_awsize ,
output [C_M_AXI_CARD_MEM0_AWUSER_WIDTH-1 : 0 ] m_axi_card_mem0_awuser ,
output m_axi_card_mem0_awvalid ,
input [C_M_AXI_CARD_MEM0_ID_WIDTH-1 : 0 ] m_axi_card_mem0_bid ,
output m_axi_card_mem0_bready ,
input [1 : 0 ] m_axi_card_mem0_bresp ,
input [C_M_AXI_CARD_MEM0_BUSER_WIDTH-1 : 0 ] m_axi_card_mem0_buser ,
input m_axi_card_mem0_bvalid ,
input [C_M_AXI_CARD_MEM0_DATA_WIDTH-1 : 0 ] m_axi_card_mem0_rdata ,
input [C_M_AXI_CARD_MEM0_ID_WIDTH-1 : 0 ] m_axi_card_mem0_rid ,
input m_axi_card_mem0_rlast ,
output m_axi_card_mem0_rready ,
input [1 : 0 ] m_axi_card_mem0_rresp ,
input [C_M_AXI_CARD_MEM0_RUSER_WIDTH-1 : 0 ] m_axi_card_mem0_ruser ,
input m_axi_card_mem0_rvalid ,
output [C_M_AXI_CARD_MEM0_DATA_WIDTH-1 : 0 ] m_axi_card_mem0_wdata ,
output m_axi_card_mem0_wlast ,
input m_axi_card_mem0_wready ,
output [(C_M_AXI_CARD_MEM0_DATA_WIDTH/8)-1 : 0 ] m_axi_card_mem0_wstrb ,
output [C_M_AXI_CARD_MEM0_WUSER_WIDTH-1 : 0 ] m_axi_card_mem0_wuser ,
output m_axi_card_mem0_wvalid ,
*/
//
// AXI Control Register Interface
input [C_S_AXI_CTRL_REG_ADDR_WIDTH-1 : 0 ] s_axi_ctrl_reg_araddr ,
output s_axi_ctrl_reg_arready ,
input s_axi_ctrl_reg_arvalid ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH-1 : 0 ] s_axi_ctrl_reg_awaddr ,
output s_axi_ctrl_reg_awready ,
input s_axi_ctrl_reg_awvalid ,
input s_axi_ctrl_reg_bready ,
output [1 : 0 ] s_axi_ctrl_reg_bresp ,
output s_axi_ctrl_reg_bvalid ,
output [C_S_AXI_CTRL_REG_DATA_WIDTH-1 : 0 ] s_axi_ctrl_reg_rdata ,
input s_axi_ctrl_reg_rready ,
output [1 : 0 ] s_axi_ctrl_reg_rresp ,
output s_axi_ctrl_reg_rvalid ,
input [C_S_AXI_CTRL_REG_DATA_WIDTH-1 : 0 ] s_axi_ctrl_reg_wdata ,
output s_axi_ctrl_reg_wready ,
input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8)-1 : 0 ] s_axi_ctrl_reg_wstrb ,
input s_axi_ctrl_reg_wvalid ,
//
// AXI Host Memory Interface
output [C_M_AXI_HOST_MEM_ADDR_WIDTH-1 : 0 ] m_axi_host_mem_araddr ,
output [1 : 0 ] m_axi_host_mem_arburst ,
output [3 : 0 ] m_axi_host_mem_arcache ,
output [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_arid ,
output [7 : 0 ] m_axi_host_mem_arlen ,
output [1 : 0 ] m_axi_host_mem_arlock ,
output [2 : 0 ] m_axi_host_mem_arprot ,
output [3 : 0 ] m_axi_host_mem_arqos ,
input m_axi_host_mem_arready ,
output [3 : 0 ] m_axi_host_mem_arregion ,
output [2 : 0 ] m_axi_host_mem_arsize ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH-1 : 0 ] m_axi_host_mem_aruser ,
output m_axi_host_mem_arvalid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH-1 : 0 ] m_axi_host_mem_awaddr ,
output [1 : 0 ] m_axi_host_mem_awburst ,
output [3 : 0 ] m_axi_host_mem_awcache ,
output [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_awid ,
output [7 : 0 ] m_axi_host_mem_awlen ,
output [1 : 0 ] m_axi_host_mem_awlock ,
output [2 : 0 ] m_axi_host_mem_awprot ,
output [3 : 0 ] m_axi_host_mem_awqos ,
input m_axi_host_mem_awready ,
output [3 : 0 ] m_axi_host_mem_awregion ,
output [2 : 0 ] m_axi_host_mem_awsize ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH-1 : 0 ] m_axi_host_mem_awuser ,
output m_axi_host_mem_awvalid ,
input [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_bid ,
output m_axi_host_mem_bready ,
input [1 : 0 ] m_axi_host_mem_bresp ,
input [C_M_AXI_HOST_MEM_BUSER_WIDTH-1 : 0 ] m_axi_host_mem_buser ,
input m_axi_host_mem_bvalid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH-1 : 0 ] m_axi_host_mem_rdata ,
input [C_M_AXI_HOST_MEM_ID_WIDTH-1 : 0 ] m_axi_host_mem_rid ,
input m_axi_host_mem_rlast ,
output m_axi_host_mem_rready ,
input [1 : 0 ] m_axi_host_mem_rresp ,
input [C_M_AXI_HOST_MEM_RUSER_WIDTH-1 : 0 ] m_axi_host_mem_ruser ,
input m_axi_host_mem_rvalid ,
output [C_M_AXI_HOST_MEM_DATA_WIDTH-1 : 0 ] m_axi_host_mem_wdata ,
output m_axi_host_mem_wlast ,
input m_axi_host_mem_wready ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8)-1 : 0 ] m_axi_host_mem_wstrb ,
output [C_M_AXI_HOST_MEM_WUSER_WIDTH-1 : 0 ] m_axi_host_mem_wuser ,
output m_axi_host_mem_wvalid
);
// Make wuser stick to 0
assign m_axi_card_mem0_wuser = 0;
assign m_axi_host_mem_wuser = 0;
action_hdl_helloworld #(
// Parameters of Axi Master Bus Interface AXI_CARD_MEM0 ; to DDR memory
.C_M_AXI_CARD_MEM0_ID_WIDTH (C_M_AXI_CARD_MEM0_ID_WIDTH ),
.C_M_AXI_CARD_MEM0_ADDR_WIDTH (C_M_AXI_CARD_MEM0_ADDR_WIDTH ),
.C_M_AXI_CARD_MEM0_DATA_WIDTH (C_M_AXI_CARD_MEM0_DATA_WIDTH ),
.C_M_AXI_CARD_MEM0_AWUSER_WIDTH(C_M_AXI_CARD_MEM0_AWUSER_WIDTH),
.C_M_AXI_CARD_MEM0_ARUSER_WIDTH(C_M_AXI_CARD_MEM0_ARUSER_WIDTH),
.C_M_AXI_CARD_MEM0_WUSER_WIDTH (C_M_AXI_CARD_MEM0_WUSER_WIDTH ),
.C_M_AXI_CARD_MEM0_RUSER_WIDTH (C_M_AXI_CARD_MEM0_RUSER_WIDTH ),
.C_M_AXI_CARD_MEM0_BUSER_WIDTH (C_M_AXI_CARD_MEM0_BUSER_WIDTH ),
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
.C_S_AXI_CTRL_REG_DATA_WIDTH (C_S_AXI_CTRL_REG_DATA_WIDTH ),
.C_S_AXI_CTRL_REG_ADDR_WIDTH (C_S_AXI_CTRL_REG_ADDR_WIDTH ),
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
.C_M_AXI_HOST_MEM_ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.C_M_AXI_HOST_MEM_ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.C_M_AXI_HOST_MEM_DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.C_M_AXI_HOST_MEM_AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.C_M_AXI_HOST_MEM_ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.C_M_AXI_HOST_MEM_WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.C_M_AXI_HOST_MEM_RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.C_M_AXI_HOST_MEM_BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) action_hdl_helloworld (
.clk (ap_clk),
.rst_n (ap_rst_n),
//---- AXI bus interfaced with SNAP core ----
// AXI write address channel
.m_axi_snap_awid (m_axi_host_mem_awid),
.m_axi_snap_awaddr (m_axi_host_mem_awaddr),
.m_axi_snap_awlen (m_axi_host_mem_awlen),
.m_axi_snap_awsize (m_axi_host_mem_awsize),
.m_axi_snap_awburst (m_axi_host_mem_awburst),
.m_axi_snap_awcache (m_axi_host_mem_awcache),
.m_axi_snap_awlock (m_axi_host_mem_awlock),
.m_axi_snap_awprot (m_axi_host_mem_awprot),
.m_axi_snap_awqos (m_axi_host_mem_awqos),
.m_axi_snap_awregion (m_axi_host_mem_awregion),
.m_axi_snap_awuser (m_axi_host_mem_awuser),
.m_axi_snap_awvalid (m_axi_host_mem_awvalid),
.m_axi_snap_awready (m_axi_host_mem_awready),
// AXI write data channel
//.m_axi_snap_wid (0),
.m_axi_snap_wdata (m_axi_host_mem_wdata),
.m_axi_snap_wstrb (m_axi_host_mem_wstrb),
.m_axi_snap_wlast (m_axi_host_mem_wlast),
.m_axi_snap_wvalid (m_axi_host_mem_wvalid),
.m_axi_snap_wready (m_axi_host_mem_wready),
// AXI write response channel
.m_axi_snap_bready (m_axi_host_mem_bready),
.m_axi_snap_bid (m_axi_host_mem_bid),
.m_axi_snap_bresp (m_axi_host_mem_bresp),
.m_axi_snap_bvalid (m_axi_host_mem_bvalid),
// AXI read address channel
.m_axi_snap_arid (m_axi_host_mem_arid),
.m_axi_snap_araddr (m_axi_host_mem_araddr),
.m_axi_snap_arlen (m_axi_host_mem_arlen),
.m_axi_snap_arsize (m_axi_host_mem_arsize),
.m_axi_snap_arburst (m_axi_host_mem_arburst),
.m_axi_snap_aruser (m_axi_host_mem_aruser),
.m_axi_snap_arcache (m_axi_host_mem_arcache),
.m_axi_snap_arlock (m_axi_host_mem_arlock),
.m_axi_snap_arprot (m_axi_host_mem_arprot),
.m_axi_snap_arqos (m_axi_host_mem_arqos),
.m_axi_snap_arregion (m_axi_host_mem_arregion),
.m_axi_snap_arvalid (m_axi_host_mem_arvalid),
.m_axi_snap_arready (m_axi_host_mem_arready),
// AXI ead data channel
.m_axi_snap_rready (m_axi_host_mem_rready),
.m_axi_snap_rid (m_axi_host_mem_rid),
.m_axi_snap_rdata (m_axi_host_mem_rdata),
.m_axi_snap_rresp (m_axi_host_mem_rresp),
.m_axi_snap_rlast (m_axi_host_mem_rlast),
.m_axi_snap_rvalid (m_axi_host_mem_rvalid),
/*
//---- AXI bus interfaced with DDR ----
// AXI write address channel
.m_axi_ddr_awid (m_axi_card_mem0_awid),
.m_axi_ddr_awaddr (m_axi_card_mem0_awaddr),
.m_axi_ddr_awlen (m_axi_card_mem0_awlen),
.m_axi_ddr_awsize (m_axi_card_mem0_awsize),
.m_axi_ddr_awburst (m_axi_card_mem0_awburst),
.m_axi_ddr_awcache (m_axi_card_mem0_awcache),
.m_axi_ddr_awlock (m_axi_card_mem0_awlock),
.m_axi_ddr_awprot (m_axi_card_mem0_awprot),
.m_axi_ddr_awqos (m_axi_card_mem0_awqos),
.m_axi_ddr_awregion (m_axi_card_mem0_awregion),
.m_axi_ddr_awuser (m_axi_card_mem0_awuser),
.m_axi_ddr_awvalid (m_axi_card_mem0_awvalid),
.m_axi_ddr_awready (m_axi_card_mem0_awready),
// AXI write data channel
//.m_axi_ddr_wid (0),
.m_axi_ddr_wdata (m_axi_card_mem0_wdata),
.m_axi_ddr_wstrb (m_axi_card_mem0_wstrb),
.m_axi_ddr_wlast (m_axi_card_mem0_wlast),
.m_axi_ddr_wvalid (m_axi_card_mem0_wvalid),
.m_axi_ddr_wready (m_axi_card_mem0_wready),
// AXI write response channel
.m_axi_ddr_bready (m_axi_card_mem0_bready),
.m_axi_ddr_bid (m_axi_card_mem0_bid),
.m_axi_ddr_bresp (m_axi_card_mem0_bresp),
.m_axi_ddr_bvalid (m_axi_card_mem0_bvalid),
// AXI read address channel
.m_axi_ddr_arid (m_axi_card_mem0_arid),
.m_axi_ddr_araddr (m_axi_card_mem0_araddr),
.m_axi_ddr_arlen (m_axi_card_mem0_arlen),
.m_axi_ddr_arsize (m_axi_card_mem0_arsize),
.m_axi_ddr_arburst (m_axi_card_mem0_arburst),
.m_axi_ddr_aruser (m_axi_card_mem0_aruser),
.m_axi_ddr_arcache (m_axi_card_mem0_arcache),
.m_axi_ddr_arlock (m_axi_card_mem0_arlock),
.m_axi_ddr_arprot (m_axi_card_mem0_arprot),
.m_axi_ddr_arqos (m_axi_card_mem0_arqos),
.m_axi_ddr_arregion (m_axi_card_mem0_arregion),
.m_axi_ddr_arvalid (m_axi_card_mem0_arvalid),
.m_axi_ddr_arready (m_axi_card_mem0_arready),
// AXI ead data channel
.m_axi_ddr_rready (m_axi_card_mem0_rready),
.m_axi_ddr_rid (m_axi_card_mem0_rid),
.m_axi_ddr_rdata (m_axi_card_mem0_rdata),
.m_axi_ddr_rresp (m_axi_card_mem0_rresp),
.m_axi_ddr_rlast (m_axi_card_mem0_rlast),
.m_axi_ddr_rvalid (m_axi_card_mem0_rvalid),
*/
//---- AXI Lite bus interfaced with SNAP core ----
// AXI write address channel
.s_axi_snap_awready (s_axi_ctrl_reg_awready),
.s_axi_snap_awaddr (s_axi_ctrl_reg_awaddr),
.s_axi_snap_awprot (s_axi_ctrl_reg_awprot),
.s_axi_snap_awvalid (s_axi_ctrl_reg_awvalid),
// axi write data channel
.s_axi_snap_wready (s_axi_ctrl_reg_wready),
.s_axi_snap_wdata (s_axi_ctrl_reg_wdata),
.s_axi_snap_wstrb (s_axi_ctrl_reg_wstrb),
.s_axi_snap_wvalid (s_axi_ctrl_reg_wvalid),
// AXI response channel
.s_axi_snap_bresp (s_axi_ctrl_reg_bresp),
.s_axi_snap_bvalid (s_axi_ctrl_reg_bvalid),
.s_axi_snap_bready (s_axi_ctrl_reg_bready),
// AXI read address channel
.s_axi_snap_arready (s_axi_ctrl_reg_arready),
.s_axi_snap_arvalid (s_axi_ctrl_reg_arvalid),
.s_axi_snap_araddr (s_axi_ctrl_reg_araddr),
.s_axi_snap_arprot (s_axi_ctrl_reg_arprot),
// AXI read data channel
.s_axi_snap_rdata (s_axi_ctrl_reg_rdata),
.s_axi_snap_rresp (s_axi_ctrl_reg_rresp),
.s_axi_snap_rready (s_axi_ctrl_reg_rready),
.s_axi_snap_rvalid (s_axi_ctrl_reg_rvalid),
.i_action_type (32'h10140002), //Should match ACTION_TYPE_HDL_HELLOWORLD with sw
.i_action_version (32'h00000001) //Hardware Version
);
endmodule
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.11.2013 10:45:37
// Design Name:
// Module Name: toe
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module topmost_zooknukv_para (
// 233MHz clock input
input sys_clk_p,
input sys_clk_n,
// 200MHz reference clock input
input clk_ref_p,
input clk_ref_n,
//-SI5324 I2C programming interface
inout i2c_clk,
inout i2c_data,
output i2c_mux_rst_n,
output si5324_rst_n,
// 156.25 MHz clock in
input xphy_refclk_p,
input xphy_refclk_n,
output xphy0_txp,
output xphy0_txn,
input xphy0_rxp,
input xphy0_rxn,
input button_north,
input button_east,
input button_west,
output xphy1_txp,
output xphy1_txn,
input xphy1_rxp,
input xphy1_rxn,
output xphy2_txp,
output xphy2_txn,
input xphy2_rxp,
input xphy2_rxn,
output xphy3_txp,
output xphy3_txn,
input xphy3_rxp,
input xphy3_rxn,
output[3:0] sfp_tx_disable,
// Connection to SODIMM-A
output [15:0] c0_ddr3_addr,
output [2:0] c0_ddr3_ba,
output c0_ddr3_cas_n,
output c0_ddr3_ck_p,
output c0_ddr3_ck_n,
output c0_ddr3_cke,
output c0_ddr3_cs_n,
output [7:0] c0_ddr3_dm,
inout [63:0] c0_ddr3_dq,
inout [7:0] c0_ddr3_dqs_p,
inout [7:0] c0_ddr3_dqs_n,
output c0_ddr3_odt,
output c0_ddr3_ras_n,
output c0_ddr3_reset_n,
output c0_ddr3_we_n,
// Connection to SODIMM-B
output [15:0] c1_ddr3_addr,
output [2:0] c1_ddr3_ba,
output c1_ddr3_cas_n,
output c1_ddr3_ck_p,
output c1_ddr3_ck_n,
output c1_ddr3_cke,
output c1_ddr3_cs_n,
output [7:0] c1_ddr3_dm,
inout [63:0] c1_ddr3_dq,
inout [7:0] c1_ddr3_dqs_p,
inout [7:0] c1_ddr3_dqs_n,
output c1_ddr3_odt,
output c1_ddr3_ras_n,
output c1_ddr3_reset_n,
output c1_ddr3_we_n,
input sys_rst,
// UART
//input RxD,
//output TxD,
output [7:0] led,
input [7:0] switch
);
wire reset;
wire network_init;
reg button_east_reg;
reg[7:0] led_reg;
wire[7:0] led_out;
assign reset = button_east_reg;// | ~network_init);
//assign reset = ~init_calib_complete_r; //~reset156_25_n;
wire aresetn;
assign aresetn = network_init;
//assign aresetn = init_calib_complete_r; //reset156_25_n;
wire axi_clk;
wire clk_ref_200;
/*
* Network Signals
*/
wire AXI_M_Stream_TVALID;
wire AXI_M_Stream_TREADY;
wire[63:0] AXI_M_Stream_TDATA;
wire[7:0] AXI_M_Stream_TKEEP;
wire AXI_M_Stream_TLAST;
wire AXI_S_Stream_TVALID;
wire AXI_S_Stream_TREADY;
wire[63:0] AXI_S_Stream_TDATA;
wire[7:0] AXI_S_Stream_TKEEP;
wire AXI_S_Stream_TLAST;
wire AXI_M2_Stream_TVALID;
wire AXI_M2_Stream_TREADY;
wire[63:0] AXI_M2_Stream_TDATA;
wire[7:0] AXI_M2_Stream_TKEEP;
wire AXI_M2_Stream_TLAST;
wire AXI_S2_Stream_TVALID;
wire AXI_S2_Stream_TREADY;
wire[63:0] AXI_S2_Stream_TDATA;
wire[7:0] AXI_S2_Stream_TKEEP;
wire AXI_S2_Stream_TLAST;
wire AXI_S2_Stream_TUSER;
wire AXI_M3_Stream_TVALID;
wire AXI_M3_Stream_TREADY;
wire[63:0] AXI_M3_Stream_TDATA;
wire[7:0] AXI_M3_Stream_TKEEP;
wire AXI_M3_Stream_TLAST;
wire AXI_S3_Stream_TVALID;
wire AXI_S3_Stream_TREADY;
wire[63:0] AXI_S3_Stream_TDATA;
wire[7:0] AXI_S3_Stream_TKEEP;
wire AXI_S3_Stream_TLAST;
wire AXI_S3_Stream_TUSER;
wire AXI_M4_Stream_TVALID;
wire AXI_M4_Stream_TREADY;
wire[63:0] AXI_M4_Stream_TDATA;
wire[7:0] AXI_M4_Stream_TKEEP;
wire AXI_M4_Stream_TLAST;
wire AXI_S4_Stream_TVALID;
wire AXI_S4_Stream_TREADY;
wire[63:0] AXI_S4_Stream_TDATA;
wire[7:0] AXI_S4_Stream_TKEEP;
wire AXI_S4_Stream_TLAST;
/*
* RX Memory Signals
*/
// memory cmd streams
wire axis_rxread_cmd_TVALID;
wire axis_rxread_cmd_TREADY;
wire[71:0] axis_rxread_cmd_TDATA;
wire axis_rxwrite_cmd_TVALID;
wire axis_rxwrite_cmd_TREADY;
wire[71:0] axis_rxwrite_cmd_TDATA;
// memory sts streams
wire axis_rxread_sts_TVALID;
wire axis_rxread_sts_TREADY;
wire[7:0] axis_rxread_sts_TDATA;
wire axis_rxwrite_sts_TVALID;
wire axis_rxwrite_sts_TREADY;
wire[31:0] axis_rxwrite_sts_TDATA;
// memory data streams
wire axis_rxread_data_TVALID;
wire axis_rxread_data_TREADY;
wire[63:0] axis_rxread_data_TDATA;
wire[7:0] axis_rxread_data_TKEEP;
wire axis_rxread_data_TLAST;
wire axis_rxwrite_data_TVALID;
wire axis_rxwrite_data_TREADY;
wire[63:0] axis_rxwrite_data_TDATA;
wire[7:0] axis_rxwrite_data_TKEEP;
wire axis_rxwrite_data_TLAST;
/*
* TX Memory Signals
*/
// memory cmd streams
wire axis_txread_cmd_TVALID;
wire axis_txread_cmd_TREADY;
wire[71:0] axis_txread_cmd_TDATA;
wire axis_txwrite_cmd_TVALID;
wire axis_txwrite_cmd_TREADY;
wire[71:0] axis_txwrite_cmd_TDATA;
// memory sts streams
wire axis_txread_sts_TVALID;
wire axis_txread_sts_TREADY;
wire[7:0] axis_txread_sts_TDATA;
wire axis_txwrite_sts_TVALID;
wire axis_txwrite_sts_TREADY;
wire[63:0] axis_txwrite_sts_TDATA;
// memory data streams
wire axis_txread_data_TVALID;
wire axis_txread_data_TREADY;
wire[63:0] axis_txread_data_TDATA;
wire[7:0] axis_txread_data_TKEEP;
wire axis_txread_data_TLAST;
wire axis_txwrite_data_TVALID;
wire axis_txwrite_data_TREADY;
wire[63:0] axis_txwrite_data_TDATA;
wire[7:0] axis_txwrite_data_TKEEP;
wire axis_txwrite_data_TLAST;
/*
* Application Signals
*/
// listen&close port
// open&close connection
wire axis_listen_port_TVALID;
wire axis_listen_port_TREADY;
wire[15:0] axis_listen_port_TDATA;
wire axis_listen_port_status_TVALID;
wire axis_listen_port_status_TREADY;
wire[7:0] axis_listen_port_status_TDATA;
//wire axis_close_port_TVALID;
//wire axis_close_port_TREADY;
//wire[15:0] axis_close_port_TDATA;
// notifications and pkg fetching
wire axis_notifications_TVALID;
wire axis_notifications_TREADY;
wire[87:0] axis_notifications_TDATA;
wire axis_read_package_TVALID;
wire axis_read_package_TREADY;
wire[31:0] axis_read_package_TDATA;
// open&close connection
wire axis_open_connection_TVALID;
wire axis_open_connection_TREADY;
wire[47:0] axis_open_connection_TDATA;
wire axis_open_status_TVALID;
wire axis_open_status_TREADY;
wire[23:0] axis_open_status_TDATA;
wire axis_close_connection_TVALID;
wire axis_close_connection_TREADY;
wire[15:0] axis_close_connection_TDATA;
// rx data
wire axis_rx_metadata_TVALID;
wire axis_rx_metadata_TREADY;
wire[15:0] axis_rx_metadata_TDATA;
wire axis_rx_data_TVALID;
wire axis_rx_data_TREADY;
wire[63:0] axis_rx_data_TDATA;
wire[7:0] axis_rx_data_TKEEP;
wire axis_rx_data_TLAST;
// tx data
wire axis_tx_metadata_TVALID;
wire axis_tx_metadata_TREADY;
wire[15:0] axis_tx_metadata_TDATA;
wire axis_tx_data_TVALID;
wire axis_tx_data_TREADY;
wire[63:0] axis_tx_data_TDATA;
wire[7:0] axis_tx_data_TKEEP;
wire axis_tx_data_TLAST;
wire axis_tx_status_TVALID;
wire axis_tx_status_TREADY;
wire[63:0] axis_tx_status_TDATA;
/*
* UDP APP Interface
*/
// UDP port
wire axis_udp_open_port_tvalid;
wire axis_udp_open_port_tready;
wire[15:0] axis_udp_open_port_tdata;
wire axis_udp_open_port_status_tvalid;
wire axis_udp_open_port_status_tready;
wire[7:0] axis_udp_open_port_status_tdata; //actually only [0:0]
// UDP RX
wire axis_udp_rx_data_tvalid;
wire axis_udp_rx_data_tready;
wire[63:0] axis_udp_rx_data_tdata;
wire[7:0] axis_udp_rx_data_tkeep;
wire axis_udp_rx_data_tlast;
wire axis_udp_rx_metadata_tvalid;
wire axis_udp_rx_metadata_tready;
wire[95:0] axis_udp_rx_metadata_tdata;
// UDP TX
wire axis_udp_tx_data_tvalid;
wire axis_udp_tx_data_tready;
wire[63:0] axis_udp_tx_data_tdata;
wire[7:0] axis_udp_tx_data_tkeep;
wire axis_udp_tx_data_tlast;
wire axis_udp_tx_metadata_tvalid;
wire axis_udp_tx_metadata_tready;
wire[95:0] axis_udp_tx_metadata_tdata;
wire axis_udp_tx_length_tvalid;
wire axis_udp_tx_length_tready;
wire[15:0] axis_udp_tx_length_tdata;
reg runExperiment;
reg dualModeEn = 0;
reg[7:0] useConn = 8'h01;
reg[7:0] pkgWordCount = 8'h08;
reg[31:0] regIpAddress1 = 32'h00000000;
reg[15:0] numCons = 16'h0001;
wire[63:0] vio_cmd;
//assign vio_cmd[0] = 0;
//assign vio_cmd[1] = 1;
//assign vio_cmd[9:2] = 8'h01;
//assign vio_cmd[17:10] = 8'h20;
//assign vio_vcmv
always @(posedge axi_clk) begin
button_east_reg <= button_east;
led_reg <= led_out;
runExperiment <= button_north | vio_cmd[0];
dualModeEn <= vio_cmd[1];
useConn <= vio_cmd[9:2];
pkgWordCount <= vio_cmd[17:10];
regIpAddress1 <= vio_cmd[49:18];
//numCons <= vio_cmd[33:18];
end
assign led = led_reg;
/*
* 10G Network Interface Module
*/
vc709_10g_interface n10g_interface_inst
(
.clk_ref_p(clk_ref_p),
.clk_ref_n(clk_ref_n),
.reset(reset),
.aresetn(aresetn),
.i2c_clk(i2c_clk),
.i2c_data(i2c_data),
.i2c_mux_rst_n(i2c_mux_rst_n),
.si5324_rst_n(si5324_rst_n),
.xphy_refclk_p(xphy_refclk_p),
.xphy_refclk_n(xphy_refclk_n),
.xphy0_txp(xphy0_txp),
.xphy0_txn(xphy0_txn),
.xphy0_rxp(xphy0_rxp),
.xphy0_rxn(xphy0_rxn),
.xphy1_txp(xphy1_txp),
.xphy1_txn(xphy1_txn),
.xphy1_rxp(xphy1_rxp),
.xphy1_rxn(xphy1_rxn),
.xphy2_txp(xphy2_txp),
.xphy2_txn(xphy2_txn),
.xphy2_rxp(xphy2_rxp),
.xphy2_rxn(xphy2_rxn),
.xphy3_txp(xphy3_txp),
.xphy3_txn(xphy3_txn),
.xphy3_rxp(xphy3_rxp),
.xphy3_rxn(xphy3_rxn),
//master
.axis_i_0_tdata(AXI_S_Stream_TDATA),
.axis_i_0_tvalid(AXI_S_Stream_TVALID),
.axis_i_0_tlast(AXI_S_Stream_TLAST),
.axis_i_0_tuser(),
.axis_i_0_tkeep(AXI_S_Stream_TKEEP),
.axis_i_0_tready(AXI_S_Stream_TREADY),
//slave
.axis_o_0_tdata(AXI_M_Stream_TDATA),
.axis_o_0_tvalid(AXI_M_Stream_TVALID),
.axis_o_0_tlast(AXI_M_Stream_TLAST),
.axis_o_0_tuser(0),
.axis_o_0_tkeep(AXI_M_Stream_TKEEP),
.axis_o_0_tready(AXI_M_Stream_TREADY),
/*
//master2
.axis_i_1_tdata(AXI_S2_Stream_TDATA),
.axis_i_1_tvalid(AXI_S2_Stream_TVALID),
.axis_i_1_tlast(AXI_S2_Stream_TLAST),
.axis_i_1_tuser(AXI_S2_Stream_TUSER),
.axis_i_1_tkeep(AXI_S2_Stream_TKEEP),
.axis_i_1_tready(AXI_S2_Stream_TREADY),
//slave2
.axis_o_1_tdata(AXI_M2_Stream_TDATA),
.axis_o_1_tvalid(AXI_M2_Stream_TVALID),
.axis_o_1_tlast(AXI_M2_Stream_TLAST),
.axis_o_1_tuser(0),
.axis_o_1_tkeep(AXI_M2_Stream_TKEEP),
.axis_o_1_tready(AXI_M2_Stream_TREADY),
//master3
.axis_i_2_tdata(AXI_S3_Stream_TDATA),
.axis_i_2_tvalid(AXI_S3_Stream_TVALID),
.axis_i_2_tlast(AXI_S3_Stream_TLAST),
.axis_i_2_tuser(AXI_S3_Stream_TUSER),
.axis_i_2_tkeep(AXI_S3_Stream_TKEEP),
.axis_i_2_tready(AXI_S3_Stream_TREADY),
//slave3
.axis_o_2_tdata(AXI_M3_Stream_TDATA),
.axis_o_2_tvalid(AXI_M3_Stream_TVALID),
.axis_o_2_tlast(AXI_M3_Stream_TLAST),
.axis_o_2_tuser(0),
.axis_o_2_tkeep(AXI_M3_Stream_TKEEP),
.axis_o_2_tready(AXI_M3_Stream_TREADY),
/*
//master4
.axis_i_3_tdata(AXI_S4_Stream_TDATA),
.axis_i_3_tvalid(AXI_S4_Stream_TVALID),
.axis_i_3_tlast(AXI_S4_Stream_TLAST),
.axis_i_3_tuser(),
.axis_i_3_tkeep(AXI_S4_Stream_TKEEP),
.axis_i_3_tready(AXI_S4_Stream_TREADY),
//slave4
.axis_o_3_tdata(AXI_M4_Stream_TDATA),
.axis_o_3_tvalid(AXI_M4_Stream_TVALID),
.axis_o_3_tlast(AXI_M4_Stream_TLAST),
.axis_o_3_tuser(0),
.axis_o_3_tkeep(AXI_M4_Stream_TKEEP),
.axis_o_3_tready(AXI_M4_Stream_TREADY),
*/
.sfp_tx_disable(sfp_tx_disable),
.clk156_out(axi_clk),
.clk_ref_200_out(clk_ref_200),
.network_reset_done(network_init),
.led(led_out)
);
/*
* TCP/IP Wrapper Module
*/
wire[31:0] ip_address;
wire[15:0] regSessionCount_V;
wire regSessionCount_V_vld;
wire [161:0] debug_out;
tcp_ip_wrapper #(
.MAC_ADDRESS (48'hE59D02350A00), //bytes reversed
.IP_ADDRESS (32'hD1D4010A), //reverse
.IP_SUBNET_MASK (32'h00FFFFFF), //reverse
.IP_DEFAULT_GATEWAY (32'h01D4010A), //reverse
.DHCP_EN (0)
)
tcp_ip_inst (
.aclk (axi_clk),
//.reset (reset),
.aresetn (aresetn),
// network interface streams
.AXI_M_Stream_TVALID (AXI_M_Stream_TVALID),
.AXI_M_Stream_TREADY (AXI_M_Stream_TREADY),
.AXI_M_Stream_TDATA (AXI_M_Stream_TDATA),
.AXI_M_Stream_TKEEP (AXI_M_Stream_TKEEP),
.AXI_M_Stream_TLAST (AXI_M_Stream_TLAST),
.AXI_S_Stream_TVALID (AXI_S_Stream_TVALID),
.AXI_S_Stream_TREADY (AXI_S_Stream_TREADY),
.AXI_S_Stream_TDATA (AXI_S_Stream_TDATA),
.AXI_S_Stream_TKEEP (AXI_S_Stream_TKEEP),
.AXI_S_Stream_TLAST (AXI_S_Stream_TLAST),
// memory rx cmd streams
.m_axis_rxread_cmd_TVALID (axis_rxread_cmd_TVALID),
.m_axis_rxread_cmd_TREADY (axis_rxread_cmd_TREADY),
.m_axis_rxread_cmd_TDATA (axis_rxread_cmd_TDATA),
.m_axis_rxwrite_cmd_TVALID (axis_rxwrite_cmd_TVALID),
.m_axis_rxwrite_cmd_TREADY (axis_rxwrite_cmd_TREADY),
.m_axis_rxwrite_cmd_TDATA (axis_rxwrite_cmd_TDATA),
// memory rx status streams
.s_axis_rxread_sts_TVALID (axis_rxread_sts_TVALID),
.s_axis_rxread_sts_TREADY (axis_rxread_sts_TREADY),
.s_axis_rxread_sts_TDATA (axis_rxread_sts_TDATA),
.s_axis_rxwrite_sts_TVALID (axis_rxwrite_sts_TVALID),
.s_axis_rxwrite_sts_TREADY (axis_rxwrite_sts_TREADY),
.s_axis_rxwrite_sts_TDATA (axis_rxwrite_sts_TDATA),
// memory rx data streams
.s_axis_rxread_data_TVALID (axis_rxread_data_TVALID),
.s_axis_rxread_data_TREADY (axis_rxread_data_TREADY),
.s_axis_rxread_data_TDATA (axis_rxread_data_TDATA),
.s_axis_rxread_data_TKEEP (axis_rxread_data_TKEEP),
.s_axis_rxread_data_TLAST (axis_rxread_data_TLAST),
.m_axis_rxwrite_data_TVALID (axis_rxwrite_data_TVALID),
.m_axis_rxwrite_data_TREADY (axis_rxwrite_data_TREADY),
.m_axis_rxwrite_data_TDATA (axis_rxwrite_data_TDATA),
.m_axis_rxwrite_data_TKEEP (axis_rxwrite_data_TKEEP),
.m_axis_rxwrite_data_TLAST (axis_rxwrite_data_TLAST),
// memory tx cmd streams
.m_axis_txread_cmd_TVALID (axis_txread_cmd_TVALID),
.m_axis_txread_cmd_TREADY (axis_txread_cmd_TREADY),
.m_axis_txread_cmd_TDATA (axis_txread_cmd_TDATA),
.m_axis_txwrite_cmd_TVALID (axis_txwrite_cmd_TVALID),
.m_axis_txwrite_cmd_TREADY (axis_txwrite_cmd_TREADY),
.m_axis_txwrite_cmd_TDATA (axis_txwrite_cmd_TDATA),
// memory tx status streams
.s_axis_txread_sts_TVALID (axis_txread_sts_TVALID),
.s_axis_txread_sts_TREADY (axis_txread_sts_TREADY),
.s_axis_txread_sts_TDATA (axis_txread_sts_TDATA),
.s_axis_txwrite_sts_TVALID (axis_txwrite_sts_TVALID),
.s_axis_txwrite_sts_TREADY (axis_txwrite_sts_TREADY),
.s_axis_txwrite_sts_TDATA (axis_txwrite_sts_TDATA),
// memory tx data streams
.s_axis_txread_data_TVALID (axis_txread_data_TVALID),
.s_axis_txread_data_TREADY (axis_txread_data_TREADY),
.s_axis_txread_data_TDATA (axis_txread_data_TDATA),
.s_axis_txread_data_TKEEP (axis_txread_data_TKEEP),
.s_axis_txread_data_TLAST (axis_txread_data_TLAST),
.m_axis_txwrite_data_TVALID (axis_txwrite_data_TVALID),
.m_axis_txwrite_data_TREADY (axis_txwrite_data_TREADY),
.m_axis_txwrite_data_TDATA (axis_txwrite_data_TDATA),
.m_axis_txwrite_data_TKEEP (axis_txwrite_data_TKEEP),
.m_axis_txwrite_data_TLAST (axis_txwrite_data_TLAST),
//application interface streams
.m_axis_listen_port_status_TVALID (axis_listen_port_status_TVALID),
.m_axis_listen_port_status_TREADY (axis_listen_port_status_TREADY),
.m_axis_listen_port_status_TDATA (axis_listen_port_status_TDATA),
.m_axis_notifications_TVALID (axis_notifications_TVALID),
.m_axis_notifications_TREADY (axis_notifications_TREADY),
.m_axis_notifications_TDATA (axis_notifications_TDATA),
.m_axis_open_status_TVALID (axis_open_status_TVALID),
.m_axis_open_status_TREADY (axis_open_status_TREADY),
.m_axis_open_status_TDATA (axis_open_status_TDATA),
.m_axis_rx_data_TVALID (axis_rx_data_TVALID),
.m_axis_rx_data_TREADY (axis_rx_data_TREADY), //axis_rx_data_TREADY
.m_axis_rx_data_TDATA (axis_rx_data_TDATA),
.m_axis_rx_data_TKEEP (axis_rx_data_TKEEP),
.m_axis_rx_data_TLAST (axis_rx_data_TLAST),
.m_axis_rx_metadata_TVALID (axis_rx_metadata_TVALID),
.m_axis_rx_metadata_TREADY (axis_rx_metadata_TREADY),
.m_axis_rx_metadata_TDATA (axis_rx_metadata_TDATA),
.m_axis_tx_status_TVALID (axis_tx_status_TVALID),
.m_axis_tx_status_TREADY (axis_tx_status_TREADY),
.m_axis_tx_status_TDATA (axis_tx_status_TDATA),
.s_axis_listen_port_TVALID (axis_listen_port_TVALID),
.s_axis_listen_port_TREADY (axis_listen_port_TREADY),
.s_axis_listen_port_TDATA (axis_listen_port_TDATA),
//.s_axis_close_port_TVALID (axis_close_port_TVALID),
//.s_axis_close_port_TREADY (axis_close_port_TREADY),
//.s_axis_close_port_TDATA (axis_close_port_TDATA),
.s_axis_close_connection_TVALID (axis_close_connection_TVALID),
.s_axis_close_connection_TREADY (axis_close_connection_TREADY),
.s_axis_close_connection_TDATA (axis_close_connection_TDATA),
.s_axis_open_connection_TVALID (axis_open_connection_TVALID),
.s_axis_open_connection_TREADY (axis_open_connection_TREADY),
.s_axis_open_connection_TDATA (axis_open_connection_TDATA),
.s_axis_read_package_TVALID (axis_read_package_TVALID),
.s_axis_read_package_TREADY (axis_read_package_TREADY),
.s_axis_read_package_TDATA (axis_read_package_TDATA),
.s_axis_tx_data_TVALID (axis_tx_data_TVALID),
.s_axis_tx_data_TREADY (axis_tx_data_TREADY),
.s_axis_tx_data_TDATA (axis_tx_data_TDATA),
.s_axis_tx_data_TKEEP (axis_tx_data_TKEEP),
.s_axis_tx_data_TLAST (axis_tx_data_TLAST),
.s_axis_tx_metadata_TVALID (axis_tx_metadata_TVALID),
.s_axis_tx_metadata_TREADY (axis_tx_metadata_TREADY),
.s_axis_tx_metadata_TDATA (axis_tx_metadata_TDATA),
// UDP
/*
.s_axis_udp_open_port_tvalid(axis_udp_open_port_tvalid),
.s_axis_udp_open_port_tready(axis_udp_open_port_tready),
.s_axis_udp_open_port_tdata(axis_udp_open_port_tdata),
.m_axis_udp_open_port_status_tvalid(axis_udp_open_port_status_tvalid),
.m_axis_udp_open_port_status_tready(axis_udp_open_port_status_tready),
.m_axis_udp_open_port_status_tdata(axis_udp_open_port_status_tdata), //actually only [0:0]
// UDP RX
.m_axis_udp_rx_data_tvalid(axis_udp_rx_data_tvalid),
.m_axis_udp_rx_data_tready(axis_udp_rx_data_tready),
.m_axis_udp_rx_data_tdata(axis_udp_rx_data_tdata),
.m_axis_udp_rx_data_tkeep(axis_udp_rx_data_tkeep),
.m_axis_udp_rx_data_tlast(axis_udp_rx_data_tlast),
.m_axis_udp_rx_metadata_tvalid(axis_udp_rx_metadata_tvalid),
.m_axis_udp_rx_metadata_tready(axis_udp_rx_metadata_tready),
.m_axis_udp_rx_metadata_tdata(axis_udp_rx_metadata_tdata),
// UDP TX
.s_axis_udp_tx_data_tvalid(axis_udp_tx_data_tvalid),
.s_axis_udp_tx_data_tready(axis_udp_tx_data_tready),
.s_axis_udp_tx_data_tdata(axis_udp_tx_data_tdata),
.s_axis_udp_tx_data_tkeep(axis_udp_tx_data_tkeep),
.s_axis_udp_tx_data_tlast(axis_udp_tx_data_tlast),
.s_axis_udp_tx_metadata_tvalid(axis_udp_tx_metadata_tvalid),
.s_axis_udp_tx_metadata_tready(axis_udp_tx_metadata_tready),
.s_axis_udp_tx_metadata_tdata(axis_udp_tx_metadata_tdata),
.s_axis_udp_tx_length_tvalid(axis_udp_tx_length_tvalid),
.s_axis_udp_tx_length_tready(axis_udp_tx_length_tready),
.s_axis_udp_tx_length_tdata(axis_udp_tx_length_tdata),
*/
.ip_address_out(ip_address),
.regSessionCount_V(regSessionCount_V),
.regSessionCount_V_ap_vld(regSessionCount_V_vld),
.debug_out(debug_out),
.board_number(switch[3:0]),
.subnet_number(switch[5:4])
);
//FOR memcached
wire axis_mc_rx_data_TVALID;
wire axis_mc_rx_data_TREADY;
wire[191:0] axis_mc_rx_data_TDATA;
wire axis_mc_tx_data_TVALID;
wire axis_mc_tx_data_TREADY;
wire[191:0] axis_mc_tx_data_TDATA;
//UDP
wire axis_mc_udp_rx_data_TVALID;
wire axis_mc_udp_rx_data_TREADY;
wire[191:0] axis_mc_udp_rx_data_TDATA;
wire axis_mc_udp_tx_data_TVALID;
wire axis_mc_udp_tx_data_TREADY;
wire[191:0] axis_mc_udp_tx_data_TDATA;
//TCP
wire axis_mc_tcp_rx_data_TVALID;
wire axis_mc_tcp_rx_data_TREADY;
wire[63:0] axis_mc_tcp_rx_data_TDATA;
wire[7:0] axis_mc_tcp_rx_data_TKEEP;
wire axis_mc_tcp_rx_data_TLAST;
wire axis_mc_tcp_tx_data_TVALID;
wire axis_mc_tcp_tx_data_TREADY;
wire[63:0] axis_mc_tcp_tx_data_TDATA;
wire[7:0] axis_mc_tcp_tx_data_TKEEP;
wire axis_mc_tcp_tx_data_TLAST;
assign axis_mc_udp_rx_data_TREADY = 1'b1;
assign axis_mc_udp_tx_data_TVALID = 1'b0;
assign axis_mc_udp_tx_data_TDATA = 0;
/*
* Application Module
*/
wire [511:0] ht_dramRdData_data;
wire ht_dramRdData_empty;
wire ht_dramRdData_almost_empty;
wire ht_dramRdData_read;
wire [63:0] ht_cmd_dramRdData_data;
wire ht_cmd_dramRdData_valid;
wire ht_cmd_dramRdData_stall;
wire [511:0] ht_dramWrData_data;
wire ht_dramWrData_valid;
wire ht_dramWrData_stall;
wire [63:0] ht_cmd_dramWrData_data;
wire ht_cmd_dramWrData_valid;
wire ht_cmd_dramWrData_stall;
wire [511:0] upd_dramRdData_data;
wire upd_dramRdData_empty;
wire upd_dramRdData_almost_empty;
wire upd_dramRdData_read;
wire [63:0] upd_cmd_dramRdData_data;
wire upd_cmd_dramRdData_valid;
wire upd_cmd_dramRdData_stall;
wire [511:0] upd_dramWrData_data;
wire upd_dramWrData_valid;
wire upd_dramWrData_stall;
wire [63:0] upd_cmd_dramWrData_data;
wire upd_cmd_dramWrData_valid;
wire upd_cmd_dramWrData_stall;
wire [63:0] ptr_rdcmd_data;
wire ptr_rdcmd_valid;
wire ptr_rdcmd_ready;
wire [512-1:0] ptr_rd_data;
wire ptr_rd_valid;
wire ptr_rd_ready;
wire [512-1:0] ptr_wr_data;
wire ptr_wr_valid;
wire ptr_wr_ready;
wire [63:0] ptr_wrcmd_data;
wire ptr_wrcmd_valid;
wire ptr_wrcmd_ready;
wire [63:0] bmap_rdcmd_data;
wire bmap_rdcmd_valid;
wire bmap_rdcmd_ready;
wire [512-1:0] bmap_rd_data;
wire bmap_rd_valid;
wire bmap_rd_ready;
wire [512-1:0] bmap_wr_data;
wire bmap_wr_valid;
wire bmap_wr_ready;
wire [63:0] bmap_wrcmd_data;
wire bmap_wrcmd_valid;
wire bmap_wrcmd_ready;
assign AXI_M2_Stream_TKEEP = AXI_M2_Stream_TVALID==1 ? 8'b11111111 : 8'b00000000;
assign AXI_M3_Stream_TKEEP = 8'b11111111;
assign AXI_M4_Stream_TKEEP = 8'b11111111;
//DRAM MEM interface
//wire clk156_25;
wire reset233_n; //active low reset signal for 233MHz clock domain
wire reset156_25_n;
//wire clk233;
wire clk200, clk200_i;
wire c0_init_calib_complete;
wire c1_init_calib_complete;
//toe stream interface signals
wire toeTX_s_axis_read_cmd_tvalid;
wire toeTX_s_axis_read_cmd_tready;
wire[71:0] toeTX_s_axis_read_cmd_tdata;
//read status
wire toeTX_m_axis_read_sts_tvalid;
wire toeTX_m_axis_read_sts_tready;
wire[7:0] toeTX_m_axis_read_sts_tdata;
//read stream
wire[63:0] toeTX_m_axis_read_tdata;
wire[7:0] toeTX_m_axis_read_tkeep;
wire toeTX_m_axis_read_tlast;
wire toeTX_m_axis_read_tvalid;
wire toeTX_m_axis_read_tready;
//write commands
wire toeTX_s_axis_write_cmd_tvalid;
wire toeTX_s_axis_write_cmd_tready;
wire[71:0] toeTX_s_axis_write_cmd_tdata;
//write status
wire toeTX_m_axis_write_sts_tvalid;
wire toeTX_m_axis_write_sts_tready;
wire[31:0] toeTX_m_axis_write_sts_tdata;
//write stream
wire[63:0] toeTX_s_axis_write_tdata;
wire[7:0] toeTX_s_axis_write_tkeep;
wire toeTX_s_axis_write_tlast;
wire toeTX_s_axis_write_tvalid;
wire toeTX_s_axis_write_tready;
//upd stream interface signals
wire upd_s_axis_read_cmd_tvalid;
wire upd_s_axis_read_cmd_tready;
wire[71:0] upd_s_axis_read_cmd_tdata;
//read status
wire upd_m_axis_read_sts_tvalid;
wire upd_m_axis_read_sts_tready;
wire[7:0] upd_m_axis_read_sts_tdata;
//read stream
wire[511:0] upd_m_axis_read_tdata;
wire[63:0] upd_m_axis_read_tkeep;
wire upd_m_axis_read_tlast;
wire upd_m_axis_read_tvalid;
wire upd_m_axis_read_tready;
//write commands
wire upd_s_axis_write_cmd_tvalid;
wire upd_s_axis_write_cmd_tready;
wire[71:0] upd_s_axis_write_cmd_tdata;
//write status
wire upd_m_axis_write_sts_tvalid;
wire upd_m_axis_write_sts_tready;
wire[31:0] upd_m_axis_write_sts_tdata;
//write stream
wire[511:0] upd_s_axis_write_tdata;
wire[63:0] upd_s_axis_write_tkeep;
wire upd_s_axis_write_tlast;
wire upd_s_axis_write_tvalid;
wire upd_s_axis_write_tready;
wire[511:0] upd_s_axis_write_tdata_x;
wire[63:0] upd_s_axis_write_tkeep_x;
wire upd_s_axis_write_tlast_x;
wire upd_s_axis_write_tvalid_x;
wire upd_s_axis_write_tready_x;
//muu_TopWrapper multiuser_kvs_top (
zookeeper_tcp_top_parallel_nkv nkv_TopWrapper (
.m_axis_open_connection_TVALID(axis_open_connection_TVALID),
.m_axis_open_connection_TDATA(axis_open_connection_TDATA),
.m_axis_open_connection_TREADY(axis_open_connection_TREADY),
.m_axis_close_connection_TVALID(axis_close_connection_TVALID),
.m_axis_close_connection_TDATA(axis_close_connection_TDATA),
.m_axis_close_connection_TREADY(axis_close_connection_TREADY),
.m_axis_listen_port_TVALID(axis_listen_port_TVALID), // output wire m_axis_listen_port_TVALID
.m_axis_listen_port_TREADY(axis_listen_port_TREADY), // input wire m_axis_listen_port_TREADY
.m_axis_listen_port_TDATA(axis_listen_port_TDATA), // output wire [15 : 0] m_axis_listen_port_TDATA
.m_axis_read_package_TVALID(axis_read_package_TVALID), // output wire m_axis_read_package_TVALID
.m_axis_read_package_TREADY(axis_read_package_TREADY), // input wire m_axis_read_package_TREADY
.m_axis_read_package_TDATA(axis_read_package_TDATA), // output wire [31 : 0] m_axis_read_package_TDATA
.m_axis_tx_data_TVALID(axis_tx_data_TVALID), // output wire m_axis_tx_data_TVALID
.m_axis_tx_data_TREADY(axis_tx_data_TREADY), // input wire m_axis_tx_data_TREADY
.m_axis_tx_data_TDATA(axis_tx_data_TDATA), // output wire [63 : 0] m_axis_tx_data_TDATA
.m_axis_tx_data_TKEEP(axis_tx_data_TKEEP), // output wire [7 : 0] m_axis_tx_data_TKEEP
.m_axis_tx_data_TLAST(axis_tx_data_TLAST), // output wire [0 : 0] m_axis_tx_data_TLAST
.m_axis_tx_metadata_TVALID(axis_tx_metadata_TVALID), // output wire m_axis_tx_metadata_TVALID
.m_axis_tx_metadata_TREADY(axis_tx_metadata_TREADY), // input wire m_axis_tx_metadata_TREADY
.m_axis_tx_metadata_TDATA(axis_tx_metadata_TDATA), // output wire [15 : 0] m_axis_tx_metadata_TDATA
.s_axis_listen_port_status_TVALID(axis_listen_port_status_TVALID), // input wire s_axis_listen_port_status_TVALID
.s_axis_listen_port_status_TREADY(axis_listen_port_status_TREADY), // output wire s_axis_listen_port_status_TREADY
.s_axis_listen_port_status_TDATA(axis_listen_port_status_TDATA), // input wire [7 : 0] s_axis_listen_port_status_TDATA
.s_axis_open_status_TVALID(axis_open_status_TVALID),
.s_axis_open_status_TDATA(axis_open_status_TDATA),
.s_axis_open_status_TREADY(axis_open_status_TREADY),
.s_axis_notifications_TVALID(axis_notifications_TVALID), // input wire s_axis_notifications_TVALID
.s_axis_notifications_TREADY(axis_notifications_TREADY), // output wire s_axis_notifications_TREADY
.s_axis_notifications_TDATA(axis_notifications_TDATA), // input wire [87 : 0] s_axis_notifications_TDATA
.s_axis_rx_data_TVALID(axis_rx_data_TVALID), // input wire s_axis_rx_data_TVALID
.s_axis_rx_data_TREADY(axis_rx_data_TREADY), // output wire s_axis_rx_data_TREADY
.s_axis_rx_data_TDATA(axis_rx_data_TDATA), // input wire [63 : 0] s_axis_rx_data_TDATA
.s_axis_rx_data_TKEEP(axis_rx_data_TKEEP), // input wire [7 : 0] s_axis_rx_data_TKEEP
.s_axis_rx_data_TLAST(axis_rx_data_TLAST), // input wire [0 : 0] s_axis_rx_data_TLAST
.s_axis_rx_metadata_TVALID(axis_rx_metadata_TVALID), // input wire s_axis_rx_metadata_TVALID
.s_axis_rx_metadata_TREADY(axis_rx_metadata_TREADY), // output wire s_axis_rx_metadata_TREADY
.s_axis_rx_metadata_TDATA(axis_rx_metadata_TDATA), // input wire [15 : 0] s_axis_rx_metadata_TDATA
.s_axis_tx_status_TVALID(axis_tx_status_TVALID), // input wire s_axis_tx_status_TVALID
.s_axis_tx_status_TREADY(axis_tx_status_TREADY), // output wire s_axis_tx_status_TREADY
.s_axis_tx_status_TDATA(axis_tx_status_TDATA), // input wire [23 : 0] s_axis_tx_status_TDATA
.ht_dramRdData_data(ht_dramRdData_data),
.ht_dramRdData_empty(ht_dramRdData_empty),
.ht_dramRdData_almost_empty(ht_dramRdData_almost_empty),
.ht_dramRdData_read(ht_dramRdData_read),
.ht_cmd_dramRdData_data(ht_cmd_dramRdData_data),
.ht_cmd_dramRdData_valid(ht_cmd_dramRdData_valid),
.ht_cmd_dramRdData_stall(ht_cmd_dramRdData_stall),
.ht_dramWrData_data(ht_dramWrData_data),
.ht_dramWrData_valid(ht_dramWrData_valid),
.ht_dramWrData_stall(ht_dramWrData_stall),
.ht_cmd_dramWrData_data(ht_cmd_dramWrData_data),
.ht_cmd_dramWrData_valid(ht_cmd_dramWrData_valid),
.ht_cmd_dramWrData_stall(ht_cmd_dramWrData_stall),
// Update DRAM Connection
.upd_dramRdData_data(upd_dramRdData_data),
.upd_dramRdData_empty(upd_dramRdData_empty),
.upd_dramRdData_almost_empty(upd_dramRdData_almost_empty),
.upd_dramRdData_read(upd_dramRdData_read),
.upd_cmd_dramRdData_data(upd_cmd_dramRdData_data),
.upd_cmd_dramRdData_valid(upd_cmd_dramRdData_valid),
.upd_cmd_dramRdData_stall(upd_cmd_dramRdData_stall),
.upd_dramWrData_data(upd_dramWrData_data),
.upd_dramWrData_valid(upd_dramWrData_valid),
.upd_dramWrData_stall(upd_dramWrData_stall),
.upd_cmd_dramWrData_data(upd_cmd_dramWrData_data),
.upd_cmd_dramWrData_valid(upd_cmd_dramWrData_valid),
.upd_cmd_dramWrData_stall(upd_cmd_dramWrData_stall),
.ptr_rdcmd_data(ptr_rdcmd_data),
.ptr_rdcmd_valid(ptr_rdcmd_valid),
.ptr_rdcmd_ready(ptr_rdcmd_ready),
.ptr_rd_data(ptr_rd_data),
.ptr_rd_valid(ptr_rd_valid),
.ptr_rd_ready(ptr_rd_ready),
.ptr_wr_data(ptr_wr_data),
.ptr_wr_valid(ptr_wr_valid),
.ptr_wr_ready(ptr_wr_ready),
.ptr_wrcmd_data(ptr_wrcmd_data),
.ptr_wrcmd_valid(ptr_wrcmd_valid),
.ptr_wrcmd_ready(ptr_wrcmd_ready),
.bmap_rdcmd_data(bmap_rdcmd_data),
.bmap_rdcmd_valid(bmap_rdcmd_valid),
.bmap_rdcmd_ready(bmap_rdcmd_ready),
.bmap_rd_data(bmap_rd_data),
.bmap_rd_valid(bmap_rd_valid),
.bmap_rd_ready(bmap_rd_ready),
.bmap_wr_data(bmap_wr_data),
.bmap_wr_valid(bmap_wr_valid),
.bmap_wr_ready(bmap_wr_ready),
.bmap_wrcmd_data(bmap_wrcmd_data),
.bmap_wrcmd_valid(bmap_wrcmd_valid),
.bmap_wrcmd_ready(bmap_wrcmd_ready),
/*
.para0_in_tvalid(AXI_S2_Stream_TVALID),
.para0_in_tready(AXI_S2_Stream_TREADY),
.para0_in_tdata(AXI_S2_Stream_TDATA),
.para0_in_tlast(AXI_S2_Stream_TLAST),
.para0_out_tvalid(AXI_M2_Stream_TVALID),
.para0_out_tready(AXI_M2_Stream_TREADY),
.para0_out_tdata(AXI_M2_Stream_TDATA),
.para0_out_tlast(AXI_M2_Stream_TLAST),
.para1_in_tvalid(AXI_S3_Stream_TVALID),
.para1_in_tready(AXI_S3_Stream_TREADY),
.para1_in_tdata(AXI_S3_Stream_TDATA),
.para1_in_tlast(AXI_S3_Stream_TLAST),
.para1_out_tvalid(AXI_M3_Stream_TVALID),
.para1_out_tready(AXI_M3_Stream_TREADY),
.para1_out_tdata(AXI_M3_Stream_TDATA),
.para1_out_tlast(AXI_M3_Stream_TLAST),
.para2_in_tvalid(AXI_S4_Stream_TVALID),
.para2_in_tready(AXI_S4_Stream_TREADY),
.para2_in_tdata(AXI_S4_Stream_TDATA),
.para2_in_tlast(AXI_S4_Stream_TLAST),
.para2_out_tvalid(AXI_M4_Stream_TVALID),
.para2_out_tready(AXI_M4_Stream_TREADY),
.para2_out_tdata(AXI_M4_Stream_TDATA),
.para2_out_tlast(AXI_M4_Stream_TLAST),
*/
.hadretransmit({toeTX_m_axis_read_tdata[54:0],toeTX_m_axis_read_tkeep[7:0],toeTX_m_axis_read_tvalid}),
//.toedebug({1'b0, AXI_S_Stream_TLAST, AXI_S_Stream_TREADY, AXI_S_Stream_TVALID, toeTX_s_axis_write_cmd_tdata[59:32], toeTX_s_axis_read_cmd_tdata[63:32], 1'b0,toeTX_s_axis_write_cmd_tvalid, toeTX_s_axis_read_cmd_tvalid,toeTX_s_axis_write_tvalid ,toeTX_s_axis_write_tdata[59:0],toeTX_s_axis_write_tkeep[7:0]}),
.toedebug(debug_out),
.aclk(axi_clk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);
wire ddr3_calib_complete, init_calib_complete;
wire toeTX_compare_error, ht_compare_error, upd_compare_error;
//reg rst_n_r1, rst_n_r2, rst_n_r3;
//reg reset156_25_n_r1, reset156_25_n_r2, reset156_25_n_r3;
//registers for crossing clock domains (from 233MHz to 156.25MHz)
reg c0_init_calib_complete_r1, c0_init_calib_complete_r2;
reg c1_init_calib_complete_r1, c1_init_calib_complete_r2;
//- 212MHz differential clock for 1866Mbps DDR3 controller
wire sys_clk_212_i;
IBUFGDS #(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
) clk_212_ibufg (
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_212_i)
);
wire sys_rst_i;
IBUF rst_212_bufg
(
.I (sys_rst),
.O (sys_rst_i)
);
always @(posedge axi_clk)
if (aresetn == 0) begin
c0_init_calib_complete_r1 <= 1'b0;
c0_init_calib_complete_r2 <= 1'b0;
c1_init_calib_complete_r1 <= 1'b0;
c1_init_calib_complete_r2 <= 1'b0;
end
else begin
c0_init_calib_complete_r1 <= c0_init_calib_complete;
c0_init_calib_complete_r2 <= c0_init_calib_complete_r1;
c1_init_calib_complete_r1 <= c1_init_calib_complete;
c1_init_calib_complete_r2 <= c1_init_calib_complete_r1;
end
assign ddr3_calib_complete = c0_init_calib_complete_r2 & c1_init_calib_complete_r2;
assign init_calib_complete = ddr3_calib_complete;
/*
* TX Memory Signals
*/
// memory cmd streams
assign toeTX_s_axis_read_cmd_tvalid = axis_txread_cmd_TVALID;
assign axis_txread_cmd_TREADY = toeTX_s_axis_read_cmd_tready;
assign toeTX_s_axis_read_cmd_tdata = axis_txread_cmd_TDATA;
assign toeTX_s_axis_write_cmd_tvalid = axis_txwrite_cmd_TVALID;
assign axis_txwrite_cmd_TREADY = toeTX_s_axis_write_cmd_tready;
assign toeTX_s_axis_write_cmd_tdata = axis_txwrite_cmd_TDATA;
// memory sts streams
assign axis_txread_sts_TVALID = toeTX_m_axis_read_sts_tvalid;
assign toeTX_m_axis_read_sts_tready = axis_txread_sts_TREADY;
assign axis_txread_sts_TDATA = toeTX_m_axis_read_sts_tdata;
assign axis_txwrite_sts_TVALID = toeTX_m_axis_write_sts_tvalid;
assign toeTX_m_axis_write_sts_tready = axis_txwrite_sts_TREADY;
assign axis_txwrite_sts_TDATA = toeTX_m_axis_write_sts_tdata;
// memory data streams
assign axis_txread_data_TVALID = toeTX_m_axis_read_tvalid;
assign toeTX_m_axis_read_tready = axis_txread_data_TREADY;
assign axis_txread_data_TDATA = toeTX_m_axis_read_tdata;
assign axis_txread_data_TKEEP = toeTX_m_axis_read_tkeep;
assign axis_txread_data_TLAST = toeTX_m_axis_read_tlast;
assign toeTX_s_axis_write_tvalid = axis_txwrite_data_TVALID;
assign axis_txwrite_data_TREADY = toeTX_s_axis_write_tready;
assign toeTX_s_axis_write_tdata = axis_txwrite_data_TDATA;
assign toeTX_s_axis_write_tkeep = axis_txwrite_data_TKEEP;
assign toeTX_s_axis_write_tlast = axis_txwrite_data_TLAST;
wire toeRX_s_axis_read_cmd_tvalid;
wire toeRX_s_axis_read_cmd_tready;
wire[71:0] toeRX_s_axis_read_cmd_tdata;
//read status
wire toeRX_m_axis_read_sts_tvalid;
wire toeRX_m_axis_read_sts_tready;
wire[7:0] toeRX_m_axis_read_sts_tdata;
//read stream
wire[63:0] toeRX_m_axis_read_tdata;
wire[7:0] toeRX_m_axis_read_tkeep;
wire toeRX_m_axis_read_tlast;
wire toeRX_m_axis_read_tvalid;
wire toeRX_m_axis_read_tready;
//write commands
wire toeRX_s_axis_write_cmd_tvalid;
wire toeRX_s_axis_write_cmd_tready;
wire[71:0] toeRX_s_axis_write_cmd_tdata;
//write status
wire toeRX_m_axis_write_sts_tvalid;
wire toeRX_m_axis_write_sts_tready;
wire[31:0] toeRX_m_axis_write_sts_tdata;
//write stream
wire[63:0] toeRX_s_axis_write_tdata;
wire[7:0] toeRX_s_axis_write_tkeep;
wire toeRX_s_axis_write_tlast;
wire toeRX_s_axis_write_tvalid;
wire toeRX_s_axis_write_tready;
/*
* RX Memory Signals
*/
// memory cmd streams
assign toeRX_s_axis_read_cmd_tvalid = axis_rxread_cmd_TVALID;
assign axis_rxread_cmd_TREADY = toeRX_s_axis_read_cmd_tready;
assign toeRX_s_axis_read_cmd_tdata = axis_rxread_cmd_TDATA;
assign toeRX_s_axis_write_cmd_tvalid = axis_rxwrite_cmd_TVALID;
assign axis_rxwrite_cmd_TREADY = toeRX_s_axis_write_cmd_tready;
assign toeRX_s_axis_write_cmd_tdata = axis_rxwrite_cmd_TDATA;
// memory sts streams
assign axis_rxread_sts_TVALID = 1'b0; //toeRX_m_axis_read_sts_tvalid;
assign toeRX_m_axis_read_sts_tready = axis_rxread_sts_TREADY;
assign axis_rxread_sts_TDATA = toeRX_m_axis_read_sts_tdata;
assign axis_rxwrite_sts_TVALID = 1'b0; //toeRX_m_axis_write_sts_tvalid;
assign toeRX_m_axis_write_sts_tready = axis_rxwrite_sts_TREADY;
assign axis_rxwrite_sts_TDATA = toeRX_m_axis_write_sts_tdata;
// memory data streams
assign axis_rxread_data_TVALID = toeRX_m_axis_read_tvalid;
assign toeRX_m_axis_read_tready = axis_rxread_data_TREADY;
assign axis_rxread_data_TDATA = toeRX_m_axis_read_tdata;
assign axis_rxread_data_TKEEP = toeRX_m_axis_read_tkeep;
assign axis_rxread_data_TLAST = toeRX_m_axis_read_tlast;
assign toeRX_s_axis_write_tvalid = axis_rxwrite_data_TVALID;
assign axis_rxwrite_data_TREADY = toeRX_s_axis_write_tready;
assign toeRX_s_axis_write_tdata = axis_rxwrite_data_TDATA;
assign toeRX_s_axis_write_tkeep = axis_rxwrite_data_TKEEP;
assign toeRX_s_axis_write_tlast = axis_rxwrite_data_TLAST;
assign upd_m_axis_read_sts_tready = 1'b1;
assign upd_m_axis_write_sts_tready = 1'b1;
/*
* TCP DDR Memory Interface
*/
nkv_ddr_mem_inf mem_inf_inst
(
.clk156_25(axi_clk),
//.reset233_n(reset233_n), //active low reset signal for 233MHz clock domain
.reset156_25_n(ddr3_calib_complete),
.clk212(sys_clk_212_i),
.clk200(clk_ref_200),
.sys_rst(sys_rst_i),
//ddr3 pins
//SODIMM 0
// Inouts
.c0_ddr3_dq(c0_ddr3_dq),
.c0_ddr3_dqs_n(c0_ddr3_dqs_n),
.c0_ddr3_dqs_p(c0_ddr3_dqs_p),
// Outputs
.c0_ddr3_addr(c0_ddr3_addr),
.c0_ddr3_ba(c0_ddr3_ba),
.c0_ddr3_ras_n(c0_ddr3_ras_n),
.c0_ddr3_cas_n(c0_ddr3_cas_n),
.c0_ddr3_we_n(c0_ddr3_we_n),
.c0_ddr3_reset_n(c0_ddr3_reset_n),
.c0_ddr3_ck_p(c0_ddr3_ck_p),
.c0_ddr3_ck_n(c0_ddr3_ck_n),
.c0_ddr3_cke(c0_ddr3_cke),
.c0_ddr3_cs_n(c0_ddr3_cs_n),
.c0_ddr3_dm(c0_ddr3_dm),
.c0_ddr3_odt(c0_ddr3_odt),
.c0_ui_clk(),
.c0_init_calib_complete(c0_init_calib_complete),
//SODIMM 1
// Inouts
.c1_ddr3_dq(c1_ddr3_dq),
.c1_ddr3_dqs_n(c1_ddr3_dqs_n),
.c1_ddr3_dqs_p(c1_ddr3_dqs_p),
// Outputs
.c1_ddr3_addr(c1_ddr3_addr),
.c1_ddr3_ba(c1_ddr3_ba),
.c1_ddr3_ras_n(c1_ddr3_ras_n),
.c1_ddr3_cas_n(c1_ddr3_cas_n),
.c1_ddr3_we_n(c1_ddr3_we_n),
.c1_ddr3_reset_n(c1_ddr3_reset_n),
.c1_ddr3_ck_p(c1_ddr3_ck_p),
.c1_ddr3_ck_n(c1_ddr3_ck_n),
.c1_ddr3_cke(c1_ddr3_cke),
.c1_ddr3_cs_n(c1_ddr3_cs_n),
.c1_ddr3_dm(c1_ddr3_dm),
.c1_ddr3_odt(c1_ddr3_odt),
.c1_ui_clk(),
.c1_init_calib_complete(c1_init_calib_complete),
//toe stream interface signals
.toeTX_s_axis_read_cmd_tvalid(toeTX_s_axis_read_cmd_tvalid),
.toeTX_s_axis_read_cmd_tready(toeTX_s_axis_read_cmd_tready),
.toeTX_s_axis_read_cmd_tdata(toeTX_s_axis_read_cmd_tdata),
//read status
.toeTX_m_axis_read_sts_tvalid(toeTX_m_axis_read_sts_tvalid),
.toeTX_m_axis_read_sts_tready(toeTX_m_axis_read_sts_tready),
.toeTX_m_axis_read_sts_tdata(toeTX_m_axis_read_sts_tdata),
//read stream
.toeTX_m_axis_read_tdata(toeTX_m_axis_read_tdata),
.toeTX_m_axis_read_tkeep(toeTX_m_axis_read_tkeep),
.toeTX_m_axis_read_tlast(toeTX_m_axis_read_tlast),
.toeTX_m_axis_read_tvalid(toeTX_m_axis_read_tvalid),
.toeTX_m_axis_read_tready(toeTX_m_axis_read_tready),
//write commands
.toeTX_s_axis_write_cmd_tvalid(toeTX_s_axis_write_cmd_tvalid),
.toeTX_s_axis_write_cmd_tready(toeTX_s_axis_write_cmd_tready),
.toeTX_s_axis_write_cmd_tdata(toeTX_s_axis_write_cmd_tdata),
//write status
.toeTX_m_axis_write_sts_tvalid(toeTX_m_axis_write_sts_tvalid),
.toeTX_m_axis_write_sts_tready(toeTX_m_axis_write_sts_tready),
.toeTX_m_axis_write_sts_tdata(toeTX_m_axis_write_sts_tdata),
//write stream
.toeTX_s_axis_write_tdata(toeTX_s_axis_write_tdata),
.toeTX_s_axis_write_tkeep(toeTX_s_axis_write_tkeep),
.toeTX_s_axis_write_tlast(toeTX_s_axis_write_tlast),
.toeTX_s_axis_write_tvalid(toeTX_s_axis_write_tvalid),
.toeTX_s_axis_write_tready(toeTX_s_axis_write_tready),
// HashTable DRAM Connection
.ht_dramRdData_data(ht_dramRdData_data),
.ht_dramRdData_empty(ht_dramRdData_empty),
.ht_dramRdData_almost_empty(ht_dramRdData_almost_empty),
.ht_dramRdData_read(ht_dramRdData_read),
.ht_cmd_dramRdData_data(ht_cmd_dramRdData_data),
.ht_cmd_dramRdData_valid(ht_cmd_dramRdData_valid),
.ht_cmd_dramRdData_stall(ht_cmd_dramRdData_stall),
.ht_dramWrData_data(ht_dramWrData_data),
.ht_dramWrData_valid(ht_dramWrData_valid),
.ht_dramWrData_stall(ht_dramWrData_stall),
.ht_cmd_dramWrData_data(ht_cmd_dramWrData_data),
.ht_cmd_dramWrData_valid(ht_cmd_dramWrData_valid),
.ht_cmd_dramWrData_stall(ht_cmd_dramWrData_stall),
.upd_dramRdData_data(upd_dramRdData_data),
.upd_dramRdData_empty(upd_dramRdData_empty),
.upd_dramRdData_almost_empty(upd_dramRdData_almost_empty),
.upd_dramRdData_read(upd_dramRdData_read),
.upd_cmd_dramRdData_data(upd_cmd_dramRdData_data),
.upd_cmd_dramRdData_valid(upd_cmd_dramRdData_valid),
.upd_cmd_dramRdData_stall(upd_cmd_dramRdData_stall),
.upd_dramWrData_data(upd_dramWrData_data),
.upd_dramWrData_valid(upd_dramWrData_valid),
.upd_dramWrData_stall(upd_dramWrData_stall),
.upd_cmd_dramWrData_data(upd_cmd_dramWrData_data),
.upd_cmd_dramWrData_valid(upd_cmd_dramWrData_valid),
.upd_cmd_dramWrData_stall(upd_cmd_dramWrData_stall),
.ptr_rdcmd_data(ptr_rdcmd_data),
.ptr_rdcmd_valid(ptr_rdcmd_valid),
.ptr_rdcmd_ready(ptr_rdcmd_ready),
.ptr_rd_data(ptr_rd_data),
.ptr_rd_valid(ptr_rd_valid),
.ptr_rd_ready(ptr_rd_ready),
.ptr_wr_data(ptr_wr_data),
.ptr_wr_valid(ptr_wr_valid),
.ptr_wr_ready(ptr_wr_ready),
.ptr_wrcmd_data(ptr_wrcmd_data),
.ptr_wrcmd_valid(ptr_wrcmd_valid),
.ptr_wrcmd_ready(ptr_wrcmd_ready),
.bmap_rdcmd_data(bmap_rdcmd_data),
.bmap_rdcmd_valid(bmap_rdcmd_valid),
.bmap_rdcmd_ready(bmap_rdcmd_ready),
.bmap_rd_data(bmap_rd_data),
.bmap_rd_valid(bmap_rd_valid),
.bmap_rd_ready(bmap_rd_ready),
.bmap_wr_data(bmap_wr_data),
.bmap_wr_valid(bmap_wr_valid),
.bmap_wr_ready(bmap_wr_ready),
.bmap_wrcmd_data(bmap_wrcmd_data),
.bmap_wrcmd_valid(bmap_wrcmd_valid),
.bmap_wrcmd_ready(bmap_wrcmd_ready)
);
//////////////////////////
// chipscope debug
//////////////////////////
/*
wire [35:0] control0, control1;
wire [255:0] data;
reg[255:0] debug_r;
reg[255:0] debug_r2;
reg ready1;
reg ready2;
reg ready3;
reg ready4;
reg ready5;
reg ready6;
reg ready7;
reg ready8;
reg ready9;
reg ready10;
reg ready11;
reg ready12;
reg[15:0] mac_rx_count;
reg[15:0] mac_tx_count;
reg[15:0] open_count;
reg[15:0] success_count;
reg[15:0] fail_count;
reg[15:0] zeroid_count;
always @(posedge axi_clk) begin
if (aresetn == 0) begin
mac_rx_count <= 0;
mac_tx_count <= 0;
open_count <= 0;
success_count <= 0;
fail_count <= 0;
zeroid_count <= 0;
end
else begin
end
end
always @(posedge axi_clk) begin
debug_r[0] <= axis_mc_tx_data_TVALID;
debug_r[1] <= axis_mc_tx_data_TREADY;
debug_r[2] <= axis_mc_rx_data_TVALID;
debug_r[3] <= axis_mc_rx_data_TREADY;
debug_r[4] <= axis_mc_udp_rx_data_TVALID;
debug_r[5] <= axis_mc_udp_rx_data_TREADY;
debug_r[6] <= axis_mc_udp_tx_data_TVALID;
debug_r[7] <= axis_mc_udp_tx_data_TREADY;
//TCP
debug_r[8] <= axis_mc_tcp_rx_data_TVALID;
debug_r[9] <= axis_mc_tcp_rx_data_TREADY;
debug_r[10] <= axis_mc_tcp_tx_data_TVALID;
debug_r[11] <= axis_mc_tcp_tx_data_TREADY;
debug_r[12] <= AXI_M2_Stream_TVALID;
debug_r[13] <= AXI_M2_Stream_TREADY;
debug_r[29:14] <= AXI_M2_Stream_TDATA;
debug_r[30] <= AXI_M2_Stream_TKEEP;
debug_r[31] <= AXI_M2_Stream_TLAST;
debug_r[32] <= AXI_S2_Stream_TVALID;
debug_r[33] <= AXI_S2_Stream_TREADY;
debug_r[49:34] <= AXI_S2_Stream_TDATA;
debug_r[50] <= AXI_S2_Stream_TUSER;
debug_r[51] <= AXI_S2_Stream_TLAST;
debug_r[52] <= AXI_M3_Stream_TVALID;
debug_r[53] <= AXI_M3_Stream_TREADY;
debug_r[59:54] <= AXI_M3_Stream_TDATA;
debug_r[60] <= AXI_M3_Stream_TKEEP;
debug_r[61] <= AXI_M3_Stream_TLAST;
debug_r[62] <= AXI_S3_Stream_TVALID;
debug_r[63] <= AXI_S3_Stream_TREADY;
debug_r[79:64] <= AXI_S3_Stream_TDATA;
debug_r[80] <= AXI_S3_Stream_TUSER;
debug_r[81] <= AXI_S3_Stream_TLAST;
debug_r[83] <= AXI_M4_Stream_TVALID;
debug_r[84] <= AXI_M4_Stream_TREADY;
//debug_r[85] <= AXI_M_Stream_TDATA;
debug_r[92:85] <= AXI_M4_Stream_TKEEP;
debug_r[93] <= AXI_M4_Stream_TLAST;
debug_r[94] <= AXI_S4_Stream_TVALID;
debug_r[95] <= AXI_S4_Stream_TREADY;
//debug_r[96] <= AXI_S_Stream_TDATA;
debug_r[104:97] <= AXI_S4_Stream_TKEEP;
debug_r[105] <= AXI_S4_Stream_TLAST;
debug_r2 <= debug_r;
end
assign data = debug_r2;
icon icon_inst(
.CONTROL0(control0),
.CONTROL1(control1)
);
vio vio_inst(
.CONTROL(control1),
.CLK(axi_clk),
.SYNC_OUT(vio_cmd)
);
ila_256 ila_256_inst(
.CONTROL(control0),
.CLK(axi_clk),
.TRIG0(data)
);
/* */
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:36:08 06/04/2015
// Design Name:
// Module Name: aesmain
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aesmain(
output [127:0] out,
output ready,
output [3:0] memadd,
input [127:0] in,
input [127:0] roundkey,
input decr,
input clk,
input reset
);
wire [127:0] outDec;
wire [127:0] outEnc;
wire [127:0] shftIn;
wire [127:0] shftInDec;
wire [127:0] shftInEnc;
wire [127:0] shftOut;
wire [127:0] mixIn;
wire [127:0] mixInDec;
wire [127:0] mixInEnc;
wire [127:0] mixOut;
wire [127:0] stateOut;
wire [127:0] stateOutEnc;
wire [127:0] stateOutDec;
wire [127:0] keyIn;
wire [127:0] keyInDec;
wire [127:0] keyInEnc;
wire [127:0] keyOut;
wire [127:0] subIn;
wire [127:0] subInDec;
wire [127:0] subInEnc;
wire [127:0] subOut;
wire [127:0] subaltout;
wire [127:0] mixaltout;
wire roundinselect;
wire suben;
wire shften;
wire mixen;
wire keyen;
reg [5:0] ctrlbits;
reg [4:0] memaddress; // Used for memory address
wire [4:0] memin;
wire [4:0] memaddressrev;
always @(posedge clk, posedge reset) begin
if(reset) begin
memaddress <= 5'b00000;
end
else if(memaddress == 5'b10111)
begin
memaddress <= 5'b00000;
end
else begin
memaddress <= memaddress + 1'b1;
end
end
assign memaddressrev = 5'b10111 - memaddress;
// Control Bit Selection Using Case
always @(*) begin
ctrlbits = 6'b000000;
if(decr) begin
case (memaddressrev)
5'b00000: ctrlbits = 6'b010000;
5'b00001: ctrlbits = 6'b000110;
5'b00010: ctrlbits = 6'b101001;
5'b00011: ctrlbits = 6'b000110;
5'b00100: ctrlbits = 6'b101001;
5'b00101: ctrlbits = 6'b000110;
5'b00110: ctrlbits = 6'b101001;
5'b00111: ctrlbits = 6'b000110;
5'b01000: ctrlbits = 6'b101001;
5'b01001: ctrlbits = 6'b000110;
5'b01010: ctrlbits = 6'b101001;
5'b01011: ctrlbits = 6'b000110;
5'b01100: ctrlbits = 6'b101001;
5'b01101: ctrlbits = 6'b000110;
5'b01110: ctrlbits = 6'b101001;
5'b01111: ctrlbits = 6'b000110;
5'b10000: ctrlbits = 6'b101001;
5'b10001: ctrlbits = 6'b000110;
5'b10010: ctrlbits = 6'b101001;
5'b10011: ctrlbits = 6'b000110;
5'b10100: ctrlbits = 6'b101000;
5'b10101: ctrlbits = 6'b000010;
default: ctrlbits = 6'b000000;
endcase
end
else begin
case (memaddress)
5'b00010: ctrlbits = 6'b100001;
5'b00011: ctrlbits = 6'b001100;
5'b00100: ctrlbits = 6'b100011;
5'b00101: ctrlbits = 6'b001100;
5'b00110: ctrlbits = 6'b100011;
5'b00111: ctrlbits = 6'b001100;
5'b01000: ctrlbits = 6'b100011;
5'b01001: ctrlbits = 6'b001100;
5'b01010: ctrlbits = 6'b100011;
5'b01011: ctrlbits = 6'b001100;
5'b01100: ctrlbits = 6'b100011;
5'b01101: ctrlbits = 6'b001100;
5'b01110: ctrlbits = 6'b100011;
5'b01111: ctrlbits = 6'b001100;
5'b10000: ctrlbits = 6'b100011;
5'b10001: ctrlbits = 6'b001100;
5'b10010: ctrlbits = 6'b100011;
5'b10011: ctrlbits = 6'b001100;
5'b10100: ctrlbits = 6'b100011;
5'b10101: ctrlbits = 6'b001100;
5'b10110: ctrlbits = 6'b010000;
default: ctrlbits = 6'b000000;
endcase
end
end
// Control Signals
assign roundinselect = ctrlbits[5];
assign ready = ctrlbits[4];
assign shften = (decr)?(ctrlbits[3]):(ctrlbits[2]);
assign suben = (decr)?(ctrlbits[2]):(ctrlbits[3]);
assign keyen = (decr)?(ctrlbits[1]):(ctrlbits[0]);
assign mixen = (decr)?(ctrlbits[0]):(ctrlbits[1]);
// Datapath Muxes and Datapath Units
assign subInDec = (shften)?(shftOut):(shftIn); // Dec
assign subInEnc = (roundinselect)?(stateOut):(in); // SubBytes Input Selector, either from previous round or external input.
assign subIn = (decr)?(subInDec):(subInEnc);
// Sub Bytes and Alternate Path Register
subBytesAll bytesub(.subOut(subOut), .subIn(subIn), .clk(clk), .inverse(decr) ); // For now just do encryption
regparam #(.SIZE(128)) subalternate (.Q(subaltout), .D(subIn), .clk(clk), .rst(reset), .clken(1'b1)); // Sub Bytes Not Used Register
assign shftInDec = (roundinselect)?(stateOut):(in); // Dec
assign shftInEnc = (suben)?(subOut):(subaltout);
assign shftIn = (decr)?(shftInDec):(shftInEnc);
// Row Shifter - Works both ways
shiftRows rowshifter (.shftOut(shftOut), .shftIn(shftIn), .inv(decr)); // For now just do encryption
assign mixInDec = (keyen)?(keyOut):(keyIn); // Dec
assign mixInEnc = (shften)?(shftOut):(shftIn);
assign mixIn = (decr)?(mixInDec):(mixInEnc);
// Mix Columns and Alternate Path Register
mixColumnsAll columnmixer(.mixOut(mixOut), .mixIn(mixIn), .clk(clk), .inverse(decr)); // For now just do encryption
regparam #(.SIZE(128)) mixalternate (.Q(mixaltout), .D(mixIn), .clk(clk), .rst(reset), .clken(1'b1)); // Mix Columns Not Used Register
assign keyInDec = (suben)?(subOut):(subaltout); // Dec
assign keyInEnc = (mixen)?(mixOut):(mixaltout);
assign keyIn = (decr)?(keyInDec):(keyInEnc);
// Key Adder - Basic XOR with 128 bits.
addKey keyadder(.keyedOut(keyOut), .keyedIn(keyIn), .key(roundkey)); // The same for encryption and decryption. Routing should be different.
assign stateOutDec = (mixen)?(mixOut):(mixaltout); // Dec
assign stateOutEnc = (keyen)?(keyOut):(keyIn);
assign stateOut = (decr)?(stateOutDec):(stateOutEnc);
assign memin = (decr)?(memaddressrev - 1'b1):(memaddress);
assign memadd = memin[4:1];
// Output Selector
assign outDec = mixaltout; // Dec
assign outEnc = keyOut;
assign out = (decr)?(outDec):(outEnc);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_2_V
`define SKY130_FD_SC_MS__DFRTP_2_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_2_V
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
//Date : Wed Jul 5 01:27:12 2017
//Host : saturn running 64-bit Ubuntu 16.10
//Command : generate_target fmrv32im_artya7.bd
//Design : fmrv32im_artya7
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "fmrv32im_artya7,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=fmrv32im_artya7,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=10,numReposBlks=9,numNonXlnxBlks=7,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_bram_cntlr_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "fmrv32im_artya7.hwdef" *)
module fmrv32im_artya7
(CLK100MHZ,
GPIO_i,
GPIO_o,
GPIO_ot,
UART_rx,
UART_tx);
input CLK100MHZ;
input [31:0]GPIO_i;
output [31:0]GPIO_o;
output [31:0]GPIO_ot;
input UART_rx;
output UART_tx;
wire CLK_1;
wire [0:0]High_dout;
wire [31:0]axi_lite_master_M_AXI_ARADDR;
wire [3:0]axi_lite_master_M_AXI_ARCACHE;
wire [2:0]axi_lite_master_M_AXI_ARPROT;
wire axi_lite_master_M_AXI_ARREADY;
wire axi_lite_master_M_AXI_ARVALID;
wire [31:0]axi_lite_master_M_AXI_AWADDR;
wire [3:0]axi_lite_master_M_AXI_AWCACHE;
wire [2:0]axi_lite_master_M_AXI_AWPROT;
wire axi_lite_master_M_AXI_AWREADY;
wire axi_lite_master_M_AXI_AWVALID;
wire axi_lite_master_M_AXI_BREADY;
wire [1:0]axi_lite_master_M_AXI_BRESP;
wire axi_lite_master_M_AXI_BVALID;
wire [31:0]axi_lite_master_M_AXI_RDATA;
wire axi_lite_master_M_AXI_RREADY;
wire [1:0]axi_lite_master_M_AXI_RRESP;
wire axi_lite_master_M_AXI_RVALID;
wire [31:0]axi_lite_master_M_AXI_WDATA;
wire axi_lite_master_M_AXI_WREADY;
wire [3:0]axi_lite_master_M_AXI_WSTRB;
wire axi_lite_master_M_AXI_WVALID;
wire [0:0]concat_dout;
wire [31:0]fmrv32im_core_PERIPHERAL_BUS_ADDR;
wire fmrv32im_core_PERIPHERAL_BUS_ENA;
wire [31:0]fmrv32im_core_PERIPHERAL_BUS_RDATA;
wire fmrv32im_core_PERIPHERAL_BUS_WAIT;
wire [31:0]fmrv32im_core_PERIPHERAL_BUS_WDATA;
wire [3:0]fmrv32im_core_PERIPHERAL_BUS_WSTB;
wire [31:0]uart_and_gpio_GPIO_I;
wire [31:0]uart_and_gpio_GPIO_O;
wire [31:0]uart_and_gpio_GPIO_OT;
wire uart_and_gpio_INTERRUPT;
wire uart_and_gpio_UART_RX;
wire uart_and_gpio_UART_TX;
assign CLK_1 = CLK100MHZ;
assign GPIO_o[31:0] = uart_and_gpio_GPIO_O;
assign GPIO_ot[31:0] = uart_and_gpio_GPIO_OT;
assign UART_tx = uart_and_gpio_UART_TX;
assign uart_and_gpio_GPIO_I = GPIO_i[31:0];
assign uart_and_gpio_UART_RX = UART_rx;
fmrv32im_artya7_xlconstant_0_0 High
(.dout(High_dout));
fmrv32im_artya7_fmrv32im_axilm_0_0 axi_lite_master
(.BUS_ADDR(fmrv32im_core_PERIPHERAL_BUS_ADDR),
.BUS_ENA(fmrv32im_core_PERIPHERAL_BUS_ENA),
.BUS_RDATA(fmrv32im_core_PERIPHERAL_BUS_RDATA),
.BUS_WAIT(fmrv32im_core_PERIPHERAL_BUS_WAIT),
.BUS_WDATA(fmrv32im_core_PERIPHERAL_BUS_WDATA),
.BUS_WSTB(fmrv32im_core_PERIPHERAL_BUS_WSTB),
.CLK(CLK_1),
.M_AXI_ARADDR(axi_lite_master_M_AXI_ARADDR),
.M_AXI_ARCACHE(axi_lite_master_M_AXI_ARCACHE),
.M_AXI_ARPROT(axi_lite_master_M_AXI_ARPROT),
.M_AXI_ARREADY(axi_lite_master_M_AXI_ARREADY),
.M_AXI_ARVALID(axi_lite_master_M_AXI_ARVALID),
.M_AXI_AWADDR(axi_lite_master_M_AXI_AWADDR),
.M_AXI_AWCACHE(axi_lite_master_M_AXI_AWCACHE),
.M_AXI_AWPROT(axi_lite_master_M_AXI_AWPROT),
.M_AXI_AWREADY(axi_lite_master_M_AXI_AWREADY),
.M_AXI_AWVALID(axi_lite_master_M_AXI_AWVALID),
.M_AXI_BREADY(axi_lite_master_M_AXI_BREADY),
.M_AXI_BRESP(axi_lite_master_M_AXI_BRESP),
.M_AXI_BVALID(axi_lite_master_M_AXI_BVALID),
.M_AXI_RDATA(axi_lite_master_M_AXI_RDATA),
.M_AXI_RREADY(axi_lite_master_M_AXI_RREADY),
.M_AXI_RRESP(axi_lite_master_M_AXI_RRESP),
.M_AXI_RVALID(axi_lite_master_M_AXI_RVALID),
.M_AXI_WDATA(axi_lite_master_M_AXI_WDATA),
.M_AXI_WREADY(axi_lite_master_M_AXI_WREADY),
.M_AXI_WSTRB(axi_lite_master_M_AXI_WSTRB),
.M_AXI_WVALID(axi_lite_master_M_AXI_WVALID),
.RST_N(High_dout));
fmrv32im_artya7_xlconcat_0_0 concat
(.In0(uart_and_gpio_INTERRUPT),
.dout(concat_dout));
fmrv32im_core_imp_14DVYUT fmrv32im_core
(.CLK(CLK_1),
.INT_IN(concat_dout),
.PERIPHERAL_bus_addr(fmrv32im_core_PERIPHERAL_BUS_ADDR),
.PERIPHERAL_bus_ena(fmrv32im_core_PERIPHERAL_BUS_ENA),
.PERIPHERAL_bus_rdata(fmrv32im_core_PERIPHERAL_BUS_RDATA),
.PERIPHERAL_bus_wait(fmrv32im_core_PERIPHERAL_BUS_WAIT),
.PERIPHERAL_bus_wdata(fmrv32im_core_PERIPHERAL_BUS_WDATA),
.PERIPHERAL_bus_wstb(fmrv32im_core_PERIPHERAL_BUS_WSTB),
.RD_REQ_req_mem_addr(1'b0),
.RD_REQ_req_mem_rdata(1'b0),
.RD_REQ_req_mem_we(1'b0),
.RD_REQ_req_ready(1'b0),
.RST_N(High_dout),
.WR_REQ_req_mem_addr(1'b0),
.WR_REQ_req_ready(1'b0));
fmrv32im_artya7_uart_and_gpio_0 uart_and_gpio
(.CLK(CLK_1),
.GPIO_I(uart_and_gpio_GPIO_I),
.GPIO_O(uart_and_gpio_GPIO_O),
.GPIO_OT(uart_and_gpio_GPIO_OT),
.INTERRUPT(uart_and_gpio_INTERRUPT),
.RST_N(High_dout),
.RXD(uart_and_gpio_UART_RX),
.S_AXI_ARADDR(axi_lite_master_M_AXI_ARADDR[15:0]),
.S_AXI_ARCACHE(axi_lite_master_M_AXI_ARCACHE),
.S_AXI_ARPROT(axi_lite_master_M_AXI_ARPROT),
.S_AXI_ARREADY(axi_lite_master_M_AXI_ARREADY),
.S_AXI_ARVALID(axi_lite_master_M_AXI_ARVALID),
.S_AXI_AWADDR(axi_lite_master_M_AXI_AWADDR[15:0]),
.S_AXI_AWCACHE(axi_lite_master_M_AXI_AWCACHE),
.S_AXI_AWPROT(axi_lite_master_M_AXI_AWPROT),
.S_AXI_AWREADY(axi_lite_master_M_AXI_AWREADY),
.S_AXI_AWVALID(axi_lite_master_M_AXI_AWVALID),
.S_AXI_BREADY(axi_lite_master_M_AXI_BREADY),
.S_AXI_BRESP(axi_lite_master_M_AXI_BRESP),
.S_AXI_BVALID(axi_lite_master_M_AXI_BVALID),
.S_AXI_RDATA(axi_lite_master_M_AXI_RDATA),
.S_AXI_RREADY(axi_lite_master_M_AXI_RREADY),
.S_AXI_RRESP(axi_lite_master_M_AXI_RRESP),
.S_AXI_RVALID(axi_lite_master_M_AXI_RVALID),
.S_AXI_WDATA(axi_lite_master_M_AXI_WDATA),
.S_AXI_WREADY(axi_lite_master_M_AXI_WREADY),
.S_AXI_WSTRB(axi_lite_master_M_AXI_WSTRB),
.S_AXI_WVALID(axi_lite_master_M_AXI_WVALID),
.TXD(uart_and_gpio_UART_TX));
endmodule
module fmrv32im_core_imp_14DVYUT
(CLK,
INT_IN,
PERIPHERAL_bus_addr,
PERIPHERAL_bus_ena,
PERIPHERAL_bus_rdata,
PERIPHERAL_bus_wait,
PERIPHERAL_bus_wdata,
PERIPHERAL_bus_wstb,
RD_REQ_req_addr,
RD_REQ_req_len,
RD_REQ_req_mem_addr,
RD_REQ_req_mem_rdata,
RD_REQ_req_mem_we,
RD_REQ_req_ready,
RD_REQ_req_start,
RST_N,
WR_REQ_req_addr,
WR_REQ_req_len,
WR_REQ_req_mem_addr,
WR_REQ_req_mem_wdata,
WR_REQ_req_ready,
WR_REQ_req_start);
input CLK;
input [0:0]INT_IN;
output [31:0]PERIPHERAL_bus_addr;
output PERIPHERAL_bus_ena;
input [31:0]PERIPHERAL_bus_rdata;
input PERIPHERAL_bus_wait;
output [31:0]PERIPHERAL_bus_wdata;
output [3:0]PERIPHERAL_bus_wstb;
output RD_REQ_req_addr;
output RD_REQ_req_len;
input RD_REQ_req_mem_addr;
input RD_REQ_req_mem_rdata;
input RD_REQ_req_mem_we;
input RD_REQ_req_ready;
output RD_REQ_req_start;
input RST_N;
output WR_REQ_req_addr;
output WR_REQ_req_len;
input WR_REQ_req_mem_addr;
output WR_REQ_req_mem_wdata;
input WR_REQ_req_ready;
output WR_REQ_req_start;
wire CLK_1;
wire [31:0]Conn1_REQ_ADDR;
wire [15:0]Conn1_REQ_LEN;
wire Conn1_REQ_MEM_ADDR;
wire Conn1_REQ_MEM_RDATA;
wire Conn1_REQ_MEM_WE;
wire Conn1_REQ_READY;
wire Conn1_REQ_START;
wire [31:0]Conn2_REQ_ADDR;
wire [15:0]Conn2_REQ_LEN;
wire Conn2_REQ_MEM_ADDR;
wire [31:0]Conn2_REQ_MEM_WDATA;
wire Conn2_REQ_READY;
wire Conn2_REQ_START;
wire [31:0]Conn3_BUS_ADDR;
wire Conn3_BUS_ENA;
wire [31:0]Conn3_BUS_RDATA;
wire Conn3_BUS_WAIT;
wire [31:0]Conn3_BUS_WDATA;
wire [3:0]Conn3_BUS_WSTB;
wire [0:0]INT_IN_1;
wire RST_N_1;
wire [31:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_ADDR;
wire dbussel_upgraded_ipi_C_MEM_BUS_MEM_BADMEM_EXCPT;
wire dbussel_upgraded_ipi_C_MEM_BUS_MEM_ENA;
wire [31:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_RDATA;
wire dbussel_upgraded_ipi_C_MEM_BUS_MEM_WAIT;
wire [31:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_WDATA;
wire [3:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_WSTB;
wire [3:0]dbussel_upgraded_ipi_PLIC_BUS_ADDR;
wire [31:0]dbussel_upgraded_ipi_PLIC_BUS_RDATA;
wire [31:0]dbussel_upgraded_ipi_PLIC_BUS_WDATA;
wire dbussel_upgraded_ipi_PLIC_BUS_WE;
wire [3:0]dbussel_upgraded_ipi_TIMER_BUS_ADDR;
wire [31:0]dbussel_upgraded_ipi_TIMER_BUS_RDATA;
wire [31:0]dbussel_upgraded_ipi_TIMER_BUS_WDATA;
wire dbussel_upgraded_ipi_TIMER_BUS_WE;
wire [31:0]fmrv32im_D_MEM_BUS_MEM_ADDR;
wire fmrv32im_D_MEM_BUS_MEM_BADMEM_EXCPT;
wire fmrv32im_D_MEM_BUS_MEM_ENA;
wire [31:0]fmrv32im_D_MEM_BUS_MEM_RDATA;
wire fmrv32im_D_MEM_BUS_MEM_WAIT;
wire [31:0]fmrv32im_D_MEM_BUS_MEM_WDATA;
wire [3:0]fmrv32im_D_MEM_BUS_MEM_WSTB;
wire [31:0]fmrv32im_I_MEM_BUS_MEM_ADDR;
wire fmrv32im_I_MEM_BUS_MEM_BADMEM_EXCPT;
wire fmrv32im_I_MEM_BUS_MEM_ENA;
wire [31:0]fmrv32im_I_MEM_BUS_MEM_RDATA;
wire fmrv32im_I_MEM_BUS_MEM_WAIT;
wire fmrv32im_plic_0_INT_OUT;
wire timer_EXPIRED;
assign CLK_1 = CLK;
assign Conn1_REQ_MEM_ADDR = RD_REQ_req_mem_addr;
assign Conn1_REQ_MEM_RDATA = RD_REQ_req_mem_rdata;
assign Conn1_REQ_MEM_WE = RD_REQ_req_mem_we;
assign Conn1_REQ_READY = RD_REQ_req_ready;
assign Conn2_REQ_MEM_ADDR = WR_REQ_req_mem_addr;
assign Conn2_REQ_READY = WR_REQ_req_ready;
assign Conn3_BUS_RDATA = PERIPHERAL_bus_rdata[31:0];
assign Conn3_BUS_WAIT = PERIPHERAL_bus_wait;
assign INT_IN_1 = INT_IN[0];
assign PERIPHERAL_bus_addr[31:0] = Conn3_BUS_ADDR;
assign PERIPHERAL_bus_ena = Conn3_BUS_ENA;
assign PERIPHERAL_bus_wdata[31:0] = Conn3_BUS_WDATA;
assign PERIPHERAL_bus_wstb[3:0] = Conn3_BUS_WSTB;
assign RD_REQ_req_addr = Conn1_REQ_ADDR[0];
assign RD_REQ_req_len = Conn1_REQ_LEN[0];
assign RD_REQ_req_start = Conn1_REQ_START;
assign RST_N_1 = RST_N;
assign WR_REQ_req_addr = Conn2_REQ_ADDR[0];
assign WR_REQ_req_len = Conn2_REQ_LEN[0];
assign WR_REQ_req_mem_wdata = Conn2_REQ_MEM_WDATA[0];
assign WR_REQ_req_start = Conn2_REQ_START;
fmrv32im_artya7_fmrv32im_cache_0_0 cache
(.CLK(CLK_1),
.D_MEM_ADDR(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ADDR),
.D_MEM_BADMEM_EXCPT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_BADMEM_EXCPT),
.D_MEM_ENA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ENA),
.D_MEM_RDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_RDATA),
.D_MEM_WAIT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WAIT),
.D_MEM_WDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WDATA),
.D_MEM_WSTB(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WSTB),
.I_MEM_ADDR(fmrv32im_I_MEM_BUS_MEM_ADDR),
.I_MEM_BADMEM_EXCPT(fmrv32im_I_MEM_BUS_MEM_BADMEM_EXCPT),
.I_MEM_ENA(fmrv32im_I_MEM_BUS_MEM_ENA),
.I_MEM_RDATA(fmrv32im_I_MEM_BUS_MEM_RDATA),
.I_MEM_WAIT(fmrv32im_I_MEM_BUS_MEM_WAIT),
.RD_REQ_ADDR(Conn1_REQ_ADDR),
.RD_REQ_LEN(Conn1_REQ_LEN),
.RD_REQ_MEM_ADDR({Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR}),
.RD_REQ_MEM_RDATA({Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA}),
.RD_REQ_MEM_WE(Conn1_REQ_MEM_WE),
.RD_REQ_READY(Conn1_REQ_READY),
.RD_REQ_START(Conn1_REQ_START),
.RST_N(RST_N_1),
.WR_REQ_ADDR(Conn2_REQ_ADDR),
.WR_REQ_LEN(Conn2_REQ_LEN),
.WR_REQ_MEM_ADDR({Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR}),
.WR_REQ_MEM_WDATA(Conn2_REQ_MEM_WDATA),
.WR_REQ_READY(Conn2_REQ_READY),
.WR_REQ_START(Conn2_REQ_START));
fmrv32im_artya7_dbussel_upgraded_ipi_0 dbussel
(.C_MEM_ADDR(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ADDR),
.C_MEM_BADMEM_EXCPT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_BADMEM_EXCPT),
.C_MEM_ENA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ENA),
.C_MEM_RDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_RDATA),
.C_MEM_WAIT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WAIT),
.C_MEM_WDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WDATA),
.C_MEM_WSTB(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WSTB),
.D_MEM_ADDR(fmrv32im_D_MEM_BUS_MEM_ADDR),
.D_MEM_BADMEM_EXCPT(fmrv32im_D_MEM_BUS_MEM_BADMEM_EXCPT),
.D_MEM_ENA(fmrv32im_D_MEM_BUS_MEM_ENA),
.D_MEM_RDATA(fmrv32im_D_MEM_BUS_MEM_RDATA),
.D_MEM_WAIT(fmrv32im_D_MEM_BUS_MEM_WAIT),
.D_MEM_WDATA(fmrv32im_D_MEM_BUS_MEM_WDATA),
.D_MEM_WSTB(fmrv32im_D_MEM_BUS_MEM_WSTB),
.PERIPHERAL_BUS_ADDR(Conn3_BUS_ADDR),
.PERIPHERAL_BUS_ENA(Conn3_BUS_ENA),
.PERIPHERAL_BUS_RDATA(Conn3_BUS_RDATA),
.PERIPHERAL_BUS_WAIT(Conn3_BUS_WAIT),
.PERIPHERAL_BUS_WDATA(Conn3_BUS_WDATA),
.PERIPHERAL_BUS_WSTB(Conn3_BUS_WSTB),
.PLIC_BUS_ADDR(dbussel_upgraded_ipi_PLIC_BUS_ADDR),
.PLIC_BUS_RDATA(dbussel_upgraded_ipi_PLIC_BUS_RDATA),
.PLIC_BUS_WDATA(dbussel_upgraded_ipi_PLIC_BUS_WDATA),
.PLIC_BUS_WE(dbussel_upgraded_ipi_PLIC_BUS_WE),
.TIMER_BUS_ADDR(dbussel_upgraded_ipi_TIMER_BUS_ADDR),
.TIMER_BUS_RDATA(dbussel_upgraded_ipi_TIMER_BUS_RDATA),
.TIMER_BUS_WDATA(dbussel_upgraded_ipi_TIMER_BUS_WDATA),
.TIMER_BUS_WE(dbussel_upgraded_ipi_TIMER_BUS_WE));
fmrv32im_artya7_fmrv32im_0 fmrv32im
(.CLK(CLK_1),
.D_MEM_ADDR(fmrv32im_D_MEM_BUS_MEM_ADDR),
.D_MEM_BADMEM_EXCPT(fmrv32im_D_MEM_BUS_MEM_BADMEM_EXCPT),
.D_MEM_ENA(fmrv32im_D_MEM_BUS_MEM_ENA),
.D_MEM_RDATA(fmrv32im_D_MEM_BUS_MEM_RDATA),
.D_MEM_WAIT(fmrv32im_D_MEM_BUS_MEM_WAIT),
.D_MEM_WDATA(fmrv32im_D_MEM_BUS_MEM_WDATA),
.D_MEM_WSTB(fmrv32im_D_MEM_BUS_MEM_WSTB),
.EXT_INTERRUPT(fmrv32im_plic_0_INT_OUT),
.I_MEM_ADDR(fmrv32im_I_MEM_BUS_MEM_ADDR),
.I_MEM_BADMEM_EXCPT(fmrv32im_I_MEM_BUS_MEM_BADMEM_EXCPT),
.I_MEM_ENA(fmrv32im_I_MEM_BUS_MEM_ENA),
.I_MEM_RDATA(fmrv32im_I_MEM_BUS_MEM_RDATA),
.I_MEM_WAIT(fmrv32im_I_MEM_BUS_MEM_WAIT),
.RST_N(RST_N_1),
.TIMER_EXPIRED(timer_EXPIRED));
fmrv32im_artya7_fmrv32im_plic_0_1 plic
(.BUS_ADDR(dbussel_upgraded_ipi_PLIC_BUS_ADDR),
.BUS_RDATA(dbussel_upgraded_ipi_PLIC_BUS_RDATA),
.BUS_WDATA(dbussel_upgraded_ipi_PLIC_BUS_WDATA),
.BUS_WE(dbussel_upgraded_ipi_PLIC_BUS_WE),
.CLK(CLK_1),
.INT_IN(INT_IN_1),
.INT_OUT(fmrv32im_plic_0_INT_OUT),
.RST_N(RST_N_1));
fmrv32im_artya7_fmrv32im_timer_0_0 timer
(.BUS_ADDR(dbussel_upgraded_ipi_TIMER_BUS_ADDR),
.BUS_RDATA(dbussel_upgraded_ipi_TIMER_BUS_RDATA),
.BUS_WDATA(dbussel_upgraded_ipi_TIMER_BUS_WDATA),
.BUS_WE(dbussel_upgraded_ipi_TIMER_BUS_WE),
.CLK(CLK_1),
.EXPIRED(timer_EXPIRED),
.RST_N(RST_N_1));
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:59:04 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1,
OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, DP_OP_15J66_123_7955_n11,
DP_OP_15J66_123_7955_n10, DP_OP_15J66_123_7955_n9,
DP_OP_15J66_123_7955_n8, DP_OP_15J66_123_7955_n7,
DP_OP_15J66_123_7955_n6, intadd_72_B_42_, intadd_72_B_41_,
intadd_72_B_40_, intadd_72_B_39_, intadd_72_B_38_, intadd_72_B_37_,
intadd_72_B_36_, intadd_72_B_35_, intadd_72_B_34_, intadd_72_B_33_,
intadd_72_B_32_, intadd_72_B_31_, intadd_72_B_30_, intadd_72_B_29_,
intadd_72_B_28_, intadd_72_B_27_, intadd_72_B_26_, intadd_72_B_25_,
intadd_72_B_24_, intadd_72_B_23_, intadd_72_B_22_, intadd_72_B_21_,
intadd_72_B_20_, intadd_72_B_19_, intadd_72_B_18_, intadd_72_B_17_,
intadd_72_B_16_, intadd_72_B_15_, intadd_72_B_14_, intadd_72_B_13_,
intadd_72_B_12_, intadd_72_B_11_, intadd_72_B_10_, intadd_72_B_9_,
intadd_72_B_8_, intadd_72_B_7_, intadd_72_B_6_, intadd_72_B_5_,
intadd_72_B_4_, intadd_72_B_3_, intadd_72_B_2_, intadd_72_B_1_,
intadd_72_B_0_, intadd_72_CI, intadd_72_SUM_42_, intadd_72_SUM_41_,
intadd_72_SUM_40_, intadd_72_SUM_39_, intadd_72_SUM_38_,
intadd_72_SUM_37_, intadd_72_SUM_36_, intadd_72_SUM_35_,
intadd_72_SUM_34_, intadd_72_SUM_33_, intadd_72_SUM_32_,
intadd_72_SUM_31_, intadd_72_SUM_30_, intadd_72_SUM_29_,
intadd_72_SUM_28_, intadd_72_SUM_27_, intadd_72_SUM_26_,
intadd_72_SUM_25_, intadd_72_SUM_24_, intadd_72_SUM_23_,
intadd_72_SUM_22_, intadd_72_SUM_21_, intadd_72_SUM_20_,
intadd_72_SUM_19_, intadd_72_SUM_18_, intadd_72_SUM_17_,
intadd_72_SUM_16_, intadd_72_SUM_15_, intadd_72_SUM_14_,
intadd_72_SUM_13_, intadd_72_SUM_12_, intadd_72_SUM_11_,
intadd_72_SUM_10_, intadd_72_SUM_9_, intadd_72_SUM_8_,
intadd_72_SUM_7_, intadd_72_SUM_6_, intadd_72_SUM_5_,
intadd_72_SUM_4_, intadd_72_SUM_3_, intadd_72_SUM_2_,
intadd_72_SUM_1_, intadd_72_SUM_0_, intadd_72_n43, intadd_72_n42,
intadd_72_n41, intadd_72_n40, intadd_72_n39, intadd_72_n38,
intadd_72_n37, intadd_72_n36, intadd_72_n35, intadd_72_n34,
intadd_72_n33, intadd_72_n32, intadd_72_n31, intadd_72_n30,
intadd_72_n29, intadd_72_n28, intadd_72_n27, intadd_72_n26,
intadd_72_n25, intadd_72_n24, intadd_72_n23, intadd_72_n22,
intadd_72_n21, intadd_72_n20, intadd_72_n19, intadd_72_n18,
intadd_72_n17, intadd_72_n16, intadd_72_n15, intadd_72_n14,
intadd_72_n13, intadd_72_n12, intadd_72_n11, intadd_72_n10,
intadd_72_n9, intadd_72_n8, intadd_72_n7, intadd_72_n6, intadd_72_n5,
intadd_72_n4, intadd_72_n3, intadd_72_n2, intadd_72_n1, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2660, n2661, n2662, n2663, n2664, n2665, n2666,
n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676,
n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686,
n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696,
n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2758,
n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768,
n2769, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [40:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1791), .CK(clk), .RN(n3238), .QN(
n1864) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n1786), .CK(clk), .RN(n3244), .Q(
Shift_reg_FLAGS_7[1]) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n1785), .CK(clk), .RN(n3239), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1720), .CK(clk), .RN(n3244), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n3236), .CK(clk), .RN(n3243), .Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1634), .CK(clk), .RN(n1803), .QN(
n1809) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1633), .CK(clk), .RN(n1803), .QN(
n1810) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1625), .CK(clk), .RN(n3237), .QN(
n1814) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1623), .CK(clk), .RN(n3245), .QN(
n1804) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1622), .CK(clk), .RN(n1796), .QN(
n1806) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1620), .CK(clk), .RN(n3244), .QN(
n1805) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1618), .CK(clk), .RN(n3237), .QN(
n1819) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1617), .CK(clk), .RN(n3238), .QN(
n1807) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1616), .CK(clk), .RN(n3244), .QN(
n1815) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1615), .CK(clk), .RN(n3239), .QN(
n1817) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1613), .CK(clk), .RN(n1796), .QN(
n1816) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1603), .CK(clk), .RN(n1801), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1646), .CK(clk), .RN(n1821), .QN(
n1811) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1644), .CK(clk), .RN(n3245), .QN(
n1812) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1643), .CK(clk), .RN(n3250), .QN(
n1813) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(n3248),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(n3247),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(n3248),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(n1801),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(n1803),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1588), .CK(clk), .RN(n3266), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1587), .CK(clk), .RN(n3272), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1586), .CK(clk), .RN(n3270), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1585), .CK(clk), .RN(n1801), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1584), .CK(clk), .RN(n3253), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1583), .CK(clk), .RN(n3261), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1582), .CK(clk), .RN(n3268), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1581), .CK(clk), .RN(n3275), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1580), .CK(clk), .RN(n1801), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1579), .CK(clk), .RN(n3254), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1578), .CK(clk), .RN(n3256), .Q(
final_result_ieee[62]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1577), .CK(clk), .RN(n1803), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1576), .CK(clk), .RN(n1799), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1575), .CK(clk), .RN(n1802), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1574), .CK(clk), .RN(n1801), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1573), .CK(clk), .RN(n1803), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1572), .CK(clk), .RN(n1803), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1571), .CK(clk), .RN(n1800), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1570), .CK(clk), .RN(n3245), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1569), .CK(clk), .RN(n1799), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1568), .CK(clk), .RN(n1802), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1567), .CK(clk), .RN(n3250), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1566), .CK(clk), .RN(n3252), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1565), .CK(clk), .RN(n3246), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1564), .CK(clk), .RN(n3247), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1563), .CK(clk), .RN(n3241), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1562), .CK(clk), .RN(n3250), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1561), .CK(clk), .RN(n3242), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1560), .CK(clk), .RN(n3241), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1559), .CK(clk), .RN(n1821), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1558), .CK(clk), .RN(n3246), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1557), .CK(clk), .RN(n3247), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1556), .CK(clk), .RN(n3252), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1555), .CK(clk), .RN(n3242), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1554), .CK(clk), .RN(n3249), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1553), .CK(clk), .RN(n3248), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1552), .CK(clk), .RN(n3252), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1551), .CK(clk), .RN(n3246), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1550), .CK(clk), .RN(n3247), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1549), .CK(clk), .RN(n3241), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1548), .CK(clk), .RN(n3250), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1547), .CK(clk), .RN(n3245), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1546), .CK(clk), .RN(n3241), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1545), .CK(clk), .RN(n3246), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1544), .CK(clk), .RN(n3247), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1543), .CK(clk), .RN(n3242), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1542), .CK(clk), .RN(n3249), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1541), .CK(clk), .RN(n3248), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1540), .CK(clk), .RN(n3246), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1539), .CK(clk), .RN(n3247), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1538), .CK(clk), .RN(n3248), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1537), .CK(clk), .RN(n3249), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1536), .CK(clk), .RN(n3242), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1535), .CK(clk), .RN(n1821), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1534), .CK(clk), .RN(n3246), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1533), .CK(clk), .RN(n3247), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1532), .CK(clk), .RN(n3252), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1531), .CK(clk), .RN(n3249), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1530), .CK(clk), .RN(n3240), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1529), .CK(clk), .RN(n1801), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1528), .CK(clk), .RN(n3241), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1527), .CK(clk), .RN(n3239), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1526), .CK(clk), .RN(n3245), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1519), .CK(clk), .RN(n3243), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1518), .CK(clk), .RN(n3240), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1517), .CK(clk), .RN(n3279), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1516), .CK(clk), .RN(n3237), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1515), .CK(clk), .RN(n3242), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1514), .CK(clk), .RN(n3248), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1513), .CK(clk), .RN(n1821), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1512), .CK(clk), .RN(n3251), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1511), .CK(clk), .RN(n3237), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1510), .CK(clk), .RN(n1821), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1509), .CK(clk), .RN(n3241), .Q(
DMP_SFG[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1508), .CK(clk), .RN(n3238), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1507), .CK(clk), .RN(n3237), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1506), .CK(clk), .RN(n1803), .Q(
DMP_SFG[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1505), .CK(clk), .RN(n3241), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1504), .CK(clk), .RN(n3245), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1503), .CK(clk), .RN(n3248), .Q(
DMP_SFG[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1502), .CK(clk), .RN(n3240), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1501), .CK(clk), .RN(n3252), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1500), .CK(clk), .RN(n1803), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1499), .CK(clk), .RN(n3252), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1498), .CK(clk), .RN(n3250), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1497), .CK(clk), .RN(n3241), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1496), .CK(clk), .RN(n3251), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1495), .CK(clk), .RN(n3277), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1494), .CK(clk), .RN(n3277), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1493), .CK(clk), .RN(n1802), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1492), .CK(clk), .RN(n1802), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1491), .CK(clk), .RN(n1802), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1490), .CK(clk), .RN(n1802), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1489), .CK(clk), .RN(n1802), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1487), .CK(clk), .RN(n1802), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1486), .CK(clk), .RN(n1802), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1484), .CK(clk), .RN(n1802), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1483), .CK(clk), .RN(n3259), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1482), .CK(clk), .RN(n3259), .Q(
DMP_SFG[9]), .QN(n3074) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1481), .CK(clk), .RN(n1796), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1480), .CK(clk), .RN(n1796), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1479), .CK(clk), .RN(n1796), .Q(
DMP_SFG[10]), .QN(n3075) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1478), .CK(clk), .RN(n1796), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1477), .CK(clk), .RN(n1796), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1476), .CK(clk), .RN(n1796), .Q(
DMP_SFG[11]), .QN(n3077) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1475), .CK(clk), .RN(n1796), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1474), .CK(clk), .RN(n1796), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1473), .CK(clk), .RN(n1796), .Q(
DMP_SFG[12]), .QN(n3076) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1472), .CK(clk), .RN(n1796), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1471), .CK(clk), .RN(n3277), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1470), .CK(clk), .RN(n3276), .Q(
DMP_SFG[13]), .QN(n3079) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1469), .CK(clk), .RN(n3240), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1468), .CK(clk), .RN(n3277), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1467), .CK(clk), .RN(n3276), .Q(
DMP_SFG[14]), .QN(n3078) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1466), .CK(clk), .RN(n3240), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1465), .CK(clk), .RN(n3277), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1464), .CK(clk), .RN(n3276), .Q(
DMP_SFG[15]), .QN(n3081) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1463), .CK(clk), .RN(n3240), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1462), .CK(clk), .RN(n3240), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1461), .CK(clk), .RN(n3277), .Q(
DMP_SFG[16]), .QN(n3080) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1460), .CK(clk), .RN(n3276), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1459), .CK(clk), .RN(n3278), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1458), .CK(clk), .RN(n3262), .Q(
DMP_SFG[17]), .QN(n3082) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1457), .CK(clk), .RN(n3257), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1456), .CK(clk), .RN(n3279), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1455), .CK(clk), .RN(n3270), .Q(
DMP_SFG[18]), .QN(n3085) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1454), .CK(clk), .RN(n3253), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1453), .CK(clk), .RN(n3257), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1452), .CK(clk), .RN(n3258), .Q(
DMP_SFG[19]), .QN(n3084) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1451), .CK(clk), .RN(n3262), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1450), .CK(clk), .RN(n1801), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1449), .CK(clk), .RN(n3272), .Q(
DMP_SFG[20]), .QN(n3088) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1448), .CK(clk), .RN(n3258), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1447), .CK(clk), .RN(n3272), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1446), .CK(clk), .RN(n3261), .Q(
DMP_SFG[21]), .QN(n3087) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1445), .CK(clk), .RN(n3273), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1444), .CK(clk), .RN(n3262), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1443), .CK(clk), .RN(n3274), .Q(
DMP_SFG[22]), .QN(n3090) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1442), .CK(clk), .RN(n3253), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1441), .CK(clk), .RN(n3256), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1440), .CK(clk), .RN(n3258), .Q(
DMP_SFG[23]), .QN(n3089) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1439), .CK(clk), .RN(n3273), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1438), .CK(clk), .RN(n1799), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1437), .CK(clk), .RN(n3269), .Q(
DMP_SFG[24]), .QN(n3093) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1436), .CK(clk), .RN(n1800), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1435), .CK(clk), .RN(n3278), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1434), .CK(clk), .RN(n3266), .Q(
DMP_SFG[25]), .QN(n3092) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1433), .CK(clk), .RN(n3275), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1432), .CK(clk), .RN(n3253), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1431), .CK(clk), .RN(n3256), .Q(
DMP_SFG[26]), .QN(n3095) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1430), .CK(clk), .RN(n3261), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1429), .CK(clk), .RN(n3253), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1428), .CK(clk), .RN(n3269), .Q(
DMP_SFG[27]), .QN(n3098) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1427), .CK(clk), .RN(n3254), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1426), .CK(clk), .RN(n3262), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1425), .CK(clk), .RN(n3270), .Q(
DMP_SFG[28]), .QN(n3097) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1424), .CK(clk), .RN(n3268), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1423), .CK(clk), .RN(n3271), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1422), .CK(clk), .RN(n3264), .Q(
DMP_SFG[29]), .QN(n3100) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n3255), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n3255), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1419), .CK(clk), .RN(n3255), .Q(
DMP_SFG[30]), .QN(n3099) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1418), .CK(clk), .RN(n3255), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1417), .CK(clk), .RN(n3255), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1416), .CK(clk), .RN(n3255), .Q(
DMP_SFG[31]), .QN(n3102) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1415), .CK(clk), .RN(n3255), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1414), .CK(clk), .RN(n3255), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1413), .CK(clk), .RN(n3255), .Q(
DMP_SFG[32]), .QN(n3101) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1412), .CK(clk), .RN(n3255), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1411), .CK(clk), .RN(n3271), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1410), .CK(clk), .RN(n3271), .Q(
DMP_SFG[33]), .QN(n3106) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1409), .CK(clk), .RN(n3277), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1408), .CK(clk), .RN(n3259), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1407), .CK(clk), .RN(n3264), .Q(
DMP_SFG[34]), .QN(n3105) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1406), .CK(clk), .RN(n3277), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1405), .CK(clk), .RN(n3271), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1404), .CK(clk), .RN(n3276), .Q(
DMP_SFG[35]), .QN(n3110) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1403), .CK(clk), .RN(n3267), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1402), .CK(clk), .RN(n3267), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1401), .CK(clk), .RN(n3277), .Q(
DMP_SFG[36]), .QN(n3136) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1400), .CK(clk), .RN(n3267), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1399), .CK(clk), .RN(n3270), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1398), .CK(clk), .RN(n3257), .Q(
DMP_SFG[37]), .QN(n3135) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1397), .CK(clk), .RN(n3261), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1396), .CK(clk), .RN(n3278), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1395), .CK(clk), .RN(n3275), .Q(
DMP_SFG[38]), .QN(n3148) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1394), .CK(clk), .RN(n3257), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1393), .CK(clk), .RN(n3279), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1392), .CK(clk), .RN(n1801), .Q(
DMP_SFG[39]), .QN(n3147) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1391), .CK(clk), .RN(n1799), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1390), .CK(clk), .RN(n3272), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1389), .CK(clk), .RN(n3258), .Q(
DMP_SFG[40]), .QN(n3156) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1388), .CK(clk), .RN(n3240), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1387), .CK(clk), .RN(n3256), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1386), .CK(clk), .RN(n3266), .Q(
DMP_SFG[41]), .QN(n3155) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1385), .CK(clk), .RN(n3273), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1384), .CK(clk), .RN(n3278), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1383), .CK(clk), .RN(n3262), .Q(
DMP_SFG[42]), .QN(n3174) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1382), .CK(clk), .RN(n1799), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1381), .CK(clk), .RN(n3272), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1380), .CK(clk), .RN(n3254), .Q(
DMP_SFG[43]), .QN(n3173) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1379), .CK(clk), .RN(n3273), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1378), .CK(clk), .RN(n3275), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1377), .CK(clk), .RN(n1803), .Q(
DMP_SFG[44]), .QN(n3184) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1376), .CK(clk), .RN(n1800), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1375), .CK(clk), .RN(n3256), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1374), .CK(clk), .RN(n3258), .Q(
DMP_SFG[45]), .QN(n3212) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1373), .CK(clk), .RN(n3270), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1372), .CK(clk), .RN(n3268), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1371), .CK(clk), .RN(n3275), .Q(
DMP_SFG[46]), .QN(n3211) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1370), .CK(clk), .RN(n3266), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1369), .CK(clk), .RN(n1799), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1368), .CK(clk), .RN(n1796), .Q(
DMP_SFG[47]), .QN(n3219) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1367), .CK(clk), .RN(n3262), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1366), .CK(clk), .RN(n3261), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1365), .CK(clk), .RN(n3257), .Q(
DMP_SFG[48]), .QN(n3218) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1364), .CK(clk), .RN(n1799), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1363), .CK(clk), .RN(n1801), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1362), .CK(clk), .RN(n3270), .Q(
DMP_SFG[49]), .QN(n3222) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1361), .CK(clk), .RN(n3256), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1360), .CK(clk), .RN(n3254), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1359), .CK(clk), .RN(n3274), .Q(
DMP_SFG[50]), .QN(n3221) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1358), .CK(clk), .RN(n3275), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1357), .CK(clk), .RN(n3268), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1356), .CK(clk), .RN(n3279), .Q(
DMP_SFG[51]), .QN(n3227) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1355), .CK(clk), .RN(n1801), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1354), .CK(clk), .RN(n3253), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1353), .CK(clk), .RN(n3268), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1352), .CK(clk), .RN(n3261), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1350), .CK(clk), .RN(n3271), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1349), .CK(clk), .RN(n3264), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1348), .CK(clk), .RN(n3244), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1347), .CK(clk), .RN(n3240), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1345), .CK(clk), .RN(n3267), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1344), .CK(clk), .RN(n3276), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1343), .CK(clk), .RN(n3259), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1342), .CK(clk), .RN(n3259), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1340), .CK(clk), .RN(n3255), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1339), .CK(clk), .RN(n3267), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1338), .CK(clk), .RN(n3264), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1337), .CK(clk), .RN(n3267), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1335), .CK(clk), .RN(n3253), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1334), .CK(clk), .RN(n3260), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1333), .CK(clk), .RN(n3258), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1332), .CK(clk), .RN(n3245), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1330), .CK(clk), .RN(n3261), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1329), .CK(clk), .RN(n3280), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1328), .CK(clk), .RN(n1800), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1327), .CK(clk), .RN(n3265), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1325), .CK(clk), .RN(n3262), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1324), .CK(clk), .RN(n3260), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1323), .CK(clk), .RN(n3270), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1322), .CK(clk), .RN(n3250), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1320), .CK(clk), .RN(n3259), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1319), .CK(clk), .RN(n3255), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1318), .CK(clk), .RN(n3244), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1317), .CK(clk), .RN(n3259), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1315), .CK(clk), .RN(n3255), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1314), .CK(clk), .RN(n3244), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1313), .CK(clk), .RN(n3259), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1312), .CK(clk), .RN(n3255), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1310), .CK(clk), .RN(n3244), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1309), .CK(clk), .RN(n3259), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1308), .CK(clk), .RN(n3255), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1307), .CK(clk), .RN(n3244), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1305), .CK(clk), .RN(n3280), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1304), .CK(clk), .RN(n3260), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1303), .CK(clk), .RN(n3264), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1302), .CK(clk), .RN(n3242), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1300), .CK(clk), .RN(n3280), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1298), .CK(clk), .RN(n3260), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1296), .CK(clk), .RN(n3259), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1294), .CK(clk), .RN(n3245), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1292), .CK(clk), .RN(n3268), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1290), .CK(clk), .RN(n3262), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1288), .CK(clk), .RN(n3274), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1286), .CK(clk), .RN(n1799), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1284), .CK(clk), .RN(n3257), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n3254), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1280), .CK(clk), .RN(n3254), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1278), .CK(clk), .RN(n1800), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1276), .CK(clk), .RN(n3274), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1274), .CK(clk), .RN(n3258), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1272), .CK(clk), .RN(n1800), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1270), .CK(clk), .RN(n3272), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1268), .CK(clk), .RN(n3269), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1266), .CK(clk), .RN(n3263), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1264), .CK(clk), .RN(n3263), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1262), .CK(clk), .RN(n3263), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1260), .CK(clk), .RN(n3263), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1258), .CK(clk), .RN(n3263), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1256), .CK(clk), .RN(n3264), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1254), .CK(clk), .RN(n3255), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1252), .CK(clk), .RN(n3264), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1250), .CK(clk), .RN(n3277), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1248), .CK(clk), .RN(n3255), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1246), .CK(clk), .RN(n3264), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1244), .CK(clk), .RN(n3272), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1242), .CK(clk), .RN(n3257), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1240), .CK(clk), .RN(n3261), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1238), .CK(clk), .RN(n3253), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1236), .CK(clk), .RN(n3270), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1234), .CK(clk), .RN(n3278), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1232), .CK(clk), .RN(n3280), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1230), .CK(clk), .RN(n3277), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1228), .CK(clk), .RN(n3280), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1226), .CK(clk), .RN(n3265), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1224), .CK(clk), .RN(n3265), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1222), .CK(clk), .RN(n3265), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1220), .CK(clk), .RN(n3260), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1218), .CK(clk), .RN(n3280), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1216), .CK(clk), .RN(n3250), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1214), .CK(clk), .RN(n3271), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1212), .CK(clk), .RN(n1865), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1210), .CK(clk), .RN(n3260), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1208), .CK(clk), .RN(n3268), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1206), .CK(clk), .RN(n3261), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1204), .CK(clk), .RN(n3269), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1202), .CK(clk), .RN(n3269), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1200), .CK(clk), .RN(n3274), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1198), .CK(clk), .RN(n3278), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1190), .CK(clk), .RN(n3274), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1189), .CK(clk), .RN(n3267), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1188), .CK(clk), .RN(n3253), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1187), .CK(clk), .RN(n1800), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1186), .CK(clk), .RN(n3267), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1185), .CK(clk), .RN(n3261), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1184), .CK(clk), .RN(n3280),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1183), .CK(clk), .RN(n3270), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1182), .CK(clk), .RN(n3257), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1181), .CK(clk), .RN(n3239), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1179), .CK(clk), .RN(n1796), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1178), .CK(clk), .RN(n1801), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1177), .CK(clk), .RN(n3265), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1176), .CK(clk), .RN(n3240), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1175), .CK(clk), .RN(n3267),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1174), .CK(clk), .RN(n3267), .Q(
final_result_ieee[63]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1126), .CK(clk), .RN(n1801),
.Q(LZD_output_NRM2_EW[5]), .QN(n3157) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1120), .CK(clk), .RN(n3266),
.Q(LZD_output_NRM2_EW[4]), .QN(n3150) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1119), .CK(clk), .RN(n3271), .Q(
DmP_mant_SFG_SWR[2]), .QN(n3229) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1117), .CK(clk), .RN(n3276), .Q(
DmP_mant_SFG_SWR[5]), .QN(n3230) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1115), .CK(clk), .RN(n3275),
.Q(LZD_output_NRM2_EW[1]), .QN(n3137) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1114), .CK(clk), .RN(n3244), .Q(
DmP_mant_SFG_SWR[3]), .QN(n3231) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1112), .CK(clk), .RN(n3264), .Q(
DmP_mant_SFG_SWR[4]), .QN(n3232) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1110), .CK(clk), .RN(n3274),
.Q(LZD_output_NRM2_EW[2]), .QN(n3138) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1109), .CK(clk), .RN(n3256),
.Q(LZD_output_NRM2_EW[3]), .QN(n3149) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1108), .CK(clk), .RN(n3244), .Q(
DmP_mant_SFG_SWR[6]), .QN(n3233) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1106), .CK(clk), .RN(n3262), .Q(
DmP_mant_SFG_SWR[7]), .QN(n3234) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1104), .CK(clk), .RN(n3272), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1103), .CK(clk), .RN(n3279), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1102), .CK(clk), .RN(n1801), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1101), .CK(clk), .RN(n1800), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1100), .CK(clk), .RN(n3257), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1099), .CK(clk), .RN(n3266), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1098), .CK(clk), .RN(n3269), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1097), .CK(clk), .RN(n3278), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1096), .CK(clk), .RN(n3256), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1095), .CK(clk), .RN(n3279), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1094), .CK(clk), .RN(n3272), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1093), .CK(clk), .RN(n3242), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1092), .CK(clk), .RN(n3257), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1091), .CK(clk), .RN(n1799), .Q(
final_result_ieee[38]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1090), .CK(clk), .RN(n3253), .Q(
DmP_mant_SFG_SWR[8]), .QN(n3235) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1088), .CK(clk), .RN(n3260), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1087), .CK(clk), .RN(n3260), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1086), .CK(clk), .RN(n3270), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1085), .CK(clk), .RN(n3261), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1084), .CK(clk), .RN(n3280), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1083), .CK(clk), .RN(n3280), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1082), .CK(clk), .RN(n3262), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1081), .CK(clk), .RN(n1800), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1080), .CK(clk), .RN(n3268), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1079), .CK(clk), .RN(n3266), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1078), .CK(clk), .RN(n3272), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1077), .CK(clk), .RN(n3278), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1076), .CK(clk), .RN(n3278), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1075), .CK(clk), .RN(n3253), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1074), .CK(clk), .RN(n3257), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1073), .CK(clk), .RN(n3275), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1072), .CK(clk), .RN(n3240), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1071), .CK(clk), .RN(n3270), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1070), .CK(clk), .RN(n3278), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1069), .CK(clk), .RN(n3270), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1068), .CK(clk), .RN(n3272), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1067), .CK(clk), .RN(n3261), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1066), .CK(clk), .RN(n3273), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1065), .CK(clk), .RN(n3275), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1064), .CK(clk), .RN(n3275), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1063), .CK(clk), .RN(n1799), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1062), .CK(clk), .RN(n3256), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1061), .CK(clk), .RN(n3258), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1060), .CK(clk), .RN(n3273), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1059), .CK(clk), .RN(n3278), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1058), .CK(clk), .RN(n3268), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1057), .CK(clk), .RN(n3266), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1056), .CK(clk), .RN(n3273), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1055), .CK(clk), .RN(n3274), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1054), .CK(clk), .RN(n3269), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1053), .CK(clk), .RN(n3253), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1052), .CK(clk), .RN(n3257), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1051), .CK(clk), .RN(n3254), .Q(
final_result_ieee[51]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1048), .CK(clk), .RN(n3273), .Q(
DmP_mant_SFG_SWR[12]), .QN(n1853) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1047), .CK(clk), .RN(n3269), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1854) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1046), .CK(clk), .RN(n3259), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1855) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1045), .CK(clk), .RN(n3277), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1856) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1044), .CK(clk), .RN(n3264), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1857) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1043), .CK(clk), .RN(n3244), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1858) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1042), .CK(clk), .RN(n3271), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1859) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1041), .CK(clk), .RN(n3240), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1860) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1040), .CK(clk), .RN(n3267), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1861) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1039), .CK(clk), .RN(n3271), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1840) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1038), .CK(clk), .RN(n3255), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1841) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1028), .CK(clk), .RN(n3276), .Q(
DmP_mant_SFG_SWR[32]), .QN(n1842) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1027), .CK(clk), .RN(n3259), .Q(
DmP_mant_SFG_SWR[33]), .QN(n1843) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1026), .CK(clk), .RN(n3240), .Q(
DmP_mant_SFG_SWR[34]), .QN(n1844) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1025), .CK(clk), .RN(n3264), .Q(
DmP_mant_SFG_SWR[35]), .QN(n1845) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1024), .CK(clk), .RN(n3271), .Q(
DmP_mant_SFG_SWR[36]), .QN(n1846) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1023), .CK(clk), .RN(n3255), .Q(
DmP_mant_SFG_SWR[37]), .QN(n1847) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1022), .CK(clk), .RN(n3244), .Q(
DmP_mant_SFG_SWR[38]), .QN(n1848) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1021), .CK(clk), .RN(n3240), .Q(
DmP_mant_SFG_SWR[39]), .QN(n1849) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1020), .CK(clk), .RN(n3240), .Q(
DmP_mant_SFG_SWR[40]), .QN(n1850) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1019), .CK(clk), .RN(n3267), .Q(
DmP_mant_SFG_SWR[41]), .QN(n1851) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1018), .CK(clk), .RN(n3276), .Q(
DmP_mant_SFG_SWR[42]), .QN(n1852) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1006), .CK(clk), .RN(n1799), .Q(
DmP_mant_SFG_SWR[54]) );
CMPR32X2TS intadd_72_U44 ( .A(n3074), .B(intadd_72_B_0_), .C(intadd_72_CI),
.CO(intadd_72_n43), .S(intadd_72_SUM_0_) );
CMPR32X2TS intadd_72_U43 ( .A(n3075), .B(intadd_72_B_1_), .C(intadd_72_n43),
.CO(intadd_72_n42), .S(intadd_72_SUM_1_) );
CMPR32X2TS intadd_72_U42 ( .A(n3077), .B(intadd_72_B_2_), .C(intadd_72_n42),
.CO(intadd_72_n41), .S(intadd_72_SUM_2_) );
CMPR32X2TS intadd_72_U41 ( .A(n3076), .B(intadd_72_B_3_), .C(intadd_72_n41),
.CO(intadd_72_n40), .S(intadd_72_SUM_3_) );
CMPR32X2TS intadd_72_U40 ( .A(n3079), .B(intadd_72_B_4_), .C(intadd_72_n40),
.CO(intadd_72_n39), .S(intadd_72_SUM_4_) );
CMPR32X2TS intadd_72_U39 ( .A(n3078), .B(intadd_72_B_5_), .C(intadd_72_n39),
.CO(intadd_72_n38), .S(intadd_72_SUM_5_) );
CMPR32X2TS intadd_72_U38 ( .A(n3081), .B(intadd_72_B_6_), .C(intadd_72_n38),
.CO(intadd_72_n37), .S(intadd_72_SUM_6_) );
CMPR32X2TS intadd_72_U37 ( .A(n3080), .B(intadd_72_B_7_), .C(intadd_72_n37),
.CO(intadd_72_n36), .S(intadd_72_SUM_7_) );
CMPR32X2TS intadd_72_U36 ( .A(n3082), .B(intadd_72_B_8_), .C(intadd_72_n36),
.CO(intadd_72_n35), .S(intadd_72_SUM_8_) );
CMPR32X2TS intadd_72_U35 ( .A(n3085), .B(intadd_72_B_9_), .C(intadd_72_n35),
.CO(intadd_72_n34), .S(intadd_72_SUM_9_) );
CMPR32X2TS intadd_72_U34 ( .A(n3084), .B(intadd_72_B_10_), .C(intadd_72_n34),
.CO(intadd_72_n33), .S(intadd_72_SUM_10_) );
CMPR32X2TS intadd_72_U33 ( .A(n3088), .B(intadd_72_B_11_), .C(intadd_72_n33),
.CO(intadd_72_n32), .S(intadd_72_SUM_11_) );
CMPR32X2TS intadd_72_U32 ( .A(n3087), .B(intadd_72_B_12_), .C(intadd_72_n32),
.CO(intadd_72_n31), .S(intadd_72_SUM_12_) );
CMPR32X2TS intadd_72_U31 ( .A(n3090), .B(intadd_72_B_13_), .C(intadd_72_n31),
.CO(intadd_72_n30), .S(intadd_72_SUM_13_) );
CMPR32X2TS intadd_72_U30 ( .A(n3089), .B(intadd_72_B_14_), .C(intadd_72_n30),
.CO(intadd_72_n29), .S(intadd_72_SUM_14_) );
CMPR32X2TS intadd_72_U29 ( .A(n3093), .B(intadd_72_B_15_), .C(intadd_72_n29),
.CO(intadd_72_n28), .S(intadd_72_SUM_15_) );
CMPR32X2TS intadd_72_U28 ( .A(n3092), .B(intadd_72_B_16_), .C(intadd_72_n28),
.CO(intadd_72_n27), .S(intadd_72_SUM_16_) );
CMPR32X2TS intadd_72_U27 ( .A(n3095), .B(intadd_72_B_17_), .C(intadd_72_n27),
.CO(intadd_72_n26), .S(intadd_72_SUM_17_) );
CMPR32X2TS intadd_72_U26 ( .A(n3098), .B(intadd_72_B_18_), .C(intadd_72_n26),
.CO(intadd_72_n25), .S(intadd_72_SUM_18_) );
CMPR32X2TS intadd_72_U25 ( .A(n3097), .B(intadd_72_B_19_), .C(intadd_72_n25),
.CO(intadd_72_n24), .S(intadd_72_SUM_19_) );
CMPR32X2TS intadd_72_U24 ( .A(n3100), .B(intadd_72_B_20_), .C(intadd_72_n24),
.CO(intadd_72_n23), .S(intadd_72_SUM_20_) );
CMPR32X2TS intadd_72_U23 ( .A(n3099), .B(intadd_72_B_21_), .C(intadd_72_n23),
.CO(intadd_72_n22), .S(intadd_72_SUM_21_) );
CMPR32X2TS intadd_72_U22 ( .A(n3102), .B(intadd_72_B_22_), .C(intadd_72_n22),
.CO(intadd_72_n21), .S(intadd_72_SUM_22_) );
CMPR32X2TS intadd_72_U21 ( .A(n3101), .B(intadd_72_B_23_), .C(intadd_72_n21),
.CO(intadd_72_n20), .S(intadd_72_SUM_23_) );
CMPR32X2TS intadd_72_U20 ( .A(n3106), .B(intadd_72_B_24_), .C(intadd_72_n20),
.CO(intadd_72_n19), .S(intadd_72_SUM_24_) );
CMPR32X2TS intadd_72_U19 ( .A(n3105), .B(intadd_72_B_25_), .C(intadd_72_n19),
.CO(intadd_72_n18), .S(intadd_72_SUM_25_) );
CMPR32X2TS intadd_72_U18 ( .A(n3110), .B(intadd_72_B_26_), .C(intadd_72_n18),
.CO(intadd_72_n17), .S(intadd_72_SUM_26_) );
CMPR32X2TS intadd_72_U17 ( .A(n3136), .B(intadd_72_B_27_), .C(intadd_72_n17),
.CO(intadd_72_n16), .S(intadd_72_SUM_27_) );
CMPR32X2TS intadd_72_U16 ( .A(n3135), .B(intadd_72_B_28_), .C(intadd_72_n16),
.CO(intadd_72_n15), .S(intadd_72_SUM_28_) );
CMPR32X2TS intadd_72_U15 ( .A(n3148), .B(intadd_72_B_29_), .C(intadd_72_n15),
.CO(intadd_72_n14), .S(intadd_72_SUM_29_) );
CMPR32X2TS intadd_72_U14 ( .A(n3147), .B(intadd_72_B_30_), .C(intadd_72_n14),
.CO(intadd_72_n13), .S(intadd_72_SUM_30_) );
CMPR32X2TS intadd_72_U13 ( .A(n3156), .B(intadd_72_B_31_), .C(intadd_72_n13),
.CO(intadd_72_n12), .S(intadd_72_SUM_31_) );
CMPR32X2TS intadd_72_U12 ( .A(n3155), .B(intadd_72_B_32_), .C(intadd_72_n12),
.CO(intadd_72_n11), .S(intadd_72_SUM_32_) );
CMPR32X2TS intadd_72_U11 ( .A(n3174), .B(intadd_72_B_33_), .C(intadd_72_n11),
.CO(intadd_72_n10), .S(intadd_72_SUM_33_) );
CMPR32X2TS intadd_72_U10 ( .A(n3173), .B(intadd_72_B_34_), .C(intadd_72_n10),
.CO(intadd_72_n9), .S(intadd_72_SUM_34_) );
CMPR32X2TS intadd_72_U9 ( .A(n3184), .B(intadd_72_B_35_), .C(intadd_72_n9),
.CO(intadd_72_n8), .S(intadd_72_SUM_35_) );
CMPR32X2TS intadd_72_U8 ( .A(n3212), .B(intadd_72_B_36_), .C(intadd_72_n8),
.CO(intadd_72_n7), .S(intadd_72_SUM_36_) );
CMPR32X2TS intadd_72_U7 ( .A(n3211), .B(intadd_72_B_37_), .C(intadd_72_n7),
.CO(intadd_72_n6), .S(intadd_72_SUM_37_) );
CMPR32X2TS intadd_72_U6 ( .A(n3219), .B(intadd_72_B_38_), .C(intadd_72_n6),
.CO(intadd_72_n5), .S(intadd_72_SUM_38_) );
CMPR32X2TS intadd_72_U5 ( .A(n3218), .B(intadd_72_B_39_), .C(intadd_72_n5),
.CO(intadd_72_n4), .S(intadd_72_SUM_39_) );
CMPR32X2TS intadd_72_U4 ( .A(n3222), .B(intadd_72_B_40_), .C(intadd_72_n4),
.CO(intadd_72_n3), .S(intadd_72_SUM_40_) );
CMPR32X2TS intadd_72_U3 ( .A(n3221), .B(intadd_72_B_41_), .C(intadd_72_n3),
.CO(intadd_72_n2), .S(intadd_72_SUM_41_) );
CMPR32X2TS intadd_72_U2 ( .A(n3227), .B(intadd_72_B_42_), .C(intadd_72_n2),
.CO(intadd_72_n1), .S(intadd_72_SUM_42_) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1169), .CK(clk), .RN(n3271), .Q(
Raw_mant_NRM_SWR[14]), .QN(n3220) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1301), .CK(clk), .RN(n3275),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3217) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1306), .CK(clk), .RN(n3275), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3210) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1636), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[25]), .QN(n3209) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1638), .CK(clk), .RN(n1801), .Q(
Data_array_SWR[27]), .QN(n3208) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1635), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[24]), .QN(n3207) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1666), .CK(clk), .RN(n3243),
.Q(intDY_EWSW[52]), .QN(n3206) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1735), .CK(clk), .RN(n3243),
.Q(intDX_EWSW[49]), .QN(n3205) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1688), .CK(clk), .RN(n3251),
.Q(intDY_EWSW[30]), .QN(n3203) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1696), .CK(clk), .RN(n1821),
.Q(intDY_EWSW[22]), .QN(n3202) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1704), .CK(clk), .RN(n3251),
.Q(intDY_EWSW[14]), .QN(n3201) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1669), .CK(clk), .RN(n3250),
.Q(intDY_EWSW[49]), .QN(n3200) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1654), .CK(clk), .RN(n1799), .Q(
Data_array_SWR[40]), .QN(n3199) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1653), .CK(clk), .RN(n1802), .Q(
Data_array_SWR[39]), .QN(n3198) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1652), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[38]), .QN(n3197) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1667), .CK(clk), .RN(n3251),
.Q(intDY_EWSW[51]), .QN(n3196) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1672), .CK(clk), .RN(n1800),
.Q(intDY_EWSW[46]), .QN(n3195) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1676), .CK(clk), .RN(n3249),
.Q(intDY_EWSW[42]), .QN(n3193) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1678), .CK(clk), .RN(n1796),
.Q(intDY_EWSW[40]), .QN(n3192) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1682), .CK(clk), .RN(n3239),
.Q(intDY_EWSW[36]), .QN(n3191) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1684), .CK(clk), .RN(n3244),
.Q(intDY_EWSW[34]), .QN(n3190) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1685), .CK(clk), .RN(n3242),
.Q(intDY_EWSW[33]), .QN(n3189) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1673), .CK(clk), .RN(n1865),
.Q(intDY_EWSW[45]), .QN(n3188) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1679), .CK(clk), .RN(n3237),
.Q(intDY_EWSW[39]), .QN(n3187) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1311), .CK(clk), .RN(n3261), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3183) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1723), .CK(clk), .RN(n3246),
.Q(intDX_EWSW[61]), .QN(n3180) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1792), .CK(clk), .RN(
n1803), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3179) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1661), .CK(clk), .RN(n3249),
.Q(intDY_EWSW[57]), .QN(n3178) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1668), .CK(clk), .RN(n3248),
.Q(intDY_EWSW[50]), .QN(n3177) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1718), .CK(clk), .RN(n3240),
.Q(intDY_EWSW[0]), .QN(n3175) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1686), .CK(clk), .RN(n3238),
.Q(intDY_EWSW[32]), .QN(n3169) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1690), .CK(clk), .RN(n3240),
.Q(intDY_EWSW[28]), .QN(n3168) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1692), .CK(clk), .RN(n3242),
.Q(intDY_EWSW[26]), .QN(n3167) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1694), .CK(clk), .RN(n1865),
.Q(intDY_EWSW[24]), .QN(n3166) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1698), .CK(clk), .RN(n3248),
.Q(intDY_EWSW[20]), .QN(n3165) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1700), .CK(clk), .RN(n1865),
.Q(intDY_EWSW[18]), .QN(n3164) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1706), .CK(clk), .RN(n3240),
.Q(intDY_EWSW[12]), .QN(n3163) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1716), .CK(clk), .RN(n3244),
.Q(intDY_EWSW[2]), .QN(n3162) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1697), .CK(clk), .RN(n1865),
.Q(intDY_EWSW[21]), .QN(n3161) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1705), .CK(clk), .RN(n3237),
.Q(intDY_EWSW[13]), .QN(n3160) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1709), .CK(clk), .RN(n3266),
.Q(intDY_EWSW[9]), .QN(n3158) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1321), .CK(clk), .RN(n1800), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3154) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1165), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3153) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1121), .CK(clk), .RN(n3264), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3152) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1171), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3151) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1129), .CK(clk), .RN(n3269), .Q(
Raw_mant_NRM_SWR[54]), .QN(n3144) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1164), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3139) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1598), .CK(clk), .RN(n3252),
.Q(shift_value_SHT2_EWR[3]), .QN(n3114) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(n3268), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3109) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1657), .CK(clk), .RN(n3245),
.Q(intDY_EWSW[61]), .QN(n3104) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1170), .CK(clk), .RN(n3251), .Q(
Raw_mant_NRM_SWR[13]), .QN(n3096) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1168), .CK(clk), .RN(n3268), .Q(
Raw_mant_NRM_SWR[15]), .QN(n3094) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1162), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[21]), .QN(n3091) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1157), .CK(clk), .RN(n1802), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3083) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1140), .CK(clk), .RN(n3274), .Q(
Raw_mant_NRM_SWR[43]), .QN(n3073) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1136), .CK(clk), .RN(n3278), .Q(
Raw_mant_NRM_SWR[47]), .QN(n3072) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1134), .CK(clk), .RN(n3266), .Q(
Raw_mant_NRM_SWR[49]), .QN(n3071) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1521), .CK(clk), .RN(n3240), .Q(
DMP_EXP_EWSW[56]), .QN(n3070) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1730), .CK(clk), .RN(n3242),
.Q(intDX_EWSW[54]), .QN(n3069) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1522), .CK(clk), .RN(n3237), .Q(
DMP_EXP_EWSW[55]), .QN(n3067) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1523), .CK(clk), .RN(n3251), .Q(
DMP_EXP_EWSW[54]), .QN(n3066) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1167), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[16]), .QN(n3065) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1524), .CK(clk), .RN(n3241), .Q(
DMP_EXP_EWSW[53]), .QN(n3064) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1149), .CK(clk), .RN(n3261), .Q(
Raw_mant_NRM_SWR[34]), .QN(n3063) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1712), .CK(clk), .RN(n3243),
.Q(intDY_EWSW[6]), .QN(n3062) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1687), .CK(clk), .RN(n3243),
.Q(intDY_EWSW[31]), .QN(n3061) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1695), .CK(clk), .RN(n1800),
.Q(intDY_EWSW[23]), .QN(n3060) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1703), .CK(clk), .RN(n3268),
.Q(intDY_EWSW[15]), .QN(n3059) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1675), .CK(clk), .RN(n3245),
.Q(intDY_EWSW[43]), .QN(n3058) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1677), .CK(clk), .RN(n1865),
.Q(intDY_EWSW[41]), .QN(n3057) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1683), .CK(clk), .RN(n1796),
.Q(intDY_EWSW[35]), .QN(n3056) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1671), .CK(clk), .RN(n3272),
.Q(intDY_EWSW[47]), .QN(n3055) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1725), .CK(clk), .RN(n3250),
.Q(intDX_EWSW[59]), .QN(n3054) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1722), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[62]), .QN(n3053) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1707), .CK(clk), .RN(n1821),
.Q(intDY_EWSW[11]), .QN(n3052) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1710), .CK(clk), .RN(n3250),
.Q(intDY_EWSW[8]), .QN(n3051) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1689), .CK(clk), .RN(n3237),
.Q(intDY_EWSW[29]), .QN(n3049) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1715), .CK(clk), .RN(n3238),
.Q(intDY_EWSW[3]), .QN(n3048) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1691), .CK(clk), .RN(n3252),
.Q(intDY_EWSW[27]), .QN(n3047) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1693), .CK(clk), .RN(n3249),
.Q(intDY_EWSW[25]), .QN(n3046) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1699), .CK(clk), .RN(n3243),
.Q(intDY_EWSW[19]), .QN(n3045) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1701), .CK(clk), .RN(n1821),
.Q(intDY_EWSW[17]), .QN(n3044) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1152), .CK(clk), .RN(n3266), .Q(
Raw_mant_NRM_SWR[31]), .QN(n3037) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1761), .CK(clk), .RN(n3244),
.Q(intDX_EWSW[23]), .QN(n3034) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1753), .CK(clk), .RN(n3250),
.Q(intDX_EWSW[31]), .QN(n3033) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1769), .CK(clk), .RN(n3238),
.Q(intDX_EWSW[15]), .QN(n3030) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1153), .CK(clk), .RN(n3270), .Q(
Raw_mant_NRM_SWR[30]), .QN(n3029) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1150), .CK(clk), .RN(n1800), .Q(
Raw_mant_NRM_SWR[33]), .QN(n3028) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1147), .CK(clk), .RN(n3269), .Q(
Raw_mant_NRM_SWR[36]), .QN(n3027) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1144), .CK(clk), .RN(n3258), .Q(
Raw_mant_NRM_SWR[39]), .QN(n3026) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1133), .CK(clk), .RN(n3257), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3025) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1193), .CK(clk), .RN(n3266), .Q(
DmP_EXP_EWSW[55]), .QN(n3023) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1194), .CK(clk), .RN(n1799), .Q(
DmP_EXP_EWSW[54]), .QN(n3021) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1195), .CK(clk), .RN(n3267), .Q(
DmP_EXP_EWSW[53]), .QN(n3020) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1151), .CK(clk), .RN(n3256), .Q(
Raw_mant_NRM_SWR[32]), .QN(n3019) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1172), .CK(clk), .RN(n3280), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3018) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1143), .CK(clk), .RN(n1799), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3017) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1192), .CK(clk), .RN(n3267), .Q(
DmP_EXP_EWSW[56]), .QN(n3015) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1665), .CK(clk), .RN(n3241),
.Q(intDY_EWSW[53]), .QN(n3014) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1663), .CK(clk), .RN(n3241),
.Q(intDY_EWSW[55]), .QN(n3013) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1800), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3043) );
DFFRX2TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1719), .CK(clk), .RN(n3239),
.Q(left_right_SHT2), .QN(n3068) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1089), .CK(clk), .RN(n3266), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3103) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1111), .CK(clk), .RN(n3264), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3128) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1118), .CK(clk), .RN(n3259), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3141) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n1787), .CK(clk), .RN(n3249), .Q(
n3016), .QN(n3225) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1163), .CK(clk), .RN(n3258), .Q(
Raw_mant_NRM_SWR[20]), .QN(n3038) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1159), .CK(clk), .RN(n3258), .Q(
Raw_mant_NRM_SWR[24]), .QN(n3086) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1156), .CK(clk), .RN(n3278), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3142) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1155), .CK(clk), .RN(n3261), .Q(
Raw_mant_NRM_SWR[28]), .QN(n3035) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1681), .CK(clk), .RN(n3243),
.Q(intDY_EWSW[37]), .QN(n3186) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1711), .CK(clk), .RN(n3258),
.Q(intDY_EWSW[7]), .QN(n3204) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1714), .CK(clk), .RN(n3242),
.Q(intDY_EWSW[4]), .QN(n3050) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1708), .CK(clk), .RN(n3241),
.Q(intDY_EWSW[10]), .QN(n3159) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1670), .CK(clk), .RN(n3241),
.Q(intDY_EWSW[48]), .QN(n3170) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1674), .CK(clk), .RN(n3251),
.Q(intDY_EWSW[44]), .QN(n3194) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1727), .CK(clk), .RN(n3241),
.Q(intDX_EWSW[57]), .QN(n3134) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1733), .CK(clk), .RN(n3247),
.Q(intDX_EWSW[51]), .QN(n3140) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1734), .CK(clk), .RN(n3246),
.Q(intDX_EWSW[50]), .QN(n3036) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1739), .CK(clk), .RN(n3240),
.Q(intDX_EWSW[45]), .QN(n3129) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1741), .CK(clk), .RN(n3245),
.Q(intDX_EWSW[43]), .QN(n3031) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1742), .CK(clk), .RN(n3248),
.Q(intDX_EWSW[42]), .QN(n3115) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1743), .CK(clk), .RN(n3273),
.Q(intDX_EWSW[41]), .QN(n3125) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1748), .CK(clk), .RN(n3244),
.Q(intDX_EWSW[36]), .QN(n3123) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1749), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[35]), .QN(n3032) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1750), .CK(clk), .RN(n3245),
.Q(intDX_EWSW[34]), .QN(n3116) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1751), .CK(clk), .RN(n1796),
.Q(intDX_EWSW[33]), .QN(n3113) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1729), .CK(clk), .RN(n3252),
.Q(intDX_EWSW[55]), .QN(n3224) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1731), .CK(clk), .RN(n1821),
.Q(intDX_EWSW[53]), .QN(n3223) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1702), .CK(clk), .RN(n1865),
.Q(intDY_EWSW[16]), .QN(n3171) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1728), .CK(clk), .RN(n3249),
.Q(intDX_EWSW[56]), .QN(n3022) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1680), .CK(clk), .RN(n3238),
.Q(intDY_EWSW[38]), .QN(n3214) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1713), .CK(clk), .RN(n3245),
.Q(intDY_EWSW[5]), .QN(n3176) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1717), .CK(clk), .RN(n3237),
.Q(intDY_EWSW[1]), .QN(n3213) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1724), .CK(clk), .RN(n3242),
.Q(intDX_EWSW[60]), .QN(n3182) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1726), .CK(clk), .RN(n1821),
.Q(intDX_EWSW[58]), .QN(n3181) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1738), .CK(clk), .RN(n3251),
.Q(intDX_EWSW[46]), .QN(n3117) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1781), .CK(clk), .RN(n3255),
.Q(intDX_EWSW[3]), .QN(n3112) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1754), .CK(clk), .RN(n3238),
.Q(intDX_EWSW[30]), .QN(n3120) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1755), .CK(clk), .RN(n3244),
.Q(intDX_EWSW[29]), .QN(n3126) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1756), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[28]), .QN(n3118) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1757), .CK(clk), .RN(n3267),
.Q(intDX_EWSW[27]), .QN(n3039) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1758), .CK(clk), .RN(n3237),
.Q(intDX_EWSW[26]), .QN(n3145) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1759), .CK(clk), .RN(n3244),
.Q(intDX_EWSW[25]), .QN(n3131) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1762), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[22]), .QN(n3121) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1763), .CK(clk), .RN(n3267),
.Q(intDX_EWSW[21]), .QN(n3143) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1764), .CK(clk), .RN(n3242),
.Q(intDX_EWSW[20]), .QN(n3119) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1765), .CK(clk), .RN(n1796),
.Q(intDX_EWSW[19]), .QN(n3040) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1766), .CK(clk), .RN(n3237),
.Q(intDX_EWSW[18]), .QN(n3146) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1767), .CK(clk), .RN(n3267),
.Q(intDX_EWSW[17]), .QN(n3132) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1770), .CK(clk), .RN(n3241),
.Q(intDX_EWSW[14]), .QN(n3108) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1771), .CK(clk), .RN(n3238),
.Q(intDX_EWSW[13]), .QN(n3127) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1772), .CK(clk), .RN(n3237),
.Q(intDX_EWSW[12]), .QN(n3107) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1773), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[11]), .QN(n3130) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1776), .CK(clk), .RN(n3245),
.Q(intDX_EWSW[8]), .QN(n3133) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1148), .CK(clk), .RN(n1800), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3041) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1595), .CK(clk), .RN(n3245),
.Q(shift_value_SHT2_EWR[5]), .QN(n3111) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1141), .CK(clk), .RN(n3268), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3124) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1137), .CK(clk), .RN(n1799), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3122) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1651), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[37]), .QN(n3185) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1130), .CK(clk), .RN(n1799), .Q(
Raw_mant_NRM_SWR[53]), .QN(n3042) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1597), .CK(clk), .RN(n3252),
.Q(shift_value_SHT2_EWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1154), .CK(clk), .RN(n3278), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1138), .CK(clk), .RN(n3266), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1779), .CK(clk), .RN(n3243),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1124), .CK(clk), .RN(n3270), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1160), .CK(clk), .RN(n1800), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1135), .CK(clk), .RN(n3254), .Q(
Raw_mant_NRM_SWR[48]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1621), .CK(clk), .RN(n1796), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1626), .CK(clk), .RN(n1800), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1624), .CK(clk), .RN(n1801), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1631), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1746), .CK(clk), .RN(n3252),
.Q(intDX_EWSW[38]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1629), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1732), .CK(clk), .RN(n3247),
.Q(intDX_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1740), .CK(clk), .RN(n1865),
.Q(intDX_EWSW[44]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1747), .CK(clk), .RN(n3250),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1737), .CK(clk), .RN(n3237),
.Q(intDX_EWSW[47]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1783), .CK(clk), .RN(n3243),
.Q(intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1744), .CK(clk), .RN(n3252),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1736), .CK(clk), .RN(n3250),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1774), .CK(clk), .RN(n3250),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1777), .CK(clk), .RN(n1800),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1768), .CK(clk), .RN(n3244),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1752), .CK(clk), .RN(n1796),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1782), .CK(clk), .RN(n3252),
.Q(intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1760), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1619), .CK(clk), .RN(n3255), .Q(
Data_array_SWR[14]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1145), .CK(clk), .RN(n3254), .Q(
Raw_mant_NRM_SWR[38]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1166), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1132), .CK(clk), .RN(n3262), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1660), .CK(clk), .RN(n3249),
.Q(intDY_EWSW[58]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1658), .CK(clk), .RN(n3248),
.Q(intDY_EWSW[60]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1793), .CK(clk), .RN(
n3238), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1656), .CK(clk), .RN(n3247),
.Q(intDY_EWSW[62]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1142), .CK(clk), .RN(n3275), .Q(
Raw_mant_NRM_SWR[41]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1158), .CK(clk), .RN(n3257), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1647), .CK(clk), .RN(n3246), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1614), .CK(clk), .RN(n3243), .Q(
Data_array_SWR[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1612), .CK(clk), .RN(n3238), .Q(
Data_array_SWR[12]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1637), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1640), .CK(clk), .RN(n1801), .Q(
Data_array_SWR[29]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1642), .CK(clk), .RN(n1799), .Q(
Data_array_SWR[31]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1648), .CK(clk), .RN(n1799), .Q(
Data_array_SWR[34]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1146), .CK(clk), .RN(n3253), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1599), .CK(clk), .RN(n1802),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1649), .CK(clk), .RN(n1802), .Q(
Data_array_SWR[35]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1611), .CK(clk), .RN(n1800), .Q(
Data_array_SWR[11]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1662), .CK(clk), .RN(n3247),
.Q(intDY_EWSW[56]), .QN(n1818) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1664), .CK(clk), .RN(n3240),
.Q(intDY_EWSW[54]), .QN(n1820) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1610), .CK(clk), .RN(n1799), .Q(
Data_array_SWR[10]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1608), .CK(clk), .RN(n1802), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1609), .CK(clk), .RN(n1801), .Q(
Data_array_SWR[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1235), .CK(clk), .RN(n3262),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1253), .CK(clk), .RN(n3271),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1271), .CK(clk), .RN(n3261),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1279), .CK(clk), .RN(n3253),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1213), .CK(clk), .RN(n1865),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1217), .CK(clk), .RN(n3239),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1221), .CK(clk), .RN(n3265),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1225), .CK(clk), .RN(n3265),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1239), .CK(clk), .RN(n3275),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1243), .CK(clk), .RN(n1800),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1247), .CK(clk), .RN(n3271),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1257), .CK(clk), .RN(n3263),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1201), .CK(clk), .RN(n3279),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1485), .CK(clk), .RN(n1802), .Q(
DMP_SFG[8]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1721), .CK(clk), .RN(n3245),
.Q(intDX_EWSW[63]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1180), .CK(clk), .RN(n3275), .Q(
OP_FLAG_SFG), .QN(n3281) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1207), .CK(clk), .RN(n1801),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1245), .CK(clk), .RN(n3264),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1251), .CK(clk), .RN(n3271),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1255), .CK(clk), .RN(n3255),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1259), .CK(clk), .RN(n3263),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1263), .CK(clk), .RN(n3263),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1196), .CK(clk), .RN(n3262), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1231), .CK(clk), .RN(n3265),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1249), .CK(clk), .RN(n3277),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1267), .CK(clk), .RN(n3263),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n3273), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1287), .CK(clk), .RN(n3278), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1293), .CK(clk), .RN(n1796), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1283), .CK(clk), .RN(n3274), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1295), .CK(clk), .RN(n3260), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1520), .CK(clk), .RN(n3279), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(n3267), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1122), .CK(clk), .RN(n3267), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1037), .CK(clk), .RN(n3240), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1049), .CK(clk), .RN(n3257), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1128), .CK(clk), .RN(n3272), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1007), .CK(clk), .RN(n1802), .Q(
DmP_mant_SFG_SWR[53]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1008), .CK(clk), .RN(n3256), .Q(
DmP_mant_SFG_SWR[52]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1009), .CK(clk), .RN(n3279), .Q(
DmP_mant_SFG_SWR[51]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1010), .CK(clk), .RN(n1801), .Q(
DmP_mant_SFG_SWR[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1011), .CK(clk), .RN(n3276), .Q(
DmP_mant_SFG_SWR[49]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1012), .CK(clk), .RN(n3240), .Q(
DmP_mant_SFG_SWR[48]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1013), .CK(clk), .RN(n3264), .Q(
DmP_mant_SFG_SWR[47]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1014), .CK(clk), .RN(n3255), .Q(
DmP_mant_SFG_SWR[46]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1015), .CK(clk), .RN(n3259), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1016), .CK(clk), .RN(n3276), .Q(
DmP_mant_SFG_SWR[44]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1017), .CK(clk), .RN(n3277), .Q(
DmP_mant_SFG_SWR[43]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1029), .CK(clk), .RN(n3244), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1030), .CK(clk), .RN(n3264), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1031), .CK(clk), .RN(n3267), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1032), .CK(clk), .RN(n3277), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1033), .CK(clk), .RN(n3267), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1034), .CK(clk), .RN(n3259), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1035), .CK(clk), .RN(n3244), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1036), .CK(clk), .RN(n3271), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1627), .CK(clk), .RN(n1799), .Q(
Data_array_SWR[18]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1331), .CK(clk), .RN(n3279), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1336), .CK(clk), .RN(n1801), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1341), .CK(clk), .RN(n3253), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1346), .CK(clk), .RN(n3262), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1131), .CK(clk), .RN(n3258), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1601), .CK(clk), .RN(n3242), .Q(
Data_array_SWR[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1655), .CK(clk), .RN(n3246),
.Q(intDY_EWSW[63]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1127), .CK(clk), .RN(n3262), .Q(
Raw_mant_NRM_SWR[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1113), .CK(clk), .RN(n3277), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1630), .CK(clk), .RN(n1802), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1628), .CK(clk), .RN(n3242), .Q(
Data_array_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1105), .CK(clk), .RN(n3268), .Q(
Raw_mant_NRM_SWR[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1780), .CK(clk), .RN(n3237),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1745), .CK(clk), .RN(n3251),
.Q(intDX_EWSW[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1775), .CK(clk), .RN(n3239),
.Q(intDX_EWSW[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1632), .CK(clk), .RN(n1800), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1639), .CK(clk), .RN(n3250), .Q(
Data_array_SWR[28]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1116), .CK(clk), .RN(n3271), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1778), .CK(clk), .RN(n3250),
.Q(intDX_EWSW[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1161), .CK(clk), .RN(n1865), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1784), .CK(clk), .RN(n3237),
.Q(intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1107), .CK(clk), .RN(n3259), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1139), .CK(clk), .RN(n3272), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1659), .CK(clk), .RN(n3246),
.Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1641), .CK(clk), .RN(n1800), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1645), .CK(clk), .RN(n3241), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1650), .CK(clk), .RN(n3244), .Q(
Data_array_SWR[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1265), .CK(clk), .RN(n3263),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1261), .CK(clk), .RN(n3263),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1229), .CK(clk), .RN(n3265),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1209), .CK(clk), .RN(n3260),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1205), .CK(clk), .RN(n3270),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1607), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1606), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1605), .CK(clk), .RN(n1801), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1604), .CK(clk), .RN(n1803), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1233), .CK(clk), .RN(n3258),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1219), .CK(clk), .RN(n3280),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1215), .CK(clk), .RN(n3260),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1297), .CK(clk), .RN(n3280), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1488), .CK(clk), .RN(n1802), .Q(
DMP_SFG[7]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(n3249),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1197), .CK(clk), .RN(n3268),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1291), .CK(clk), .RN(n3253), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1285), .CK(clk), .RN(n3272), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1289), .CK(clk), .RN(n3266), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1125), .CK(clk), .RN(n1800), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1199), .CK(clk), .RN(n3257),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1275), .CK(clk), .RN(n3262),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1273), .CK(clk), .RN(n3254),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1277), .CK(clk), .RN(n3275),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1269), .CK(clk), .RN(n3270),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1241), .CK(clk), .RN(n3266),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1237), .CK(clk), .RN(n3268),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1227), .CK(clk), .RN(n3265),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1223), .CK(clk), .RN(n3265),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1211), .CK(clk), .RN(n3260),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1203), .CK(clk), .RN(n3258),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1050), .CK(clk), .RN(n3258), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n1788), .CK(clk), .RN(n1796), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1326), .CK(clk), .RN(n1800), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1600), .CK(clk), .RN(n3252), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n1821), .Q(
Data_array_SWR[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1191), .CK(clk), .RN(n3278), .Q(
DmP_EXP_EWSW[57]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1123), .CK(clk), .RN(n3254),
.Q(LZD_output_NRM2_EW[0]), .QN(n1862) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1525), .CK(clk), .RN(n3252), .Q(
DMP_EXP_EWSW[52]), .QN(n3216) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1173), .CK(clk), .RN(n3267), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3215) );
ADDFX1TS DP_OP_15J66_123_7955_U11 ( .A(n3137), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J66_123_7955_n11), .CO(DP_OP_15J66_123_7955_n10), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J66_123_7955_U10 ( .A(n3138), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J66_123_7955_n10), .CO(DP_OP_15J66_123_7955_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J66_123_7955_U9 ( .A(n3149), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J66_123_7955_n9), .CO(DP_OP_15J66_123_7955_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J66_123_7955_U8 ( .A(n3150), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J66_123_7955_n8), .CO(DP_OP_15J66_123_7955_n7), .S(
exp_rslt_NRM2_EW1[4]) );
ADDFX1TS DP_OP_15J66_123_7955_U7 ( .A(n3157), .B(DMP_exp_NRM2_EW[5]), .CI(
DP_OP_15J66_123_7955_n7), .CO(DP_OP_15J66_123_7955_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1316), .CK(clk), .RN(n3272), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3172) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1790), .CK(clk), .RN(n3239), .Q(
n1863), .QN(n3228) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1789), .CK(clk), .RN(n3242), .Q(
n3024), .QN(n3226) );
AOI222X1TS U1837 ( .A0(n2897), .A1(n2958), .B0(n2896), .B1(n2940), .C0(n2895), .C1(n2939), .Y(n2988) );
CLKINVX6TS U1838 ( .A(n2704), .Y(n2705) );
AOI222X1TS U1839 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[43]), .C0(n2562), .C1(DmP_mant_SHT1_SW[42]), .Y(n2558) );
INVX12TS U1840 ( .A(n2465), .Y(n2470) );
BUFX4TS U1841 ( .A(n2474), .Y(n2580) );
AOI222X1TS U1842 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1797), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2497), .C0(DmP_mant_SHT1_SW[50]), .C1(n2576), .Y(n2666) );
AOI222X1TS U1843 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1797), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2562), .C0(n2563), .C1(
DmP_mant_SHT1_SW[51]), .Y(n2593) );
AOI222X1TS U1844 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[41]), .C0(n2562), .C1(DmP_mant_SHT1_SW[40]), .Y(n2561) );
OAI32X1TS U1845 ( .A0(n2072), .A1(Raw_mant_NRM_SWR[8]), .A2(
Raw_mant_NRM_SWR[7]), .B0(n2071), .B1(n2072), .Y(n2446) );
INVX1TS U1846 ( .A(n2424), .Y(n2448) );
INVX1TS U1847 ( .A(n2459), .Y(n2056) );
OR2X6TS U1848 ( .A(n2790), .B(n2778), .Y(n2829) );
INVX6TS U1849 ( .A(n2773), .Y(n1794) );
BUFX6TS U1850 ( .A(n2346), .Y(n1795) );
BUFX6TS U1851 ( .A(n3244), .Y(n3267) );
BUFX6TS U1852 ( .A(n1801), .Y(n3244) );
CLKINVX6TS U1853 ( .A(n2491), .Y(n2576) );
BUFX6TS U1854 ( .A(n1803), .Y(n3240) );
BUFX6TS U1855 ( .A(n1802), .Y(n1796) );
CLKINVX6TS U1856 ( .A(n1873), .Y(n2884) );
INVX6TS U1857 ( .A(n1918), .Y(n1973) );
OR2X2TS U1858 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1987) );
NOR2X1TS U1859 ( .A(n2651), .B(n2591), .Y(n2592) );
BUFX4TS U1860 ( .A(n2492), .Y(n2658) );
INVX3TS U1861 ( .A(n2490), .Y(n2643) );
AOI222X1TS U1862 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2631), .C0(n2576), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2600) );
AOI222X1TS U1863 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2618), .B0(
Raw_mant_NRM_SWR[6]), .B1(n2497), .C0(n2563), .C1(DmP_mant_SHT1_SW[46]), .Y(n2632) );
AOI222X1TS U1864 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2618), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2497), .C0(n2630), .C1(
DmP_mant_SHT1_SW[36]), .Y(n2657) );
AOI222X1TS U1865 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2631), .C0(n2563), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2644) );
AOI222X1TS U1866 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2631), .C0(n2630), .C1(
DmP_mant_SHT1_SW[40]), .Y(n2614) );
AOI222X1TS U1867 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2618), .B0(
Raw_mant_NRM_SWR[14]), .B1(n2497), .C0(n2630), .C1(
DmP_mant_SHT1_SW[38]), .Y(n2617) );
AOI222X1TS U1868 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2631), .C0(n2630), .C1(
DmP_mant_SHT1_SW[11]), .Y(n2652) );
AOI222X1TS U1869 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2631), .C0(n2563), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2635) );
CLKINVX6TS U1870 ( .A(n2505), .Y(n2724) );
AOI222X1TS U1871 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2631), .B0(
Raw_mant_NRM_SWR[4]), .B1(n2497), .C0(n2563), .C1(DmP_mant_SHT1_SW[48]), .Y(n2661) );
AOI222X1TS U1872 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2618), .B0(
Raw_mant_NRM_SWR[23]), .B1(n2497), .C0(n2630), .C1(
DmP_mant_SHT1_SW[29]), .Y(n2607) );
AOI222X1TS U1873 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2631), .C0(n2576), .C1(
DmP_mant_SHT1_SW[42]), .Y(n2626) );
AOI222X1TS U1874 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[33]), .B1(n2631), .C0(n2630), .C1(
DmP_mant_SHT1_SW[20]), .Y(n2625) );
AOI222X1TS U1875 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2618), .B0(n2563), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2575), .C1(DmP_mant_SHT1_SW[36]), .Y(n2586) );
AOI222X1TS U1876 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[21]), .C0(n2575), .C1(DmP_mant_SHT1_SW[20]), .Y(n2554) );
NOR2X1TS U1877 ( .A(n2473), .B(n2688), .Y(n2474) );
AOI222X1TS U1878 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2631), .B0(n2563), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2562), .C1(DmP_mant_SHT1_SW[48]), .Y(n2581) );
BUFX4TS U1879 ( .A(n2464), .Y(n2497) );
BUFX6TS U1880 ( .A(n2494), .Y(n1797) );
NAND4XLTS U1881 ( .A(n2463), .B(n2462), .C(n2461), .D(n2460), .Y(n2466) );
NAND3X1TS U1882 ( .A(n2073), .B(Raw_mant_NRM_SWR[1]), .C(n3141), .Y(n2460)
);
NAND3BX1TS U1883 ( .AN(Raw_mant_NRM_SWR[7]), .B(n2071), .C(n3103), .Y(n2060)
);
NOR3X1TS U1884 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .C(
n2012), .Y(n2018) );
BUFX6TS U1885 ( .A(n2218), .Y(n2773) );
OR2X2TS U1886 ( .A(n2219), .B(n2753), .Y(n2218) );
CLKINVX6TS U1887 ( .A(n2346), .Y(n1798) );
AOI211XLTS U1888 ( .A0(n2444), .A1(n2450), .B0(n2443), .C0(n2442), .Y(n2445)
);
BUFX6TS U1889 ( .A(n3267), .Y(n3255) );
BUFX6TS U1890 ( .A(n3269), .Y(n1799) );
BUFX6TS U1891 ( .A(n3252), .Y(n1800) );
BUFX6TS U1892 ( .A(n1866), .Y(n2991) );
BUFX6TS U1893 ( .A(n3274), .Y(n1801) );
NOR2X4TS U1894 ( .A(n2867), .B(n1953), .Y(n1883) );
NOR2X6TS U1895 ( .A(left_right_SHT2), .B(n1870), .Y(n1958) );
AND2X2TS U1896 ( .A(Shift_reg_FLAGS_7[3]), .B(n2959), .Y(n1866) );
BUFX6TS U1897 ( .A(n3273), .Y(n1802) );
BUFX6TS U1898 ( .A(n3279), .Y(n1803) );
INVX3TS U1899 ( .A(n3226), .Y(busy) );
NOR2XLTS U1900 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2070)
);
INVX3TS U1901 ( .A(OP_FLAG_SFG), .Y(n2797) );
BUFX6TS U1902 ( .A(n3226), .Y(n2760) );
NAND2X6TS U1903 ( .A(shift_value_SHT2_EWR[4]), .B(n3111), .Y(n1870) );
CLKINVX6TS U1904 ( .A(rst), .Y(n1865) );
NAND2BXLTS U1905 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2113) );
NAND2X1TS U1906 ( .A(n2037), .B(n3073), .Y(n2031) );
NOR2X1TS U1907 ( .A(Raw_mant_NRM_SWR[34]), .B(n2013), .Y(n2023) );
NAND2BXLTS U1908 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2150) );
NAND2X1TS U1909 ( .A(n2044), .B(n3083), .Y(n2038) );
NAND2BXLTS U1910 ( .AN(n2439), .B(n2014), .Y(n2011) );
INVX2TS U1911 ( .A(n2031), .Y(n2449) );
NOR2X1TS U1912 ( .A(Raw_mant_NRM_SWR[16]), .B(n2424), .Y(n2066) );
INVX2TS U1913 ( .A(n2012), .Y(n2041) );
OR2X1TS U1914 ( .A(n2669), .B(Raw_mant_NRM_SWR[35]), .Y(n2013) );
NAND2X1TS U1915 ( .A(n2057), .B(n2459), .Y(n2424) );
INVX2TS U1916 ( .A(n2425), .Y(n2427) );
NOR2BX1TS U1917 ( .AN(n2671), .B(n2670), .Y(n2431) );
NOR3X1TS U1918 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n2425), .Y(n2043) );
NAND2BXLTS U1919 ( .AN(n2038), .B(Raw_mant_NRM_SWR[25]), .Y(n2672) );
NAND3X1TS U1920 ( .A(n3017), .B(n3026), .C(n2444), .Y(n2670) );
NAND2X1TS U1921 ( .A(n3027), .B(n2431), .Y(n2669) );
NAND2X1TS U1922 ( .A(n2030), .B(n2062), .Y(n2069) );
NOR3X1TS U1923 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n2069),
.Y(n2073) );
NOR2X1TS U1924 ( .A(Raw_mant_NRM_SWR[14]), .B(n2017), .Y(n2026) );
NAND2BXLTS U1925 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2158) );
OAI211XLTS U1926 ( .A0(n2669), .A1(n3041), .B0(n2457), .C0(n2456), .Y(n2458)
);
NAND3XLTS U1927 ( .A(n2039), .B(n2436), .C(n2672), .Y(n2040) );
NAND2X1TS U1928 ( .A(n2058), .B(n3018), .Y(n2050) );
OAI211XLTS U1929 ( .A0(n2028), .A1(n3142), .B0(n2027), .C0(n2065), .Y(n2029)
);
NAND2X1TS U1930 ( .A(n2066), .B(n3094), .Y(n2017) );
OAI31X1TS U1931 ( .A0(n2439), .A1(n2015), .A2(Raw_mant_NRM_SWR[48]), .B0(
n2014), .Y(n2016) );
NAND4XLTS U1932 ( .A(n2435), .B(n2434), .C(n2433), .D(n2432), .Y(n2684) );
AO21XLTS U1933 ( .A0(n3018), .A1(n3151), .B0(n2067), .Y(n2068) );
AOI222X1TS U1934 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n1797), .B0(n2576), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2575), .C1(DmP_mant_SHT1_SW[2]), .Y(n2514)
);
AOI222X1TS U1935 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n1797), .B0(n2576), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2575), .C1(DmP_mant_SHT1_SW[8]), .Y(n2648)
);
AOI222X1TS U1936 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2618), .B0(n2563), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2575), .C1(DmP_mant_SHT1_SW[9]), .Y(n2528)
);
AOI222X1TS U1937 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1797), .B0(n2576), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2575), .C1(DmP_mant_SHT1_SW[27]), .Y(n2545) );
AOI222X1TS U1938 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1797), .B0(n2576), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2575), .C1(DmP_mant_SHT1_SW[29]), .Y(n2573) );
AOI222X1TS U1939 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2575), .C1(DmP_mant_SHT1_SW[24]), .Y(n2597) );
AOI2BB2XLTS U1940 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n2799), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_72_B_12_) );
CLKAND2X2TS U1941 ( .A(DMP_SFG[7]), .B(n2667), .Y(n2792) );
AOI2BB2XLTS U1942 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n2799), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[11]), .Y(intadd_72_CI) );
AOI222X1TS U1943 ( .A0(n2792), .A1(DMP_SFG[8]), .B0(n2792), .B1(n2793), .C0(
DMP_SFG[8]), .C1(n2793), .Y(intadd_72_B_0_) );
NAND3XLTS U1944 ( .A(Raw_mant_NRM_SWR[0]), .B(n2688), .C(n2491), .Y(n2596)
);
AOI222X1TS U1945 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[39]), .C0(n2562), .C1(DmP_mant_SHT1_SW[38]), .Y(n2567) );
OAI211X1TS U1946 ( .A0(n1808), .A1(n2892), .B0(n2891), .C0(n2890), .Y(n2980)
);
OAI211X1TS U1947 ( .A0(n1808), .A1(n2898), .B0(n2888), .C0(n2887), .Y(n2972)
);
OAI211X1TS U1948 ( .A0(n2857), .A1(n2892), .B0(n2856), .C0(n2855), .Y(n2979)
);
OAI211X1TS U1949 ( .A0(n2857), .A1(n2898), .B0(n2853), .C0(n2852), .Y(n2973)
);
OAI211X1TS U1950 ( .A0(n2839), .A1(n2892), .B0(n2838), .C0(n2837), .Y(n2977)
);
OAI211X1TS U1951 ( .A0(n2839), .A1(n2898), .B0(n2835), .C0(n2834), .Y(n2975)
);
NOR2X1TS U1952 ( .A(n2473), .B(n2787), .Y(n2687) );
AOI222X1TS U1953 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2631), .C0(n2630), .C1(DmP_mant_SHT1_SW[44]), .Y(n2629) );
AOI222X1TS U1954 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2631), .B0(n2563), .B1(
DmP_mant_SHT1_SW[45]), .C0(n2562), .C1(DmP_mant_SHT1_SW[44]), .Y(n2540) );
AOI222X1TS U1955 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2631), .B0(n2576), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2562), .C1(DmP_mant_SHT1_SW[46]), .Y(n2585) );
AOI222X1TS U1956 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[4]), .C0(n2477), .C1(DmP_mant_SHT1_SW[3]), .Y(n2518)
);
AOI222X1TS U1957 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[12]), .C0(n2562), .C1(DmP_mant_SHT1_SW[11]), .Y(n2566) );
AOI222X1TS U1958 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2618), .B0(n2563), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2562), .C1(DmP_mant_SHT1_SW[13]), .Y(n2579) );
AOI222X1TS U1959 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2464), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2631), .C0(n2630), .C1(
DmP_mant_SHT1_SW[15]), .Y(n2642) );
AOI222X1TS U1960 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2618), .B0(
Raw_mant_NRM_SWR[34]), .B1(n2497), .C0(n2630), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2622) );
AOI222X1TS U1961 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2575), .C1(DmP_mant_SHT1_SW[16]), .Y(n2531) );
AOI222X1TS U1962 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2618), .B0(n2563), .B1(
DmP_mant_SHT1_SW[19]), .C0(n2575), .C1(DmP_mant_SHT1_SW[18]), .Y(n2557) );
AOI222X1TS U1963 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2575), .C1(DmP_mant_SHT1_SW[22]), .Y(n2551) );
AOI222X1TS U1964 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2631), .C0(n2563), .C1(
DmP_mant_SHT1_SW[24]), .Y(n2638) );
AOI222X1TS U1965 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2575), .C1(DmP_mant_SHT1_SW[25]), .Y(n2548) );
AOI222X1TS U1966 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2575), .C1(DmP_mant_SHT1_SW[31]), .Y(n2570) );
AOI222X1TS U1967 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2575), .C1(DmP_mant_SHT1_SW[33]), .Y(n2653) );
AOI222X1TS U1968 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2497), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2631), .C0(n2563), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2647) );
AOI222X1TS U1969 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2631), .B0(n2563), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2575), .C1(DmP_mant_SHT1_SW[34]), .Y(n2590) );
AO22XLTS U1970 ( .A0(n2702), .A1(busy), .B0(n2701), .B1(Shift_reg_FLAGS_7[3]), .Y(n1788) );
AO22XLTS U1971 ( .A0(n2780), .A1(DmP_EXP_EWSW[48]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[48]), .Y(n1203) );
AO22XLTS U1972 ( .A0(n2780), .A1(DmP_EXP_EWSW[44]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[44]), .Y(n1211) );
AO22XLTS U1973 ( .A0(n2783), .A1(DmP_EXP_EWSW[38]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1223) );
AO22XLTS U1974 ( .A0(n2783), .A1(DmP_EXP_EWSW[36]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[36]), .Y(n1227) );
AO22XLTS U1975 ( .A0(n2783), .A1(DmP_EXP_EWSW[31]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1237) );
AO22XLTS U1976 ( .A0(n2783), .A1(DmP_EXP_EWSW[29]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[29]), .Y(n1241) );
AO22XLTS U1977 ( .A0(n2771), .A1(DmP_EXP_EWSW[15]), .B0(n2769), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1269) );
AO22XLTS U1978 ( .A0(n2768), .A1(DmP_EXP_EWSW[11]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1277) );
AO22XLTS U1979 ( .A0(n2768), .A1(DmP_EXP_EWSW[13]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1273) );
AO22XLTS U1980 ( .A0(n2768), .A1(DmP_EXP_EWSW[12]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1275) );
AO22XLTS U1981 ( .A0(n3002), .A1(n1878), .B0(n3009), .B1(DmP_mant_SFG_SWR[1]), .Y(n1125) );
AO22XLTS U1982 ( .A0(n2768), .A1(DmP_EXP_EWSW[5]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1289) );
AO22XLTS U1983 ( .A0(n2768), .A1(DmP_EXP_EWSW[7]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1285) );
AO22XLTS U1984 ( .A0(n2768), .A1(DmP_EXP_EWSW[4]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1291) );
AO22XLTS U1985 ( .A0(n1822), .A1(n2731), .B0(n2759), .B1(
Shift_amount_SHT1_EWR[0]), .Y(n1594) );
AO22XLTS U1986 ( .A0(n2767), .A1(DmP_EXP_EWSW[1]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1297) );
AO22XLTS U1987 ( .A0(n2780), .A1(DmP_EXP_EWSW[42]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[42]), .Y(n1215) );
AO22XLTS U1988 ( .A0(n2780), .A1(DmP_EXP_EWSW[40]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[40]), .Y(n1219) );
AO22XLTS U1989 ( .A0(n2783), .A1(DmP_EXP_EWSW[33]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1233) );
AOI2BB2XLTS U1990 ( .B0(Raw_mant_NRM_SWR[48]), .B1(n2582), .A0N(n2515),
.A1N(n2651), .Y(n2516) );
AO22XLTS U1991 ( .A0(n2780), .A1(DmP_EXP_EWSW[47]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1205) );
AO22XLTS U1992 ( .A0(n2780), .A1(DmP_EXP_EWSW[45]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1209) );
AO22XLTS U1993 ( .A0(n2783), .A1(DmP_EXP_EWSW[35]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1229) );
AO22XLTS U1994 ( .A0(n2771), .A1(DmP_EXP_EWSW[19]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1261) );
AO22XLTS U1995 ( .A0(n2771), .A1(DmP_EXP_EWSW[17]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1265) );
AOI2BB2XLTS U1996 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n2724), .A0N(n2593), .A1N(
n2651), .Y(n2543) );
AOI2BB2XLTS U1997 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[45]), .A0N(n2629),
.A1N(n2660), .Y(n2603) );
AOI2BB2XLTS U1998 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[41]), .A0N(n2614),
.A1N(n2643), .Y(n2605) );
AO22XLTS U1999 ( .A0(n2719), .A1(Data_Y[59]), .B0(n2720), .B1(intDY_EWSW[59]), .Y(n1659) );
AO22XLTS U2000 ( .A0(n2719), .A1(Data_X[0]), .B0(n2718), .B1(intDX_EWSW[0]),
.Y(n1784) );
AO22XLTS U2001 ( .A0(n2711), .A1(Data_X[6]), .B0(n2710), .B1(intDX_EWSW[6]),
.Y(n1778) );
AOI2BB2XLTS U2002 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[39]), .A0N(n2617),
.A1N(n2643), .Y(n2612) );
AOI2BB2XLTS U2003 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2644),
.A1N(n2643), .Y(n2645) );
AO22XLTS U2004 ( .A0(n2715), .A1(Data_X[9]), .B0(n2710), .B1(intDX_EWSW[9]),
.Y(n1775) );
AO22XLTS U2005 ( .A0(n2705), .A1(Data_X[39]), .B0(n2713), .B1(intDX_EWSW[39]), .Y(n1745) );
AO22XLTS U2006 ( .A0(n2711), .A1(Data_X[4]), .B0(n2712), .B1(intDX_EWSW[4]),
.Y(n1780) );
OAI211XLTS U2007 ( .A0(n2607), .A1(n2656), .B0(n2602), .C0(n2601), .Y(n1628)
);
AOI2BB2XLTS U2008 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2600),
.A1N(n2643), .Y(n2601) );
AOI2BB2XLTS U2009 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2607),
.A1N(n2643), .Y(n2608) );
AO22XLTS U2010 ( .A0(n2705), .A1(Data_Y[63]), .B0(n2720), .B1(intDY_EWSW[63]), .Y(n1655) );
AOI2BB2XLTS U2011 ( .B0(n2802), .B1(intadd_72_SUM_41_), .A0N(
Raw_mant_NRM_SWR[52]), .A1N(n2801), .Y(n1131) );
OAI211XLTS U2012 ( .A0(n2548), .A1(n2589), .B0(n2547), .C0(n2546), .Y(n1627)
);
AOI2BB2XLTS U2013 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n2582), .A0N(n2545),
.A1N(n2665), .Y(n2546) );
AO22XLTS U2014 ( .A0(n2994), .A1(n1907), .B0(n2761), .B1(DmP_mant_SFG_SWR[0]), .Y(n1122) );
AO22XLTS U2015 ( .A0(n2767), .A1(DmP_EXP_EWSW[0]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22XLTS U2016 ( .A0(n2767), .A1(DmP_EXP_EWSW[2]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1295) );
AO22XLTS U2017 ( .A0(n2768), .A1(DmP_EXP_EWSW[8]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1283) );
AO22XLTS U2018 ( .A0(n2768), .A1(DmP_EXP_EWSW[3]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1293) );
AO22XLTS U2019 ( .A0(n2768), .A1(DmP_EXP_EWSW[6]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1287) );
AO22XLTS U2020 ( .A0(n2768), .A1(DmP_EXP_EWSW[9]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1281) );
AO22XLTS U2021 ( .A0(n2771), .A1(DmP_EXP_EWSW[16]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1267) );
AO22XLTS U2022 ( .A0(n2771), .A1(DmP_EXP_EWSW[25]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1249) );
AO22XLTS U2023 ( .A0(n2783), .A1(DmP_EXP_EWSW[34]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1231) );
AOI222X1TS U2024 ( .A0(n2418), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n2753), .C0(intDY_EWSW[52]), .C1(n1795), .Y(n2419) );
AO22XLTS U2025 ( .A0(n2771), .A1(DmP_EXP_EWSW[18]), .B0(n3228), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1263) );
AO22XLTS U2026 ( .A0(n2771), .A1(DmP_EXP_EWSW[20]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1259) );
AO22XLTS U2027 ( .A0(n2771), .A1(DmP_EXP_EWSW[22]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1255) );
AO22XLTS U2028 ( .A0(n2771), .A1(DmP_EXP_EWSW[24]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[24]), .Y(n1251) );
AO22XLTS U2029 ( .A0(n2783), .A1(DmP_EXP_EWSW[27]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1245) );
AO22XLTS U2030 ( .A0(n2780), .A1(DmP_EXP_EWSW[46]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[46]), .Y(n1207) );
AO22XLTS U2031 ( .A0(n2717), .A1(Data_X[63]), .B0(n2718), .B1(intDX_EWSW[63]), .Y(n1721) );
AO22XLTS U2032 ( .A0(n1866), .A1(DMP_SHT2_EWSW[8]), .B0(n2763), .B1(
DMP_SFG[8]), .Y(n1485) );
AO22XLTS U2033 ( .A0(n2780), .A1(DmP_EXP_EWSW[49]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1201) );
AO22XLTS U2034 ( .A0(n2771), .A1(DmP_EXP_EWSW[21]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1257) );
AO22XLTS U2035 ( .A0(n2771), .A1(DmP_EXP_EWSW[26]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1247) );
AO22XLTS U2036 ( .A0(n2783), .A1(DmP_EXP_EWSW[28]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1243) );
AO22XLTS U2037 ( .A0(n2783), .A1(DmP_EXP_EWSW[30]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1239) );
AO22XLTS U2038 ( .A0(n2783), .A1(DmP_EXP_EWSW[37]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1225) );
AO22XLTS U2039 ( .A0(n2780), .A1(DmP_EXP_EWSW[39]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1221) );
AO22XLTS U2040 ( .A0(n2780), .A1(DmP_EXP_EWSW[41]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1217) );
AO22XLTS U2041 ( .A0(n2780), .A1(DmP_EXP_EWSW[43]), .B0(n2772), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1213) );
AO22XLTS U2042 ( .A0(n2768), .A1(DmP_EXP_EWSW[10]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1279) );
AO22XLTS U2043 ( .A0(n2768), .A1(DmP_EXP_EWSW[14]), .B0(n2782), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1271) );
AO22XLTS U2044 ( .A0(n2771), .A1(DmP_EXP_EWSW[23]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1253) );
AO22XLTS U2045 ( .A0(n2783), .A1(DmP_EXP_EWSW[32]), .B0(n2781), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1235) );
AOI2BB2XLTS U2046 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n2582), .A0N(n2648),
.A1N(n2651), .Y(n2521) );
AOI2BB2XLTS U2047 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2648),
.A1N(n2660), .Y(n2649) );
AOI2BB2XLTS U2048 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n2582), .A0N(n2566),
.A1N(n2665), .Y(n2526) );
OAI211XLTS U2049 ( .A0(n2666), .A1(n2665), .B0(n2664), .C0(n2663), .Y(n1649)
);
AOI2BB2XLTS U2050 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n2662), .A0N(n2661),
.A1N(n2660), .Y(n2663) );
OAI211XLTS U2051 ( .A0(n2585), .A1(n2589), .B0(n2584), .C0(n2583), .Y(n1648)
);
AOI2BB2XLTS U2052 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n2582), .A0N(n2581), .A1N(
n2665), .Y(n2583) );
AOI2BB2XLTS U2053 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n2724), .A0N(n2558),
.A1N(n2665), .Y(n2559) );
AOI2BB2XLTS U2054 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n2582), .A0N(n2561),
.A1N(n2665), .Y(n2549) );
AOI2BB2XLTS U2055 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2657),
.A1N(n2643), .Y(n2615) );
AOI2BB2XLTS U2056 ( .B0(n2658), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2652),
.A1N(n2660), .Y(n2495) );
AOI2BB2XLTS U2057 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2639),
.A1N(n2660), .Y(n2640) );
OAI211XLTS U2058 ( .A0(n2661), .A1(n2651), .B0(n2634), .C0(n2633), .Y(n1647)
);
AOI2BB2XLTS U2059 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2632),
.A1N(n2660), .Y(n2633) );
AO22XLTS U2060 ( .A0(n2719), .A1(Data_Y[62]), .B0(n2718), .B1(intDY_EWSW[62]), .Y(n1656) );
AO22XLTS U2061 ( .A0(n2719), .A1(Data_Y[60]), .B0(n2720), .B1(intDY_EWSW[60]), .Y(n1658) );
AO22XLTS U2062 ( .A0(n2717), .A1(Data_Y[58]), .B0(n2720), .B1(intDY_EWSW[58]), .Y(n1660) );
AOI2BB2XLTS U2063 ( .B0(n2800), .B1(intadd_72_SUM_40_), .A0N(
Raw_mant_NRM_SWR[51]), .A1N(n2801), .Y(n1132) );
AOI2BB2XLTS U2064 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[19]), .A0N(n2622),
.A1N(n2660), .Y(n2623) );
AO22XLTS U2065 ( .A0(n2715), .A1(Data_X[24]), .B0(n2712), .B1(intDX_EWSW[24]), .Y(n1760) );
AO22XLTS U2066 ( .A0(n2705), .A1(Data_X[2]), .B0(n2704), .B1(intDX_EWSW[2]),
.Y(n1782) );
AO22XLTS U2067 ( .A0(n2719), .A1(Data_X[32]), .B0(n2713), .B1(intDX_EWSW[32]), .Y(n1752) );
AO22XLTS U2068 ( .A0(n2715), .A1(Data_X[16]), .B0(n2710), .B1(intDX_EWSW[16]), .Y(n1768) );
AO22XLTS U2069 ( .A0(n2714), .A1(Data_X[7]), .B0(n2710), .B1(intDX_EWSW[7]),
.Y(n1777) );
AO22XLTS U2070 ( .A0(n2714), .A1(Data_X[10]), .B0(n2710), .B1(intDX_EWSW[10]), .Y(n1774) );
AO22XLTS U2071 ( .A0(n2719), .A1(Data_X[48]), .B0(n2718), .B1(intDX_EWSW[48]), .Y(n1736) );
AO22XLTS U2072 ( .A0(n2705), .A1(Data_X[40]), .B0(n2713), .B1(intDX_EWSW[40]), .Y(n1744) );
AO22XLTS U2073 ( .A0(n2714), .A1(Data_X[1]), .B0(n2704), .B1(intDX_EWSW[1]),
.Y(n1783) );
AO22XLTS U2074 ( .A0(n2719), .A1(Data_X[47]), .B0(n2718), .B1(intDX_EWSW[47]), .Y(n1737) );
AO22XLTS U2075 ( .A0(n2705), .A1(Data_X[37]), .B0(n2713), .B1(intDX_EWSW[37]), .Y(n1747) );
AO22XLTS U2076 ( .A0(n2705), .A1(Data_X[44]), .B0(n2718), .B1(intDX_EWSW[44]), .Y(n1740) );
AO22XLTS U2077 ( .A0(n2717), .A1(Data_X[52]), .B0(n2718), .B1(intDX_EWSW[52]), .Y(n1732) );
OAI211XLTS U2078 ( .A0(n2545), .A1(n2660), .B0(n2525), .C0(n2524), .Y(n1629)
);
AOI2BB2XLTS U2079 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n2582), .A0N(n2573),
.A1N(n2665), .Y(n2524) );
AO22XLTS U2080 ( .A0(n2705), .A1(Data_X[38]), .B0(n2713), .B1(intDX_EWSW[38]), .Y(n1746) );
AOI2BB2XLTS U2081 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n2724), .A0N(n2570),
.A1N(n2665), .Y(n2571) );
AOI2BB2XLTS U2082 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n2582), .A0N(n2597),
.A1N(n2651), .Y(n2519) );
AOI2BB2XLTS U2083 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2597),
.A1N(n2643), .Y(n2598) );
AOI2BB2XLTS U2084 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[21]), .A0N(n2625),
.A1N(n2660), .Y(n2610) );
AOI2BB2XLTS U2085 ( .B0(n2800), .B1(intadd_72_SUM_37_), .A0N(
Raw_mant_NRM_SWR[48]), .A1N(n2801), .Y(n1135) );
AO22XLTS U2086 ( .A0(n2715), .A1(Data_X[5]), .B0(n2710), .B1(intDX_EWSW[5]),
.Y(n1779) );
AOI2BB2XLTS U2087 ( .B0(n2800), .B1(intadd_72_SUM_34_), .A0N(
Raw_mant_NRM_SWR[45]), .A1N(n2801), .Y(n1138) );
OAI211XLTS U2088 ( .A0(n2666), .A1(n2643), .B0(n2510), .C0(n2509), .Y(n1651)
);
AO22XLTS U2089 ( .A0(n2701), .A1(n2801), .B0(n2702), .B1(
Shift_reg_FLAGS_7[3]), .Y(n1787) );
OAI21XLTS U2090 ( .A0(n2800), .A1(n3144), .B0(n2423), .Y(n1129) );
MX2X1TS U2091 ( .A(n2865), .B(n2864), .S0(n2422), .Y(n2423) );
OAI211XLTS U2092 ( .A0(n2651), .A1(n2596), .B0(n2595), .C0(n2594), .Y(n1652)
);
AOI2BB1XLTS U2093 ( .A0N(n2593), .A1N(n2643), .B0(n2662), .Y(n2594) );
OAI21XLTS U2094 ( .A0(n3152), .A1(n2505), .B0(n2468), .Y(n1653) );
OAI21XLTS U2095 ( .A0(n2643), .A1(n2596), .B0(n2493), .Y(n1654) );
OAI211XLTS U2096 ( .A0(n2657), .A1(n2656), .B0(n2655), .C0(n2654), .Y(n1635)
);
AOI2BB2XLTS U2097 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2653),
.A1N(n2660), .Y(n2654) );
OAI211XLTS U2098 ( .A0(n2586), .A1(n2589), .B0(n2569), .C0(n2568), .Y(n1638)
);
AOI2BB2XLTS U2099 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n2724), .A0N(n2567),
.A1N(n2665), .Y(n2568) );
OAI211XLTS U2100 ( .A0(n2590), .A1(n2589), .B0(n2588), .C0(n2587), .Y(n1636)
);
AOI2BB2XLTS U2101 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n2724), .A0N(n2586),
.A1N(n2665), .Y(n2587) );
AO22XLTS U2102 ( .A0(n2010), .A1(n3010), .B0(final_result_ieee[51]), .B1(
n2929), .Y(n1051) );
AO22XLTS U2103 ( .A0(n2010), .A1(n3007), .B0(final_result_ieee[50]), .B1(
n2901), .Y(n1052) );
AO22XLTS U2104 ( .A0(n2010), .A1(n3005), .B0(final_result_ieee[49]), .B1(
n2929), .Y(n1053) );
AO22XLTS U2105 ( .A0(n2010), .A1(n2804), .B0(final_result_ieee[0]), .B1(
n2929), .Y(n1054) );
AO22XLTS U2106 ( .A0(n2010), .A1(n3003), .B0(final_result_ieee[47]), .B1(
n2901), .Y(n1055) );
AO22XLTS U2107 ( .A0(n2010), .A1(n2806), .B0(final_result_ieee[3]), .B1(
n2929), .Y(n1060) );
AO22XLTS U2108 ( .A0(n2010), .A1(n2808), .B0(final_result_ieee[1]), .B1(
n2901), .Y(n1061) );
AO22XLTS U2109 ( .A0(n2010), .A1(n3004), .B0(final_result_ieee[48]), .B1(
n2929), .Y(n1062) );
AO22XLTS U2110 ( .A0(n2010), .A1(n2810), .B0(final_result_ieee[2]), .B1(
n2901), .Y(n1063) );
AO22XLTS U2111 ( .A0(n2010), .A1(n3001), .B0(final_result_ieee[46]), .B1(
n2901), .Y(n1070) );
AO22XLTS U2112 ( .A0(n2010), .A1(n2812), .B0(final_result_ieee[4]), .B1(
n2901), .Y(n1071) );
AO22XLTS U2113 ( .A0(n2010), .A1(n2998), .B0(final_result_ieee[43]), .B1(
n2901), .Y(n1072) );
AO22XLTS U2114 ( .A0(n2010), .A1(n2978), .B0(final_result_ieee[27]), .B1(
n2929), .Y(n1075) );
AO22XLTS U2115 ( .A0(n2010), .A1(n2974), .B0(final_result_ieee[23]), .B1(
n2901), .Y(n1076) );
AO22XLTS U2116 ( .A0(n2903), .A1(n2902), .B0(final_result_ieee[7]), .B1(
n2901), .Y(n1077) );
AO22XLTS U2117 ( .A0(n2903), .A1(n3000), .B0(final_result_ieee[45]), .B1(
n2901), .Y(n1078) );
AO22XLTS U2118 ( .A0(n2903), .A1(n2980), .B0(final_result_ieee[29]), .B1(
n2901), .Y(n1081) );
AO22XLTS U2119 ( .A0(n2903), .A1(n2972), .B0(final_result_ieee[21]), .B1(
n2901), .Y(n1082) );
AO22XLTS U2120 ( .A0(n2903), .A1(n2881), .B0(final_result_ieee[5]), .B1(
n2901), .Y(n1083) );
AO22XLTS U2121 ( .A0(n2903), .A1(n2999), .B0(final_result_ieee[44]), .B1(
n2901), .Y(n1084) );
AO22XLTS U2122 ( .A0(n2903), .A1(n2878), .B0(final_result_ieee[6]), .B1(
n2901), .Y(n1085) );
AO22XLTS U2123 ( .A0(n2903), .A1(n2995), .B0(final_result_ieee[41]), .B1(
n2901), .Y(n1086) );
AO22XLTS U2124 ( .A0(n2903), .A1(n2960), .B0(final_result_ieee[9]), .B1(
n2901), .Y(n1087) );
AO22XLTS U2125 ( .A0(n2903), .A1(n2976), .B0(final_result_ieee[25]), .B1(
n2929), .Y(n1088) );
AO22XLTS U2126 ( .A0(n2903), .A1(n2979), .B0(final_result_ieee[28]), .B1(
n2929), .Y(n1092) );
AO22XLTS U2127 ( .A0(n2903), .A1(n2973), .B0(final_result_ieee[22]), .B1(
n2929), .Y(n1093) );
AO22XLTS U2128 ( .A0(n2903), .A1(n2996), .B0(final_result_ieee[42]), .B1(
n2901), .Y(n1095) );
AO22XLTS U2129 ( .A0(n2903), .A1(n2977), .B0(final_result_ieee[26]), .B1(
n2901), .Y(n1098) );
AO22XLTS U2130 ( .A0(n2903), .A1(n2975), .B0(final_result_ieee[24]), .B1(
n2901), .Y(n1099) );
AO22XLTS U2131 ( .A0(n2010), .A1(n1980), .B0(final_result_ieee[8]), .B1(
n2901), .Y(n1100) );
AO22XLTS U2132 ( .A0(n2755), .A1(n2754), .B0(ZERO_FLAG_EXP), .B1(n2753), .Y(
n1513) );
OAI211XLTS U2133 ( .A0(n2629), .A1(n2651), .B0(n2628), .C0(n2627), .Y(n1643)
);
AOI2BB2XLTS U2134 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[43]), .A0N(n2626),
.A1N(n2643), .Y(n2627) );
OAI211XLTS U2135 ( .A0(n2558), .A1(n2589), .B0(n2542), .C0(n2541), .Y(n1644)
);
AOI2BB2XLTS U2136 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n2724), .A0N(n2540), .A1N(
n2651), .Y(n2541) );
OAI211XLTS U2137 ( .A0(n2540), .A1(n2589), .B0(n2539), .C0(n2538), .Y(n1646)
);
AOI2BB2XLTS U2138 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n2724), .A0N(n2585), .A1N(
n2656), .Y(n2538) );
OAI211XLTS U2139 ( .A0(n2518), .A1(n2651), .B0(n2481), .C0(n2480), .Y(n1603)
);
OAI211XLTS U2140 ( .A0(n2566), .A1(n2589), .B0(n2565), .C0(n2564), .Y(n1613)
);
AOI2BB2XLTS U2141 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n2582), .A0N(n2579),
.A1N(n2665), .Y(n2564) );
OAI211XLTS U2142 ( .A0(n2579), .A1(n2589), .B0(n2578), .C0(n2577), .Y(n1615)
);
AOI2BB2XLTS U2143 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n2582), .A0N(n2619),
.A1N(n2665), .Y(n2577) );
AOI2BB2XLTS U2144 ( .B0(n2658), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2642),
.A1N(n2660), .Y(n2500) );
OAI211XLTS U2145 ( .A0(n2622), .A1(n2651), .B0(n2621), .C0(n2620), .Y(n1617)
);
AOI2BB2XLTS U2146 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2619),
.A1N(n2660), .Y(n2620) );
OAI211XLTS U2147 ( .A0(n2531), .A1(n2589), .B0(n2530), .C0(n2529), .Y(n1618)
);
AOI2BB2XLTS U2148 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n2582), .A0N(n2557),
.A1N(n2665), .Y(n2529) );
OAI211XLTS U2149 ( .A0(n2557), .A1(n2589), .B0(n2556), .C0(n2555), .Y(n1620)
);
AOI2BB2XLTS U2150 ( .B0(Raw_mant_NRM_SWR[33]), .B1(n2582), .A0N(n2554),
.A1N(n2665), .Y(n2555) );
OAI211XLTS U2151 ( .A0(n2554), .A1(n2589), .B0(n2553), .C0(n2552), .Y(n1622)
);
AOI2BB2XLTS U2152 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n2582), .A0N(n2551),
.A1N(n2665), .Y(n2552) );
OAI211XLTS U2153 ( .A0(n2638), .A1(n2651), .B0(n2637), .C0(n2636), .Y(n1623)
);
AOI2BB2XLTS U2154 ( .B0(n2662), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2635),
.A1N(n2660), .Y(n2636) );
OAI211XLTS U2155 ( .A0(n2548), .A1(n2651), .B0(n2503), .C0(n2502), .Y(n1625)
);
AOI2BB2XLTS U2156 ( .B0(n2658), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2638),
.A1N(n2660), .Y(n2502) );
OAI211XLTS U2157 ( .A0(n2570), .A1(n2660), .B0(n2533), .C0(n2532), .Y(n1633)
);
AOI2BB2XLTS U2158 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n2724), .A0N(n2653),
.A1N(n2665), .Y(n2532) );
OAI211XLTS U2159 ( .A0(n2590), .A1(n2651), .B0(n2499), .C0(n2498), .Y(n1634)
);
AOI2BB2XLTS U2160 ( .B0(n2658), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2647),
.A1N(n2643), .Y(n2498) );
OR2X1TS U2161 ( .A(n1837), .B(n1838), .Y(n1808) );
OAI221X1TS U2162 ( .A0(n3047), .A1(intDX_EWSW[27]), .B0(n3167), .B1(
intDX_EWSW[26]), .C0(n2259), .Y(n2262) );
AOI222X1TS U2163 ( .A0(n2821), .A1(n2958), .B0(n2822), .B1(n1958), .C0(n2823), .C1(n2940), .Y(n2981) );
AOI222X1TS U2164 ( .A0(n2821), .A1(n3068), .B0(n2822), .B1(n2939), .C0(n2823), .C1(n2938), .Y(n2971) );
AOI211X4TS U2165 ( .A0(n2947), .A1(n2823), .B0(n1896), .C0(n1895), .Y(n1906)
);
OAI21X1TS U2166 ( .A0(n3208), .A1(n1918), .B0(n1917), .Y(n1919) );
OAI21X1TS U2167 ( .A0(n3209), .A1(n1918), .B0(n1910), .Y(n1911) );
OAI211XLTS U2168 ( .A0(n2514), .A1(n2651), .B0(n2476), .C0(n2475), .Y(n1602)
);
NAND2X4TS U2169 ( .A(n2689), .B(n3236), .Y(n2695) );
NOR4X2TS U2170 ( .A(n2080), .B(n2148), .C(n2160), .D(n2152), .Y(n2205) );
BUFX4TS U2171 ( .A(n3280), .Y(n3261) );
BUFX4TS U2172 ( .A(n3260), .Y(n3257) );
BUFX4TS U2173 ( .A(n3255), .Y(n3253) );
BUFX4TS U2174 ( .A(n3240), .Y(n3275) );
BUFX4TS U2175 ( .A(n3280), .Y(n3266) );
BUFX4TS U2176 ( .A(n3260), .Y(n3272) );
BUFX4TS U2177 ( .A(n1796), .Y(n3278) );
INVX4TS U2178 ( .A(n1987), .Y(n2831) );
CLKINVX6TS U2179 ( .A(n1987), .Y(n2883) );
BUFX4TS U2180 ( .A(n2759), .Y(n2758) );
BUFX6TS U2181 ( .A(n3228), .Y(n2759) );
BUFX4TS U2182 ( .A(n3267), .Y(n3271) );
BUFX4TS U2183 ( .A(n3240), .Y(n3277) );
BUFX4TS U2184 ( .A(n3251), .Y(n3259) );
BUFX4TS U2185 ( .A(n3267), .Y(n3264) );
BUFX4TS U2186 ( .A(n1865), .Y(n3260) );
BUFX4TS U2187 ( .A(n3280), .Y(n3258) );
BUFX4TS U2188 ( .A(n3260), .Y(n3268) );
BUFX4TS U2189 ( .A(n3244), .Y(n3270) );
BUFX4TS U2190 ( .A(n1801), .Y(n3262) );
BUFX4TS U2191 ( .A(n1865), .Y(n3280) );
NOR2X2TS U2192 ( .A(OP_FLAG_SFG), .B(n2796), .Y(n2421) );
BUFX4TS U2193 ( .A(n1802), .Y(n3250) );
BUFX3TS U2194 ( .A(n1799), .Y(n1821) );
BUFX4TS U2195 ( .A(n1802), .Y(n3245) );
BUFX4TS U2196 ( .A(n1799), .Y(n3252) );
BUFX4TS U2197 ( .A(n1802), .Y(n3242) );
BUFX4TS U2198 ( .A(n1801), .Y(n3237) );
BUFX4TS U2199 ( .A(n1803), .Y(n3239) );
OAI22X2TS U2200 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2914), .B0(n3185), .B1(
n1989), .Y(n2915) );
OAI22X2TS U2201 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2921), .B0(n3197), .B1(
n1989), .Y(n2930) );
OAI22X2TS U2202 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2819), .B0(n3199), .B1(
n1989), .Y(n2827) );
XNOR2X2TS U2203 ( .A(DMP_exp_NRM2_EW[10]), .B(n1939), .Y(n1970) );
NOR2X4TS U2204 ( .A(n2470), .B(n2469), .Y(n2722) );
CLKINVX6TS U2205 ( .A(n2788), .Y(n2787) );
BUFX6TS U2206 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2788) );
BUFX6TS U2207 ( .A(n2576), .Y(n2563) );
AOI2BB2X2TS U2208 ( .B0(DmP_mant_SFG_SWR[10]), .B1(OP_FLAG_SFG), .A0N(n2798),
.A1N(DmP_mant_SFG_SWR[10]), .Y(n2793) );
AOI222X1TS U2209 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2618), .B0(n2576), .B1(
DmP_mant_SHT1_SW[16]), .C0(n2575), .C1(DmP_mant_SHT1_SW[15]), .Y(n2619) );
AOI222X1TS U2210 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2618), .B0(n2630), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2562), .C1(DmP_mant_SHT1_SW[12]), .Y(n2639) );
AOI222X1TS U2211 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n1797), .B0(n2576), .B1(
DmP_mant_SHT1_SW[6]), .C0(n2562), .C1(DmP_mant_SHT1_SW[5]), .Y(n2515)
);
AOI222X1TS U2212 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n1797), .B0(n2576), .B1(
DmP_mant_SHT1_SW[7]), .C0(n2575), .C1(DmP_mant_SHT1_SW[6]), .Y(n2523)
);
CLKAND2X4TS U2213 ( .A(n2775), .B(n2219), .Y(n2346) );
OAI222X1TS U2214 ( .A0(n2774), .A1(n3223), .B0(n3064), .B1(n2775), .C0(n3014), .C1(n2776), .Y(n1524) );
OAI222X1TS U2215 ( .A0(n2774), .A1(n3069), .B0(n3066), .B1(n2775), .C0(n1820), .C1(n2776), .Y(n1523) );
OAI222X1TS U2216 ( .A0(n2774), .A1(n3224), .B0(n3067), .B1(n2775), .C0(n3013), .C1(n2776), .Y(n1522) );
CLKINVX3TS U2217 ( .A(n2753), .Y(n2775) );
OAI211XLTS U2218 ( .A0(n2514), .A1(n2589), .B0(n2513), .C0(n2512), .Y(n1604)
);
OAI211XLTS U2219 ( .A0(n2518), .A1(n2589), .B0(n2517), .C0(n2516), .Y(n1605)
);
OAI211XLTS U2220 ( .A0(n2523), .A1(n2651), .B0(n2485), .C0(n2484), .Y(n1606)
);
OAI211XLTS U2221 ( .A0(n2515), .A1(n2589), .B0(n2507), .C0(n2506), .Y(n1607)
);
CLKINVX3TS U2222 ( .A(n2759), .Y(n1822) );
CLKINVX6TS U2223 ( .A(left_right_SHT2), .Y(n2953) );
BUFX6TS U2224 ( .A(left_right_SHT2), .Y(n2958) );
BUFX4TS U2225 ( .A(n2651), .Y(n2665) );
INVX3TS U2226 ( .A(n2760), .Y(n2785) );
BUFX4TS U2227 ( .A(n2383), .Y(n2700) );
BUFX6TS U2228 ( .A(n2383), .Y(n2412) );
BUFX4TS U2229 ( .A(n2383), .Y(n2408) );
CLKINVX6TS U2230 ( .A(n3236), .Y(n2901) );
CLKINVX3TS U2231 ( .A(n2346), .Y(n2385) );
INVX4TS U2232 ( .A(n2346), .Y(n2376) );
BUFX6TS U2233 ( .A(n2753), .Y(n2388) );
BUFX6TS U2234 ( .A(n1864), .Y(n2753) );
CLKINVX6TS U2235 ( .A(n3236), .Y(n2929) );
INVX3TS U2236 ( .A(n2796), .Y(n2800) );
CLKINVX6TS U2237 ( .A(n2591), .Y(n2575) );
BUFX6TS U2238 ( .A(n1963), .Y(n2943) );
INVX4TS U2239 ( .A(n2997), .Y(n3006) );
INVX4TS U2240 ( .A(n2991), .Y(n3009) );
INVX4TS U2241 ( .A(n2991), .Y(n2992) );
INVX6TS U2242 ( .A(n2773), .Y(n2418) );
INVX3TS U2243 ( .A(n2814), .Y(n2862) );
NAND2X4TS U2244 ( .A(n2802), .B(OP_FLAG_SFG), .Y(n2865) );
INVX4TS U2245 ( .A(n3225), .Y(n2802) );
BUFX6TS U2246 ( .A(n2918), .Y(n2944) );
BUFX6TS U2247 ( .A(n1902), .Y(n2945) );
INVX2TS U2248 ( .A(n1817), .Y(n1823) );
AOI22X2TS U2249 ( .A0(Data_array_SWR[40]), .A1(n2849), .B0(
Data_array_SWR[36]), .B1(n2831), .Y(n2922) );
INVX2TS U2250 ( .A(n1812), .Y(n1824) );
INVX2TS U2251 ( .A(n1811), .Y(n1825) );
OAI211XLTS U2252 ( .A0(n2632), .A1(n2665), .B0(n2604), .C0(n2603), .Y(n1645)
);
OAI211XLTS U2253 ( .A0(n2626), .A1(n2656), .B0(n2606), .C0(n2605), .Y(n1641)
);
INVX2TS U2254 ( .A(n1816), .Y(n1826) );
INVX2TS U2255 ( .A(n1813), .Y(n1827) );
AOI32X1TS U2256 ( .A0(n3181), .A1(n2150), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3054), .Y(n2151) );
OAI221XLTS U2257 ( .A0(n3182), .A1(intDY_EWSW[60]), .B0(n3054), .B1(
intDY_EWSW[59]), .C0(n2232), .Y(n2233) );
AOI211X1TS U2258 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2437), .B0(
Raw_mant_NRM_SWR[48]), .C0(Raw_mant_NRM_SWR[47]), .Y(n2440) );
NOR4X2TS U2259 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .D(n2045), .Y(n2037) );
NOR3XLTS U2260 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n2046) );
NOR2X1TS U2261 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2062)
);
OAI2BB2XLTS U2262 ( .B0(n2069), .B1(n3128), .A0N(n2030), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n2032) );
OAI221XLTS U2263 ( .A0(n3175), .A1(intDX_EWSW[0]), .B0(n3051), .B1(
intDX_EWSW[8]), .C0(n2284), .Y(n2285) );
OAI221X1TS U2264 ( .A0(n3204), .A1(intDX_EWSW[7]), .B0(n3062), .B1(
intDX_EWSW[6]), .C0(n2281), .Y(n2288) );
AOI32X1TS U2265 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2030), .A2(n3128), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2030), .Y(n2021) );
INVX2TS U2266 ( .A(n1819), .Y(n1828) );
INVX2TS U2267 ( .A(n1810), .Y(n1829) );
INVX2TS U2268 ( .A(n1809), .Y(n1830) );
OAI211XLTS U2269 ( .A0(n2614), .A1(n2651), .B0(n2613), .C0(n2612), .Y(n1639)
);
INVX2TS U2270 ( .A(n1807), .Y(n1831) );
OAI211XLTS U2271 ( .A0(n2647), .A1(n2656), .B0(n2646), .C0(n2645), .Y(n1632)
);
INVX2TS U2272 ( .A(n1815), .Y(n1832) );
INVX2TS U2273 ( .A(n1804), .Y(n1833) );
OAI221XLTS U2274 ( .A0(n3158), .A1(intDX_EWSW[9]), .B0(n3171), .B1(
intDX_EWSW[16]), .C0(n2276), .Y(n2277) );
AOI221X1TS U2275 ( .A0(n3214), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3187), .C0(n2251), .Y(n2254) );
AOI222X1TS U2276 ( .A0(intDX_EWSW[4]), .A1(n3050), .B0(intDX_EWSW[5]), .B1(
n3176), .C0(n2105), .C1(n2104), .Y(n2106) );
OAI221X1TS U2277 ( .A0(n3160), .A1(intDX_EWSW[13]), .B0(n3050), .B1(
intDX_EWSW[4]), .C0(n2274), .Y(n2279) );
AOI32X1TS U2278 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2059), .A2(n3103), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2059), .Y(n2039) );
INVX2TS U2279 ( .A(n1814), .Y(n1834) );
AOI21X2TS U2280 ( .A0(Data_array_SWR[19]), .A1(n2884), .B0(n1911), .Y(n2857)
);
AOI21X2TS U2281 ( .A0(Data_array_SWR[21]), .A1(n2884), .B0(n1919), .Y(n2839)
);
INVX2TS U2282 ( .A(n1805), .Y(n1835) );
INVX2TS U2283 ( .A(n1806), .Y(n1836) );
NOR2BX2TS U2284 ( .AN(n2059), .B(Raw_mant_NRM_SWR[9]), .Y(n2071) );
OAI211XLTS U2285 ( .A0(n2537), .A1(n2589), .B0(n2536), .C0(n2535), .Y(n1601)
);
NOR4X2TS U2286 ( .A(n2296), .B(n2295), .C(n2294), .D(n2293), .Y(n2755) );
NOR4X2TS U2287 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .C(
Raw_mant_NRM_SWR[52]), .D(Raw_mant_NRM_SWR[51]), .Y(n2014) );
NOR2XLTS U2288 ( .A(n2884), .B(n1901), .Y(n1837) );
NOR2XLTS U2289 ( .A(Data_array_SWR[18]), .B(n1901), .Y(n1838) );
OAI21X1TS U2290 ( .A0(n3207), .A1(n1918), .B0(n1900), .Y(n1901) );
BUFX4TS U2291 ( .A(n1799), .Y(n3241) );
OAI211X2TS U2292 ( .A0(intDY_EWSW[20]), .A1(n3119), .B0(n2265), .C0(n2096),
.Y(n2134) );
OAI211X2TS U2293 ( .A0(intDY_EWSW[12]), .A1(n3107), .B0(n2273), .C0(n2097),
.Y(n2125) );
XNOR2X2TS U2294 ( .A(DMP_exp_NRM2_EW[8]), .B(n1932), .Y(n2693) );
OAI211X2TS U2295 ( .A0(intDY_EWSW[28]), .A1(n3118), .B0(n2257), .C0(n2087),
.Y(n2142) );
XNOR2X2TS U2296 ( .A(DMP_exp_NRM2_EW[0]), .B(n1862), .Y(n2690) );
XNOR2X2TS U2297 ( .A(DMP_exp_NRM2_EW[9]), .B(n1935), .Y(n2694) );
XNOR2X2TS U2298 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J66_123_7955_n6), .Y(
n2691) );
CLKINVX3TS U2299 ( .A(n2591), .Y(n2562) );
AOI222X1TS U2300 ( .A0(n2910), .A1(n2953), .B0(n2909), .B1(n2938), .C0(n2908), .C1(n1958), .Y(n2962) );
AOI222X1TS U2301 ( .A0(n2897), .A1(n2953), .B0(n2896), .B1(n2938), .C0(n2895), .C1(n1958), .Y(n2964) );
AOI222X4TS U2302 ( .A0(n2923), .A1(n2958), .B0(n2924), .B1(n1958), .C0(n2925), .C1(n2940), .Y(n2983) );
AOI222X4TS U2303 ( .A0(n2941), .A1(n2958), .B0(n2946), .B1(n1958), .C0(n2948), .C1(n2940), .Y(n2982) );
AOI222X4TS U2304 ( .A0(n2844), .A1(n2958), .B0(n2843), .B1(n2940), .C0(n2842), .C1(n2939), .Y(n2993) );
AOI222X4TS U2305 ( .A0(n2860), .A1(n2958), .B0(n2859), .B1(n2940), .C0(n2858), .C1(n2939), .Y(n2989) );
AOI222X4TS U2306 ( .A0(n2910), .A1(n2958), .B0(n2909), .B1(n2940), .C0(n2908), .C1(n2939), .Y(n2990) );
BUFX4TS U2307 ( .A(n1957), .Y(n2939) );
BUFX3TS U2308 ( .A(n3228), .Y(n2779) );
INVX3TS U2309 ( .A(n2938), .Y(n2892) );
INVX3TS U2310 ( .A(n2940), .Y(n2898) );
BUFX6TS U2311 ( .A(OP_FLAG_SFG), .Y(n2798) );
XOR2XLTS U2312 ( .A(DMP_SFG[8]), .B(n2792), .Y(n2794) );
OAI211XLTS U2313 ( .A0(n2528), .A1(n2651), .B0(n2489), .C0(n2488), .Y(n1609)
);
OAI211XLTS U2314 ( .A0(n2523), .A1(n2589), .B0(n2522), .C0(n2521), .Y(n1608)
);
OAI211XLTS U2315 ( .A0(n2652), .A1(n2651), .B0(n2650), .C0(n2649), .Y(n1610)
);
OAI211XLTS U2316 ( .A0(n2528), .A1(n2589), .B0(n2527), .C0(n2526), .Y(n1611)
);
INVX4TS U2317 ( .A(n1795), .Y(n2774) );
INVX3TS U2318 ( .A(n2760), .Y(n2765) );
INVX3TS U2319 ( .A(n3236), .Y(n2959) );
BUFX6TS U2320 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3236) );
AOI22X2TS U2321 ( .A0(Data_array_SWR[35]), .A1(n2831), .B0(
Data_array_SWR[39]), .B1(n2849), .Y(n2937) );
NAND2X2TS U2322 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1918) );
NOR2X1TS U2323 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n2671) );
AOI22X2TS U2324 ( .A0(Data_array_SWR[38]), .A1(n2849), .B0(
Data_array_SWR[34]), .B1(n2831), .Y(n2820) );
OAI211XLTS U2325 ( .A0(n2561), .A1(n2589), .B0(n2560), .C0(n2559), .Y(n1642)
);
OAI211XLTS U2326 ( .A0(n2567), .A1(n2589), .B0(n2550), .C0(n2549), .Y(n1640)
);
OAI211XLTS U2327 ( .A0(n2617), .A1(n2656), .B0(n2616), .C0(n2615), .Y(n1637)
);
OAI211XLTS U2328 ( .A0(n2639), .A1(n2651), .B0(n2496), .C0(n2495), .Y(n1612)
);
OAI211XLTS U2329 ( .A0(n2642), .A1(n2651), .B0(n2641), .C0(n2640), .Y(n1614)
);
AOI22X2TS U2330 ( .A0(Data_array_SWR[33]), .A1(n2883), .B0(
Data_array_SWR[37]), .B1(n2849), .Y(n2899) );
NOR2BX1TS U2331 ( .AN(n2019), .B(Raw_mant_NRM_SWR[41]), .Y(n2444) );
OAI221X1TS U2332 ( .A0(n3053), .A1(intDY_EWSW[62]), .B0(n3180), .B1(
intDY_EWSW[61]), .C0(n2231), .Y(n2234) );
NOR2X2TS U2333 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3179), .Y(n2699) );
OAI221X1TS U2334 ( .A0(n3181), .A1(intDY_EWSW[58]), .B0(n3178), .B1(
intDX_EWSW[57]), .C0(n2229), .Y(n2236) );
OAI211XLTS U2335 ( .A0(n2625), .A1(n2651), .B0(n2624), .C0(n2623), .Y(n1619)
);
OAI221X1TS U2336 ( .A0(n3044), .A1(intDX_EWSW[17]), .B0(n3166), .B1(
intDX_EWSW[24]), .C0(n2268), .Y(n2269) );
OAI221X1TS U2337 ( .A0(n3048), .A1(intDX_EWSW[3]), .B0(n3162), .B1(
intDX_EWSW[2]), .C0(n2283), .Y(n2286) );
OAI221X1TS U2338 ( .A0(n3046), .A1(intDX_EWSW[25]), .B0(n3169), .B1(
intDX_EWSW[32]), .C0(n2260), .Y(n2261) );
AOI211XLTS U2339 ( .A0(intDX_EWSW[16]), .A1(n3171), .B0(n2129), .C0(n2135),
.Y(n2126) );
OAI221X1TS U2340 ( .A0(n3159), .A1(intDX_EWSW[10]), .B0(n3163), .B1(
intDX_EWSW[12]), .C0(n2275), .Y(n2278) );
OAI221X1TS U2341 ( .A0(n3161), .A1(intDX_EWSW[21]), .B0(n3170), .B1(
intDX_EWSW[48]), .C0(n2266), .Y(n2271) );
AOI211X2TS U2342 ( .A0(intDX_EWSW[44]), .A1(n3194), .B0(n2162), .C0(n2171),
.Y(n2169) );
AOI211X1TS U2343 ( .A0(intDX_EWSW[52]), .A1(n3206), .B0(n2079), .C0(n2194),
.Y(n2196) );
AOI222X1TS U2344 ( .A0(n1795), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n2753), .C0(intDY_EWSW[52]), .C1(n2416), .Y(n2417) );
AOI21X2TS U2345 ( .A0(Data_array_SWR[20]), .A1(n2884), .B0(n1882), .Y(n1985)
);
OAI211XLTS U2346 ( .A0(n2573), .A1(n2660), .B0(n2572), .C0(n2571), .Y(n1631)
);
OAI211XLTS U2347 ( .A0(n2551), .A1(n2589), .B0(n2520), .C0(n2519), .Y(n1624)
);
OAI211XLTS U2348 ( .A0(n2600), .A1(n2656), .B0(n2599), .C0(n2598), .Y(n1626)
);
OAI211XLTS U2349 ( .A0(n2635), .A1(n2651), .B0(n2611), .C0(n2610), .Y(n1621)
);
OAI221XLTS U2350 ( .A0(n3176), .A1(intDX_EWSW[5]), .B0(n3168), .B1(
intDX_EWSW[28]), .C0(n2282), .Y(n2287) );
OAI211XLTS U2351 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2678), .B0(n2446), .C0(
n2445), .Y(n2447) );
NAND2X2TS U2352 ( .A(shift_value_SHT2_EWR[4]), .B(n2831), .Y(n1989) );
OAI22X2TS U2353 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2936), .B0(n3198), .B1(
n1989), .Y(n2955) );
BUFX3TS U2354 ( .A(n3016), .Y(n1839) );
OAI21XLTS U2355 ( .A0(intDX_EWSW[1]), .A1(n3213), .B0(intDX_EWSW[0]), .Y(
n2100) );
OAI21XLTS U2356 ( .A0(intDY_EWSW[35]), .A1(n3032), .B0(intDY_EWSW[34]), .Y(
n2180) );
NOR2XLTS U2357 ( .A(n2197), .B(intDX_EWSW[48]), .Y(n2198) );
NOR2XLTS U2358 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2437) );
OAI21XLTS U2359 ( .A0(intDY_EWSW[31]), .A1(n3033), .B0(intDY_EWSW[30]), .Y(
n2092) );
NAND2X1TS U2360 ( .A(n2455), .B(n3072), .Y(n2045) );
NOR2XLTS U2361 ( .A(n2195), .B(n2194), .Y(n2208) );
AOI211XLTS U2362 ( .A0(intDY_EWSW[46]), .A1(n2175), .B0(n2174), .C0(n2173),
.Y(n2212) );
OAI21XLTS U2363 ( .A0(n3209), .A1(n1987), .B0(n1946), .Y(n1947) );
NAND2X1TS U2364 ( .A(n2429), .B(n3086), .Y(n2012) );
INVX2TS U2365 ( .A(n2674), .Y(n2022) );
OAI211XLTS U2366 ( .A0(n1808), .A1(n1870), .B0(n1904), .C0(n1903), .Y(n1905)
);
AOI31XLTS U2367 ( .A0(n2057), .A1(n3065), .A2(n3220), .B0(n2056), .Y(n2064)
);
NAND2X1TS U2368 ( .A(n2026), .B(n3096), .Y(n2067) );
OAI21XLTS U2369 ( .A0(DmP_EXP_EWSW[55]), .A1(n3067), .B0(n2743), .Y(n2740)
);
OAI211XLTS U2370 ( .A0(n3151), .A1(n2067), .B0(n2463), .C0(n2054), .Y(n2033)
);
OAI21XLTS U2371 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n2865), .B0(n2078), .Y(n1124) );
OAI21XLTS U2372 ( .A0(n3188), .A1(n1798), .B0(n2329), .Y(n1210) );
OAI21XLTS U2373 ( .A0(n3054), .A1(n2376), .B0(n2402), .Y(n1518) );
OAI21XLTS U2374 ( .A0(n3057), .A1(n2390), .B0(n2360), .Y(n1536) );
OAI21XLTS U2375 ( .A0(n3047), .A1(n2773), .B0(n2222), .Y(n1550) );
OAI21XLTS U2376 ( .A0(n3160), .A1(n2776), .B0(n2314), .Y(n1564) );
OAI211XLTS U2377 ( .A0(n2581), .A1(n2589), .B0(n2544), .C0(n2543), .Y(n1650)
);
OAI211XLTS U2378 ( .A0(n2531), .A1(n2651), .B0(n2501), .C0(n2500), .Y(n1616)
);
OAI211XLTS U2379 ( .A0(n2644), .A1(n2656), .B0(n2609), .C0(n2608), .Y(n1630)
);
BUFX3TS U2380 ( .A(n3260), .Y(n3256) );
BUFX3TS U2381 ( .A(n1865), .Y(n3265) );
BUFX3TS U2382 ( .A(n1796), .Y(n3263) );
BUFX3TS U2383 ( .A(n1799), .Y(n3248) );
BUFX3TS U2384 ( .A(n3280), .Y(n3254) );
BUFX3TS U2385 ( .A(n1802), .Y(n3249) );
BUFX3TS U2386 ( .A(n3280), .Y(n3279) );
BUFX3TS U2387 ( .A(n1803), .Y(n3251) );
BUFX3TS U2388 ( .A(n1803), .Y(n3247) );
BUFX3TS U2389 ( .A(n1796), .Y(n3276) );
BUFX3TS U2390 ( .A(n3239), .Y(n3269) );
BUFX3TS U2391 ( .A(n1802), .Y(n3274) );
BUFX3TS U2392 ( .A(n1799), .Y(n3238) );
BUFX3TS U2393 ( .A(n1803), .Y(n3246) );
BUFX3TS U2394 ( .A(n1801), .Y(n3243) );
BUFX3TS U2395 ( .A(n3260), .Y(n3273) );
AO22XLTS U2396 ( .A0(n3236), .A1(ZERO_FLAG_SHT1SHT2), .B0(n2929), .B1(
zero_flag), .Y(n1183) );
OAI21XLTS U2397 ( .A0(n2785), .A1(n2953), .B0(n2787), .Y(n1719) );
BUFX4TS U2398 ( .A(n1866), .Y(n2994) );
BUFX3TS U2399 ( .A(n1866), .Y(n2756) );
AO22XLTS U2400 ( .A0(n2994), .A1(DMP_SHT2_EWSW[60]), .B0(n2763), .B1(
DMP_SFG[60]), .Y(n1313) );
AO22XLTS U2401 ( .A0(n2997), .A1(DMP_SHT2_EWSW[4]), .B0(n2761), .B1(
DMP_SFG[4]), .Y(n1497) );
AO22XLTS U2402 ( .A0(n2997), .A1(DMP_SHT2_EWSW[6]), .B0(n2786), .B1(
DMP_SFG[6]), .Y(n1491) );
AO22XLTS U2403 ( .A0(n2994), .A1(DMP_SHT2_EWSW[0]), .B0(n3012), .B1(
DMP_SFG[0]), .Y(n1509) );
INVX4TS U2404 ( .A(n2994), .Y(n2786) );
AO22XLTS U2405 ( .A0(n2994), .A1(DMP_SHT2_EWSW[58]), .B0(n2786), .B1(
DMP_SFG[58]), .Y(n1323) );
AO22XLTS U2406 ( .A0(n2997), .A1(DMP_SHT2_EWSW[56]), .B0(n3012), .B1(
DMP_SFG[56]), .Y(n1333) );
AO22XLTS U2407 ( .A0(n2756), .A1(DMP_SHT2_EWSW[62]), .B0(n2763), .B1(
DMP_SFG[62]), .Y(n1303) );
BUFX4TS U2408 ( .A(n2991), .Y(n3011) );
NOR2XLTS U2409 ( .A(shift_value_SHT2_EWR[4]), .B(n3111), .Y(n1867) );
BUFX3TS U2410 ( .A(n1867), .Y(n2947) );
NOR2X1TS U2411 ( .A(shift_value_SHT2_EWR[2]), .B(n3114), .Y(n1887) );
INVX2TS U2412 ( .A(n1887), .Y(n2867) );
INVX4TS U2413 ( .A(n2867), .Y(n2830) );
AOI22X1TS U2414 ( .A0(Data_array_SWR[32]), .A1(n1973), .B0(
Data_array_SWR[30]), .B1(n2830), .Y(n1869) );
NAND2X1TS U2415 ( .A(n3114), .B(shift_value_SHT2_EWR[2]), .Y(n1873) );
BUFX4TS U2416 ( .A(n2884), .Y(n2849) );
AOI22X1TS U2417 ( .A0(Data_array_SWR[26]), .A1(n2849), .B0(n1829), .B1(n2831), .Y(n1868) );
NAND2X1TS U2418 ( .A(n1869), .B(n1868), .Y(n2948) );
INVX4TS U2419 ( .A(n2867), .Y(n2882) );
AOI22X1TS U2420 ( .A0(n1834), .A1(n2882), .B0(Data_array_SWR[20]), .B1(n1973), .Y(n1872) );
AOI22X1TS U2421 ( .A0(Data_array_SWR[15]), .A1(n2849), .B0(n1831), .B1(n2883), .Y(n1871) );
AOI21X1TS U2422 ( .A0(n1872), .A1(n1871), .B0(n1870), .Y(n1877) );
NAND2X1TS U2423 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2001) );
NAND2BX2TS U2424 ( .AN(shift_value_SHT2_EWR[4]), .B(n3111), .Y(n1953) );
NOR2X1TS U2425 ( .A(n1918), .B(n1953), .Y(n2918) );
NOR2X1TS U2426 ( .A(n1987), .B(n1953), .Y(n1902) );
AOI22X1TS U2427 ( .A0(n1826), .A1(n2944), .B0(Data_array_SWR[1]), .B1(n2945),
.Y(n1875) );
NOR2X1TS U2428 ( .A(n1873), .B(n1953), .Y(n1963) );
AOI22X1TS U2429 ( .A0(Data_array_SWR[9]), .A1(n1883), .B0(Data_array_SWR[5]),
.B1(n2943), .Y(n1874) );
OAI211XLTS U2430 ( .A0(n2937), .A1(n2001), .B0(n1875), .C0(n1874), .Y(n1876)
);
AOI211X1TS U2431 ( .A0(n2947), .A1(n2948), .B0(n1877), .C0(n1876), .Y(n2004)
);
NAND2X1TS U2432 ( .A(n2958), .B(n2945), .Y(n2005) );
OAI22X1TS U2433 ( .A0(n2958), .A1(n2004), .B0(n3198), .B1(n2005), .Y(n1878)
);
AOI22X1TS U2434 ( .A0(Data_array_SWR[35]), .A1(n2882), .B0(
Data_array_SWR[39]), .B1(n1973), .Y(n1880) );
AOI22X1TS U2435 ( .A0(Data_array_SWR[32]), .A1(n2849), .B0(
Data_array_SWR[30]), .B1(n2883), .Y(n1879) );
NAND2X2TS U2436 ( .A(n1880), .B(n1879), .Y(n2909) );
AOI22X1TS U2437 ( .A0(Data_array_SWR[26]), .A1(n1973), .B0(n1829), .B1(n2882), .Y(n1881) );
OAI2BB1X1TS U2438 ( .A0N(n1834), .A1N(n2831), .B0(n1881), .Y(n1882) );
AOI22X1TS U2439 ( .A0(n1831), .A1(n1883), .B0(Data_array_SWR[9]), .B1(n2945),
.Y(n1885) );
AOI22X1TS U2440 ( .A0(Data_array_SWR[15]), .A1(n2944), .B0(n1826), .B1(n2943), .Y(n1884) );
OAI211XLTS U2441 ( .A0(n1985), .A1(n1870), .B0(n1885), .C0(n1884), .Y(n1886)
);
AOI21X1TS U2442 ( .A0(n2947), .A1(n2909), .B0(n1886), .Y(n1979) );
AOI222X4TS U2443 ( .A0(Data_array_SWR[35]), .A1(n2884), .B0(
Data_array_SWR[32]), .B1(n2883), .C0(Data_array_SWR[39]), .C1(n1887),
.Y(n2907) );
NOR2XLTS U2444 ( .A(n3068), .B(n1953), .Y(n1888) );
BUFX3TS U2445 ( .A(n1888), .Y(n2938) );
OAI22X1TS U2446 ( .A0(n2958), .A1(n1979), .B0(n2907), .B1(n2892), .Y(n2902)
);
AO22XLTS U2447 ( .A0(n2997), .A1(n2902), .B0(n3012), .B1(DmP_mant_SFG_SWR[9]), .Y(n1128) );
AOI22X1TS U2448 ( .A0(n1824), .A1(n1973), .B0(Data_array_SWR[29]), .B1(n2830), .Y(n1890) );
AOI22X1TS U2449 ( .A0(Data_array_SWR[23]), .A1(n2831), .B0(
Data_array_SWR[25]), .B1(n2849), .Y(n1889) );
NAND2X1TS U2450 ( .A(n1890), .B(n1889), .Y(n2823) );
AOI22X1TS U2451 ( .A0(Data_array_SWR[19]), .A1(n1973), .B0(
Data_array_SWR[16]), .B1(n2830), .Y(n1892) );
AOI22X1TS U2452 ( .A0(n1832), .A1(n2883), .B0(n1835), .B1(n2849), .Y(n1891)
);
AOI21X1TS U2453 ( .A0(n1892), .A1(n1891), .B0(n1870), .Y(n1896) );
AOI22X1TS U2454 ( .A0(Data_array_SWR[12]), .A1(n2944), .B0(Data_array_SWR[0]), .B1(n2945), .Y(n1894) );
AOI22X1TS U2455 ( .A0(Data_array_SWR[8]), .A1(n1883), .B0(Data_array_SWR[4]),
.B1(n2943), .Y(n1893) );
OAI211XLTS U2456 ( .A0(n2820), .A1(n2001), .B0(n1894), .C0(n1893), .Y(n1895)
);
NAND2X1TS U2457 ( .A(n2945), .B(n2953), .Y(n2007) );
OAI22X1TS U2458 ( .A0(n1906), .A1(n2953), .B0(n3199), .B1(n2007), .Y(n1897)
);
AO22XLTS U2459 ( .A0(n2756), .A1(n1897), .B0(n2763), .B1(
DmP_mant_SFG_SWR[54]), .Y(n1006) );
INVX4TS U2460 ( .A(n2756), .Y(n3012) );
BUFX4TS U2461 ( .A(n1866), .Y(n2997) );
AOI22X1TS U2462 ( .A0(Data_array_SWR[33]), .A1(n2882), .B0(
Data_array_SWR[37]), .B1(n1973), .Y(n1899) );
AOI22X1TS U2463 ( .A0(n1827), .A1(n2849), .B0(Data_array_SWR[28]), .B1(n2831), .Y(n1898) );
NAND2X2TS U2464 ( .A(n1899), .B(n1898), .Y(n2896) );
AOI22X1TS U2465 ( .A0(n1833), .A1(n2831), .B0(Data_array_SWR[22]), .B1(n2830), .Y(n1900) );
AOI22X1TS U2466 ( .A0(n1823), .A1(n1883), .B0(Data_array_SWR[11]), .B1(n2943), .Y(n1904) );
AOI22X1TS U2467 ( .A0(Data_array_SWR[14]), .A1(n2944), .B0(Data_array_SWR[7]), .B1(n1902), .Y(n1903) );
AOI21X1TS U2468 ( .A0(n2947), .A1(n2896), .B0(n1905), .Y(n2900) );
OAI22X1TS U2469 ( .A0(n2958), .A1(n2900), .B0(n2899), .B1(n2892), .Y(n2881)
);
AO22XLTS U2470 ( .A0(n2763), .A1(DmP_mant_SFG_SWR[7]), .B0(n2756), .B1(n2881), .Y(n1106) );
OAI22X1TS U2471 ( .A0(n2958), .A1(n1906), .B0(n3199), .B1(n2005), .Y(n1907)
);
AOI22X1TS U2472 ( .A0(Data_array_SWR[38]), .A1(n1973), .B0(
Data_array_SWR[34]), .B1(n2882), .Y(n1909) );
AOI22X1TS U2473 ( .A0(n1824), .A1(n2849), .B0(Data_array_SWR[29]), .B1(n2831), .Y(n1908) );
NAND2X2TS U2474 ( .A(n1909), .B(n1908), .Y(n2859) );
AOI22X1TS U2475 ( .A0(Data_array_SWR[23]), .A1(n2882), .B0(
Data_array_SWR[16]), .B1(n2831), .Y(n1910) );
AOI22X1TS U2476 ( .A0(n1832), .A1(n1883), .B0(Data_array_SWR[12]), .B1(n2943), .Y(n1913) );
AOI22X1TS U2477 ( .A0(n1835), .A1(n2944), .B0(Data_array_SWR[8]), .B1(n2945),
.Y(n1912) );
OAI211XLTS U2478 ( .A0(n2857), .A1(n1870), .B0(n1913), .C0(n1912), .Y(n1914)
);
AOI21X1TS U2479 ( .A0(n2947), .A1(n2859), .B0(n1914), .Y(n2880) );
AOI222X4TS U2480 ( .A0(Data_array_SWR[40]), .A1(n2830), .B0(
Data_array_SWR[36]), .B1(n2884), .C0(n1825), .C1(n2883), .Y(n2879) );
OAI22X1TS U2481 ( .A0(n2958), .A1(n2880), .B0(n2879), .B1(n2892), .Y(n2878)
);
AO22XLTS U2482 ( .A0(n2761), .A1(DmP_mant_SFG_SWR[8]), .B0(n2994), .B1(n2878), .Y(n1090) );
AOI22X1TS U2483 ( .A0(Data_array_SWR[40]), .A1(n1973), .B0(
Data_array_SWR[36]), .B1(n2882), .Y(n1916) );
AOI22X1TS U2484 ( .A0(n1825), .A1(n2849), .B0(Data_array_SWR[31]), .B1(n2883), .Y(n1915) );
NAND2X2TS U2485 ( .A(n1916), .B(n1915), .Y(n2843) );
AOI22X1TS U2486 ( .A0(n1830), .A1(n2882), .B0(Data_array_SWR[17]), .B1(n2831), .Y(n1917) );
BUFX4TS U2487 ( .A(n1883), .Y(n2942) );
AOI22X1TS U2488 ( .A0(Data_array_SWR[13]), .A1(n2943), .B0(n1828), .B1(n2942), .Y(n1921) );
AOI22X1TS U2489 ( .A0(Data_array_SWR[10]), .A1(n2945), .B0(n1836), .B1(n2944), .Y(n1920) );
OAI211XLTS U2490 ( .A0(n2839), .A1(n1870), .B0(n1921), .C0(n1920), .Y(n1922)
);
AOI21X1TS U2491 ( .A0(n2947), .A1(n2843), .B0(n1922), .Y(n2846) );
AOI222X4TS U2492 ( .A0(Data_array_SWR[38]), .A1(n2882), .B0(
Data_array_SWR[34]), .B1(n2884), .C0(n1824), .C1(n2883), .Y(n2845) );
OAI22X1TS U2493 ( .A0(n2958), .A1(n2846), .B0(n2845), .B1(n2892), .Y(n1980)
);
AO22XLTS U2494 ( .A0(n2786), .A1(DmP_mant_SFG_SWR[10]), .B0(n2756), .B1(
n1980), .Y(n1050) );
INVX2TS U2495 ( .A(DP_OP_15J66_123_7955_n6), .Y(n1923) );
NAND2X1TS U2496 ( .A(n3154), .B(n1923), .Y(n1929) );
INVX2TS U2497 ( .A(n1929), .Y(n1924) );
NAND2X1TS U2498 ( .A(n3172), .B(n1924), .Y(n1932) );
NOR2XLTS U2499 ( .A(n2690), .B(exp_rslt_NRM2_EW1[1]), .Y(n1927) );
INVX2TS U2500 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1926) );
INVX2TS U2501 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1925) );
NAND4BXLTS U2502 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1927), .C(n1926), .D(n1925), .Y(n1928) );
NOR2XLTS U2503 ( .A(n1928), .B(exp_rslt_NRM2_EW1[5]), .Y(n1931) );
XNOR2X1TS U2504 ( .A(DMP_exp_NRM2_EW[7]), .B(n1929), .Y(n2692) );
INVX2TS U2505 ( .A(n2692), .Y(n1943) );
INVX2TS U2506 ( .A(n2691), .Y(n1930) );
NAND4BXLTS U2507 ( .AN(n2693), .B(n1931), .C(n1943), .D(n1930), .Y(n1934) );
INVX2TS U2508 ( .A(n1932), .Y(n1933) );
NAND2X1TS U2509 ( .A(n3183), .B(n1933), .Y(n1935) );
NOR2XLTS U2510 ( .A(n1934), .B(n2694), .Y(n1937) );
INVX2TS U2511 ( .A(n1935), .Y(n1936) );
NAND2X1TS U2512 ( .A(n3210), .B(n1936), .Y(n1939) );
NOR2BX1TS U2513 ( .AN(n1937), .B(n1970), .Y(n1938) );
INVX2TS U2514 ( .A(n1938), .Y(n2689) );
INVX2TS U2515 ( .A(n2689), .Y(n2790) );
INVX2TS U2516 ( .A(n1939), .Y(n1940) );
CLKAND2X2TS U2517 ( .A(n3217), .B(n1940), .Y(n1945) );
NAND4XLTS U2518 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n2690), .D(exp_rslt_NRM2_EW1[1]), .Y(n1941) );
NAND4BXLTS U2519 ( .AN(n1941), .B(n2691), .C(exp_rslt_NRM2_EW1[5]), .D(
exp_rslt_NRM2_EW1[4]), .Y(n1942) );
NOR3BXLTS U2520 ( .AN(n2693), .B(n1943), .C(n1942), .Y(n1944) );
NAND4XLTS U2521 ( .A(n2694), .B(n1945), .C(n1970), .D(n1944), .Y(n2789) );
NAND2X1TS U2522 ( .A(n3236), .B(n2789), .Y(n2778) );
INVX4TS U2523 ( .A(n2829), .Y(n2010) );
AOI22X1TS U2524 ( .A0(Data_array_SWR[34]), .A1(n1973), .B0(n1824), .B1(n2830), .Y(n1946) );
AOI21X1TS U2525 ( .A0(Data_array_SWR[29]), .A1(n2849), .B0(n1947), .Y(n2921)
);
AO22XLTS U2526 ( .A0(Data_array_SWR[8]), .A1(n2943), .B0(Data_array_SWR[4]),
.B1(n2945), .Y(n1952) );
AOI22X1TS U2527 ( .A0(Data_array_SWR[23]), .A1(n1973), .B0(
Data_array_SWR[19]), .B1(n2830), .Y(n1950) );
AOI22X1TS U2528 ( .A0(n1832), .A1(n2944), .B0(Data_array_SWR[12]), .B1(n2942), .Y(n1949) );
AOI22X1TS U2529 ( .A0(Data_array_SWR[16]), .A1(n2884), .B0(n1835), .B1(n2883), .Y(n1948) );
AOI32X1TS U2530 ( .A0(n1950), .A1(n1949), .A2(n1948), .B0(n1870), .B1(n1949),
.Y(n1951) );
AOI211X1TS U2531 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2930), .B0(n1952),
.C0(n1951), .Y(n1969) );
OAI22X1TS U2532 ( .A0(n2958), .A1(n1969), .B0(n2922), .B1(n2892), .Y(n2810)
);
NOR2XLTS U2533 ( .A(n1953), .B(left_right_SHT2), .Y(n1954) );
BUFX3TS U2534 ( .A(n1954), .Y(n2940) );
AOI22X1TS U2535 ( .A0(Data_array_SWR[30]), .A1(n1973), .B0(
Data_array_SWR[26]), .B1(n2830), .Y(n1956) );
AOI22X1TS U2536 ( .A0(n1829), .A1(n2884), .B0(Data_array_SWR[20]), .B1(n2883), .Y(n1955) );
NAND2X1TS U2537 ( .A(n1956), .B(n1955), .Y(n2908) );
NOR2XLTS U2538 ( .A(n3068), .B(n1870), .Y(n1957) );
INVX2TS U2539 ( .A(n2907), .Y(n1982) );
AOI22X1TS U2540 ( .A0(n2938), .A1(n2908), .B0(n2939), .B1(n1982), .Y(n1960)
);
NAND2X1TS U2541 ( .A(n1958), .B(n2909), .Y(n1959) );
OAI211X1TS U2542 ( .A0(n1985), .A1(n2898), .B0(n1960), .C0(n1959), .Y(n2974)
);
AOI22X1TS U2543 ( .A0(Data_array_SWR[32]), .A1(n2882), .B0(
Data_array_SWR[26]), .B1(n2831), .Y(n1961) );
OAI2BB1X1TS U2544 ( .A0N(Data_array_SWR[35]), .A1N(n1973), .B0(n1961), .Y(
n1962) );
AOI21X1TS U2545 ( .A0(Data_array_SWR[30]), .A1(n2849), .B0(n1962), .Y(n2936)
);
AO22XLTS U2546 ( .A0(Data_array_SWR[9]), .A1(n1963), .B0(Data_array_SWR[5]),
.B1(n2945), .Y(n1968) );
AOI22X1TS U2547 ( .A0(n1829), .A1(n1973), .B0(Data_array_SWR[20]), .B1(n2830), .Y(n1966) );
AOI22X1TS U2548 ( .A0(n1831), .A1(n2944), .B0(n1826), .B1(n2942), .Y(n1965)
);
AOI22X1TS U2549 ( .A0(Data_array_SWR[15]), .A1(n2883), .B0(n1834), .B1(n2849), .Y(n1964) );
AOI32X1TS U2550 ( .A0(n1966), .A1(n1965), .A2(n1964), .B0(n1870), .B1(n1965),
.Y(n1967) );
AOI211X1TS U2551 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2955), .B0(n1968),
.C0(n1967), .Y(n2009) );
OAI22X1TS U2552 ( .A0(n2937), .A1(n2892), .B0(n2958), .B1(n2009), .Y(n2806)
);
OAI22X1TS U2553 ( .A0(n1969), .A1(n2953), .B0(n2922), .B1(n2898), .Y(n3004)
);
AO22XLTS U2554 ( .A0(n2010), .A1(n1970), .B0(n2959), .B1(
final_result_ieee[62]), .Y(n1578) );
AOI22X1TS U2555 ( .A0(Data_array_SWR[36]), .A1(n1973), .B0(n1825), .B1(n2830), .Y(n1971) );
OAI21XLTS U2556 ( .A0(n3208), .A1(n1987), .B0(n1971), .Y(n1972) );
AOI21X1TS U2557 ( .A0(Data_array_SWR[31]), .A1(n2884), .B0(n1972), .Y(n2819)
);
AO22XLTS U2558 ( .A0(Data_array_SWR[10]), .A1(n2943), .B0(Data_array_SWR[6]),
.B1(n2945), .Y(n1978) );
AOI22X1TS U2559 ( .A0(Data_array_SWR[21]), .A1(n2882), .B0(n1830), .B1(n1973), .Y(n1976) );
AOI22X1TS U2560 ( .A0(Data_array_SWR[13]), .A1(n2942), .B0(n1828), .B1(n2944), .Y(n1975) );
AOI22X1TS U2561 ( .A0(Data_array_SWR[17]), .A1(n2884), .B0(n1836), .B1(n2883), .Y(n1974) );
AOI32X1TS U2562 ( .A0(n1976), .A1(n1975), .A2(n1974), .B0(n1870), .B1(n1975),
.Y(n1977) );
AOI211X1TS U2563 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2827), .B0(n1978),
.C0(n1977), .Y(n1981) );
OAI22X1TS U2564 ( .A0(n1981), .A1(n2953), .B0(n2820), .B1(n2898), .Y(n3001)
);
OAI22X1TS U2565 ( .A0(n1979), .A1(n2953), .B0(n2907), .B1(n2898), .Y(n2998)
);
OAI22X1TS U2566 ( .A0(n2958), .A1(n1981), .B0(n2820), .B1(n2892), .Y(n2812)
);
AOI22X1TS U2567 ( .A0(n2940), .A1(n2908), .B0(n2939), .B1(n2909), .Y(n1984)
);
NAND2X1TS U2568 ( .A(n1958), .B(n1982), .Y(n1983) );
OAI211X1TS U2569 ( .A0(n1985), .A1(n2892), .B0(n1984), .C0(n1983), .Y(n2978)
);
AOI22X1TS U2570 ( .A0(Data_array_SWR[33]), .A1(n1973), .B0(n1827), .B1(n2830), .Y(n1986) );
OAI21XLTS U2571 ( .A0(n3207), .A1(n1987), .B0(n1986), .Y(n1988) );
AOI21X1TS U2572 ( .A0(Data_array_SWR[28]), .A1(n2884), .B0(n1988), .Y(n2914)
);
AO22XLTS U2573 ( .A0(Data_array_SWR[7]), .A1(n2943), .B0(Data_array_SWR[3]),
.B1(n2945), .Y(n1994) );
AOI22X1TS U2574 ( .A0(Data_array_SWR[22]), .A1(n1973), .B0(
Data_array_SWR[18]), .B1(n2830), .Y(n1992) );
AOI22X1TS U2575 ( .A0(n1823), .A1(n2944), .B0(Data_array_SWR[11]), .B1(n2942), .Y(n1991) );
AOI22X1TS U2576 ( .A0(n1833), .A1(n2884), .B0(Data_array_SWR[14]), .B1(n2883), .Y(n1990) );
AOI32X1TS U2577 ( .A0(n1992), .A1(n1991), .A2(n1990), .B0(n1870), .B1(n1991),
.Y(n1993) );
AOI211X1TS U2578 ( .A0(shift_value_SHT2_EWR[5]), .A1(n2915), .B0(n1994),
.C0(n1993), .Y(n2008) );
OAI22X1TS U2579 ( .A0(n2958), .A1(n2008), .B0(n3185), .B1(n2005), .Y(n2808)
);
AOI22X1TS U2580 ( .A0(n1825), .A1(n1973), .B0(Data_array_SWR[31]), .B1(n2830), .Y(n1996) );
AOI22X1TS U2581 ( .A0(n1830), .A1(n2831), .B0(Data_array_SWR[27]), .B1(n2849), .Y(n1995) );
NAND2X1TS U2582 ( .A(n1996), .B(n1995), .Y(n2925) );
AOI22X1TS U2583 ( .A0(Data_array_SWR[21]), .A1(n1973), .B0(
Data_array_SWR[17]), .B1(n2830), .Y(n1998) );
AOI22X1TS U2584 ( .A0(n1836), .A1(n2849), .B0(n1828), .B1(n2883), .Y(n1997)
);
AOI21X1TS U2585 ( .A0(n1998), .A1(n1997), .B0(n1870), .Y(n2003) );
AOI22X1TS U2586 ( .A0(Data_array_SWR[13]), .A1(n2944), .B0(Data_array_SWR[2]), .B1(n2945), .Y(n2000) );
AOI22X1TS U2587 ( .A0(Data_array_SWR[10]), .A1(n1883), .B0(Data_array_SWR[6]), .B1(n2943), .Y(n1999) );
OAI211XLTS U2588 ( .A0(n2922), .A1(n2001), .B0(n2000), .C0(n1999), .Y(n2002)
);
AOI211X1TS U2589 ( .A0(n2947), .A1(n2925), .B0(n2003), .C0(n2002), .Y(n2006)
);
OAI22X1TS U2590 ( .A0(n2006), .A1(n3068), .B0(n3197), .B1(n2007), .Y(n3007)
);
OAI22X1TS U2591 ( .A0(n2004), .A1(n3068), .B0(n3198), .B1(n2007), .Y(n3010)
);
OAI22X1TS U2592 ( .A0(n2958), .A1(n2006), .B0(n3197), .B1(n2005), .Y(n2804)
);
OAI22X1TS U2593 ( .A0(n2008), .A1(n3068), .B0(n3185), .B1(n2007), .Y(n3005)
);
OAI22X1TS U2594 ( .A0(n2009), .A1(n2953), .B0(n2937), .B1(n2898), .Y(n3003)
);
NAND2X1TS U2595 ( .A(n2787), .B(n2760), .Y(n2465) );
NOR2X2TS U2596 ( .A(n2788), .B(n2760), .Y(n2727) );
AOI22X1TS U2597 ( .A0(n2470), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n2727), .Y(n2036) );
NAND2X1TS U2598 ( .A(n3025), .B(n3071), .Y(n2439) );
NOR2X2TS U2599 ( .A(Raw_mant_NRM_SWR[48]), .B(n2011), .Y(n2455) );
NOR2X2TS U2600 ( .A(Raw_mant_NRM_SWR[42]), .B(n2031), .Y(n2019) );
NAND2X2TS U2601 ( .A(n2023), .B(n3028), .Y(n2425) );
NAND2X2TS U2602 ( .A(n2043), .B(n3029), .Y(n2674) );
NOR4X2TS U2603 ( .A(Raw_mant_NRM_SWR[27]), .B(Raw_mant_NRM_SWR[28]), .C(
Raw_mant_NRM_SWR[29]), .D(n2674), .Y(n2044) );
NOR2X2TS U2604 ( .A(Raw_mant_NRM_SWR[25]), .B(n2038), .Y(n2429) );
NAND2X2TS U2605 ( .A(n2018), .B(n3091), .Y(n2048) );
NOR2X1TS U2606 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n2057) );
NOR3X2TS U2607 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n2048), .Y(n2459) );
OAI22X1TS U2608 ( .A0(n3038), .A1(n2048), .B0(n2017), .B1(n3220), .Y(n2035)
);
NAND2X1TS U2609 ( .A(n2041), .B(Raw_mant_NRM_SWR[22]), .Y(n2042) );
OAI22X1TS U2610 ( .A0(n3019), .A1(n2425), .B0(n2013), .B1(n3063), .Y(n2015)
);
NAND2X1TS U2611 ( .A(n2022), .B(Raw_mant_NRM_SWR[28]), .Y(n2678) );
OAI211XLTS U2612 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2042), .B0(n2016), .C0(
n2678), .Y(n2034) );
NOR2X2TS U2613 ( .A(Raw_mant_NRM_SWR[12]), .B(n2067), .Y(n2058) );
NOR2X2TS U2614 ( .A(Raw_mant_NRM_SWR[10]), .B(n2050), .Y(n2059) );
INVX2TS U2615 ( .A(n2060), .Y(n2030) );
NAND2X1TS U2616 ( .A(Raw_mant_NRM_SWR[21]), .B(n2018), .Y(n2679) );
AOI32X1TS U2617 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2019), .A2(n3017), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2019), .Y(n2020) );
OAI211X1TS U2618 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2021), .B0(n2679), .C0(
n2020), .Y(n2052) );
NAND2X1TS U2619 ( .A(n2022), .B(n3035), .Y(n2028) );
NOR3X1TS U2620 ( .A(Raw_mant_NRM_SWR[32]), .B(n3037), .C(n2425), .Y(n2025)
);
AOI22X1TS U2621 ( .A0(Raw_mant_NRM_SWR[33]), .A1(n2023), .B0(n2022), .B1(
Raw_mant_NRM_SWR[29]), .Y(n2673) );
OAI31X1TS U2622 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3139), .A2(n2048), .B0(
n2673), .Y(n2024) );
AOI211X1TS U2623 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2455), .B0(n2025), .C0(
n2024), .Y(n2027) );
NAND2X1TS U2624 ( .A(Raw_mant_NRM_SWR[13]), .B(n2026), .Y(n2065) );
AOI211X1TS U2625 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2058), .B0(n2052), .C0(
n2029), .Y(n2463) );
OAI31X1TS U2626 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2032), .A2(
Raw_mant_NRM_SWR[40]), .B0(n2449), .Y(n2054) );
OAI31X1TS U2627 ( .A0(n2035), .A1(n2034), .A2(n2033), .B0(n2788), .Y(n2686)
);
NAND2X1TS U2628 ( .A(n2036), .B(n2686), .Y(n1599) );
NAND2X1TS U2629 ( .A(Raw_mant_NRM_SWR[43]), .B(n2037), .Y(n2436) );
AOI21X1TS U2630 ( .A0(n2041), .A1(Raw_mant_NRM_SWR[23]), .B0(n2040), .Y(
n2462) );
OAI2BB1X1TS U2631 ( .A0N(n2043), .A1N(Raw_mant_NRM_SWR[30]), .B0(n2042), .Y(
n2677) );
OAI2BB2XLTS U2632 ( .B0(n2046), .B1(n2045), .A0N(Raw_mant_NRM_SWR[26]),
.A1N(n2044), .Y(n2047) );
AOI211X1TS U2633 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2429), .B0(n2677), .C0(
n2047), .Y(n2049) );
AO21XLTS U2634 ( .A0(n3139), .A1(n3038), .B0(n2048), .Y(n2433) );
OAI211XLTS U2635 ( .A0(n3215), .A1(n2050), .B0(n2049), .C0(n2433), .Y(n2051)
);
AOI211X1TS U2636 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2071), .B0(n2052), .C0(
n2051), .Y(n2053) );
AOI31X1TS U2637 ( .A0(n2054), .A1(n2462), .A2(n2053), .B0(n2787), .Y(n2685)
);
AOI21X1TS U2638 ( .A0(n2727), .A1(Shift_amount_SHT1_EWR[3]), .B0(n2685), .Y(
n2055) );
OAI21XLTS U2639 ( .A0(n2465), .A1(n3114), .B0(n2055), .Y(n1598) );
INVX2TS U2640 ( .A(n2073), .Y(n2681) );
NOR4X2TS U2641 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n2681),
.D(n3152), .Y(n2430) );
AOI22X1TS U2642 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2059), .B0(
Raw_mant_NRM_SWR[10]), .B1(n2058), .Y(n2061) );
AOI32X1TS U2643 ( .A0(n2062), .A1(n2061), .A2(n3141), .B0(n2060), .B1(n2061),
.Y(n2063) );
NOR4BX1TS U2644 ( .AN(n2065), .B(n2430), .C(n2064), .D(n2063), .Y(n2074) );
NAND2X1TS U2645 ( .A(Raw_mant_NRM_SWR[15]), .B(n2066), .Y(n2456) );
OAI211X1TS U2646 ( .A0(n2070), .A1(n2069), .B0(n2456), .C0(n2068), .Y(n2072)
);
AOI31X1TS U2647 ( .A0(n2074), .A1(n2446), .A2(n2460), .B0(n2787), .Y(n2668)
);
AOI21X1TS U2648 ( .A0(n2727), .A1(Shift_amount_SHT1_EWR[5]), .B0(n2668), .Y(
n2075) );
OAI21XLTS U2649 ( .A0(n2465), .A1(n3111), .B0(n2075), .Y(n1595) );
BUFX4TS U2650 ( .A(n3225), .Y(n2814) );
BUFX4TS U2651 ( .A(n3225), .Y(n2796) );
AOI22X1TS U2652 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n2814), .B0(
DmP_mant_SFG_SWR[0]), .B1(n2421), .Y(n2076) );
OAI21XLTS U2653 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n2865), .B0(n2076), .Y(n1121) );
AOI2BB2X1TS U2654 ( .B0(DmP_mant_SFG_SWR[9]), .B1(OP_FLAG_SFG), .A0N(
OP_FLAG_SFG), .A1N(DmP_mant_SFG_SWR[9]), .Y(n2667) );
OAI32X1TS U2655 ( .A0(DMP_SFG[7]), .A1(n2814), .A2(n2667), .B0(
Raw_mant_NRM_SWR[9]), .B1(n3016), .Y(n2077) );
INVX2TS U2656 ( .A(n2077), .Y(n1127) );
AOI22X1TS U2657 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n2814), .B0(
DmP_mant_SFG_SWR[1]), .B1(n2421), .Y(n2078) );
NOR2XLTS U2658 ( .A(n3223), .B(intDY_EWSW[53]), .Y(n2079) );
OAI22X1TS U2659 ( .A0(n3224), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3069), .Y(n2194) );
NOR2BX1TS U2660 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2080) );
NOR2X1TS U2661 ( .A(n3134), .B(intDY_EWSW[57]), .Y(n2148) );
NAND2X1TS U2662 ( .A(n3104), .B(intDX_EWSW[61]), .Y(n2154) );
OAI211X1TS U2663 ( .A0(intDY_EWSW[60]), .A1(n3182), .B0(n2158), .C0(n2154),
.Y(n2160) );
OAI21X1TS U2664 ( .A0(intDY_EWSW[58]), .A1(n3181), .B0(n2150), .Y(n2152) );
NOR2X1TS U2665 ( .A(n3205), .B(intDY_EWSW[49]), .Y(n2197) );
NAND2BXLTS U2666 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2199) );
OAI21X1TS U2667 ( .A0(intDY_EWSW[50]), .A1(n3036), .B0(n2199), .Y(n2203) );
AOI211X1TS U2668 ( .A0(intDX_EWSW[48]), .A1(n3170), .B0(n2197), .C0(n2203),
.Y(n2081) );
NAND3X1TS U2669 ( .A(n2196), .B(n2205), .C(n2081), .Y(n2213) );
NOR2BX1TS U2670 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2188) );
AOI21X1TS U2671 ( .A0(intDX_EWSW[38]), .A1(n3214), .B0(n2188), .Y(n2187) );
NAND2X1TS U2672 ( .A(n3186), .B(intDX_EWSW[37]), .Y(n2176) );
OAI211X1TS U2673 ( .A0(intDY_EWSW[36]), .A1(n3123), .B0(n2187), .C0(n2176),
.Y(n2178) );
NOR2X1TS U2674 ( .A(n3129), .B(intDY_EWSW[45]), .Y(n2162) );
NAND2BXLTS U2675 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2161) );
OAI21X1TS U2676 ( .A0(intDY_EWSW[46]), .A1(n3117), .B0(n2161), .Y(n2171) );
OA22X1TS U2677 ( .A0(n3115), .A1(intDY_EWSW[42]), .B0(n3031), .B1(
intDY_EWSW[43]), .Y(n2167) );
NAND2BXLTS U2678 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2083) );
NAND2BXLTS U2679 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2082) );
NAND4XLTS U2680 ( .A(n2169), .B(n2167), .C(n2083), .D(n2082), .Y(n2211) );
NAND2BXLTS U2681 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2084) );
OA22X1TS U2682 ( .A0(n3116), .A1(intDY_EWSW[34]), .B0(n3032), .B1(
intDY_EWSW[35]), .Y(n2182) );
OAI211XLTS U2683 ( .A0(n3113), .A1(intDY_EWSW[33]), .B0(n2084), .C0(n2182),
.Y(n2085) );
NOR4X1TS U2684 ( .A(n2213), .B(n2178), .C(n2211), .D(n2085), .Y(n2217) );
OA22X1TS U2685 ( .A0(n3120), .A1(intDY_EWSW[30]), .B0(n3033), .B1(
intDY_EWSW[31]), .Y(n2257) );
OAI21XLTS U2686 ( .A0(intDY_EWSW[29]), .A1(n3126), .B0(intDY_EWSW[28]), .Y(
n2086) );
OAI2BB2XLTS U2687 ( .B0(intDX_EWSW[28]), .B1(n2086), .A0N(intDY_EWSW[29]),
.A1N(n3126), .Y(n2095) );
NAND2BXLTS U2688 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2089) );
OAI21X1TS U2689 ( .A0(intDY_EWSW[26]), .A1(n3145), .B0(n2089), .Y(n2143) );
NAND2BXLTS U2690 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2087) );
NOR2X1TS U2691 ( .A(n3131), .B(intDY_EWSW[25]), .Y(n2140) );
NOR2XLTS U2692 ( .A(n2140), .B(intDX_EWSW[24]), .Y(n2088) );
AOI22X1TS U2693 ( .A0(n2088), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3131), .Y(n2091) );
AOI32X1TS U2694 ( .A0(n3145), .A1(n2089), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3039), .Y(n2090) );
OAI32X1TS U2695 ( .A0(n2143), .A1(n2142), .A2(n2091), .B0(n2090), .B1(n2142),
.Y(n2094) );
OAI2BB2XLTS U2696 ( .B0(intDX_EWSW[30]), .B1(n2092), .A0N(intDY_EWSW[31]),
.A1N(n3033), .Y(n2093) );
AOI211X1TS U2697 ( .A0(n2257), .A1(n2095), .B0(n2094), .C0(n2093), .Y(n2147)
);
OA22X1TS U2698 ( .A0(n3121), .A1(intDY_EWSW[22]), .B0(n3034), .B1(
intDY_EWSW[23]), .Y(n2265) );
NAND2BXLTS U2699 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2096) );
OA22X1TS U2700 ( .A0(n3108), .A1(intDY_EWSW[14]), .B0(n3030), .B1(
intDY_EWSW[15]), .Y(n2273) );
NAND2BXLTS U2701 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2097) );
OAI2BB1X1TS U2702 ( .A0N(n3176), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2098) );
OAI22X1TS U2703 ( .A0(intDX_EWSW[4]), .A1(n2098), .B0(n3176), .B1(
intDX_EWSW[5]), .Y(n2108) );
OAI2BB1X1TS U2704 ( .A0N(n3204), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2099) );
OAI22X1TS U2705 ( .A0(intDX_EWSW[6]), .A1(n2099), .B0(n3204), .B1(
intDX_EWSW[7]), .Y(n2107) );
NAND2BXLTS U2706 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2102) );
AOI2BB2XLTS U2707 ( .B0(intDX_EWSW[1]), .B1(n3213), .A0N(intDY_EWSW[0]),
.A1N(n2100), .Y(n2101) );
OAI211XLTS U2708 ( .A0(n3112), .A1(intDY_EWSW[3]), .B0(n2102), .C0(n2101),
.Y(n2105) );
OAI21XLTS U2709 ( .A0(intDY_EWSW[3]), .A1(n3112), .B0(intDY_EWSW[2]), .Y(
n2103) );
AOI2BB2XLTS U2710 ( .B0(intDY_EWSW[3]), .B1(n3112), .A0N(intDX_EWSW[2]),
.A1N(n2103), .Y(n2104) );
AOI22X1TS U2711 ( .A0(intDX_EWSW[7]), .A1(n3204), .B0(intDX_EWSW[6]), .B1(
n3062), .Y(n2281) );
OAI32X1TS U2712 ( .A0(n2108), .A1(n2107), .A2(n2106), .B0(n2281), .B1(n2107),
.Y(n2124) );
NAND2BXLTS U2713 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2112) );
NOR2X1TS U2714 ( .A(n3130), .B(intDY_EWSW[11]), .Y(n2110) );
AOI21X1TS U2715 ( .A0(intDX_EWSW[10]), .A1(n3159), .B0(n2110), .Y(n2115) );
OAI211XLTS U2716 ( .A0(intDY_EWSW[8]), .A1(n3133), .B0(n2112), .C0(n2115),
.Y(n2123) );
OAI21XLTS U2717 ( .A0(intDY_EWSW[13]), .A1(n3127), .B0(intDY_EWSW[12]), .Y(
n2109) );
OAI2BB2XLTS U2718 ( .B0(intDX_EWSW[12]), .B1(n2109), .A0N(intDY_EWSW[13]),
.A1N(n3127), .Y(n2121) );
NOR2XLTS U2719 ( .A(n2110), .B(intDX_EWSW[10]), .Y(n2111) );
AOI22X1TS U2720 ( .A0(intDY_EWSW[11]), .A1(n3130), .B0(intDY_EWSW[10]), .B1(
n2111), .Y(n2117) );
NAND3XLTS U2721 ( .A(n3133), .B(n2112), .C(intDY_EWSW[8]), .Y(n2114) );
AOI21X1TS U2722 ( .A0(n2114), .A1(n2113), .B0(n2125), .Y(n2116) );
OAI2BB2XLTS U2723 ( .B0(n2117), .B1(n2125), .A0N(n2116), .A1N(n2115), .Y(
n2120) );
OAI21XLTS U2724 ( .A0(intDY_EWSW[15]), .A1(n3030), .B0(intDY_EWSW[14]), .Y(
n2118) );
OAI2BB2XLTS U2725 ( .B0(intDX_EWSW[14]), .B1(n2118), .A0N(intDY_EWSW[15]),
.A1N(n3030), .Y(n2119) );
AOI211X1TS U2726 ( .A0(n2273), .A1(n2121), .B0(n2120), .C0(n2119), .Y(n2122)
);
OAI31X1TS U2727 ( .A0(n2125), .A1(n2124), .A2(n2123), .B0(n2122), .Y(n2127)
);
NOR2X1TS U2728 ( .A(n3132), .B(intDY_EWSW[17]), .Y(n2129) );
NAND2BXLTS U2729 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2131) );
OAI21X1TS U2730 ( .A0(intDY_EWSW[18]), .A1(n3146), .B0(n2131), .Y(n2135) );
NAND3BXLTS U2731 ( .AN(n2134), .B(n2127), .C(n2126), .Y(n2146) );
OAI21XLTS U2732 ( .A0(intDY_EWSW[21]), .A1(n3143), .B0(intDY_EWSW[20]), .Y(
n2128) );
OAI2BB2XLTS U2733 ( .B0(intDX_EWSW[20]), .B1(n2128), .A0N(intDY_EWSW[21]),
.A1N(n3143), .Y(n2139) );
NOR2XLTS U2734 ( .A(n2129), .B(intDX_EWSW[16]), .Y(n2130) );
AOI22X1TS U2735 ( .A0(n2130), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3132), .Y(n2133) );
AOI32X1TS U2736 ( .A0(n3146), .A1(n2131), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3040), .Y(n2132) );
OAI32X1TS U2737 ( .A0(n2135), .A1(n2134), .A2(n2133), .B0(n2132), .B1(n2134),
.Y(n2138) );
OAI21XLTS U2738 ( .A0(intDY_EWSW[23]), .A1(n3034), .B0(intDY_EWSW[22]), .Y(
n2136) );
OAI2BB2XLTS U2739 ( .B0(intDX_EWSW[22]), .B1(n2136), .A0N(intDY_EWSW[23]),
.A1N(n3034), .Y(n2137) );
AOI211X1TS U2740 ( .A0(n2265), .A1(n2139), .B0(n2138), .C0(n2137), .Y(n2145)
);
NOR2BX1TS U2741 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2141) );
OR4X2TS U2742 ( .A(n2143), .B(n2142), .C(n2141), .D(n2140), .Y(n2144) );
AOI32X1TS U2743 ( .A0(n2147), .A1(n2146), .A2(n2145), .B0(n2144), .B1(n2147),
.Y(n2216) );
NOR2XLTS U2744 ( .A(n2148), .B(intDX_EWSW[56]), .Y(n2149) );
AOI22X1TS U2745 ( .A0(intDY_EWSW[57]), .A1(n3134), .B0(intDY_EWSW[56]), .B1(
n2149), .Y(n2153) );
OA21XLTS U2746 ( .A0(n2153), .A1(n2152), .B0(n2151), .Y(n2159) );
NAND2BXLTS U2747 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2156) );
NAND3XLTS U2748 ( .A(n3182), .B(n2154), .C(intDY_EWSW[60]), .Y(n2155) );
OAI211XLTS U2749 ( .A0(intDX_EWSW[61]), .A1(n3104), .B0(n2156), .C0(n2155),
.Y(n2157) );
OAI2BB2XLTS U2750 ( .B0(n2160), .B1(n2159), .A0N(n2158), .A1N(n2157), .Y(
n2215) );
NOR2BX1TS U2751 ( .AN(n2161), .B(intDX_EWSW[46]), .Y(n2175) );
NOR2XLTS U2752 ( .A(n2162), .B(intDX_EWSW[44]), .Y(n2163) );
AOI22X1TS U2753 ( .A0(intDY_EWSW[45]), .A1(n3129), .B0(intDY_EWSW[44]), .B1(
n2163), .Y(n2172) );
OAI21XLTS U2754 ( .A0(intDY_EWSW[41]), .A1(n3125), .B0(intDY_EWSW[40]), .Y(
n2164) );
OAI2BB2XLTS U2755 ( .B0(intDX_EWSW[40]), .B1(n2164), .A0N(intDY_EWSW[41]),
.A1N(n3125), .Y(n2168) );
OAI21XLTS U2756 ( .A0(intDY_EWSW[43]), .A1(n3031), .B0(intDY_EWSW[42]), .Y(
n2165) );
OAI2BB2XLTS U2757 ( .B0(intDX_EWSW[42]), .B1(n2165), .A0N(intDY_EWSW[43]),
.A1N(n3031), .Y(n2166) );
AOI32X1TS U2758 ( .A0(n2169), .A1(n2168), .A2(n2167), .B0(n2166), .B1(n2169),
.Y(n2170) );
OAI21XLTS U2759 ( .A0(n2172), .A1(n2171), .B0(n2170), .Y(n2174) );
NOR2BX1TS U2760 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2173) );
NAND3XLTS U2761 ( .A(n3123), .B(n2176), .C(intDY_EWSW[36]), .Y(n2177) );
OAI21XLTS U2762 ( .A0(intDX_EWSW[37]), .A1(n3186), .B0(n2177), .Y(n2186) );
INVX2TS U2763 ( .A(n2178), .Y(n2184) );
OAI21XLTS U2764 ( .A0(intDY_EWSW[33]), .A1(n3113), .B0(intDY_EWSW[32]), .Y(
n2179) );
OAI2BB2XLTS U2765 ( .B0(intDX_EWSW[32]), .B1(n2179), .A0N(intDY_EWSW[33]),
.A1N(n3113), .Y(n2183) );
OAI2BB2XLTS U2766 ( .B0(intDX_EWSW[34]), .B1(n2180), .A0N(intDY_EWSW[35]),
.A1N(n3032), .Y(n2181) );
AOI32X1TS U2767 ( .A0(n2184), .A1(n2183), .A2(n2182), .B0(n2181), .B1(n2184),
.Y(n2185) );
OAI2BB1X1TS U2768 ( .A0N(n2187), .A1N(n2186), .B0(n2185), .Y(n2192) );
NOR2BX1TS U2769 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2191) );
NOR3X1TS U2770 ( .A(n3214), .B(n2188), .C(intDX_EWSW[38]), .Y(n2190) );
INVX2TS U2771 ( .A(n2213), .Y(n2189) );
OAI31X1TS U2772 ( .A0(n2192), .A1(n2191), .A2(n2190), .B0(n2189), .Y(n2210)
);
OAI21XLTS U2773 ( .A0(intDY_EWSW[53]), .A1(n3223), .B0(intDY_EWSW[52]), .Y(
n2193) );
AOI2BB2XLTS U2774 ( .B0(intDY_EWSW[53]), .B1(n3223), .A0N(intDX_EWSW[52]),
.A1N(n2193), .Y(n2195) );
INVX2TS U2775 ( .A(n2196), .Y(n2202) );
AOI22X1TS U2776 ( .A0(intDY_EWSW[49]), .A1(n3205), .B0(intDY_EWSW[48]), .B1(
n2198), .Y(n2201) );
AOI32X1TS U2777 ( .A0(n3036), .A1(n2199), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3140), .Y(n2200) );
OAI32X1TS U2778 ( .A0(n2203), .A1(n2202), .A2(n2201), .B0(n2200), .B1(n2202),
.Y(n2207) );
OAI21XLTS U2779 ( .A0(intDY_EWSW[55]), .A1(n3224), .B0(intDY_EWSW[54]), .Y(
n2204) );
OAI2BB2XLTS U2780 ( .B0(intDX_EWSW[54]), .B1(n2204), .A0N(intDY_EWSW[55]),
.A1N(n3224), .Y(n2206) );
OAI31X1TS U2781 ( .A0(n2208), .A1(n2207), .A2(n2206), .B0(n2205), .Y(n2209)
);
OAI221XLTS U2782 ( .A0(n2213), .A1(n2212), .B0(n2211), .B1(n2210), .C0(n2209), .Y(n2214) );
AOI211X1TS U2783 ( .A0(n2217), .A1(n2216), .B0(n2215), .C0(n2214), .Y(n2219)
);
BUFX4TS U2784 ( .A(n2346), .Y(n2356) );
AOI22X1TS U2785 ( .A0(intDX_EWSW[23]), .A1(n2356), .B0(DMP_EXP_EWSW[23]),
.B1(n2388), .Y(n2220) );
OAI21XLTS U2786 ( .A0(n3060), .A1(n2218), .B0(n2220), .Y(n1554) );
AOI22X1TS U2787 ( .A0(intDX_EWSW[31]), .A1(n2356), .B0(DMP_EXP_EWSW[31]),
.B1(n2700), .Y(n2221) );
OAI21XLTS U2788 ( .A0(n3061), .A1(n2218), .B0(n2221), .Y(n1546) );
AOI22X1TS U2789 ( .A0(intDX_EWSW[27]), .A1(n2356), .B0(DMP_EXP_EWSW[27]),
.B1(n2388), .Y(n2222) );
AOI22X1TS U2790 ( .A0(intDX_EWSW[11]), .A1(n1795), .B0(DMP_EXP_EWSW[11]),
.B1(n2388), .Y(n2223) );
OAI21XLTS U2791 ( .A0(n3052), .A1(n2218), .B0(n2223), .Y(n1566) );
AOI22X1TS U2792 ( .A0(intDX_EWSW[24]), .A1(n2356), .B0(DMP_EXP_EWSW[24]),
.B1(n2388), .Y(n2224) );
OAI21XLTS U2793 ( .A0(n3166), .A1(n2218), .B0(n2224), .Y(n1553) );
AOI22X1TS U2794 ( .A0(n3052), .A1(intDX_EWSW[11]), .B0(n3177), .B1(
intDX_EWSW[50]), .Y(n2225) );
OAI221XLTS U2795 ( .A0(n3052), .A1(intDX_EWSW[11]), .B0(n3177), .B1(
intDX_EWSW[50]), .C0(n2225), .Y(n2226) );
AOI221X1TS U2796 ( .A0(intDY_EWSW[49]), .A1(n3205), .B0(n3200), .B1(
intDX_EWSW[49]), .C0(n2226), .Y(n2240) );
OAI22X1TS U2797 ( .A0(n3014), .A1(intDX_EWSW[53]), .B0(n1820), .B1(
intDX_EWSW[54]), .Y(n2227) );
AOI221X1TS U2798 ( .A0(n3014), .A1(intDX_EWSW[53]), .B0(intDX_EWSW[54]),
.B1(n1820), .C0(n2227), .Y(n2239) );
OAI22X1TS U2799 ( .A0(n3196), .A1(intDX_EWSW[51]), .B0(n3206), .B1(
intDX_EWSW[52]), .Y(n2228) );
AOI221X1TS U2800 ( .A0(n3196), .A1(intDX_EWSW[51]), .B0(intDX_EWSW[52]),
.B1(n3206), .C0(n2228), .Y(n2238) );
AOI22X1TS U2801 ( .A0(n3181), .A1(intDY_EWSW[58]), .B0(n3178), .B1(
intDX_EWSW[57]), .Y(n2229) );
AOI22X1TS U2802 ( .A0(n1818), .A1(intDX_EWSW[56]), .B0(n3013), .B1(
intDX_EWSW[55]), .Y(n2230) );
OAI221XLTS U2803 ( .A0(n1818), .A1(intDX_EWSW[56]), .B0(n3013), .B1(
intDX_EWSW[55]), .C0(n2230), .Y(n2235) );
AOI22X1TS U2804 ( .A0(n3053), .A1(intDY_EWSW[62]), .B0(n3180), .B1(
intDY_EWSW[61]), .Y(n2231) );
AOI22X1TS U2805 ( .A0(n3182), .A1(intDY_EWSW[60]), .B0(n3054), .B1(
intDY_EWSW[59]), .Y(n2232) );
NOR4X1TS U2806 ( .A(n2236), .B(n2235), .C(n2234), .D(n2233), .Y(n2237) );
NAND4XLTS U2807 ( .A(n2240), .B(n2239), .C(n2238), .D(n2237), .Y(n2296) );
OAI22X1TS U2808 ( .A0(n3193), .A1(intDX_EWSW[42]), .B0(n3058), .B1(
intDX_EWSW[43]), .Y(n2241) );
AOI221X1TS U2809 ( .A0(n3193), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3058), .C0(n2241), .Y(n2248) );
OAI22X1TS U2810 ( .A0(n3192), .A1(intDX_EWSW[40]), .B0(n3057), .B1(
intDX_EWSW[41]), .Y(n2242) );
AOI221X1TS U2811 ( .A0(n3192), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3057), .C0(n2242), .Y(n2247) );
OAI22X1TS U2812 ( .A0(n3195), .A1(intDX_EWSW[46]), .B0(n3055), .B1(
intDX_EWSW[47]), .Y(n2243) );
AOI221X1TS U2813 ( .A0(n3195), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3055), .C0(n2243), .Y(n2246) );
OAI22X1TS U2814 ( .A0(n3194), .A1(intDX_EWSW[44]), .B0(n3188), .B1(
intDX_EWSW[45]), .Y(n2244) );
AOI221X1TS U2815 ( .A0(n3194), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3188), .C0(n2244), .Y(n2245) );
NAND4XLTS U2816 ( .A(n2248), .B(n2247), .C(n2246), .D(n2245), .Y(n2295) );
OAI22X1TS U2817 ( .A0(n3190), .A1(intDX_EWSW[34]), .B0(n3056), .B1(
intDX_EWSW[35]), .Y(n2249) );
AOI221X1TS U2818 ( .A0(n3190), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3056), .C0(n2249), .Y(n2256) );
OAI22X1TS U2819 ( .A0(n3213), .A1(intDX_EWSW[1]), .B0(n3189), .B1(
intDX_EWSW[33]), .Y(n2250) );
AOI221X1TS U2820 ( .A0(n3213), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[33]), .B1(
n3189), .C0(n2250), .Y(n2255) );
OAI22X1TS U2821 ( .A0(n3214), .A1(intDX_EWSW[38]), .B0(n3187), .B1(
intDX_EWSW[39]), .Y(n2251) );
OAI22X1TS U2822 ( .A0(n3191), .A1(intDX_EWSW[36]), .B0(n3186), .B1(
intDX_EWSW[37]), .Y(n2252) );
AOI221X1TS U2823 ( .A0(n3191), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3186), .C0(n2252), .Y(n2253) );
NAND4XLTS U2824 ( .A(n2256), .B(n2255), .C(n2254), .D(n2253), .Y(n2294) );
OAI221XLTS U2825 ( .A0(n3061), .A1(intDX_EWSW[31]), .B0(n3203), .B1(
intDX_EWSW[30]), .C0(n2257), .Y(n2264) );
AOI22X1TS U2826 ( .A0(n3049), .A1(intDX_EWSW[29]), .B0(n3165), .B1(
intDX_EWSW[20]), .Y(n2258) );
OAI221XLTS U2827 ( .A0(n3049), .A1(intDX_EWSW[29]), .B0(n3165), .B1(
intDX_EWSW[20]), .C0(n2258), .Y(n2263) );
AOI22X1TS U2828 ( .A0(n3047), .A1(intDX_EWSW[27]), .B0(n3167), .B1(
intDX_EWSW[26]), .Y(n2259) );
AOI22X1TS U2829 ( .A0(n3046), .A1(intDX_EWSW[25]), .B0(n3169), .B1(
intDX_EWSW[32]), .Y(n2260) );
NOR4X1TS U2830 ( .A(n2261), .B(n2263), .C(n2262), .D(n2264), .Y(n2292) );
OAI221XLTS U2831 ( .A0(n3060), .A1(intDX_EWSW[23]), .B0(n3202), .B1(
intDX_EWSW[22]), .C0(n2265), .Y(n2272) );
AOI22X1TS U2832 ( .A0(n3161), .A1(intDX_EWSW[21]), .B0(n3170), .B1(
intDX_EWSW[48]), .Y(n2266) );
AOI22X1TS U2833 ( .A0(n3045), .A1(intDX_EWSW[19]), .B0(n3164), .B1(
intDX_EWSW[18]), .Y(n2267) );
OAI221XLTS U2834 ( .A0(n3045), .A1(intDX_EWSW[19]), .B0(n3164), .B1(
intDX_EWSW[18]), .C0(n2267), .Y(n2270) );
AOI22X1TS U2835 ( .A0(n3044), .A1(intDX_EWSW[17]), .B0(n3166), .B1(
intDX_EWSW[24]), .Y(n2268) );
NOR4X1TS U2836 ( .A(n2271), .B(n2272), .C(n2269), .D(n2270), .Y(n2291) );
OAI221XLTS U2837 ( .A0(n3059), .A1(intDX_EWSW[15]), .B0(n3201), .B1(
intDX_EWSW[14]), .C0(n2273), .Y(n2280) );
AOI22X1TS U2838 ( .A0(n3160), .A1(intDX_EWSW[13]), .B0(n3050), .B1(
intDX_EWSW[4]), .Y(n2274) );
AOI22X1TS U2839 ( .A0(n3159), .A1(intDX_EWSW[10]), .B0(n3163), .B1(
intDX_EWSW[12]), .Y(n2275) );
AOI22X1TS U2840 ( .A0(n3158), .A1(intDX_EWSW[9]), .B0(n3171), .B1(
intDX_EWSW[16]), .Y(n2276) );
NOR4X1TS U2841 ( .A(n2279), .B(n2280), .C(n2278), .D(n2277), .Y(n2290) );
AOI22X1TS U2842 ( .A0(n3176), .A1(intDX_EWSW[5]), .B0(n3168), .B1(
intDX_EWSW[28]), .Y(n2282) );
AOI22X1TS U2843 ( .A0(n3048), .A1(intDX_EWSW[3]), .B0(n3162), .B1(
intDX_EWSW[2]), .Y(n2283) );
AOI22X1TS U2844 ( .A0(n3175), .A1(intDX_EWSW[0]), .B0(n3051), .B1(
intDX_EWSW[8]), .Y(n2284) );
NOR4X1TS U2845 ( .A(n2288), .B(n2287), .C(n2286), .D(n2285), .Y(n2289) );
NAND4XLTS U2846 ( .A(n2292), .B(n2291), .C(n2290), .D(n2289), .Y(n2293) );
CLKXOR2X2TS U2847 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2752) );
INVX2TS U2848 ( .A(n2752), .Y(n2299) );
OAI21XLTS U2849 ( .A0(n2299), .A1(n2753), .B0(n2385), .Y(n2297) );
BUFX4TS U2850 ( .A(n2388), .Y(n2383) );
AOI22X1TS U2851 ( .A0(intDX_EWSW[63]), .A1(n2297), .B0(SIGN_FLAG_EXP), .B1(
n2408), .Y(n2298) );
OAI31X1TS U2852 ( .A0(n2755), .A1(n2299), .A2(n2773), .B0(n2298), .Y(n1512)
);
BUFX4TS U2853 ( .A(n2773), .Y(n2390) );
AOI22X1TS U2854 ( .A0(intDX_EWSW[49]), .A1(n1795), .B0(DMP_EXP_EWSW[49]),
.B1(n2408), .Y(n2300) );
OAI21XLTS U2855 ( .A0(n3200), .A1(n2390), .B0(n2300), .Y(n1528) );
AOI22X1TS U2856 ( .A0(intDX_EWSW[16]), .A1(n2356), .B0(DMP_EXP_EWSW[16]),
.B1(n2388), .Y(n2301) );
OAI21XLTS U2857 ( .A0(n3171), .A1(n2390), .B0(n2301), .Y(n1561) );
AOI22X1TS U2858 ( .A0(intDX_EWSW[44]), .A1(n1795), .B0(DMP_EXP_EWSW[44]),
.B1(n2700), .Y(n2302) );
OAI21XLTS U2859 ( .A0(n3194), .A1(n2390), .B0(n2302), .Y(n1533) );
AOI22X1TS U2860 ( .A0(intDX_EWSW[20]), .A1(n2356), .B0(DMP_EXP_EWSW[20]),
.B1(n2388), .Y(n2303) );
OAI21XLTS U2861 ( .A0(n3165), .A1(n2390), .B0(n2303), .Y(n1557) );
AOI22X1TS U2862 ( .A0(intDX_EWSW[43]), .A1(n1795), .B0(DMP_EXP_EWSW[43]),
.B1(n2412), .Y(n2304) );
OAI21XLTS U2863 ( .A0(n3058), .A1(n2390), .B0(n2304), .Y(n1534) );
AOI22X1TS U2864 ( .A0(intDX_EWSW[46]), .A1(n1795), .B0(DMP_EXP_EWSW[46]),
.B1(n2700), .Y(n2305) );
OAI21XLTS U2865 ( .A0(n3195), .A1(n2390), .B0(n2305), .Y(n1531) );
AOI22X1TS U2866 ( .A0(intDX_EWSW[40]), .A1(n2356), .B0(DMP_EXP_EWSW[40]),
.B1(n2700), .Y(n2306) );
OAI21XLTS U2867 ( .A0(n3192), .A1(n2390), .B0(n2306), .Y(n1537) );
AOI22X1TS U2868 ( .A0(intDX_EWSW[28]), .A1(n2356), .B0(DMP_EXP_EWSW[28]),
.B1(n2700), .Y(n2307) );
OAI21XLTS U2869 ( .A0(n3168), .A1(n2390), .B0(n2307), .Y(n1549) );
AOI22X1TS U2870 ( .A0(intDX_EWSW[30]), .A1(n2356), .B0(DMP_EXP_EWSW[30]),
.B1(n2388), .Y(n2308) );
OAI21XLTS U2871 ( .A0(n3203), .A1(n2390), .B0(n2308), .Y(n1547) );
AOI22X1TS U2872 ( .A0(intDX_EWSW[25]), .A1(n2356), .B0(DMP_EXP_EWSW[25]),
.B1(n2383), .Y(n2309) );
OAI21XLTS U2873 ( .A0(n3046), .A1(n2390), .B0(n2309), .Y(n1552) );
AOI22X1TS U2874 ( .A0(intDX_EWSW[47]), .A1(n1795), .B0(DMP_EXP_EWSW[47]),
.B1(n2408), .Y(n2310) );
OAI21XLTS U2875 ( .A0(n3055), .A1(n2390), .B0(n2310), .Y(n1530) );
AOI22X1TS U2876 ( .A0(intDX_EWSW[26]), .A1(n2356), .B0(DMP_EXP_EWSW[26]),
.B1(n2383), .Y(n2311) );
OAI21XLTS U2877 ( .A0(n3167), .A1(n2390), .B0(n2311), .Y(n1551) );
AOI22X1TS U2878 ( .A0(intDX_EWSW[48]), .A1(n1795), .B0(DMP_EXP_EWSW[48]),
.B1(n2408), .Y(n2312) );
OAI21XLTS U2879 ( .A0(n3170), .A1(n2390), .B0(n2312), .Y(n1529) );
AOI22X1TS U2880 ( .A0(intDX_EWSW[45]), .A1(n1795), .B0(DMP_EXP_EWSW[45]),
.B1(n2412), .Y(n2313) );
OAI21XLTS U2881 ( .A0(n3188), .A1(n2390), .B0(n2313), .Y(n1532) );
BUFX4TS U2882 ( .A(n2773), .Y(n2776) );
AOI22X1TS U2883 ( .A0(intDX_EWSW[13]), .A1(n2356), .B0(DMP_EXP_EWSW[13]),
.B1(n2388), .Y(n2314) );
AOI22X1TS U2884 ( .A0(intDX_EWSW[12]), .A1(n2346), .B0(DMP_EXP_EWSW[12]),
.B1(n2388), .Y(n2315) );
OAI21XLTS U2885 ( .A0(n3163), .A1(n2776), .B0(n2315), .Y(n1565) );
AOI22X1TS U2886 ( .A0(intDX_EWSW[15]), .A1(n2356), .B0(DMP_EXP_EWSW[15]),
.B1(n2388), .Y(n2316) );
OAI21XLTS U2887 ( .A0(n3059), .A1(n2776), .B0(n2316), .Y(n1562) );
AOI22X1TS U2888 ( .A0(intDX_EWSW[51]), .A1(n1795), .B0(DMP_EXP_EWSW[51]),
.B1(n2412), .Y(n2317) );
OAI21XLTS U2889 ( .A0(n3196), .A1(n2776), .B0(n2317), .Y(n1526) );
AOI22X1TS U2890 ( .A0(intDX_EWSW[50]), .A1(n1795), .B0(DMP_EXP_EWSW[50]),
.B1(n2412), .Y(n2318) );
OAI21XLTS U2891 ( .A0(n3177), .A1(n2776), .B0(n2318), .Y(n1527) );
AOI22X1TS U2892 ( .A0(intDX_EWSW[29]), .A1(n2356), .B0(DMP_EXP_EWSW[29]),
.B1(n2753), .Y(n2319) );
OAI21XLTS U2893 ( .A0(n3049), .A1(n2776), .B0(n2319), .Y(n1548) );
AOI22X1TS U2894 ( .A0(intDX_EWSW[0]), .A1(n1795), .B0(DMP_EXP_EWSW[0]), .B1(
n2753), .Y(n2320) );
OAI21XLTS U2895 ( .A0(n3175), .A1(n2776), .B0(n2320), .Y(n1577) );
AOI22X1TS U2896 ( .A0(intDX_EWSW[17]), .A1(n2356), .B0(DMP_EXP_EWSW[17]),
.B1(n2388), .Y(n2321) );
OAI21XLTS U2897 ( .A0(n3044), .A1(n2776), .B0(n2321), .Y(n1560) );
AOI22X1TS U2898 ( .A0(intDX_EWSW[29]), .A1(n1794), .B0(DmP_EXP_EWSW[29]),
.B1(n2412), .Y(n2322) );
OAI21XLTS U2899 ( .A0(n3049), .A1(n1798), .B0(n2322), .Y(n1242) );
AOI22X1TS U2900 ( .A0(intDX_EWSW[31]), .A1(n1794), .B0(DmP_EXP_EWSW[31]),
.B1(n2753), .Y(n2323) );
OAI21XLTS U2901 ( .A0(n3061), .A1(n2376), .B0(n2323), .Y(n1238) );
AOI22X1TS U2902 ( .A0(intDX_EWSW[30]), .A1(n2418), .B0(DmP_EXP_EWSW[30]),
.B1(n2383), .Y(n2324) );
OAI21XLTS U2903 ( .A0(n3203), .A1(n1798), .B0(n2324), .Y(n1240) );
AOI22X1TS U2904 ( .A0(intDX_EWSW[41]), .A1(n1794), .B0(DmP_EXP_EWSW[41]),
.B1(n2388), .Y(n2325) );
OAI21XLTS U2905 ( .A0(n3057), .A1(n1798), .B0(n2325), .Y(n1218) );
AOI22X1TS U2906 ( .A0(intDX_EWSW[46]), .A1(n1794), .B0(DmP_EXP_EWSW[46]),
.B1(n2412), .Y(n2326) );
OAI21XLTS U2907 ( .A0(n3195), .A1(n2376), .B0(n2326), .Y(n1208) );
AOI22X1TS U2908 ( .A0(intDX_EWSW[33]), .A1(n1794), .B0(DmP_EXP_EWSW[33]),
.B1(n2700), .Y(n2327) );
OAI21XLTS U2909 ( .A0(n3189), .A1(n1798), .B0(n2327), .Y(n1234) );
AOI22X1TS U2910 ( .A0(intDX_EWSW[34]), .A1(n2418), .B0(DmP_EXP_EWSW[34]),
.B1(n2408), .Y(n2328) );
OAI21XLTS U2911 ( .A0(n3190), .A1(n2376), .B0(n2328), .Y(n1232) );
AOI22X1TS U2912 ( .A0(intDX_EWSW[45]), .A1(n1794), .B0(DmP_EXP_EWSW[45]),
.B1(n2388), .Y(n2329) );
AOI22X1TS U2913 ( .A0(intDX_EWSW[26]), .A1(n2418), .B0(DmP_EXP_EWSW[26]),
.B1(n2383), .Y(n2330) );
OAI21XLTS U2914 ( .A0(n3167), .A1(n1798), .B0(n2330), .Y(n1248) );
AOI22X1TS U2915 ( .A0(intDX_EWSW[35]), .A1(n1794), .B0(DmP_EXP_EWSW[35]),
.B1(n2412), .Y(n2331) );
OAI21XLTS U2916 ( .A0(n3056), .A1(n1798), .B0(n2331), .Y(n1230) );
AOI22X1TS U2917 ( .A0(intDX_EWSW[42]), .A1(n1794), .B0(DmP_EXP_EWSW[42]),
.B1(n2700), .Y(n2332) );
OAI21XLTS U2918 ( .A0(n3193), .A1(n1798), .B0(n2332), .Y(n1216) );
AOI22X1TS U2919 ( .A0(intDX_EWSW[27]), .A1(n2418), .B0(DmP_EXP_EWSW[27]),
.B1(n2383), .Y(n2333) );
OAI21XLTS U2920 ( .A0(n3047), .A1(n1798), .B0(n2333), .Y(n1246) );
AOI22X1TS U2921 ( .A0(intDX_EWSW[36]), .A1(n2418), .B0(DmP_EXP_EWSW[36]),
.B1(n2753), .Y(n2334) );
OAI21XLTS U2922 ( .A0(n3191), .A1(n2376), .B0(n2334), .Y(n1228) );
AOI22X1TS U2923 ( .A0(intDX_EWSW[43]), .A1(n1794), .B0(DmP_EXP_EWSW[43]),
.B1(n2408), .Y(n2335) );
OAI21XLTS U2924 ( .A0(n3058), .A1(n1798), .B0(n2335), .Y(n1214) );
AOI22X1TS U2925 ( .A0(intDX_EWSW[28]), .A1(n1794), .B0(DmP_EXP_EWSW[28]),
.B1(n2700), .Y(n2336) );
OAI21XLTS U2926 ( .A0(n3168), .A1(n2376), .B0(n2336), .Y(n1244) );
AOI22X1TS U2927 ( .A0(intDX_EWSW[25]), .A1(n2418), .B0(DmP_EXP_EWSW[25]),
.B1(n2408), .Y(n2337) );
OAI21XLTS U2928 ( .A0(n3046), .A1(n1798), .B0(n2337), .Y(n1250) );
AOI22X1TS U2929 ( .A0(intDX_EWSW[18]), .A1(n1795), .B0(DMP_EXP_EWSW[18]),
.B1(n2388), .Y(n2338) );
OAI21XLTS U2930 ( .A0(n3164), .A1(n2773), .B0(n2338), .Y(n1559) );
AOI22X1TS U2931 ( .A0(intDX_EWSW[9]), .A1(n2346), .B0(DMP_EXP_EWSW[9]), .B1(
n2753), .Y(n2339) );
OAI21XLTS U2932 ( .A0(n3158), .A1(n2773), .B0(n2339), .Y(n1568) );
AOI22X1TS U2933 ( .A0(intDX_EWSW[6]), .A1(n1795), .B0(DMP_EXP_EWSW[6]), .B1(
n2753), .Y(n2340) );
OAI21XLTS U2934 ( .A0(n3062), .A1(n2773), .B0(n2340), .Y(n1571) );
AOI22X1TS U2935 ( .A0(intDX_EWSW[22]), .A1(n1795), .B0(DMP_EXP_EWSW[22]),
.B1(n2388), .Y(n2341) );
OAI21XLTS U2936 ( .A0(n3202), .A1(n2773), .B0(n2341), .Y(n1555) );
AOI22X1TS U2937 ( .A0(intDX_EWSW[19]), .A1(n2356), .B0(DMP_EXP_EWSW[19]),
.B1(n2388), .Y(n2342) );
OAI21XLTS U2938 ( .A0(n3045), .A1(n2773), .B0(n2342), .Y(n1558) );
AOI22X1TS U2939 ( .A0(intDX_EWSW[7]), .A1(n2346), .B0(DMP_EXP_EWSW[7]), .B1(
n2753), .Y(n2343) );
OAI21XLTS U2940 ( .A0(n3204), .A1(n2773), .B0(n2343), .Y(n1570) );
AOI22X1TS U2941 ( .A0(intDX_EWSW[8]), .A1(n2346), .B0(DMP_EXP_EWSW[8]), .B1(
n2388), .Y(n2344) );
OAI21XLTS U2942 ( .A0(n3051), .A1(n2773), .B0(n2344), .Y(n1569) );
AOI22X1TS U2943 ( .A0(intDX_EWSW[3]), .A1(n2346), .B0(DMP_EXP_EWSW[3]), .B1(
n2753), .Y(n2345) );
OAI21XLTS U2944 ( .A0(n3048), .A1(n2773), .B0(n2345), .Y(n1574) );
AOI22X1TS U2945 ( .A0(intDX_EWSW[12]), .A1(n1794), .B0(DmP_EXP_EWSW[12]),
.B1(n2412), .Y(n2347) );
OAI21XLTS U2946 ( .A0(n3163), .A1(n2385), .B0(n2347), .Y(n1276) );
AOI22X1TS U2947 ( .A0(intDX_EWSW[11]), .A1(n2418), .B0(DmP_EXP_EWSW[11]),
.B1(n2412), .Y(n2348) );
OAI21XLTS U2948 ( .A0(n3052), .A1(n2385), .B0(n2348), .Y(n1278) );
AOI22X1TS U2949 ( .A0(intDX_EWSW[32]), .A1(n1794), .B0(DmP_EXP_EWSW[32]),
.B1(n2408), .Y(n2349) );
OAI21XLTS U2950 ( .A0(n3169), .A1(n1798), .B0(n2349), .Y(n1236) );
AOI22X1TS U2951 ( .A0(intDX_EWSW[40]), .A1(n1794), .B0(DmP_EXP_EWSW[40]),
.B1(n2412), .Y(n2350) );
OAI21XLTS U2952 ( .A0(n3192), .A1(n1798), .B0(n2350), .Y(n1220) );
AOI22X1TS U2953 ( .A0(intDX_EWSW[47]), .A1(n1794), .B0(DmP_EXP_EWSW[47]),
.B1(n2412), .Y(n2351) );
OAI21XLTS U2954 ( .A0(n3055), .A1(n2376), .B0(n2351), .Y(n1206) );
AOI22X1TS U2955 ( .A0(intDX_EWSW[37]), .A1(n2418), .B0(DmP_EXP_EWSW[37]),
.B1(n2753), .Y(n2352) );
OAI21XLTS U2956 ( .A0(n3186), .A1(n1798), .B0(n2352), .Y(n1226) );
AOI22X1TS U2957 ( .A0(intDX_EWSW[38]), .A1(n1794), .B0(DmP_EXP_EWSW[38]),
.B1(n2700), .Y(n2353) );
OAI21XLTS U2958 ( .A0(n3214), .A1(n1798), .B0(n2353), .Y(n1224) );
AOI22X1TS U2959 ( .A0(intDX_EWSW[44]), .A1(n1794), .B0(DmP_EXP_EWSW[44]),
.B1(n2408), .Y(n2354) );
OAI21XLTS U2960 ( .A0(n3194), .A1(n2376), .B0(n2354), .Y(n1212) );
AOI22X1TS U2961 ( .A0(DmP_EXP_EWSW[57]), .A1(n2412), .B0(intDX_EWSW[57]),
.B1(n2418), .Y(n2355) );
OAI21XLTS U2962 ( .A0(n3178), .A1(n2376), .B0(n2355), .Y(n1191) );
BUFX3TS U2963 ( .A(n2356), .Y(n2386) );
AOI22X1TS U2964 ( .A0(intDX_EWSW[14]), .A1(n2386), .B0(DMP_EXP_EWSW[14]),
.B1(n2388), .Y(n2357) );
OAI21XLTS U2965 ( .A0(n3201), .A1(n2776), .B0(n2357), .Y(n1563) );
AOI22X1TS U2966 ( .A0(intDX_EWSW[34]), .A1(n2386), .B0(DMP_EXP_EWSW[34]),
.B1(n2753), .Y(n2358) );
OAI21XLTS U2967 ( .A0(n3190), .A1(n2773), .B0(n2358), .Y(n1543) );
AOI22X1TS U2968 ( .A0(intDX_EWSW[42]), .A1(n2386), .B0(DMP_EXP_EWSW[42]),
.B1(n2412), .Y(n2359) );
OAI21XLTS U2969 ( .A0(n3193), .A1(n2390), .B0(n2359), .Y(n1535) );
AOI22X1TS U2970 ( .A0(intDX_EWSW[41]), .A1(n2386), .B0(DMP_EXP_EWSW[41]),
.B1(n2753), .Y(n2360) );
AOI22X1TS U2971 ( .A0(intDX_EWSW[35]), .A1(n2386), .B0(DMP_EXP_EWSW[35]),
.B1(n2388), .Y(n2361) );
OAI21XLTS U2972 ( .A0(n3056), .A1(n2773), .B0(n2361), .Y(n1542) );
AOI22X1TS U2973 ( .A0(intDX_EWSW[21]), .A1(n2386), .B0(DMP_EXP_EWSW[21]),
.B1(n2388), .Y(n2362) );
OAI21XLTS U2974 ( .A0(n3161), .A1(n2390), .B0(n2362), .Y(n1556) );
AOI22X1TS U2975 ( .A0(intDX_EWSW[36]), .A1(n2386), .B0(DMP_EXP_EWSW[36]),
.B1(n2700), .Y(n2363) );
OAI21XLTS U2976 ( .A0(n3191), .A1(n2773), .B0(n2363), .Y(n1541) );
AOI22X1TS U2977 ( .A0(intDX_EWSW[33]), .A1(n2386), .B0(DMP_EXP_EWSW[33]),
.B1(n2408), .Y(n2364) );
OAI21XLTS U2978 ( .A0(n3189), .A1(n2776), .B0(n2364), .Y(n1544) );
INVX4TS U2979 ( .A(n2218), .Y(n2416) );
AOI22X1TS U2980 ( .A0(intDX_EWSW[21]), .A1(n2416), .B0(DmP_EXP_EWSW[21]),
.B1(n2383), .Y(n2365) );
OAI21XLTS U2981 ( .A0(n3161), .A1(n2385), .B0(n2365), .Y(n1258) );
AOI22X1TS U2982 ( .A0(intDX_EWSW[23]), .A1(n2416), .B0(DmP_EXP_EWSW[23]),
.B1(n2383), .Y(n2366) );
OAI21XLTS U2983 ( .A0(n3060), .A1(n1798), .B0(n2366), .Y(n1254) );
AOI22X1TS U2984 ( .A0(intDX_EWSW[14]), .A1(n2416), .B0(DmP_EXP_EWSW[14]),
.B1(n2383), .Y(n2367) );
OAI21XLTS U2985 ( .A0(n3201), .A1(n2385), .B0(n2367), .Y(n1272) );
AOI22X1TS U2986 ( .A0(intDX_EWSW[13]), .A1(n2416), .B0(DmP_EXP_EWSW[13]),
.B1(n2700), .Y(n2368) );
OAI21XLTS U2987 ( .A0(n3160), .A1(n2385), .B0(n2368), .Y(n1274) );
AOI22X1TS U2988 ( .A0(intDX_EWSW[15]), .A1(n2416), .B0(DmP_EXP_EWSW[15]),
.B1(n2412), .Y(n2369) );
OAI21XLTS U2989 ( .A0(n3059), .A1(n2385), .B0(n2369), .Y(n1270) );
AOI22X1TS U2990 ( .A0(intDX_EWSW[19]), .A1(n2416), .B0(DmP_EXP_EWSW[19]),
.B1(n2383), .Y(n2370) );
OAI21XLTS U2991 ( .A0(n3045), .A1(n2385), .B0(n2370), .Y(n1262) );
AOI22X1TS U2992 ( .A0(intDX_EWSW[17]), .A1(n2416), .B0(DmP_EXP_EWSW[17]),
.B1(n2383), .Y(n2371) );
OAI21XLTS U2993 ( .A0(n3044), .A1(n2385), .B0(n2371), .Y(n1266) );
AOI22X1TS U2994 ( .A0(intDX_EWSW[18]), .A1(n2416), .B0(DmP_EXP_EWSW[18]),
.B1(n2383), .Y(n2372) );
OAI21XLTS U2995 ( .A0(n3164), .A1(n2385), .B0(n2372), .Y(n1264) );
AOI22X1TS U2996 ( .A0(intDX_EWSW[20]), .A1(n2416), .B0(DmP_EXP_EWSW[20]),
.B1(n2383), .Y(n2373) );
OAI21XLTS U2997 ( .A0(n3165), .A1(n2376), .B0(n2373), .Y(n1260) );
AOI22X1TS U2998 ( .A0(intDX_EWSW[22]), .A1(n2416), .B0(DmP_EXP_EWSW[22]),
.B1(n2383), .Y(n2374) );
OAI21XLTS U2999 ( .A0(n3202), .A1(n1798), .B0(n2374), .Y(n1256) );
AOI22X1TS U3000 ( .A0(intDY_EWSW[60]), .A1(n2418), .B0(DMP_EXP_EWSW[60]),
.B1(n2412), .Y(n2375) );
OAI21XLTS U3001 ( .A0(n3182), .A1(n2376), .B0(n2375), .Y(n1517) );
AOI22X1TS U3002 ( .A0(intDX_EWSW[10]), .A1(n2418), .B0(DmP_EXP_EWSW[10]),
.B1(n2753), .Y(n2377) );
OAI21XLTS U3003 ( .A0(n3159), .A1(n1798), .B0(n2377), .Y(n1280) );
AOI22X1TS U3004 ( .A0(intDX_EWSW[32]), .A1(n2386), .B0(DMP_EXP_EWSW[32]),
.B1(n2388), .Y(n2378) );
OAI21XLTS U3005 ( .A0(n3169), .A1(n2218), .B0(n2378), .Y(n1545) );
AOI22X1TS U3006 ( .A0(intDX_EWSW[24]), .A1(n2416), .B0(DmP_EXP_EWSW[24]),
.B1(n2383), .Y(n2379) );
OAI21XLTS U3007 ( .A0(n3166), .A1(n1798), .B0(n2379), .Y(n1252) );
AOI22X1TS U3008 ( .A0(intDX_EWSW[39]), .A1(n2386), .B0(DMP_EXP_EWSW[39]),
.B1(n2412), .Y(n2380) );
OAI21XLTS U3009 ( .A0(n3187), .A1(n2776), .B0(n2380), .Y(n1538) );
AOI22X1TS U3010 ( .A0(intDX_EWSW[39]), .A1(n2416), .B0(DmP_EXP_EWSW[39]),
.B1(n2408), .Y(n2381) );
OAI21XLTS U3011 ( .A0(n3187), .A1(n1798), .B0(n2381), .Y(n1222) );
AOI22X1TS U3012 ( .A0(intDX_EWSW[37]), .A1(n2386), .B0(DMP_EXP_EWSW[37]),
.B1(n2388), .Y(n2382) );
OAI21XLTS U3013 ( .A0(n3186), .A1(n2218), .B0(n2382), .Y(n1540) );
AOI22X1TS U3014 ( .A0(intDX_EWSW[16]), .A1(n2416), .B0(DmP_EXP_EWSW[16]),
.B1(n2383), .Y(n2384) );
OAI21XLTS U3015 ( .A0(n3171), .A1(n2376), .B0(n2384), .Y(n1268) );
AOI22X1TS U3016 ( .A0(intDX_EWSW[38]), .A1(n2386), .B0(DMP_EXP_EWSW[38]),
.B1(n2753), .Y(n2387) );
OAI21XLTS U3017 ( .A0(n3214), .A1(n2218), .B0(n2387), .Y(n1539) );
AOI22X1TS U3018 ( .A0(intDX_EWSW[10]), .A1(n1795), .B0(DMP_EXP_EWSW[10]),
.B1(n2388), .Y(n2389) );
OAI21XLTS U3019 ( .A0(n3159), .A1(n2390), .B0(n2389), .Y(n1567) );
AOI22X1TS U3020 ( .A0(intDX_EWSW[2]), .A1(n1795), .B0(DMP_EXP_EWSW[2]), .B1(
n2753), .Y(n2391) );
OAI21XLTS U3021 ( .A0(n3162), .A1(n2773), .B0(n2391), .Y(n1575) );
AOI22X1TS U3022 ( .A0(intDX_EWSW[4]), .A1(n1795), .B0(DMP_EXP_EWSW[4]), .B1(
n2753), .Y(n2392) );
OAI21XLTS U3023 ( .A0(n3050), .A1(n2773), .B0(n2392), .Y(n1573) );
AOI22X1TS U3024 ( .A0(intDX_EWSW[1]), .A1(n1795), .B0(DMP_EXP_EWSW[1]), .B1(
n2753), .Y(n2393) );
OAI21XLTS U3025 ( .A0(n3213), .A1(n2773), .B0(n2393), .Y(n1576) );
AOI22X1TS U3026 ( .A0(intDX_EWSW[5]), .A1(n1795), .B0(DMP_EXP_EWSW[5]), .B1(
n2753), .Y(n2394) );
OAI21XLTS U3027 ( .A0(n3176), .A1(n2773), .B0(n2394), .Y(n1572) );
AOI22X1TS U3028 ( .A0(DMP_EXP_EWSW[57]), .A1(n2408), .B0(intDX_EWSW[57]),
.B1(n1795), .Y(n2395) );
OAI21XLTS U3029 ( .A0(n3178), .A1(n2776), .B0(n2395), .Y(n1520) );
AOI22X1TS U3030 ( .A0(intDX_EWSW[6]), .A1(n1794), .B0(DmP_EXP_EWSW[6]), .B1(
n2408), .Y(n2396) );
OAI21XLTS U3031 ( .A0(n3062), .A1(n2376), .B0(n2396), .Y(n1288) );
AOI22X1TS U3032 ( .A0(intDX_EWSW[3]), .A1(n2418), .B0(DmP_EXP_EWSW[3]), .B1(
n2412), .Y(n2397) );
OAI21XLTS U3033 ( .A0(n3048), .A1(n2376), .B0(n2397), .Y(n1294) );
AOI22X1TS U3034 ( .A0(intDX_EWSW[7]), .A1(n2418), .B0(DmP_EXP_EWSW[7]), .B1(
n2412), .Y(n2398) );
OAI21XLTS U3035 ( .A0(n3204), .A1(n2376), .B0(n2398), .Y(n1286) );
AOI22X1TS U3036 ( .A0(intDX_EWSW[1]), .A1(n1794), .B0(DmP_EXP_EWSW[1]), .B1(
n2412), .Y(n2399) );
OAI21XLTS U3037 ( .A0(n3213), .A1(n2376), .B0(n2399), .Y(n1298) );
AOI22X1TS U3038 ( .A0(intDY_EWSW[61]), .A1(n2418), .B0(DMP_EXP_EWSW[61]),
.B1(n2412), .Y(n2400) );
OAI21XLTS U3039 ( .A0(n3180), .A1(n2376), .B0(n2400), .Y(n1516) );
AOI22X1TS U3040 ( .A0(intDX_EWSW[8]), .A1(n2418), .B0(DmP_EXP_EWSW[8]), .B1(
n2412), .Y(n2401) );
OAI21XLTS U3041 ( .A0(n3051), .A1(n1798), .B0(n2401), .Y(n1284) );
AOI22X1TS U3042 ( .A0(intDY_EWSW[59]), .A1(n1794), .B0(DMP_EXP_EWSW[59]),
.B1(n2412), .Y(n2402) );
AOI22X1TS U3043 ( .A0(intDX_EWSW[0]), .A1(n1794), .B0(DmP_EXP_EWSW[0]), .B1(
n2388), .Y(n2403) );
OAI21XLTS U3044 ( .A0(n3175), .A1(n1798), .B0(n2403), .Y(n1300) );
AOI22X1TS U3045 ( .A0(intDX_EWSW[5]), .A1(n2418), .B0(DmP_EXP_EWSW[5]), .B1(
n2412), .Y(n2404) );
OAI21XLTS U3046 ( .A0(n3176), .A1(n2385), .B0(n2404), .Y(n1290) );
AOI22X1TS U3047 ( .A0(intDX_EWSW[2]), .A1(n2418), .B0(DmP_EXP_EWSW[2]), .B1(
n2700), .Y(n2405) );
OAI21XLTS U3048 ( .A0(n3162), .A1(n2774), .B0(n2405), .Y(n1296) );
AOI22X1TS U3049 ( .A0(intDY_EWSW[62]), .A1(n2418), .B0(DMP_EXP_EWSW[62]),
.B1(n2408), .Y(n2406) );
OAI21XLTS U3050 ( .A0(n3053), .A1(n2774), .B0(n2406), .Y(n1515) );
AOI22X1TS U3051 ( .A0(intDX_EWSW[9]), .A1(n1794), .B0(DmP_EXP_EWSW[9]), .B1(
n2408), .Y(n2407) );
OAI21XLTS U3052 ( .A0(n3158), .A1(n2774), .B0(n2407), .Y(n1282) );
AOI22X1TS U3053 ( .A0(intDX_EWSW[4]), .A1(n2418), .B0(DmP_EXP_EWSW[4]), .B1(
n2700), .Y(n2409) );
OAI21XLTS U3054 ( .A0(n3050), .A1(n2774), .B0(n2409), .Y(n1292) );
AOI22X1TS U3055 ( .A0(intDX_EWSW[48]), .A1(n2418), .B0(DmP_EXP_EWSW[48]),
.B1(n2412), .Y(n2410) );
OAI21XLTS U3056 ( .A0(n3170), .A1(n2774), .B0(n2410), .Y(n1204) );
AOI22X1TS U3057 ( .A0(intDX_EWSW[50]), .A1(n1794), .B0(DmP_EXP_EWSW[50]),
.B1(n2408), .Y(n2411) );
OAI21XLTS U3058 ( .A0(n3177), .A1(n2774), .B0(n2411), .Y(n1200) );
AOI22X1TS U3059 ( .A0(intDY_EWSW[58]), .A1(n1794), .B0(DMP_EXP_EWSW[58]),
.B1(n2700), .Y(n2413) );
OAI21XLTS U3060 ( .A0(n3181), .A1(n2774), .B0(n2413), .Y(n1519) );
AOI22X1TS U3061 ( .A0(intDX_EWSW[49]), .A1(n1794), .B0(DmP_EXP_EWSW[49]),
.B1(n2700), .Y(n2414) );
OAI21XLTS U3062 ( .A0(n3200), .A1(n2774), .B0(n2414), .Y(n1202) );
AOI22X1TS U3063 ( .A0(intDX_EWSW[51]), .A1(n2418), .B0(DmP_EXP_EWSW[51]),
.B1(n2700), .Y(n2415) );
OAI21XLTS U3064 ( .A0(n3196), .A1(n2774), .B0(n2415), .Y(n1198) );
INVX2TS U3065 ( .A(n2417), .Y(n1525) );
INVX2TS U3066 ( .A(n2419), .Y(n1196) );
AOI2BB2XLTS U3067 ( .B0(beg_OP), .B1(n3043), .A0N(n3043), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2420) );
NAND3XLTS U3068 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3043), .C(
n3179), .Y(n2696) );
OAI21XLTS U3069 ( .A0(n2699), .A1(n2420), .B0(n2696), .Y(n1792) );
INVX2TS U3070 ( .A(n2421), .Y(n2864) );
XOR2X1TS U3071 ( .A(DmP_mant_SFG_SWR[54]), .B(intadd_72_n1), .Y(n2422) );
NOR2XLTS U3072 ( .A(Raw_mant_NRM_SWR[29]), .B(n2674), .Y(n2428) );
NAND2X1TS U3073 ( .A(n3019), .B(n3037), .Y(n2426) );
AOI22X1TS U3074 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2428), .B0(n2427), .B1(
n2426), .Y(n2435) );
OAI31X1TS U3075 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2430), .A2(
Raw_mant_NRM_SWR[24]), .B0(n2429), .Y(n2434) );
OAI21XLTS U3076 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n2431), .Y(n2432) );
NAND2X1TS U3077 ( .A(n3017), .B(n3026), .Y(n2450) );
INVX2TS U3078 ( .A(n2436), .Y(n2443) );
NAND2X1TS U3079 ( .A(n3144), .B(n3042), .Y(n2441) );
NOR2XLTS U3080 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2438) );
OAI32X1TS U3081 ( .A0(n2441), .A1(n2440), .A2(n2439), .B0(n2438), .B1(n2441),
.Y(n2442) );
AOI211X4TS U3082 ( .A0(n2448), .A1(Raw_mant_NRM_SWR[16]), .B0(n2684), .C0(
n2447), .Y(n2473) );
NAND4BXLTS U3083 ( .AN(n2450), .B(n2449), .C(Raw_mant_NRM_SWR[37]), .D(n3124), .Y(n2453) );
AOI21X1TS U3084 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n3025), .B0(
Raw_mant_NRM_SWR[51]), .Y(n2451) );
AOI2BB1XLTS U3085 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n2451), .B0(
Raw_mant_NRM_SWR[53]), .Y(n2452) );
OAI22X1TS U3086 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2453), .B0(
Raw_mant_NRM_SWR[54]), .B1(n2452), .Y(n2454) );
AOI31XLTS U3087 ( .A0(n2455), .A1(Raw_mant_NRM_SWR[45]), .A2(n3122), .B0(
n2454), .Y(n2457) );
AOI31XLTS U3088 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2459), .A2(n3153), .B0(
n2458), .Y(n2461) );
NAND2X1TS U3089 ( .A(n2466), .B(n2788), .Y(n2688) );
INVX2TS U3090 ( .A(n2688), .Y(n2464) );
NAND2X1TS U3091 ( .A(n2473), .B(n2464), .Y(n2505) );
AOI21X1TS U3092 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n2787), .B0(n2687), .Y(
n2469) );
AND2X2TS U3093 ( .A(n2469), .B(n2465), .Y(n2490) );
NOR2X1TS U3094 ( .A(n2787), .B(n2466), .Y(n2494) );
AOI22X1TS U3095 ( .A0(n1797), .A1(Raw_mant_NRM_SWR[1]), .B0(
DmP_mant_SHT1_SW[51]), .B1(n2787), .Y(n2467) );
NAND2X1TS U3096 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2787), .Y(n2491) );
NAND2X1TS U3097 ( .A(n2467), .B(n2491), .Y(n2508) );
AOI22X1TS U3098 ( .A0(n2470), .A1(Data_array_SWR[39]), .B0(n2490), .B1(n2508), .Y(n2468) );
NOR2X1TS U3099 ( .A(n2788), .B(Shift_amount_SHT1_EWR[0]), .Y(n2477) );
INVX2TS U3100 ( .A(n2477), .Y(n2591) );
INVX2TS U3101 ( .A(n2722), .Y(n2656) );
BUFX6TS U3102 ( .A(n2656), .Y(n2651) );
AOI22X1TS U3103 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2464), .B0(n2576), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2472) );
AOI22X1TS U3104 ( .A0(Raw_mant_NRM_SWR[52]), .A1(n1797), .B0(n2575), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2471) );
NAND2X1TS U3105 ( .A(n2472), .B(n2471), .Y(n2721) );
AOI22X1TS U3106 ( .A0(n2470), .A1(Data_array_SWR[2]), .B0(n2490), .B1(n2721),
.Y(n2476) );
NAND2X1TS U3107 ( .A(Raw_mant_NRM_SWR[49]), .B(n2580), .Y(n2475) );
BUFX4TS U3108 ( .A(n2470), .Y(n2728) );
AOI22X1TS U3109 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2464), .B0(n2630), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2479) );
AOI22X1TS U3110 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n1797), .B0(n2575), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2478) );
NAND2X1TS U3111 ( .A(n2479), .B(n2478), .Y(n2534) );
AOI22X1TS U3112 ( .A0(n2728), .A1(Data_array_SWR[3]), .B0(n2490), .B1(n2534),
.Y(n2481) );
NAND2X1TS U3113 ( .A(Raw_mant_NRM_SWR[48]), .B(n2580), .Y(n2480) );
AOI22X1TS U3114 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2464), .B0(n2630), .B1(
DmP_mant_SHT1_SW[5]), .Y(n2483) );
AOI22X1TS U3115 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n1797), .B0(n2575), .B1(
DmP_mant_SHT1_SW[4]), .Y(n2482) );
NAND2X1TS U3116 ( .A(n2483), .B(n2482), .Y(n2511) );
AOI22X1TS U3117 ( .A0(n2470), .A1(Data_array_SWR[6]), .B0(n2490), .B1(n2511),
.Y(n2485) );
NAND2X1TS U3118 ( .A(Raw_mant_NRM_SWR[45]), .B(n2580), .Y(n2484) );
BUFX4TS U3119 ( .A(n1797), .Y(n2618) );
AOI22X1TS U3120 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2464), .B0(n2630), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2487) );
AOI22X1TS U3121 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n1797), .B0(n2575), .B1(
DmP_mant_SHT1_SW[7]), .Y(n2486) );
NAND2X1TS U3122 ( .A(n2487), .B(n2486), .Y(n2504) );
AOI22X1TS U3123 ( .A0(n2728), .A1(Data_array_SWR[9]), .B0(n2490), .B1(n2504),
.Y(n2489) );
NAND2X1TS U3124 ( .A(Raw_mant_NRM_SWR[42]), .B(n2580), .Y(n2488) );
NOR2X1TS U3125 ( .A(n2591), .B(n2643), .Y(n2492) );
AOI21X1TS U3126 ( .A0(n2470), .A1(Data_array_SWR[40]), .B0(n2658), .Y(n2493)
);
BUFX4TS U3127 ( .A(n2470), .Y(n2723) );
BUFX3TS U3128 ( .A(n2580), .Y(n2574) );
AOI22X1TS U3129 ( .A0(n2723), .A1(Data_array_SWR[12]), .B0(
Raw_mant_NRM_SWR[39]), .B1(n2574), .Y(n2496) );
BUFX4TS U3130 ( .A(n1797), .Y(n2631) );
BUFX3TS U3131 ( .A(n2576), .Y(n2630) );
INVX4TS U3132 ( .A(n2490), .Y(n2660) );
AOI22X1TS U3133 ( .A0(n2728), .A1(n1830), .B0(Raw_mant_NRM_SWR[17]), .B1(
n2580), .Y(n2499) );
AOI22X1TS U3134 ( .A0(n2723), .A1(n1832), .B0(Raw_mant_NRM_SWR[35]), .B1(
n2574), .Y(n2501) );
AOI22X1TS U3135 ( .A0(n2728), .A1(n1834), .B0(Raw_mant_NRM_SWR[26]), .B1(
n2574), .Y(n2503) );
CLKINVX6TS U3136 ( .A(n2490), .Y(n2589) );
AOI22X1TS U3137 ( .A0(n2728), .A1(Data_array_SWR[7]), .B0(n2722), .B1(n2504),
.Y(n2507) );
NAND2X1TS U3138 ( .A(Raw_mant_NRM_SWR[46]), .B(n2724), .Y(n2506) );
AOI22X1TS U3139 ( .A0(n2470), .A1(Data_array_SWR[37]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2580), .Y(n2510) );
AOI22X1TS U3140 ( .A0(n2722), .A1(n2508), .B0(DmP_mant_SHT1_SW[49]), .B1(
n2658), .Y(n2509) );
AOI22X1TS U3141 ( .A0(n2723), .A1(Data_array_SWR[4]), .B0(n2722), .B1(n2511),
.Y(n2513) );
NAND2X1TS U3142 ( .A(Raw_mant_NRM_SWR[49]), .B(n2724), .Y(n2512) );
AOI22X1TS U3143 ( .A0(n2470), .A1(Data_array_SWR[5]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2574), .Y(n2517) );
BUFX3TS U3144 ( .A(n2724), .Y(n2582) );
AOI22X1TS U3145 ( .A0(n2723), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2574), .Y(n2520) );
AOI22X1TS U3146 ( .A0(n2470), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2574), .Y(n2522) );
AOI22X1TS U3147 ( .A0(n2728), .A1(Data_array_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2580), .Y(n2525) );
AOI22X1TS U3148 ( .A0(n2470), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[40]), .B1(n2574), .Y(n2527) );
AOI22X1TS U3149 ( .A0(n2723), .A1(n1828), .B0(Raw_mant_NRM_SWR[33]), .B1(
n2574), .Y(n2530) );
AOI22X1TS U3150 ( .A0(n2728), .A1(n1829), .B0(Raw_mant_NRM_SWR[18]), .B1(
n2580), .Y(n2533) );
AOI22X1TS U3151 ( .A0(Raw_mant_NRM_SWR[53]), .A1(n1797), .B0(n2563), .B1(
DmP_mant_SHT1_SW[0]), .Y(n2537) );
AOI22X1TS U3152 ( .A0(n2723), .A1(Data_array_SWR[1]), .B0(n2722), .B1(n2534),
.Y(n2536) );
NAND2X1TS U3153 ( .A(Raw_mant_NRM_SWR[52]), .B(n2724), .Y(n2535) );
AOI22X1TS U3154 ( .A0(n2470), .A1(n1825), .B0(Raw_mant_NRM_SWR[5]), .B1(
n2580), .Y(n2539) );
AOI22X1TS U3155 ( .A0(n2470), .A1(n1824), .B0(Raw_mant_NRM_SWR[7]), .B1(
n2580), .Y(n2542) );
AOI22X1TS U3156 ( .A0(n2728), .A1(Data_array_SWR[36]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2574), .Y(n2544) );
AOI22X1TS U3157 ( .A0(n2728), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2580), .Y(n2547) );
AOI22X1TS U3158 ( .A0(n2470), .A1(Data_array_SWR[29]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2580), .Y(n2550) );
AOI22X1TS U3159 ( .A0(n2723), .A1(n1836), .B0(Raw_mant_NRM_SWR[29]), .B1(
n2574), .Y(n2553) );
AOI22X1TS U3160 ( .A0(n2723), .A1(n1835), .B0(Raw_mant_NRM_SWR[31]), .B1(
n2574), .Y(n2556) );
AOI22X1TS U3161 ( .A0(n2470), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2580), .Y(n2560) );
AOI22X1TS U3162 ( .A0(n2723), .A1(n1826), .B0(Raw_mant_NRM_SWR[38]), .B1(
n2574), .Y(n2565) );
AOI22X1TS U3163 ( .A0(n2470), .A1(Data_array_SWR[27]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2580), .Y(n2569) );
AOI22X1TS U3164 ( .A0(n2728), .A1(Data_array_SWR[22]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2580), .Y(n2572) );
AOI22X1TS U3165 ( .A0(n2723), .A1(n1823), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2574), .Y(n2578) );
AOI22X1TS U3166 ( .A0(n2470), .A1(Data_array_SWR[34]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2580), .Y(n2584) );
AOI22X1TS U3167 ( .A0(n2728), .A1(Data_array_SWR[25]), .B0(
Raw_mant_NRM_SWR[15]), .B1(n2580), .Y(n2588) );
AOI22X1TS U3168 ( .A0(n2728), .A1(Data_array_SWR[38]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2724), .Y(n2595) );
BUFX4TS U3169 ( .A(n2592), .Y(n2662) );
AOI22X1TS U3170 ( .A0(n2728), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2724), .Y(n2599) );
AOI22X1TS U3171 ( .A0(n2728), .A1(Data_array_SWR[19]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2602) );
AOI22X1TS U3172 ( .A0(n2470), .A1(Data_array_SWR[32]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[43]), .Y(n2604) );
AOI22X1TS U3173 ( .A0(n2470), .A1(Data_array_SWR[30]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[39]), .Y(n2606) );
AOI22X1TS U3174 ( .A0(n2728), .A1(Data_array_SWR[21]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2609) );
AOI22X1TS U3175 ( .A0(n2723), .A1(Data_array_SWR[15]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[19]), .Y(n2611) );
AOI22X1TS U3176 ( .A0(n2470), .A1(Data_array_SWR[28]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2613) );
AOI22X1TS U3177 ( .A0(n2470), .A1(Data_array_SWR[26]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2616) );
AOI22X1TS U3178 ( .A0(n2723), .A1(n1831), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2724), .Y(n2621) );
AOI22X1TS U3179 ( .A0(n2723), .A1(Data_array_SWR[14]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2624) );
AOI22X1TS U3180 ( .A0(n2470), .A1(n1827), .B0(n2658), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2628) );
AOI22X1TS U3181 ( .A0(n2470), .A1(Data_array_SWR[33]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2634) );
AOI22X1TS U3182 ( .A0(n2723), .A1(n1833), .B0(n2658), .B1(
DmP_mant_SHT1_SW[21]), .Y(n2637) );
AOI22X1TS U3183 ( .A0(n2723), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[39]), .B1(n2724), .Y(n2641) );
AOI22X1TS U3184 ( .A0(n2728), .A1(Data_array_SWR[23]), .B0(n2658), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2646) );
AOI22X1TS U3185 ( .A0(n2723), .A1(Data_array_SWR[10]), .B0(
Raw_mant_NRM_SWR[43]), .B1(n2724), .Y(n2650) );
AOI22X1TS U3186 ( .A0(n2728), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2724), .Y(n2655) );
AOI22X1TS U3187 ( .A0(n2470), .A1(Data_array_SWR[35]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n2658), .Y(n2664) );
NAND2X1TS U3188 ( .A(n3109), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J66_123_7955_n11) );
MX2X1TS U3189 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(n2788),
.Y(n1301) );
MX2X1TS U3190 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n2788),
.Y(n1306) );
MX2X1TS U3191 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n2788),
.Y(n1311) );
MX2X1TS U3192 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2788),
.Y(n1316) );
MX2X1TS U3193 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2788),
.Y(n1321) );
MX2X1TS U3194 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2788),
.Y(n1326) );
MX2X1TS U3195 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2788),
.Y(n1331) );
MX2X1TS U3196 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2788),
.Y(n1336) );
MX2X1TS U3197 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2788),
.Y(n1341) );
MX2X1TS U3198 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n2788),
.Y(n1346) );
MX2X1TS U3199 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n2788),
.Y(n1351) );
AO21XLTS U3200 ( .A0(LZD_output_NRM2_EW[5]), .A1(n2787), .B0(n2668), .Y(
n1126) );
NOR2XLTS U3201 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n2682)
);
OAI22X1TS U3202 ( .A0(n2671), .A1(n2670), .B0(n2669), .B1(n3063), .Y(n2676)
);
OAI211XLTS U3203 ( .A0(n3083), .A1(n2674), .B0(n2673), .C0(n2672), .Y(n2675)
);
NOR4BX1TS U3204 ( .AN(n2678), .B(n2677), .C(n2676), .D(n2675), .Y(n2680) );
OAI211XLTS U3205 ( .A0(n2682), .A1(n2681), .B0(n2680), .C0(n2679), .Y(n2683)
);
OAI21X1TS U3206 ( .A0(n2684), .A1(n2683), .B0(n2788), .Y(n2729) );
OAI2BB1X1TS U3207 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n2787), .B0(n2729),
.Y(n1120) );
AO21XLTS U3208 ( .A0(LZD_output_NRM2_EW[3]), .A1(n2787), .B0(n2685), .Y(
n1109) );
OAI2BB1X1TS U3209 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n2787), .B0(n2686),
.Y(n1110) );
AO21XLTS U3210 ( .A0(LZD_output_NRM2_EW[1]), .A1(n2787), .B0(n2687), .Y(
n1115) );
OAI2BB1X1TS U3211 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n2787), .B0(n2688),
.Y(n1123) );
OA22X1TS U3212 ( .A0(n2695), .A1(n2690), .B0(n3236), .B1(
final_result_ieee[52]), .Y(n1588) );
OA22X1TS U3213 ( .A0(n2695), .A1(exp_rslt_NRM2_EW1[1]), .B0(n3236), .B1(
final_result_ieee[53]), .Y(n1587) );
OA22X1TS U3214 ( .A0(n2695), .A1(exp_rslt_NRM2_EW1[2]), .B0(n3236), .B1(
final_result_ieee[54]), .Y(n1586) );
OA22X1TS U3215 ( .A0(n2695), .A1(exp_rslt_NRM2_EW1[3]), .B0(n3236), .B1(
final_result_ieee[55]), .Y(n1585) );
OA22X1TS U3216 ( .A0(n2695), .A1(exp_rslt_NRM2_EW1[4]), .B0(n3236), .B1(
final_result_ieee[56]), .Y(n1584) );
OA22X1TS U3217 ( .A0(n2695), .A1(exp_rslt_NRM2_EW1[5]), .B0(n3236), .B1(
final_result_ieee[57]), .Y(n1583) );
OA22X1TS U3218 ( .A0(n2695), .A1(n2691), .B0(n3236), .B1(
final_result_ieee[58]), .Y(n1582) );
OA22X1TS U3219 ( .A0(n2695), .A1(n2692), .B0(n3236), .B1(
final_result_ieee[59]), .Y(n1581) );
OA22X1TS U3220 ( .A0(n2695), .A1(n2693), .B0(n3236), .B1(
final_result_ieee[60]), .Y(n1580) );
OA22X1TS U3221 ( .A0(n2695), .A1(n2694), .B0(n3236), .B1(
final_result_ieee[61]), .Y(n1579) );
INVX2TS U3222 ( .A(n2699), .Y(n2697) );
AOI22X1TS U3223 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2697), .B1(n3043), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3224 ( .A(n2697), .B(n2696), .Y(n1793) );
NOR2XLTS U3225 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2698) );
AOI32X4TS U3226 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2698), .B1(n3179), .Y(n2702)
);
INVX2TS U3227 ( .A(n2702), .Y(n2701) );
AOI22X1TS U3228 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2699), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3043), .Y(n2703) );
AO22XLTS U3229 ( .A0(n2701), .A1(n2775), .B0(n2702), .B1(n2703), .Y(n1791)
);
AOI22X1TS U3230 ( .A0(n2702), .A1(n2412), .B0(n2759), .B1(n2701), .Y(n1790)
);
AOI22X1TS U3231 ( .A0(n2702), .A1(n2779), .B0(n2760), .B1(n2701), .Y(n1789)
);
INVX4TS U3232 ( .A(n3225), .Y(n2801) );
AOI22X1TS U3233 ( .A0(n2702), .A1(n2814), .B0(n2787), .B1(n2701), .Y(n1786)
);
AOI22X1TS U3234 ( .A0(n2702), .A1(n2787), .B0(n2959), .B1(n2701), .Y(n1785)
);
NAND2X1TS U3235 ( .A(beg_OP), .B(n2703), .Y(n2704) );
BUFX4TS U3236 ( .A(n2705), .Y(n2717) );
BUFX4TS U3237 ( .A(n2717), .Y(n2719) );
INVX4TS U3238 ( .A(n2717), .Y(n2718) );
BUFX4TS U3239 ( .A(n2705), .Y(n2714) );
AO22XLTS U3240 ( .A0(n2714), .A1(Data_X[3]), .B0(n2710), .B1(intDX_EWSW[3]),
.Y(n1781) );
BUFX4TS U3241 ( .A(n2705), .Y(n2711) );
BUFX4TS U3242 ( .A(n2705), .Y(n2715) );
INVX4TS U3243 ( .A(n2719), .Y(n2710) );
AO22XLTS U3244 ( .A0(n2714), .A1(Data_X[8]), .B0(n2710), .B1(intDX_EWSW[8]),
.Y(n1776) );
AO22XLTS U3245 ( .A0(n2714), .A1(Data_X[11]), .B0(n2710), .B1(intDX_EWSW[11]), .Y(n1773) );
AO22XLTS U3246 ( .A0(n2705), .A1(Data_X[12]), .B0(n2710), .B1(intDX_EWSW[12]), .Y(n1772) );
AO22XLTS U3247 ( .A0(n2705), .A1(Data_X[13]), .B0(n2710), .B1(intDX_EWSW[13]), .Y(n1771) );
AO22XLTS U3248 ( .A0(n2705), .A1(Data_X[14]), .B0(n2710), .B1(intDX_EWSW[14]), .Y(n1770) );
AO22XLTS U3249 ( .A0(n2711), .A1(Data_X[15]), .B0(n2710), .B1(intDX_EWSW[15]), .Y(n1769) );
AO22XLTS U3250 ( .A0(n2711), .A1(Data_X[17]), .B0(n2710), .B1(intDX_EWSW[17]), .Y(n1767) );
INVX4TS U3251 ( .A(n2719), .Y(n2712) );
AO22XLTS U3252 ( .A0(n2715), .A1(Data_X[18]), .B0(n2712), .B1(intDX_EWSW[18]), .Y(n1766) );
AO22XLTS U3253 ( .A0(n2711), .A1(Data_X[19]), .B0(n2712), .B1(intDX_EWSW[19]), .Y(n1765) );
AO22XLTS U3254 ( .A0(n2715), .A1(Data_X[20]), .B0(n2712), .B1(intDX_EWSW[20]), .Y(n1764) );
AO22XLTS U3255 ( .A0(n2714), .A1(Data_X[21]), .B0(n2712), .B1(intDX_EWSW[21]), .Y(n1763) );
AO22XLTS U3256 ( .A0(n2711), .A1(Data_X[22]), .B0(n2712), .B1(intDX_EWSW[22]), .Y(n1762) );
AO22XLTS U3257 ( .A0(n2715), .A1(Data_X[23]), .B0(n2712), .B1(intDX_EWSW[23]), .Y(n1761) );
AO22XLTS U3258 ( .A0(n2714), .A1(Data_X[25]), .B0(n2712), .B1(intDX_EWSW[25]), .Y(n1759) );
AO22XLTS U3259 ( .A0(n2719), .A1(Data_X[26]), .B0(n2712), .B1(intDX_EWSW[26]), .Y(n1758) );
AO22XLTS U3260 ( .A0(n2719), .A1(Data_X[27]), .B0(n2712), .B1(intDX_EWSW[27]), .Y(n1757) );
AO22XLTS U3261 ( .A0(n2719), .A1(Data_X[28]), .B0(n2712), .B1(intDX_EWSW[28]), .Y(n1756) );
AO22XLTS U3262 ( .A0(n2719), .A1(Data_X[29]), .B0(n2712), .B1(intDX_EWSW[29]), .Y(n1755) );
AO22XLTS U3263 ( .A0(n2719), .A1(Data_X[30]), .B0(n2712), .B1(intDX_EWSW[30]), .Y(n1754) );
INVX4TS U3264 ( .A(n2717), .Y(n2713) );
AO22XLTS U3265 ( .A0(n2719), .A1(Data_X[31]), .B0(n2713), .B1(intDX_EWSW[31]), .Y(n1753) );
AO22XLTS U3266 ( .A0(n2717), .A1(Data_X[33]), .B0(n2713), .B1(intDX_EWSW[33]), .Y(n1751) );
AO22XLTS U3267 ( .A0(n2717), .A1(Data_X[34]), .B0(n2713), .B1(intDX_EWSW[34]), .Y(n1750) );
AO22XLTS U3268 ( .A0(n2717), .A1(Data_X[35]), .B0(n2713), .B1(intDX_EWSW[35]), .Y(n1749) );
AO22XLTS U3269 ( .A0(n2717), .A1(Data_X[36]), .B0(n2713), .B1(intDX_EWSW[36]), .Y(n1748) );
AO22XLTS U3270 ( .A0(n2705), .A1(Data_X[41]), .B0(n2713), .B1(intDX_EWSW[41]), .Y(n1743) );
AO22XLTS U3271 ( .A0(n2705), .A1(Data_X[42]), .B0(n2713), .B1(intDX_EWSW[42]), .Y(n1742) );
AO22XLTS U3272 ( .A0(n2705), .A1(Data_X[43]), .B0(n2713), .B1(intDX_EWSW[43]), .Y(n1741) );
AO22XLTS U3273 ( .A0(n2705), .A1(Data_X[45]), .B0(n2718), .B1(intDX_EWSW[45]), .Y(n1739) );
AO22XLTS U3274 ( .A0(n2719), .A1(Data_X[46]), .B0(n2718), .B1(intDX_EWSW[46]), .Y(n1738) );
CLKBUFX2TS U3275 ( .A(n2705), .Y(n2708) );
BUFX4TS U3276 ( .A(n2708), .Y(n2709) );
AO22XLTS U3277 ( .A0(n2718), .A1(intDX_EWSW[49]), .B0(n2709), .B1(Data_X[49]), .Y(n1735) );
AO22XLTS U3278 ( .A0(n2717), .A1(Data_X[50]), .B0(n2718), .B1(intDX_EWSW[50]), .Y(n1734) );
AO22XLTS U3279 ( .A0(n2717), .A1(Data_X[51]), .B0(n2718), .B1(intDX_EWSW[51]), .Y(n1733) );
INVX4TS U3280 ( .A(n2717), .Y(n2707) );
AO22XLTS U3281 ( .A0(n2707), .A1(intDX_EWSW[53]), .B0(n2709), .B1(Data_X[53]), .Y(n1731) );
AO22XLTS U3282 ( .A0(n2710), .A1(intDX_EWSW[54]), .B0(n2709), .B1(Data_X[54]), .Y(n1730) );
INVX4TS U3283 ( .A(n2717), .Y(n2716) );
AO22XLTS U3284 ( .A0(n2716), .A1(intDX_EWSW[55]), .B0(n2709), .B1(Data_X[55]), .Y(n1729) );
INVX4TS U3285 ( .A(n2717), .Y(n2720) );
AO22XLTS U3286 ( .A0(n2720), .A1(intDX_EWSW[56]), .B0(n2709), .B1(Data_X[56]), .Y(n1728) );
AO22XLTS U3287 ( .A0(n2717), .A1(Data_X[57]), .B0(n2718), .B1(intDX_EWSW[57]), .Y(n1727) );
AO22XLTS U3288 ( .A0(n2718), .A1(intDX_EWSW[58]), .B0(n2709), .B1(Data_X[58]), .Y(n1726) );
AO22XLTS U3289 ( .A0(n2707), .A1(intDX_EWSW[59]), .B0(n2709), .B1(Data_X[59]), .Y(n1725) );
AO22XLTS U3290 ( .A0(n2718), .A1(intDX_EWSW[60]), .B0(n2709), .B1(Data_X[60]), .Y(n1724) );
AO22XLTS U3291 ( .A0(n2716), .A1(intDX_EWSW[61]), .B0(n2709), .B1(Data_X[61]), .Y(n1723) );
AO22XLTS U3292 ( .A0(n2713), .A1(intDX_EWSW[62]), .B0(n2709), .B1(Data_X[62]), .Y(n1722) );
AO22XLTS U3293 ( .A0(n2717), .A1(add_subt), .B0(n2718), .B1(intAS), .Y(n1720) );
AO22XLTS U3294 ( .A0(n2716), .A1(intDY_EWSW[0]), .B0(n2709), .B1(Data_Y[0]),
.Y(n1718) );
AO22XLTS U3295 ( .A0(n2720), .A1(intDY_EWSW[1]), .B0(n2709), .B1(Data_Y[1]),
.Y(n1717) );
AO22XLTS U3296 ( .A0(n2720), .A1(intDY_EWSW[2]), .B0(n2709), .B1(Data_Y[2]),
.Y(n1716) );
AO22XLTS U3297 ( .A0(n2720), .A1(intDY_EWSW[3]), .B0(n2709), .B1(Data_Y[3]),
.Y(n1715) );
AO22XLTS U3298 ( .A0(n2720), .A1(intDY_EWSW[4]), .B0(n2714), .B1(Data_Y[4]),
.Y(n1714) );
AO22XLTS U3299 ( .A0(n2720), .A1(intDY_EWSW[5]), .B0(n2709), .B1(Data_Y[5]),
.Y(n1713) );
AO22XLTS U3300 ( .A0(n2720), .A1(intDY_EWSW[6]), .B0(n2711), .B1(Data_Y[6]),
.Y(n1712) );
AO22XLTS U3301 ( .A0(n2720), .A1(intDY_EWSW[7]), .B0(n2705), .B1(Data_Y[7]),
.Y(n1711) );
AO22XLTS U3302 ( .A0(n2720), .A1(intDY_EWSW[8]), .B0(n2709), .B1(Data_Y[8]),
.Y(n1710) );
AO22XLTS U3303 ( .A0(n2720), .A1(intDY_EWSW[9]), .B0(n2715), .B1(Data_Y[9]),
.Y(n1709) );
AO22XLTS U3304 ( .A0(n2716), .A1(intDY_EWSW[10]), .B0(n2705), .B1(Data_Y[10]), .Y(n1708) );
AO22XLTS U3305 ( .A0(n2707), .A1(intDY_EWSW[11]), .B0(n2711), .B1(Data_Y[11]), .Y(n1707) );
AO22XLTS U3306 ( .A0(n2710), .A1(intDY_EWSW[12]), .B0(n2711), .B1(Data_Y[12]), .Y(n1706) );
AO22XLTS U3307 ( .A0(n2720), .A1(intDY_EWSW[13]), .B0(n2705), .B1(Data_Y[13]), .Y(n1705) );
AO22XLTS U3308 ( .A0(n2713), .A1(intDY_EWSW[14]), .B0(n2711), .B1(Data_Y[14]), .Y(n1704) );
AO22XLTS U3309 ( .A0(n2716), .A1(intDY_EWSW[15]), .B0(n2711), .B1(Data_Y[15]), .Y(n1703) );
AO22XLTS U3310 ( .A0(n2707), .A1(intDY_EWSW[16]), .B0(n2709), .B1(Data_Y[16]), .Y(n1702) );
AO22XLTS U3311 ( .A0(n2707), .A1(intDY_EWSW[17]), .B0(n2711), .B1(Data_Y[17]), .Y(n1701) );
AO22XLTS U3312 ( .A0(n2713), .A1(intDY_EWSW[18]), .B0(n2711), .B1(Data_Y[18]), .Y(n1700) );
AO22XLTS U3313 ( .A0(n2716), .A1(intDY_EWSW[19]), .B0(n2715), .B1(Data_Y[19]), .Y(n1699) );
AO22XLTS U3314 ( .A0(n2707), .A1(intDY_EWSW[20]), .B0(n2711), .B1(Data_Y[20]), .Y(n1698) );
AO22XLTS U3315 ( .A0(n2718), .A1(intDY_EWSW[21]), .B0(n2711), .B1(Data_Y[21]), .Y(n1697) );
AO22XLTS U3316 ( .A0(n2707), .A1(intDY_EWSW[22]), .B0(n2715), .B1(Data_Y[22]), .Y(n1696) );
AO22XLTS U3317 ( .A0(n2707), .A1(intDY_EWSW[23]), .B0(n2715), .B1(Data_Y[23]), .Y(n1695) );
AO22XLTS U3318 ( .A0(n2707), .A1(intDY_EWSW[24]), .B0(n2715), .B1(Data_Y[24]), .Y(n1694) );
AO22XLTS U3319 ( .A0(n2707), .A1(intDY_EWSW[25]), .B0(n2715), .B1(Data_Y[25]), .Y(n1693) );
AO22XLTS U3320 ( .A0(n2707), .A1(intDY_EWSW[26]), .B0(n2711), .B1(Data_Y[26]), .Y(n1692) );
AO22XLTS U3321 ( .A0(n2707), .A1(intDY_EWSW[27]), .B0(n2709), .B1(Data_Y[27]), .Y(n1691) );
AO22XLTS U3322 ( .A0(n2707), .A1(intDY_EWSW[28]), .B0(n2715), .B1(Data_Y[28]), .Y(n1690) );
AO22XLTS U3323 ( .A0(n2707), .A1(intDY_EWSW[29]), .B0(n2715), .B1(Data_Y[29]), .Y(n1689) );
AO22XLTS U3324 ( .A0(n2707), .A1(intDY_EWSW[30]), .B0(n2708), .B1(Data_Y[30]), .Y(n1688) );
AO22XLTS U3325 ( .A0(n2707), .A1(intDY_EWSW[31]), .B0(n2709), .B1(Data_Y[31]), .Y(n1687) );
AO22XLTS U3326 ( .A0(n2712), .A1(intDY_EWSW[32]), .B0(n2708), .B1(Data_Y[32]), .Y(n1686) );
AO22XLTS U3327 ( .A0(n2707), .A1(intDY_EWSW[33]), .B0(n2708), .B1(Data_Y[33]), .Y(n1685) );
AO22XLTS U3328 ( .A0(n2712), .A1(intDY_EWSW[34]), .B0(n2708), .B1(Data_Y[34]), .Y(n1684) );
AO22XLTS U3329 ( .A0(n2707), .A1(intDY_EWSW[35]), .B0(n2711), .B1(Data_Y[35]), .Y(n1683) );
AO22XLTS U3330 ( .A0(n2710), .A1(intDY_EWSW[36]), .B0(n2708), .B1(Data_Y[36]), .Y(n1682) );
AO22XLTS U3331 ( .A0(n2720), .A1(intDY_EWSW[37]), .B0(n2708), .B1(Data_Y[37]), .Y(n1681) );
AO22XLTS U3332 ( .A0(n2713), .A1(intDY_EWSW[38]), .B0(n2709), .B1(Data_Y[38]), .Y(n1680) );
AO22XLTS U3333 ( .A0(n2712), .A1(intDY_EWSW[39]), .B0(n2715), .B1(Data_Y[39]), .Y(n1679) );
AO22XLTS U3334 ( .A0(n2710), .A1(intDY_EWSW[40]), .B0(n2711), .B1(Data_Y[40]), .Y(n1678) );
AO22XLTS U3335 ( .A0(n2720), .A1(intDY_EWSW[41]), .B0(n2711), .B1(Data_Y[41]), .Y(n1677) );
AO22XLTS U3336 ( .A0(n2704), .A1(intDY_EWSW[42]), .B0(n2711), .B1(Data_Y[42]), .Y(n1676) );
AO22XLTS U3337 ( .A0(n2718), .A1(intDY_EWSW[43]), .B0(n2715), .B1(Data_Y[43]), .Y(n1675) );
AO22XLTS U3338 ( .A0(n2716), .A1(intDY_EWSW[44]), .B0(n2714), .B1(Data_Y[44]), .Y(n1674) );
AO22XLTS U3339 ( .A0(n2712), .A1(intDY_EWSW[45]), .B0(n2714), .B1(Data_Y[45]), .Y(n1673) );
AO22XLTS U3340 ( .A0(n2716), .A1(intDY_EWSW[46]), .B0(n2714), .B1(Data_Y[46]), .Y(n1672) );
AO22XLTS U3341 ( .A0(n2713), .A1(intDY_EWSW[47]), .B0(n2714), .B1(Data_Y[47]), .Y(n1671) );
AO22XLTS U3342 ( .A0(n2716), .A1(intDY_EWSW[48]), .B0(n2714), .B1(Data_Y[48]), .Y(n1670) );
AO22XLTS U3343 ( .A0(n2716), .A1(intDY_EWSW[49]), .B0(n2714), .B1(Data_Y[49]), .Y(n1669) );
AO22XLTS U3344 ( .A0(n2716), .A1(intDY_EWSW[50]), .B0(n2714), .B1(Data_Y[50]), .Y(n1668) );
AO22XLTS U3345 ( .A0(n2716), .A1(intDY_EWSW[51]), .B0(n2714), .B1(Data_Y[51]), .Y(n1667) );
AO22XLTS U3346 ( .A0(n2716), .A1(intDY_EWSW[52]), .B0(n2714), .B1(Data_Y[52]), .Y(n1666) );
AO22XLTS U3347 ( .A0(n2716), .A1(intDY_EWSW[53]), .B0(n2714), .B1(Data_Y[53]), .Y(n1665) );
AO22XLTS U3348 ( .A0(n2716), .A1(intDY_EWSW[54]), .B0(n2714), .B1(Data_Y[54]), .Y(n1664) );
AO22XLTS U3349 ( .A0(n2716), .A1(intDY_EWSW[55]), .B0(n2715), .B1(Data_Y[55]), .Y(n1663) );
AO22XLTS U3350 ( .A0(n2716), .A1(intDY_EWSW[56]), .B0(n2715), .B1(Data_Y[56]), .Y(n1662) );
AO22XLTS U3351 ( .A0(n2716), .A1(intDY_EWSW[57]), .B0(n2715), .B1(Data_Y[57]), .Y(n1661) );
AO22XLTS U3352 ( .A0(n2719), .A1(Data_Y[61]), .B0(n2720), .B1(intDY_EWSW[61]), .Y(n1657) );
AOI22X1TS U3353 ( .A0(n2723), .A1(Data_array_SWR[0]), .B0(n2722), .B1(n2721),
.Y(n2726) );
AOI22X1TS U3354 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n1797), .B0(
Raw_mant_NRM_SWR[53]), .B1(n2724), .Y(n2725) );
NAND2X1TS U3355 ( .A(n2726), .B(n2725), .Y(n1600) );
AOI22X1TS U3356 ( .A0(n2728), .A1(shift_value_SHT2_EWR[4]), .B0(n2727), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n2730) );
NAND2X1TS U3357 ( .A(n2730), .B(n2729), .Y(n1597) );
NAND2X1TS U3358 ( .A(DmP_EXP_EWSW[52]), .B(n3216), .Y(n2735) );
OAI21XLTS U3359 ( .A0(DmP_EXP_EWSW[52]), .A1(n3216), .B0(n2735), .Y(n2731)
);
NAND2X1TS U3360 ( .A(DmP_EXP_EWSW[53]), .B(n3064), .Y(n2734) );
OAI21XLTS U3361 ( .A0(DmP_EXP_EWSW[53]), .A1(n3064), .B0(n2734), .Y(n2732)
);
XNOR2X1TS U3362 ( .A(n2735), .B(n2732), .Y(n2733) );
AO22XLTS U3363 ( .A0(n1822), .A1(n2733), .B0(n2758), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1593) );
AOI22X1TS U3364 ( .A0(DMP_EXP_EWSW[53]), .A1(n3020), .B0(n2735), .B1(n2734),
.Y(n2738) );
NOR2X1TS U3365 ( .A(n3021), .B(DMP_EXP_EWSW[54]), .Y(n2739) );
AOI21X1TS U3366 ( .A0(DMP_EXP_EWSW[54]), .A1(n3021), .B0(n2739), .Y(n2736)
);
XNOR2X1TS U3367 ( .A(n2738), .B(n2736), .Y(n2737) );
AO22XLTS U3368 ( .A0(n1822), .A1(n2737), .B0(n2758), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1592) );
OAI22X1TS U3369 ( .A0(n2739), .A1(n2738), .B0(DmP_EXP_EWSW[54]), .B1(n3066),
.Y(n2742) );
NAND2X1TS U3370 ( .A(DmP_EXP_EWSW[55]), .B(n3067), .Y(n2743) );
XNOR2X1TS U3371 ( .A(n2742), .B(n2740), .Y(n2741) );
AO22XLTS U3372 ( .A0(n1822), .A1(n2741), .B0(n2758), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1591) );
AOI22X1TS U3373 ( .A0(DMP_EXP_EWSW[55]), .A1(n3023), .B0(n2743), .B1(n2742),
.Y(n2746) );
NOR2X1TS U3374 ( .A(n3015), .B(DMP_EXP_EWSW[56]), .Y(n2747) );
AOI21X1TS U3375 ( .A0(DMP_EXP_EWSW[56]), .A1(n3015), .B0(n2747), .Y(n2744)
);
XNOR2X1TS U3376 ( .A(n2746), .B(n2744), .Y(n2745) );
AO22XLTS U3377 ( .A0(n1822), .A1(n2745), .B0(n2758), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1590) );
OAI22X1TS U3378 ( .A0(n2747), .A1(n2746), .B0(DmP_EXP_EWSW[56]), .B1(n3070),
.Y(n2749) );
XNOR2X1TS U3379 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n2748) );
XOR2XLTS U3380 ( .A(n2749), .B(n2748), .Y(n2750) );
AO22XLTS U3381 ( .A0(n1822), .A1(n2750), .B0(n2758), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1589) );
OAI222X1TS U3382 ( .A0(n2774), .A1(n3022), .B0(n3070), .B1(n2775), .C0(n1818), .C1(n2776), .Y(n1521) );
OAI21XLTS U3383 ( .A0(n2752), .A1(intDX_EWSW[63]), .B0(n2775), .Y(n2751) );
AOI21X1TS U3384 ( .A0(n2752), .A1(intDX_EWSW[63]), .B0(n2751), .Y(n2754) );
AO21XLTS U3385 ( .A0(OP_FLAG_EXP), .A1(n2753), .B0(n2754), .Y(n1514) );
AO22XLTS U3386 ( .A0(n1822), .A1(DMP_EXP_EWSW[0]), .B0(n2779), .B1(
DMP_SHT1_EWSW[0]), .Y(n1511) );
AO22XLTS U3387 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n3226), .B1(
DMP_SHT2_EWSW[0]), .Y(n1510) );
AO22XLTS U3388 ( .A0(n1822), .A1(DMP_EXP_EWSW[1]), .B0(n2779), .B1(
DMP_SHT1_EWSW[1]), .Y(n1508) );
AO22XLTS U3389 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n2760), .B1(
DMP_SHT2_EWSW[1]), .Y(n1507) );
BUFX4TS U3390 ( .A(n2991), .Y(n3008) );
AO22XLTS U3391 ( .A0(n3002), .A1(DMP_SHT2_EWSW[1]), .B0(n2761), .B1(
DMP_SFG[1]), .Y(n1506) );
AO22XLTS U3392 ( .A0(n1822), .A1(DMP_EXP_EWSW[2]), .B0(n2779), .B1(
DMP_SHT1_EWSW[2]), .Y(n1505) );
AO22XLTS U3393 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n2760), .B1(
DMP_SHT2_EWSW[2]), .Y(n1504) );
AO22XLTS U3394 ( .A0(n3008), .A1(DMP_SHT2_EWSW[2]), .B0(n2786), .B1(
DMP_SFG[2]), .Y(n1503) );
AO22XLTS U3395 ( .A0(n1822), .A1(DMP_EXP_EWSW[3]), .B0(n2759), .B1(
DMP_SHT1_EWSW[3]), .Y(n1502) );
AO22XLTS U3396 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n2760), .B1(
DMP_SHT2_EWSW[3]), .Y(n1501) );
AO22XLTS U3397 ( .A0(n3011), .A1(DMP_SHT2_EWSW[3]), .B0(n3006), .B1(
DMP_SFG[3]), .Y(n1500) );
AO22XLTS U3398 ( .A0(n1822), .A1(DMP_EXP_EWSW[4]), .B0(n2758), .B1(
DMP_SHT1_EWSW[4]), .Y(n1499) );
AO22XLTS U3399 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n2760), .B1(
DMP_SHT2_EWSW[4]), .Y(n1498) );
AO22XLTS U3400 ( .A0(n1822), .A1(DMP_EXP_EWSW[5]), .B0(n2758), .B1(
DMP_SHT1_EWSW[5]), .Y(n1496) );
AO22XLTS U3401 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n2760), .B1(
DMP_SHT2_EWSW[5]), .Y(n1495) );
AO22XLTS U3402 ( .A0(n2991), .A1(DMP_SHT2_EWSW[5]), .B0(n2786), .B1(
DMP_SFG[5]), .Y(n1494) );
AO22XLTS U3403 ( .A0(n1863), .A1(DMP_EXP_EWSW[6]), .B0(n2758), .B1(
DMP_SHT1_EWSW[6]), .Y(n1493) );
AO22XLTS U3404 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n2760), .B1(
DMP_SHT2_EWSW[6]), .Y(n1492) );
AO22XLTS U3405 ( .A0(n2771), .A1(DMP_EXP_EWSW[7]), .B0(n2759), .B1(
DMP_SHT1_EWSW[7]), .Y(n1490) );
AO22XLTS U3406 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n2760), .B1(
DMP_SHT2_EWSW[7]), .Y(n1489) );
AO22XLTS U3407 ( .A0(n3002), .A1(DMP_SHT2_EWSW[7]), .B0(n3012), .B1(
DMP_SFG[7]), .Y(n1488) );
AO22XLTS U3408 ( .A0(n2768), .A1(DMP_EXP_EWSW[8]), .B0(n2759), .B1(
DMP_SHT1_EWSW[8]), .Y(n1487) );
AO22XLTS U3409 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n2760), .B1(
DMP_SHT2_EWSW[8]), .Y(n1486) );
AO22XLTS U3410 ( .A0(n2783), .A1(DMP_EXP_EWSW[9]), .B0(n2759), .B1(
DMP_SHT1_EWSW[9]), .Y(n1484) );
AO22XLTS U3411 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n2760), .B1(
DMP_SHT2_EWSW[9]), .Y(n1483) );
INVX4TS U3412 ( .A(n2997), .Y(n2763) );
AO22XLTS U3413 ( .A0(n3012), .A1(DMP_SFG[9]), .B0(n3011), .B1(
DMP_SHT2_EWSW[9]), .Y(n1482) );
AO22XLTS U3414 ( .A0(n2780), .A1(DMP_EXP_EWSW[10]), .B0(n2759), .B1(
DMP_SHT1_EWSW[10]), .Y(n1481) );
AO22XLTS U3415 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n2760), .B1(
DMP_SHT2_EWSW[10]), .Y(n1480) );
BUFX3TS U3416 ( .A(n2991), .Y(n3002) );
AO22XLTS U3417 ( .A0(n2786), .A1(DMP_SFG[10]), .B0(n3008), .B1(
DMP_SHT2_EWSW[10]), .Y(n1479) );
AO22XLTS U3418 ( .A0(n2783), .A1(DMP_EXP_EWSW[11]), .B0(n2759), .B1(
DMP_SHT1_EWSW[11]), .Y(n1478) );
AO22XLTS U3419 ( .A0(n3024), .A1(DMP_SHT1_EWSW[11]), .B0(n2760), .B1(
DMP_SHT2_EWSW[11]), .Y(n1477) );
AO22XLTS U3420 ( .A0(n3012), .A1(DMP_SFG[11]), .B0(n3011), .B1(
DMP_SHT2_EWSW[11]), .Y(n1476) );
AO22XLTS U3421 ( .A0(n2780), .A1(DMP_EXP_EWSW[12]), .B0(n2759), .B1(
DMP_SHT1_EWSW[12]), .Y(n1475) );
AO22XLTS U3422 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n2760), .B1(
DMP_SHT2_EWSW[12]), .Y(n1474) );
INVX4TS U3423 ( .A(n2994), .Y(n2761) );
AO22XLTS U3424 ( .A0(n2763), .A1(DMP_SFG[12]), .B0(n3002), .B1(
DMP_SHT2_EWSW[12]), .Y(n1473) );
AO22XLTS U3425 ( .A0(n1863), .A1(DMP_EXP_EWSW[13]), .B0(n2758), .B1(
DMP_SHT1_EWSW[13]), .Y(n1472) );
AO22XLTS U3426 ( .A0(n3024), .A1(DMP_SHT1_EWSW[13]), .B0(n3226), .B1(
DMP_SHT2_EWSW[13]), .Y(n1471) );
AO22XLTS U3427 ( .A0(n2763), .A1(DMP_SFG[13]), .B0(n3008), .B1(
DMP_SHT2_EWSW[13]), .Y(n1470) );
AO22XLTS U3428 ( .A0(n2783), .A1(DMP_EXP_EWSW[14]), .B0(n2759), .B1(
DMP_SHT1_EWSW[14]), .Y(n1469) );
AO22XLTS U3429 ( .A0(n3024), .A1(DMP_SHT1_EWSW[14]), .B0(n3226), .B1(
DMP_SHT2_EWSW[14]), .Y(n1468) );
AO22XLTS U3430 ( .A0(n2761), .A1(DMP_SFG[14]), .B0(n3011), .B1(
DMP_SHT2_EWSW[14]), .Y(n1467) );
AO22XLTS U3431 ( .A0(n1863), .A1(DMP_EXP_EWSW[15]), .B0(n2758), .B1(
DMP_SHT1_EWSW[15]), .Y(n1466) );
AO22XLTS U3432 ( .A0(n3024), .A1(DMP_SHT1_EWSW[15]), .B0(n3226), .B1(
DMP_SHT2_EWSW[15]), .Y(n1465) );
AO22XLTS U3433 ( .A0(n2786), .A1(DMP_SFG[15]), .B0(n2991), .B1(
DMP_SHT2_EWSW[15]), .Y(n1464) );
AO22XLTS U3434 ( .A0(n1863), .A1(DMP_EXP_EWSW[16]), .B0(n2758), .B1(
DMP_SHT1_EWSW[16]), .Y(n1463) );
AO22XLTS U3435 ( .A0(n3024), .A1(DMP_SHT1_EWSW[16]), .B0(n3226), .B1(
DMP_SHT2_EWSW[16]), .Y(n1462) );
AO22XLTS U3436 ( .A0(n3012), .A1(DMP_SFG[16]), .B0(n3011), .B1(
DMP_SHT2_EWSW[16]), .Y(n1461) );
AO22XLTS U3437 ( .A0(n2767), .A1(DMP_EXP_EWSW[17]), .B0(n2758), .B1(
DMP_SHT1_EWSW[17]), .Y(n1460) );
AO22XLTS U3438 ( .A0(n3024), .A1(DMP_SHT1_EWSW[17]), .B0(n3226), .B1(
DMP_SHT2_EWSW[17]), .Y(n1459) );
AO22XLTS U3439 ( .A0(n2763), .A1(DMP_SFG[17]), .B0(n2991), .B1(
DMP_SHT2_EWSW[17]), .Y(n1458) );
INVX4TS U3440 ( .A(n2779), .Y(n2771) );
AO22XLTS U3441 ( .A0(n2771), .A1(DMP_EXP_EWSW[18]), .B0(n2758), .B1(
DMP_SHT1_EWSW[18]), .Y(n1457) );
AO22XLTS U3442 ( .A0(n3024), .A1(DMP_SHT1_EWSW[18]), .B0(n3226), .B1(
DMP_SHT2_EWSW[18]), .Y(n1456) );
AO22XLTS U3443 ( .A0(n2786), .A1(DMP_SFG[18]), .B0(n3002), .B1(
DMP_SHT2_EWSW[18]), .Y(n1455) );
INVX4TS U3444 ( .A(n2779), .Y(n2768) );
AO22XLTS U3445 ( .A0(n2768), .A1(DMP_EXP_EWSW[19]), .B0(n2758), .B1(
DMP_SHT1_EWSW[19]), .Y(n1454) );
AO22XLTS U3446 ( .A0(n3024), .A1(DMP_SHT1_EWSW[19]), .B0(n3226), .B1(
DMP_SHT2_EWSW[19]), .Y(n1453) );
AO22XLTS U3447 ( .A0(n2761), .A1(DMP_SFG[19]), .B0(n3008), .B1(
DMP_SHT2_EWSW[19]), .Y(n1452) );
INVX4TS U3448 ( .A(n2779), .Y(n2767) );
AO22XLTS U3449 ( .A0(n2767), .A1(DMP_EXP_EWSW[20]), .B0(n2758), .B1(
DMP_SHT1_EWSW[20]), .Y(n1451) );
AO22XLTS U3450 ( .A0(n3024), .A1(DMP_SHT1_EWSW[20]), .B0(n3226), .B1(
DMP_SHT2_EWSW[20]), .Y(n1450) );
AO22XLTS U3451 ( .A0(n3012), .A1(DMP_SFG[20]), .B0(n3011), .B1(
DMP_SHT2_EWSW[20]), .Y(n1449) );
AO22XLTS U3452 ( .A0(n2771), .A1(DMP_EXP_EWSW[21]), .B0(n2758), .B1(
DMP_SHT1_EWSW[21]), .Y(n1448) );
AO22XLTS U3453 ( .A0(n3024), .A1(DMP_SHT1_EWSW[21]), .B0(n3226), .B1(
DMP_SHT2_EWSW[21]), .Y(n1447) );
AO22XLTS U3454 ( .A0(n3012), .A1(DMP_SFG[21]), .B0(n3002), .B1(
DMP_SHT2_EWSW[21]), .Y(n1446) );
AO22XLTS U3455 ( .A0(n2768), .A1(DMP_EXP_EWSW[22]), .B0(n2758), .B1(
DMP_SHT1_EWSW[22]), .Y(n1445) );
INVX4TS U3456 ( .A(n3226), .Y(n2762) );
AO22XLTS U3457 ( .A0(n2762), .A1(DMP_SHT1_EWSW[22]), .B0(n3226), .B1(
DMP_SHT2_EWSW[22]), .Y(n1444) );
AO22XLTS U3458 ( .A0(n2763), .A1(DMP_SFG[22]), .B0(n2991), .B1(
DMP_SHT2_EWSW[22]), .Y(n1443) );
AO22XLTS U3459 ( .A0(n2767), .A1(DMP_EXP_EWSW[23]), .B0(n2758), .B1(
DMP_SHT1_EWSW[23]), .Y(n1442) );
AO22XLTS U3460 ( .A0(n2762), .A1(DMP_SHT1_EWSW[23]), .B0(n3226), .B1(
DMP_SHT2_EWSW[23]), .Y(n1441) );
AO22XLTS U3461 ( .A0(n2763), .A1(DMP_SFG[23]), .B0(n3008), .B1(
DMP_SHT2_EWSW[23]), .Y(n1440) );
AO22XLTS U3462 ( .A0(n2771), .A1(DMP_EXP_EWSW[24]), .B0(n2758), .B1(
DMP_SHT1_EWSW[24]), .Y(n1439) );
AO22XLTS U3463 ( .A0(n2762), .A1(DMP_SHT1_EWSW[24]), .B0(n2760), .B1(
DMP_SHT2_EWSW[24]), .Y(n1438) );
AO22XLTS U3464 ( .A0(n3012), .A1(DMP_SFG[24]), .B0(n3011), .B1(
DMP_SHT2_EWSW[24]), .Y(n1437) );
AO22XLTS U3465 ( .A0(n2768), .A1(DMP_EXP_EWSW[25]), .B0(n2758), .B1(
DMP_SHT1_EWSW[25]), .Y(n1436) );
BUFX4TS U3466 ( .A(n3226), .Y(n2766) );
AO22XLTS U3467 ( .A0(n2762), .A1(DMP_SHT1_EWSW[25]), .B0(n2766), .B1(
DMP_SHT2_EWSW[25]), .Y(n1435) );
AO22XLTS U3468 ( .A0(n2761), .A1(DMP_SFG[25]), .B0(n3008), .B1(
DMP_SHT2_EWSW[25]), .Y(n1434) );
AO22XLTS U3469 ( .A0(n2767), .A1(DMP_EXP_EWSW[26]), .B0(n2759), .B1(
DMP_SHT1_EWSW[26]), .Y(n1433) );
BUFX3TS U3470 ( .A(n3226), .Y(n2784) );
AO22XLTS U3471 ( .A0(n2762), .A1(DMP_SHT1_EWSW[26]), .B0(n2784), .B1(
DMP_SHT2_EWSW[26]), .Y(n1432) );
AO22XLTS U3472 ( .A0(n2761), .A1(DMP_SFG[26]), .B0(n2991), .B1(
DMP_SHT2_EWSW[26]), .Y(n1431) );
AO22XLTS U3473 ( .A0(n2771), .A1(DMP_EXP_EWSW[27]), .B0(n2759), .B1(
DMP_SHT1_EWSW[27]), .Y(n1430) );
AO22XLTS U3474 ( .A0(n2762), .A1(DMP_SHT1_EWSW[27]), .B0(n2760), .B1(
DMP_SHT2_EWSW[27]), .Y(n1429) );
AO22XLTS U3475 ( .A0(n3006), .A1(DMP_SFG[27]), .B0(n3011), .B1(
DMP_SHT2_EWSW[27]), .Y(n1428) );
AO22XLTS U3476 ( .A0(n2768), .A1(DMP_EXP_EWSW[28]), .B0(n2759), .B1(
DMP_SHT1_EWSW[28]), .Y(n1427) );
AO22XLTS U3477 ( .A0(n2762), .A1(DMP_SHT1_EWSW[28]), .B0(n2766), .B1(
DMP_SHT2_EWSW[28]), .Y(n1426) );
AO22XLTS U3478 ( .A0(n2786), .A1(DMP_SFG[28]), .B0(n3008), .B1(
DMP_SHT2_EWSW[28]), .Y(n1425) );
AO22XLTS U3479 ( .A0(n2767), .A1(DMP_EXP_EWSW[29]), .B0(n2759), .B1(
DMP_SHT1_EWSW[29]), .Y(n1424) );
AO22XLTS U3480 ( .A0(n2762), .A1(DMP_SHT1_EWSW[29]), .B0(n2784), .B1(
DMP_SHT2_EWSW[29]), .Y(n1423) );
AO22XLTS U3481 ( .A0(n2786), .A1(DMP_SFG[29]), .B0(n2991), .B1(
DMP_SHT2_EWSW[29]), .Y(n1422) );
INVX4TS U3482 ( .A(n2779), .Y(n2764) );
AO22XLTS U3483 ( .A0(n2764), .A1(DMP_EXP_EWSW[30]), .B0(n2759), .B1(
DMP_SHT1_EWSW[30]), .Y(n1421) );
AO22XLTS U3484 ( .A0(n2762), .A1(DMP_SHT1_EWSW[30]), .B0(n2760), .B1(
DMP_SHT2_EWSW[30]), .Y(n1420) );
AO22XLTS U3485 ( .A0(n2992), .A1(DMP_SFG[30]), .B0(n2997), .B1(
DMP_SHT2_EWSW[30]), .Y(n1419) );
AO22XLTS U3486 ( .A0(n2771), .A1(DMP_EXP_EWSW[31]), .B0(n2759), .B1(
DMP_SHT1_EWSW[31]), .Y(n1418) );
AO22XLTS U3487 ( .A0(n2762), .A1(DMP_SHT1_EWSW[31]), .B0(n2766), .B1(
DMP_SHT2_EWSW[31]), .Y(n1417) );
AO22XLTS U3488 ( .A0(n3012), .A1(DMP_SFG[31]), .B0(n3011), .B1(
DMP_SHT2_EWSW[31]), .Y(n1416) );
AO22XLTS U3489 ( .A0(n2764), .A1(DMP_EXP_EWSW[32]), .B0(n2759), .B1(
DMP_SHT1_EWSW[32]), .Y(n1415) );
AO22XLTS U3490 ( .A0(n2762), .A1(DMP_SHT1_EWSW[32]), .B0(n2760), .B1(
DMP_SHT2_EWSW[32]), .Y(n1414) );
AO22XLTS U3491 ( .A0(n2763), .A1(DMP_SFG[32]), .B0(n2991), .B1(
DMP_SHT2_EWSW[32]), .Y(n1413) );
AO22XLTS U3492 ( .A0(n2768), .A1(DMP_EXP_EWSW[33]), .B0(n2759), .B1(
DMP_SHT1_EWSW[33]), .Y(n1412) );
AO22XLTS U3493 ( .A0(n2762), .A1(DMP_SHT1_EWSW[33]), .B0(n2766), .B1(
DMP_SHT2_EWSW[33]), .Y(n1411) );
AO22XLTS U3494 ( .A0(n2761), .A1(DMP_SFG[33]), .B0(n3002), .B1(
DMP_SHT2_EWSW[33]), .Y(n1410) );
AO22XLTS U3495 ( .A0(n2764), .A1(DMP_EXP_EWSW[34]), .B0(n2759), .B1(
DMP_SHT1_EWSW[34]), .Y(n1409) );
AO22XLTS U3496 ( .A0(n2762), .A1(DMP_SHT1_EWSW[34]), .B0(n2784), .B1(
DMP_SHT2_EWSW[34]), .Y(n1408) );
AO22XLTS U3497 ( .A0(n3009), .A1(DMP_SFG[34]), .B0(n3008), .B1(
DMP_SHT2_EWSW[34]), .Y(n1407) );
AO22XLTS U3498 ( .A0(n2767), .A1(DMP_EXP_EWSW[35]), .B0(n2759), .B1(
DMP_SHT1_EWSW[35]), .Y(n1406) );
AO22XLTS U3499 ( .A0(n2762), .A1(DMP_SHT1_EWSW[35]), .B0(n2760), .B1(
DMP_SHT2_EWSW[35]), .Y(n1405) );
AO22XLTS U3500 ( .A0(n2763), .A1(DMP_SFG[35]), .B0(n3011), .B1(
DMP_SHT2_EWSW[35]), .Y(n1404) );
AO22XLTS U3501 ( .A0(n2764), .A1(DMP_EXP_EWSW[36]), .B0(n2759), .B1(
DMP_SHT1_EWSW[36]), .Y(n1403) );
AO22XLTS U3502 ( .A0(n2762), .A1(DMP_SHT1_EWSW[36]), .B0(n2766), .B1(
DMP_SHT2_EWSW[36]), .Y(n1402) );
AO22XLTS U3503 ( .A0(n2763), .A1(DMP_SFG[36]), .B0(n2756), .B1(
DMP_SHT2_EWSW[36]), .Y(n1401) );
BUFX3TS U3504 ( .A(n3228), .Y(n2769) );
AO22XLTS U3505 ( .A0(n2764), .A1(DMP_EXP_EWSW[37]), .B0(n2769), .B1(
DMP_SHT1_EWSW[37]), .Y(n1400) );
AO22XLTS U3506 ( .A0(n2762), .A1(DMP_SHT1_EWSW[37]), .B0(n2760), .B1(
DMP_SHT2_EWSW[37]), .Y(n1399) );
AO22XLTS U3507 ( .A0(n2786), .A1(DMP_SFG[37]), .B0(n2994), .B1(
DMP_SHT2_EWSW[37]), .Y(n1398) );
AO22XLTS U3508 ( .A0(n2764), .A1(DMP_EXP_EWSW[38]), .B0(n2769), .B1(
DMP_SHT1_EWSW[38]), .Y(n1397) );
AO22XLTS U3509 ( .A0(n2762), .A1(DMP_SHT1_EWSW[38]), .B0(n2760), .B1(
DMP_SHT2_EWSW[38]), .Y(n1396) );
AO22XLTS U3510 ( .A0(n2761), .A1(DMP_SFG[38]), .B0(n2997), .B1(
DMP_SHT2_EWSW[38]), .Y(n1395) );
INVX4TS U3511 ( .A(n2769), .Y(n2780) );
AO22XLTS U3512 ( .A0(n2780), .A1(DMP_EXP_EWSW[39]), .B0(n2769), .B1(
DMP_SHT1_EWSW[39]), .Y(n1394) );
AO22XLTS U3513 ( .A0(n2765), .A1(DMP_SHT1_EWSW[39]), .B0(n2766), .B1(
DMP_SHT2_EWSW[39]), .Y(n1393) );
AO22XLTS U3514 ( .A0(n3012), .A1(DMP_SFG[39]), .B0(n2994), .B1(
DMP_SHT2_EWSW[39]), .Y(n1392) );
INVX4TS U3515 ( .A(n2759), .Y(n2783) );
AO22XLTS U3516 ( .A0(n2783), .A1(DMP_EXP_EWSW[40]), .B0(n2769), .B1(
DMP_SHT1_EWSW[40]), .Y(n1391) );
AO22XLTS U3517 ( .A0(n2765), .A1(DMP_SHT1_EWSW[40]), .B0(n2766), .B1(
DMP_SHT2_EWSW[40]), .Y(n1390) );
AO22XLTS U3518 ( .A0(n2761), .A1(DMP_SFG[40]), .B0(n2994), .B1(
DMP_SHT2_EWSW[40]), .Y(n1389) );
AO22XLTS U3519 ( .A0(n2780), .A1(DMP_EXP_EWSW[41]), .B0(n2769), .B1(
DMP_SHT1_EWSW[41]), .Y(n1388) );
AO22XLTS U3520 ( .A0(n2765), .A1(DMP_SHT1_EWSW[41]), .B0(n2760), .B1(
DMP_SHT2_EWSW[41]), .Y(n1387) );
AO22XLTS U3521 ( .A0(n3009), .A1(DMP_SFG[41]), .B0(n2997), .B1(
DMP_SHT2_EWSW[41]), .Y(n1386) );
AO22XLTS U3522 ( .A0(n2764), .A1(DMP_EXP_EWSW[42]), .B0(n2769), .B1(
DMP_SHT1_EWSW[42]), .Y(n1385) );
AO22XLTS U3523 ( .A0(n2765), .A1(DMP_SHT1_EWSW[42]), .B0(n2766), .B1(
DMP_SHT2_EWSW[42]), .Y(n1384) );
AO22XLTS U3524 ( .A0(n2992), .A1(DMP_SFG[42]), .B0(n2997), .B1(
DMP_SHT2_EWSW[42]), .Y(n1383) );
AO22XLTS U3525 ( .A0(n2764), .A1(DMP_EXP_EWSW[43]), .B0(n2769), .B1(
DMP_SHT1_EWSW[43]), .Y(n1382) );
AO22XLTS U3526 ( .A0(n2765), .A1(DMP_SHT1_EWSW[43]), .B0(n2784), .B1(
DMP_SHT2_EWSW[43]), .Y(n1381) );
AO22XLTS U3527 ( .A0(n2761), .A1(DMP_SFG[43]), .B0(n2756), .B1(
DMP_SHT2_EWSW[43]), .Y(n1380) );
AO22XLTS U3528 ( .A0(n2764), .A1(DMP_EXP_EWSW[44]), .B0(n2769), .B1(
DMP_SHT1_EWSW[44]), .Y(n1379) );
AO22XLTS U3529 ( .A0(n2765), .A1(DMP_SHT1_EWSW[44]), .B0(n2784), .B1(
DMP_SHT2_EWSW[44]), .Y(n1378) );
AO22XLTS U3530 ( .A0(n2786), .A1(DMP_SFG[44]), .B0(n2756), .B1(
DMP_SHT2_EWSW[44]), .Y(n1377) );
AO22XLTS U3531 ( .A0(n2764), .A1(DMP_EXP_EWSW[45]), .B0(n2769), .B1(
DMP_SHT1_EWSW[45]), .Y(n1376) );
AO22XLTS U3532 ( .A0(n2765), .A1(DMP_SHT1_EWSW[45]), .B0(n2766), .B1(
DMP_SHT2_EWSW[45]), .Y(n1375) );
AO22XLTS U3533 ( .A0(n2786), .A1(DMP_SFG[45]), .B0(n2994), .B1(
DMP_SHT2_EWSW[45]), .Y(n1374) );
AO22XLTS U3534 ( .A0(n2764), .A1(DMP_EXP_EWSW[46]), .B0(n2769), .B1(
DMP_SHT1_EWSW[46]), .Y(n1373) );
AO22XLTS U3535 ( .A0(n2765), .A1(DMP_SHT1_EWSW[46]), .B0(n2766), .B1(
DMP_SHT2_EWSW[46]), .Y(n1372) );
AO22XLTS U3536 ( .A0(n3012), .A1(DMP_SFG[46]), .B0(n2997), .B1(
DMP_SHT2_EWSW[46]), .Y(n1371) );
AO22XLTS U3537 ( .A0(n2764), .A1(DMP_EXP_EWSW[47]), .B0(n2769), .B1(
DMP_SHT1_EWSW[47]), .Y(n1370) );
AO22XLTS U3538 ( .A0(n2765), .A1(DMP_SHT1_EWSW[47]), .B0(n2766), .B1(
DMP_SHT2_EWSW[47]), .Y(n1369) );
AO22XLTS U3539 ( .A0(n2763), .A1(DMP_SFG[47]), .B0(n2994), .B1(
DMP_SHT2_EWSW[47]), .Y(n1368) );
BUFX4TS U3540 ( .A(n2779), .Y(n2782) );
AO22XLTS U3541 ( .A0(n2764), .A1(DMP_EXP_EWSW[48]), .B0(n2782), .B1(
DMP_SHT1_EWSW[48]), .Y(n1367) );
AO22XLTS U3542 ( .A0(n2765), .A1(DMP_SHT1_EWSW[48]), .B0(n2766), .B1(
DMP_SHT2_EWSW[48]), .Y(n1366) );
AO22XLTS U3543 ( .A0(n2763), .A1(DMP_SFG[48]), .B0(n2756), .B1(
DMP_SHT2_EWSW[48]), .Y(n1365) );
AO22XLTS U3544 ( .A0(n2764), .A1(DMP_EXP_EWSW[49]), .B0(n2782), .B1(
DMP_SHT1_EWSW[49]), .Y(n1364) );
AO22XLTS U3545 ( .A0(n2765), .A1(DMP_SHT1_EWSW[49]), .B0(n2766), .B1(
DMP_SHT2_EWSW[49]), .Y(n1363) );
AO22XLTS U3546 ( .A0(n2761), .A1(DMP_SFG[49]), .B0(n2991), .B1(
DMP_SHT2_EWSW[49]), .Y(n1362) );
AO22XLTS U3547 ( .A0(n2764), .A1(DMP_EXP_EWSW[50]), .B0(n2782), .B1(
DMP_SHT1_EWSW[50]), .Y(n1361) );
AO22XLTS U3548 ( .A0(n2762), .A1(DMP_SHT1_EWSW[50]), .B0(n2766), .B1(
DMP_SHT2_EWSW[50]), .Y(n1360) );
AO22XLTS U3549 ( .A0(n3012), .A1(DMP_SFG[50]), .B0(n3002), .B1(
DMP_SHT2_EWSW[50]), .Y(n1359) );
AO22XLTS U3550 ( .A0(n2764), .A1(DMP_EXP_EWSW[51]), .B0(n2782), .B1(
DMP_SHT1_EWSW[51]), .Y(n1358) );
AO22XLTS U3551 ( .A0(n2765), .A1(DMP_SHT1_EWSW[51]), .B0(n2766), .B1(
DMP_SHT2_EWSW[51]), .Y(n1357) );
AO22XLTS U3552 ( .A0(n3006), .A1(DMP_SFG[51]), .B0(n3008), .B1(
DMP_SHT2_EWSW[51]), .Y(n1356) );
AO22XLTS U3553 ( .A0(n2764), .A1(DMP_EXP_EWSW[52]), .B0(n2782), .B1(
DMP_SHT1_EWSW[52]), .Y(n1355) );
AO22XLTS U3554 ( .A0(n2765), .A1(DMP_SHT1_EWSW[52]), .B0(n2766), .B1(
DMP_SHT2_EWSW[52]), .Y(n1354) );
AO22XLTS U3555 ( .A0(n3008), .A1(DMP_SHT2_EWSW[52]), .B0(n2761), .B1(
DMP_SFG[52]), .Y(n1353) );
AO22XLTS U3556 ( .A0(n2801), .A1(DMP_SFG[52]), .B0(n2796), .B1(
DMP_exp_NRM_EW[0]), .Y(n1352) );
AO22XLTS U3557 ( .A0(n2764), .A1(DMP_EXP_EWSW[53]), .B0(n2782), .B1(
DMP_SHT1_EWSW[53]), .Y(n1350) );
AO22XLTS U3558 ( .A0(n2765), .A1(DMP_SHT1_EWSW[53]), .B0(n2766), .B1(
DMP_SHT2_EWSW[53]), .Y(n1349) );
AO22XLTS U3559 ( .A0(n3011), .A1(DMP_SHT2_EWSW[53]), .B0(n3006), .B1(
DMP_SFG[53]), .Y(n1348) );
AO22XLTS U3560 ( .A0(n2802), .A1(DMP_SFG[53]), .B0(n2796), .B1(
DMP_exp_NRM_EW[1]), .Y(n1347) );
AO22XLTS U3561 ( .A0(n2767), .A1(DMP_EXP_EWSW[54]), .B0(n2782), .B1(
DMP_SHT1_EWSW[54]), .Y(n1345) );
AO22XLTS U3562 ( .A0(n2785), .A1(DMP_SHT1_EWSW[54]), .B0(n2766), .B1(
DMP_SHT2_EWSW[54]), .Y(n1344) );
AO22XLTS U3563 ( .A0(n2991), .A1(DMP_SHT2_EWSW[54]), .B0(n2786), .B1(
DMP_SFG[54]), .Y(n1343) );
AO22XLTS U3564 ( .A0(n2802), .A1(DMP_SFG[54]), .B0(n2796), .B1(
DMP_exp_NRM_EW[2]), .Y(n1342) );
AO22XLTS U3565 ( .A0(n2767), .A1(DMP_EXP_EWSW[55]), .B0(n2782), .B1(
DMP_SHT1_EWSW[55]), .Y(n1340) );
AO22XLTS U3566 ( .A0(n2785), .A1(DMP_SHT1_EWSW[55]), .B0(n2766), .B1(
DMP_SHT2_EWSW[55]), .Y(n1339) );
AO22XLTS U3567 ( .A0(n3002), .A1(DMP_SHT2_EWSW[55]), .B0(n3012), .B1(
DMP_SFG[55]), .Y(n1338) );
AO22XLTS U3568 ( .A0(n2802), .A1(DMP_SFG[55]), .B0(n2796), .B1(
DMP_exp_NRM_EW[3]), .Y(n1337) );
AO22XLTS U3569 ( .A0(n2767), .A1(DMP_EXP_EWSW[56]), .B0(n2782), .B1(
DMP_SHT1_EWSW[56]), .Y(n1335) );
AO22XLTS U3570 ( .A0(n2785), .A1(DMP_SHT1_EWSW[56]), .B0(n2766), .B1(
DMP_SHT2_EWSW[56]), .Y(n1334) );
AO22XLTS U3571 ( .A0(n2802), .A1(DMP_SFG[56]), .B0(n2796), .B1(
DMP_exp_NRM_EW[4]), .Y(n1332) );
AO22XLTS U3572 ( .A0(n2767), .A1(DMP_EXP_EWSW[57]), .B0(n2782), .B1(
DMP_SHT1_EWSW[57]), .Y(n1330) );
AO22XLTS U3573 ( .A0(n2785), .A1(DMP_SHT1_EWSW[57]), .B0(n2784), .B1(
DMP_SHT2_EWSW[57]), .Y(n1329) );
AO22XLTS U3574 ( .A0(n3008), .A1(DMP_SHT2_EWSW[57]), .B0(n2763), .B1(
DMP_SFG[57]), .Y(n1328) );
AO22XLTS U3575 ( .A0(n2802), .A1(DMP_SFG[57]), .B0(n2796), .B1(
DMP_exp_NRM_EW[5]), .Y(n1327) );
AO22XLTS U3576 ( .A0(n2767), .A1(DMP_EXP_EWSW[58]), .B0(n3228), .B1(
DMP_SHT1_EWSW[58]), .Y(n1325) );
AO22XLTS U3577 ( .A0(n2785), .A1(DMP_SHT1_EWSW[58]), .B0(n2784), .B1(
DMP_SHT2_EWSW[58]), .Y(n1324) );
AO22XLTS U3578 ( .A0(n2802), .A1(DMP_SFG[58]), .B0(n2796), .B1(
DMP_exp_NRM_EW[6]), .Y(n1322) );
AO22XLTS U3579 ( .A0(n2767), .A1(DMP_EXP_EWSW[59]), .B0(n3228), .B1(
DMP_SHT1_EWSW[59]), .Y(n1320) );
AO22XLTS U3580 ( .A0(n2785), .A1(DMP_SHT1_EWSW[59]), .B0(n2784), .B1(
DMP_SHT2_EWSW[59]), .Y(n1319) );
AO22XLTS U3581 ( .A0(n3008), .A1(DMP_SHT2_EWSW[59]), .B0(n2761), .B1(
DMP_SFG[59]), .Y(n1318) );
AO22XLTS U3582 ( .A0(n2802), .A1(DMP_SFG[59]), .B0(n2796), .B1(
DMP_exp_NRM_EW[7]), .Y(n1317) );
AO22XLTS U3583 ( .A0(n2767), .A1(DMP_EXP_EWSW[60]), .B0(n3228), .B1(
DMP_SHT1_EWSW[60]), .Y(n1315) );
AO22XLTS U3584 ( .A0(n2785), .A1(DMP_SHT1_EWSW[60]), .B0(n2784), .B1(
DMP_SHT2_EWSW[60]), .Y(n1314) );
AO22XLTS U3585 ( .A0(n2802), .A1(DMP_SFG[60]), .B0(n2796), .B1(
DMP_exp_NRM_EW[8]), .Y(n1312) );
AO22XLTS U3586 ( .A0(n2767), .A1(DMP_EXP_EWSW[61]), .B0(n3228), .B1(
DMP_SHT1_EWSW[61]), .Y(n1310) );
AO22XLTS U3587 ( .A0(n2785), .A1(DMP_SHT1_EWSW[61]), .B0(n2784), .B1(
DMP_SHT2_EWSW[61]), .Y(n1309) );
AO22XLTS U3588 ( .A0(n3011), .A1(DMP_SHT2_EWSW[61]), .B0(n2786), .B1(
DMP_SFG[61]), .Y(n1308) );
AO22XLTS U3589 ( .A0(n2802), .A1(DMP_SFG[61]), .B0(n2796), .B1(
DMP_exp_NRM_EW[9]), .Y(n1307) );
AO22XLTS U3590 ( .A0(n2767), .A1(DMP_EXP_EWSW[62]), .B0(n3228), .B1(
DMP_SHT1_EWSW[62]), .Y(n1305) );
AO22XLTS U3591 ( .A0(n2785), .A1(DMP_SHT1_EWSW[62]), .B0(n2784), .B1(
DMP_SHT2_EWSW[62]), .Y(n1304) );
AO22XLTS U3592 ( .A0(n2802), .A1(DMP_SFG[62]), .B0(n3225), .B1(
DMP_exp_NRM_EW[10]), .Y(n1302) );
BUFX3TS U3593 ( .A(n3228), .Y(n2772) );
BUFX4TS U3594 ( .A(n2772), .Y(n2781) );
AO22XLTS U3595 ( .A0(n2780), .A1(DmP_EXP_EWSW[50]), .B0(n2779), .B1(
DmP_mant_SHT1_SW[50]), .Y(n1199) );
AO22XLTS U3596 ( .A0(n2780), .A1(DmP_EXP_EWSW[51]), .B0(n2779), .B1(
DmP_mant_SHT1_SW[51]), .Y(n1197) );
OAI222X1TS U3597 ( .A0(n2776), .A1(n3223), .B0(n3020), .B1(n2775), .C0(n3014), .C1(n2774), .Y(n1195) );
OAI222X1TS U3598 ( .A0(n2773), .A1(n3069), .B0(n3021), .B1(n2775), .C0(n1820), .C1(n2774), .Y(n1194) );
OAI222X1TS U3599 ( .A0(n2773), .A1(n3224), .B0(n3023), .B1(n2775), .C0(n3013), .C1(n2774), .Y(n1193) );
OAI222X1TS U3600 ( .A0(n2776), .A1(n3022), .B0(n3015), .B1(n2775), .C0(n1818), .C1(n2774), .Y(n1192) );
NAND2X1TS U3601 ( .A(n3236), .B(n2790), .Y(n2777) );
OAI2BB1X1TS U3602 ( .A0N(underflow_flag), .A1N(n2929), .B0(n2777), .Y(n1190)
);
OA21XLTS U3603 ( .A0(n3236), .A1(overflow_flag), .B0(n2778), .Y(n1189) );
AO22XLTS U3604 ( .A0(n2780), .A1(ZERO_FLAG_EXP), .B0(n2779), .B1(
ZERO_FLAG_SHT1), .Y(n1188) );
AO22XLTS U3605 ( .A0(n2785), .A1(ZERO_FLAG_SHT1), .B0(n2784), .B1(
ZERO_FLAG_SHT2), .Y(n1187) );
AO22XLTS U3606 ( .A0(n3011), .A1(ZERO_FLAG_SHT2), .B0(n3012), .B1(
ZERO_FLAG_SFG), .Y(n1186) );
AO22XLTS U3607 ( .A0(n2802), .A1(ZERO_FLAG_SFG), .B0(n2796), .B1(
ZERO_FLAG_NRM), .Y(n1185) );
AO22XLTS U3608 ( .A0(n2788), .A1(ZERO_FLAG_NRM), .B0(n2787), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1184) );
AO22XLTS U3609 ( .A0(n2783), .A1(OP_FLAG_EXP), .B0(n2781), .B1(OP_FLAG_SHT1),
.Y(n1182) );
AO22XLTS U3610 ( .A0(n2785), .A1(OP_FLAG_SHT1), .B0(n2784), .B1(OP_FLAG_SHT2), .Y(n1181) );
AO22XLTS U3611 ( .A0(n2761), .A1(OP_FLAG_SFG), .B0(n2991), .B1(OP_FLAG_SHT2),
.Y(n1180) );
AO22XLTS U3612 ( .A0(n2783), .A1(SIGN_FLAG_EXP), .B0(n2782), .B1(
SIGN_FLAG_SHT1), .Y(n1179) );
AO22XLTS U3613 ( .A0(n2785), .A1(SIGN_FLAG_SHT1), .B0(n2784), .B1(
SIGN_FLAG_SHT2), .Y(n1178) );
AO22XLTS U3614 ( .A0(n2991), .A1(SIGN_FLAG_SHT2), .B0(n2763), .B1(
SIGN_FLAG_SFG), .Y(n1177) );
AO22XLTS U3615 ( .A0(n2802), .A1(SIGN_FLAG_SFG), .B0(n3225), .B1(
SIGN_FLAG_NRM), .Y(n1176) );
AO22XLTS U3616 ( .A0(n2788), .A1(SIGN_FLAG_NRM), .B0(n2787), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1175) );
OAI211XLTS U3617 ( .A0(n2790), .A1(SIGN_FLAG_SHT1SHT2), .B0(n3236), .C0(
n2789), .Y(n2791) );
OAI2BB1X1TS U3618 ( .A0N(final_result_ieee[63]), .A1N(n2901), .B0(n2791),
.Y(n1174) );
XNOR2X1TS U3619 ( .A(n2794), .B(n2793), .Y(n2795) );
AOI22X1TS U3620 ( .A0(n3016), .A1(n2795), .B0(n3215), .B1(n2796), .Y(n1173)
);
CLKINVX6TS U3621 ( .A(n2798), .Y(n2799) );
INVX4TS U3622 ( .A(n2798), .Y(n2803) );
AOI22X1TS U3623 ( .A0(n1839), .A1(intadd_72_SUM_0_), .B0(n3018), .B1(n2796),
.Y(n1172) );
AOI22X1TS U3624 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n2797), .B0(OP_FLAG_SFG),
.B1(n1853), .Y(intadd_72_B_1_) );
AOI22X1TS U3625 ( .A0(n1839), .A1(intadd_72_SUM_1_), .B0(n3151), .B1(n2796),
.Y(n1171) );
AOI22X1TS U3626 ( .A0(DmP_mant_SFG_SWR[13]), .A1(n2797), .B0(n2798), .B1(
n1854), .Y(intadd_72_B_2_) );
AOI22X1TS U3627 ( .A0(n1839), .A1(intadd_72_SUM_2_), .B0(n3096), .B1(n2796),
.Y(n1170) );
AOI22X1TS U3628 ( .A0(DmP_mant_SFG_SWR[14]), .A1(n2797), .B0(n2798), .B1(
n1855), .Y(intadd_72_B_3_) );
AOI22X1TS U3629 ( .A0(n1839), .A1(intadd_72_SUM_3_), .B0(n3220), .B1(n2796),
.Y(n1169) );
AOI22X1TS U3630 ( .A0(DmP_mant_SFG_SWR[15]), .A1(n2797), .B0(n2798), .B1(
n1856), .Y(intadd_72_B_4_) );
BUFX4TS U3631 ( .A(n3225), .Y(n2861) );
AOI22X1TS U3632 ( .A0(n1839), .A1(intadd_72_SUM_4_), .B0(n3094), .B1(n2861),
.Y(n1168) );
AOI22X1TS U3633 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n2797), .B0(n2798), .B1(
n1857), .Y(intadd_72_B_5_) );
AOI22X1TS U3634 ( .A0(n1839), .A1(intadd_72_SUM_5_), .B0(n3065), .B1(n2861),
.Y(n1167) );
AOI22X1TS U3635 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n2797), .B0(n2798), .B1(
n1858), .Y(intadd_72_B_6_) );
AOI2BB2XLTS U3636 ( .B0(n2800), .B1(intadd_72_SUM_6_), .A0N(
Raw_mant_NRM_SWR[17]), .A1N(n2801), .Y(n1166) );
AOI22X1TS U3637 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n2797), .B0(n2798), .B1(
n1859), .Y(intadd_72_B_7_) );
AOI22X1TS U3638 ( .A0(n2801), .A1(intadd_72_SUM_7_), .B0(n3153), .B1(n2861),
.Y(n1165) );
AOI22X1TS U3639 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n2797), .B0(n2798), .B1(
n1860), .Y(intadd_72_B_8_) );
AOI22X1TS U3640 ( .A0(n2802), .A1(intadd_72_SUM_8_), .B0(n3139), .B1(n2861),
.Y(n1164) );
AOI22X1TS U3641 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n2797), .B0(n2798), .B1(
n1861), .Y(intadd_72_B_9_) );
AOI22X1TS U3642 ( .A0(n3016), .A1(intadd_72_SUM_9_), .B0(n3038), .B1(n2861),
.Y(n1163) );
AOI22X1TS U3643 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n2797), .B0(n2798), .B1(
n1840), .Y(intadd_72_B_10_) );
AOI22X1TS U3644 ( .A0(n2802), .A1(intadd_72_SUM_10_), .B0(n3091), .B1(n2861),
.Y(n1162) );
AOI22X1TS U3645 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n2797), .B0(n2798), .B1(
n1841), .Y(intadd_72_B_11_) );
AOI2BB2XLTS U3646 ( .B0(n2800), .B1(intadd_72_SUM_11_), .A0N(
Raw_mant_NRM_SWR[22]), .A1N(n2801), .Y(n1161) );
AOI2BB2XLTS U3647 ( .B0(n2800), .B1(intadd_72_SUM_12_), .A0N(
Raw_mant_NRM_SWR[23]), .A1N(n2801), .Y(n1160) );
AOI2BB2XLTS U3648 ( .B0(DmP_mant_SFG_SWR[24]), .B1(n2799), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[24]), .Y(intadd_72_B_13_) );
AOI22X1TS U3649 ( .A0(n2862), .A1(intadd_72_SUM_13_), .B0(n3086), .B1(n2861),
.Y(n1159) );
AOI2BB2XLTS U3650 ( .B0(DmP_mant_SFG_SWR[25]), .B1(n2799), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[25]), .Y(intadd_72_B_14_) );
AOI2BB2XLTS U3651 ( .B0(n2800), .B1(intadd_72_SUM_14_), .A0N(
Raw_mant_NRM_SWR[25]), .A1N(n2801), .Y(n1158) );
AOI2BB2XLTS U3652 ( .B0(DmP_mant_SFG_SWR[26]), .B1(n3281), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[26]), .Y(intadd_72_B_15_) );
AOI22X1TS U3653 ( .A0(n2862), .A1(intadd_72_SUM_15_), .B0(n3083), .B1(n2861),
.Y(n1157) );
AOI2BB2XLTS U3654 ( .B0(DmP_mant_SFG_SWR[27]), .B1(n2799), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[27]), .Y(intadd_72_B_16_) );
AOI22X1TS U3655 ( .A0(n2862), .A1(intadd_72_SUM_16_), .B0(n3142), .B1(n2861),
.Y(n1156) );
AOI2BB2XLTS U3656 ( .B0(DmP_mant_SFG_SWR[28]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[28]), .Y(intadd_72_B_17_) );
AOI22X1TS U3657 ( .A0(n2862), .A1(intadd_72_SUM_17_), .B0(n3035), .B1(n3225),
.Y(n1155) );
AOI2BB2XLTS U3658 ( .B0(DmP_mant_SFG_SWR[29]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[29]), .Y(intadd_72_B_18_) );
AOI2BB2XLTS U3659 ( .B0(n2800), .B1(intadd_72_SUM_18_), .A0N(
Raw_mant_NRM_SWR[29]), .A1N(n2801), .Y(n1154) );
AOI2BB2XLTS U3660 ( .B0(DmP_mant_SFG_SWR[30]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[30]), .Y(intadd_72_B_19_) );
AOI22X1TS U3661 ( .A0(n2862), .A1(intadd_72_SUM_19_), .B0(n3029), .B1(n2861),
.Y(n1153) );
AOI2BB2XLTS U3662 ( .B0(DmP_mant_SFG_SWR[31]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[31]), .Y(intadd_72_B_20_) );
AOI22X1TS U3663 ( .A0(n2802), .A1(intadd_72_SUM_20_), .B0(n3037), .B1(n2861),
.Y(n1152) );
AOI22X1TS U3664 ( .A0(DmP_mant_SFG_SWR[32]), .A1(n2797), .B0(n2798), .B1(
n1842), .Y(intadd_72_B_21_) );
AOI22X1TS U3665 ( .A0(n2862), .A1(intadd_72_SUM_21_), .B0(n3019), .B1(n2861),
.Y(n1151) );
AOI22X1TS U3666 ( .A0(DmP_mant_SFG_SWR[33]), .A1(n3281), .B0(n2798), .B1(
n1843), .Y(intadd_72_B_22_) );
AOI22X1TS U3667 ( .A0(n2862), .A1(intadd_72_SUM_22_), .B0(n3028), .B1(n2861),
.Y(n1150) );
AOI22X1TS U3668 ( .A0(DmP_mant_SFG_SWR[34]), .A1(n3281), .B0(n2798), .B1(
n1844), .Y(intadd_72_B_23_) );
AOI22X1TS U3669 ( .A0(n2862), .A1(intadd_72_SUM_23_), .B0(n3063), .B1(n2861),
.Y(n1149) );
AOI22X1TS U3670 ( .A0(DmP_mant_SFG_SWR[35]), .A1(n3281), .B0(n2798), .B1(
n1845), .Y(intadd_72_B_24_) );
AOI22X1TS U3671 ( .A0(n2862), .A1(intadd_72_SUM_24_), .B0(n3041), .B1(n2861),
.Y(n1148) );
AOI22X1TS U3672 ( .A0(DmP_mant_SFG_SWR[36]), .A1(n3281), .B0(n2798), .B1(
n1846), .Y(intadd_72_B_25_) );
AOI22X1TS U3673 ( .A0(n2862), .A1(intadd_72_SUM_25_), .B0(n3027), .B1(n2861),
.Y(n1147) );
AOI22X1TS U3674 ( .A0(DmP_mant_SFG_SWR[37]), .A1(n3281), .B0(n2798), .B1(
n1847), .Y(intadd_72_B_26_) );
AOI2BB2XLTS U3675 ( .B0(n2800), .B1(intadd_72_SUM_26_), .A0N(
Raw_mant_NRM_SWR[37]), .A1N(n2801), .Y(n1146) );
AOI22X1TS U3676 ( .A0(DmP_mant_SFG_SWR[38]), .A1(n2797), .B0(n2798), .B1(
n1848), .Y(intadd_72_B_27_) );
AOI2BB2XLTS U3677 ( .B0(n2800), .B1(intadd_72_SUM_27_), .A0N(
Raw_mant_NRM_SWR[38]), .A1N(n2801), .Y(n1145) );
AOI22X1TS U3678 ( .A0(DmP_mant_SFG_SWR[39]), .A1(n3281), .B0(n2798), .B1(
n1849), .Y(intadd_72_B_28_) );
AOI22X1TS U3679 ( .A0(n2862), .A1(intadd_72_SUM_28_), .B0(n3026), .B1(n2861),
.Y(n1144) );
AOI22X1TS U3680 ( .A0(DmP_mant_SFG_SWR[40]), .A1(n3281), .B0(OP_FLAG_SFG),
.B1(n1850), .Y(intadd_72_B_29_) );
AOI22X1TS U3681 ( .A0(n2862), .A1(intadd_72_SUM_29_), .B0(n3017), .B1(n3225),
.Y(n1143) );
AOI22X1TS U3682 ( .A0(DmP_mant_SFG_SWR[41]), .A1(n3281), .B0(OP_FLAG_SFG),
.B1(n1851), .Y(intadd_72_B_30_) );
AOI2BB2XLTS U3683 ( .B0(n2800), .B1(intadd_72_SUM_30_), .A0N(
Raw_mant_NRM_SWR[41]), .A1N(n2801), .Y(n1142) );
AOI22X1TS U3684 ( .A0(DmP_mant_SFG_SWR[42]), .A1(n3281), .B0(OP_FLAG_SFG),
.B1(n1852), .Y(intadd_72_B_31_) );
AOI22X1TS U3685 ( .A0(n3016), .A1(intadd_72_SUM_31_), .B0(n3124), .B1(n2814),
.Y(n1141) );
AOI2BB2XLTS U3686 ( .B0(DmP_mant_SFG_SWR[43]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[43]), .Y(intadd_72_B_32_) );
AOI22X1TS U3687 ( .A0(n3016), .A1(intadd_72_SUM_32_), .B0(n3073), .B1(n2814),
.Y(n1140) );
AOI2BB2XLTS U3688 ( .B0(DmP_mant_SFG_SWR[44]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[44]), .Y(intadd_72_B_33_) );
AOI2BB2XLTS U3689 ( .B0(n2800), .B1(intadd_72_SUM_33_), .A0N(
Raw_mant_NRM_SWR[44]), .A1N(n2801), .Y(n1139) );
AOI2BB2XLTS U3690 ( .B0(DmP_mant_SFG_SWR[45]), .B1(n3281), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[45]), .Y(intadd_72_B_34_) );
AOI2BB2XLTS U3691 ( .B0(DmP_mant_SFG_SWR[46]), .B1(n2799), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[46]), .Y(intadd_72_B_35_) );
AOI22X1TS U3692 ( .A0(n3016), .A1(intadd_72_SUM_35_), .B0(n3122), .B1(n2814),
.Y(n1137) );
AOI2BB2XLTS U3693 ( .B0(DmP_mant_SFG_SWR[47]), .B1(n3281), .A0N(n2799),
.A1N(DmP_mant_SFG_SWR[47]), .Y(intadd_72_B_36_) );
AOI22X1TS U3694 ( .A0(n3016), .A1(intadd_72_SUM_36_), .B0(n3072), .B1(n2814),
.Y(n1136) );
AOI2BB2XLTS U3695 ( .B0(DmP_mant_SFG_SWR[48]), .B1(n2799), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[48]), .Y(intadd_72_B_37_) );
AOI2BB2XLTS U3696 ( .B0(DmP_mant_SFG_SWR[49]), .B1(n3281), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[49]), .Y(intadd_72_B_38_) );
AOI22X1TS U3697 ( .A0(n3016), .A1(intadd_72_SUM_38_), .B0(n3071), .B1(n2814),
.Y(n1134) );
AOI2BB2XLTS U3698 ( .B0(DmP_mant_SFG_SWR[50]), .B1(n2803), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[50]), .Y(intadd_72_B_39_) );
AOI22X1TS U3699 ( .A0(n2801), .A1(intadd_72_SUM_39_), .B0(n3025), .B1(n2814),
.Y(n1133) );
AOI2BB2XLTS U3700 ( .B0(DmP_mant_SFG_SWR[51]), .B1(n2803), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[51]), .Y(intadd_72_B_40_) );
AOI2BB2XLTS U3701 ( .B0(DmP_mant_SFG_SWR[52]), .B1(n3281), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[52]), .Y(intadd_72_B_41_) );
AOI2BB2XLTS U3702 ( .B0(DmP_mant_SFG_SWR[53]), .B1(n2803), .A0N(n2803),
.A1N(DmP_mant_SFG_SWR[53]), .Y(intadd_72_B_42_) );
AOI22X1TS U3703 ( .A0(n2801), .A1(intadd_72_SUM_42_), .B0(n3042), .B1(n2814),
.Y(n1130) );
AO22XLTS U3704 ( .A0(n2786), .A1(DmP_mant_SFG_SWR[2]), .B0(n3011), .B1(n2804), .Y(n1119) );
AOI22X1TS U3705 ( .A0(n1839), .A1(DMP_SFG[0]), .B0(Raw_mant_NRM_SWR[2]),
.B1(n2814), .Y(n2805) );
OAI221XLTS U3706 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n2865), .B0(n3229), .B1(
n2864), .C0(n2805), .Y(n1118) );
AO22XLTS U3707 ( .A0(n3012), .A1(DmP_mant_SFG_SWR[5]), .B0(n2991), .B1(n2806), .Y(n1117) );
AOI22X1TS U3708 ( .A0(n1839), .A1(DMP_SFG[3]), .B0(Raw_mant_NRM_SWR[5]),
.B1(n2814), .Y(n2807) );
OAI221XLTS U3709 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n2865), .B0(n3230), .B1(
n2864), .C0(n2807), .Y(n1116) );
AO22XLTS U3710 ( .A0(n2763), .A1(DmP_mant_SFG_SWR[3]), .B0(n3008), .B1(n2808), .Y(n1114) );
AOI22X1TS U3711 ( .A0(n1839), .A1(DMP_SFG[1]), .B0(Raw_mant_NRM_SWR[3]),
.B1(n2814), .Y(n2809) );
OAI221XLTS U3712 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n2865), .B0(n3231), .B1(
n2864), .C0(n2809), .Y(n1113) );
AO22XLTS U3713 ( .A0(n2761), .A1(DmP_mant_SFG_SWR[4]), .B0(n2997), .B1(n2810), .Y(n1112) );
AOI22X1TS U3714 ( .A0(n1839), .A1(DMP_SFG[2]), .B0(Raw_mant_NRM_SWR[4]),
.B1(n2814), .Y(n2811) );
OAI221XLTS U3715 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n2865), .B0(n3232), .B1(
n2864), .C0(n2811), .Y(n1111) );
AO22XLTS U3716 ( .A0(n2786), .A1(DmP_mant_SFG_SWR[6]), .B0(n2756), .B1(n2812), .Y(n1108) );
AOI22X1TS U3717 ( .A0(n1839), .A1(DMP_SFG[4]), .B0(Raw_mant_NRM_SWR[6]),
.B1(n2814), .Y(n2813) );
OAI221XLTS U3718 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n2865), .B0(n3233), .B1(
n2864), .C0(n2813), .Y(n1107) );
AOI22X1TS U3719 ( .A0(n1839), .A1(DMP_SFG[5]), .B0(Raw_mant_NRM_SWR[7]),
.B1(n2814), .Y(n2815) );
OAI221XLTS U3720 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n2865), .B0(n3234), .B1(
n2864), .C0(n2815), .Y(n1105) );
AOI22X1TS U3721 ( .A0(Data_array_SWR[17]), .A1(n2943), .B0(n1836), .B1(n2945), .Y(n2818) );
NAND2X1TS U3722 ( .A(n2831), .B(n2947), .Y(n2932) );
OAI2BB2XLTS U3723 ( .B0(n3199), .B1(n2932), .A0N(Data_array_SWR[21]), .A1N(
n2942), .Y(n2816) );
AOI21X1TS U3724 ( .A0(n1830), .A1(n2944), .B0(n2816), .Y(n2817) );
OAI211X1TS U3725 ( .A0(n2819), .A1(n1870), .B0(n2818), .C0(n2817), .Y(n2821)
);
INVX2TS U3726 ( .A(n2820), .Y(n2822) );
OAI2BB2XLTS U3727 ( .B0(n2971), .B1(n2829), .A0N(final_result_ieee[20]),
.A1N(n2929), .Y(n1104) );
OAI2BB2XLTS U3728 ( .B0(n2981), .B1(n2829), .A0N(final_result_ieee[30]),
.A1N(n2929), .Y(n1103) );
NOR2X2TS U3729 ( .A(shift_value_SHT2_EWR[5]), .B(n2953), .Y(n2954) );
AOI22X1TS U3730 ( .A0(Data_array_SWR[16]), .A1(n2942), .B0(n1835), .B1(n2943), .Y(n2826) );
AOI22X1TS U3731 ( .A0(Data_array_SWR[19]), .A1(n2944), .B0(n1832), .B1(n2945), .Y(n2825) );
INVX2TS U3732 ( .A(n1870), .Y(n2949) );
AOI22X1TS U3733 ( .A0(n2949), .A1(n2823), .B0(n2947), .B1(n2822), .Y(n2824)
);
NAND3XLTS U3734 ( .A(n2826), .B(n2825), .C(n2824), .Y(n2828) );
AOI22X1TS U3735 ( .A0(n2954), .A1(n2827), .B0(n2953), .B1(n2828), .Y(n2965)
);
OAI2BB2XLTS U3736 ( .B0(n2965), .B1(n2829), .A0N(final_result_ieee[14]),
.A1N(n2929), .Y(n1102) );
NOR2X2TS U3737 ( .A(shift_value_SHT2_EWR[5]), .B(n2958), .Y(n2956) );
AOI22X1TS U3738 ( .A0(n2958), .A1(n2828), .B0(n2956), .B1(n2827), .Y(n2987)
);
OAI2BB2XLTS U3739 ( .B0(n2987), .B1(n2829), .A0N(final_result_ieee[36]),
.A1N(n2929), .Y(n1101) );
INVX4TS U3740 ( .A(n2829), .Y(n2903) );
AOI22X1TS U3741 ( .A0(Data_array_SWR[29]), .A1(n1973), .B0(
Data_array_SWR[25]), .B1(n2830), .Y(n2833) );
AOI22X1TS U3742 ( .A0(Data_array_SWR[23]), .A1(n2884), .B0(
Data_array_SWR[19]), .B1(n2883), .Y(n2832) );
NAND2X1TS U3743 ( .A(n2833), .B(n2832), .Y(n2842) );
INVX2TS U3744 ( .A(n2845), .Y(n2836) );
AOI22X1TS U3745 ( .A0(n2938), .A1(n2842), .B0(n2939), .B1(n2836), .Y(n2835)
);
NAND2X1TS U3746 ( .A(n1958), .B(n2843), .Y(n2834) );
AOI22X1TS U3747 ( .A0(n2940), .A1(n2842), .B0(n2939), .B1(n2843), .Y(n2838)
);
NAND2X1TS U3748 ( .A(n1958), .B(n2836), .Y(n2837) );
INVX2TS U3749 ( .A(n2947), .Y(n2906) );
AOI22X1TS U3750 ( .A0(Data_array_SWR[12]), .A1(n2945), .B0(n1835), .B1(n2942), .Y(n2841) );
AOI22X1TS U3751 ( .A0(n1832), .A1(n2943), .B0(Data_array_SWR[16]), .B1(n2944), .Y(n2840) );
OAI211X1TS U3752 ( .A0(n2845), .A1(n2906), .B0(n2841), .C0(n2840), .Y(n2844)
);
AOI222X1TS U3753 ( .A0(n2844), .A1(n3068), .B0(n2842), .B1(n1958), .C0(n2843), .C1(n2938), .Y(n2961) );
OAI2BB2XLTS U3754 ( .B0(n2961), .B1(n2829), .A0N(final_result_ieee[10]),
.A1N(n2929), .Y(n1097) );
OAI2BB2XLTS U3755 ( .B0(n2993), .B1(n2829), .A0N(final_result_ieee[40]),
.A1N(n2929), .Y(n1096) );
OAI22X1TS U3756 ( .A0(n2846), .A1(n3068), .B0(n2845), .B1(n2898), .Y(n2996)
);
AOI22X1TS U3757 ( .A0(Data_array_SWR[13]), .A1(n2945), .B0(n1836), .B1(n2942), .Y(n2848) );
AOI22X1TS U3758 ( .A0(Data_array_SWR[17]), .A1(n2944), .B0(n1828), .B1(n2943), .Y(n2847) );
OAI211X1TS U3759 ( .A0(n2879), .A1(n2906), .B0(n2848), .C0(n2847), .Y(n2860)
);
AOI22X1TS U3760 ( .A0(Data_array_SWR[31]), .A1(n1973), .B0(
Data_array_SWR[27]), .B1(n2882), .Y(n2851) );
AOI22X1TS U3761 ( .A0(Data_array_SWR[21]), .A1(n2883), .B0(n1830), .B1(n2849), .Y(n2850) );
NAND2X1TS U3762 ( .A(n2851), .B(n2850), .Y(n2858) );
AOI222X1TS U3763 ( .A0(n2860), .A1(n2953), .B0(n2858), .B1(n1958), .C0(n2859), .C1(n2938), .Y(n2963) );
OAI2BB2XLTS U3764 ( .B0(n2963), .B1(n2829), .A0N(final_result_ieee[12]),
.A1N(n2929), .Y(n1094) );
INVX2TS U3765 ( .A(n2879), .Y(n2854) );
AOI22X1TS U3766 ( .A0(n2938), .A1(n2858), .B0(n2939), .B1(n2854), .Y(n2853)
);
NAND2X1TS U3767 ( .A(n1958), .B(n2859), .Y(n2852) );
AOI22X1TS U3768 ( .A0(n2940), .A1(n2858), .B0(n2939), .B1(n2859), .Y(n2856)
);
NAND2X1TS U3769 ( .A(n1958), .B(n2854), .Y(n2855) );
OAI2BB2XLTS U3770 ( .B0(n2989), .B1(n2829), .A0N(final_result_ieee[38]),
.A1N(n2929), .Y(n1091) );
AOI22X1TS U3771 ( .A0(n2862), .A1(DMP_SFG[6]), .B0(Raw_mant_NRM_SWR[8]),
.B1(n2861), .Y(n2863) );
OAI221XLTS U3772 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n2865), .B0(n3235), .B1(
n2864), .C0(n2863), .Y(n1089) );
AOI22X1TS U3773 ( .A0(Data_array_SWR[33]), .A1(n2884), .B0(n1827), .B1(n2831), .Y(n2866) );
OAI21X1TS U3774 ( .A0(n3185), .A1(n2867), .B0(n2866), .Y(n2875) );
INVX2TS U3775 ( .A(n2875), .Y(n2877) );
AOI22X1TS U3776 ( .A0(Data_array_SWR[24]), .A1(n2942), .B0(
Data_array_SWR[18]), .B1(n2945), .Y(n2869) );
AOI22X1TS U3777 ( .A0(Data_array_SWR[28]), .A1(n2944), .B0(
Data_array_SWR[22]), .B1(n2943), .Y(n2868) );
OAI211X1TS U3778 ( .A0(n2877), .A1(n1870), .B0(n2869), .C0(n2868), .Y(n2976)
);
AO22XLTS U3779 ( .A0(Data_array_SWR[14]), .A1(n2942), .B0(n1823), .B1(n2943),
.Y(n2874) );
AOI22X1TS U3780 ( .A0(Data_array_SWR[28]), .A1(n1973), .B0(
Data_array_SWR[24]), .B1(n2882), .Y(n2872) );
AOI22X1TS U3781 ( .A0(n1833), .A1(n2944), .B0(Data_array_SWR[11]), .B1(n2945), .Y(n2871) );
AOI22X1TS U3782 ( .A0(Data_array_SWR[22]), .A1(n2884), .B0(
Data_array_SWR[18]), .B1(n2883), .Y(n2870) );
AOI32X1TS U3783 ( .A0(n2872), .A1(n2871), .A2(n2870), .B0(n1870), .B1(n2871),
.Y(n2873) );
AOI211X1TS U3784 ( .A0(n2947), .A1(n2875), .B0(n2874), .C0(n2873), .Y(n2876)
);
OAI22X1TS U3785 ( .A0(n2958), .A1(n2876), .B0(n2877), .B1(n2892), .Y(n2960)
);
OAI22X1TS U3786 ( .A0(n2877), .A1(n2898), .B0(n2876), .B1(n2953), .Y(n2995)
);
OAI22X1TS U3787 ( .A0(n2880), .A1(n3068), .B0(n2879), .B1(n2898), .Y(n2999)
);
AOI22X1TS U3788 ( .A0(n1827), .A1(n1973), .B0(Data_array_SWR[28]), .B1(n2882), .Y(n2886) );
AOI22X1TS U3789 ( .A0(Data_array_SWR[24]), .A1(n2884), .B0(
Data_array_SWR[22]), .B1(n2883), .Y(n2885) );
NAND2X1TS U3790 ( .A(n2886), .B(n2885), .Y(n2895) );
INVX2TS U3791 ( .A(n2899), .Y(n2889) );
AOI22X1TS U3792 ( .A0(n2938), .A1(n2895), .B0(n2939), .B1(n2889), .Y(n2888)
);
NAND2X1TS U3793 ( .A(n1958), .B(n2896), .Y(n2887) );
AOI22X1TS U3794 ( .A0(n2940), .A1(n2895), .B0(n2939), .B1(n2896), .Y(n2891)
);
NAND2X1TS U3795 ( .A(n1958), .B(n2889), .Y(n2890) );
AOI22X1TS U3796 ( .A0(n1833), .A1(n2942), .B0(n1823), .B1(n2945), .Y(n2894)
);
AOI22X1TS U3797 ( .A0(Data_array_SWR[14]), .A1(n2943), .B0(
Data_array_SWR[18]), .B1(n2944), .Y(n2893) );
OAI211X1TS U3798 ( .A0(n2899), .A1(n2906), .B0(n2894), .C0(n2893), .Y(n2897)
);
OAI2BB2XLTS U3799 ( .B0(n2964), .B1(n2829), .A0N(final_result_ieee[13]),
.A1N(n2929), .Y(n1080) );
OAI2BB2XLTS U3800 ( .B0(n2988), .B1(n2829), .A0N(final_result_ieee[37]),
.A1N(n2929), .Y(n1079) );
OAI22X1TS U3801 ( .A0(n2900), .A1(n2953), .B0(n2899), .B1(n2898), .Y(n3000)
);
AOI22X1TS U3802 ( .A0(Data_array_SWR[15]), .A1(n2942), .B0(n1826), .B1(n2945), .Y(n2905) );
AOI22X1TS U3803 ( .A0(n1834), .A1(n2944), .B0(n1831), .B1(n2943), .Y(n2904)
);
OAI211X1TS U3804 ( .A0(n2907), .A1(n2906), .B0(n2905), .C0(n2904), .Y(n2910)
);
OAI2BB2XLTS U3805 ( .B0(n2962), .B1(n2829), .A0N(final_result_ieee[11]),
.A1N(n2959), .Y(n1074) );
OAI2BB2XLTS U3806 ( .B0(n2990), .B1(n2829), .A0N(final_result_ieee[39]),
.A1N(n2959), .Y(n1073) );
AOI22X1TS U3807 ( .A0(n1833), .A1(n2943), .B0(Data_array_SWR[14]), .B1(n2945), .Y(n2913) );
OAI2BB2XLTS U3808 ( .B0(n3185), .B1(n2932), .A0N(Data_array_SWR[18]), .A1N(
n2942), .Y(n2911) );
AOI21X1TS U3809 ( .A0(Data_array_SWR[22]), .A1(n2944), .B0(n2911), .Y(n2912)
);
OAI211X1TS U3810 ( .A0(n2914), .A1(n1870), .B0(n2913), .C0(n2912), .Y(n2916)
);
AOI22X1TS U3811 ( .A0(n2954), .A1(n2915), .B0(n2953), .B1(n2916), .Y(n2968)
);
OAI2BB2XLTS U3812 ( .B0(n2968), .B1(n2829), .A0N(final_result_ieee[17]),
.A1N(n2959), .Y(n1069) );
AOI22X1TS U3813 ( .A0(n2958), .A1(n2916), .B0(n2956), .B1(n2915), .Y(n2984)
);
OAI2BB2XLTS U3814 ( .B0(n2984), .B1(n2829), .A0N(final_result_ieee[33]),
.A1N(n2959), .Y(n1068) );
AOI22X1TS U3815 ( .A0(Data_array_SWR[16]), .A1(n2943), .B0(n1835), .B1(n2945), .Y(n2920) );
OAI2BB2XLTS U3816 ( .B0(n3197), .B1(n2932), .A0N(Data_array_SWR[19]), .A1N(
n2942), .Y(n2917) );
AOI21X1TS U3817 ( .A0(Data_array_SWR[23]), .A1(n2918), .B0(n2917), .Y(n2919)
);
OAI211X1TS U3818 ( .A0(n2921), .A1(n1870), .B0(n2920), .C0(n2919), .Y(n2923)
);
INVX2TS U3819 ( .A(n2922), .Y(n2924) );
AOI222X1TS U3820 ( .A0(n2923), .A1(n2953), .B0(n2924), .B1(n2939), .C0(n2925), .C1(n2938), .Y(n2969) );
OAI2BB2XLTS U3821 ( .B0(n2969), .B1(n2829), .A0N(final_result_ieee[18]),
.A1N(n2959), .Y(n1067) );
OAI2BB2XLTS U3822 ( .B0(n2983), .B1(n2829), .A0N(final_result_ieee[32]),
.A1N(n2959), .Y(n1066) );
AOI22X1TS U3823 ( .A0(Data_array_SWR[17]), .A1(n2942), .B0(n1836), .B1(n2943), .Y(n2928) );
AOI22X1TS U3824 ( .A0(Data_array_SWR[21]), .A1(n2944), .B0(n1828), .B1(n2945), .Y(n2927) );
AOI22X1TS U3825 ( .A0(n2949), .A1(n2925), .B0(n2947), .B1(n2924), .Y(n2926)
);
NAND3XLTS U3826 ( .A(n2928), .B(n2927), .C(n2926), .Y(n2931) );
AOI22X1TS U3827 ( .A0(n2954), .A1(n2930), .B0(n2953), .B1(n2931), .Y(n2967)
);
OAI2BB2XLTS U3828 ( .B0(n2967), .B1(n2829), .A0N(final_result_ieee[16]),
.A1N(n2929), .Y(n1065) );
AOI22X1TS U3829 ( .A0(n2958), .A1(n2931), .B0(n2956), .B1(n2930), .Y(n2985)
);
OAI2BB2XLTS U3830 ( .B0(n2985), .B1(n2829), .A0N(final_result_ieee[34]),
.A1N(n2959), .Y(n1064) );
AOI22X1TS U3831 ( .A0(Data_array_SWR[15]), .A1(n2945), .B0(n1834), .B1(n2943), .Y(n2935) );
OAI2BB2XLTS U3832 ( .B0(n3198), .B1(n2932), .A0N(Data_array_SWR[20]), .A1N(
n2942), .Y(n2933) );
AOI21X1TS U3833 ( .A0(n1829), .A1(n2944), .B0(n2933), .Y(n2934) );
OAI211X1TS U3834 ( .A0(n2936), .A1(n1870), .B0(n2935), .C0(n2934), .Y(n2941)
);
INVX2TS U3835 ( .A(n2937), .Y(n2946) );
AOI222X1TS U3836 ( .A0(n2941), .A1(n2953), .B0(n2946), .B1(n2939), .C0(n2948), .C1(n2938), .Y(n2970) );
OAI2BB2XLTS U3837 ( .B0(n2970), .B1(n2829), .A0N(final_result_ieee[19]),
.A1N(n2959), .Y(n1059) );
OAI2BB2XLTS U3838 ( .B0(n2982), .B1(n2829), .A0N(final_result_ieee[31]),
.A1N(n2959), .Y(n1058) );
AOI22X1TS U3839 ( .A0(Data_array_SWR[15]), .A1(n2943), .B0(n1834), .B1(n2942), .Y(n2952) );
AOI22X1TS U3840 ( .A0(n1831), .A1(n2945), .B0(Data_array_SWR[20]), .B1(n2944), .Y(n2951) );
AOI22X1TS U3841 ( .A0(n2949), .A1(n2948), .B0(n2947), .B1(n2946), .Y(n2950)
);
NAND3XLTS U3842 ( .A(n2952), .B(n2951), .C(n2950), .Y(n2957) );
AOI22X1TS U3843 ( .A0(n2954), .A1(n2955), .B0(n2953), .B1(n2957), .Y(n2966)
);
OAI2BB2XLTS U3844 ( .B0(n2966), .B1(n2829), .A0N(final_result_ieee[15]),
.A1N(n2959), .Y(n1057) );
AOI22X1TS U3845 ( .A0(n2958), .A1(n2957), .B0(n2956), .B1(n2955), .Y(n2986)
);
OAI2BB2XLTS U3846 ( .B0(n2986), .B1(n2829), .A0N(final_result_ieee[35]),
.A1N(n2959), .Y(n1056) );
AO22XLTS U3847 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[11]), .B0(n2994), .B1(
n2960), .Y(n1049) );
AOI22X1TS U3848 ( .A0(n3011), .A1(n2961), .B0(n3009), .B1(n1853), .Y(n1048)
);
AOI22X1TS U3849 ( .A0(n2756), .A1(n2962), .B0(n2992), .B1(n1854), .Y(n1047)
);
AOI22X1TS U3850 ( .A0(n2994), .A1(n2963), .B0(n2992), .B1(n1855), .Y(n1046)
);
AOI22X1TS U3851 ( .A0(n2997), .A1(n2964), .B0(n3009), .B1(n1856), .Y(n1045)
);
AOI22X1TS U3852 ( .A0(n2991), .A1(n2965), .B0(n2992), .B1(n1857), .Y(n1044)
);
AOI22X1TS U3853 ( .A0(n2994), .A1(n2966), .B0(n3009), .B1(n1858), .Y(n1043)
);
AOI22X1TS U3854 ( .A0(n1866), .A1(n2967), .B0(n3009), .B1(n1859), .Y(n1042)
);
AOI22X1TS U3855 ( .A0(n3002), .A1(n2968), .B0(n2992), .B1(n1860), .Y(n1041)
);
AOI22X1TS U3856 ( .A0(n3008), .A1(n2969), .B0(n3009), .B1(n1861), .Y(n1040)
);
AOI22X1TS U3857 ( .A0(n2994), .A1(n2970), .B0(n2992), .B1(n1840), .Y(n1039)
);
AOI22X1TS U3858 ( .A0(n1866), .A1(n2971), .B0(n2992), .B1(n1841), .Y(n1038)
);
AO22XLTS U3859 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[23]), .B0(n3011), .B1(
n2972), .Y(n1037) );
AO22XLTS U3860 ( .A0(n2761), .A1(DmP_mant_SFG_SWR[24]), .B0(n3002), .B1(
n2973), .Y(n1036) );
AO22XLTS U3861 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[25]), .B0(n3008), .B1(
n2974), .Y(n1035) );
AO22XLTS U3862 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[26]), .B0(n3008), .B1(
n2975), .Y(n1034) );
AO22XLTS U3863 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[27]), .B0(n3011), .B1(
n2976), .Y(n1033) );
AO22XLTS U3864 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[28]), .B0(n2997), .B1(
n2977), .Y(n1032) );
AO22XLTS U3865 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[29]), .B0(n3011), .B1(
n2978), .Y(n1031) );
AO22XLTS U3866 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[30]), .B0(n2991), .B1(
n2979), .Y(n1030) );
AO22XLTS U3867 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[31]), .B0(n3002), .B1(
n2980), .Y(n1029) );
AOI22X1TS U3868 ( .A0(n3008), .A1(n2981), .B0(n3009), .B1(n1842), .Y(n1028)
);
AOI22X1TS U3869 ( .A0(n2997), .A1(n2982), .B0(n3009), .B1(n1843), .Y(n1027)
);
AOI22X1TS U3870 ( .A0(n2756), .A1(n2983), .B0(n2992), .B1(n1844), .Y(n1026)
);
AOI22X1TS U3871 ( .A0(n1866), .A1(n2984), .B0(n3009), .B1(n1845), .Y(n1025)
);
AOI22X1TS U3872 ( .A0(n2991), .A1(n2985), .B0(n2992), .B1(n1846), .Y(n1024)
);
AOI22X1TS U3873 ( .A0(n1866), .A1(n2986), .B0(n2992), .B1(n1847), .Y(n1023)
);
AOI22X1TS U3874 ( .A0(n3011), .A1(n2987), .B0(n2992), .B1(n1848), .Y(n1022)
);
AOI22X1TS U3875 ( .A0(n2997), .A1(n2988), .B0(n3009), .B1(n1849), .Y(n1021)
);
AOI22X1TS U3876 ( .A0(n2994), .A1(n2989), .B0(n3009), .B1(n1850), .Y(n1020)
);
AOI22X1TS U3877 ( .A0(n2994), .A1(n2990), .B0(n3009), .B1(n1851), .Y(n1019)
);
AOI22X1TS U3878 ( .A0(n2997), .A1(n2993), .B0(n2992), .B1(n1852), .Y(n1018)
);
AO22XLTS U3879 ( .A0(n2786), .A1(DmP_mant_SFG_SWR[43]), .B0(n3011), .B1(
n2995), .Y(n1017) );
AO22XLTS U3880 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[44]), .B0(n2997), .B1(
n2996), .Y(n1016) );
AO22XLTS U3881 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[45]), .B0(n3002), .B1(
n2998), .Y(n1015) );
AO22XLTS U3882 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[46]), .B0(n2991), .B1(
n2999), .Y(n1014) );
AO22XLTS U3883 ( .A0(n2992), .A1(DmP_mant_SFG_SWR[47]), .B0(n2991), .B1(
n3000), .Y(n1013) );
AO22XLTS U3884 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[48]), .B0(n2991), .B1(
n3001), .Y(n1012) );
AO22XLTS U3885 ( .A0(n3009), .A1(DmP_mant_SFG_SWR[49]), .B0(n3002), .B1(
n3003), .Y(n1011) );
AO22XLTS U3886 ( .A0(n3009), .A1(DmP_mant_SFG_SWR[50]), .B0(n2991), .B1(
n3004), .Y(n1010) );
AO22XLTS U3887 ( .A0(n3006), .A1(DmP_mant_SFG_SWR[51]), .B0(n3008), .B1(
n3005), .Y(n1009) );
AO22XLTS U3888 ( .A0(n2992), .A1(DmP_mant_SFG_SWR[52]), .B0(n3008), .B1(
n3007), .Y(n1008) );
AO22XLTS U3889 ( .A0(n3012), .A1(DmP_mant_SFG_SWR[53]), .B0(n3008), .B1(
n3010), .Y(n1007) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_LOA_syn.sdf");
endmodule
|
// -*- Mode: Verilog -*-
// Filename : system_controller.v
// Description : Prototype System Controller for SPI FPGA
// Author : Philip Tracton
// Created On : Fri Jul 8 20:54:44 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Jul 8 20:54:44 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module system_controller (/*AUTOARG*/
// Outputs
clk, rst, nrst,
// Inputs
clk_i, rst_i
) ;
input wire clk_i;
input wire rst_i;
output wire clk;
output wire rst;
output wire nrst;
`ifdef XILINX
//
// Input buffer the clk pin
//
wire clk_ibuf;
IBUF xclk_ibufg(.I(clk_i), .O(clk_ibuf));
`else
assign clk = clk_i;
reg [4:0] reset_count =0;
assign rst = |reset_count;
assign nrst = ~rst;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
reset_count <= 1;
end else begin
if (reset_count)
reset_count <= reset_count + 1;
end
`endif
endmodule // system_controller
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_frontend.v
//
// *Module Description:
// openMSP430 Instruction fetch and decode unit
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 60 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-02-03 22:12:25 +0100 (Mi, 03 Feb 2010) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_frontend (
// OUTPUTs
dbg_halt_st, // Halt/Run status from CPU
decode_noirq, // Frontend decode instruction
e_state, // Execution state
exec_done, // Execution completed
inst_ad, // Decoded Inst: destination addressing mode
inst_as, // Decoded Inst: source addressing mode
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_dest, // Decoded Inst: destination (one hot)
inst_dext, // Decoded Inst: destination extended instruction word
inst_irq_rst, // Decoded Inst: Reset interrupt
inst_jmp, // Decoded Inst: Conditional jump
inst_sext, // Decoded Inst: source extended instruction word
inst_so, // Decoded Inst: Single-operand arithmetic
inst_src, // Decoded Inst: source (one hot)
inst_type, // Decoded Instruction type
irq_acc, // Interrupt request accepted (one-hot signal)
mab, // Frontend Memory address bus
mb_en, // Frontend Memory bus enable
nmi_acc, // Non-Maskable interrupt request accepted
pc, // Program counter
pc_nxt, // Next PC value (for CALL & IRQ)
// INPUTs
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
fe_pmem_wait, // Frontend wait for Instruction fetch
gie, // General interrupt enable
irq, // Maskable interrupts
mclk, // Main system clock
mdb_in, // Frontend Memory data bus input
nmi_evt, // Non-maskable interrupt event
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
puc, // Main system reset
wdt_irq // Watchdog-timer interrupt
);
// OUTPUTs
//=========
output dbg_halt_st; // Halt/Run status from CPU
output decode_noirq; // Frontend decode instruction
output [3:0] e_state; // Execution state
output exec_done; // Execution completed
output [7:0] inst_ad; // Decoded Inst: destination addressing mode
output [7:0] inst_as; // Decoded Inst: source addressing mode
output [11:0] inst_alu; // ALU control signals
output inst_bw; // Decoded Inst: byte width
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
output inst_irq_rst; // Decoded Inst: Reset interrupt
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
output [15:0] inst_src; // Decoded Inst: source (one hot)
output [2:0] inst_type; // Decoded Instruction type
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [15:0] mab; // Frontend Memory address bus
output mb_en; // Frontend Memory bus enable
output nmi_acc; // Non-Maskable interrupt request accepted
output [15:0] pc; // Program counter
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
// INPUTs
//=========
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
input fe_pmem_wait; // Frontend wait for Instruction fetch
input gie; // General interrupt enable
input [13:0] irq; // Maskable interrupts
input mclk; // Main system clock
input [15:0] mdb_in; // Frontend Memory data bus input
input nmi_evt; // Non-maskable interrupt event
input [15:0] pc_sw; // Program counter software value
input pc_sw_wr; // Program counter software write
input puc; // Main system reset
input wdt_irq; // Watchdog-timer interrupt
//=============================================================================
// 1) FRONTEND STATE MACHINE
//=============================================================================
// The wire "conv" is used as state bits to calculate the next response
reg [2:0] i_state;
reg [2:0] i_state_nxt;
reg [1:0] inst_sz;
wire [1:0] inst_sz_nxt;
wire irq_detect;
wire [2:0] inst_type_nxt;
wire is_const;
reg [15:0] sconst_nxt;
reg [3:0] e_state_nxt;
// State machine definitons
parameter I_IRQ_FETCH = 3'h0;
parameter I_IRQ_DONE = 3'h1;
parameter I_DEC = 3'h2; // New instruction ready for decode
parameter I_EXT1 = 3'h3; // 1st Extension word
parameter I_EXT2 = 3'h4; // 2nd Extension word
parameter I_IDLE = 3'h5; // CPU is in IDLE mode
// States Transitions
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state)
case(i_state)
I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
(~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE;
I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
I_IRQ_DONE : i_state_nxt = I_DEC;
I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
(cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE :
dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
pc_sw_wr ? I_DEC :
~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH :
pc_sw_wr ? I_DEC :
(inst_sz!=2'b01) ? I_EXT2 : I_DEC;
I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC;
default : i_state_nxt = I_IRQ_FETCH;
endcase
// State machine
always @(posedge mclk or posedge puc)
if (puc) i_state <= I_IRQ_FETCH;
else i_state <= i_state_nxt;
// Utility signals
wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE)));
wire decode = decode_noirq | irq_detect;
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE);
// Debug interface cpu status
reg dbg_halt_st;
always @(posedge mclk or posedge puc)
if (puc) dbg_halt_st <= 1'b0;
else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
//=============================================================================
// 2) INTERRUPT HANDLING
//=============================================================================
// Detect nmi interrupt
reg inst_nmi;
always @(posedge mclk or posedge puc)
if (puc) inst_nmi <= 1'b0;
else if (nmi_evt) inst_nmi <= 1'b1;
else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0;
// Detect reset interrupt
reg inst_irq_rst;
always @(posedge mclk or posedge puc)
if (puc) inst_irq_rst <= 1'b1;
else if (exec_done) inst_irq_rst <= 1'b0;
// Detect other interrupts
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE));
// Select interrupt vector
reg [3:0] irq_num;
always @(posedge mclk or posedge puc)
if (puc) irq_num <= 4'hf;
else if (irq_detect) irq_num <= inst_nmi ? 4'he :
irq[13] ? 4'hd :
irq[12] ? 4'hc :
irq[11] ? 4'hb :
(irq[10] | wdt_irq) ? 4'ha :
irq[9] ? 4'h9 :
irq[8] ? 4'h8 :
irq[7] ? 4'h7 :
irq[6] ? 4'h6 :
irq[5] ? 4'h5 :
irq[4] ? 4'h4 :
irq[3] ? 4'h3 :
irq[2] ? 4'h2 :
irq[1] ? 4'h1 :
irq[0] ? 4'h0 : 4'hf;
wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
// Interrupt request accepted
wire [15:0] irq_acc_all = (16'h0001 << irq_num) & {16{(i_state==I_IRQ_FETCH)}};
wire [13:0] irq_acc = irq_acc_all[13:0];
wire nmi_acc = irq_acc_all[14];
//=============================================================================
// 3) FETCH INSTRUCTION
//=============================================================================
//
// 3.1) PROGRAM COUNTER & MEMORY INTERFACE
//-----------------------------------------
// Program counter
reg [15:0] pc;
// Compute next PC value
wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
wire [15:0] pc_nxt = pc_sw_wr ? pc_sw :
(i_state==I_IRQ_FETCH) ? irq_addr :
(i_state==I_IRQ_DONE) ? mdb_in : pc_incr;
always @(posedge mclk or posedge puc)
if (puc) pc <= 16'h0000;
else pc <= pc_nxt;
// Check if ROM has been busy in order to retry ROM access
reg pmem_busy;
always @(posedge mclk or posedge puc)
if (puc) pmem_busy <= 16'h0000;
else pmem_busy <= fe_pmem_wait;
// Memory interface
wire [15:0] mab = pc_nxt;
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
//
// 3.2) INSTRUCTION REGISTER
//--------------------------------
// Instruction register
wire [15:0] ir = mdb_in;
// Detect if source extension word is required
wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
// Detect if destination extension word is required
wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]);
// For the Symbolic addressing mode, add -2 to the extension word in order
// to make up for the PC address
wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) |
((i_state==I_EXT2) & inst_ad[`SYMB]) |
((i_state==I_EXT1) & ~inst_as[`SYMB] &
~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16'hfffe : 16'h0000;
wire [15:0] ext_nxt = ir + ext_incr;
// Store source extension word
reg [15:0] inst_sext;
always @(posedge mclk or posedge puc)
if (puc) inst_sext <= 16'h0000;
else if (decode & is_const) inst_sext <= sconst_nxt;
else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt;
// Source extension word is ready
wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
// Store destination extension word
reg [15:0] inst_dext;
always @(posedge mclk or posedge puc)
if (puc) inst_dext <= 16'h0000;
else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
else if (i_state==I_EXT2) inst_dext <= ext_nxt;
// Destination extension word is ready
wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
//=============================================================================
// 4) DECODE INSTRUCTION
//=============================================================================
//
// 4.1) OPCODE: INSTRUCTION TYPE
//----------------------------------------
// Instructions type is encoded in a one hot fashion as following:
//
// 3'b001: Single-operand arithmetic
// 3'b010: Conditional jump
// 3'b100: Two-operand arithmetic
reg [2:0] inst_type;
assign inst_type_nxt = {(ir[15:14]!=2'b00),
(ir[15:13]==3'b001),
(ir[15:13]==3'b000)} & {3{~irq_detect}};
always @(posedge mclk or posedge puc)
if (puc) inst_type <= 3'b000;
else if (decode) inst_type <= inst_type_nxt;
//
// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC
//----------------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 8'b00000001: RRC
// 8'b00000010: SWPB
// 8'b00000100: RRA
// 8'b00001000: SXT
// 8'b00010000: PUSH
// 8'b00100000: CALL
// 8'b01000000: RETI
// 8'b10000000: IRQ
reg [7:0] inst_so;
wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : ((8'h01<<ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
always @(posedge mclk or posedge puc)
if (puc) inst_so <= 8'h00;
else if (decode) inst_so <= inst_so_nxt;
//
// 4.3) OPCODE: CONDITIONAL JUMP
//--------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 8'b00000001: JNE/JNZ
// 8'b00000010: JEQ/JZ
// 8'b00000100: JNC/JLO
// 8'b00001000: JC/JHS
// 8'b00010000: JN
// 8'b00100000: JGE
// 8'b01000000: JL
// 8'b10000000: JMP
reg [2:0] inst_jmp_bin;
always @(posedge mclk or posedge puc)
if (puc) inst_jmp_bin <= 3'h0;
else if (decode) inst_jmp_bin <= ir[12:10];
wire [7:0] inst_jmp = (8'h01<<inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
//
// 4.4) OPCODE: TWO-OPERAND ARITHMETIC
//-------------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 12'b000000000001: MOV
// 12'b000000000010: ADD
// 12'b000000000100: ADDC
// 12'b000000001000: SUBC
// 12'b000000010000: SUB
// 12'b000000100000: CMP
// 12'b000001000000: DADD
// 12'b000010000000: BIT
// 12'b000100000000: BIC
// 12'b001000000000: BIS
// 12'b010000000000: XOR
// 12'b100000000000: AND
wire [15:0] inst_to_1hot = (16'h0001<<ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
//
// 4.5) SOURCE AND DESTINATION REGISTERS
//---------------------------------------
// Destination register
reg [3:0] inst_dest_bin;
always @(posedge mclk or posedge puc)
if (puc) inst_dest_bin <= 4'h0;
else if (decode) inst_dest_bin <= ir[3:0];
wire [15:0] inst_dest = dbg_halt_st ? (16'h0001 << dbg_reg_sel) :
inst_type[`INST_JMP] ? 16'h0001 :
inst_so[`IRQ] |
inst_so[`PUSH] |
inst_so[`CALL] ? 16'h0002 :
(16'h0001 << inst_dest_bin);
// Source register
reg [3:0] inst_src_bin;
always @(posedge mclk or posedge puc)
if (puc) inst_src_bin <= 4'h0;
else if (decode) inst_src_bin <= ir[11:8];
wire [15:0] inst_src = inst_type[`INST_TO] ? (16'h0001 << inst_src_bin) :
inst_so[`RETI] ? 16'h0002 :
inst_so[`IRQ] ? 16'h0001 :
inst_type[`INST_SO] ? (16'h0001 << inst_dest_bin) : 16'h0000;
//
// 4.6) SOURCE ADDRESSING MODES
//--------------------------------
// Source addressing modes are encoded in a one hot fashion as following:
//
// 13'b0000000000001: Register direct.
// 13'b0000000000010: Register indexed.
// 13'b0000000000100: Register indirect.
// 13'b0000000001000: Register indirect autoincrement.
// 13'b0000000010000: Symbolic (operand is in memory at address PC+x).
// 13'b0000000100000: Immediate (operand is next word in the instruction stream).
// 13'b0000001000000: Absolute (operand is in memory at address x).
// 13'b0000010000000: Constant 4.
// 13'b0000100000000: Constant 8.
// 13'b0001000000000: Constant 0.
// 13'b0010000000000: Constant 1.
// 13'b0100000000000: Constant 2.
// 13'b1000000000000: Constant -1.
reg [12:0] inst_as_nxt;
wire [3:0] src_reg = inst_type_nxt[`INST_SO] ? ir[3:0] : ir[11:8];
always @(src_reg or ir or inst_type_nxt)
begin
if (inst_type_nxt[`INST_JMP])
inst_as_nxt = 13'b0000000000001;
else if (src_reg==4'h3) // Addressing mode using R3
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b1000000000000;
2'b10 : inst_as_nxt = 13'b0100000000000;
2'b01 : inst_as_nxt = 13'b0010000000000;
default: inst_as_nxt = 13'b0001000000000;
endcase
else if (src_reg==4'h2) // Addressing mode using R2
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b0000100000000;
2'b10 : inst_as_nxt = 13'b0000010000000;
2'b01 : inst_as_nxt = 13'b0000001000000;
default: inst_as_nxt = 13'b0000000000001;
endcase
else if (src_reg==4'h0) // Addressing mode using R0
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b0000000100000;
2'b10 : inst_as_nxt = 13'b0000000000100;
2'b01 : inst_as_nxt = 13'b0000000010000;
default: inst_as_nxt = 13'b0000000000001;
endcase
else // General Addressing mode
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b0000000001000;
2'b10 : inst_as_nxt = 13'b0000000000100;
2'b01 : inst_as_nxt = 13'b0000000000010;
default: inst_as_nxt = 13'b0000000000001;
endcase
end
assign is_const = |inst_as_nxt[12:7];
reg [7:0] inst_as;
always @(posedge mclk or posedge puc)
if (puc) inst_as <= 8'h00;
else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
// 13'b0000010000000: Constant 4.
// 13'b0000100000000: Constant 8.
// 13'b0001000000000: Constant 0.
// 13'b0010000000000: Constant 1.
// 13'b0100000000000: Constant 2.
// 13'b1000000000000: Constant -1.
always @(inst_as_nxt)
begin
if (inst_as_nxt[7]) sconst_nxt = 16'h0004;
else if (inst_as_nxt[8]) sconst_nxt = 16'h0008;
else if (inst_as_nxt[9]) sconst_nxt = 16'h0000;
else if (inst_as_nxt[10]) sconst_nxt = 16'h0001;
else if (inst_as_nxt[11]) sconst_nxt = 16'h0002;
else if (inst_as_nxt[12]) sconst_nxt = 16'hffff;
else sconst_nxt = 16'h0000;
end
//
// 4.7) DESTINATION ADDRESSING MODES
//-----------------------------------
// Destination addressing modes are encoded in a one hot fashion as following:
//
// 8'b00000001: Register direct.
// 8'b00000010: Register indexed.
// 8'b00010000: Symbolic (operand is in memory at address PC+x).
// 8'b01000000: Absolute (operand is in memory at address x).
reg [7:0] inst_ad_nxt;
wire [3:0] dest_reg = ir[3:0];
always @(dest_reg or ir or inst_type_nxt)
begin
if (~inst_type_nxt[`INST_TO])
inst_ad_nxt = 8'b00000000;
else if (dest_reg==4'h2) // Addressing mode using R2
case (ir[7])
1'b1 : inst_ad_nxt = 8'b01000000;
default: inst_ad_nxt = 8'b00000001;
endcase
else if (dest_reg==4'h0) // Addressing mode using R0
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00010000;
default: inst_ad_nxt = 8'b00000001;
endcase
else // General Addressing mode
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00000010;
default: inst_ad_nxt = 8'b00000001;
endcase
end
reg [7:0] inst_ad;
always @(posedge mclk or posedge puc)
if (puc) inst_ad <= 8'h00;
else if (decode) inst_ad <= inst_ad_nxt;
//
// 4.8) REMAINING INSTRUCTION DECODING
//-------------------------------------
// Operation size
reg inst_bw;
always @(posedge mclk or posedge puc)
if (puc) inst_bw <= 1'b0;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~dbg_halt_cmd;
// Extended instruction size
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
always @(posedge mclk or posedge puc)
if (puc) inst_sz <= 2'b00;
else if (decode) inst_sz <= inst_sz_nxt;
//=============================================================================
// 5) EXECUTION-UNIT STATE MACHINE
//=============================================================================
// State machine registers
reg [3:0] e_state;
// State machine control signals
//--------------------------------
wire src_acalc_pre = inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS];
wire src_rd_pre = inst_as_nxt[`INDIR] | inst_as_nxt[`INDIR_I] | inst_as_nxt[`IMM] | inst_so_nxt[`RETI];
wire dst_acalc_pre = inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS];
wire dst_acalc = inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS];
wire dst_rd_pre = inst_ad_nxt[`IDX] | inst_so_nxt[`PUSH] | inst_so_nxt[`CALL] | inst_so_nxt[`RETI];
wire dst_rd = inst_ad[`IDX] | inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI];
wire inst_branch = (inst_ad_nxt[`DIR] & (ir[3:0]==4'h0)) | inst_type_nxt[`INST_JMP] | inst_so_nxt[`RETI];
reg exec_jmp;
always @(posedge mclk or posedge puc)
if (puc) exec_jmp <= 1'b0;
else if (inst_branch & decode) exec_jmp <= 1'b1;
else if (e_state==`E_JUMP) exec_jmp <= 1'b0;
reg exec_dst_wr;
always @(posedge mclk or posedge puc)
if (puc) exec_dst_wr <= 1'b0;
else if (e_state==`E_DST_RD) exec_dst_wr <= 1'b1;
else if (e_state==`E_DST_WR) exec_dst_wr <= 1'b0;
reg exec_src_wr;
always @(posedge mclk or posedge puc)
if (puc) exec_src_wr <= 1'b0;
else if (inst_type[`INST_SO] & (e_state==`E_SRC_RD)) exec_src_wr <= 1'b1;
else if ((e_state==`E_SRC_WR) || (e_state==`E_DST_WR)) exec_src_wr <= 1'b0;
reg exec_dext_rdy;
always @(posedge mclk or posedge puc)
if (puc) exec_dext_rdy <= 1'b0;
else if (e_state==`E_DST_RD) exec_dext_rdy <= 1'b0;
else if (inst_dext_rdy) exec_dext_rdy <= 1'b1;
// Execution first state
//wire [3:0] e_first_state = dbg_halt_cmd ? `E_IDLE :
wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 :
dbg_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
cpuoff ? `E_IDLE :
src_acalc_pre ? `E_SRC_AD :
src_rd_pre ? `E_SRC_RD :
dst_acalc_pre ? `E_DST_AD :
dst_rd_pre ? `E_DST_RD : `E_EXEC;
// State machine
//--------------------------------
// States Transitions
always @(e_state or dst_acalc or dst_rd or inst_sext_rdy or
inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr or
e_first_state or exec_src_wr)
case(e_state)
`E_IDLE : e_state_nxt = e_first_state;
`E_IRQ_0 : e_state_nxt = `E_IRQ_1;
`E_IRQ_1 : e_state_nxt = `E_IRQ_2;
`E_IRQ_2 : e_state_nxt = `E_IRQ_3;
`E_IRQ_3 : e_state_nxt = `E_IRQ_4;
`E_IRQ_4 : e_state_nxt = `E_EXEC;
`E_SRC_AD : e_state_nxt = inst_sext_rdy ? `E_SRC_RD : `E_SRC_AD;
`E_SRC_RD : e_state_nxt = dst_acalc ? `E_DST_AD :
dst_rd ? `E_DST_RD : `E_EXEC;
`E_DST_AD : e_state_nxt = (inst_dext_rdy |
exec_dext_rdy) ? `E_DST_RD : `E_DST_AD;
`E_DST_RD : e_state_nxt = `E_EXEC;
`E_EXEC : e_state_nxt = exec_dst_wr ? `E_DST_WR :
exec_jmp ? `E_JUMP :
exec_src_wr ? `E_SRC_WR : e_first_state;
`E_JUMP : e_state_nxt = e_first_state;
`E_DST_WR : e_state_nxt = exec_jmp ? `E_JUMP : e_first_state;
`E_SRC_WR : e_state_nxt = e_first_state;
default : e_state_nxt = `E_IRQ_0;
endcase
// State machine
always @(posedge mclk or posedge puc)
if (puc) e_state <= `E_IRQ_1;
else e_state <= e_state_nxt;
// Frontend State machine control signals
//----------------------------------------
wire exec_done = exec_jmp ? (e_state==`E_JUMP) :
exec_dst_wr ? (e_state==`E_DST_WR) :
exec_src_wr ? (e_state==`E_SRC_WR) : (e_state==`E_EXEC);
//=============================================================================
// 6) EXECUTION-UNIT STATE CONTROL
//=============================================================================
//
// 6.1) ALU CONTROL SIGNALS
//-------------------------------------
//
// 12'b000000000001: Enable ALU source inverter
// 12'b000000000010: Enable Incrementer
// 12'b000000000100: Enable Incrementer on carry bit
// 12'b000000001000: Select Adder
// 12'b000000010000: Select AND
// 12'b000000100000: Select OR
// 12'b000001000000: Select XOR
// 12'b000010000000: Select DADD
// 12'b000100000000: Update N, Z & C (C=~Z)
// 12'b001000000000: Update all status bits
// 12'b010000000000: Update status bit for XOR instruction
// 12'b100000000000: Don't write to destination
reg [11:0] inst_alu;
wire alu_src_inv = inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_to_nxt[`BIC] ;
wire alu_inc = inst_to_nxt[`SUB] | inst_to_nxt[`CMP];
wire alu_inc_c = inst_to_nxt[`ADDC] | inst_to_nxt[`DADD] |
inst_to_nxt[`SUBC];
wire alu_add = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] |
inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_type_nxt[`INST_JMP] |
inst_so_nxt[`RETI];
wire alu_and = inst_to_nxt[`AND] | inst_to_nxt[`BIC] |
inst_to_nxt[`BIT];
wire alu_or = inst_to_nxt[`BIS];
wire alu_xor = inst_to_nxt[`XOR];
wire alu_dadd = inst_to_nxt[`DADD];
wire alu_stat_7 = inst_to_nxt[`BIT] | inst_to_nxt[`AND] |
inst_so_nxt[`SXT];
wire alu_stat_f = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] |
inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_to_nxt[`DADD] |
inst_to_nxt[`BIT] | inst_to_nxt[`XOR] |
inst_to_nxt[`AND] |
inst_so_nxt[`RRC] | inst_so_nxt[`RRA] |
inst_so_nxt[`SXT];
wire alu_shift = inst_so_nxt[`RRC] | inst_so_nxt[`RRA];
wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT];
always @(posedge mclk or posedge puc)
if (puc) inst_alu <= 12'h000;
else if (decode) inst_alu <= {exec_no_wr,
alu_shift,
alu_stat_f,
alu_stat_7,
alu_dadd,
alu_xor,
alu_or,
alu_and,
alu_add,
alu_inc_c,
alu_inc,
alu_src_inv};
endmodule // omsp_frontend
`include "openMSP430_undefines.v"
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_pipe_ctrl
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_LOAD_BYPASS = 1
,parameter SUPPORT_MUL_BYPASS = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i
,input rst_i
// Issue
,input issue_valid_i
,input issue_accept_i
,input issue_stall_i
,input issue_lsu_i
,input issue_csr_i
,input issue_div_i
,input issue_mul_i
,input issue_branch_i
,input issue_rd_valid_i
,input [4:0] issue_rd_i
,input [5:0] issue_exception_i
,input take_interrupt_i
,input issue_branch_taken_i
,input [31:0] issue_branch_target_i
,input [31:0] issue_pc_i
,input [31:0] issue_opcode_i
,input [31:0] issue_operand_ra_i
,input [31:0] issue_operand_rb_i
// Execution stage 1: ALU result
,input [31:0] alu_result_e1_i
// Execution stage 1: CSR read result / early exceptions
,input [ 31:0] csr_result_value_e1_i
,input csr_result_write_e1_i
,input [ 31:0] csr_result_wdata_e1_i
,input [ 5:0] csr_result_exception_e1_i
// Execution stage 1
,output load_e1_o
,output store_e1_o
,output mul_e1_o
,output branch_e1_o
,output [ 4:0] rd_e1_o
,output [31:0] pc_e1_o
,output [31:0] opcode_e1_o
,output [31:0] operand_ra_e1_o
,output [31:0] operand_rb_e1_o
// Execution stage 2: Other results
,input mem_complete_i
,input [31:0] mem_result_e2_i
,input [5:0] mem_exception_e2_i
,input [31:0] mul_result_e2_i
// Execution stage 2
,output load_e2_o
,output mul_e2_o
,output [ 4:0] rd_e2_o
,output [31:0] result_e2_o
// Out of pipe: Divide Result
,input div_complete_i
,input [31:0] div_result_i
// Commit
,output valid_wb_o
,output csr_wb_o
,output [ 4:0] rd_wb_o
,output [31:0] result_wb_o
,output [31:0] pc_wb_o
,output [31:0] opcode_wb_o
,output [31:0] operand_ra_wb_o
,output [31:0] operand_rb_wb_o
,output [5:0] exception_wb_o
,output csr_write_wb_o
,output [11:0] csr_waddr_wb_o
,output [31:0] csr_wdata_wb_o
,output stall_o
,output squash_e1_e2_o
,input squash_e1_e2_i
,input squash_wb_i
);
//-------------------------------------------------------------
// Includes
//-------------------------------------------------------------
`include "riscv_defs.v"
wire squash_e1_e2_w;
wire branch_misaligned_w = (issue_branch_taken_i && issue_branch_target_i[1:0] != 2'b0);
//-------------------------------------------------------------
// E1 / Address
//-------------------------------------------------------------
`define PCINFO_W 10
`define PCINFO_ALU 0
`define PCINFO_LOAD 1
`define PCINFO_STORE 2
`define PCINFO_CSR 3
`define PCINFO_DIV 4
`define PCINFO_MUL 5
`define PCINFO_BRANCH 6
`define PCINFO_RD_VALID 7
`define PCINFO_INTR 8
`define PCINFO_COMPLETE 9
`define RD_IDX_R 11:7
reg valid_e1_q;
reg [`PCINFO_W-1:0] ctrl_e1_q;
reg [31:0] pc_e1_q;
reg [31:0] npc_e1_q;
reg [31:0] opcode_e1_q;
reg [31:0] operand_ra_e1_q;
reg [31:0] operand_rb_e1_q;
reg [`EXCEPTION_W-1:0] exception_e1_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_e1_q <= 1'b0;
ctrl_e1_q <= `PCINFO_W'b0;
pc_e1_q <= 32'b0;
npc_e1_q <= 32'b0;
opcode_e1_q <= 32'b0;
operand_ra_e1_q <= 32'b0;
operand_rb_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
// Stall - no change in E1 state
else if (issue_stall_i)
;
else if ((issue_valid_i && issue_accept_i) && ~(squash_e1_e2_o || squash_e1_e2_i))
begin
valid_e1_q <= 1'b1;
ctrl_e1_q[`PCINFO_ALU] <= ~(issue_lsu_i | issue_csr_i | issue_div_i | issue_mul_i);
ctrl_e1_q[`PCINFO_LOAD] <= issue_lsu_i & issue_rd_valid_i & ~take_interrupt_i; // TODO: Check
ctrl_e1_q[`PCINFO_STORE] <= issue_lsu_i & ~issue_rd_valid_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_CSR] <= issue_csr_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_DIV] <= issue_div_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_MUL] <= issue_mul_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_BRANCH] <= issue_branch_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_RD_VALID] <= issue_rd_valid_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_INTR] <= take_interrupt_i;
ctrl_e1_q[`PCINFO_COMPLETE] <= 1'b1;
pc_e1_q <= issue_pc_i;
npc_e1_q <= issue_branch_taken_i ? issue_branch_target_i : issue_pc_i + 32'd4;
opcode_e1_q <= issue_opcode_i;
operand_ra_e1_q <= issue_operand_ra_i;
operand_rb_e1_q <= issue_operand_rb_i;
exception_e1_q <= (|issue_exception_i) ? issue_exception_i :
branch_misaligned_w ? `EXCEPTION_MISALIGNED_FETCH : `EXCEPTION_W'b0;
end
// No valid instruction (or pipeline flush event)
else
begin
valid_e1_q <= 1'b0;
ctrl_e1_q <= `PCINFO_W'b0;
pc_e1_q <= 32'b0;
npc_e1_q <= 32'b0;
opcode_e1_q <= 32'b0;
operand_ra_e1_q <= 32'b0;
operand_rb_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
wire alu_e1_w = ctrl_e1_q[`PCINFO_ALU];
assign load_e1_o = ctrl_e1_q[`PCINFO_LOAD];
assign store_e1_o = ctrl_e1_q[`PCINFO_STORE];
wire csr_e1_w = ctrl_e1_q[`PCINFO_CSR];
wire div_e1_w = ctrl_e1_q[`PCINFO_DIV];
assign mul_e1_o = ctrl_e1_q[`PCINFO_MUL];
assign branch_e1_o = ctrl_e1_q[`PCINFO_BRANCH];
assign rd_e1_o = {5{ctrl_e1_q[`PCINFO_RD_VALID]}} & opcode_e1_q[`RD_IDX_R];
assign pc_e1_o = pc_e1_q;
assign opcode_e1_o = opcode_e1_q;
assign operand_ra_e1_o = operand_ra_e1_q;
assign operand_rb_e1_o = operand_rb_e1_q;
//-------------------------------------------------------------
// E2 / Mem result
//-------------------------------------------------------------
reg valid_e2_q;
reg [`PCINFO_W-1:0] ctrl_e2_q;
reg csr_wr_e2_q;
reg [31:0] csr_wdata_e2_q;
reg [31:0] result_e2_q;
reg [31:0] pc_e2_q;
reg [31:0] npc_e2_q;
reg [31:0] opcode_e2_q;
reg [31:0] operand_ra_e2_q;
reg [31:0] operand_rb_e2_q;
reg [`EXCEPTION_W-1:0] exception_e2_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_e2_q <= 1'b0;
ctrl_e2_q <= `PCINFO_W'b0;
csr_wr_e2_q <= 1'b0;
csr_wdata_e2_q <= 32'b0;
pc_e2_q <= 32'b0;
npc_e2_q <= 32'b0;
opcode_e2_q <= 32'b0;
operand_ra_e2_q <= 32'b0;
operand_rb_e2_q <= 32'b0;
result_e2_q <= 32'b0;
exception_e2_q <= `EXCEPTION_W'b0;
end
// Stall - no change in E2 state
else if (issue_stall_i)
;
// Pipeline flush
else if (squash_e1_e2_o || squash_e1_e2_i)
begin
valid_e2_q <= 1'b0;
ctrl_e2_q <= `PCINFO_W'b0;
csr_wr_e2_q <= 1'b0;
csr_wdata_e2_q <= 32'b0;
pc_e2_q <= 32'b0;
npc_e2_q <= 32'b0;
opcode_e2_q <= 32'b0;
operand_ra_e2_q <= 32'b0;
operand_rb_e2_q <= 32'b0;
result_e2_q <= 32'b0;
exception_e2_q <= `EXCEPTION_W'b0;
end
// Normal pipeline advance
else
begin
valid_e2_q <= valid_e1_q;
ctrl_e2_q <= ctrl_e1_q;
csr_wr_e2_q <= csr_result_write_e1_i;
csr_wdata_e2_q <= csr_result_wdata_e1_i;
pc_e2_q <= pc_e1_q;
npc_e2_q <= npc_e1_q;
opcode_e2_q <= opcode_e1_q;
operand_ra_e2_q <= operand_ra_e1_q;
operand_rb_e2_q <= operand_rb_e1_q;
// Launch interrupt
if (ctrl_e1_q[`PCINFO_INTR])
exception_e2_q <= `EXCEPTION_INTERRUPT;
// If frontend reports bad instruction, ignore later CSR errors...
else if (|exception_e1_q)
begin
valid_e2_q <= 1'b0;
exception_e2_q <= exception_e1_q;
end
else
exception_e2_q <= csr_result_exception_e1_i;
if (ctrl_e1_q[`PCINFO_DIV])
result_e2_q <= div_result_i;
else if (ctrl_e1_q[`PCINFO_CSR])
result_e2_q <= csr_result_value_e1_i;
else
result_e2_q <= alu_result_e1_i;
end
reg [31:0] result_e2_r;
wire valid_e2_w = valid_e2_q & ~issue_stall_i;
always @ *
begin
// Default: ALU result
result_e2_r = result_e2_q;
if (SUPPORT_LOAD_BYPASS && valid_e2_w && (ctrl_e2_q[`PCINFO_LOAD] || ctrl_e2_q[`PCINFO_STORE]))
result_e2_r = mem_result_e2_i;
else if (SUPPORT_MUL_BYPASS && valid_e2_w && ctrl_e2_q[`PCINFO_MUL])
result_e2_r = mul_result_e2_i;
end
wire load_store_e2_w = ctrl_e2_q[`PCINFO_LOAD] | ctrl_e2_q[`PCINFO_STORE];
assign load_e2_o = ctrl_e2_q[`PCINFO_LOAD];
assign mul_e2_o = ctrl_e2_q[`PCINFO_MUL];
assign rd_e2_o = {5{(valid_e2_w && ctrl_e2_q[`PCINFO_RD_VALID] && ~stall_o)}} & opcode_e2_q[`RD_IDX_R];
assign result_e2_o = result_e2_r;
// Load store result not ready when reaching E2
assign stall_o = (ctrl_e1_q[`PCINFO_DIV] && ~div_complete_i) || ((ctrl_e2_q[`PCINFO_LOAD] | ctrl_e2_q[`PCINFO_STORE]) & ~mem_complete_i);
reg [`EXCEPTION_W-1:0] exception_e2_r;
always @ *
begin
if (valid_e2_q && (ctrl_e2_q[`PCINFO_LOAD] || ctrl_e2_q[`PCINFO_STORE]) && mem_complete_i)
exception_e2_r = mem_exception_e2_i;
else
exception_e2_r = exception_e2_q;
end
assign squash_e1_e2_w = |exception_e2_r;
reg squash_e1_e2_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
squash_e1_e2_q <= 1'b0;
else if (~issue_stall_i)
squash_e1_e2_q <= squash_e1_e2_w;
assign squash_e1_e2_o = squash_e1_e2_w | squash_e1_e2_q;
//-------------------------------------------------------------
// Writeback / Commit
//-------------------------------------------------------------
reg valid_wb_q;
reg [`PCINFO_W-1:0] ctrl_wb_q;
reg csr_wr_wb_q;
reg [31:0] csr_wdata_wb_q;
reg [31:0] result_wb_q;
reg [31:0] pc_wb_q;
reg [31:0] npc_wb_q;
reg [31:0] opcode_wb_q;
reg [31:0] operand_ra_wb_q;
reg [31:0] operand_rb_wb_q;
reg [`EXCEPTION_W-1:0] exception_wb_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_wb_q <= 1'b0;
ctrl_wb_q <= `PCINFO_W'b0;
csr_wr_wb_q <= 1'b0;
csr_wdata_wb_q <= 32'b0;
pc_wb_q <= 32'b0;
npc_wb_q <= 32'b0;
opcode_wb_q <= 32'b0;
operand_ra_wb_q <= 32'b0;
operand_rb_wb_q <= 32'b0;
result_wb_q <= 32'b0;
exception_wb_q <= `EXCEPTION_W'b0;
end
// Stall - no change in WB state
else if (issue_stall_i)
;
else if (squash_wb_i)
begin
valid_wb_q <= 1'b0;
ctrl_wb_q <= `PCINFO_W'b0;
csr_wr_wb_q <= 1'b0;
csr_wdata_wb_q <= 32'b0;
pc_wb_q <= 32'b0;
npc_wb_q <= 32'b0;
opcode_wb_q <= 32'b0;
operand_ra_wb_q <= 32'b0;
operand_rb_wb_q <= 32'b0;
result_wb_q <= 32'b0;
exception_wb_q <= `EXCEPTION_W'b0;
end
else
begin
// Squash instruction valid on memory faults
case (exception_e2_r)
`EXCEPTION_MISALIGNED_LOAD,
`EXCEPTION_FAULT_LOAD,
`EXCEPTION_MISALIGNED_STORE,
`EXCEPTION_FAULT_STORE,
`EXCEPTION_PAGE_FAULT_LOAD,
`EXCEPTION_PAGE_FAULT_STORE:
valid_wb_q <= 1'b0;
default:
valid_wb_q <= valid_e2_q;
endcase
csr_wr_wb_q <= csr_wr_e2_q; // TODO: Fault disable???
csr_wdata_wb_q <= csr_wdata_e2_q;
// Exception - squash writeback
if (|exception_e2_r)
ctrl_wb_q <= ctrl_e2_q & ~(1 << `PCINFO_RD_VALID);
else
ctrl_wb_q <= ctrl_e2_q;
pc_wb_q <= pc_e2_q;
npc_wb_q <= npc_e2_q;
opcode_wb_q <= opcode_e2_q;
operand_ra_wb_q <= operand_ra_e2_q;
operand_rb_wb_q <= operand_rb_e2_q;
exception_wb_q <= exception_e2_r;
if (valid_e2_w && (ctrl_e2_q[`PCINFO_LOAD] || ctrl_e2_q[`PCINFO_STORE]))
result_wb_q <= mem_result_e2_i;
else if (valid_e2_w && ctrl_e2_q[`PCINFO_MUL])
result_wb_q <= mul_result_e2_i;
else
result_wb_q <= result_e2_q;
end
// Instruction completion (for debug)
wire complete_wb_w = ctrl_wb_q[`PCINFO_COMPLETE] & ~issue_stall_i;
assign valid_wb_o = valid_wb_q & ~issue_stall_i;
assign csr_wb_o = ctrl_wb_q[`PCINFO_CSR] & ~issue_stall_i; // TODO: Fault disable???
assign rd_wb_o = {5{(valid_wb_o && ctrl_wb_q[`PCINFO_RD_VALID] && ~stall_o)}} & opcode_wb_q[`RD_IDX_R];
assign result_wb_o = result_wb_q;
assign pc_wb_o = pc_wb_q;
assign opcode_wb_o = opcode_wb_q;
assign operand_ra_wb_o = operand_ra_wb_q;
assign operand_rb_wb_o = operand_rb_wb_q;
assign exception_wb_o = exception_wb_q;
assign csr_write_wb_o = csr_wr_wb_q;
assign csr_waddr_wb_o = opcode_wb_q[31:20];
assign csr_wdata_wb_o = csr_wdata_wb_q;
`ifdef verilator
riscv_trace_sim
u_trace_d
(
.valid_i(issue_valid_i)
,.pc_i(issue_pc_i)
,.opcode_i(issue_opcode_i)
);
riscv_trace_sim
u_trace_wb
(
.valid_i(valid_wb_o)
,.pc_i(pc_wb_o)
,.opcode_i(opcode_wb_o)
);
`endif
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_2_V
`define SKY130_FD_SC_HDLL__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_SYMBOL_V
`define SKY130_FD_SC_HS__NOR2_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_SYMBOL_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module daala_zynq_auto_pc_121 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* si570_i2c_init
*/
module si570_i2c_init (
input wire clk,
input wire rst,
/*
* I2C master interface
*/
output wire [6:0] cmd_address,
output wire cmd_start,
output wire cmd_read,
output wire cmd_write,
output wire cmd_write_multiple,
output wire cmd_stop,
output wire cmd_valid,
input wire cmd_ready,
output wire [7:0] data_out,
output wire data_out_valid,
input wire data_out_ready,
output wire data_out_last,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire start
);
/*
Generic module for I2C bus initialization. Good for use when multiple devices
on an I2C bus must be initialized on system start without intervention of a
general-purpose processor.
Copy this file and change init_data and INIT_DATA_LEN as needed.
This module can be used in two modes: simple device initalization, or multiple
device initialization. In multiple device mode, the same initialization sequence
can be performed on multiple different device addresses.
To use single device mode, only use the start write to address and write data commands.
The module will generate the I2C commands in sequential order. Terminate the list
with a 0 entry.
To use the multiple device mode, use the start data and start address block commands
to set up lists of initialization data and device addresses. The module enters
multiple device mode upon seeing a start data block command. The module stores the
offset of the start of the data block and then skips ahead until it reaches a start
address block command. The module will store the offset to the address block and
read the first address in the block. Then it will jump back to the data block
and execute it, substituting the stored address for each current address write
command. Upon reaching the start address block command, the module will read out the
next address and start again at the top of the data block. If the module encounters
a start data block command while looking for an address, then it will store a new data
offset and then look for a start address block command. Terminate the list with a 0
entry. Normal address commands will operate normally inside a data block.
Commands:
00 0000000 : stop
00 0000001 : exit multiple device mode
00 0000011 : start write to current address
00 0001000 : start address block
00 0001001 : start data block
01 aaaaaaa : start write to address
1 dddddddd : write 8-bit data
Examples
write 0x11223344 to register 0x0004 on device at 0x50
01 1010000 start write to 0x50
1 00000000 write address 0x0004
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
0 00000000 stop
write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
00 0001001 start data block
00 0000011 start write to current address
1 00000000 write address 0x0004
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
00 0001000 start address block
01 1010000 address 0x50
01 1010001 address 0x51
01 1010010 address 0x52
01 1010011 address 0x53
00 0000000 stop
*/
// init_data ROM
localparam INIT_DATA_LEN = 18;
reg [8:0] init_data [INIT_DATA_LEN-1:0];
initial begin
// Set Si570 to generate 644.53125 MHz
init_data[0] = {2'b01, 7'h00}; // start write to address 0x00
init_data[1] = {1'b1, 8'd137}; // write address 137
init_data[2] = {1'b1, 8'h10}; // write data 0x10 (freeze DCO)
init_data[3] = {2'b01, 7'h00}; // start write to address 0x00
init_data[4] = {1'b1, 8'd7}; // write address 7
init_data[5] = {1'b1, {3'b000, 5'b000000}}; // write data (address 7) (HS_DIV = 3'b000)
init_data[6] = {1'b1, {2'b01, 6'h2}}; // write data (address 8) (N1 = 7'b000001)
init_data[7] = {1'b1, 8'hD1}; // write data (address 9)
init_data[8] = {1'b1, 8'hE1}; // write data (address 10)
init_data[9] = {1'b1, 8'h27}; // write data (address 11)
init_data[10] = {1'b1, 8'hAF}; // write data (address 12) (RFREQ = 38'h2D1E127AF)
init_data[11] = {2'b01, 7'h00}; // start write to address 0x00
init_data[12] = {1'b1, 8'd137}; // write address 137
init_data[13] = {1'b1, 8'h00}; // write data 0x00 (un-freeze DCO)
init_data[14] = {2'b01, 7'h00}; // start write to address 0x00
init_data[15] = {1'b1, 8'd135}; // write address 135
init_data[16] = {1'b1, 8'h40}; // write data 0x40 (new frequency applied)
init_data[17] = 9'd0; // stop
end
localparam [3:0]
STATE_IDLE = 3'd0,
STATE_RUN = 3'd1,
STATE_TABLE_1 = 3'd2,
STATE_TABLE_2 = 3'd3,
STATE_TABLE_3 = 3'd4;
reg [4:0] state_reg = STATE_IDLE, state_next;
parameter AW = $clog2(INIT_DATA_LEN);
reg [8:0] init_data_reg = 9'd0;
reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;
reg [6:0] cur_address_reg = 7'd0, cur_address_next;
reg [6:0] cmd_address_reg = 7'd0, cmd_address_next;
reg cmd_start_reg = 1'b0, cmd_start_next;
reg cmd_write_reg = 1'b0, cmd_write_next;
reg cmd_stop_reg = 1'b0, cmd_stop_next;
reg cmd_valid_reg = 1'b0, cmd_valid_next;
reg [7:0] data_out_reg = 8'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;
reg start_flag_reg = 1'b0, start_flag_next;
reg busy_reg = 1'b0;
assign cmd_address = cmd_address_reg;
assign cmd_start = cmd_start_reg;
assign cmd_read = 1'b0;
assign cmd_write = cmd_write_reg;
assign cmd_write_multiple = 1'b0;
assign cmd_stop = cmd_stop_reg;
assign cmd_valid = cmd_valid_reg;
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign data_out_last = 1'b1;
assign busy = busy_reg;
always @* begin
state_next = STATE_IDLE;
address_next = address_reg;
address_ptr_next = address_ptr_reg;
data_ptr_next = data_ptr_reg;
cur_address_next = cur_address_reg;
cmd_address_next = cmd_address_reg;
cmd_start_next = cmd_start_reg & ~(cmd_valid & cmd_ready);
cmd_write_next = cmd_write_reg & ~(cmd_valid & cmd_ready);
cmd_stop_next = cmd_stop_reg & ~(cmd_valid & cmd_ready);
cmd_valid_next = cmd_valid_reg & ~cmd_ready;
data_out_next = data_out_reg;
data_out_valid_next = data_out_valid_reg & ~data_out_ready;
start_flag_next = start_flag_reg;
if (cmd_valid | data_out_valid) begin
// wait for output registers to clear
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// wait for start signal
if (~start_flag_reg & start) begin
address_next = {AW{1'b0}};
start_flag_next = 1'b1;
state_next = STATE_RUN;
end else begin
state_next = STATE_IDLE;
end
end
STATE_RUN: begin
// process commands
if (init_data_reg[8] == 1'b1) begin
// write data
cmd_write_next = 1'b1;
cmd_stop_next = 1'b0;
cmd_valid_next = 1'b1;
data_out_next = init_data_reg[7:0];
data_out_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
cmd_address_next = init_data_reg[6:0];
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_RUN;
end
end
STATE_TABLE_1: begin
// find address table start
if (init_data_reg == 9'b000001000) begin
// address table start
address_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end
end
STATE_TABLE_2: begin
// find next address
if (init_data_reg[8:7] == 2'b01) begin
// write address command
// store address and move to data table
cur_address_next = init_data_reg[6:0];
address_ptr_next = address_reg + 1;
address_next = data_ptr_reg;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end
end
STATE_TABLE_3: begin
// process data table with selected address
if (init_data_reg[8] == 1'b1) begin
// write data
cmd_write_next = 1'b1;
cmd_stop_next = 1'b0;
cmd_valid_next = 1'b1;
data_out_next = init_data_reg[7:0];
data_out_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
cmd_address_next = init_data_reg[6:0];
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000000011) begin
// write current address
cmd_address_next = cur_address_reg;
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'b000001000) begin
// address table start
address_next = address_ptr_reg;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
init_data_reg <= 9'd0;
address_reg <= {AW{1'b0}};
address_ptr_reg <= {AW{1'b0}};
data_ptr_reg <= {AW{1'b0}};
cur_address_reg <= 7'd0;
cmd_valid_reg <= 1'b0;
data_out_valid_reg <= 1'b0;
start_flag_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
// read init_data ROM
init_data_reg <= init_data[address_next];
address_reg <= address_next;
address_ptr_reg <= address_ptr_next;
data_ptr_reg <= data_ptr_next;
cur_address_reg <= cur_address_next;
cmd_valid_reg <= cmd_valid_next;
data_out_valid_reg <= data_out_valid_next;
start_flag_reg <= start & start_flag_next;
busy_reg <= (state_reg != STATE_IDLE);
end
cmd_address_reg <= cmd_address_next;
cmd_start_reg <= cmd_start_next;
cmd_write_reg <= cmd_write_next;
cmd_stop_reg <= cmd_stop_next;
data_out_reg <= data_out_next;
end
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_LS__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module cf_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
up_pn_type);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input up_pn_type;
reg adc_pn_type_m1 = 'd0;
reg adc_pn_type_m2 = 'd0;
reg adc_pn_type = 'd0;
reg adc_pn_en = 'd0;
reg [15:0] adc_data_d = 'd0;
reg [31:0] adc_pn_data = 'd0;
reg adc_pn_en_d = 'd0;
reg adc_pn_match = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
reg [ 4:0] adc_pn_err_count = 'd0;
reg adc_pn_err = 'd0;
wire [31:0] adc_pn_data_in_s;
wire adc_pn_match0_s;
wire adc_pn_match1_s;
wire adc_pn_match2_s;
wire adc_pn_match_s;
wire [31:0] adc_pn_data_s;
wire adc_pn_err_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// This PN sequence checking algorithm is commonly used is most applications.
// It is a simple function generated based on the OOS status.
// If OOS is asserted (PN is OUT of sync):
// The next sequence is generated from the incoming data.
// If 16 sequences match CONSECUTIVELY, OOS is cleared (de-asserted).
// If OOS is de-asserted (PN is IN sync)
// The next sequence is generated from the current sequence.
// If 64 sequences mismatch CONSECUTIVELY, OOS is set (asserted).
// If OOS is de-asserted, any spurious mismatches sets the ERROR register.
// Ideally, processor should make sure both OOS == 0x0 AND ERR == 0x0.
assign adc_pn_data_in_s[31:16] = {~adc_data_d[15], adc_data_d[14:0]};
assign adc_pn_data_in_s[15:0] = {~adc_data[15], adc_data[14:0]};
assign adc_pn_match0_s = (adc_pn_data_in_s[31:16] == adc_pn_data[31:16]) ? 1'b1 : 1'b0;
assign adc_pn_match1_s = (adc_pn_data_in_s[15:0] == adc_pn_data[15:0]) ? 1'b1 : 1'b0;
assign adc_pn_match2_s = ((adc_data == 16'd0) && (adc_data_d == 16'd0)) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match0_s & adc_pn_match1_s & adc_pn_match2_s;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match);
// PN running sequence
always @(posedge adc_clk) begin
adc_pn_type_m1 <= up_pn_type;
adc_pn_type_m2 <= adc_pn_type_m1;
adc_pn_type <= adc_pn_type_m2;
adc_pn_en <= ~adc_pn_en;
adc_data_d <= adc_data;
if (adc_pn_en == 1'b1) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
end
// PN OOS and counters (16 to clear, 64 to set). These numbers are actually determined
// based on BER parameters set by the system (usually in network applications).
always @(posedge adc_clk) begin
adc_pn_en_d <= adc_pn_en;
adc_pn_match <= adc_pn_match_s;
if (adc_pn_en_d == 1'b1) begin
if (adc_pn_oos == 1'b1) begin
if (adc_pn_match == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd0;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= 'd1;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd1;
end
end else begin
if (adc_pn_match == 1'b0) begin
if (adc_pn_oos_count >= 64) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd1;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= 'd0;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd0;
end
end
end
end
// The error state is streched to multiple adc clocks such that processor
// has enough time to sample the error condition.
always @(posedge adc_clk) begin
if (adc_pn_en_d == 1'b1) begin
if (adc_pn_err_s == 1'b1) begin
adc_pn_err_count <= 5'h10;
end else if (adc_pn_err_count[4] == 1'b1) begin
adc_pn_err_count <= adc_pn_err_count + 1'b1;
end
end
adc_pn_err <= adc_pn_err_count[4];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] crc;
integer fd;
integer fdtmp;
t_case_write1_tasks tasks ();
integer cyc; initial cyc=0;
always @ (posedge clk) begin
$fwrite(fd, "[%0d] crc=%x ", cyc, crc);
tasks.big_case(fd, crc[31:0]);
$fwrite(fd, "\n");
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==1) begin
crc <= 64'h00000000_00000097;
$write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"});
fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w");
fd <= fdtmp;
end
if (cyc==90) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp2(/*AUTOARG*/
// Outputs
scan_out, pcx_scache2_data_px_l,
// Inputs
shiftenable, scan_in, rclk, arbpc2_pcxdp_shift_px,
arbpc2_pcxdp_qsel1_pa, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_q0_hold_pa, arbpc2_pcxdp_grant_pa, spc0_pcx_data_pa,
spc1_pcx_data_pa, spc2_pcx_data_pa, spc3_pcx_data_pa,
spc4_pcx_data_pa, spc5_pcx_data_pa, spc6_pcx_data_pa,
spc7_pcx_data_pa
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] scan_out; // From mac0 of pcx_dp_maca_r.v, ...
// End of automatics
output [`PCX_WIDTH-1:0] pcx_scache2_data_px_l; // From mac4 of pcx_dp_macc.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] arbpc2_pcxdp_grant_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc2_pcxdp_q0_hold_pa;// To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc2_pcxdp_qsel0_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc2_pcxdp_qsel1_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc2_pcxdp_shift_px; // To mac0 of pcx_dp_maca_r.v, ...
input rclk; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] scan_in; // To mac0 of pcx_dp_maca_r.v, ...
input shiftenable; // To mac7 of pcx_dp_maca_l.v
// End of automatics
input [`PCX_WIDTH-1:0] spc0_pcx_data_pa; // To mac0 of pcx_dp_maca.v
input [`PCX_WIDTH-1:0] spc1_pcx_data_pa; // To mac1 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc2_pcx_data_pa; // To mac2 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc3_pcx_data_pa; // To mac3 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc4_pcx_data_pa; // To mac4 of pcx_dp_macc.v
input [`PCX_WIDTH-1:0] spc5_pcx_data_pa; // To mac5 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc6_pcx_data_pa; // To mac6 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc7_pcx_data_pa; // To mac7 of pcx_dp_maca.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [129:0] pcx_col0_data_px_l; // From mac0 of pcx_dp_maca_r.v
wire [129:0] pcx_col1_data_px_l; // From mac1 of pcx_dp_macb_r.v
wire [129:0] pcx_col2_data_px_l; // From mac2 of pcx_dp_macb_r.v
wire [129:0] pcx_col3_data_px_l; // From mac3 of pcx_dp_macb_r.v
wire [129:0] pcx_col5_data_px_l; // From mac5 of pcx_dp_macb_l.v
wire [129:0] pcx_col6_data_px_l; // From mac6 of pcx_dp_macb_l.v
wire [129:0] pcx_col7_data_px_l; // From mac7 of pcx_dp_maca_l.v
wire [7:1] shiftenable_buf; // From mac1 of pcx_dp_macb_r.v, ...
// End of automatics
wire [5:0] unused;
/*
// DATAPATH ORGANISATION(pcx_dp2)
sparc0 sparc1 sparc2 sparc3 sparc4 sparc5 sparc6 sparc7
| | | | | | | |
v v v v v v v v
mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 <- mac6 <- mac7
(new)ar br br br cl bl bl al
(old)a b b b b c b a
|
v
to sctag2
*/
/*
pcx_dp_maca_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_maca_r mac0(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col0_data_px_l[129:0]), // Templated
.scan_out (scan_out[0]), // Templated
.shiftenable_buf (), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[0]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[0]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[0]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[0]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[0]), // Templated
.src_pcx_data_pa ({6'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[0]), // Templated
.shiftenable (shiftenable_buf[1])); // Templated
/*
pcx_dp_macb_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(- @ 1)"_data_px_l[129:0]),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_r mac1(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col1_data_px_l[129:0]), // Templated
.scan_out (scan_out[1]), // Templated
.shiftenable_buf (shiftenable_buf[1]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[1]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[1]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[1]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[1]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[1]), // Templated
.src_pcx_data_pa ({6'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col0_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[1]), // Templated
.shiftenable (shiftenable_buf[2])); // Templated
pcx_dp_macb_r mac2(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col2_data_px_l[129:0]), // Templated
.scan_out (scan_out[2]), // Templated
.shiftenable_buf (shiftenable_buf[2]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[2]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[2]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[2]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[2]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[2]), // Templated
.src_pcx_data_pa ({6'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col1_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[2]), // Templated
.shiftenable (shiftenable_buf[3])); // Templated
pcx_dp_macb_r mac3(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col3_data_px_l[129:0]), // Templated
.scan_out (scan_out[3]), // Templated
.shiftenable_buf (shiftenable_buf[3]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[3]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[3]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[3]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[3]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[3]), // Templated
.src_pcx_data_pa ({6'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col2_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[3]), // Templated
.shiftenable (shiftenable_buf[4])); // Templated
/*
pcx_dp_macc_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l ({unused[5:0],pcx_scache2_data_px_l[`PCX_WIDTH-1:0]}),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_crit_px_l (pcx_col@"(- @ 1)"_data_px_l[129:0]),
.data_ncrit_px_l(pcx_col@"(+ @ 1)"_data_px_l[129:0]),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macc_l mac4(/*AUTOINST*/
// Outputs
.data_out_px_l ({unused[5:0],pcx_scache2_data_px_l[`PCX_WIDTH-1:0]}), // Templated
.scan_out (scan_out[4]), // Templated
.shiftenable_buf (shiftenable_buf[4]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[4]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[4]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[4]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[4]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[4]), // Templated
.src_pcx_data_pa ({6'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_crit_px_l (pcx_col3_data_px_l[129:0]), // Templated
.data_ncrit_px_l (pcx_col5_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[4]), // Templated
.shiftenable (shiftenable_buf[5])); // Templated
/*
pcx_dp_macb_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(+ @ 1)"_data_px_l[129:0]),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_l mac5(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col5_data_px_l[129:0]), // Templated
.scan_out (scan_out[5]), // Templated
.shiftenable_buf (shiftenable_buf[5]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[5]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[5]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[5]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[5]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[5]), // Templated
.src_pcx_data_pa ({6'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col6_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[5]), // Templated
.shiftenable (shiftenable_buf[6])); // Templated
pcx_dp_macb_l mac6(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col6_data_px_l[129:0]), // Templated
.scan_out (scan_out[6]), // Templated
.shiftenable_buf (shiftenable_buf[6]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[6]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[6]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[6]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[6]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[6]), // Templated
.src_pcx_data_pa ({6'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col7_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[6]), // Templated
.shiftenable (shiftenable_buf[7])); // Templated
/*
pcx_dp_maca_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable));
*/
pcx_dp_maca_l mac7(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col7_data_px_l[129:0]), // Templated
.scan_out (scan_out[7]), // Templated
.shiftenable_buf (shiftenable_buf[7]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7]), // Templated
.arb_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7]), // Templated
.arb_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7]), // Templated
.arb_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7]), // Templated
.src_pcx_data_pa ({6'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[7]), // Templated
.shiftenable (shiftenable)); // Templated
// Code start here
//
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
endmodule
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Aug 23 2017
//Description: (Testbench) MBus Member Controller
//Update History: May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Combined the following three modules into one:
// mbus_member_sleep_ctrl_testbench
// mbus_member_wire_ctrl_testbench
// mbus_member_addr_rf_testbench
// mbus_int_ctrl_testbench
// Fixed potential hold-time violation in ext_int_dout & EXTERNAL_INT
// OLD: int_busy = WAKEUP_REQ & mbus_busy_b
// ext_int_dout and EXTERNAL_INT set to mbus_busy_b @ (posedge int_busy)
// NEW: int_busy = WAKEUP_REQ & mbus_busy_b & LRC_SLEEP
// ext_int_dout and EXTERNAL_INT set to 1 @ (posedge int_busy)
// Dec 16 2016 - Updated for MBus r04
// Fixed CIN glitch issue
// Now MBUS_BUSY_B is generated in mbus_node
// Apr 28 2017 - Updated for MBus r04p1
// More explicit isolation for SLEEP_REQ
// SLEEP_REQ* and MBUS_BUSY are isolated here, rather than in mbus_isolation.
// Aug 23 2017 - Checked for mbus_testbench
//*******************************************************************************************
`include "include/mbus_def_testbench.v"
module mbus_member_ctrl_testbench (
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output reg COUT,
output reg DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ,
input WAKEUP_REQ,
// Power-Gating Signals
output reg MBC_ISOLATE,
output MBC_ISOLATE_B,
output reg MBC_RESET,
output MBC_RESET_B,
output reg MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output reg EXTERNAL_INT,
// Short-Prefix
input ADDR_WR_EN,
input ADDR_CLR_B,
input [`MBUSTB_DYNA_WIDTH-1:0] ADDR_IN,
output reg [`MBUSTB_DYNA_WIDTH-1:0] ADDR_OUT,
output reg ADDR_VALID,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
wire next_mbc_isolate;
wire sleep_req_isol;
reg goingsleep;
assign MBC_SLEEP_B = ~MBC_SLEEP;
assign MBC_ISOLATE_B = ~MBC_ISOLATE;
assign MBC_RESET_B = ~MBC_RESET;
assign next_mbc_isolate = goingsleep | sleep_req_isol | MBC_SLEEP;
assign sleep_req_isol = SLEEP_REQ & MBC_ISOLATE_B;
always @ (posedge CIN or negedge RESETn) begin
if (~RESETn) begin
goingsleep <= `MBUSTB_SD 1'b0;
MBC_SLEEP <= `MBUSTB_SD 1'b1;
MBC_ISOLATE <= `MBUSTB_SD 1'b1;
end
else begin
goingsleep <= `SD sleep_req_isol;
MBC_SLEEP <= `MBUSTB_SD goingsleep;
MBC_ISOLATE <= `MBUSTB_SD next_mbc_isolate;
end
end
always @ (negedge CIN or negedge RESETn) begin
if (~RESETn) MBC_RESET <= `MBUSTB_SD 1'b1;
else MBC_RESET <= `MBUSTB_SD MBC_ISOLATE;
end
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
wire RESETn_local = RESETn & CIN;
wire RESETn_local2 = RESETn & clr_ext_int_b;
// mbus_busy_b_isol
wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
// int_busy
wire int_busy = (WAKEUP_REQ & mbus_busy_b_isol & LRC_SLEEP);
// ext_int_dout
reg ext_int_dout;
always @ (posedge int_busy or negedge RESETn_local) begin
if (~RESETn_local) ext_int_dout <= `MBUSTB_SD 0;
else ext_int_dout <= `MBUSTB_SD 1;
end
// EXTERNAL_INT
always @ (posedge int_busy or negedge RESETn_local2) begin
if (~RESETn_local2) EXTERNAL_INT <= `MBUSTB_SD 0;
else EXTERNAL_INT <= `MBUSTB_SD 1;
end
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
always @* begin
if (~RESETn) COUT <= `MBUSTB_SD 1'b1;
else if (MBC_ISOLATE) COUT <= `MBUSTB_SD CIN;
else COUT <= `MBUSTB_SD COUT_FROM_BUS;
if (~RESETn) DOUT <= `MBUSTB_SD 1'b1;
else if (ext_int_dout) DOUT <= `MBUSTB_SD 0;
else if (MBC_ISOLATE) DOUT <= `MBUSTB_SD DIN;
else DOUT <= `MBUSTB_SD DOUT_FROM_BUS;
end
//****************************************************************************
// SHORT ADDRESS (SHORT PREFIX) REGISTER
//****************************************************************************
wire RESETn_local3 = (RESETn & ADDR_CLR_B);
wire addr_update = (ADDR_WR_EN & (~MBC_ISOLATE));
always @ (posedge addr_update or negedge RESETn_local3) begin
if (~RESETn_local3) begin
ADDR_OUT <= `MBUSTB_SD {`MBUSTB_DYNA_WIDTH{1'b1}};
ADDR_VALID <= `MBUSTB_SD 0;
end
else begin
ADDR_OUT <= `MBUSTB_SD ADDR_IN;
ADDR_VALID <= `MBUSTB_SD 1;
end
end
endmodule // mbus_member_ctrl_testbench
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file instructionROM.v when simulating
// the core, instructionROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module instructionROM(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("instructionROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* bsg_router_crossbar_o_by_i.v
*
* This module connects N inputs to M outputs with a crossbar network.
*/
`include "bsg_defines.v"
module bsg_router_crossbar_o_by_i
#(parameter i_els_p=2
, parameter `BSG_INV_PARAM(o_els_p)
, parameter `BSG_INV_PARAM(i_width_p)
, parameter logic [i_els_p-1:0] i_use_credits_p = {i_els_p{1'b0}}
, parameter int i_fifo_els_p[i_els_p-1:0] = '{2,2}
, parameter lg_o_els_lp = `BSG_SAFE_CLOG2(o_els_p)
// drop_header_p drops the lower bits to select dest id from the datapath.
// The drop header parameter can be optionally used to combine multiple crossbars
// into a network and implement source routing.
, parameter drop_header_p = 0
, parameter o_width_lp = i_width_p-(drop_header_p*lg_o_els_lp)
)
(
input clk_i
, input reset_i
// fifo inputs
, input [i_els_p-1:0] valid_i
, input [i_els_p-1:0][i_width_p-1:0] data_i // lower bits = dest id.
, output [i_els_p-1:0] credit_ready_and_o // this can be either credits or ready_and_i on inputs based on i_use_credits_p
// crossbar output
, output [o_els_p-1:0] valid_o
, output [o_els_p-1:0][o_width_lp-1:0] data_o
, input [o_els_p-1:0] ready_and_i
);
// parameter checking
initial begin
// for now we leave this case unhandled
// awaiting an actual use case so we can
// determine whether the code is cleaner with
// 0-bit or 1-bit source routing.
assert(o_els_p > 1) else $error("o_els_p needs to be greater than 1.");
end
// input FIFO
logic [i_els_p-1:0] fifo_ready_lo;
logic [i_els_p-1:0] fifo_v_lo;
logic [i_els_p-1:0][i_width_p-1:0] fifo_data_lo;
logic [i_els_p-1:0] fifo_yumi_li;
for (genvar i = 0; i < i_els_p; i++) begin: fifo
bsg_fifo_1r1w_small #(
.width_p(i_width_p)
,.els_p(i_fifo_els_p[i])
) fifo0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(valid_i[i])
,.ready_o(fifo_ready_lo[i])
,.data_i(data_i[i])
,.v_o(fifo_v_lo[i])
,.data_o(fifo_data_lo[i])
,.yumi_i(fifo_yumi_li[i])
);
end
// credit or ready interface
for (genvar i = 0; i < i_els_p; i++) begin: intf
if (i_use_credits_p[i]) begin: cr
bsg_dff_reset #(
.width_p(1)
,.reset_val_p(0)
) dff0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(fifo_yumi_li[i])
,.data_o(credit_ready_and_o[i])
);
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i & valid_i[i]) begin
assert(fifo_ready_lo[i]) else $error("Trying to enque when there is no space in FIFO, while using credit interface. i =%d", i);
end
end
// synopsys translate_on
end
else begin: rd
assign credit_ready_and_o[i] = fifo_ready_lo[i];
end
end
// crossbar ctrl
logic [i_els_p-1:0][lg_o_els_lp-1:0] ctrl_sel_io_li;
logic [i_els_p-1:0] ctrl_yumi_lo;
logic [o_els_p-1:0][i_els_p-1:0] grants_lo;
bsg_crossbar_control_basic_o_by_i #(
.i_els_p(i_els_p)
,.o_els_p(o_els_p)
) ctrl0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.valid_i(fifo_v_lo)
,.sel_io_i(ctrl_sel_io_li)
,.yumi_o(fifo_yumi_li)
,.ready_and_i(ready_and_i)
,.valid_o(valid_o)
,.grants_oi_one_hot_o(grants_lo)
);
// lower bits encode the dest id.
for (genvar i = 0; i < i_els_p; i++) begin
assign ctrl_sel_io_li[i] = fifo_data_lo[i][0+:lg_o_els_lp];
end
// output mux
logic [i_els_p-1:0][o_width_lp-1:0] odata;
for (genvar i = 0; i < i_els_p; i++) begin
if (drop_header_p) begin
assign odata[i] = fifo_data_lo[i][i_width_p-1:lg_o_els_lp];
end
else begin
assign odata[i] = fifo_data_lo[i];
end
end
for (genvar i = 0; i < o_els_p; i++) begin: mux
bsg_mux_one_hot #(
.width_p(o_width_lp)
,.els_p(i_els_p)
) mux0 (
.data_i(odata)
,.sel_one_hot_i(grants_lo[i])
,.data_o(data_o[i])
);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_router_crossbar_o_by_i)
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_monitor_ram.v
// Title : LM32 monitor RAM, hold the load/monitor code
// Dependencies : system_conf.v
// Version : 6.1.17
// : Initial Release
// Version : version 7.0 (7.0SP2)
// : No Change
// : version 7.1: updated to fix r0 not being zero
// : when hitting a breakpoint (CR 38134)
// : version 7.2: updated to also store ip/im registers
// : and update im register when restoring stack
// =============================================================================
`include "system_conf.v"
module lm32_monitor_ram (DataInA, DataInB, AddressA, AddressB, ClockA,
ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB, QA, QB);
input [31:0] DataInA;
input [31:0] DataInB;
input [8:0] AddressA;
input [8:0] AddressB;
input ClockA;
input ClockB;
input ClockEnA;
input ClockEnB;
input WrA;
input WrB;
input ResetA;
input ResetB;
output [31:0] QA;
output [31:0] QB;
parameter lat_family = `LATTICE_FAMILY;
wire scuba_vhi;
wire scuba_vlo;
/* Verilog netlist generated by SCUBA Diamond_1.3_Production (92) */
/* Module Version: 7.1 */
/* c:\Diamond\diamond\1.3\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5d00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr ENABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e */
/* Wed Jun 29 15:54:43 2011 */
generate
if (lat_family == "MachXO2" || lat_family == "MachXO3L" || lat_family == "MachXO3LF") begin
defparam lm32_monitor_ram_0_0_3.INIT_DATA = "STATIC" ;
defparam lm32_monitor_ram_0_0_3.ASYNC_RESET_RELEASE = "SYNC" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_0C = "0x00000000000000000000000000000000000001810018300185001872944F314003180031C0032000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_0B = "0x324003280032C0038200001FB002010015B02E0000170001723F6012D401001AB000002F6002FBB1" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_0A = "0x31A003680036C1B06C1A05E190701807013066120661106610066090660806607001890019C3F200" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_09 = "0x001FB000003ADB2000040144100C0033400048040100C020140301C0402400000000000000000000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_08 = "0x003F30C65009A470DA460E42C0AE1F0EE003780000000000000A9FF000000A9FF000000080801810" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_07 = "0x0281803820049DC00008009DD011DF013E1015E301608009F80000C00808011E7013E9015EB017ED" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_06 = "0x009F4000003FE00000020A8003FE001FE001FE003FD00000000E8840009800094000900008C0F878" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_05 = "0x0E06C0D0640C05C0B0540A04C090440803C070340602C050240401C030140200C010000E88400098" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_04 = "0x00094000900008C100780E06C0D0640C05C0B0540A04C090440803C070340602C050240401C03014" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_03 = "0x0200C010003400000878000880020100201002FF34094000900008C0009C00098000800F8740E06C" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_02 = "0x0D0640C05C0B0540A04C090440803C070340602C050240401C030140200C010000006038A003E800" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_01 = "0x07CBC008001080A0000008CC400800108120000009CCC008001081A000000ACD4008001082200000" ;
defparam lm32_monitor_ram_0_0_3.INITVAL_00 = "0x10CDC008001082A000000CCE400800108320000012CEC008001083A0000000000000000003E00000" ;
defparam lm32_monitor_ram_0_0_3.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_0_3.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_0_3.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_0_3.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_0_3.GSR = "ENABLED" ;
defparam lm32_monitor_ram_0_0_3.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_0_3.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_0_3.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_0_3.DATA_WIDTH_B = 9 ;
defparam lm32_monitor_ram_0_0_3.DATA_WIDTH_A = 9 ;
DP8KC lm32_monitor_ram_0_0_3 (.DIA8(DataInA[8]), .DIA7(DataInA[7]),
.DIA6(DataInA[6]), .DIA5(DataInA[5]), .DIA4(DataInA[4]), .DIA3(DataInA[3]),
.DIA2(DataInA[2]), .DIA1(DataInA[1]), .DIA0(DataInA[0]), .ADA12(scuba_vlo),
.ADA11(AddressA[8]), .ADA10(AddressA[7]), .ADA9(AddressA[6]), .ADA8(AddressA[5]),
.ADA7(AddressA[4]), .ADA6(AddressA[3]), .ADA5(AddressA[2]), .ADA4(AddressA[1]),
.ADA3(AddressA[0]), .ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi),
.CEA(ClockEnA), .OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(DataInB[8]),
.DIB7(DataInB[7]), .DIB6(DataInB[6]), .DIB5(DataInB[5]), .DIB4(DataInB[4]),
.DIB3(DataInB[3]), .DIB2(DataInB[2]), .DIB1(DataInB[1]), .DIB0(DataInB[0]),
.ADB12(scuba_vlo), .ADB11(AddressB[8]), .ADB10(AddressB[7]), .ADB9(AddressB[6]),
.ADB8(AddressB[5]), .ADB7(AddressB[4]), .ADB6(AddressB[3]), .ADB5(AddressB[2]),
.ADB4(AddressB[1]), .ADB3(AddressB[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
.ADB0(scuba_vhi), .CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB),
.WEB(WrB), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
.RSTB(ResetB), .DOA8(QA[8]), .DOA7(QA[7]), .DOA6(QA[6]), .DOA5(QA[5]),
.DOA4(QA[4]), .DOA3(QA[3]), .DOA2(QA[2]), .DOA1(QA[1]), .DOA0(QA[0]),
.DOB8(QB[8]), .DOB7(QB[7]), .DOB6(QB[6]), .DOB5(QB[5]), .DOB4(QB[4]),
.DOB3(QB[3]), .DOB2(QB[2]), .DOB1(QB[1]), .DOB0(QB[0]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */;
defparam lm32_monitor_ram_0_1_2.INIT_DATA = "STATIC" ;
defparam lm32_monitor_ram_0_1_2.ASYNC_RESET_RELEASE = "SYNC" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_0C = "0x00000000000000000000000000000000000001FF301FF301FF301FF3FE803FF803FF803FF803FF80" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_0B = "0x3FF803FF803FF803FE04071FF00180101FF10000069FF059FF3FF803FE00100FF000343FE2C3FFFF" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_0A = "0x3FE043FF800FE8000080000800008000080000800008000080000800008000080011FF059FF3FE04" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_09 = "0x0707F308383FFFF0080010000100083FE00000802008000180200800018000000000800000000080" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_08 = "0x1007F1000010000100001000010000100083FE00300223FC801007F008801007F008441010010000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_07 = "0x30100100003007F00000101FF101FF101FF101FF100801007F0000010080101FF101FF101FF101FF" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_06 = "0x1007F001000FE0800000100800FE0810000100000FE8001000001802010030180301803018020080" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_05 = "0x30100100003010010000301001000030100100003010010000301001000030100100000010020100" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_04 = "0x20100201002010030080301001000030100100003010010000301001000030100100003010010000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_03 = "0x30100100001F87000080100801008010080100801F88000880008800088000880009802000030100" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_02 = "0x10000301001000030100100003010010000301001000030100100003010010000000833FF8000670" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_01 = "0x00000100042000000000000001000420000000000000010004200000000000000100042000000000" ;
defparam lm32_monitor_ram_0_1_2.INITVAL_00 = "0x00000100043000000000000001000420000000000000010004300000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_2.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_1_2.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_1_2.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_1_2.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_1_2.GSR = "ENABLED" ;
defparam lm32_monitor_ram_0_1_2.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_1_2.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_1_2.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_1_2.DATA_WIDTH_B = 9 ;
defparam lm32_monitor_ram_0_1_2.DATA_WIDTH_A = 9 ;
DP8KC lm32_monitor_ram_0_1_2 (.DIA8(DataInA[17]), .DIA7(DataInA[16]),
.DIA6(DataInA[15]), .DIA5(DataInA[14]), .DIA4(DataInA[13]), .DIA3(DataInA[12]),
.DIA2(DataInA[11]), .DIA1(DataInA[10]), .DIA0(DataInA[9]), .ADA12(scuba_vlo),
.ADA11(AddressA[8]), .ADA10(AddressA[7]), .ADA9(AddressA[6]), .ADA8(AddressA[5]),
.ADA7(AddressA[4]), .ADA6(AddressA[3]), .ADA5(AddressA[2]), .ADA4(AddressA[1]),
.ADA3(AddressA[0]), .ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi),
.CEA(ClockEnA), .OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(DataInB[17]),
.DIB7(DataInB[16]), .DIB6(DataInB[15]), .DIB5(DataInB[14]), .DIB4(DataInB[13]),
.DIB3(DataInB[12]), .DIB2(DataInB[11]), .DIB1(DataInB[10]), .DIB0(DataInB[9]),
.ADB12(scuba_vlo), .ADB11(AddressB[8]), .ADB10(AddressB[7]), .ADB9(AddressB[6]),
.ADB8(AddressB[5]), .ADB7(AddressB[4]), .ADB6(AddressB[3]), .ADB5(AddressB[2]),
.ADB4(AddressB[1]), .ADB3(AddressB[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
.ADB0(scuba_vhi), .CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB),
.WEB(WrB), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
.RSTB(ResetB), .DOA8(QA[17]), .DOA7(QA[16]), .DOA6(QA[15]), .DOA5(QA[14]),
.DOA4(QA[13]), .DOA3(QA[12]), .DOA2(QA[11]), .DOA1(QA[10]), .DOA0(QA[9]),
.DOB8(QB[17]), .DOB7(QB[16]), .DOB6(QB[15]), .DOB5(QB[14]), .DOB4(QB[13]),
.DOB3(QB[12]), .DOB2(QB[11]), .DOB1(QB[10]), .DOB0(QB[9]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */;
defparam lm32_monitor_ram_0_2_1.INIT_DATA = "STATIC" ;
defparam lm32_monitor_ram_0_2_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_0C = "0x00000000000000000000000000000000000000FF1A4FF184FF134FF1FF001FECA1FE921FE8A1FE82" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_0B = "0x1FE4A1FE421FE3A1FE70060FF2C75A0B0FF2C703010FF010FF1FF5A1FF630B163206081FE081FEFF" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_0A = "0x1FE881FEDA2111021110211102111021110211102111021110211102111021108010FF010FF1FE70" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_09 = "0x0A10C0E6301FEFF0E10822108210081FEE83CEE71C8E41C8E31C6E31C6E220100200202010020018" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_08 = "0x201082210822108221082210822108210081FE840F60400670201080E070201080E0081CEE41C8E4" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_07 = "0x1C6E31C6E31C5E71D1E71CEFF1C0FF1C0FF1C0FF1C0E01CFE71D1E71CEE01C0FF1C0FF1C0FF1C0FF" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_06 = "0x1CFE71D070220701D1082107022070010E802078210100F0F81CEE701EE700EE709EE707EE71CEE7" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_05 = "0x1CCE61CCE61CAE51CAE51C8E41C8E41C6E31C6E31C4E21C4E21C2E11C2E11C0E01C0F01CEE701EE7" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_04 = "0x00EE709EE707EE71CEE71CCE61CCE61CAE51CAE51C8E41C8E41C6E31C6E31C4E21C4E21C2E11C2E1" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_03 = "0x1C0E01C0E83DEE81D0E81D0E80100801008010083D0E8000E8090E8070E8020E8010EF1DEEF1DCEE" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_02 = "0x1DCEE1DAED1DAED1D8EC1D8EC1D6EB1D6EB1D4EA1D4EA1D2E91D2E91D0E81D0001D1EF1FF073CEE8" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_01 = "0x00000210E01CE001D00000000210E01CE001D00000000210E01CE001D00000000210E01CE001D000" ;
defparam lm32_monitor_ram_0_2_1.INITVAL_00 = "0x00000210E01CE001D00000000210E01CE001D00000000210E01CE001D00020100201002000001000" ;
defparam lm32_monitor_ram_0_2_1.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_2_1.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_2_1.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_2_1.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_2_1.GSR = "ENABLED" ;
defparam lm32_monitor_ram_0_2_1.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_2_1.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_2_1.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_2_1.DATA_WIDTH_B = 9 ;
defparam lm32_monitor_ram_0_2_1.DATA_WIDTH_A = 9 ;
DP8KC lm32_monitor_ram_0_2_1 (.DIA8(DataInA[26]), .DIA7(DataInA[25]),
.DIA6(DataInA[24]), .DIA5(DataInA[23]), .DIA4(DataInA[22]), .DIA3(DataInA[21]),
.DIA2(DataInA[20]), .DIA1(DataInA[19]), .DIA0(DataInA[18]), .ADA12(scuba_vlo),
.ADA11(AddressA[8]), .ADA10(AddressA[7]), .ADA9(AddressA[6]), .ADA8(AddressA[5]),
.ADA7(AddressA[4]), .ADA6(AddressA[3]), .ADA5(AddressA[2]), .ADA4(AddressA[1]),
.ADA3(AddressA[0]), .ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi),
.CEA(ClockEnA), .OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo),
.CSA1(scuba_vlo), .CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(DataInB[26]),
.DIB7(DataInB[25]), .DIB6(DataInB[24]), .DIB5(DataInB[23]), .DIB4(DataInB[22]),
.DIB3(DataInB[21]), .DIB2(DataInB[20]), .DIB1(DataInB[19]), .DIB0(DataInB[18]),
.ADB12(scuba_vlo), .ADB11(AddressB[8]), .ADB10(AddressB[7]), .ADB9(AddressB[6]),
.ADB8(AddressB[5]), .ADB7(AddressB[4]), .ADB6(AddressB[3]), .ADB5(AddressB[2]),
.ADB4(AddressB[1]), .ADB3(AddressB[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo),
.ADB0(scuba_vhi), .CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB),
.WEB(WrB), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
.RSTB(ResetB), .DOA8(QA[26]), .DOA7(QA[25]), .DOA6(QA[24]), .DOA5(QA[23]),
.DOA4(QA[22]), .DOA3(QA[21]), .DOA2(QA[20]), .DOA1(QA[19]), .DOA0(QA[18]),
.DOB8(QB[26]), .DOB7(QB[25]), .DOB6(QB[24]), .DOB5(QB[23]), .DOB4(QB[22]),
.DOB3(QB[21]), .DOB2(QB[20]), .DOB1(QB[19]), .DOB0(QB[18]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam lm32_monitor_ram_0_3_0.INIT_DATA = "STATIC" ;
defparam lm32_monitor_ram_0_3_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_0C = "0x000000000000000000000000000000000000001C0341C0341C0341C03E060381A0381A0381A0381A" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_0B = "0x0381A0381A0381A038170241C00C0600C1F0120602E1F02E1F0380603E060100900C1703E1703E1C" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_0A = "0x03E170381A0160F0100F0100F0100F0100F0100F0100F0100F0100F0100F0100F02E1F02E1F03817" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_09 = "0x02408028120381F02E0801E0801E1703E1800C0500A0500A0500A0500A0500C0600C1A00C0600C1A" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_08 = "0x00C0B01E0801E0801E0801E0801E0801E1703E0700E0F01E1A00C0B0241A00C0B024170160B0160B" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_07 = "0x0160B0160B016060300600A1F0101F0101F0101F0100B016060300600A0500C1F00C1F00C1F00C1F" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_06 = "0x016060301A016120300801E1A01612008180081A010040241800A050340503405034050340500A05" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_05 = "0x00A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A1800A0503405" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_04 = "0x03405034050340500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A05" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_03 = "0x00A0500A1800C170160B00A0B00000000000000400C0B0240B0240B0240B0240B0240B0160B0160B" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_02 = "0x0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B01613016060380600C17" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_01 = "0x0381F00C170161F02E130381F00C170161F02E130381F00C170161F02E130381F00C170161F02E13" ;
defparam lm32_monitor_ram_0_3_0.INITVAL_00 = "0x0381F00C170161F02E130381F00C170161F02E130381F00C170161F02E1300C0600C0600C1F03413" ;
defparam lm32_monitor_ram_0_3_0.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_3_0.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_3_0.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_3_0.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_3_0.GSR = "ENABLED" ;
defparam lm32_monitor_ram_0_3_0.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_3_0.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_3_0.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_3_0.DATA_WIDTH_B = 9 ;
defparam lm32_monitor_ram_0_3_0.DATA_WIDTH_A = 9 ;
DP8KC lm32_monitor_ram_0_3_0 (.DIA8(scuba_vlo), .DIA7(scuba_vlo), .DIA6(scuba_vlo),
.DIA5(scuba_vlo), .DIA4(DataInA[31]), .DIA3(DataInA[30]), .DIA2(DataInA[29]),
.DIA1(DataInA[28]), .DIA0(DataInA[27]), .ADA12(scuba_vlo), .ADA11(AddressA[8]),
.ADA10(AddressA[7]), .ADA9(AddressA[6]), .ADA8(AddressA[5]), .ADA7(AddressA[4]),
.ADA6(AddressA[3]), .ADA5(AddressA[2]), .ADA4(AddressA[1]), .ADA3(AddressA[0]),
.ADA2(scuba_vlo), .ADA1(scuba_vlo), .ADA0(scuba_vhi), .CEA(ClockEnA),
.OCEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo),
.CSA0(scuba_vlo), .RSTA(ResetA), .DIB8(scuba_vlo), .DIB7(scuba_vlo),
.DIB6(scuba_vlo), .DIB5(scuba_vlo), .DIB4(DataInB[31]), .DIB3(DataInB[30]),
.DIB2(DataInB[29]), .DIB1(DataInB[28]), .DIB0(DataInB[27]), .ADB12(scuba_vlo),
.ADB11(AddressB[8]), .ADB10(AddressB[7]), .ADB9(AddressB[6]), .ADB8(AddressB[5]),
.ADB7(AddressB[4]), .ADB6(AddressB[3]), .ADB5(AddressB[2]), .ADB4(AddressB[1]),
.ADB3(AddressB[0]), .ADB2(scuba_vlo), .ADB1(scuba_vlo), .ADB0(scuba_vhi),
.CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB2(scuba_vlo),
.CSB1(scuba_vlo), .CSB0(scuba_vlo), .RSTB(ResetB), .DOA8(), .DOA7(),
.DOA6(), .DOA5(), .DOA4(QA[31]), .DOA3(QA[30]), .DOA2(QA[29]), .DOA1(QA[28]),
.DOA0(QA[27]), .DOB8(), .DOB7(), .DOB6(), .DOB5(), .DOB4(QB[31]),
.DOB3(QB[30]), .DOB2(QB[29]), .DOB1(QB[28]), .DOB0(QB[27]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */;
// exemplar begin
// exemplar attribute lm32_monitor_ram_0_0_3 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_0_3 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_1_2 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_1_2 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_2_1 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_2_1 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_3_0 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_3_0 MEM_INIT_FILE lm32_monitor.mem
// exemplar end
end else if (lat_family == "ECP5U" || lat_family == "ECP5UM") begin
/* Verilog netlist generated by SCUBA Diamond Version 3.2.0.61 */
/* Module Version: 7.3 */
/* C:\lscc\diamond\3.2\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr ENABLED -writemode NORMAL -resetmode SYNC -memfile lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e */
/* Thu Mar 06 13:30:33 2014 */
defparam lm32_monitor_ram_0_0_1.INIT_DATA = "STATIC" ;
defparam lm32_monitor_ram_0_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_19 = "0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_18 = "0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_17 = "0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_16 = "0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_15 = "0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_14 = "0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_13 = "0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_12 = "0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_11 = "0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_10 = "0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0F = "0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0E = "0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0D = "0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0C = "0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0B = "0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0A = "0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_09 = "0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_08 = "0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_07 = "0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_06 = "0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_05 = "0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_04 = "0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_03 = "0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_02 = "0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_01 = "0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_00 = "0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" ;
defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_0_1.GSR = "ENABLED" ;
defparam lm32_monitor_ram_0_0_1.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ;
DP16KD lm32_monitor_ram_0_0_1 (.DIA17(DataInA[17]), .DIA16(DataInA[16]),
.DIA15(DataInA[15]), .DIA14(DataInA[14]), .DIA13(DataInA[13]), .DIA12(DataInA[12]),
.DIA11(DataInA[11]), .DIA10(DataInA[10]), .DIA9(DataInA[9]), .DIA8(DataInA[8]),
.DIA7(DataInA[7]), .DIA6(DataInA[6]), .DIA5(DataInA[5]), .DIA4(DataInA[4]),
.DIA3(DataInA[3]), .DIA2(DataInA[2]), .DIA1(DataInA[1]), .DIA0(DataInA[0]),
.ADA13(scuba_vlo), .ADA12(AddressA[8]), .ADA11(AddressA[7]), .ADA10(AddressA[6]),
.ADA9(AddressA[5]), .ADA8(AddressA[4]), .ADA7(AddressA[3]), .ADA6(AddressA[2]),
.ADA5(AddressA[1]), .ADA4(AddressA[0]), .ADA3(scuba_vlo), .ADA2(scuba_vlo),
.ADA1(scuba_vhi), .ADA0(scuba_vhi), .CEA(ClockEnA), .OCEA(ClockEnA),
.CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo), .CSA0(scuba_vlo),
.RSTA(ResetA), .DIB17(DataInB[17]), .DIB16(DataInB[16]), .DIB15(DataInB[15]),
.DIB14(DataInB[14]), .DIB13(DataInB[13]), .DIB12(DataInB[12]), .DIB11(DataInB[11]),
.DIB10(DataInB[10]), .DIB9(DataInB[9]), .DIB8(DataInB[8]), .DIB7(DataInB[7]),
.DIB6(DataInB[6]), .DIB5(DataInB[5]), .DIB4(DataInB[4]), .DIB3(DataInB[3]),
.DIB2(DataInB[2]), .DIB1(DataInB[1]), .DIB0(DataInB[0]), .ADB13(scuba_vlo),
.ADB12(AddressB[8]), .ADB11(AddressB[7]), .ADB10(AddressB[6]), .ADB9(AddressB[5]),
.ADB8(AddressB[4]), .ADB7(AddressB[3]), .ADB6(AddressB[2]), .ADB5(AddressB[1]),
.ADB4(AddressB[0]), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vhi),
.ADB0(scuba_vhi), .CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB),
.WEB(WrB), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
.RSTB(ResetB), .DOA17(QA[17]), .DOA16(QA[16]), .DOA15(QA[15]), .DOA14(QA[14]),
.DOA13(QA[13]), .DOA12(QA[12]), .DOA11(QA[11]), .DOA10(QA[10]),
.DOA9(QA[9]), .DOA8(QA[8]), .DOA7(QA[7]), .DOA6(QA[6]), .DOA5(QA[5]),
.DOA4(QA[4]), .DOA3(QA[3]), .DOA2(QA[2]), .DOA1(QA[1]), .DOA0(QA[0]),
.DOB17(QB[17]), .DOB16(QB[16]), .DOB15(QB[15]), .DOB14(QB[14]),
.DOB13(QB[13]), .DOB12(QB[12]), .DOB11(QB[11]), .DOB10(QB[10]),
.DOB9(QB[9]), .DOB8(QB[8]), .DOB7(QB[7]), .DOB6(QB[6]), .DOB5(QB[5]),
.DOB4(QB[4]), .DOB3(QB[3]), .DOB2(QB[2]), .DOB1(QB[1]), .DOB0(QB[0]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam lm32_monitor_ram_0_1_0.INIT_DATA = "STATIC" ;
defparam lm32_monitor_ram_0_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_19 = "0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_18 = "0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_17 = "0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_16 = "0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_15 = "0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_14 = "0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_13 = "0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_12 = "0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_11 = "0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_10 = "0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0F = "0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0E = "0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0D = "0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0C = "0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0B = "0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0A = "0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_09 = "0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_08 = "0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_07 = "0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_06 = "0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_05 = "0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_04 = "0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_03 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_02 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_01 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_00 = "0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" ;
defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_1_0.GSR = "ENABLED" ;
defparam lm32_monitor_ram_0_1_0.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ;
DP16KD lm32_monitor_ram_0_1_0 (.DIA17(scuba_vlo), .DIA16(scuba_vlo),
.DIA15(scuba_vlo), .DIA14(scuba_vlo), .DIA13(DataInA[31]), .DIA12(DataInA[30]),
.DIA11(DataInA[29]), .DIA10(DataInA[28]), .DIA9(DataInA[27]), .DIA8(DataInA[26]),
.DIA7(DataInA[25]), .DIA6(DataInA[24]), .DIA5(DataInA[23]), .DIA4(DataInA[22]),
.DIA3(DataInA[21]), .DIA2(DataInA[20]), .DIA1(DataInA[19]), .DIA0(DataInA[18]),
.ADA13(scuba_vlo), .ADA12(AddressA[8]), .ADA11(AddressA[7]), .ADA10(AddressA[6]),
.ADA9(AddressA[5]), .ADA8(AddressA[4]), .ADA7(AddressA[3]), .ADA6(AddressA[2]),
.ADA5(AddressA[1]), .ADA4(AddressA[0]), .ADA3(scuba_vlo), .ADA2(scuba_vlo),
.ADA1(scuba_vhi), .ADA0(scuba_vhi), .CEA(ClockEnA), .OCEA(ClockEnA),
.CLKA(ClockA), .WEA(WrA), .CSA2(scuba_vlo), .CSA1(scuba_vlo), .CSA0(scuba_vlo),
.RSTA(ResetA), .DIB17(scuba_vlo), .DIB16(scuba_vlo), .DIB15(scuba_vlo),
.DIB14(scuba_vlo), .DIB13(DataInB[31]), .DIB12(DataInB[30]), .DIB11(DataInB[29]),
.DIB10(DataInB[28]), .DIB9(DataInB[27]), .DIB8(DataInB[26]), .DIB7(DataInB[25]),
.DIB6(DataInB[24]), .DIB5(DataInB[23]), .DIB4(DataInB[22]), .DIB3(DataInB[21]),
.DIB2(DataInB[20]), .DIB1(DataInB[19]), .DIB0(DataInB[18]), .ADB13(scuba_vlo),
.ADB12(AddressB[8]), .ADB11(AddressB[7]), .ADB10(AddressB[6]), .ADB9(AddressB[5]),
.ADB8(AddressB[4]), .ADB7(AddressB[3]), .ADB6(AddressB[2]), .ADB5(AddressB[1]),
.ADB4(AddressB[0]), .ADB3(scuba_vlo), .ADB2(scuba_vlo), .ADB1(scuba_vhi),
.ADB0(scuba_vhi), .CEB(ClockEnB), .OCEB(ClockEnB), .CLKB(ClockB),
.WEB(WrB), .CSB2(scuba_vlo), .CSB1(scuba_vlo), .CSB0(scuba_vlo),
.RSTB(ResetB), .DOA17(), .DOA16(), .DOA15(), .DOA14(), .DOA13(QA[31]),
.DOA12(QA[30]), .DOA11(QA[29]), .DOA10(QA[28]), .DOA9(QA[27]), .DOA8(QA[26]),
.DOA7(QA[25]), .DOA6(QA[24]), .DOA5(QA[23]), .DOA4(QA[22]), .DOA3(QA[21]),
.DOA2(QA[20]), .DOA1(QA[19]), .DOA0(QA[18]), .DOB17(), .DOB16(),
.DOB15(), .DOB14(), .DOB13(QB[31]), .DOB12(QB[30]), .DOB11(QB[29]),
.DOB10(QB[28]), .DOB9(QB[27]), .DOB8(QB[26]), .DOB7(QB[25]), .DOB6(QB[24]),
.DOB5(QB[23]), .DOB4(QB[22]), .DOB3(QB[21]), .DOB2(QB[20]), .DOB1(QB[19]),
.DOB0(QB[18]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */;
// exemplar begin
// exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem
// exemplar end
end else if (lat_family == "ECP3") begin
/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
/* Module Version: 7.0 */
/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e */
/* Tue Jun 16 18:01:57 2009 */
defparam lm32_monitor_ram_0_0_1.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_19 = "0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_18 = "0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_17 = "0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_16 = "0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_15 = "0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_14 = "0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_13 = "0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_12 = "0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_11 = "0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_10 = "0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0F = "0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0E = "0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0D = "0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0C = "0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0B = "0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0A = "0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_09 = "0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_08 = "0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_07 = "0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_06 = "0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_05 = "0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_04 = "0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_03 = "0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_02 = "0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_01 = "0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" ;
defparam lm32_monitor_ram_0_0_1.INITVAL_00 = "0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" ;
defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_0_1.GSR = "DISABLED" ;
defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ;
DP16KC lm32_monitor_ram_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]),
.DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]),
.DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]),
.DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]),
.DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
.OCEA(ClockEnA), .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo),
.CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]),
.DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]),
.DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]),
.DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]),
.DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]),
.ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo),
.ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]),
.ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]),
.ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB),
.OCEB(ClockEnB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo),
.CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]),
.DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]),
.DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]),
.DOA13(QA[13]), .DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]),
.DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]),
.DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]),
.DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]),
.DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis RESETMODE="SYNC" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam lm32_monitor_ram_0_1_0.INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_19 = "0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_18 = "0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_17 = "0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_16 = "0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_15 = "0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_14 = "0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_13 = "0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_12 = "0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_11 = "0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_10 = "0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0F = "0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0E = "0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0D = "0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0C = "0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0B = "0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0A = "0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_09 = "0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_08 = "0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_07 = "0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_06 = "0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_05 = "0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_04 = "0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_03 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_02 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_01 = "0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" ;
defparam lm32_monitor_ram_0_1_0.INITVAL_00 = "0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" ;
defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "0b000" ;
defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "0b000" ;
defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_1_0.GSR = "DISABLED" ;
defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ;
DP16KC lm32_monitor_ram_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]),
.DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
.DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
.DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
.DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
.OCEA(ClockEnA), .WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo),
.CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]),
.DIB2(DataInB[20]), .DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]),
.DIB6(DataInB[24]), .DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]),
.DIB10(DataInB[28]), .DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]),
.DIB14(scuba_vlo), .DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo),
.ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo),
.ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]),
.ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]),
.ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB),
.OCEB(ClockEnB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo),
.CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]),
.DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]),
.DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]),
.DOA13(QA[31]), .DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]),
.DOB1(QB[19]), .DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]),
.DOB6(QB[24]), .DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]),
.DOB11(QB[29]), .DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(),
.DOB16(), .DOB17())
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis RESETMODE="SYNC" */;
// exemplar begin
// exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE SYNC
// exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE SYNC
// exemplar end
end else if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin
/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
/* Module Version: 7.0 */
/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5g00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -n lm32_monitor_ram -e */
/* Tue Jun 16 18:01:57 2009 */
// synopsys translate_off
defparam lm32_monitor_ram_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ;
defparam lm32_monitor_ram_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ;
defparam lm32_monitor_ram_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ;
defparam lm32_monitor_ram_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ;
defparam lm32_monitor_ram_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ;
defparam lm32_monitor_ram_0_0_1.CSDECODE_B = "000" ;
defparam lm32_monitor_ram_0_0_1.CSDECODE_A = "000" ;
defparam lm32_monitor_ram_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_0_1.GSR = "DISABLED" ;
defparam lm32_monitor_ram_0_0_1.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_0_1.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_0_1.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_0_0_1.DATA_WIDTH_A = 18 ;
// synopsys translate_on
DP8KA lm32_monitor_ram_0_0_1 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA),
.CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA),
.CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo),
.CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[0]), .DIA1(DataInA[1]),
.DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]),
.DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]),
.DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]),
.DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]),
.DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]),
.DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]),
.DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]),
.DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi),
.ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
.ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
.ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
.DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]),
.DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]),
.DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]),
.DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]),
.DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]),
.DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]),
.DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]),
.DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */
/* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */
/* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */
/* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */
/* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */
/* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */
/* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */
/* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */
/* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */
/* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */
/* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */
/* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */
/* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */
/* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */
/* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */
/* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */
/* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */
/* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */
/* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */
/* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */
/* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */
/* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */
/* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */
/* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */
/* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */
/* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */
/* synthesis CSDECODE_B="000" */
/* synthesis CSDECODE_A="000" */
/* synthesis WRITEMODE_B="NORMAL" */
/* synthesis WRITEMODE_A="NORMAL" */
/* synthesis GSR="DISABLED" */
/* synthesis RESETMODE="SYNC" */
/* synthesis REGMODE_B="NOREG" */
/* synthesis REGMODE_A="NOREG" */
/* synthesis DATA_WIDTH_B="18" */
/* synthesis DATA_WIDTH_A="18" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
// synopsys translate_off
defparam lm32_monitor_ram_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ;
defparam lm32_monitor_ram_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ;
defparam lm32_monitor_ram_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ;
defparam lm32_monitor_ram_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
defparam lm32_monitor_ram_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam lm32_monitor_ram_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ;
defparam lm32_monitor_ram_0_1_0.CSDECODE_B = "000" ;
defparam lm32_monitor_ram_0_1_0.CSDECODE_A = "000" ;
defparam lm32_monitor_ram_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_0_1_0.GSR = "DISABLED" ;
defparam lm32_monitor_ram_0_1_0.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_0_1_0.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_0_1_0.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_0_1_0.DATA_WIDTH_A = 18 ;
// synopsys translate_on
DP8KA lm32_monitor_ram_0_1_0 (.CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA),
.CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA),
.CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo),
.CSB2(scuba_vlo), .RSTB(ResetB), .DIA0(DataInA[18]), .DIA1(DataInA[19]),
.DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
.DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
.DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
.DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]),
.DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]),
.DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]),
.DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo),
.DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi),
.ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
.ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
.ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
.DOA0(QA[18]), .DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]),
.DOA5(QA[23]), .DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]),
.DOA10(QA[28]), .DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]),
.DOA14(), .DOA15(), .DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]),
.DOB2(QB[20]), .DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]),
.DOB7(QB[25]), .DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]),
.DOB12(QB[30]), .DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
/* synthesis MEM_LPC_FILE="lm32_monitor_ram.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */
/* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */
/* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */
/* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */
/* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */
/* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */
/* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */
/* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */
/* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */
/* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */
/* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */
/* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */
/* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */
/* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */
/* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */
/* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */
/* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */
/* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */
/* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */
/* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */
/* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
/* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
/* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */
/* synthesis CSDECODE_B="000" */
/* synthesis CSDECODE_A="000" */
/* synthesis WRITEMODE_B="NORMAL" */
/* synthesis WRITEMODE_A="NORMAL" */
/* synthesis GSR="DISABLED" */
/* synthesis RESETMODE="SYNC" */
/* synthesis REGMODE_B="NOREG" */
/* synthesis REGMODE_A="NOREG" */
/* synthesis DATA_WIDTH_B="18" */
/* synthesis DATA_WIDTH_A="18" */;
// exemplar begin
// exemplar attribute lm32_monitor_ram_0_0_1 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_0_1 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000
// exemplar attribute lm32_monitor_ram_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000
// exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_B 000
// exemplar attribute lm32_monitor_ram_0_0_1 CSDECODE_A 000
// exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_B NORMAL
// exemplar attribute lm32_monitor_ram_0_0_1 WRITEMODE_A NORMAL
// exemplar attribute lm32_monitor_ram_0_0_1 GSR DISABLED
// exemplar attribute lm32_monitor_ram_0_0_1 RESETMODE SYNC
// exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_B NOREG
// exemplar attribute lm32_monitor_ram_0_0_1 REGMODE_A NOREG
// exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_B 18
// exemplar attribute lm32_monitor_ram_0_0_1 DATA_WIDTH_A 18
// exemplar attribute lm32_monitor_ram_0_1_0 MEM_LPC_FILE lm32_monitor_ram.lpc
// exemplar attribute lm32_monitor_ram_0_1_0 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute lm32_monitor_ram_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600
// exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_B 000
// exemplar attribute lm32_monitor_ram_0_1_0 CSDECODE_A 000
// exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_B NORMAL
// exemplar attribute lm32_monitor_ram_0_1_0 WRITEMODE_A NORMAL
// exemplar attribute lm32_monitor_ram_0_1_0 GSR DISABLED
// exemplar attribute lm32_monitor_ram_0_1_0 RESETMODE SYNC
// exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_B NOREG
// exemplar attribute lm32_monitor_ram_0_1_0 REGMODE_A NOREG
// exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_B 18
// exemplar attribute lm32_monitor_ram_0_1_0 DATA_WIDTH_A 18
// exemplar end
end else if (lat_family == "ECP2" || lat_family == "ECP2M" || lat_family == "XP2") begin
/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
/* Module Version: 7.0 */
/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5a00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -writemode NORMAL -resetmode SYNC -memfile ../../lm32_monitor.mem -memformat hex -e -n lm32_monitor_ram_ecp2 */
/* Tue Jun 16 18:01:57 2009 */
// synopsys translate_off
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_B = 3'b000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.CSDECODE_A = 3'b000 ;
defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_ecp2_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_ecp2_0_0_1.GSR = "DISABLED" ;
defparam lm32_monitor_ram_ecp2_0_0_1.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_ecp2_0_0_1.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_ecp2_0_0_1.DATA_WIDTH_A = 18 ;
// synopsys translate_on
DP16KB lm32_monitor_ram_ecp2_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]),
.DIA2(DataInA[2]), .DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]),
.DIA6(DataInA[6]), .DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]),
.DIA10(DataInA[10]), .DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]),
.DIA14(DataInA[14]), .DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
.WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
.RSTA(ResetA), .DIB0(DataInB[0]), .DIB1(DataInB[1]), .DIB2(DataInB[2]),
.DIB3(DataInB[3]), .DIB4(DataInB[4]), .DIB5(DataInB[5]), .DIB6(DataInB[6]),
.DIB7(DataInB[7]), .DIB8(DataInB[8]), .DIB9(DataInB[9]), .DIB10(DataInB[10]),
.DIB11(DataInB[11]), .DIB12(DataInB[12]), .DIB13(DataInB[13]), .DIB14(DataInB[14]),
.DIB15(DataInB[15]), .DIB16(DataInB[16]), .DIB17(DataInB[17]), .ADB0(scuba_vhi),
.ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
.ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
.ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
.ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo),
.CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[0]),
.DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]), .DOA4(QA[4]), .DOA5(QA[5]),
.DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]), .DOA9(QA[9]), .DOA10(QA[10]),
.DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]), .DOA14(QA[14]),
.DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]), .DOB0(QB[0]), .DOB1(QB[1]),
.DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]), .DOB5(QB[5]), .DOB6(QB[6]),
.DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]), .DOB10(QB[10]), .DOB11(QB[11]),
.DOB12(QB[12]), .DOB13(QB[13]), .DOB14(QB[14]), .DOB15(QB[15]),
.DOB16(QB[16]), .DOB17(QB[17]))
/* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */
/* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */
/* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */
/* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */
/* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */
/* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */
/* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */
/* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */
/* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */
/* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */
/* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */
/* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */
/* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */
/* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */
/* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */
/* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */
/* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */
/* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */
/* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */
/* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */
/* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */
/* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */
/* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */
/* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */
/* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */
/* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */
/* synthesis CSDECODE_B="0b000" */
/* synthesis CSDECODE_A="0b000" */
/* synthesis WRITEMODE_B="NORMAL" */
/* synthesis WRITEMODE_A="NORMAL" */
/* synthesis GSR="DISABLED" */
/* synthesis RESETMODE="SYNC" */
/* synthesis REGMODE_B="NOREG" */
/* synthesis REGMODE_A="NOREG" */
/* synthesis DATA_WIDTH_B="18" */
/* synthesis DATA_WIDTH_A="18" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
// synopsys translate_off
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam lm32_monitor_ram_ecp2_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ;
defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_B = 3'b000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.CSDECODE_A = 3'b000 ;
defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam lm32_monitor_ram_ecp2_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam lm32_monitor_ram_ecp2_0_1_0.GSR = "DISABLED" ;
defparam lm32_monitor_ram_ecp2_0_1_0.RESETMODE = "SYNC" ;
defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_B = "NOREG" ;
defparam lm32_monitor_ram_ecp2_0_1_0.REGMODE_A = "NOREG" ;
defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_B = 18 ;
defparam lm32_monitor_ram_ecp2_0_1_0.DATA_WIDTH_A = 18 ;
// synopsys translate_on
DP16KB lm32_monitor_ram_ecp2_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]),
.DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
.DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
.DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
.DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
.WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
.RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]),
.DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]),
.DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]),
.DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo),
.DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi),
.ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
.ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
.ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
.ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo),
.CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]),
.DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]),
.DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]),
.DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(),
.DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]),
.DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]),
.DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]),
.DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
/* synthesis MEM_LPC_FILE="lm32_monitor_ram_ecp2.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */
/* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */
/* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */
/* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */
/* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */
/* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */
/* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */
/* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */
/* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */
/* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */
/* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */
/* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */
/* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */
/* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */
/* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */
/* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */
/* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */
/* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */
/* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */
/* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */
/* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
/* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
/* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */
/* synthesis CSDECODE_B="0b000" */
/* synthesis CSDECODE_A="0b000" */
/* synthesis WRITEMODE_B="NORMAL" */
/* synthesis WRITEMODE_A="NORMAL" */
/* synthesis GSR="DISABLED" */
/* synthesis RESETMODE="SYNC" */
/* synthesis REGMODE_B="NOREG" */
/* synthesis REGMODE_A="NOREG" */
/* synthesis DATA_WIDTH_B="18" */
/* synthesis DATA_WIDTH_A="18" */;
// exemplar begin
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_B 0b000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 CSDECODE_A 0b000
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_B NORMAL
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 WRITEMODE_A NORMAL
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 GSR DISABLED
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 RESETMODE SYNC
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_B NOREG
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 REGMODE_A NOREG
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_B 18
// exemplar attribute lm32_monitor_ram_ecp2_0_0_1 DATA_WIDTH_A 18
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_LPC_FILE lm32_monitor_ram_ecp2.lpc
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_B 0b000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 CSDECODE_A 0b000
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_B NORMAL
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 WRITEMODE_A NORMAL
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 GSR DISABLED
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 RESETMODE SYNC
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_B NOREG
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 REGMODE_A NOREG
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_B 18
// exemplar attribute lm32_monitor_ram_ecp2_0_1_0 DATA_WIDTH_A 18
// exemplar end
end else if (lat_family == "SC" || lat_family == "SCM") begin
/* Verilog netlist generated by SCUBA ispLever_v8.0_ALPHA (69) */
/* Module Version: 7.0 */
/* c:\ispTOOLS8_0\ispFPGA\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch or5s00 -type bram -wp 11 -rp 1010 -addr_width 9 -data_width 32 -num_rows 512 -gsr DISABLED -sync_reset -memfile ../../lm32_monitor.mem -memformat hex -e -n sc_rom_monitor */
/* Tue Jun 16 18:01:58 2009 */
// synopsys translate_off
defparam sc_rom_monitor_0_0_1.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_19 = 320'h0000000000000000000000000000000000000000000000000000000000000000000000000003FF81 ;
defparam sc_rom_monitor_0_0_1.INITVAL_18 = 320'h300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_17 = 320'h3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_16 = 320'h068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1 ;
defparam sc_rom_monitor_0_0_1.INITVAL_15 = 320'h3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012 ;
defparam sc_rom_monitor_0_0_1.INITVAL_14 = 320'h00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800 ;
defparam sc_rom_monitor_0_0_1.INITVAL_13 = 320'h070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004 ;
defparam sc_rom_monitor_0_0_1.INITVAL_12 = 320'h200081000C0001030014200181001C00020300240000000000000001000000000000000000010000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_11 = 320'h100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_10 = 320'h30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010 ;
defparam sc_rom_monitor_0_0_1.INITVAL_0F = 320'h30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3 ;
defparam sc_rom_monitor_0_0_1.INITVAL_0E = 320'h1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED ;
defparam sc_rom_monitor_0_0_1.INITVAL_0D = 320'h100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_0C = 320'h0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078 ;
defparam sc_rom_monitor_0_0_1.INITVAL_0B = 320'h300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034 ;
defparam sc_rom_monitor_0_0_1.INITVAL_0A = 320'h300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098 ;
defparam sc_rom_monitor_0_0_1.INITVAL_09 = 320'h20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054 ;
defparam sc_rom_monitor_0_0_1.INITVAL_08 = 320'h300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014 ;
defparam sc_rom_monitor_0_0_1.INITVAL_07 = 320'h300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF ;
defparam sc_rom_monitor_0_0_1.INITVAL_06 = 320'h1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C ;
defparam sc_rom_monitor_0_0_1.INITVAL_05 = 320'h1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C ;
defparam sc_rom_monitor_0_0_1.INITVAL_04 = 320'h1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_03 = 320'h0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_02 = 320'h0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_01 = 320'h00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000 ;
defparam sc_rom_monitor_0_0_1.INITVAL_00 = 320'h00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000 ;
defparam sc_rom_monitor_0_0_1.CSDECODE_B = 3'b000 ;
defparam sc_rom_monitor_0_0_1.CSDECODE_A = 3'b000 ;
defparam sc_rom_monitor_0_0_1.WRITEMODE_B = "NORMAL" ;
defparam sc_rom_monitor_0_0_1.WRITEMODE_A = "NORMAL" ;
defparam sc_rom_monitor_0_0_1.GSR = "DISABLED" ;
defparam sc_rom_monitor_0_0_1.RESETMODE = "SYNC" ;
defparam sc_rom_monitor_0_0_1.REGMODE_B = "NOREG" ;
defparam sc_rom_monitor_0_0_1.REGMODE_A = "NOREG" ;
defparam sc_rom_monitor_0_0_1.DATA_WIDTH_B = 18 ;
defparam sc_rom_monitor_0_0_1.DATA_WIDTH_A = 18 ;
// synopsys translate_on
DP16KA sc_rom_monitor_0_0_1 (.DIA0(DataInA[0]), .DIA1(DataInA[1]), .DIA2(DataInA[2]),
.DIA3(DataInA[3]), .DIA4(DataInA[4]), .DIA5(DataInA[5]), .DIA6(DataInA[6]),
.DIA7(DataInA[7]), .DIA8(DataInA[8]), .DIA9(DataInA[9]), .DIA10(DataInA[10]),
.DIA11(DataInA[11]), .DIA12(DataInA[12]), .DIA13(DataInA[13]), .DIA14(DataInA[14]),
.DIA15(DataInA[15]), .DIA16(DataInA[16]), .DIA17(DataInA[17]), .ADA0(scuba_vhi),
.ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo), .ADA4(AddressA[0]),
.ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]), .ADA8(AddressA[4]),
.ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]), .ADA12(AddressA[8]),
.ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA), .WEA(WrA), .CSA0(scuba_vlo),
.CSA1(scuba_vlo), .CSA2(scuba_vlo), .RSTA(ResetA), .DIB0(DataInB[0]),
.DIB1(DataInB[1]), .DIB2(DataInB[2]), .DIB3(DataInB[3]), .DIB4(DataInB[4]),
.DIB5(DataInB[5]), .DIB6(DataInB[6]), .DIB7(DataInB[7]), .DIB8(DataInB[8]),
.DIB9(DataInB[9]), .DIB10(DataInB[10]), .DIB11(DataInB[11]), .DIB12(DataInB[12]),
.DIB13(DataInB[13]), .DIB14(DataInB[14]), .DIB15(DataInB[15]), .DIB16(DataInB[16]),
.DIB17(DataInB[17]), .ADB0(scuba_vhi), .ADB1(scuba_vhi), .ADB2(scuba_vlo),
.ADB3(scuba_vlo), .ADB4(AddressB[0]), .ADB5(AddressB[1]), .ADB6(AddressB[2]),
.ADB7(AddressB[3]), .ADB8(AddressB[4]), .ADB9(AddressB[5]), .ADB10(AddressB[6]),
.ADB11(AddressB[7]), .ADB12(AddressB[8]), .ADB13(scuba_vlo), .CEB(ClockEnB),
.CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo),
.RSTB(ResetB), .DOA0(QA[0]), .DOA1(QA[1]), .DOA2(QA[2]), .DOA3(QA[3]),
.DOA4(QA[4]), .DOA5(QA[5]), .DOA6(QA[6]), .DOA7(QA[7]), .DOA8(QA[8]),
.DOA9(QA[9]), .DOA10(QA[10]), .DOA11(QA[11]), .DOA12(QA[12]), .DOA13(QA[13]),
.DOA14(QA[14]), .DOA15(QA[15]), .DOA16(QA[16]), .DOA17(QA[17]),
.DOB0(QB[0]), .DOB1(QB[1]), .DOB2(QB[2]), .DOB3(QB[3]), .DOB4(QB[4]),
.DOB5(QB[5]), .DOB6(QB[6]), .DOB7(QB[7]), .DOB8(QB[8]), .DOB9(QB[9]),
.DOB10(QB[10]), .DOB11(QB[11]), .DOB12(QB[12]), .DOB13(QB[13]),
.DOB14(QB[14]), .DOB15(QB[15]), .DOB16(QB[16]), .DOB17(QB[17]))
/* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_19="0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81" */
/* synthesis INITVAL_18="0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000" */
/* synthesis INITVAL_17="0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000" */
/* synthesis INITVAL_16="0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1" */
/* synthesis INITVAL_15="0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012" */
/* synthesis INITVAL_14="0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800" */
/* synthesis INITVAL_13="0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004" */
/* synthesis INITVAL_12="0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000" */
/* synthesis INITVAL_11="0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000" */
/* synthesis INITVAL_10="0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010" */
/* synthesis INITVAL_0F="0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3" */
/* synthesis INITVAL_0E="0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED" */
/* synthesis INITVAL_0D="0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000" */
/* synthesis INITVAL_0C="0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078" */
/* synthesis INITVAL_0B="0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034" */
/* synthesis INITVAL_0A="0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098" */
/* synthesis INITVAL_09="0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054" */
/* synthesis INITVAL_08="0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014" */
/* synthesis INITVAL_07="0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF" */
/* synthesis INITVAL_06="0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C" */
/* synthesis INITVAL_05="0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C" */
/* synthesis INITVAL_04="0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000" */
/* synthesis INITVAL_03="0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000" */
/* synthesis INITVAL_02="0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000" */
/* synthesis INITVAL_01="0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000" */
/* synthesis INITVAL_00="0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000" */
/* synthesis CSDECODE_B="0b000" */
/* synthesis CSDECODE_A="0b000" */
/* synthesis WRITEMODE_B="NORMAL" */
/* synthesis WRITEMODE_A="NORMAL" */
/* synthesis GSR="DISABLED" */
/* synthesis RESETMODE="SYNC" */
/* synthesis REGMODE_B="NOREG" */
/* synthesis REGMODE_A="NOREG" */
/* synthesis DATA_WIDTH_B="18" */
/* synthesis DATA_WIDTH_A="18" */;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
// synopsys translate_off
defparam sc_rom_monitor_0_1_0.INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000 ;
defparam sc_rom_monitor_0_1_0.INITVAL_19 = 320'h000000000000000000000000000000000000000000000000000000000000000000000000000038FF ;
defparam sc_rom_monitor_0_1_0.INITVAL_18 = 320'h034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482 ;
defparam sc_rom_monitor_0_1_0.INITVAL_17 = 320'h038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03 ;
defparam sc_rom_monitor_0_1_0.INITVAL_16 = 320'h02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF ;
defparam sc_rom_monitor_0_1_0.INITVAL_15 = 320'h03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10 ;
defparam sc_rom_monitor_0_1_0.INITVAL_14 = 320'h0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70 ;
defparam sc_rom_monitor_0_1_0.INITVAL_13 = 320'h024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7 ;
defparam sc_rom_monitor_0_1_0.INITVAL_12 = 320'h00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418 ;
defparam sc_rom_monitor_0_1_0.INITVAL_11 = 320'h00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84 ;
defparam sc_rom_monitor_0_1_0.INITVAL_10 = 320'h00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4 ;
defparam sc_rom_monitor_0_1_0.INITVAL_0F = 320'h016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF ;
defparam sc_rom_monitor_0_1_0.INITVAL_0E = 320'h010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF ;
defparam sc_rom_monitor_0_1_0.INITVAL_0D = 320'h016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478 ;
defparam sc_rom_monitor_0_1_0.INITVAL_0C = 320'h011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7 ;
defparam sc_rom_monitor_0_1_0.INITVAL_0B = 320'h00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3 ;
defparam sc_rom_monitor_0_1_0.INITVAL_0A = 320'h00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7 ;
defparam sc_rom_monitor_0_1_0.INITVAL_09 = 320'h0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5 ;
defparam sc_rom_monitor_0_1_0.INITVAL_08 = 320'h00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1 ;
defparam sc_rom_monitor_0_1_0.INITVAL_07 = 320'h00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808 ;
defparam sc_rom_monitor_0_1_0.INITVAL_06 = 320'h00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE ;
defparam sc_rom_monitor_0_1_0.INITVAL_05 = 320'h016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA ;
defparam sc_rom_monitor_0_1_0.INITVAL_04 = 320'h016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8 ;
defparam sc_rom_monitor_0_1_0.INITVAL_03 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam sc_rom_monitor_0_1_0.INITVAL_02 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam sc_rom_monitor_0_1_0.INITVAL_01 = 320'h0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600 ;
defparam sc_rom_monitor_0_1_0.INITVAL_00 = 320'h0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600 ;
defparam sc_rom_monitor_0_1_0.CSDECODE_B = 3'b000 ;
defparam sc_rom_monitor_0_1_0.CSDECODE_A = 3'b000 ;
defparam sc_rom_monitor_0_1_0.WRITEMODE_B = "NORMAL" ;
defparam sc_rom_monitor_0_1_0.WRITEMODE_A = "NORMAL" ;
defparam sc_rom_monitor_0_1_0.GSR = "DISABLED" ;
defparam sc_rom_monitor_0_1_0.RESETMODE = "SYNC" ;
defparam sc_rom_monitor_0_1_0.REGMODE_B = "NOREG" ;
defparam sc_rom_monitor_0_1_0.REGMODE_A = "NOREG" ;
defparam sc_rom_monitor_0_1_0.DATA_WIDTH_B = 18 ;
defparam sc_rom_monitor_0_1_0.DATA_WIDTH_A = 18 ;
// synopsys translate_on
DP16KA sc_rom_monitor_0_1_0 (.DIA0(DataInA[18]), .DIA1(DataInA[19]),
.DIA2(DataInA[20]), .DIA3(DataInA[21]), .DIA4(DataInA[22]), .DIA5(DataInA[23]),
.DIA6(DataInA[24]), .DIA7(DataInA[25]), .DIA8(DataInA[26]), .DIA9(DataInA[27]),
.DIA10(DataInA[28]), .DIA11(DataInA[29]), .DIA12(DataInA[30]), .DIA13(DataInA[31]),
.DIA14(scuba_vlo), .DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo),
.ADA0(scuba_vhi), .ADA1(scuba_vhi), .ADA2(scuba_vlo), .ADA3(scuba_vlo),
.ADA4(AddressA[0]), .ADA5(AddressA[1]), .ADA6(AddressA[2]), .ADA7(AddressA[3]),
.ADA8(AddressA[4]), .ADA9(AddressA[5]), .ADA10(AddressA[6]), .ADA11(AddressA[7]),
.ADA12(AddressA[8]), .ADA13(scuba_vlo), .CEA(ClockEnA), .CLKA(ClockA),
.WEA(WrA), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
.RSTA(ResetA), .DIB0(DataInB[18]), .DIB1(DataInB[19]), .DIB2(DataInB[20]),
.DIB3(DataInB[21]), .DIB4(DataInB[22]), .DIB5(DataInB[23]), .DIB6(DataInB[24]),
.DIB7(DataInB[25]), .DIB8(DataInB[26]), .DIB9(DataInB[27]), .DIB10(DataInB[28]),
.DIB11(DataInB[29]), .DIB12(DataInB[30]), .DIB13(DataInB[31]), .DIB14(scuba_vlo),
.DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vhi),
.ADB1(scuba_vhi), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(AddressB[0]),
.ADB5(AddressB[1]), .ADB6(AddressB[2]), .ADB7(AddressB[3]), .ADB8(AddressB[4]),
.ADB9(AddressB[5]), .ADB10(AddressB[6]), .ADB11(AddressB[7]), .ADB12(AddressB[8]),
.ADB13(scuba_vlo), .CEB(ClockEnB), .CLKB(ClockB), .WEB(WrB), .CSB0(scuba_vlo),
.CSB1(scuba_vlo), .CSB2(scuba_vlo), .RSTB(ResetB), .DOA0(QA[18]),
.DOA1(QA[19]), .DOA2(QA[20]), .DOA3(QA[21]), .DOA4(QA[22]), .DOA5(QA[23]),
.DOA6(QA[24]), .DOA7(QA[25]), .DOA8(QA[26]), .DOA9(QA[27]), .DOA10(QA[28]),
.DOA11(QA[29]), .DOA12(QA[30]), .DOA13(QA[31]), .DOA14(), .DOA15(),
.DOA16(), .DOA17(), .DOB0(QB[18]), .DOB1(QB[19]), .DOB2(QB[20]),
.DOB3(QB[21]), .DOB4(QB[22]), .DOB5(QB[23]), .DOB6(QB[24]), .DOB7(QB[25]),
.DOB8(QB[26]), .DOB9(QB[27]), .DOB10(QB[28]), .DOB11(QB[29]), .DOB12(QB[30]),
.DOB13(QB[31]), .DOB14(), .DOB15(), .DOB16(), .DOB17())
/* synthesis MEM_LPC_FILE="sc_rom_monitor.lpc" */
/* synthesis MEM_INIT_FILE="lm32_monitor.mem" */
/* synthesis INITVAL_3F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_3A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_39="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_38="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_37="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_36="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_35="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_34="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_33="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_32="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_31="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_30="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_2A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_29="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_28="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_27="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_26="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_25="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_24="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_23="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_22="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_21="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_20="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1F="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1E="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1D="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1C="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1B="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_1A="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" */
/* synthesis INITVAL_19="0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF" */
/* synthesis INITVAL_18="0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482" */
/* synthesis INITVAL_17="0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03" */
/* synthesis INITVAL_16="0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF" */
/* synthesis INITVAL_15="0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10" */
/* synthesis INITVAL_14="0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70" */
/* synthesis INITVAL_13="0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7" */
/* synthesis INITVAL_12="0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418" */
/* synthesis INITVAL_11="0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84" */
/* synthesis INITVAL_10="0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4" */
/* synthesis INITVAL_0F="0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF" */
/* synthesis INITVAL_0E="0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF" */
/* synthesis INITVAL_0D="0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478" */
/* synthesis INITVAL_0C="0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7" */
/* synthesis INITVAL_0B="0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3" */
/* synthesis INITVAL_0A="0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7" */
/* synthesis INITVAL_09="0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5" */
/* synthesis INITVAL_08="0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1" */
/* synthesis INITVAL_07="0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808" */
/* synthesis INITVAL_06="0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE" */
/* synthesis INITVAL_05="0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA" */
/* synthesis INITVAL_04="0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8" */
/* synthesis INITVAL_03="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_02="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_01="0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600" */
/* synthesis INITVAL_00="0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600" */
/* synthesis CSDECODE_B="0b000" */
/* synthesis CSDECODE_A="0b000" */
/* synthesis WRITEMODE_B="NORMAL" */
/* synthesis WRITEMODE_A="NORMAL" */
/* synthesis GSR="DISABLED" */
/* synthesis RESETMODE="SYNC" */
/* synthesis REGMODE_B="NOREG" */
/* synthesis REGMODE_A="NOREG" */
/* synthesis DATA_WIDTH_B="18" */
/* synthesis DATA_WIDTH_A="18" */;
// exemplar begin
// exemplar attribute sc_rom_monitor_0_0_1 MEM_LPC_FILE sc_rom_monitor.lpc
// exemplar attribute sc_rom_monitor_0_0_1 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_19 0x0000000000000000000000000000000000000000000000000000000000000000000000000003FF81
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_18 0x300003FF83300003FF85300003FF873FF4A1004F3FF8A300003FF8C300003FF8E300003FF9030000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_17 0x3FF92300003FF94300003FF96300003FFC100800070003FFFB0000130001100003FF5B1001700000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_16 0x068003FF70058003FF723FFFB300013FF6A00001100001FFAB00000068003FF7B058003FF7D3FFB1
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_15 0x3FF8D008003FFB4300000FFB61001B000361001A0002F10019000381001800038100130003310012
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_14 0x00033100110003310010000331000900033100080003310007010003FF89058003FF9C3FFF900800
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_13 0x070000FFFB30800070003FFD63FFB200800000041000A0004110006010003FF9A000000002410004
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_12 0x200081000C0001030014200181001C00020300240000000000000001000000000000000000010000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_11 0x100010FFF310063000501004D000471006D00046100720002C100570001F10077010003FFBC00000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_10 0x30000044003FC0010000100540FFFF0080010000100540FFFF008000880010004200081000C00010
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0F 0x30014200181001C00020300240FFDC0000000008100043FFDD100083FFDF100093FFE11000A3FFE3
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0E 0x1000B10008100040FFF8000000000C1000410008100083FFE7100093FFE91000A3FFEB1000B3FFED
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0D 0x100040FFF400000200000FFFF01000000000000210054100000FFFF01000100FF00000100FF00000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0C 0x0FFFE1010001000000000007430084200002009830000300943000030090300003008C2007C10078
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0B 0x300702006C1006800064300602005C1005800054300502004C1004800044300402003C1003800034
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_0A 0x300302002C1002800024300202001C1001800014300102000C100080000000074200842000020098
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_09 0x20000200942000020090200002008C3008010078300702006C1006800064300602005C1005800054
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_08 0x300502004C1004800044300402003C1003800034300302002C1002800024300202001C1001800014
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_07 0x300102000C10008000001F9A00E000000041007810000100881000110001100011000110001100FF
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_06 0x1F9A0100940080010090008001008C008001009C008001009800800300802007C00074300702006C
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_05 0x1006800064300602005C1005800054300502004C1004800044300402003C1003800034300302002C
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_04 0x1002800024300202001C1001800014300102000C100080000000000106603FFC530000007F40E000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_03 0x0003E000BC1000400800200840000A000000000000046000C4100040080020084000120000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_02 0x0004E000CC1000400800200840001A000000000000056000D4100040080020084000220000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_01 0x00086000DC1000400800300840002A000000000000066000E4100040080020084000320000000000
// exemplar attribute sc_rom_monitor_0_0_1 INITVAL_00 0x00096000EC1000400800300840003A000000000000000000000000000000000000003E0000000000
// exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_B 0b000
// exemplar attribute sc_rom_monitor_0_0_1 CSDECODE_A 0b000
// exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_B NORMAL
// exemplar attribute sc_rom_monitor_0_0_1 WRITEMODE_A NORMAL
// exemplar attribute sc_rom_monitor_0_0_1 GSR DISABLED
// exemplar attribute sc_rom_monitor_0_0_1 RESETMODE SYNC
// exemplar attribute sc_rom_monitor_0_0_1 REGMODE_B NOREG
// exemplar attribute sc_rom_monitor_0_0_1 REGMODE_A NOREG
// exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_B 18
// exemplar attribute sc_rom_monitor_0_0_1 DATA_WIDTH_A 18
// exemplar attribute sc_rom_monitor_0_1_0 MEM_LPC_FILE sc_rom_monitor.lpc
// exemplar attribute sc_rom_monitor_0_1_0 MEM_INIT_FILE lm32_monitor.mem
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_3A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_39 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_38 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_37 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_36 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_35 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_34 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_33 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_32 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_31 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_30 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_2A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_29 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_28 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_27 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_26 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_25 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_24 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_23 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_22 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_21 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_20 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1F 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1E 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1D 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1C 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1B 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_1A 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_19 0x000000000000000000000000000000000000000000000000000000000000000000000000000038FF
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_18 0x034D2038FF034C2038FF0349A038FF03EFF00D00038FF034CA038FF03492038FF0348A038FF03482
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_17 0x038FF0344A038FF03442038FF0343A038FF02E7002430038FF00D6300D5A00C5803EFF0136300D03
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_16 0x02E0803EFF02E0803EFF038FF00D5A03EFF00D63010580136300D0302E0803EFF02E0803EFF038FF
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_15 0x03EFF02E88038FF034DA0170801F100110801F100110801F100110801F100110801F100110801F10
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_14 0x0110801F100110801F100110801F100110801F100110801F0802E0803EFF02E0803EFF038FF02E70
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_13 0x024500110C0287302430038FF03EFF02E700110801F100110801F0802E0803EFF030E800DE700AE7
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_12 0x00AE400AE400AE400AE300AE300AE300AE300AE200D0000D0000D000342000D0000D0000D0003418
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_11 0x00D000170801F100110801F100110801F100110801F100110801F100110801F0802E0803EFF00E84
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_10 0x00E7B01E0401E030347000D0001708024700347000D00017080247002E08016E7016E4016E4016E4
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0F 0x016E3016E3016E3016E3016E200DE7030E800DE700AE703EFF010E003EFF010E003EFF010E003EFF
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0E 0x010E0016E0016E700DE7030E800DE700AE700AE000CE003EFF00CE003EFF00CE003EFF00CE003EFF
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0D 0x016E700DE7030E8034700171002470030E80110801F0803470017100247000808030E80081003478
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0C 0x011080081002478030F800AE700AE70340F00AE70340700AE70344F00AE70343F00AE700AE700AE7
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0B 0x00AE600AE600AE600AE600AE500AE500AE500AE500AE400AE400AE400AE400AE300AE300AE300AE3
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_0A 0x00AE200AE200AE200AE200AE100AE100AE100AE100AE000AE000AE0030F000AE700AE70340F00AE7
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_09 0x0340700AE70344F00AE70343F00AE700AE700AE700AE600AE600AE600AE600AE500AE500AE500AE5
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_08 0x00AE400AE400AE400AE400AE300AE300AE300AE300AE200AE200AE200AE200AE100AE100AE100AE1
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_07 0x00AE000AE000AE0030E800DEF02EE8016E8016E800AE8016E8000080000800008000080000800808
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_06 0x00DE8016E802400016E802448016E802438016E802410016E802408016EF016EF016EF016EE016EE
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_05 0x016EE016EE016ED016ED016ED016ED016EC016EC016EC016EC016EB016EB016EB016EB016EA016EA
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_04 0x016EA016EA016E9016E9016E9016E9016E8016E8016E802600016E800DEF038FF00D0700DE702EE8
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_03 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_02 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_01 0x0380003E0000D0802EE0016E703E0002EE8026000380003E0000D0802EE0016E703E0002EE802600
// exemplar attribute sc_rom_monitor_0_1_0 INITVAL_00 0x0380003E0000D0802EE0016E703E0002EE80260000D0000D0000D0000D0000D0003E000340802600
// exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_B 0b000
// exemplar attribute sc_rom_monitor_0_1_0 CSDECODE_A 0b000
// exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_B NORMAL
// exemplar attribute sc_rom_monitor_0_1_0 WRITEMODE_A NORMAL
// exemplar attribute sc_rom_monitor_0_1_0 GSR DISABLED
// exemplar attribute sc_rom_monitor_0_1_0 RESETMODE SYNC
// exemplar attribute sc_rom_monitor_0_1_0 REGMODE_B NOREG
// exemplar attribute sc_rom_monitor_0_1_0 REGMODE_A NOREG
// exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_B 18
// exemplar attribute sc_rom_monitor_0_1_0 DATA_WIDTH_A 18
// exemplar end
end
endgenerate
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: cx4_mul.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cx4_mul (
clock,
dataa,
datab,
result);
input clock;
input [23:0] dataa;
input [23:0] datab;
output [47:0] result;
wire [47:0] sub_wire0;
wire [47:0] result = sub_wire0[47:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 2,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 24,
lpm_mult_component.lpm_widthb = 24,
lpm_mult_component.lpm_widthp = 48;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "24"
// Retrieval info: PRIVATE: WidthB NUMERIC "24"
// Retrieval info: PRIVATE: WidthP NUMERIC "48"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "48"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 24 0 INPUT NODEFVAL "dataa[23..0]"
// Retrieval info: USED_PORT: datab 0 0 24 0 INPUT NODEFVAL "datab[23..0]"
// Retrieval info: USED_PORT: result 0 0 48 0 OUTPUT NODEFVAL "result[47..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 24 0 dataa 0 0 24 0
// Retrieval info: CONNECT: @datab 0 0 24 0 datab 0 0 24 0
// Retrieval info: CONNECT: result 0 0 48 0 @result 0 0 48 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_mul_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`include "e200_defines.v"
module tb_top();
reg clk;
reg lfextclk;
reg rst_n;
wire hfclk = clk;
`define CPU_TOP u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top
`define EXU `CPU_TOP.u_e200_cpu.u_e200_core.u_e200_exu
`define ITCM `CPU_TOP.u_e200_srams.u_e200_itcm_ram.u_e200_itcm_gnrl_ram.u_sirv_sim_ram
`define PC_WRITE_TOHOST `E200_PC_SIZE'h80000086
`define PC_EXT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000a6
`define PC_SFT_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000be
`define PC_TMR_IRQ_BEFOR_MRET `E200_PC_SIZE'h800000d6
`define PC_AFTER_SETMTVEC `E200_PC_SIZE'h8000015C
wire [`E200_XLEN-1:0] x3 = `EXU.u_e200_exu_regfile.rf_r[3];
wire [`E200_PC_SIZE-1:0] pc = `EXU.u_e200_exu_commit.alu_cmt_i_pc;
wire [`E200_PC_SIZE-1:0] pc_vld = `EXU.u_e200_exu_commit.alu_cmt_i_valid;
reg [31:0] pc_write_to_host_cnt;
reg [31:0] pc_write_to_host_cycle;
reg [31:0] valid_ir_cycle;
reg [31:0] cycle_count;
reg pc_write_to_host_flag;
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
pc_write_to_host_cnt <= 32'b0;
pc_write_to_host_flag <= 1'b0;
pc_write_to_host_cycle <= 32'b0;
end
else if (pc_vld & (pc == `PC_WRITE_TOHOST)) begin
pc_write_to_host_cnt <= pc_write_to_host_cnt + 1'b1;
pc_write_to_host_flag <= 1'b1;
if (pc_write_to_host_flag == 1'b0) begin
pc_write_to_host_cycle <= cycle_count;
end
end
end
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
cycle_count <= 32'b0;
end
else begin
cycle_count <= cycle_count + 1'b1;
end
end
wire i_valid = `EXU.i_valid;
wire i_ready = `EXU.i_ready;
always @(posedge hfclk or negedge rst_n)
begin
if(rst_n == 1'b0) begin
valid_ir_cycle <= 32'b0;
end
else if(i_valid & i_ready & (pc_write_to_host_flag == 1'b0)) begin
valid_ir_cycle <= valid_ir_cycle + 1'b1;
end
end
// Randomly force the external interrupt
`define EXT_IRQ u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.plic_ext_irq
`define SFT_IRQ u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_sft_irq
`define TMR_IRQ u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.clint_tmr_irq
`define U_CPU u_e200_soc_top.u_e200_subsys_top.u_e200_subsys_main.u_e200_cpu_top.u_e200_cpu
`define ITCM_BUS_ERR `U_CPU.u_e200_itcm_ctrl.sram_icb_rsp_err
`define ITCM_BUS_READ `U_CPU.u_e200_itcm_ctrl.sram_icb_rsp_read
`define STATUS_MIE `U_CPU.u_e200_core.u_e200_exu.u_e200_exu_commit.u_e200_exu_excp.status_mie_r
wire stop_assert_irq = (pc_write_to_host_cnt > 32);
reg tb_itcm_bus_err;
reg tb_ext_irq;
reg tb_tmr_irq;
reg tb_sft_irq;
initial begin
tb_ext_irq = 1'b0;
tb_tmr_irq = 1'b0;
tb_sft_irq = 1'b0;
end
`ifdef ENABLE_TB_FORCE
initial begin
tb_itcm_bus_err = 1'b0;
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 20)) @(posedge clk) tb_itcm_bus_err = 1'b0; // Wait random times
repeat ($urandom_range(1, 200)) @(posedge clk) tb_itcm_bus_err = 1'b1; // Wait random times
if(stop_assert_irq) begin
break;
end
end
end
initial begin
force `EXT_IRQ = tb_ext_irq;
force `SFT_IRQ = tb_sft_irq;
force `TMR_IRQ = tb_tmr_irq;
// We force the bus-error only when:
// It is in common code, not in exception code, by checking MIE bit
// It is in read operation, not write, otherwise the test cannot recover
force `ITCM_BUS_ERR = tb_itcm_bus_err
& `STATUS_MIE
& `ITCM_BUS_READ
;
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 1000)) @(posedge clk) tb_ext_irq = 1'b0; // Wait random times
tb_ext_irq = 1'b1; // assert the irq
@((pc == `PC_EXT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_ext_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 1000)) @(posedge clk) tb_sft_irq = 1'b0; // Wait random times
tb_sft_irq = 1'b1; // assert the irq
@((pc == `PC_SFT_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_sft_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
initial begin
#100
@(pc == `PC_AFTER_SETMTVEC ) // Wait the program goes out the reset_vector program
forever begin
repeat ($urandom_range(1, 1000)) @(posedge clk) tb_tmr_irq = 1'b0; // Wait random times
tb_tmr_irq = 1'b1; // assert the irq
@((pc == `PC_TMR_IRQ_BEFOR_MRET)) // Wait the program run into the IRQ handler by check PC values
tb_tmr_irq = 1'b0;
if(stop_assert_irq) begin
break;
end
end
end
`endif
reg[8*300:1] testcase;
integer dumpwave;
initial begin
$display("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
if($value$plusargs("TESTCASE=%s",testcase))begin
$display("TESTCASE=%s",testcase);
end
pc_write_to_host_flag <=0;
clk <=0;
lfextclk <=0;
rst_n <=0;
#120 rst_n <=1;
@(pc_write_to_host_cnt == 32'd8) #10 rst_n <=1;
`ifdef ENABLE_TB_FORCE
@((~tb_tmr_irq) & (~tb_sft_irq) & (~tb_ext_irq)) #10 rst_n <=1;// Wait the interrupt to complete
`endif
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~ Test Result Summary ~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~TESTCASE: %s ~~~~~~~~~~~~~", testcase);
$display("~~~~~~~~~~~~~~Total cycle_count value: %d ~~~~~~~~~~~~~", cycle_count);
$display("~~~~~~~~~~The valid Instruction Count: %d ~~~~~~~~~~~~~", valid_ir_cycle);
$display("~~~~~The test ending reached at cycle: %d ~~~~~~~~~~~~~", pc_write_to_host_cycle);
$display("~~~~~~~~~~~~~~~The final x3 Reg value: %d ~~~~~~~~~~~~~", x3);
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
if (x3 == 1) begin
$display("~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # # # # #~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end
else begin
$display("~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # # ~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~# # # # ######~~~~~~~~~~~~~~~~");
$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
end
#10
$finish;
end
initial begin
#40000000
$display("Time Out !!!");
$finish;
end
always
begin
#2 clk <= ~clk;
end
always
begin
#33 lfextclk <= ~lfextclk;
end
initial begin
$value$plusargs("DUMPWAVE=%d",dumpwave);
if(dumpwave != 0)begin
// To add your waveform generation function
end
end
integer i;
reg [7:0] itcm_mem [0:(`E200_ITCM_RAM_DP*8)-1];
initial begin
$readmemh({testcase, ".verilog"}, itcm_mem);
for (i=0;i<(`E200_ITCM_RAM_DP);i=i+1) begin
`ITCM.mem_r[i][00+7:00] = itcm_mem[i*8+0];
`ITCM.mem_r[i][08+7:08] = itcm_mem[i*8+1];
`ITCM.mem_r[i][16+7:16] = itcm_mem[i*8+2];
`ITCM.mem_r[i][24+7:24] = itcm_mem[i*8+3];
`ITCM.mem_r[i][32+7:32] = itcm_mem[i*8+4];
`ITCM.mem_r[i][40+7:40] = itcm_mem[i*8+5];
`ITCM.mem_r[i][48+7:48] = itcm_mem[i*8+6];
`ITCM.mem_r[i][56+7:56] = itcm_mem[i*8+7];
end
$display("ITCM 0x00: %h", `ITCM.mem_r[8'h00]);
$display("ITCM 0x01: %h", `ITCM.mem_r[8'h01]);
$display("ITCM 0x02: %h", `ITCM.mem_r[8'h02]);
$display("ITCM 0x03: %h", `ITCM.mem_r[8'h03]);
$display("ITCM 0x04: %h", `ITCM.mem_r[8'h04]);
$display("ITCM 0x05: %h", `ITCM.mem_r[8'h05]);
$display("ITCM 0x06: %h", `ITCM.mem_r[8'h06]);
$display("ITCM 0x07: %h", `ITCM.mem_r[8'h07]);
$display("ITCM 0x16: %h", `ITCM.mem_r[8'h16]);
$display("ITCM 0x20: %h", `ITCM.mem_r[8'h20]);
end
wire jtag_TDI = 1'b0;
wire jtag_TDO;
wire jtag_TCK = 1'b0;
wire jtag_TMS = 1'b0;
wire jtag_TRST = 1'b0;
wire jtag_DRV_TDO = 1'b0;
e200_soc_top u_e200_soc_top(
.hfextclk(hfclk),
.hfxoscen(),
.lfextclk(lfextclk),
.lfxoscen(),
.io_pads_jtag_TCK_i_ival (jtag_TCK),
.io_pads_jtag_TMS_i_ival (jtag_TMS),
.io_pads_jtag_TDI_i_ival (jtag_TDI),
.io_pads_jtag_TDO_o_oval (jtag_TDO),
.io_pads_jtag_TDO_o_oe (),
.io_pads_gpio_0_i_ival (1'b1),
.io_pads_gpio_0_o_oval (),
.io_pads_gpio_0_o_oe (),
.io_pads_gpio_0_o_ie (),
.io_pads_gpio_0_o_pue (),
.io_pads_gpio_0_o_ds (),
.io_pads_gpio_1_i_ival (1'b1),
.io_pads_gpio_1_o_oval (),
.io_pads_gpio_1_o_oe (),
.io_pads_gpio_1_o_ie (),
.io_pads_gpio_1_o_pue (),
.io_pads_gpio_1_o_ds (),
.io_pads_gpio_2_i_ival (1'b1),
.io_pads_gpio_2_o_oval (),
.io_pads_gpio_2_o_oe (),
.io_pads_gpio_2_o_ie (),
.io_pads_gpio_2_o_pue (),
.io_pads_gpio_2_o_ds (),
.io_pads_gpio_3_i_ival (1'b1),
.io_pads_gpio_3_o_oval (),
.io_pads_gpio_3_o_oe (),
.io_pads_gpio_3_o_ie (),
.io_pads_gpio_3_o_pue (),
.io_pads_gpio_3_o_ds (),
.io_pads_gpio_4_i_ival (1'b1),
.io_pads_gpio_4_o_oval (),
.io_pads_gpio_4_o_oe (),
.io_pads_gpio_4_o_ie (),
.io_pads_gpio_4_o_pue (),
.io_pads_gpio_4_o_ds (),
.io_pads_gpio_5_i_ival (1'b1),
.io_pads_gpio_5_o_oval (),
.io_pads_gpio_5_o_oe (),
.io_pads_gpio_5_o_ie (),
.io_pads_gpio_5_o_pue (),
.io_pads_gpio_5_o_ds (),
.io_pads_gpio_6_i_ival (1'b1),
.io_pads_gpio_6_o_oval (),
.io_pads_gpio_6_o_oe (),
.io_pads_gpio_6_o_ie (),
.io_pads_gpio_6_o_pue (),
.io_pads_gpio_6_o_ds (),
.io_pads_gpio_7_i_ival (1'b1),
.io_pads_gpio_7_o_oval (),
.io_pads_gpio_7_o_oe (),
.io_pads_gpio_7_o_ie (),
.io_pads_gpio_7_o_pue (),
.io_pads_gpio_7_o_ds (),
.io_pads_gpio_8_i_ival (1'b1),
.io_pads_gpio_8_o_oval (),
.io_pads_gpio_8_o_oe (),
.io_pads_gpio_8_o_ie (),
.io_pads_gpio_8_o_pue (),
.io_pads_gpio_8_o_ds (),
.io_pads_gpio_9_i_ival (1'b1),
.io_pads_gpio_9_o_oval (),
.io_pads_gpio_9_o_oe (),
.io_pads_gpio_9_o_ie (),
.io_pads_gpio_9_o_pue (),
.io_pads_gpio_9_o_ds (),
.io_pads_gpio_10_i_ival (1'b1),
.io_pads_gpio_10_o_oval (),
.io_pads_gpio_10_o_oe (),
.io_pads_gpio_10_o_ie (),
.io_pads_gpio_10_o_pue (),
.io_pads_gpio_10_o_ds (),
.io_pads_gpio_11_i_ival (1'b1),
.io_pads_gpio_11_o_oval (),
.io_pads_gpio_11_o_oe (),
.io_pads_gpio_11_o_ie (),
.io_pads_gpio_11_o_pue (),
.io_pads_gpio_11_o_ds (),
.io_pads_gpio_12_i_ival (1'b1),
.io_pads_gpio_12_o_oval (),
.io_pads_gpio_12_o_oe (),
.io_pads_gpio_12_o_ie (),
.io_pads_gpio_12_o_pue (),
.io_pads_gpio_12_o_ds (),
.io_pads_gpio_13_i_ival (1'b1),
.io_pads_gpio_13_o_oval (),
.io_pads_gpio_13_o_oe (),
.io_pads_gpio_13_o_ie (),
.io_pads_gpio_13_o_pue (),
.io_pads_gpio_13_o_ds (),
.io_pads_gpio_14_i_ival (1'b1),
.io_pads_gpio_14_o_oval (),
.io_pads_gpio_14_o_oe (),
.io_pads_gpio_14_o_ie (),
.io_pads_gpio_14_o_pue (),
.io_pads_gpio_14_o_ds (),
.io_pads_gpio_15_i_ival (1'b1),
.io_pads_gpio_15_o_oval (),
.io_pads_gpio_15_o_oe (),
.io_pads_gpio_15_o_ie (),
.io_pads_gpio_15_o_pue (),
.io_pads_gpio_15_o_ds (),
.io_pads_gpio_16_i_ival (1'b1),
.io_pads_gpio_16_o_oval (),
.io_pads_gpio_16_o_oe (),
.io_pads_gpio_16_o_ie (),
.io_pads_gpio_16_o_pue (),
.io_pads_gpio_16_o_ds (),
.io_pads_gpio_17_i_ival (1'b1),
.io_pads_gpio_17_o_oval (),
.io_pads_gpio_17_o_oe (),
.io_pads_gpio_17_o_ie (),
.io_pads_gpio_17_o_pue (),
.io_pads_gpio_17_o_ds (),
.io_pads_gpio_18_i_ival (1'b1),
.io_pads_gpio_18_o_oval (),
.io_pads_gpio_18_o_oe (),
.io_pads_gpio_18_o_ie (),
.io_pads_gpio_18_o_pue (),
.io_pads_gpio_18_o_ds (),
.io_pads_gpio_19_i_ival (1'b1),
.io_pads_gpio_19_o_oval (),
.io_pads_gpio_19_o_oe (),
.io_pads_gpio_19_o_ie (),
.io_pads_gpio_19_o_pue (),
.io_pads_gpio_19_o_ds (),
.io_pads_gpio_20_i_ival (1'b1),
.io_pads_gpio_20_o_oval (),
.io_pads_gpio_20_o_oe (),
.io_pads_gpio_20_o_ie (),
.io_pads_gpio_20_o_pue (),
.io_pads_gpio_20_o_ds (),
.io_pads_gpio_21_i_ival (1'b1),
.io_pads_gpio_21_o_oval (),
.io_pads_gpio_21_o_oe (),
.io_pads_gpio_21_o_ie (),
.io_pads_gpio_21_o_pue (),
.io_pads_gpio_21_o_ds (),
.io_pads_gpio_22_i_ival (1'b1),
.io_pads_gpio_22_o_oval (),
.io_pads_gpio_22_o_oe (),
.io_pads_gpio_22_o_ie (),
.io_pads_gpio_22_o_pue (),
.io_pads_gpio_22_o_ds (),
.io_pads_gpio_23_i_ival (1'b1),
.io_pads_gpio_23_o_oval (),
.io_pads_gpio_23_o_oe (),
.io_pads_gpio_23_o_ie (),
.io_pads_gpio_23_o_pue (),
.io_pads_gpio_23_o_ds (),
.io_pads_gpio_24_i_ival (1'b1),
.io_pads_gpio_24_o_oval (),
.io_pads_gpio_24_o_oe (),
.io_pads_gpio_24_o_ie (),
.io_pads_gpio_24_o_pue (),
.io_pads_gpio_24_o_ds (),
.io_pads_gpio_25_i_ival (1'b1),
.io_pads_gpio_25_o_oval (),
.io_pads_gpio_25_o_oe (),
.io_pads_gpio_25_o_ie (),
.io_pads_gpio_25_o_pue (),
.io_pads_gpio_25_o_ds (),
.io_pads_gpio_26_i_ival (1'b1),
.io_pads_gpio_26_o_oval (),
.io_pads_gpio_26_o_oe (),
.io_pads_gpio_26_o_ie (),
.io_pads_gpio_26_o_pue (),
.io_pads_gpio_26_o_ds (),
.io_pads_gpio_27_i_ival (1'b1),
.io_pads_gpio_27_o_oval (),
.io_pads_gpio_27_o_oe (),
.io_pads_gpio_27_o_ie (),
.io_pads_gpio_27_o_pue (),
.io_pads_gpio_27_o_ds (),
.io_pads_gpio_28_i_ival (1'b1),
.io_pads_gpio_28_o_oval (),
.io_pads_gpio_28_o_oe (),
.io_pads_gpio_28_o_ie (),
.io_pads_gpio_28_o_pue (),
.io_pads_gpio_28_o_ds (),
.io_pads_gpio_29_i_ival (1'b1),
.io_pads_gpio_29_o_oval (),
.io_pads_gpio_29_o_oe (),
.io_pads_gpio_29_o_ie (),
.io_pads_gpio_29_o_pue (),
.io_pads_gpio_29_o_ds (),
.io_pads_gpio_30_i_ival (1'b1),
.io_pads_gpio_30_o_oval (),
.io_pads_gpio_30_o_oe (),
.io_pads_gpio_30_o_ie (),
.io_pads_gpio_30_o_pue (),
.io_pads_gpio_30_o_ds (),
.io_pads_gpio_31_i_ival (1'b1),
.io_pads_gpio_31_o_oval (),
.io_pads_gpio_31_o_oe (),
.io_pads_gpio_31_o_ie (),
.io_pads_gpio_31_o_pue (),
.io_pads_gpio_31_o_ds (),
.io_pads_qspi_sck_o_oval (),
.io_pads_qspi_dq_0_i_ival (1'b1),
.io_pads_qspi_dq_0_o_oval (),
.io_pads_qspi_dq_0_o_oe (),
.io_pads_qspi_dq_0_o_ie (),
.io_pads_qspi_dq_0_o_pue (),
.io_pads_qspi_dq_0_o_ds (),
.io_pads_qspi_dq_1_i_ival (1'b1),
.io_pads_qspi_dq_1_o_oval (),
.io_pads_qspi_dq_1_o_oe (),
.io_pads_qspi_dq_1_o_ie (),
.io_pads_qspi_dq_1_o_pue (),
.io_pads_qspi_dq_1_o_ds (),
.io_pads_qspi_dq_2_i_ival (1'b1),
.io_pads_qspi_dq_2_o_oval (),
.io_pads_qspi_dq_2_o_oe (),
.io_pads_qspi_dq_2_o_ie (),
.io_pads_qspi_dq_2_o_pue (),
.io_pads_qspi_dq_2_o_ds (),
.io_pads_qspi_dq_3_i_ival (1'b1),
.io_pads_qspi_dq_3_o_oval (),
.io_pads_qspi_dq_3_o_oe (),
.io_pads_qspi_dq_3_o_ie (),
.io_pads_qspi_dq_3_o_pue (),
.io_pads_qspi_dq_3_o_ds (),
.io_pads_qspi_cs_0_o_oval (),
.io_pads_aon_erst_n_i_ival (rst_n),//This is the real reset, active low
.io_pads_aon_pmu_dwakeup_n_i_ival (1'b1),
.io_pads_aon_pmu_vddpaden_o_oval (),
.io_pads_aon_pmu_padrst_o_oval (),
.io_pads_bootrom_n_i_ival (1'b0),// In Simulation we boot from ROM
.io_pads_dbgmode0_n_i_ival (1'b1),
.io_pads_dbgmode1_n_i_ival (1'b1),
.io_pads_dbgmode2_n_i_ival (1'b1)
);
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-----------------------------------------------------------------------------------------------------------------------------
// Filename : cabac_cu_binari_intra_luma_mode.v
// Author : chewein
// Created : 2014-9-11
// Description : binarization an cu , cu size is 8x8 , 16x16 , 32x32 64x64
//-----------------------------------------------------------------------------------------------------------------------------
`include"enc_defines.v"
module cabac_cu_binari_intra_luma_mode(
// input
luma_curr_mode_i ,
luma_left_mode_i ,
luma_top_mode_i ,
//output
ctx_pair_luma_mode_0_o ,
ctx_pair_luma_mode_1_o
);
//-----------------------------------------------------------------------------------------------------------------------------
//
// input signals and output signals
//
//-----------------------------------------------------------------------------------------------------------------------------
input [5:0] luma_curr_mode_i ;
input [5:0] luma_left_mode_i ;
input [5:0] luma_top_mode_i ;
output [10:0] ctx_pair_luma_mode_0_o ;
output [10:0] ctx_pair_luma_mode_1_o ;
//-----------------------------------------------------------------------------------------------------------------------------
//
// reg and wire signals declaration
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [5:0] preds_0_r , preds_1_r , preds_2_r ;
reg [1:0] pred_idx_r ;
wire preds_0_le_1_w ,preds_0_le_2_w ,preds_1_le_2_w ;
reg [5:0] preds_0_sort_r ,preds_1_sort_r ,preds_2_sort_r ;
wire [5:0] luma_curr_mode_minus1_w ;
wire [5:0] luma_curr_mode_minus2_w ;
wire [5:0] luma_curr_mode_minus3_w ;
reg [5:0] luma_mode_dir_r ;
// calculation prediction candidates : preds_0_r ,preds_1_r ,preds_2_r
always @* begin
if(luma_top_mode_i == luma_left_mode_i) begin
if(luma_left_mode_i[5:1]) begin // >6'd1
preds_0_r = luma_left_mode_i ;
preds_1_r = ((luma_left_mode_i + 6'd29)&7'd31) + 6'd2 ;
preds_2_r = ((luma_left_mode_i - 6'd1 )&7'd31) + 6'd2 ;
end
else begin
preds_0_r = 6'd0 ;
preds_1_r = 6'd1 ;
preds_2_r = 6'd26 ;
end
end
else begin
if(luma_left_mode_i && luma_top_mode_i) begin
preds_0_r = luma_left_mode_i ;
preds_1_r = luma_top_mode_i ;
preds_2_r = 6'd0 ;
end
else begin
preds_0_r = luma_left_mode_i ;
preds_1_r = luma_top_mode_i ;
preds_2_r = (luma_left_mode_i + luma_top_mode_i)<7'd2 ? 6'd26 :6'd1 ;
end
end
end
// most probably candidates : pred_idx_r
always @* begin
if(luma_curr_mode_i == preds_2_r)
pred_idx_r = 2'd2 ;
else if(luma_curr_mode_i == preds_1_r)
pred_idx_r = 2'd1 ;
else if(luma_curr_mode_i == preds_0_r)
pred_idx_r = 2'd0 ;
else
pred_idx_r = 2'd3 ;
end
// prediction candidates resorting
assign preds_0_le_1_w = preds_0_r < preds_1_r ;
assign preds_0_le_2_w = preds_0_r < preds_2_r ;
assign preds_1_le_2_w = preds_1_r < preds_2_r ;
always @* begin
if(preds_0_le_1_w && preds_0_le_2_w && preds_1_le_2_w) begin
preds_0_sort_r = preds_0_r;
preds_1_sort_r = preds_1_r;
preds_2_sort_r = preds_2_r;
end
else if(preds_0_le_1_w && preds_0_le_2_w && (!preds_1_le_2_w) )begin
preds_0_sort_r = preds_0_r;
preds_1_sort_r = preds_2_r;
preds_2_sort_r = preds_1_r;
end
else if(preds_0_le_1_w && (!preds_0_le_2_w) )begin
preds_0_sort_r = preds_2_r;
preds_1_sort_r = preds_0_r;
preds_2_sort_r = preds_1_r;
end
else if((!preds_0_le_1_w) && preds_0_le_2_w) begin
preds_0_sort_r = preds_1_r;
preds_1_sort_r = preds_0_r;
preds_2_sort_r = preds_2_r;
end
else if( (!preds_0_le_1_w) && (!preds_0_le_2_w) && preds_1_le_2_w) begin
preds_0_sort_r = preds_1_r;
preds_1_sort_r = preds_2_r;
preds_2_sort_r = preds_0_r;
end
else begin
preds_0_sort_r = preds_2_r;
preds_1_sort_r = preds_1_r;
preds_2_sort_r = preds_0_r;
end
end
// calculation luma_mode_dir_r : final modified luma mode
assign luma_curr_mode_minus1_w = luma_curr_mode_i - 6'd1 ;
assign luma_curr_mode_minus2_w = luma_curr_mode_i - 6'd2 ;
assign luma_curr_mode_minus3_w = luma_curr_mode_i - 6'd3 ;
always @* begin
if(luma_curr_mode_i>preds_2_sort_r) begin
if(luma_curr_mode_minus1_w>preds_1_sort_r) begin
if(luma_curr_mode_minus2_w>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus3_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_minus2_w ;
end
end
else begin
if(luma_curr_mode_minus1_w>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus2_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_minus1_w ;
end
end
end
else begin
if(luma_curr_mode_i>preds_1_sort_r) begin
if(luma_curr_mode_minus1_w>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus2_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_minus1_w ;
end
end
else begin
if(luma_curr_mode_i>preds_0_sort_r) begin
luma_mode_dir_r = luma_curr_mode_minus1_w ;
end
else begin
luma_mode_dir_r = luma_curr_mode_i ;
end
end
end
end
//-----------------------------------------------------------------------------------------------------------------------------
//
// output signals
//
//-----------------------------------------------------------------------------------------------------------------------------
reg [8:0] bin_string_luma_mode_r ;
always @* begin
case(pred_idx_r)
2'd0: bin_string_luma_mode_r = {3'b001,1'b1,3'b000,1'b0, 1'b0} ; // 2 bins = 1bin regular + 1bypass
2'd1: bin_string_luma_mode_r = {3'b010,1'b1,3'b000,1'b1, 1'b0} ; // 3 bins = 1bin regular + 2bypass
2'd2: bin_string_luma_mode_r = {3'b010,1'b1,3'b000,1'b1, 1'b1} ; // 3 bins = 1bin regular + 2bypass
2'd3: bin_string_luma_mode_r = {3'b101,1'b0, luma_mode_dir_r[4:0]} ; // 6 bins = 1bin regular + 5bypass
default: bin_string_luma_mode_r = 9'd0;
endcase
end
// coding_mode:0:regular mode,1:invalid,2:bypass mode,3:terminal mode
// regular:{2'b01, bin, bank_num,addr_idx} {2,1,3,5}
// bypass :{2'b10,1resverd,bins_num,bin_string} {2,1resverd,3,5}
assign ctx_pair_luma_mode_0_o = {2'b00,bin_string_luma_mode_r[5] ,3'd0, 5'd30};
assign ctx_pair_luma_mode_1_o = {2'b10,1'b0,bin_string_luma_mode_r[8:6],bin_string_luma_mode_r[4:0]};
endmodule
|
`timescale 1ns / 1ps
module tx_tb();
reg reset;
reg clock;
wire [7:0] tx_data;
wire tx_enable;
reg fifo_data_start;
reg fifo_data_end;
reg [7:0] fifo_data;
wire fifo_data_read;
reg [7:0] packet [0:1518];
reg data_available;
integer i;
tx_sm U_tx_sm (
.reset(reset),
.clock(clock),
.fifo_data(fifo_data),
.fifo_data_read(fifo_data_read),
.fifo_data_start(fifo_data_start),
.fifo_data_end(fifo_data_end),
.fifo_data_available(data_available),
.fifo_retry(retry),
.mode(1'b1),
.carrier_sense(),
.collision(),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, tx_tb);
end
initial
begin
reset = 1;
clock = 0;
fifo_data = 0;
data_available = 0;
$readmemh("packet.hex", packet);
#15 reset = 0;
// Send a packet
data_available = 1;
wait_for_read();
push(packet[8], 1, 0);
for(i = 9; i < 99; i = i + 1)
begin
push(packet[i], 0, 0);
end
push(packet[i], 0, 1);
#100
$finish;
end
always
#2 clock = ~clock;
task push;
input [7:0] data;
input data_start;
input data_end;
begin
fifo_data = data;
fifo_data_start = data_start;
fifo_data_end = data_end;
@(posedge clock);
#1 fifo_data_start = 0;
fifo_data_end = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task wait_for_read;
begin
@(posedge fifo_data_read);
end
endtask
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.12.2015 18:04:09
// Design Name:
// Module Name: product_sat
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_product_sat
#( parameter BITS_IN1 = 50,
parameter BITS_IN2 = 50,
parameter BITS_OUT = 50,
parameter SHIFT = 10
)
(
input signed [BITS_IN1-1:0] factor1_i,
input signed [BITS_IN2-1:0] factor2_i,
output signed [BITS_OUT-1:0] product_o,
output overflow
);
wire signed [BITS_IN1+BITS_IN2-1:0] product;
//assign product = factor1_i*factor2_i;
// simple saturation added:
assign product = factor1_i*factor2_i + $signed(1 <<(SHIFT-1));
assign {product_o,overflow} = ( {product[BITS_IN1+BITS_IN2-1],|product[BITS_IN1+BITS_IN2-2:SHIFT+BITS_OUT-1]} ==2'b01) ? {{1'b0,{BITS_OUT-1{1'b1}}},1'b1} : //positive overflow
( {product[BITS_IN1+BITS_IN2-1],&product[BITS_IN1+BITS_IN2-2:SHIFT+BITS_OUT-1]} ==2'b10) ? {{1'b1,{BITS_OUT-1{1'b0}}},1'b1} : //negative overflow
{product[SHIFT+BITS_OUT-1:SHIFT],1'b0} ; //correct value
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_TB_V
`define SKY130_FD_SC_MS__BUFINV_TB_V
/**
* bufinv: Buffer followed by inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__bufinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_TB_V
|
// ======================================================================
// Comparator_PSoC4_Example01.v generated from TopDesign.cysch
// 09/09/2013 at 15:53
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 3
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 4
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: not_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v"
`endif
// Comp_P4_v1_0(Hysteresis=0, Polarity=0, Power=3, CY_COMPONENT_NAME=Comp_P4_v1_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=Comp, CY_INSTANCE_SHORT_NAME=Comp, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=Comp, )
module Comp_P4_v1_0_0 (
Vplus,
CmpOut,
Vminus);
inout Vplus;
electrical Vplus;
output CmpOut;
inout Vminus;
electrical Vminus;
electrical Net_32;
electrical Net_33;
electrical Net_34;
wire Net_9;
wire Net_1;
// VirtualMux_1 (cy_virtualmux_v1_0)
assign CmpOut = Net_1;
assign Net_9 = ~Net_1;
cy_psoc4_abuf_v1_0 cy_psoc4_abuf (
.vplus(Vplus),
.vminus(Vminus),
.vout1(Net_32),
.vout10(Net_33),
.rs_bot(Net_34),
.cmpout(Net_1));
defparam cy_psoc4_abuf.has_resistor = 0;
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_32));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_33));
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_34));
endmodule
// CharLCD_v1_90(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, TypeReplacementString=uint32, CY_COMPONENT_NAME=CharLCD_v1_90, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=LCD, CY_INSTANCE_SHORT_NAME=LCD, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=90, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=LCD, )
module CharLCD_v1_90_1 ;
wire [6:0] tmpOE__LCDPort_net;
wire [6:0] tmpFB_6__LCDPort_net;
wire [6:0] tmpIO_6__LCDPort_net;
wire [0:0] tmpINTERRUPT_0__LCDPort_net;
electrical [0:0] tmpSIOVREF__LCDPort_net;
cy_psoc3_pins_v1_10
#(.id("ebb09a38-5eea-4c64-8860-7b9b51f99ce7/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(21'b110_110_110_110_110_110_110),
.ibuf_enabled(7'b1_1_1_1_1_1_1),
.init_dr_st(7'b0_0_0_0_0_0_0),
.input_clk_en(0),
.input_sync(7'b1_1_1_1_1_1_1),
.input_sync_mode(7'b0_0_0_0_0_0_0),
.intr_mode(14'b00_00_00_00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(", , , , , , "),
.layout_mode("CONTIGUOUS"),
.oe_conn(7'b0_0_0_0_0_0_0),
.oe_reset(0),
.oe_sync(7'b0_0_0_0_0_0_0),
.output_clk_en(0),
.output_clock_mode(7'b0_0_0_0_0_0_0),
.output_conn(7'b0_0_0_0_0_0_0),
.output_mode(7'b0_0_0_0_0_0_0),
.output_reset(0),
.output_sync(7'b0_0_0_0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(",,,,,,"),
.pin_mode("OOOOOOO"),
.por_state(4),
.use_annotation(7'b0_0_0_0_0_0_0),
.sio_group_cnt(0),
.sio_hyst(7'b0_0_0_0_0_0_0),
.sio_ibuf(""),
.sio_info(14'b00_00_00_00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(7'b0_0_0_0_0_0_0),
.spanning(0),
.vtrip(14'b10_10_10_10_10_10_10),
.width(7))
LCDPort
(.oe(tmpOE__LCDPort_net),
.y({7'b0}),
.fb({tmpFB_6__LCDPort_net[6:0]}),
.io({tmpIO_6__LCDPort_net[6:0]}),
.siovref(tmpSIOVREF__LCDPort_net),
.interrupt({tmpINTERRUPT_0__LCDPort_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LCDPort_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{7'b1111111} : {7'b1111111};
endmodule
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files\Cypress\PSoC Creator\2.2\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// SCB_P4_v1_10(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=1600, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=false, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, ScbClkFreqDes=115.2, ScbClockSelect=1, ScbClockTermEnable=false, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=115.2, UartClockFromTerm=false, UartDataRate=9600, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=0, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART, CY_INSTANCE_SHORT_NAME=UART, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART, )
module SCB_P4_v1_10_2 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire [3:0] ss;
wire Net_88;
wire Net_84;
wire Net_149;
wire Net_150;
wire Net_152;
wire Net_453;
wire uncfg_rx_irq;
wire Net_427;
wire Net_436;
wire Net_449;
wire Net_433;
wire Net_373;
wire Net_452;
wire Net_459;
wire Net_458;
wire Net_430;
wire Net_237;
wire Net_413;
wire Net_244;
wire Net_422;
wire rx_irq;
wire Net_379;
wire Net_409;
wire Net_246;
wire Net_252;
wire Net_245;
wire Net_243;
wire Net_89;
wire Net_284;
wire Net_416;
wire Net_387;
wire Net_151;
wire Net_410;
cy_m0s8_scb_v1_0 SCB (
.rx(Net_244),
.miso_m(Net_410),
.clock(Net_237),
.select_m(ss[3:0]),
.sclk_m(Net_88),
.mosi_s(Net_89),
.select_s(Net_430),
.sclk_s(Net_413),
.mosi_m(Net_84),
.scl(Net_149),
.sda(Net_150),
.tx(Net_151),
.miso_s(Net_152),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/29084e80-7594-46a9-94af-639e276dfc5f"),
.source_clock_id(""),
.divisor(0),
.period("8680555555.55556"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
assign sclk = Net_284 | Net_427;
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_151}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_410 = Net_436;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_89 = Net_449;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_413 = Net_433;
// clock_VM (cy_virtualmux_v1_0)
assign Net_237 = Net_284;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_373 = uncfg_rx_irq;
// rx_VM (cy_virtualmux_v1_0)
assign Net_244 = Net_379;
ZeroTerminal ZeroTerminal_1 (
.z(Net_433));
ZeroTerminal ZeroTerminal_2 (
.z(Net_436));
ZeroTerminal ZeroTerminal_3 (
.z(Net_449));
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_430 = Net_459;
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
endmodule
// top
module top ;
wire Net_67;
wire Net_66;
wire Net_65;
wire Net_14;
electrical Net_36;
electrical Net_45;
electrical Net_13;
electrical Net_43;
electrical Net_27;
electrical Net_26;
electrical Net_32;
electrical Net_39;
electrical Net_42;
Comp_P4_v1_0_0 Comp (
.Vplus(Net_13),
.CmpOut(Net_14),
.Vminus(Net_45));
cy_annotation_universal_v1_0 LED_1 (
.connect({
Net_32,
Net_26
})
);
defparam LED_1.comp_name = "LED_v1_0";
defparam LED_1.port_names = "A, K";
defparam LED_1.width = 2;
cy_annotation_universal_v1_0 R1 (
.connect({
Net_27,
Net_26
})
);
defparam R1.comp_name = "Resistor_v1_0";
defparam R1.port_names = "T1, T2";
defparam R1.width = 2;
cy_annotation_universal_v1_0 GND_1 (
.connect({
Net_27
})
);
defparam GND_1.comp_name = "Gnd_v1_0";
defparam GND_1.port_names = "T1";
defparam GND_1.width = 1;
wire [0:0] tmpOE__LED_net;
wire [0:0] tmpFB_0__LED_net;
wire [0:0] tmpIO_0__LED_net;
wire [0:0] tmpINTERRUPT_0__LED_net;
electrical [0:0] tmpSIOVREF__LED_net;
cy_psoc3_pins_v1_10
#(.id("52f31aa9-2f0a-497d-9a1f-1424095e13e6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
LED
(.oe(tmpOE__LED_net),
.y({Net_14}),
.fb({tmpFB_0__LED_net[0:0]}),
.io({tmpIO_0__LED_net[0:0]}),
.siovref(tmpSIOVREF__LED_net),
.interrupt({tmpINTERRUPT_0__LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_annotation_universal_v1_0 VR1 (
.connect({
Net_42,
Net_43,
Net_36
})
);
defparam VR1.comp_name = "Potentiometer_v1_0";
defparam VR1.port_names = "T1, T2, W";
defparam VR1.width = 3;
cy_annotation_universal_v1_0 VR2 (
.connect({
Net_42,
Net_43,
Net_39
})
);
defparam VR2.comp_name = "Potentiometer_v1_0";
defparam VR2.port_names = "T1, T2, W";
defparam VR2.width = 3;
wire [0:0] tmpOE__V1_net;
wire [0:0] tmpFB_0__V1_net;
wire [0:0] tmpIO_0__V1_net;
wire [0:0] tmpINTERRUPT_0__V1_net;
electrical [0:0] tmpSIOVREF__V1_net;
cy_psoc3_pins_v1_10
#(.id("05a9c8de-3ba2-4909-8250-95fdc61c0bf4"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
V1
(.oe(tmpOE__V1_net),
.y({1'b0}),
.fb({tmpFB_0__V1_net[0:0]}),
.analog({Net_13}),
.io({tmpIO_0__V1_net[0:0]}),
.siovref(tmpSIOVREF__V1_net),
.interrupt({tmpINTERRUPT_0__V1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__V1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__V2_net;
wire [0:0] tmpFB_0__V2_net;
wire [0:0] tmpIO_0__V2_net;
wire [0:0] tmpINTERRUPT_0__V2_net;
electrical [0:0] tmpSIOVREF__V2_net;
cy_psoc3_pins_v1_10
#(.id("270dcf4b-3db6-4837-9ed4-a19952ec4eff"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.use_annotation(1'b0),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.vtrip(2'b10),
.width(1))
V2
(.oe(tmpOE__V2_net),
.y({1'b0}),
.fb({tmpFB_0__V2_net[0:0]}),
.analog({Net_45}),
.io({tmpIO_0__V2_net[0:0]}),
.siovref(tmpSIOVREF__V2_net),
.interrupt({tmpINTERRUPT_0__V2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__V2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_annotation_universal_v1_0 PWR (
.connect({
Net_42
})
);
defparam PWR.comp_name = "Power_v1_0";
defparam PWR.port_names = "T1";
defparam PWR.width = 1;
cy_annotation_universal_v1_0 GND_2 (
.connect({
Net_43
})
);
defparam GND_2.comp_name = "Gnd_v1_0";
defparam GND_2.port_names = "T1";
defparam GND_2.width = 1;
CharLCD_v1_90_1 LCD ();
SCB_P4_v1_10_2 UART (
.sclk(Net_65),
.interrupt(Net_66),
.clock(1'b0));
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_ddrio(
input sys_clk,
input sys_clk_n,
input dqs_clk,
input dqs_clk_n,
input direction,
input direction_r,
input [7:0] mo,
input [63:0] do,
output [63:0] di,
output [3:0] sdram_dqm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
input idelay_rst,
input idelay_ce,
input idelay_inc
);
wire [31:0] sdram_data_out;
assign sdram_dq = direction ? sdram_data_out : 32'hzzzzzzzz;
assign sdram_dqs = direction ? {4{dqs_clk}} : 4'hz;
hpdmc_oddr4 oddr_dqm(
.Q(sdram_dqm),
.C(sys_clk),
.CE(1'b1),
.D1(mo[7:4]),
.D2(mo[3:0]),
.R(1'b0),
.S(1'b0)
);
hpdmc_oddr32 oddr_dq(
.Q(sdram_data_out),
.C(sys_clk),
.CE(1'b1),
.D1(do[63:32]),
.D2(do[31:0]),
.R(1'b0),
.S(1'b0)
);
wire [31:0] sdram_dq_delayed;
hpdmc_idelay8 dq_delay0 (
.i(sdram_dq[7:0]),
.o(sdram_dq_delayed[7:0]),
.clk(sys_clk),
.rst(idelay_rst),
.ce(idelay_ce),
.inc(idelay_inc)
);
hpdmc_idelay8 dq_delay1 (
.i(sdram_dq[15:8]),
.o(sdram_dq_delayed[15:8]),
.clk(sys_clk),
.rst(idelay_rst),
.ce(idelay_ce),
.inc(idelay_inc)
);
hpdmc_idelay8 dq_delay2 (
.i(sdram_dq[23:16]),
.o(sdram_dq_delayed[23:16]),
.clk(sys_clk),
.rst(idelay_rst),
.ce(idelay_ce),
.inc(idelay_inc)
);
hpdmc_idelay8 dq_delay3 (
.i(sdram_dq[31:24]),
.o(sdram_dq_delayed[31:24]),
.clk(sys_clk),
.rst(idelay_rst),
.ce(idelay_ce),
.inc(idelay_inc)
);
hpdmc_iddr32 iddr_dq(
.Q1(di[31:0]),
.Q2(di[63:32]),
.C(sys_clk),
.CE(1'b1),
.D(sdram_dq_delayed),
.R(1'b0),
.S(1'b0)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_64_16.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_64_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [5:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire [5:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [15:0] q = sub_wire2[15:0];
wire [5:0] usedw = sub_wire3[5:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 6 0 OUTPUT NODEFVAL "usedw[5..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: usedw 0 0 6 0 @usedw 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_16_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={0} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={4} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={23.809523} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=30.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.217, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.133, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.089, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.248, PCW_UIPARAM_DDR_BOARD_DELAY0=0.537, PCW_UIPARAM_DDR_BOARD_DELAY1=0.442, PCW_UIPARAM_DDR_BOARD_DELAY2=0.464, PCW_UIPARAM_DDR_BOARD_DELAY3=0.521, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=23.8095, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=166, PCW_FPGA1_PERIPHERAL_FREQMHZ=142, PCW_FPGA2_PERIPHERAL_FREQMHZ=100, PCW_FPGA3_PERIPHERAL_FREQMHZ=200, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=1, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=100, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 1.8V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J256M8 HX-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=8 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=1, PCW_ENET0_RESET_IO=MIO 11, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 0, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 15, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=1, PCW_CAN0_CAN0_IO=MIO 46 .. 47, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 50 .. 51, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=1, PCW_I2C0_RESET_IO=MIO 13, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=100 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=ARM PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=IO PLL, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=1, PCW_PCAP_PERIPHERAL_CLKSRC=1, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=1, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=2, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=2, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=2, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=2, PCW_NAND_CYCLES_T_RR=0, PCW_NAND_CYCLES_T_AR=0, PCW_NAND_CYCLES_T_CLR=0, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
(* HW_HANDOFF = "zc702_processing_system7_1_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
wire S_AXI_GP0_ARESETN_shim;
wire S_AXI_GP0_ARREADY_shim;
wire S_AXI_GP0_AWREADY_shim;
wire S_AXI_GP0_BVALID_shim;
wire S_AXI_GP0_RLAST_shim;
wire S_AXI_GP0_RVALID_shim;
wire S_AXI_GP0_WREADY_shim;
wire [1:0] S_AXI_GP0_BRESP_shim;
wire [1:0] S_AXI_GP0_RRESP_shim;
wire [31:0] S_AXI_GP0_RDATA_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID_out_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID_out_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID_shim;
wire S_AXI_GP0_ACLK_shim;
wire S_AXI_GP0_ARVALID_shim;
wire S_AXI_GP0_AWVALID_shim;
wire S_AXI_GP0_BREADY_shim;
wire S_AXI_GP0_RREADY_shim;
wire S_AXI_GP0_WLAST_shim;
wire S_AXI_GP0_WVALID_shim;
wire [1:0] S_AXI_GP0_ARBURST_shim;
wire [1:0] S_AXI_GP0_ARLOCK_shim;
wire [2:0] S_AXI_GP0_ARSIZE_shim;
wire [1:0] S_AXI_GP0_AWBURST_shim;
wire [1:0] S_AXI_GP0_AWLOCK_shim;
wire [2:0] S_AXI_GP0_AWSIZE_shim;
wire [2:0] S_AXI_GP0_ARPROT_shim;
wire [2:0] S_AXI_GP0_AWPROT_shim;
wire [31:0] S_AXI_GP0_ARADDR_shim;
wire [31:0] S_AXI_GP0_AWADDR_shim;
wire [31:0] S_AXI_GP0_WDATA_shim;
wire [3:0] S_AXI_GP0_ARCACHE_shim;
wire [3:0] S_AXI_GP0_ARLEN_shim;
wire [3:0] S_AXI_GP0_ARQOS_shim;
wire [3:0] S_AXI_GP0_AWCACHE_shim;
wire [3:0] S_AXI_GP0_AWLEN_shim;
wire [3:0] S_AXI_GP0_AWQOS_shim;
wire [3:0] S_AXI_GP0_WSTRB_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID_in_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID_in_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID_in_shim;
xlnx_axi_wrshim_unwrap #
(
.ID_WIDTH(C_S_AXI_GP0_ID_WIDTH),
.D_WIDTH(32)
)xlnx_axi_wrshim_unwrap_inst_gp0
(
.clk(S_AXI_GP0_ACLK_temp),
.rst_n(S_AXI_GP0_ARESETN),
.awqos_in(S_AXI_GP0_AWQOS),
.awid_in(S_AXI_GP0_AWID_in),
.awaddr_in(S_AXI_GP0_AWADDR),
.awlen_in(S_AXI_GP0_AWLEN),
.awsize_in(S_AXI_GP0_AWSIZE),
.awburst_in(S_AXI_GP0_AWBURST),
.awlock_in(S_AXI_GP0_AWLOCK),
.awcache_in(S_AXI_GP0_AWCACHE),
.awprot_in(S_AXI_GP0_AWPROT),
.awvalid_in(S_AXI_GP0_AWVALID),
.wdata_in(S_AXI_GP0_WDATA),
.wid_in(S_AXI_GP0_WID_in),
.wstrb_in(S_AXI_GP0_WSTRB),
.wlast_in(S_AXI_GP0_WLAST),
.wvalid_in(S_AXI_GP0_WVALID),
.bready_in(S_AXI_GP0_BREADY),
.arqos_in(S_AXI_GP0_ARQOS),
.arid_in(S_AXI_GP0_ARID_in),
.araddr_in(S_AXI_GP0_ARADDR),
.arlen_in(S_AXI_GP0_ARLEN),
.arsize_in(S_AXI_GP0_ARSIZE),
.arburst_in(S_AXI_GP0_ARBURST),
.arlock_in(S_AXI_GP0_ARLOCK),
.arcache_in(S_AXI_GP0_ARCACHE),
.arprot_in(S_AXI_GP0_ARPROT),
.arvalid_in(S_AXI_GP0_ARVALID),
.rready_in(S_AXI_GP0_RREADY),
.awready_in(S_AXI_GP0_AWREADY),
.arready_in(S_AXI_GP0_ARREADY),
.rid_in(S_AXI_GP0_RID),
.rdata_in(S_AXI_GP0_RDATA),
.rresp_in(S_AXI_GP0_RRESP),
.rlast_in(S_AXI_GP0_RLAST),
.rvalid_in(S_AXI_GP0_RVALID),
.wready_in(S_AXI_GP0_WREADY),
.bid_in(S_AXI_GP0_BID),
.bresp_in(S_AXI_GP0_BRESP),
.bvalid_in(S_AXI_GP0_BVALID),
.awqos_out(S_AXI_GP0_AWQOS_shim),
.awid_out(S_AXI_GP0_AWID_in_shim),
.awaddr_out(S_AXI_GP0_AWADDR_shim),
.awlen_out(S_AXI_GP0_AWLEN_shim),
.awsize_out(S_AXI_GP0_AWSIZE_shim),
.awburst_out(S_AXI_GP0_AWBURST_shim),
.awlock_out(S_AXI_GP0_AWLOCK_shim),
.awcache_out(S_AXI_GP0_AWCACHE_shim),
.awprot_out(S_AXI_GP0_AWPROT_shim),
.awvalid_out(S_AXI_GP0_AWVALID_shim),
.wdata_out(S_AXI_GP0_WDATA_shim),
.wid_out(S_AXI_GP0_WID_in_shim),
.wstrb_out(S_AXI_GP0_WSTRB_shim),
.wlast_out(S_AXI_GP0_WLAST_shim),
.wvalid_out(S_AXI_GP0_WVALID_shim),
.bready_out(S_AXI_GP0_BREADY_shim),
.arqos_out(S_AXI_GP0_ARQOS_shim),
.arid_out(S_AXI_GP0_ARID_in_shim),
.araddr_out(S_AXI_GP0_ARADDR_shim),
.arlen_out(S_AXI_GP0_ARLEN_shim),
.arsize_out(S_AXI_GP0_ARSIZE_shim),
.arburst_out(S_AXI_GP0_ARBURST_shim),
.arlock_out(S_AXI_GP0_ARLOCK_shim),
.arcache_out(S_AXI_GP0_ARCACHE_shim),
.arprot_out(S_AXI_GP0_ARPROT_shim),
.arvalid_out(S_AXI_GP0_ARVALID_shim),
.rready_out(S_AXI_GP0_RREADY_shim),
.awready_out(S_AXI_GP0_AWREADY_shim),
.arready_out(S_AXI_GP0_ARREADY_shim),
.rid_out(S_AXI_GP0_RID_shim),
.rdata_out(S_AXI_GP0_RDATA_shim),
.rresp_out(S_AXI_GP0_RRESP_shim),
.rlast_out(S_AXI_GP0_RLAST_shim),
.rvalid_out(S_AXI_GP0_RVALID_shim),
.wready_out(S_AXI_GP0_WREADY_shim),
.bid_out(S_AXI_GP0_BID_shim),
.bresp_out(S_AXI_GP0_BRESP_shim),
.bvalid_out(S_AXI_GP0_BVALID_shim));
wire S_AXI_GP1_ARESETN_shim;
wire S_AXI_GP1_ARREADY_shim;
wire S_AXI_GP1_AWREADY_shim;
wire S_AXI_GP1_BVALID_shim;
wire S_AXI_GP1_RLAST_shim;
wire S_AXI_GP1_RVALID_shim;
wire S_AXI_GP1_WREADY_shim;
wire [1:0] S_AXI_GP1_BRESP_shim;
wire [1:0] S_AXI_GP1_RRESP_shim;
wire [31:0] S_AXI_GP1_RDATA_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID_out_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID_out_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID_shim;
// -- Input
wire S_AXI_GP1_ACLK_shim;
wire S_AXI_GP1_ARVALID_shim;
wire S_AXI_GP1_AWVALID_shim;
wire S_AXI_GP1_BREADY_shim;
wire S_AXI_GP1_RREADY_shim;
wire S_AXI_GP1_WLAST_shim;
wire S_AXI_GP1_WVALID_shim;
wire [1:0] S_AXI_GP1_ARBURST_shim;
wire [1:0] S_AXI_GP1_ARLOCK_shim;
wire [2:0] S_AXI_GP1_ARSIZE_shim;
wire [1:0] S_AXI_GP1_AWBURST_shim;
wire [1:0] S_AXI_GP1_AWLOCK_shim;
wire [2:0] S_AXI_GP1_AWSIZE_shim;
wire [2:0] S_AXI_GP1_ARPROT_shim;
wire [2:0] S_AXI_GP1_AWPROT_shim;
wire [31:0] S_AXI_GP1_ARADDR_shim;
wire [31:0] S_AXI_GP1_AWADDR_shim;
wire [31:0] S_AXI_GP1_WDATA_shim;
wire [3:0] S_AXI_GP1_ARCACHE_shim;
wire [3:0] S_AXI_GP1_ARLEN_shim;
wire [3:0] S_AXI_GP1_ARQOS_shim;
wire [3:0] S_AXI_GP1_AWCACHE_shim;
wire [3:0] S_AXI_GP1_AWLEN_shim;
wire [3:0] S_AXI_GP1_AWQOS_shim;
wire [3:0] S_AXI_GP1_WSTRB_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID_in_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID_in_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID_in_shim;
xlnx_axi_wrshim_unwrap #
(
.ID_WIDTH(C_S_AXI_GP1_ID_WIDTH),
.D_WIDTH(32)
)xlnx_axi_wrshim_unwrap_inst_gp1
(
.clk(S_AXI_GP1_ACLK_temp),
.rst_n(S_AXI_GP1_ARESETN),
.awqos_in(S_AXI_GP1_AWQOS),
.awid_in(S_AXI_GP1_AWID_in),
.awaddr_in(S_AXI_GP1_AWADDR),
.awlen_in(S_AXI_GP1_AWLEN),
.awsize_in(S_AXI_GP1_AWSIZE),
.awburst_in(S_AXI_GP1_AWBURST),
.awlock_in(S_AXI_GP1_AWLOCK),
.awcache_in(S_AXI_GP1_AWCACHE),
.awprot_in(S_AXI_GP1_AWPROT),
.awvalid_in(S_AXI_GP1_AWVALID),
.wdata_in(S_AXI_GP1_WDATA),
.wid_in(S_AXI_GP1_WID_in),
.wstrb_in(S_AXI_GP1_WSTRB),
.wlast_in(S_AXI_GP1_WLAST),
.wvalid_in(S_AXI_GP1_WVALID),
.bready_in(S_AXI_GP1_BREADY),
.arqos_in(S_AXI_GP1_ARQOS),
.arid_in(S_AXI_GP1_ARID_in),
.araddr_in(S_AXI_GP1_ARADDR),
.arlen_in(S_AXI_GP1_ARLEN),
.arsize_in(S_AXI_GP1_ARSIZE),
.arburst_in(S_AXI_GP1_ARBURST),
.arlock_in(S_AXI_GP1_ARLOCK),
.arcache_in(S_AXI_GP1_ARCACHE),
.arprot_in(S_AXI_GP1_ARPROT),
.arvalid_in(S_AXI_GP1_ARVALID),
.rready_in(S_AXI_GP1_RREADY),
.awready_in(S_AXI_GP1_AWREADY),
.arready_in(S_AXI_GP1_ARREADY),
.rid_in(S_AXI_GP1_RID),
.rdata_in(S_AXI_GP1_RDATA),
.rresp_in(S_AXI_GP1_RRESP),
.rlast_in(S_AXI_GP1_RLAST),
.rvalid_in(S_AXI_GP1_RVALID),
.wready_in(S_AXI_GP1_WREADY),
.bid_in(S_AXI_GP1_BID),
.bresp_in(S_AXI_GP1_BRESP),
.bvalid_in(S_AXI_GP1_BVALID),
.awqos_out(S_AXI_GP1_AWQOS_shim),
.awid_out(S_AXI_GP1_AWID_in_shim),
.awaddr_out(S_AXI_GP1_AWADDR_shim),
.awlen_out(S_AXI_GP1_AWLEN_shim),
.awsize_out(S_AXI_GP1_AWSIZE_shim),
.awburst_out(S_AXI_GP1_AWBURST_shim),
.awlock_out(S_AXI_GP1_AWLOCK_shim),
.awcache_out(S_AXI_GP1_AWCACHE_shim),
.awprot_out(S_AXI_GP1_AWPROT_shim),
.awvalid_out(S_AXI_GP1_AWVALID_shim),
.wdata_out(S_AXI_GP1_WDATA_shim),
.wid_out(S_AXI_GP1_WID_in_shim),
.wstrb_out(S_AXI_GP1_WSTRB_shim),
.wlast_out(S_AXI_GP1_WLAST_shim),
.wvalid_out(S_AXI_GP1_WVALID_shim),
.bready_out(S_AXI_GP1_BREADY_shim),
.arqos_out(S_AXI_GP1_ARQOS_shim),
.arid_out(S_AXI_GP1_ARID_in_shim),
.araddr_out(S_AXI_GP1_ARADDR_shim),
.arlen_out(S_AXI_GP1_ARLEN_shim),
.arsize_out(S_AXI_GP1_ARSIZE_shim),
.arburst_out(S_AXI_GP1_ARBURST_shim),
.arlock_out(S_AXI_GP1_ARLOCK_shim),
.arcache_out(S_AXI_GP1_ARCACHE_shim),
.arprot_out(S_AXI_GP1_ARPROT_shim),
.arvalid_out(S_AXI_GP1_ARVALID_shim),
.rready_out(S_AXI_GP1_RREADY_shim),
.awready_out(S_AXI_GP1_AWREADY_shim),
.arready_out(S_AXI_GP1_ARREADY_shim),
.rid_out(S_AXI_GP1_RID_shim),
.rdata_out(S_AXI_GP1_RDATA_shim),
.rresp_out(S_AXI_GP1_RRESP_shim),
.rlast_out(S_AXI_GP1_RLAST_shim),
.rvalid_out(S_AXI_GP1_RVALID_shim),
.wready_out(S_AXI_GP1_WREADY_shim),
.bid_out(S_AXI_GP1_BID_shim),
.bresp_out(S_AXI_GP1_BRESP_shim),
.bvalid_out(S_AXI_GP1_BVALID_shim));
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID_shim = id_out_gp0(S_AXI_GP0_BID_out_shim);
assign S_AXI_GP0_RID_shim = id_out_gp0(S_AXI_GP0_RID_out_shim);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID_shim = id_out_gp1(S_AXI_GP1_BID_out_shim);
assign S_AXI_GP1_RID_shim = id_out_gp1(S_AXI_GP1_RID_out_shim);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY_shim),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY_shim),
.SAXIGP0BID (S_AXI_GP0_BID_out_shim),
.SAXIGP0BRESP (S_AXI_GP0_BRESP_shim ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID_shim ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA_shim ),
.SAXIGP0RID (S_AXI_GP0_RID_out_shim ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST_shim ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP_shim ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID_shim ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY_shim ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY_shim),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY_shim),
.SAXIGP1BID (S_AXI_GP1_BID_out_shim ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP_shim ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID_shim ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA_shim ),
.SAXIGP1RID (S_AXI_GP1_RID_out_shim ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST_shim ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP_shim ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID_shim ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY_shim ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR_shim ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST_shim),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE_shim),
.SAXIGP0ARID (S_AXI_GP0_ARID_in_shim ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN_shim ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK_shim ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT_shim ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS_shim ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE_shim[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID_shim),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR_shim ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST_shim),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE_shim),
.SAXIGP0AWID (S_AXI_GP0_AWID_in_shim ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN_shim ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK_shim ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT_shim ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS_shim ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE_shim[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID_shim),
.SAXIGP0BREADY (S_AXI_GP0_BREADY_shim ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY_shim ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA_shim ),
.SAXIGP0WID (S_AXI_GP0_WID_in_shim ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST_shim ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB_shim ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID_shim ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR_shim ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST_shim),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE_shim),
.SAXIGP1ARID (S_AXI_GP1_ARID_in_shim ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN_shim ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK_shim ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT_shim ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS_shim ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE_shim[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID_shim),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR_shim ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST_shim),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE_shim),
.SAXIGP1AWID (S_AXI_GP1_AWID_in_shim ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN_shim ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK_shim ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT_shim ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS_shim ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE_shim[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID_shim),
.SAXIGP1BREADY (S_AXI_GP1_BREADY_shim ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY_shim ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA_shim ),
.SAXIGP1WID (S_AXI_GP1_WID_in_shim ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST_shim ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB_shim ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID_shim ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY_shim),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY_shim),
.SAXIGP0BID (S_AXI_GP0_BID_out_shim),
.SAXIGP0BRESP (S_AXI_GP0_BRESP_shim ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID_shim ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA_shim ),
.SAXIGP0RID (S_AXI_GP0_RID_out_shim ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST_shim ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP_shim ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID_shim ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY_shim ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY_shim),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY_shim),
.SAXIGP1BID (S_AXI_GP1_BID_out_shim ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP_shim ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID_shim ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA_shim ),
.SAXIGP1RID (S_AXI_GP1_RID_out_shim ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST_shim ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP_shim ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID_shim ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY_shim ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR_shim ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST_shim),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE_shim),
.SAXIGP0ARID (S_AXI_GP0_ARID_in_shim ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN_shim ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK_shim ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT_shim ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS_shim ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE_shim[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID_shim),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR_shim ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST_shim),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE_shim),
.SAXIGP0AWID (S_AXI_GP0_AWID_in_shim ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN_shim ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK_shim ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT_shim ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS_shim ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE_shim[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID_shim),
.SAXIGP0BREADY (S_AXI_GP0_BREADY_shim ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY_shim ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA_shim ),
.SAXIGP0WID (S_AXI_GP0_WID_in_shim ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST_shim ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB_shim ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID_shim ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR_shim ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST_shim),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE_shim),
.SAXIGP1ARID (S_AXI_GP1_ARID_in_shim ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN_shim ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK_shim ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT_shim ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS_shim ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE_shim[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID_shim),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR_shim ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST_shim),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE_shim),
.SAXIGP1AWID (S_AXI_GP1_AWID_in_shim ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN_shim ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK_shim ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT_shim ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS_shim ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE_shim[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID_shim),
.SAXIGP1BREADY (S_AXI_GP1_BREADY_shim ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY_shim ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA_shim ),
.SAXIGP1WID (S_AXI_GP1_WID_in_shim ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST_shim ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB_shim ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID_shim ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
/****************************************************************************
* Xilinx Confidential
* Copyright 2013 Xilinx, Inc. All rights reserved
*
* File: xlnx_axi_wrshim_unwrap.sv
* Owner: jmurray
* Initial Date: 22-May-2013
*
*
* Description:
* - Wr Shim to prevent PCIe lockup scenario
* - Should be inserted inline with any masters WrData and WrCmd AXI
* channels
* - Will not allow the wrCmd to be issued unless the first beat of
* the associated wrBurst is available
* - Likewise, will not allow the first beat of wrData to be issued
* unless the associated wrCmd is available
*
****************************************************************************/
module xlnx_axi_wrshim_unwrap #(
parameter ID_WIDTH = 6, // ID width
parameter AD_WIDTH = 32, // Address Width
parameter D_WIDTH = 64 // Data Width
)
(
//
//*********** MISC Signals *****************
//
input clk,
input rst_n,
//input apb_en_wrshim,
//
//*********** FUll AXI Interface Input (from Master) *****************
//
input[3:0] awqos_in,
input[ID_WIDTH-1:0] awid_in,
input[AD_WIDTH-1:0] awaddr_in,
input[3:0] awlen_in,
input[2:0] awsize_in,
input[1:0] awburst_in,
input[1:0] awlock_in,
input[3:0] awcache_in,
input[2:0] awprot_in,
input awvalid_in,
output awready_in,
input[D_WIDTH-1:0] wdata_in,
input[ID_WIDTH-1:0] wid_in,
input[D_WIDTH/8-1:0] wstrb_in,
input wlast_in,
input wvalid_in,
output wready_in,
output[ID_WIDTH-1:0] bid_in,
output[1:0] bresp_in,
output bvalid_in,
input bready_in,
input[3:0] arqos_in,
input[ID_WIDTH-1:0] arid_in,
input[AD_WIDTH-1:0] araddr_in,
input[3:0] arlen_in,
input[2:0] arsize_in,
input[1:0] arburst_in,
input[1:0] arlock_in,
input[3:0] arcache_in,
input[2:0] arprot_in,
input arvalid_in,
output arready_in,
output[ID_WIDTH-1:0] rid_in,
output[D_WIDTH-1:0] rdata_in,
output[1:0] rresp_in,
output rlast_in,
output rvalid_in,
input rready_in,
//
//*********** FUll AXI Interface Input (to Slave ) *****************
//
output[3:0] awqos_out,
output[ID_WIDTH-1:0] awid_out,
output[AD_WIDTH-1:0] awaddr_out,
output[3:0] awlen_out,
output[2:0] awsize_out,
output[1:0] awburst_out,
output[1:0] awlock_out,
output[3:0] awcache_out,
output[2:0] awprot_out,
output awvalid_out,
input awready_out,
output[D_WIDTH-1:0] wdata_out,
output[ID_WIDTH-1:0] wid_out,
output[D_WIDTH/8-1:0] wstrb_out,
output wlast_out,
output wvalid_out,
input wready_out,
input[ID_WIDTH-1:0] bid_out,
input[1:0] bresp_out,
input bvalid_out,
output bready_out,
output[3:0] arqos_out,
output[ID_WIDTH-1:0] arid_out,
output[AD_WIDTH-1:0] araddr_out,
output[3:0] arlen_out,
output[2:0] arsize_out,
output[1:0] arburst_out,
output[1:0] arlock_out,
output[3:0] arcache_out,
output[2:0] arprot_out,
output arvalid_out,
input arready_out,
input[ID_WIDTH-1:0] rid_out,
input[D_WIDTH-1:0] rdata_out,
input[1:0] rresp_out,
input rlast_out,
input rvalid_out,
output rready_out
);
/* ========================================================================== */
// Register and Wire Declarations
/* ========================================================================== */
wire wlast_consumed;
wire en_wrshim;
reg wlast_detect;
reg stall_awvalid;
reg store_first_beat;
reg previous_cmd_done;
reg burst_still_active;
reg [2:0] awsize_i;
reg [D_WIDTH-1:0] wdata_i;
reg [1:0] address_offset;
localparam AXI_WRSHIM_APB_SYNC_LEVELS = 2;
/* ========================================================================== */
// Code the Shim
/* ========================================================================== */
// Sync the APB enable signal for the shim
/*
xlnx_sync_bit #(AXI_WRSHIM_APB_SYNC_LEVELS, 0) axi_wrshim_en_sync (
.clk (clk),
.rst_n (rst_n),
.raw_input (apb_en_wrshim),
.sync_out (en_wrshim)
);
*/
wire axi_burst_length_is_zero= (awvalid_in && (awlen_in==0))?1'b1:1'b0;
wire zero_length_transfer=axi_burst_length_is_zero ;
//assign en_wrshim=zero_length_transfer;
assign en_wrshim=1'b1;
//
//*********** AXI signals Flow Throughs *****************
//
assign bid_in = bid_out;
assign bresp_in = bresp_out;
assign bvalid_in = bvalid_out;
assign arready_in = arready_out;
assign rid_in = rid_out;
assign rdata_in = rdata_out;
assign rresp_in = rresp_out;
assign rlast_in = rlast_out;
assign rvalid_in = rvalid_out;
assign awqos_out = awqos_in;
assign awid_out = awid_in;
assign awaddr_out[31:2] = awaddr_in[31:2];
assign awaddr_out[1:0] = (zero_length_transfer==1)?address_offset:awaddr_in[1:0];
assign awlen_out = awlen_in;
assign awsize_out = (zero_length_transfer==1)?awsize_i:awsize_in;
assign awburst_out = awburst_in;
assign awlock_out = awlock_in;
assign awcache_out = awcache_in;
assign awprot_out = awprot_in;
//assign wdata_out = (zero_length_transfer==1)?wdata_i:wdata_in;
assign wdata_out = wdata_in;
assign wid_out = wid_in;
assign wstrb_out = wstrb_in;
assign wlast_out = wlast_in;
assign bready_out = bready_in;
assign arqos_out = arqos_in;
assign arid_out = arid_in;
assign araddr_out = araddr_in;
assign arlen_out = arlen_in;
assign arsize_out = arsize_in;
assign arburst_out = arburst_in;
assign arlock_out = arlock_in;
assign arcache_out = arcache_in;
assign arprot_out = arprot_in;
assign arvalid_out = arvalid_in;
assign rready_out = rready_in;
// *****************************************************************
// ************************* WRITE COMMAND ****************************
// *****************************************************************
// Detect a Wlast. This is required since we cannot release the next AwCmd
// before we have seen a wlast from the previous WrBurst
always @(posedge clk )
if (!rst_n)
wlast_detect <= 1'b1;
else begin
if (wlast_consumed)
wlast_detect <= 1'b1;
else if (en_wrshim && wvalid_out && wready_out)
wlast_detect <= 1'b0;
end
// Detect the First WrData Beat of a wrBurst - only need to determine if
// it is available, NOT that it is consumed
wire first_beat_detect = wlast_detect && wvalid_in;
// Enable the Write Command to be issued
wire awcmd_en = en_wrshim ? ((first_beat_detect && !stall_awvalid) ||
store_first_beat) : 1'b1;
//assign awvalid_out = (zero_length_transfer==1)?awvalid_in && awcmd_en:awvalid_in;
assign awvalid_out = awvalid_in && awcmd_en;
// Also need to flow control the AwReady
//assign awready_in = (zero_length_transfer==1)?awready_out && awcmd_en:awready_out;
assign awready_in = awready_out && awcmd_en;
// Detect the case where AwCmd is released, but the wrData is not consumed
always @(posedge clk )
if (!rst_n)
stall_awvalid <= 1'b0;
else begin
if (en_wrshim && awvalid_out && awready_out && !wready_out)
stall_awvalid <= 1'b1;
else if (wready_out)
stall_awvalid <= 1'b0;
end
// Detect the case where AwValid=1, WValid=1, but AWReady=0 (WReady=1)
always @(posedge clk )
if (!rst_n)
store_first_beat <= 1'b0;
else begin
if (en_wrshim && first_beat_detect && !awready_out)
store_first_beat <= 1'b1;
else if (awready_out)
store_first_beat <= 1'b0;
end
// *****************************************************************
// ************************* WRITE DATA ****************************
// *****************************************************************
assign wlast_consumed = (wvalid_out && wready_out && wlast_in);
// For the Write Data, We need to enable the entire wrBurst
wire start_wr = wlast_detect && awvalid_in && previous_cmd_done;
// Detect if the previous AwCmd was consumed - May be backpressure
always @(posedge clk )
if (!rst_n)
previous_cmd_done <= 1'b1;
else begin
if (awvalid_out && awready_out)
previous_cmd_done <= 1'b1;
else if (awvalid_out && en_wrshim)
previous_cmd_done <= 1'b0;
end
// Store the enable unless it is a single beat wrCmd
always @(posedge clk )
if (!rst_n)
burst_still_active <= 1'b0;
else begin
if (start_wr && !wlast_consumed && en_wrshim)
burst_still_active <= 1'b1;
else if (wlast_consumed)
burst_still_active <= 1'b0;
end
wire write_data_en = en_wrshim ? (burst_still_active || start_wr) : 1'b1;
//assign wvalid_out = (zero_length_transfer==1)? wvalid_in && write_data_en:wvalid_in;
//assign wready_in = (zero_length_transfer==1)? wready_out && write_data_en:wready_out;
assign wvalid_out = wvalid_in && write_data_en;
assign wready_in = wready_out && write_data_en;
always @ *
case (wstrb_in)
4'b0001:begin
awsize_i=0;
wdata_i=wdata_in[7:0];
address_offset<=0;
end
4'b0010:begin
awsize_i=0;
wdata_i=wdata_in[15:8];
address_offset<=1;
end
4'b0100:begin
awsize_i=0;
wdata_i=wdata_in[23:16];
address_offset<=2;
end
4'b1000:begin
awsize_i=0;
wdata_i=wdata_in[31:24];
address_offset<=3;
end
4'b1100:begin
awsize_i=1;
wdata_i=wdata_in[31:16];
address_offset<=2;
end
4'b0011:begin
awsize_i=1;
wdata_i=wdata_in[15:0];
address_offset<=0;
end
default: begin
awsize_i=awsize_in;
wdata_i=wdata_in;
address_offset<=0;
end
endcase
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_gtp_pipe_drp.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_drp.v
// Description : GTP PIPE DRP Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- GTP PIPE DRP Module -----------------------------------------------
module PCIEBus_gtp_pipe_drp #
(
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 1'd0 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 2:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 2:0] fsm = 0;
//---------- DRP Address -------------------------------
localparam ADDR_RX_DATAWIDTH = 9'h011;
//---------- DRP Mask ----------------------------------
localparam MASK_RX_DATAWIDTH = 16'b1111011111111111; // Unmask bit [ 11]
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_LOAD = 1;
localparam FSM_READ = 2;
localparam FSM_RRDY = 3;
localparam FSM_WRITE = 4;
localparam FSM_WRDY = 5;
localparam FSM_DONE = 6;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
1'd0 :
begin
addr_reg <= ADDR_RX_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_DATAWIDTH) | data_rx_datawidth;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if (index == INDEX_MAX)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/30/2017 01:18:01 AM
// Design Name:
// Module Name: top_new
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_new#(parameter WIDTH=170, //% @param Width of data input and output
parameter CNT_WIDTH=8, //% @param WIDTH must be no greater than 2**CNT_WIDTH
parameter DIV_WIDTH=6, //% @param width of division factor.
parameter SHIFT_DIRECTION=1, //% @param 1: MSB out first, 0: LSB out first
parameter READ_TRIG_SRC=0, //% @param 0:start act as trig, 1: load_sr act as trig
parameter READ_DELAY=0 //% @param state machine delay period
)(
input clk_in, //% clock input is synchronised with input signals control clock.
input rst, //% module reset
//input start, //% start signal
input [WIDTH-1:0] din, //% 170-bit data input to config shift register
input data_in_p, //% data from shift register
input data_in_n, //% data from shift register
input [DIV_WIDTH-1:0] div, //% division factor 2**div
input pulse_in,
output clk, //% sub modules' control clock
output clk_sr_p, //% control clock send to shift register
output clk_sr_n, //% control clock send to shift register
output data_out_p, //% data send to shift register
output data_out_n, //% data send to shift register
output load_sr_p, //% load signal send to shift register
output load_sr_n, //% load signal send to shift register
output valid, //% valid is asserted when 170-bit dout is on the output port
output [WIDTH-1:0] dout
);
wire start;
Top_SR top_sr_inst(
.clk_in(clk_in), //% clock input is synchronised with input signals control clock.
.rst(rst), //% module reset
.start(start), //% start signal
.din(din), //% 170-bit data input to config shift register
.data_in_p(data_in_p), //% data from shift register
.data_in_n(data_in_n), //% data from shift register
.div(div), //% division factor 2**div
.clk(clk), //% sub modules' control clock
.clk_sr_p(clk_sr_p), //% control clock send to shift register
.clk_sr_n(clk_sr_n), //% control clock send to shift register
.data_out_p(data_out_p), //% data send to shift register
.data_out_n(data_out_n), //% data send to shift register
.load_sr_p(load_sr_p), //% load signal send to shift register
.load_sr_n(load_sr_n), //% load signal send to shift register
.valid(valid), //% valid is asserted when 170-bit dout is on the output port
.dout(dout)
);
pulse_synchronise pulse_synchronise_inst(
.pulse_in(pulse_in), //% input pulse
.clk_in(clk_in), //% pulse_in control clock
.clk_out(clk), //% pulse_out control clock
.rst(rst), //% module reset
.pulse_out(start)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRT Controller
// File : crtc.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Few important signals generated by this module are
// c_t_vsync - Vertical sync to Monitor
// c_vert_blank - Indicates the vertical blanking period
// c_vde - Vertical display timing strobe
// c_pre_vde - Indicates Vertical Display will start next scan line
// line_cmp - Indicates the succeeding lines will be in Screen B.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
// transceiver
// hcrt - Horizontal CRT controller
// vcrt - Vertical CRT controller
// clk_sel - clock selection logic
// crt_clk_gen - CRT clock generator
// crt_reg_dec - Decoder CRXX and ERXX registers
// crt_op_stage - CRT out put stage
// crt_misc - CRT Misc. module
// txt_time - Text time module
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crtc
(
input [15:0] h_io_addr, // Used for IO decoding.
input h_dec_3bx, // IO group decode of address range 03BX
input h_dec_3cx, // IO group decode of address range 03CX
input h_dec_3dx, // IO group decode of address range 03DX
input h_io_16, // Indicates the current IO cycle is 16 bit.
input h_io_8, // Indicates the current IO cycle is 16 bit.
input h_reset_n, // Power on reset to initialize
input h_iord, // Indicates a read cycle.
input h_iowr, // Indicates a write cycle.
input h_hclk, // Host clock.
input t_crt_clk, // Main crt clock
input m_sr01_b0, // 8/9 dot clock
input m_sr01_b2, // shift and load 16
input m_sr01_b3, // dot clock divided by 2
input m_sr01_b4, // shift and load 32
input m_sr01_b5, // Disable video display control.'1'
input a_ar10_b0, // graphics mode, graphics - 1, text - 0
input a_ar10_b5, // pixel panning compatibility
input a_ar10_b6, // pixel clock divided by 2
input t_sense_n, // switch sense bit
input a_arx_b5, // Video display enable control bit
input a_is01_b5, // diagnostic
input a_is01_b4, // diagnostic
input m_dec_sr00_sr06, /* Valid IO decode of 03c5
* index 0f 00 through 06 */
input m_dec_sr07, // Valid IO decode of 03c5 index of 07
input m_soft_rst_n,
input a_ar13_b3, // Pixel panning control bits 3-0
input a_ar13_b2,
input a_ar13_b1,
input a_ar13_b0,
input [15:0] h_io_dbus, // host I/O data bus
input vga_en, // Disable CRT and REF reqs
output [7:0] c_reg_ht, // Horizontal total
output [7:0] c_reg_hde, //Horizontal Display End
output [7:0] c_reg_hbs, //Horizontal Blanking Start
output [7:0] c_reg_hbe, //Horizontal Blanking End
output [7:0] c_reg_hss, //Horizontal Sync Start
output [7:0] c_reg_hse, //Horizontal Sync End
output [7:0] c_reg_cr06,
output [7:0] c_reg_cr07,
output [7:0] c_reg_cr10,
output [7:0] c_reg_cr11,
output [7:0] c_reg_cr12,
output [7:0] c_reg_cr15,
output [7:0] c_reg_cr16,
output [7:0] c_reg_cr18,
output [7:0] c_crtc_index,// crtc index register
output [7:0] c_ext_index, // extension index register
output [7:0] c_reg_ins0,
output [7:0] c_reg_ins1,
output [7:0] c_reg_fcr,
output [7:0] c_reg_cr17,
output [7:0] c_reg_cr08,
output [7:0] c_reg_cr09,
output [7:0] c_reg_cr0a,
output [7:0] c_reg_cr0b,
output [7:0] c_reg_cr14,
output [7:0] c_reg_misc,
output c_cr24_rd,
output c_cr26_rd,
output c_9dot,
output c_mis_3c2_b5,
output c_misc_b0,
output c_cr0b_b5, // Text cursor skew control 0
output c_cr0b_b6, // Text cursor skew control 1
output c_cr0a_b5,
output c_cr14_b6, // Double word mode
output c_cr17_b0,
output c_cr17_b1,
output c_cr17_b5,
output c_cr17_b6,
output c_gr_ext_en, // enable Graphic's extension registers
output [3:0] c_ext_index_b, // lower 4 bits of ER's index register
output c_dec_3ba_or_3da,
output c_vert_blank, // vertical blanking period
output c_ready_n, // current IO to CRT module is done
output c_t_clk_sel, // crt clock frequency select to pix_pll
output c_ahde, // early horizontal display enable
output c_t_cblank_n, // composite blank to RAMDAC
output c_crt_line_end, // end of current scan line
output c_dclk_en, // Dot clock enable
output c_crt_ff_read, /* read data from CRT fifo into
* Attributes */
output c_shift_ld, // Load signal to Attribute serializer
output c_shift_ld_pulse, // Load signal to Attr serializer
output c_t_hsync, // Horizontal sync. to CRT monitor
output c_shift_clk, // Attribute serializer shift clock
output c_pre_vde, /* Indicates vertical display will start
* next scan line */
output c_split_screen_pulse, /* Indicates screen B will start
* from next line untiil end of
* vertical display */
output c_vde, // Vertical display timing strobe
output c_vdisp_end, // end of vertical display period.
output c_t_vsync, // Vertical sync. to CRT monitor
output c_attr_de, /* This signal indicates the actual display
* enable to the attribute control */
output c_uln_on, // under line on
output c_cursory,
output [4:0] c_slc_op, // scan line counter output
output c_row_end, // end of row
output c_cr0c_f13_22_hit,
output c_misc_b1,
output crt_mod_rd_en_hb,
output crt_mod_rd_en_lb,
output pre_load,
output [10:0] vcount
);
wire c_t_crt_int;
wire c_raw_vsync;
wire int_h_io_wr;
wire [15:0] crt_io_dbus;
wire cclk_en;
wire dclk_en;
wire pclk_en;
wire misc_b6;
wire cr11_b7;
wire line_cmp;
wire byte_pan_en;
wire misc_b7;
wire vsync_sel_ctl;
wire cr11_b4;
wire cr11_b5;
wire hblank;
wire hde;
wire vsync_vde;
wire clk_sel_strb;
wire final_crt_rd;
wire final_sh_ld;
wire sr_00_06_wr;
wire sr07_wr;
wire c_ahde_1;
wire c_ahde_1_u;
wire ade;
wire screen_off;
wire cr09_b5; // Vertical Blanking start bit 9
wire cr09_b6; // Line compare bit 9
wire cr08_b5;
wire cr08_b6;
wire cr14_b5;
wire cr03_b7; // Compatible read
wire misc_b0;
wire sel_sh_ld;
wire int_crt_line_end;
wire lncmp_zero;
wire txt_crt_line_end;
wire txt_crt_line_end_pulse;
wire cr17_b2;
wire cr17_b7;
wire lclk_or_by_2;
wire pel_pan_en;
wire int_split_screen_pulse;
wire cr17_b3;
wire dis_en_sta;
assign c_crt_ff_read = final_crt_rd;
assign c_dclk_en = dclk_en;
assign c_shift_clk = pclk_en;
assign c_shift_ld = sel_sh_ld;
assign c_misc_b0 = misc_b0;
hcrt HC
(
.m_sr01_b3 (m_sr01_b3),
.h_reset_n (h_reset_n),
.cclk_en (cclk_en),
.dclk_en (dclk_en),
.h_hclk (h_hclk),
.color_mode (misc_b0),
.h_io_16 (h_io_16),
.h_io_wr (int_h_io_wr),
.h_addr (h_io_addr),
.c_crtc_index (c_crtc_index[5:0]),
.c_ext_index (c_ext_index),
.misc_b6 (misc_b6),
.a_ar10_b0 (a_ar10_b0),
.cr11_b7 (cr11_b7),
.line_cmp (line_cmp),
.a_ar10_b5 (a_ar10_b5),
.cr17_b2 (cr17_b2),
.byte_pan_en (byte_pan_en),
.cr08_b5 (cr08_b5),
.cr08_b6 (cr08_b6),
.cr17_b7 (cr17_b7),
.sr_00_06_wr (sr_00_06_wr),
.sr07_wr (sr07_wr),
.t_crt_clk (t_crt_clk),
.h_io_dbus (h_io_dbus[15:8]),
.reg_ht (c_reg_ht),
.reg_hde (c_reg_hde),
.reg_hbs (c_reg_hbs),
.reg_hbe (c_reg_hbe),
.reg_hss (c_reg_hss),
.reg_hse (c_reg_hse),
.cr03_b7 (cr03_b7),
.c_t_hsync (c_t_hsync),
.c_ahde (c_ahde),
.c_ahde_1 (c_ahde_1),
.c_ahde_1_u (c_ahde_1_u),
.hblank (hblank),
.hde (hde),
.lclk_or_by_2 (lclk_or_by_2),
.int_crt_line_end (int_crt_line_end)
);
vcrt VC
(
.m_soft_rst_n (m_soft_rst_n),
.h_reset_n (h_reset_n),
.h_hclk (h_hclk),
.color_mode (misc_b0),
.h_io_16 (h_io_16),
.h_io_wr (int_h_io_wr),
.h_addr (h_io_addr),
.c_crtc_index (c_crtc_index[5:0]),
.c_ext_index (c_ext_index),
.cclk_en (cclk_en),
.lclk_or_by_2 (lclk_or_by_2),
.cr03_b7 (cr03_b7),
.cr17_b7 (cr17_b7),
.cr09_b6 (cr09_b6),
.cr09_b5 (cr09_b5),
.misc_b7 (misc_b7),
.vsync_sel_ctl (vsync_sel_ctl),
.int_crt_line_end (int_crt_line_end),
.t_crt_clk (t_crt_clk),
.h_io_dbus (h_io_dbus[15:8]),
.vga_en (vga_en),
.reg_cr06 (c_reg_cr06),
.reg_cr07 (c_reg_cr07),
.reg_cr10 (c_reg_cr10),
.reg_cr11 (c_reg_cr11),
.reg_cr12 (c_reg_cr12),
.reg_cr15 (c_reg_cr15),
.reg_cr16 (c_reg_cr16),
.reg_cr18 (c_reg_cr18),
.vsync_vde (vsync_vde),
.cr11_b4 (cr11_b4),
.cr11_b5 (cr11_b5),
.cr11_b7 (cr11_b7),
.c_vde (c_vde),
.c_pre_vde (c_pre_vde),
.c_vert_blank (c_vert_blank),
.c_t_vsync (c_t_vsync),
.line_cmp (line_cmp),
.byte_pan_en (byte_pan_en),
.pel_pan_en (pel_pan_en),
.c_vdisp_end (c_vdisp_end),
.c_split_screen_pulse (c_split_screen_pulse),
.int_split_screen_pulse (int_split_screen_pulse),
.c_crt_line_end (c_crt_line_end),
.txt_crt_line_end (txt_crt_line_end),
.txt_crt_line_end_pulse (txt_crt_line_end_pulse),
.c_raw_vsync (c_raw_vsync),
.lncmp_zero (lncmp_zero),
.vcrt_cntr_op (vcount)
);
clk_sel CS
(
.h_reset_n (h_reset_n),
.t_crt_clk (t_crt_clk),
.m_sr01_b3 (m_sr01_b3),
.a_ar10_b6 (a_ar10_b6),
.final_sh_ld (final_sh_ld),
.pre_load (pre_load),
.cclk_en (cclk_en),
.sel_sh_ld (sel_sh_ld),
.sel_sh_ld_pulse (c_shift_ld_pulse),
.dclk_en (dclk_en),
.pclk_en (pclk_en)
);
crt_clk_gen CG
(
.t_crt_clk (t_crt_clk),
.line_cmp (line_cmp),
.pix_pan (a_ar10_b5),
.h_reset_n (h_reset_n),
.h_io_16 (h_io_16),
.h_io_wr (int_h_io_wr),
.h_addr (h_io_addr),
.c_ext_index (c_ext_index),
.m_sr01_b4 (m_sr01_b4),
.m_sr01_b2 (m_sr01_b2),
.m_sr01_b0 (m_sr01_b0),
.a_ar10_b0 (a_ar10_b0),
.a_ar10_b6 (a_ar10_b6),
.a_ar13_b3 (a_ar13_b3),
.a_ar13_b2 (a_ar13_b2),
.a_ar13_b1 (a_ar13_b1),
.a_ar13_b0 (a_ar13_b0),
.cr14_b5 (cr14_b5),
.cr17_b3 (cr17_b3),
.c_ahde_1 (c_ahde_1),
.h_hclk (h_hclk),
.ade (ade),
.screen_off (screen_off),
.pel_pan_en (pel_pan_en),
.dclk_en (dclk_en),
.h_io_dbus (h_io_dbus),
.reg_misc (c_reg_misc),
.c_9dot (c_9dot),
.misc_b0 (misc_b0),
.misc_b6 (misc_b6),
.misc_b7 (misc_b7),
.c_mis_3c2_b5 (c_mis_3c2_b5),
.clk_sel_ctl (c_t_clk_sel),
.cclk_en (cclk_en),
.final_sh_ld (final_sh_ld),
.final_crt_rd (final_crt_rd),
.c_misc_b1 (c_misc_b1),
.pre_load (pre_load)
);
crt_reg_dec CD
(
.h_reset_n (h_reset_n),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_hclk (h_hclk),
.h_io_16 (h_io_16),
.h_io_8 (h_io_8),
.misc_b0 (misc_b0),
.h_dec_3bx (h_dec_3bx),
.h_dec_3cx (h_dec_3cx),
.h_dec_3dx (h_dec_3dx),
.m_dec_sr07 (m_dec_sr07),
.m_dec_sr00_sr06 (m_dec_sr00_sr06),
.h_io_addr (h_io_addr),
.h_io_dbus (h_io_dbus),
.crtc_index (c_crtc_index),
.ext_index (c_ext_index),
.trim_wr (int_h_io_wr),
.c_gr_ext_en (c_gr_ext_en),
.c_ext_index_b (c_ext_index_b),
.crt_mod_rd_en_hb (crt_mod_rd_en_hb),
.crt_mod_rd_en_lb (crt_mod_rd_en_lb),
.c_ready_n (c_ready_n),
.sr_00_06_wr (sr_00_06_wr),
.sr07_wr (sr07_wr),
.cr24_rd (c_cr24_rd),
.cr26_rd (c_cr26_rd),
.c_dec_3ba_or_3da (c_dec_3ba_or_3da),
.c_cr0c_f13_22_hit (c_cr0c_f13_22_hit)
);
crt_op_stage CO
(
.h_reset_n (h_reset_n),
.c_vde (c_vde),
.cr11_b4 (cr11_b4),
.cr11_b5 (cr11_b5),
.a_arx_b5 (a_arx_b5),
.m_sr01_b5 (m_sr01_b5),
.vblank (c_vert_blank),
.hblank (hblank),
.cclk_en (cclk_en),
.dclk_en (dclk_en),
.hde (hde),
.c_ahde (c_ahde),
.int_crt_line_end (int_crt_line_end),
.t_crt_clk (t_crt_clk),
.a_ar10_b0 (a_ar10_b0),
.vga_en (vga_en),
.c_t_crt_int (c_t_crt_int),
.c_attr_de (c_attr_de),
.c_t_cblank_n (c_t_cblank_n),
.ade (ade),
.screen_off (screen_off),
.dis_en_sta (dis_en_sta)
);
crt_misc CM
(
.dis_en_sta (dis_en_sta),
.c_raw_vsync (c_raw_vsync),
.h_reset_n (h_reset_n),
.h_hclk (h_hclk),
.color_mode (misc_b0),
.h_io_16 (h_io_16),
.h_io_wr (int_h_io_wr),
.h_addr (h_io_addr),
.c_crtc_index (c_crtc_index[5:0]),
.c_ext_index (c_ext_index),
.t_sense_n (t_sense_n),
.c_t_crt_int (c_t_crt_int),
.a_is01_b5 (a_is01_b5),
.a_is01_b4 (a_is01_b4),
.vsync_vde (vsync_vde),
.h_io_dbus (h_io_dbus),
.reg_ins0 (c_reg_ins0),
.reg_ins1 (c_reg_ins1),
.reg_fcr (c_reg_fcr),
.reg_cr17 (c_reg_cr17),
.c_cr17_b0 (c_cr17_b0),
.c_cr17_b1 (c_cr17_b1),
.cr17_b2 (cr17_b2),
.cr17_b3 (cr17_b3),
.c_cr17_b5 (c_cr17_b5),
.c_cr17_b6 (c_cr17_b6),
.cr17_b7 (cr17_b7),
.vsync_sel_ctl (vsync_sel_ctl)
);
txt_time CT
(
.h_reset_n (h_reset_n),
.h_hclk (h_hclk),
.color_mode (misc_b0),
.h_io_16 (h_io_16),
.h_io_wr (int_h_io_wr),
.h_addr (h_io_addr),
.c_crtc_index (c_crtc_index[5:0]),
.t_crt_clk (t_crt_clk),
.cclk_en (cclk_en), // character clock
.dclk_en (dclk_en),
.int_pre_vde (c_pre_vde), /* Indicates Vertical Display will
* start next scan line */
.int_split_screen_pulse (int_split_screen_pulse),
.txt_crt_line_end (txt_crt_line_end),
.txt_crt_line_end_pulse (txt_crt_line_end_pulse),
.c_vdisp_end (c_vdisp_end),
.lncmp_zero (lncmp_zero),
.h_io_dbus (h_io_dbus[15:8]), // data bus
.reg_cr08 (c_reg_cr08),
.reg_cr09 (c_reg_cr09),
.reg_cr0a (c_reg_cr0a),
.reg_cr0b (c_reg_cr0b),
.reg_cr14 (c_reg_cr14),
.cr08_b5 (cr08_b5),
.cr08_b6 (cr08_b6),
.cr09_b5 (cr09_b5), // Vertical Blanking start bit 9
.cr09_b6 (cr09_b6), // Line compare bit 9
.c_cr0b_b5 (c_cr0b_b5), // Text cursor skew control bit 0
.c_cr0b_b6 (c_cr0b_b6), // Text cursor skew control bit 1
.c_cr0a_b5 (c_cr0a_b5), // Disable Text cursor
.cr14_b5 (cr14_b5), // Count by four
.c_cr14_b6 (c_cr14_b6), // Double word mode
.c_uln_on (c_uln_on), // under line on
.c_cursor_on_line (c_cursory),
.c_slc_op (c_slc_op), // scan line counter output
.c_row_end (c_row_end) // end of row
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_1_V
`define SKY130_FD_SC_LP__DLXBP_1_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_1_V
|
module testmem();
reg clk;
reg reset;
reg [7:0] snoopa;
reg [7:0] snoopd;
reg snoopp;
discus dcs(.clk(clk),
.reset(reset),
.snoop_clk(clk),
.snoopa(snoopa),
.snoopd(snoopd),
.snoopq(),
.snoopm(1'b0),
.snoopp(snoopp));
wire[7:0] prgram[0:15] = {
8'h68,
8'h15, 8'ha4,
8'he0,
8'h08, 8'ha4,
8'he0,
8'h01, 8'ha4,
8'h01, 8'h8c,
8'h08, 8'h94,
8'h15, 8'h9c,
8'ha8
};
initial begin : testit
integer i;
clk = 0;
snoopp = 1;
reset = 1;
for (i = 0; i <= 255; i = i + 1) begin
if (prgram[i] != 0) begin
snoopa = i;
snoopd = prgram[i];
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
end
end
snoopp = 0;
reset = 0;
for (i = 0; i <= 20; i = i + 1) begin
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
end
for (i = 0; i < 32; i = i + 1) begin
snoopa = i;
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
end
end
endmodule
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module io_requester(
input clk,
input rst_n,
////////////////// io_requester <--> arbiter
// RD TX
output wire cor_tx_rd_ready,
input wire cor_tx_rd_valid,
input wire [70:0] cor_tx_rd_hdr,
// WR TX
output wire cor_tx_wr_ready,
input wire cor_tx_wr_valid,
input wire [74:0] cor_tx_wr_hdr,
input wire [511:0] cor_tx_data,
//////////////////// io_requester <--> server_io
// TX_RD request,
input wire rq_tx_rd_ready,
output reg rq_tx_rd_valid,
output reg [44:0] rq_tx_rd_hdr,
// TX_WR request
input wire rq_tx_wr_ready,
output reg rq_tx_wr_valid,
output reg [48:0] rq_tx_wr_hdr,
output reg [511:0] rq_tx_data,
///////////////////// io_requester <--> pagetable
// afu_virt_waddr --> afu_phy_waddr
output reg [57:0] afu_virt_wr_addr,
output reg pt_re_wr,
input wire [31:0] afu_phy_wr_addr,
input wire afu_phy_wr_addr_valid,
// afu_virt_raddr --> afu_phy_raddr
output reg [57:0] afu_virt_rd_addr,
output reg pt_re_rd,
input wire [31:0] afu_phy_rd_addr,
input wire afu_phy_rd_addr_valid
);
wire trq_empty;
wire [4:0] trq_count;
wire trq_full;
wire trq_valid;
wire [44:0] trq_dout;
wire twq_empty;
wire [4:0] twq_count;
wire twq_full;
wire twq_valid;
wire [560:0] twq_dout;
reg [31:0] rd_cnt;
reg [511:0] afu_virt_wr_data_d0;
reg [74:0] afu_virt_wr_hdr_d0;
reg afu_virt_wr_valid_d0;
reg [511:0] afu_virt_wr_data_d1;
reg [74:0] afu_virt_wr_hdr_d1;
reg afu_virt_wr_valid_d1;
reg [511:0] afu_virt_wr_data_d2;
reg [74:0] afu_virt_wr_hdr_d2;
reg afu_virt_wr_valid_d2;
reg [511:0] afu_virt_wr_data_d3;
reg [74:0] afu_virt_wr_hdr_d3;
reg afu_virt_wr_valid_d3;
reg [70:0] afu_virt_rd_hdr_d0;
reg afu_virt_rd_valid_d0;
reg [70:0] afu_virt_rd_hdr_d1;
reg afu_virt_rd_valid_d1;
reg [70:0] afu_virt_rd_hdr_d2;
reg afu_virt_rd_valid_d2;
reg [70:0] afu_virt_rd_hdr_d3;
reg afu_virt_rd_valid_d3;
//-------------------------------------------------
always @(posedge clk) begin
if( ~rst_n ) begin
rd_cnt <= 32'b0;
end
else if (rq_tx_rd_valid) begin
rd_cnt <= rd_cnt +1'b1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// TX RD Channel ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign cor_tx_rd_ready = ~trq_full;
always@(posedge clk) begin
if(~rst_n) begin
rq_tx_rd_valid <= 0;
rq_tx_rd_hdr <= 0;
end
else if(rq_tx_rd_ready) begin
rq_tx_rd_valid <= trq_valid;
rq_tx_rd_hdr <= trq_dout;
end
end
// TX_RD transmit queue
quick_fifo #(.FIFO_WIDTH(45), //
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) txrd_queue(
.clk (clk),
.reset_n (rst_n),
.din (afu_virt_rd_hdr_d3[44:0]),
.we (afu_virt_rd_valid_d3),
.re (rq_tx_rd_ready),
.dout (trq_dout),
.empty (trq_empty),
.valid (trq_valid),
.full (),
.count (trq_count),
.almostfull (trq_full)
);
always@(posedge clk) begin
if( ~rst_n ) begin
pt_re_rd <= 0;
afu_virt_rd_addr <= 0;
afu_virt_rd_valid_d0 <= 0;
//afu_virt_rd_hdr_d0 <= 0;
// S1
afu_virt_rd_valid_d1 <= 0;
//afu_virt_rd_hdr_d1 <= 0;
// S2
afu_virt_rd_valid_d2 <= 0;
//afu_virt_rd_hdr_d2 <= 0;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_rd_valid_d3 <= 0;
//afu_virt_rd_hdr_d3 <= 0;
end
else begin
pt_re_rd <= cor_tx_rd_valid & cor_tx_rd_ready;
afu_virt_rd_addr <= cor_tx_rd_hdr[70:13];
// PT pipeline stages delay
// S0
afu_virt_rd_valid_d0 <= cor_tx_rd_valid & cor_tx_rd_ready;
afu_virt_rd_hdr_d0 <= cor_tx_rd_hdr;
// S1
afu_virt_rd_valid_d1 <= afu_virt_rd_valid_d0;
afu_virt_rd_hdr_d1 <= afu_virt_rd_hdr_d0;
// S2
afu_virt_rd_valid_d2 <= afu_virt_rd_valid_d1;
afu_virt_rd_hdr_d2 <= afu_virt_rd_hdr_d1;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_rd_valid_d3 <= afu_virt_rd_valid_d2;
afu_virt_rd_hdr_d3 <= {afu_phy_rd_addr, afu_virt_rd_hdr_d2[12:0]};
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// TX WR Channel ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign cor_tx_wr_ready = ~twq_full;
always@(posedge clk) begin
if(~rst_n) begin
rq_tx_wr_valid <= 0;
rq_tx_data <= 0;
rq_tx_wr_hdr <= 0;
end
else if(rq_tx_wr_ready) begin
rq_tx_wr_valid <= twq_valid;
rq_tx_data <= twq_dout[511:0];
rq_tx_wr_hdr <= twq_dout[560:512];
end
end
// TX_WR transmit queue
quick_fifo #(.FIFO_WIDTH(561), //
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 -8)
) txwr_queue(
.clk (clk),
.reset_n (rst_n),
.din ({afu_virt_wr_hdr_d3[48:0], afu_virt_wr_data_d3}),
.we (afu_virt_wr_valid_d3),
.re (rq_tx_wr_ready),
.dout (twq_dout),
.empty (twq_empty),
.valid (twq_valid),
.full (),
.count (twq_count),
.almostfull (twq_full)
);
always@(posedge clk) begin
if( ~rst_n ) begin
pt_re_wr <= 0;
afu_virt_wr_addr <= 0;
// PT pipeline stages delay
// S0
afu_virt_wr_valid_d0 <= 0;
afu_virt_wr_hdr_d0 <= 0;
afu_virt_wr_data_d0 <= 0;
// S1
afu_virt_wr_valid_d1 <= 0;
afu_virt_wr_hdr_d1 <= 0;
afu_virt_wr_data_d1 <= 0;
// S2
afu_virt_wr_valid_d2 <= 0;
afu_virt_wr_hdr_d2 <= 0;
afu_virt_wr_data_d2 <= 0;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_wr_valid_d3 <= 0;
afu_virt_wr_hdr_d3 <= 0;
afu_virt_wr_data_d3 <= 0;
end
else begin
pt_re_wr <= cor_tx_wr_valid & cor_tx_wr_ready;
afu_virt_wr_addr <= cor_tx_wr_hdr[70:13];
// PT pipeline stages delay
// S0
afu_virt_wr_valid_d0 <= cor_tx_wr_valid & cor_tx_wr_ready;
afu_virt_wr_hdr_d0 <= cor_tx_wr_hdr;
afu_virt_wr_data_d0 <= cor_tx_data;
// S1
afu_virt_wr_valid_d1 <= afu_virt_wr_valid_d0;
afu_virt_wr_hdr_d1 <= afu_virt_wr_hdr_d0;
afu_virt_wr_data_d1 <= afu_virt_wr_data_d0;
// S2
afu_virt_wr_valid_d2 <= afu_virt_wr_valid_d1;
afu_virt_wr_hdr_d2 <= afu_virt_wr_hdr_d1;
afu_virt_wr_data_d2 <= afu_virt_wr_data_d1;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_wr_valid_d3 <= afu_virt_wr_valid_d2;
afu_virt_wr_hdr_d3 <= { afu_virt_wr_hdr_d2[74:71], afu_phy_wr_addr, afu_virt_wr_hdr_d2[12:0]};
afu_virt_wr_data_d3 <= afu_virt_wr_data_d2;
end
end
endmodule
|
// (c) 2010,2012 NedoPC
//
// fpga SPI slave device -- AVR controlled.
`include "../include/tune.v"
module slavespi(
input wire fclk,
input wire rst_n,
input wire spics_n, // avr SPI iface
output wire spidi, //
input wire spido, //
input wire spick, //
input wire [ 7:0] status_in, // status bits to be shown to avr
output wire [39:0] kbd_out,
output wire kbd_stb,
output wire [ 7:0] mus_out,
output wire mus_xstb,
output wire mus_ystb,
output wire mus_btnstb,
output wire kj_stb,
input wire [ 7:0] gluclock_addr,
input wire [ 2:0] comport_addr,
input wire [ 7:0] wait_write,
output wire [ 7:0] wait_read,
input wire wait_rnw,
output wire wait_end,
output wire [ 7:0] config0, // config bits for overall system
output wire genrst, // positive pulse, causes Z80 reset
output wire sd_lock_out, // SDcard control iface
input wire sd_lock_in, //
output wire sd_cs_n, //
output wire sd_start, //
output wire [ 7:0] sd_datain, //
input wire [ 7:0] sd_dataout //
);
`ifdef SIMULATE
initial
begin
force wait_read = 8'h00;
end
`endif
// re-synchronize SPI
//
reg [2:0] spics_n_sync;
reg [1:0] spido_sync;
reg [2:0] spick_sync;
//
always @(posedge fclk)
begin
spics_n_sync[2:0] <= { spics_n_sync[1:0], spics_n };
spido_sync [1:0] <= { spido_sync [0], spido };
spick_sync [2:0] <= { spick_sync [1:0], spick };
end
//
wire scs_n = spics_n_sync[1]; // scs_n - synchronized CS_N
wire sdo = spido_sync[1];
wire sck = spick_sync[1];
//
wire scs_n_01 = (~spics_n_sync[2]) & spics_n_sync[1] ;
wire scs_n_10 = spics_n_sync[2] & (~spics_n_sync[1]);
//
wire sck_01 = (~spick_sync[2]) & spick_sync[1] ;
wire sck_10 = spick_sync[2] & (~spick_sync[1]);
reg [7:0] regnum; // register number holder
reg [7:0] shift_out;
reg [7:0] data_in;
// register selectors
wire sel_kbdreg, sel_kbdstb, sel_musxcr, sel_musycr, sel_musbtn, sel_kj,
sel_rstreg, sel_waitreg, sel_gluadr, sel_comadr, sel_cfg0,
sel_sddata, sel_sdctrl;
// keyboard register
reg [39:0] kbd_reg;
// common single-byte shift-in register
reg [7:0] common_reg;
// wait data out register
reg [7:0] wait_reg;
//
reg [7:0] cfg0_reg_out; // one for shifting, second for storing values
// SDcard access registers
reg [7:0] sddata; // output to SDcard
reg [1:0] sdctrl; // SDcard control (CS_n and lock)
`ifdef SIMULATE
initial
begin
cfg0_reg_out[7:0] = 8'd0;
end
`endif
// register number
//
always @(posedge fclk)
begin
if( scs_n_01 )
begin
regnum <= 8'd0;
end
else if( scs_n && sck_01 )
begin
regnum[7:0] <= { sdo, regnum[7:1] };
end
end
// send data to avr
//
always @*
case(1'b1)
sel_waitreg: data_in = wait_write;
sel_gluadr: data_in = gluclock_addr;
sel_comadr: data_in = comport_addr;
sel_sddata: data_in = sd_dataout;
sel_sdctrl: data_in = { sd_lock_in, 7'bXXX_XXXX };
default: data_in = 8'bXXXX_XXXX;
endcase
//
always @(posedge fclk)
begin
if( scs_n_01 || scs_n_10 ) // both edges
begin
shift_out <= scs_n ? status_in : data_in;
end
else if( sck_01 )
begin
shift_out[7:0] <= { 1'b0, shift_out[7:1] };
end
end
//
assign spidi = shift_out[0];
// reg number decoding
//
assign sel_kbdreg = ( (regnum[7:4]==4'h1) && !regnum[0] ); // $10
assign sel_kbdstb = ( (regnum[7:4]==4'h1) && regnum[0] ); // $11
//
assign sel_musxcr = ( (regnum[7:4]==4'h2) && !regnum[1] && !regnum[0] ); // $20
assign sel_musycr = ( (regnum[7:4]==4'h2) && !regnum[1] && regnum[0] ); // $21
assign sel_musbtn = ( (regnum[7:4]==4'h2) && regnum[1] && !regnum[0] ); // $22
assign sel_kj = ( (regnum[7:4]==4'h2) && regnum[1] && regnum[0] ); // $23
//
assign sel_rstreg = ( (regnum[7:4]==4'h3) ) ; // $30
//
assign sel_waitreg = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b00) ); // $40
assign sel_gluadr = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b01) ); // $41
assign sel_comadr = ( (regnum[7:4]==4'h4) && (regnum[1:0]==2'b10) ); // $42
//
assign sel_cfg0 = (regnum[7:4]==4'h5); // $50
//
assign sel_sddata = ( (regnum[7:4]==4'h6) && !regnum[0] ); // $60
assign sel_sdctrl = ( (regnum[7:4]==4'h6) && regnum[0] ); // $61
// registers data-in
//
always @(posedge fclk)
begin
// kbd data shift-in
if( !scs_n && sel_kbdreg && sck_01 )
kbd_reg[39:0] <= { sdo, kbd_reg[39:1] };
// mouse data shift-in
if( !scs_n && (sel_musxcr || sel_musycr || sel_musbtn || sel_kj) && sck_01 )
common_reg[7:0] <= { sdo, common_reg[7:1] };
// wait read data shift-in
if( !scs_n && sel_waitreg && sck_01 )
wait_reg[7:0] <= { sdo, wait_reg[7:1] };
// config shift-in
if( !scs_n && sel_cfg0 && sck_01 )
common_reg[7:0] <= { sdo, common_reg[7:1] };
// config output
if( scs_n_01 && sel_cfg0 )
cfg0_reg_out <= common_reg;
// SD data shift-in
if( !scs_n && sel_sddata && sck_01 )
common_reg[7:0] <= { sdo, common_reg[7:1] };
// SD control shift-in
if( !scs_n && sel_sdctrl && sck_01 )
common_reg[7:0] <= { sdo, common_reg[7:1] };
end
//
// SD control output
always @(posedge fclk, negedge rst_n)
if( !rst_n )
sdctrl <= 2'b01;
else // posedge clk
begin
if( scs_n_01 && sel_sdctrl )
sdctrl <= { common_reg[7], common_reg[0] };
end
// output data
assign kbd_out = kbd_reg;
assign kbd_stb = sel_kbdstb && scs_n_01;
assign mus_out = common_reg;
assign mus_xstb = sel_musxcr && scs_n_01;
assign mus_ystb = sel_musycr && scs_n_01;
assign mus_btnstb = sel_musbtn && scs_n_01;
assign kj_stb = sel_kj && scs_n_01;
assign genrst = sel_rstreg && scs_n_01;
assign wait_read = wait_reg;
assign wait_end = sel_waitreg && scs_n_01;
assign config0 = cfg0_reg_out;
// SD control output
assign sd_lock_out = sdctrl[1];
assign sd_cs_n = sdctrl[0];
// SD data output
assign sd_datain = common_reg;
// SD start strobe
assign sd_start = sel_sddata && scs_n_01;
endmodule
|
// sonic_pma_v1_03
`timescale 1 ps / 1 ps
module sonic_pma_v1_05 (
input wire phy_mgmt_clk, // phy_mgmt_clk.clk
input wire phy_mgmt_clk_reset, // phy_mgmt_clk_reset.reset
input wire [8:0] phy_mgmt_address, // phy_mgmt.address
input wire phy_mgmt_read, // .read
output wire [31:0] phy_mgmt_readdata, // .readdata
output wire phy_mgmt_waitrequest, // .waitrequest
input wire phy_mgmt_write, // .write
input wire [31:0] phy_mgmt_writedata, // .writedata
output wire [3:0] tx_ready, // tx_ready.export
output wire [3:0] rx_ready, // rx_ready.export
input wire [0:0] pll_ref_clk, // pll_ref_clk.clk
output wire [3:0] pll_locked, // pll_locked.export
output wire [3:0] tx_serial_data, // tx_serial_data.export
input wire [3:0] rx_serial_data, // rx_serial_data.export
output wire [3:0] rx_is_lockedtoref, // rx_is_lockedtoref.export
output wire [3:0] rx_is_lockedtodata, // rx_is_lockedtodata.export
output wire tx_clkout0, // tx_clkout0.clk
output wire tx_clkout1, // tx_clkout0.clk
output wire tx_clkout2, // tx_clkout0.clk
output wire tx_clkout3, // tx_clkout0.clk
output wire rx_clkout0, // rx_clkout0.clk
output wire rx_clkout1, // rx_clkout0.clk
output wire rx_clkout2, // rx_clkout0.clk
output wire rx_clkout3, // rx_clkout0.clk
input wire [39:0] tx_parallel_data0, // tx_parallel_data0.data
input wire [39:0] tx_parallel_data1, // tx_parallel_data0.data
input wire [39:0] tx_parallel_data2, // tx_parallel_data0.data
input wire [39:0] tx_parallel_data3, // tx_parallel_data0.data
output wire [39:0] rx_parallel_data0, // rx_parallel_data0.data
output wire [39:0] rx_parallel_data1, // rx_parallel_data0.data
output wire [39:0] rx_parallel_data2, // rx_parallel_data0.data
output wire [39:0] rx_parallel_data3 // rx_parallel_data0.data
);
wire [3:0] pll_powerdown;
wire [3:0] tx_digitalreset;
wire [3:0] tx_analogreset;
wire [3:0] rx_digitalreset;
wire [3:0] rx_analogreset;
wire [3:0] tx_pma_clkout;
wire [3:0] rx_pma_clkout;
wire [3:0] tx_cal_busy;
wire [3:0] rx_cal_busy;
wire reconfig_busy;
wire [159:0] rx_pma_parallel_data;
wire [159:0] tx_pma_parallel_data;
wire [367:0] reconfig_from_xcvr;
wire [559:0] reconfig_to_xcvr;
//----------------------------------------------------------------------
// Reconfiguration Controller
//----------------------------------------------------------------------
altera_xgbe_pma_reconfig_wrapper altera_xgbe_pma_reconfig_wrapper_inst(
/* inputs */
//----------------------------------------------------------------------
// Transceiver Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr),
.reconfig_mgmt_address (phy_mgmt_address),
.reconfig_mgmt_read (phy_mgmt_read),
.reconfig_mgmt_write (phy_mgmt_write),
.reconfig_mgmt_writedata (phy_mgmt_writedata),
// Reconfiguration mMnagement
.mgmt_rst_reset (phy_mgmt_clk_reset),
.mgmt_clk_clk (phy_mgmt_clk),
//----------------------------------------------------------------------
/* outputs */
//----------------------------------------------------------------------
// Transceiver Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr),
.reconfig_busy (reconfig_busy),
.reconfig_mgmt_readdata (phy_mgmt_readdata),
.reconfig_mgmt_waitrequest (phy_mgmt_waitrequest)
//----------------------------------------------------------------------
);
//----------------------------------------------------------------------
// Native PHY IP Transceiver Instance
//----------------------------------------------------------------------
altera_xcvr_native_sv_wrapper altera_xcvr_native_sv_wrapper_inst (
/*inputs */
//----------------------------------------------------------------------
// FPGA Fabric interface
.tx_pma_parallel_data (tx_pma_parallel_data),
.unused_tx_pma_parallel_data (),
// PLL, CDR, and Loopback
.tx_pll_refclk (pll_ref_clk),
.rx_cdr_refclk (pll_ref_clk),
.pll_powerdown (pll_powerdown),
.rx_seriallpbken (2'b0), // loopback mode
// Speed Serial I/O
.rx_serial_data (rx_serial_data),
// Reset And Calibration Status
.tx_digitalreset (tx_digitalreset),
.tx_analogreset (tx_analogreset),
.rx_digitalreset (rx_digitalreset),
.rx_analogreset (rx_analogreset),
// Transceiver Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr),
//----------------------------------------------------------------------
/* outputs */
//----------------------------------------------------------------------
// FPGA Fabric interface
.tx_pma_clkout (tx_pma_clkout),
.rx_pma_clkout (rx_pma_clkout),
.rx_pma_parallel_data (rx_pma_parallel_data),
.unused_rx_pma_parallel_data (),
// PLL, CDR, and Loopback
.pll_locked (pll_locked),
.rx_is_lockedtodata (rx_is_lockedtodata),
.rx_is_lockedtoref (rx_is_lockedtoref),
// Speed Serial I/O
.tx_serial_data (tx_serial_data),
// Reset And Calibration Status
.tx_cal_busy (tx_cal_busy),
.rx_cal_busy (rx_cal_busy),
// Transceiver Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr)
//----------------------------------------------------------------------
);
//----------------------------------------------------------------------
// Reset Controller
//----------------------------------------------------------------------
altera_xcvr_reset_control_wrapper altera_xcvr_reset_control_wrapper_inst (
/* inputs */
//----------------------------------------------------------------------
// PLL and Calibration Status
.pll_locked (pll_locked),
.pll_select (2'b11), // only needed for multiple PLLs
.tx_cal_busy (tx_cal_busy),
.rx_cal_busy (rx_cal_busy),
.rx_is_lockedtodata (rx_is_lockedtodata),
// Clock and Reset
.clock (phy_mgmt_clk),
.reset (phy_mgmt_clk_reset),
//----------------------------------------------------------------------
/* outputs */
//----------------------------------------------------------------------
// TX and RX Resets and Status
.tx_digitalreset (tx_digitalreset),
.tx_analogreset (tx_analogreset),
.tx_ready (tx_ready),
.rx_digitalreset (rx_digitalreset),
.rx_analogreset (rx_analogreset),
.rx_ready (rx_ready),
// PLL Powerdown
.pll_powerdown (pll_powerdown)
//----------------------------------------------------------------------
);
assign tx_pma_parallel_data = {tx_parallel_data3,tx_parallel_data2,tx_parallel_data1,tx_parallel_data0};
assign rx_parallel_data3 = rx_pma_parallel_data[159:120];
assign rx_parallel_data2 = rx_pma_parallel_data[119:80];
assign rx_parallel_data1 = rx_pma_parallel_data[79:40];
assign rx_parallel_data0 = rx_pma_parallel_data[39:0];
assign tx_clkout = tx_pma_clkout;
assign rx_clkout = rx_pma_clkout;
endmodule
|
/*
* File: imx_uocm.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Description:
* general purpose synchronous single-port memory
* Notes:
* 1, currently signal "oe" is NOT driven by this module, it should be used by
* memory controller to tag validation of read data.
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module imx_uocm(
clk,
ce, oe, we,
addr, di, doq
);
parameter aw = `UOCM_Word_BW; // 2**9 word = 2K Bytes (one xilinx block ram)
parameter dw = `OPERAND_WIDTH;
input clk;
input ce;
input we;
input oe;
input [aw-1:0] addr;
input [dw-1:0] di;
output [dw-1:0] doq;
//
// Internal wires and registers
//
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [aw-1:0] addr_reg;
//
// boot flash
//
initial begin
$readmemh("boot_binary.dat", mem);
end
//
// read access
//
// memory read address register for synchronous access
always @(posedge clk) begin
if (ce)
addr_reg <= addr;
end
// Data output
assign doq = mem[addr_reg];
//
// write access
//
always @(posedge clk) begin
if (we && ce)
mem[addr] <= di;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_SYMBOL_V
`define SKY130_FD_SC_HS__DFSBP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_SYMBOL_V
|
`timescale 1ns /1ps
module add_zero_delay ( o, a, b );
output [15:0] o;
input [15:0] a;
input [15:0] b;
wire n1, n2, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79,
n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163,
n164;
not #(0.000) U4 ( n60, n160 );
nor #(0.000) U5 ( n160, n161, n162 );
not #(0.000) U6 ( n52, n156 );
not #(0.000) U7 ( n45, n152 );
not #(0.000) U8 ( n38, n148 );
not #(0.000) U9 ( n31, n144 );
not #(0.000) U10 ( n24, n140 );
not #(0.000) U11 ( n17, n136 );
not #(0.000) U12 ( n10, n132 );
not #(0.000) U13 ( n109, n107 );
not #(0.000) U14 ( n98, n96 );
not #(0.000) U15 ( n87, n85 );
not #(0.000) U16 ( n73, n71 );
not #(0.000) U17 ( n120, n118 );
nor #(0.000) U18 ( o[2], n50, n51 );
and #(0.000) U19 ( n51, n52, n53 );
nor #(0.000) U20 ( n50, n52, n53 );
nand #(0.000) U21 ( n53, n54, n55 );
nor #(0.000) U22 ( o[3], n43, n44 );
and #(0.000) U23 ( n44, n45, n46 );
nor #(0.000) U24 ( n43, n45, n46 );
nand #(0.000) U25 ( n46, n47, n48 );
nor #(0.000) U26 ( o[4], n36, n37 );
and #(0.000) U27 ( n37, n38, n39 );
nor #(0.000) U28 ( n36, n38, n39 );
nand #(0.000) U29 ( n39, n40, n41 );
nor #(0.000) U30 ( o[5], n29, n30 );
and #(0.000) U31 ( n30, n31, n32 );
nor #(0.000) U32 ( n29, n31, n32 );
nand #(0.000) U33 ( n32, n33, n34 );
nor #(0.000) U34 ( o[6], n22, n23 );
and #(0.000) U35 ( n23, n24, n25 );
nor #(0.000) U36 ( n22, n24, n25 );
nand #(0.000) U37 ( n25, n26, n27 );
nor #(0.000) U38 ( o[7], n15, n16 );
and #(0.000) U39 ( n16, n17, n18 );
nor #(0.000) U40 ( n15, n17, n18 );
nand #(0.000) U41 ( n18, n19, n20 );
nor #(0.000) U42 ( o[8], n8, n9 );
and #(0.000) U43 ( n9, n10, n11 );
nor #(0.000) U44 ( n8, n10, n11 );
nand #(0.000) U45 ( n11, n12, n13 );
nor #(0.000) U46 ( o[9], n1, n2 );
and #(0.000) U47 ( n2, n3, n4 );
nor #(0.000) U48 ( n1, n3, n4 );
nand #(0.000) U49 ( n4, n5, n6 );
nor #(0.000) U50 ( o[10], n121, n122 );
and #(0.000) U51 ( n122, n120, n123 );
nor #(0.000) U52 ( n121, n120, n123 );
nand #(0.000) U53 ( n123, n124, n125 );
nor #(0.000) U54 ( o[11], n110, n111 );
and #(0.000) U55 ( n111, n109, n112 );
nor #(0.000) U56 ( n110, n109, n112 );
nand #(0.000) U57 ( n112, n113, n114 );
nor #(0.000) U58 ( o[12], n99, n100 );
and #(0.000) U59 ( n100, n98, n101 );
nor #(0.000) U60 ( n99, n98, n101 );
nand #(0.000) U61 ( n101, n102, n103 );
nor #(0.000) U62 ( o[13], n88, n89 );
and #(0.000) U63 ( n89, n87, n90 );
nor #(0.000) U64 ( n88, n87, n90 );
nand #(0.000) U65 ( n90, n91, n92 );
nor #(0.000) U66 ( o[14], n77, n78 );
and #(0.000) U67 ( n78, n73, n79 );
nor #(0.000) U68 ( n77, n73, n79 );
nand #(0.000) U69 ( n79, n80, n81 );
nor #(0.000) U70 ( o[15], n64, n65 );
and #(0.000) U71 ( n65, n66, n67 );
nor #(0.000) U72 ( n64, n67, n66 );
nand #(0.000) U73 ( n66, n68, n69 );
nand #(0.000) U74 ( o[1], n57, n58 );
or #(0.000) U75 ( n58, n59, n60 );
nand #(0.000) U76 ( n57, n59, n60 );
nand #(0.000) U77 ( n59, n61, n62 );
nand #(0.000) U78 ( n3, n129, n130 );
nand #(0.000) U79 ( n129, a[8], n10 );
nand #(0.000) U80 ( n130, b[8], n131 );
nand #(0.000) U81 ( n131, n132, n14 );
and #(0.000) U82 ( n156, n157, n158 );
nand #(0.000) U83 ( n158, b[1], n159 );
nand #(0.000) U84 ( n157, a[1], n160 );
nand #(0.000) U85 ( n159, n63, n60 );
and #(0.000) U86 ( n152, n153, n154 );
nand #(0.000) U87 ( n153, a[2], n52 );
nand #(0.000) U88 ( n154, b[2], n155 );
nand #(0.000) U89 ( n155, n156, n56 );
and #(0.000) U90 ( n148, n149, n150 );
nand #(0.000) U91 ( n149, a[3], n45 );
nand #(0.000) U92 ( n150, b[3], n151 );
nand #(0.000) U93 ( n151, n152, n49 );
and #(0.000) U94 ( n144, n145, n146 );
nand #(0.000) U95 ( n145, a[4], n38 );
nand #(0.000) U96 ( n146, b[4], n147 );
nand #(0.000) U97 ( n147, n148, n42 );
and #(0.000) U98 ( n107, n115, n116 );
nand #(0.000) U99 ( n115, a[10], n120 );
nand #(0.000) U100 ( n116, b[10], n117 );
nand #(0.000) U101 ( n117, n118, n119 );
and #(0.000) U102 ( n140, n141, n142 );
nand #(0.000) U103 ( n141, a[5], n31 );
nand #(0.000) U104 ( n142, b[5], n143 );
nand #(0.000) U105 ( n143, n144, n35 );
and #(0.000) U106 ( n96, n104, n105 );
nand #(0.000) U107 ( n104, a[11], n109 );
nand #(0.000) U108 ( n105, b[11], n106 );
nand #(0.000) U109 ( n106, n107, n108 );
and #(0.000) U110 ( n136, n137, n138 );
nand #(0.000) U111 ( n137, a[6], n24 );
nand #(0.000) U112 ( n138, b[6], n139 );
nand #(0.000) U113 ( n139, n140, n28 );
and #(0.000) U114 ( n85, n93, n94 );
nand #(0.000) U115 ( n93, a[12], n98 );
nand #(0.000) U116 ( n94, b[12], n95 );
nand #(0.000) U117 ( n95, n96, n97 );
and #(0.000) U118 ( n132, n133, n134 );
nand #(0.000) U119 ( n133, a[7], n17 );
nand #(0.000) U120 ( n134, b[7], n135 );
nand #(0.000) U121 ( n135, n136, n21 );
and #(0.000) U122 ( n71, n82, n83 );
nand #(0.000) U123 ( n82, a[13], n87 );
nand #(0.000) U124 ( n83, b[13], n84 );
nand #(0.000) U125 ( n84, n85, n86 );
and #(0.000) U126 ( n118, n126, n127 );
nand #(0.000) U127 ( n127, b[9], n128 );
nand #(0.000) U128 ( n126, a[9], n3 );
or #(0.000) U129 ( n128, n3, a[9] );
nand #(0.000) U130 ( n67, n74, n75 );
or #(0.000) U131 ( n74, n76, b[15] );
nand #(0.000) U132 ( n75, b[15], n76 );
not #(0.000) U133 ( n76, a[15] );
nand #(0.000) U134 ( n55, b[2], n56 );
nand #(0.000) U135 ( n48, b[3], n49 );
nand #(0.000) U136 ( n41, b[4], n42 );
nand #(0.000) U137 ( n34, b[5], n35 );
nand #(0.000) U138 ( n27, b[6], n28 );
nand #(0.000) U139 ( n20, b[7], n21 );
nand #(0.000) U140 ( n13, b[8], n14 );
nand #(0.000) U141 ( n125, b[10], n119 );
nand #(0.000) U142 ( n114, b[11], n108 );
nand #(0.000) U143 ( n103, b[12], n97 );
nand #(0.000) U144 ( n92, b[13], n86 );
nand #(0.000) U145 ( n81, b[14], n72 );
nand #(0.000) U146 ( n62, b[1], n63 );
nand #(0.000) U147 ( n69, b[14], n70 );
nand #(0.000) U148 ( n70, n71, n72 );
nand #(0.000) U149 ( n68, a[14], n73 );
not #(0.000) U150 ( n56, a[2] );
not #(0.000) U151 ( n49, a[3] );
not #(0.000) U152 ( n42, a[4] );
not #(0.000) U153 ( n35, a[5] );
not #(0.000) U154 ( n28, a[6] );
not #(0.000) U155 ( n21, a[7] );
not #(0.000) U156 ( n14, a[8] );
not #(0.000) U157 ( n119, a[10] );
not #(0.000) U158 ( n108, a[11] );
not #(0.000) U159 ( n97, a[12] );
not #(0.000) U160 ( n86, a[13] );
not #(0.000) U161 ( n72, a[14] );
nand #(0.000) U162 ( n6, b[9], n7 );
not #(0.000) U163 ( n63, a[1] );
not #(0.000) U164 ( n161, b[0] );
not #(0.000) U165 ( n162, a[0] );
nand #(0.000) U166 ( o[0], n163, n164 );
nand #(0.000) U167 ( n163, a[0], n161 );
nand #(0.000) U168 ( n164, b[0], n162 );
or #(0.000) U169 ( n61, n63, b[1] );
or #(0.000) U170 ( n54, n56, b[2] );
or #(0.000) U171 ( n47, n49, b[3] );
or #(0.000) U172 ( n40, n42, b[4] );
or #(0.000) U173 ( n33, n35, b[5] );
or #(0.000) U174 ( n26, n28, b[6] );
or #(0.000) U175 ( n19, n21, b[7] );
or #(0.000) U176 ( n12, n14, b[8] );
or #(0.000) U177 ( n5, n7, b[9] );
or #(0.000) U178 ( n124, n119, b[10] );
or #(0.000) U179 ( n113, n108, b[11] );
or #(0.000) U180 ( n102, n97, b[12] );
or #(0.000) U181 ( n91, n86, b[13] );
or #(0.000) U182 ( n80, n72, b[14] );
not #(0.000) U183 ( n7, a[9] );
endmodule
|
//====================================================
// This is FSM demo program using single always
// for both seq and combo logic
// Design Name : fsm_using_single_always
// File Name : fsm_using_single_always.v
//=====================================================
module fsm_using_single_always (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//=============Input Ports=============================
input clock,reset,req_0,req_1;
//=============Output Ports===========================
output gnt_0,gnt_1;
//=============Input ports Data Type===================
wire clock,reset,req_0,req_1;
//=============Output Ports Data Type==================
reg gnt_0,gnt_1;
//=============Internal Constants======================
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//=============Internal Variables======================
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//==========Code startes Here==========================
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT1;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT1;
end else begin
gnt_1 <= 0;
state <= #1 IDLE;
end
default : state <= #1 IDLE;
endcase
end
endmodule // End of Module arbiter |
/*
* PS2 Mouse without FIFO buffer
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_nofifo (
input clk,
input reset,
input [7:0] writedata, // data to send
input write, // signal to send it
output [7:0] readdata, // data read
output irq, // signal data has arrived
output command_was_sent,
output error_sending_command,
output buffer_overrun_error,
inout ps2_clk,
inout ps2_dat
);
// Unused outputs
wire start_receiving_data;
wire wait_for_incoming_data;
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse mouse (
.clk (clk),
.reset (reset),
.the_command (writedata),
.send_command (write),
.received_data (readdata),
.received_data_en (irq),
.command_was_sent (command_was_sent),
.error_communication_timed_out (error_sending_command),
.start_receiving_data (start_receiving_data),
.wait_for_incoming_data (wait_for_incoming_data),
.ps2_clk (ps2_clk),
.ps2_dat (ps2_dat)
);
// Continous assignments
assign buffer_overrun_error = error_sending_command;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 14:50:26
// Design Name:
// Module Name: _8_to_3_priority_encoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _8_to_3_priority_encoder(
input [7:0] v,
input en_in_n,
output reg [2:0] y,
output reg en_out,
output reg gs
);
always @(v or en_in_n) begin
case ({en_in_n, v})
9'b1_xxxx_xxxx: {y, gs, en_out} = 5'b1_1111;
9'b0_1111_1111: {y, gs, en_out} = 5'b1_1110;
9'b0_xxxx_xxx0: {y, gs, en_out} = 5'b0_0001;
9'b0_xxxx_xx01: {y, gs, en_out} = 5'b0_0101;
9'b0_xxxx_x011: {y, gs, en_out} = 5'b0_1001;
9'b0_xxxx_0111: {y, gs, en_out} = 5'b0_1101;
9'b0_xxx0_1111: {y, gs, en_out} = 5'b1_0001;
9'b0_xx01_1111: {y, gs, en_out} = 5'b1_0101;
9'b0_x011_1111: {y, gs, en_out} = 5'b1_1001;
9'b0_0111_1111: {y, gs, en_out} = 5'b1_1101;
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dirl_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_dirl_buf(/*AUTOARG*/
// Outputs
lkup_en_c4_buf, inval_mask_c4_buf, rw_dec_c4_buf, rd_en_c4_buf,
wr_en_c4_buf, rw_entry_c4_buf, lkup_wr_data_c4_buf,
dir_clear_c4_buf,
// Inputs
rd_en_c4, wr_en_c4, inval_mask_c4, rw_row_en_c4, rw_panel_en_c4,
rw_entry_c4, lkup_row_en_c4, lkup_panel_en_c4, lkup_wr_data_c4,
dir_clear_c4
);
input rd_en_c4; // Right
input wr_en_c4; // Right
input [7:0] inval_mask_c4; // Right
input [1:0] rw_row_en_c4; // Right
input [3:0] rw_panel_en_c4; // Right
input [5:0] rw_entry_c4; // Right
input [1:0] lkup_row_en_c4; // qualified already // Right
input [3:0] lkup_panel_en_c4; // qualified already // Right
input [32:0] lkup_wr_data_c4; // Bottom
input dir_clear_c4; // Right
output [7:0] lkup_en_c4_buf ; // Left
output [7:0] inval_mask_c4_buf ; // Left
output [7:0] rw_dec_c4_buf; // Left
output rd_en_c4_buf ; // Left
output wr_en_c4_buf ; // Left
output [5:0] rw_entry_c4_buf; // Left
output [32:0] lkup_wr_data_c4_buf; // Left 31(top) to 0(bottom)
output dir_clear_c4_buf; // Left
assign inval_mask_c4_buf = inval_mask_c4 ;
assign rd_en_c4_buf = rd_en_c4 ;
assign wr_en_c4_buf = wr_en_c4 ;
assign rw_entry_c4_buf = rw_entry_c4 ;
assign lkup_wr_data_c4_buf = lkup_wr_data_c4 ;
assign lkup_en_c4_buf[0] = lkup_row_en_c4[0] & lkup_panel_en_c4[0] ;
assign lkup_en_c4_buf[1] = lkup_row_en_c4[0] & lkup_panel_en_c4[1] ;
assign lkup_en_c4_buf[2] = lkup_row_en_c4[0] & lkup_panel_en_c4[2] ;
assign lkup_en_c4_buf[3] = lkup_row_en_c4[0] & lkup_panel_en_c4[3] ;
assign lkup_en_c4_buf[4] = lkup_row_en_c4[1] & lkup_panel_en_c4[0] ;
assign lkup_en_c4_buf[5] = lkup_row_en_c4[1] & lkup_panel_en_c4[1] ;
assign lkup_en_c4_buf[6] = lkup_row_en_c4[1] & lkup_panel_en_c4[2] ;
assign lkup_en_c4_buf[7] = lkup_row_en_c4[1] & lkup_panel_en_c4[3] ;
assign dir_clear_c4_buf = dir_clear_c4 ;
assign rw_dec_c4_buf[0] = rw_row_en_c4[0] & rw_panel_en_c4[0] ;
assign rw_dec_c4_buf[1] = rw_row_en_c4[0] & rw_panel_en_c4[1] ;
assign rw_dec_c4_buf[2] = rw_row_en_c4[0] & rw_panel_en_c4[2] ;
assign rw_dec_c4_buf[3] = rw_row_en_c4[0] & rw_panel_en_c4[3] ;
assign rw_dec_c4_buf[4] = rw_row_en_c4[1] & rw_panel_en_c4[0] ;
assign rw_dec_c4_buf[5] = rw_row_en_c4[1] & rw_panel_en_c4[1] ;
assign rw_dec_c4_buf[6] = rw_row_en_c4[1] & rw_panel_en_c4[2] ;
assign rw_dec_c4_buf[7] = rw_row_en_c4[1] & rw_panel_en_c4[3] ;
endmodule
|
/*
Copyright (c) 2017-2022 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* XFCP GTY DRP module
*/
module xfcp_mod_gty #
(
parameter XFCP_ID_TYPE = 16'h8A82,
parameter XFCP_ID_STR = "GTY DRP",
parameter XFCP_EXT_ID = 0,
parameter XFCP_EXT_ID_STR = "",
parameter ADDR_WIDTH = 10
)
(
input wire clk,
input wire rst,
/*
* XFCP upstream interface
*/
input wire [7:0] up_xfcp_in_tdata,
input wire up_xfcp_in_tvalid,
output wire up_xfcp_in_tready,
input wire up_xfcp_in_tlast,
input wire up_xfcp_in_tuser,
output wire [7:0] up_xfcp_out_tdata,
output wire up_xfcp_out_tvalid,
input wire up_xfcp_out_tready,
output wire up_xfcp_out_tlast,
output wire up_xfcp_out_tuser,
/*
* Transceiver interface
*/
output wire [ADDR_WIDTH-1:0] gty_drp_addr,
output wire [15:0] gty_drp_do,
input wire [15:0] gty_drp_di,
output wire gty_drp_en,
output wire gty_drp_we,
input wire gty_drp_rdy,
output wire gty_reset,
output wire gty_tx_pcs_reset,
output wire gty_tx_pma_reset,
output wire gty_rx_pcs_reset,
output wire gty_rx_pma_reset,
output wire gty_rx_dfe_lpm_reset,
output wire gty_eyescan_reset,
input wire gty_tx_reset_done,
input wire gty_tx_pma_reset_done,
input wire gty_rx_reset_done,
input wire gty_rx_pma_reset_done,
input wire gty_txusrclk2,
output wire [3:0] gty_txprbssel,
output wire gty_txprbsforceerr,
output wire gty_txpolarity,
output wire gty_txelecidle,
output wire gty_txinhibit,
output wire [4:0] gty_txdiffctrl,
output wire [6:0] gty_txmaincursor,
output wire [4:0] gty_txpostcursor,
output wire [4:0] gty_txprecursor,
input wire gty_rxusrclk2,
output wire gty_rxpolarity,
output wire gty_rxprbscntreset,
output wire [3:0] gty_rxprbssel,
input wire gty_rxprbserr,
input wire gty_rxprbslocked
);
wire [ADDR_WIDTH+1-1:0] wb_adr;
wire [15:0] wb_dat_m;
wire [15:0] wb_dat_drp;
wire wb_we;
wire wb_stb;
wire wb_ack_drp;
wire wb_cyc;
reg [15:0] wb_dat_int_reg = 16'd0, wb_dat_int_next;
reg wb_ack_int_reg = 1'b0, wb_ack_int_next;
reg gty_reset_reg = 1'b0, gty_reset_next;
reg gty_tx_pcs_reset_reg = 1'b0, gty_tx_pcs_reset_next;
reg gty_tx_pma_reset_reg = 1'b0, gty_tx_pma_reset_next;
reg gty_rx_pcs_reset_reg = 1'b0, gty_rx_pcs_reset_next;
reg gty_rx_pma_reset_reg = 1'b0, gty_rx_pma_reset_next;
reg gty_rx_dfe_lpm_reset_reg = 1'b0, gty_rx_dfe_lpm_reset_next;
reg gty_eyescan_reset_reg = 1'b0, gty_eyescan_reset_next;
assign gty_reset = gty_reset_reg;
assign gty_tx_pcs_reset = gty_tx_pcs_reset_reg;
assign gty_tx_pma_reset = gty_tx_pma_reset_reg;
assign gty_rx_pcs_reset = gty_rx_pcs_reset_reg;
assign gty_rx_pma_reset = gty_rx_pma_reset_reg;
assign gty_rx_dfe_lpm_reset = gty_rx_dfe_lpm_reset_reg;
assign gty_eyescan_reset = gty_eyescan_reset_reg;
reg gty_tx_reset_done_reg = 1'b0;
reg gty_tx_reset_done_sync_1_reg = 1'b0, gty_tx_reset_done_sync_2_reg = 1'b0;
reg gty_tx_pma_reset_done_reg = 1'b0;
reg gty_tx_pma_reset_done_sync_1_reg = 1'b0, gty_tx_pma_reset_done_sync_2_reg = 1'b0;
reg gty_rx_reset_done_reg = 1'b0;
reg gty_rx_reset_done_sync_1_reg = 1'b0, gty_rx_reset_done_sync_2_reg = 1'b0;
reg gty_rx_pma_reset_done_reg = 1'b0;
reg gty_rx_pma_reset_done_sync_1_reg = 1'b0, gty_rx_pma_reset_done_sync_2_reg = 1'b0;
always @(posedge gty_txusrclk2) begin
gty_tx_reset_done_reg <= gty_tx_reset_done;
gty_tx_pma_reset_done_reg <= gty_tx_pma_reset_done;
end
always @(posedge gty_rxusrclk2) begin
gty_rx_reset_done_reg <= gty_rx_reset_done;
gty_rx_pma_reset_done_reg <= gty_rx_pma_reset_done;
end
always @(posedge clk) begin
gty_tx_reset_done_sync_1_reg <= gty_tx_reset_done_reg;
gty_tx_reset_done_sync_2_reg <= gty_tx_reset_done_sync_1_reg;
gty_tx_pma_reset_done_sync_1_reg <= gty_tx_pma_reset_done_reg;
gty_tx_pma_reset_done_sync_2_reg <= gty_tx_pma_reset_done_sync_1_reg;
gty_rx_reset_done_sync_1_reg <= gty_rx_reset_done_reg;
gty_rx_reset_done_sync_2_reg <= gty_rx_reset_done_sync_1_reg;
gty_rx_pma_reset_done_sync_1_reg <= gty_rx_pma_reset_done_reg;
gty_rx_pma_reset_done_sync_2_reg <= gty_rx_pma_reset_done_sync_1_reg;
end
reg [3:0] gty_txprbssel_reg = 4'd0, gty_txprbssel_next;
reg [3:0] gty_txprbssel_sync_reg = 4'd0;
reg gty_txprbsforceerr_reg = 1'b0, gty_txprbsforceerr_next;
reg gty_txprbsforceerr_sync_1_reg = 1'b0, gty_txprbsforceerr_sync_2_reg = 1'b0, gty_txprbsforceerr_sync_3_reg = 1'b0;
reg gty_txpolarity_reg = 1'b0, gty_txpolarity_next;
reg gty_txpolarity_sync_reg = 1'b0;
reg gty_txelecidle_reg = 1'b0, gty_txelecidle_next;
reg gty_txelecidle_sync_reg = 1'b0;
reg gty_txinhibit_reg = 1'b0, gty_txinhibit_next;
reg gty_txinhibit_sync_reg = 1'b0;
reg [4:0] gty_txdiffctrl_reg = 5'd16, gty_txdiffctrl_next;
reg [4:0] gty_txdiffctrl_sync_reg = 5'd16;
reg [6:0] gty_txmaincursor_reg = 7'd64, gty_txmaincursor_next;
reg [6:0] gty_txmaincursor_sync_reg = 7'd64;
reg [4:0] gty_txpostcursor_reg = 5'd0, gty_txpostcursor_next;
reg [4:0] gty_txpostcursor_sync_reg = 5'd0;
reg [4:0] gty_txprecursor_reg = 5'd0, gty_txprecursor_next;
reg [4:0] gty_txprecursor_sync_reg = 5'd0;
always @(posedge gty_txusrclk2) begin
gty_txprbssel_sync_reg <= gty_txprbssel_reg;
gty_txprbsforceerr_sync_1_reg <= gty_txprbsforceerr_reg;
gty_txprbsforceerr_sync_2_reg <= gty_txprbsforceerr_sync_1_reg;
gty_txprbsforceerr_sync_3_reg <= gty_txprbsforceerr_sync_2_reg;
gty_txpolarity_sync_reg <= gty_txpolarity_reg;
gty_txelecidle_sync_reg <= gty_txelecidle_reg;
gty_txinhibit_sync_reg <= gty_txinhibit_reg;
gty_txdiffctrl_sync_reg <= gty_txdiffctrl_reg;
gty_txmaincursor_sync_reg <= gty_txmaincursor_reg;
gty_txpostcursor_sync_reg <= gty_txpostcursor_reg;
gty_txprecursor_sync_reg <= gty_txprecursor_reg;
end
assign gty_txprbssel = gty_txprbssel_sync_reg;
assign gty_txprbsforceerr = gty_txprbsforceerr_sync_2_reg ^ gty_txprbsforceerr_sync_3_reg;
assign gty_txpolarity = gty_txpolarity_sync_reg;
assign gty_txelecidle = gty_txelecidle_sync_reg;
assign gty_txinhibit = gty_txinhibit_sync_reg;
assign gty_txdiffctrl = gty_txdiffctrl_sync_reg;
assign gty_txmaincursor = gty_txmaincursor_sync_reg;
assign gty_txpostcursor = gty_txpostcursor_sync_reg;
assign gty_txprecursor = gty_txprecursor_sync_reg;
reg gty_rxpolarity_reg = 1'b0, gty_rxpolarity_next;
reg gty_rxpolarity_sync_reg = 1'b0;
reg gty_rxprbscntreset_reg = 1'b0, gty_rxprbscntreset_next;
reg gty_rxprbscntreset_sync_1_reg = 1'b0, gty_rxprbscntreset_sync_2_reg = 1'b0, gty_rxprbscntreset_sync_3_reg = 1'b0;
reg [3:0] gty_rxprbssel_reg = 4'd0, gty_rxprbssel_next;
reg [3:0] gty_rxprbssel_sync_reg = 4'd0;
reg gty_rxprbserr_reg = 1'b0, gty_rxprbserr_next;
reg gty_rxprbserr_sync_1_reg = 1'b0, gty_rxprbserr_sync_2_reg = 1'b0, gty_rxprbserr_sync_3_reg = 1'b0;
reg gty_rxprbserr_sync_4_reg = 1'b0, gty_rxprbserr_sync_5_reg = 1'b0;
reg gty_rxprbslocked_reg = 1'b0;
reg gty_rxprbslocked_sync_1_reg = 1'b0, gty_rxprbslocked_sync_2_reg = 1'b0;
always @(posedge gty_rxusrclk2) begin
gty_rxpolarity_sync_reg <= gty_rxpolarity_reg;
gty_rxprbscntreset_sync_1_reg <= gty_rxprbscntreset_reg;
gty_rxprbscntreset_sync_2_reg <= gty_rxprbscntreset_sync_1_reg;
gty_rxprbscntreset_sync_3_reg <= gty_rxprbscntreset_sync_2_reg;
gty_rxprbssel_sync_reg <= gty_rxprbssel_reg;
gty_rxprbserr_sync_1_reg <= (gty_rxprbserr_sync_1_reg && !gty_rxprbserr_sync_5_reg) || gty_rxprbserr;
gty_rxprbserr_sync_4_reg <= gty_rxprbserr_sync_3_reg;
gty_rxprbserr_sync_5_reg <= gty_rxprbserr_sync_4_reg;
gty_rxprbslocked_reg <= gty_rxprbslocked;
end
always @(posedge clk) begin
gty_rxprbserr_sync_2_reg <= gty_rxprbserr_sync_1_reg;
gty_rxprbserr_sync_3_reg <= gty_rxprbserr_sync_2_reg;
gty_rxprbslocked_sync_1_reg <= gty_rxprbslocked_reg;
gty_rxprbslocked_sync_2_reg <= gty_rxprbslocked_sync_1_reg;
end
assign gty_rxpolarity = gty_rxpolarity_sync_reg;
assign gty_rxprbscntreset = gty_rxprbscntreset_sync_2_reg ^ gty_rxprbscntreset_sync_3_reg;
assign gty_rxprbssel = gty_rxprbssel_sync_reg;
wire sel_drp = !wb_adr[ADDR_WIDTH];
always @* begin
wb_dat_int_next = 16'd0;
wb_ack_int_next = 1'b0;
gty_reset_next = gty_reset_reg;
gty_tx_pcs_reset_next = gty_tx_pcs_reset_reg;
gty_tx_pma_reset_next = gty_tx_pma_reset_reg;
gty_rx_pcs_reset_next = gty_rx_pcs_reset_reg;
gty_rx_pma_reset_next = gty_rx_pma_reset_reg;
gty_rx_dfe_lpm_reset_next = gty_rx_dfe_lpm_reset_reg;
gty_eyescan_reset_next = gty_eyescan_reset_reg;
gty_txprbssel_next = gty_txprbssel_reg;
gty_txprbsforceerr_next = gty_txprbsforceerr_reg;
gty_txpolarity_next = gty_txpolarity_reg;
gty_txelecidle_next = gty_txelecidle_reg;
gty_txinhibit_next = gty_txinhibit_reg;
gty_txdiffctrl_next = gty_txdiffctrl_reg;
gty_txmaincursor_next = gty_txmaincursor_reg;
gty_txpostcursor_next = gty_txpostcursor_reg;
gty_txprecursor_next = gty_txprecursor_reg;
gty_rxpolarity_next = gty_rxpolarity_reg;
gty_rxprbscntreset_next = gty_rxprbscntreset_reg;
gty_rxprbssel_next = gty_rxprbssel_reg;
gty_rxprbserr_next = gty_rxprbserr_reg || gty_rxprbserr_sync_3_reg;
if (!sel_drp && wb_cyc && wb_stb && !wb_ack_int_reg) begin
if (wb_we) begin
// write
case (wb_adr[7:0])
8'h00: begin
gty_reset_next = wb_dat_m[0];
gty_tx_pcs_reset_next = wb_dat_m[1];
gty_tx_pma_reset_next = wb_dat_m[2];
gty_rx_pcs_reset_next = wb_dat_m[3];
gty_rx_pma_reset_next = wb_dat_m[4];
gty_rx_dfe_lpm_reset_next = wb_dat_m[5];
gty_eyescan_reset_next = wb_dat_m[6];
end
8'h01: begin
gty_txpolarity_next = wb_dat_m[0];
gty_rxpolarity_next = wb_dat_m[1];
end
8'h02: begin
gty_txprbssel_next = wb_dat_m[3:0];
gty_rxprbssel_next = wb_dat_m[7:4];
end
8'h03: begin
gty_txprbsforceerr_next = gty_txprbsforceerr_reg ^ wb_dat_m[0];
gty_rxprbscntreset_next = gty_rxprbscntreset_reg ^ wb_dat_m[1];
end
8'h04: begin
gty_txelecidle_next = wb_dat_m[0];
gty_txinhibit_next = wb_dat_m[1];
end
8'h05: begin
gty_txdiffctrl_next = wb_dat_m[4:0];
end
8'h06: begin
gty_txmaincursor_next = wb_dat_m[6:0];
end
8'h07: begin
gty_txpostcursor_next = wb_dat_m[4:0];
end
8'h08: begin
gty_txprecursor_next = wb_dat_m[4:0];
end
endcase
wb_ack_int_next = 1'b1;
end else begin
// read
case (wb_adr[7:0])
8'h00: begin
wb_dat_int_next[0] = gty_reset_reg;
wb_dat_int_next[1] = gty_tx_pcs_reset_reg;
wb_dat_int_next[2] = gty_tx_pma_reset_reg;
wb_dat_int_next[3] = gty_rx_pcs_reset_reg;
wb_dat_int_next[4] = gty_rx_pma_reset_reg;
wb_dat_int_next[5] = gty_rx_dfe_lpm_reset_reg;
wb_dat_int_next[6] = gty_eyescan_reset_reg;
wb_dat_int_next[8] = gty_tx_reset_done_sync_2_reg;
wb_dat_int_next[9] = gty_tx_pma_reset_done_sync_2_reg;
wb_dat_int_next[10] = gty_rx_reset_done_sync_2_reg;
wb_dat_int_next[11] = gty_rx_pma_reset_done_sync_2_reg;
end
8'h01: begin
wb_dat_int_next[0] = gty_txpolarity_reg;
wb_dat_int_next[1] = gty_rxpolarity_reg;
end
8'h02: begin
wb_dat_int_next[3:0] = gty_txprbssel_reg;
wb_dat_int_next[7:4] = gty_rxprbssel_reg;
end
8'h03: begin
wb_dat_int_next[2] = gty_rxprbserr_reg;
wb_dat_int_next[3] = gty_rxprbslocked_sync_2_reg;
gty_rxprbserr_next = gty_rxprbserr_sync_3_reg;
end
8'h04: begin
wb_dat_int_next[0] = gty_txelecidle_reg;
wb_dat_int_next[1] = gty_txinhibit_reg;
end
8'h05: begin
wb_dat_int_next[4:0] = gty_txdiffctrl_reg;
end
8'h06: begin
wb_dat_int_next[6:0] = gty_txmaincursor_reg;
end
8'h07: begin
wb_dat_int_next[4:0] = gty_txpostcursor_reg;
end
8'h08: begin
wb_dat_int_next[4:0] = gty_txprecursor_reg;
end
endcase
wb_ack_int_next = 1'b1;
end
end
end
always @(posedge clk) begin
wb_dat_int_reg <= wb_dat_int_next;
wb_ack_int_reg <= wb_ack_int_next;
gty_reset_reg <= gty_reset_next;
gty_tx_pcs_reset_reg <= gty_tx_pcs_reset_next;
gty_tx_pma_reset_reg <= gty_tx_pma_reset_next;
gty_rx_pcs_reset_reg <= gty_rx_pcs_reset_next;
gty_rx_pma_reset_reg <= gty_rx_pma_reset_next;
gty_rx_dfe_lpm_reset_reg <= gty_rx_dfe_lpm_reset_next;
gty_eyescan_reset_reg <= gty_eyescan_reset_next;
gty_txprbssel_reg <= gty_txprbssel_next;
gty_txprbsforceerr_reg <= gty_txprbsforceerr_next;
gty_txpolarity_reg <= gty_txpolarity_next;
gty_txelecidle_reg <= gty_txelecidle_next;
gty_txinhibit_reg <= gty_txinhibit_next;
gty_txdiffctrl_reg <= gty_txdiffctrl_next;
gty_txmaincursor_reg <= gty_txmaincursor_next;
gty_txpostcursor_reg <= gty_txpostcursor_next;
gty_txprecursor_reg <= gty_txprecursor_next;
gty_rxpolarity_reg <= gty_rxpolarity_next;
gty_rxprbscntreset_reg <= gty_rxprbscntreset_next;
gty_rxprbssel_reg <= gty_rxprbssel_next;
gty_rxprbserr_reg <= gty_rxprbserr_next;
if (rst) begin
wb_ack_int_reg <= 1'b0;
gty_reset_reg <= 1'b0;
gty_tx_pcs_reset_reg <= 1'b0;
gty_tx_pma_reset_reg <= 1'b0;
gty_rx_pcs_reset_reg <= 1'b0;
gty_rx_pma_reset_reg <= 1'b0;
gty_rx_dfe_lpm_reset_reg <= 1'b0;
gty_eyescan_reset_reg <= 1'b0;
gty_txprbssel_reg <= 4'd0;
gty_txprbsforceerr_reg <= 1'b0;
gty_txpolarity_reg <= 1'b0;
gty_txelecidle_reg <= 1'b0;
gty_txinhibit_reg <= 1'b0;
gty_txdiffctrl_reg <= 5'd16;
gty_txmaincursor_reg <= 7'd64;
gty_txpostcursor_reg <= 5'd0;
gty_txprecursor_reg <= 5'd0;
gty_rxpolarity_reg <= 1'b0;
gty_rxprbscntreset_reg <= 1'b0;
gty_rxprbssel_reg <= 4'd0;
gty_rxprbserr_reg <= 1'b0;
end
end
xfcp_mod_wb #(
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(16),
.WB_ADDR_WIDTH(ADDR_WIDTH+1),
.WB_SELECT_WIDTH(1)
)
xfcp_mod_wb_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.wb_adr_o(wb_adr),
.wb_dat_i(wb_ack_int_reg ? wb_dat_int_reg : wb_dat_drp),
.wb_dat_o(wb_dat_m),
.wb_we_o(wb_we),
.wb_sel_o(),
.wb_stb_o(wb_stb),
.wb_ack_i(wb_ack_int_reg ? wb_ack_int_reg : wb_ack_drp),
.wb_err_i(1'b0),
.wb_cyc_o(wb_cyc)
);
wb_drp #(
.ADDR_WIDTH(ADDR_WIDTH)
)
wb_drp_inst (
.clk(clk),
.rst(rst),
.wb_adr_i(wb_adr[ADDR_WIDTH-1:0]),
.wb_dat_i(wb_dat_m),
.wb_dat_o(wb_dat_drp),
.wb_we_i(wb_we),
.wb_stb_i(wb_stb && sel_drp),
.wb_ack_o(wb_ack_drp),
.wb_cyc_i(wb_cyc && sel_drp),
.drp_addr(gty_drp_addr),
.drp_do(gty_drp_do),
.drp_di(gty_drp_di),
.drp_en(gty_drp_en),
.drp_we(gty_drp_we),
.drp_rdy(gty_drp_rdy)
);
endmodule
|
`timescale 1 ns / 1 ps
module hapara_axis_id_generator_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4,
// Parameters of Axi Master Bus Interface M00_AXIS
parameter integer C_M00_AXIS_TDATA_WIDTH = 32
// parameter integer C_M00_AXIS_START_COUNT = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready,
// Ports of Axi Master Bus Interface M00_AXIS
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire m00_axis_tvalid,
output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
// output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
output wire m00_axis_tlast,
input wire m00_axis_tready
);
wire En;
wire Finish;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] orgX;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] orgY;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] lengthX;
// wire [C_S00_AXI_DATA_WIDTH - 1 : 0] lengthY;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] org;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] len;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] numOfSlv;
// Instantiation of Axi Bus Interface S00_AXI
hapara_axis_id_generator_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) hapara_axis_id_generator_v1_0_S00_AXI_inst (
.En(En),
.Finish(Finish),
.org(org),
.len(len),
.numOfSlv(numOfSlv),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Instantiation of Axi Bus Interface M00_AXIS
hapara_axis_id_generator_v1_0_M00_AXIS # (
.C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
// .C_M_START_COUNT(C_M00_AXIS_START_COUNT)
) hapara_axis_id_generator_v1_0_M00_AXIS_inst (
.En(En),
.Finish(Finish),
.org(org),
.len(len),
.numOfSlv(numOfSlv),
.M_AXIS_ACLK(m00_axis_aclk),
.M_AXIS_ARESETN(m00_axis_aresetn),
.M_AXIS_TVALID(m00_axis_tvalid),
.M_AXIS_TDATA(m00_axis_tdata),
// .M_AXIS_TSTRB(m00_axis_tstrb),
.M_AXIS_TLAST(m00_axis_tlast),
.M_AXIS_TREADY(m00_axis_tready)
);
// Add user logic here
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_4_V
`define SKY130_FD_SC_MS__A211O_4_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211o_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_4_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ec_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ec_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_ec_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ec_e
//
// No user `defines in this module
module inst_ec_e
//
// Generated Module inst_ec
//
(
p_mix_c_addr_12_0_gi,
p_mix_c_bus_in_31_0_gi,
p_mix_v_select_2_2_gi,
p_mix_v_select_5_5_gi
);
// Generated Module Inputs:
input [12:0] p_mix_c_addr_12_0_gi;
input [31:0] p_mix_c_bus_in_31_0_gi;
input p_mix_v_select_2_2_gi;
input p_mix_v_select_5_5_gi;
// Generated Wires:
wire [12:0] p_mix_c_addr_12_0_gi;
wire [31:0] p_mix_c_bus_in_31_0_gi;
wire p_mix_v_select_2_2_gi;
wire p_mix_v_select_5_5_gi;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [12:0] c_addr; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] c_bus_in; // __W_PORT_SIGNAL_MAP_REQ
wire [5:0] v_select; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign c_addr = p_mix_c_addr_12_0_gi; // __I_I_BUS_PORT
assign c_bus_in = p_mix_c_bus_in_31_0_gi; // __I_I_BUS_PORT
assign v_select[5] = p_mix_v_select_5_5_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign v_select[2] = p_mix_v_select_2_2_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eca
inst_eca_e inst_eca (
.c_add(c_addr),
.c_bus_in(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.v_select(v_select) // RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
// End of Generated Instance Port Map for inst_eca
// Generated Instance Port Map for inst_ecb
inst_ecb_e inst_ecb (
.c_addr(c_addr),
.c_bus_in(c_bus_in) // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
// End of Generated Instance Port Map for inst_ecb
// Generated Instance Port Map for inst_ecc
inst_ecc_e inst_ecc (
.c_addr(c_addr),
.c_bus_in(c_bus_in) // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
// End of Generated Instance Port Map for inst_ecc
endmodule
//
// End of Generated Module rtl of inst_ec_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : relojes.v
// /___/ /\ Timestamp : 06/01/2016 18:29:52
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st C:\Users\rodriguj\Documents\zxspectrum\zxuno\cores\cores_para_testar_la_placa\test_sram_y_video\ipcore_dir\relojes.xaw C:\Users\rodriguj\Documents\zxspectrum\zxuno\cores\cores_para_testar_la_placa\test_sram_y_video\ipcore_dir\relojes
//Design Name: relojes
//Device: xc3s250e-4tq144
//
// Module relojes
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.92 ns
`timescale 1ns / 1ps
module relojes(CLKIN_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(10.0), .CLKFX_DIVIDE(25),
.CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A32O_PP_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_V
`define SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FAH_PP_SYMBOL_V
/**
* fah: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_PP_SYMBOL_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(**************************************************************)
(* MSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable Setoid DecidableTypeEx MSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecideOn (E : DecidableType)(Import M : WSetsOn E).
Module F := MSetFacts.WFactsOn E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the MSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module MSetLogicalFacts.
Export Decidable.
Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isn't decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End MSetLogicalFacts.
Import MSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module MSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
Ltac abstract_term t :=
tryif (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-MSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive MSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
MSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
MSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
MSet_elt_Prop (In x s)
| True_elt_prop :
MSet_elt_Prop True
| False_elt_prop :
MSet_elt_Prop False
| conj_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
MSet_elt_Prop P ->
MSet_elt_Prop (~ P).
Inductive MSet_Prop : Prop -> Prop :=
| elt_MSet_Prop : forall P,
MSet_elt_Prop P ->
MSet_Prop P
| Empty_MSet_Prop : forall s,
MSet_Prop (Empty s)
| Subset_MSet_Prop : forall s1 s2,
MSet_Prop (Subset s1 s2)
| Equal_MSet_Prop : forall s1 s2,
MSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
#[global]
Hint Constructors MSet_elt_Prop MSet_Prop : MSet_Prop.
Ltac discard_nonMSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
tryif (change T with E.t in H) then fail
else tryif (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
tryif prop (MSet_Prop P) holds by
(auto 100 with MSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [MSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of MSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [MSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
#[global]
Hint Resolve dec_In dec_eq : MSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substMSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_MSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substMSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_MSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using MSet_decidability;
substMSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End MSetDecideAuxiliary.
Import MSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonMSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonMSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [MSet_elt_Prop], noting
that any [MSet_elt_Prop] is decidable. *)
pull not using MSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
tryif prop (MSet_elt_Prop P) holds by
(auto 100 with MSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module MSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End MSetDecideTestCases.
End WDecideOn.
Require Import MSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WSets) := !WDecideOn M.E M.
Module Decide := WDecide.
|
module premuat1_16(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
output signed [15:0] o_8;
output signed [15:0] o_9;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [15:0] o1;
reg signed [15:0] o2;
reg signed [15:0] o3;
reg signed [15:0] o4;
reg signed [15:0] o5;
reg signed [15:0] o6;
reg signed [15:0] o7;
reg signed [15:0] o8;
reg signed [15:0] o9;
reg signed [15:0] o10;
reg signed [15:0] o11;
reg signed [15:0] o12;
reg signed [15:0] o13;
reg signed [15:0] o14;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2;
o2 =i_4;
o3 =i_6;
o4 =i_8;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_1;
o9 =i_3;
o10=i_5;
o11=i_7;
o12=i_9;
o13=i_11;
o14=i_13;
end
else
begin
o1 =i_8;
o2 =i_1;
o3 =i_9;
o4 =i_2;
o5 =i_10;
o6 =i_3;
o7 =i_11;
o8 =i_4;
o9 =i_12;
o10=i_5;
o11=i_13;
o12=i_6;
o13=i_14;
o14=i_7;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=i_15;
endmodule
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