text
stringlengths 938
1.05M
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module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
/*
* Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
* TxD_data is latched so that it doesn't have to stay valid while it is being sent
*/
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 9600;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
/* ============================== */
`ifdef SIMULATION
/* output one bit per clock cycle */
wire BitTick = 1'b1;
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state < 4) | (TxD_state[3] & TxD_shift[0]);
endmodule
|
//*******************************************************************************************
// Description: Netlist for FLPv3L's MBus Register File
// Generated by genRF (Version 1.01) 08/25/2017 00:09:00
//*******************************************************************************************
//*******************************************************************************************
// MEMORY MAP
//*******************************************************************************************
// MBUS ADDR || Register Name || Reset Value || Type || Comments
//*******************************************************************************************
// 8'h00 || REGISTER 0x00 ( 0) || || ||
//-------------------------------------------------------------------------------------------
// 8'h00 [23:19] || Tcyc_read || 5'h1F || W/R || Default: ~30us
// 8'h00 [18:13] || T3us || 6'h02 || W/R || Default: ~3us
// 8'h00 [12: 7] || T5us || 6'h04 || W/R || Default: ~5us
// 8'h00 [ 6: 0] || T10us || 7'h09 || W/R || Default: ~10us
//*******************************************************************************************
// 8'h01 || REGISTER 0x01 ( 1) || || ||
//-------------------------------------------------------------------------------------------
// 8'h01 [23: 8] || Tcyc_prog || 16'h007F || W/R || Default: ~128us
// 8'h01 [ 7: 0] || Tprog || 8'h09 || W/R || Default: ~10us
//*******************************************************************************************
// 8'h02 || REGISTER 0x02 ( 2) || || ||
//-------------------------------------------------------------------------------------------
// 8'h02 [15: 0] || Terase || 16'h0100 || W/R || Default: ~256us
//*******************************************************************************************
// 8'h03 || REGISTER 0x03 ( 3) || || ||
//-------------------------------------------------------------------------------------------
// 8'h03 [23:10] || Thvcp_en || 14'h03E8 || W/R || Default: ~1ms
// 8'h03 [ 9: 0] || Tben || 10'h031 || W/R || Default: ~50us
//*******************************************************************************************
// 8'h04 || REGISTER 0x04 ( 4) || || ||
//-------------------------------------------------------------------------------------------
// 8'h04 [23:12] || Tmvcp_en || 12'h3E8 || W/R || Default: ~1ms
// 8'h04 [11: 0] || Tsc_en || 12'h3E8 || W/R || Default: ~1ms
//*******************************************************************************************
// 8'h05 || REGISTER 0x05 ( 5) || || ||
//-------------------------------------------------------------------------------------------
// 8'h05 [19: 0] || Tcap || 20'h007CF || W/R || Default: ~2ms
//*******************************************************************************************
// 8'h06 || REGISTER 0x06 ( 6) || || ||
//-------------------------------------------------------------------------------------------
// 8'h06 [16: 0] || Tvref || 17'h01F3F || W/R || Default: ~8ms
//*******************************************************************************************
// 8'h07 || REGISTER 0x07 ( 7) || || ||
//-------------------------------------------------------------------------------------------
// 8'h07 [12: 0] || SRAM_START_ADDR || 13'h0000 || LC ||
//*******************************************************************************************
// 8'h08 || REGISTER 0x08 ( 8) || || ||
//-------------------------------------------------------------------------------------------
// 8'h08 [17: 0] || FLSH_START_ADDR || 18'h00000 || LC ||
//*******************************************************************************************
// 8'h09 || REGISTER 0x09 ( 9) || || ||
//-------------------------------------------------------------------------------------------
// 8'h09 [18: 6] || LENGTH || 13'h0000 || LC ||
// 8'h09 [ 5] || IRQ_EN || 1'h0 || LC ||
// 8'h09 [ 4: 1] || CMD || 4'h0 || LC ||
// 8'h09 [ 0] || GO || 1'h0 || LC ||
//*******************************************************************************************
// 8'h0A || REGISTER 0x0A ( 10) || || ||
//-------------------------------------------------------------------------------------------
// 8'h0A [ 4] || VREF_SLEEP || 1'h1 || W/R ||
// 8'h0A [ 3] || COMP_SLEEP || 1'h1 || W/R ||
// 8'h0A [ 2] || COMP_CLKENB || 1'h1 || W/R ||
// 8'h0A [ 1] || COMP_ISOL || 1'h1 || W/R ||
//*******************************************************************************************
// 8'h0B || REGISTER 0x0B ( 11) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h0C || REGISTER 0x0C ( 12) || || ||
//-------------------------------------------------------------------------------------------
// 8'h0C [ 3] || WRAP_EXT || 1'h0 || W/R ||
// 8'h0C [ 2] || UPDATE_ADDR_EXT || 1'h0 || W/R ||
// 8'h0C [ 1: 0] || BIT_EN_EXT || 2'h1 || W/R ||
//*******************************************************************************************
// 8'h0D || REGISTER 0x0D ( 13) || || ||
//-------------------------------------------------------------------------------------------
// 8'h0D [19: 0] || TIMEOUT_EXT || 20'hFFFFF || W/R || 0 means no time-limit
//*******************************************************************************************
// 8'h0E || REGISTER 0x0E ( 14) || || ||
//-------------------------------------------------------------------------------------------
// 8'h0E [12: 0] || SRAM_START_ADDR_EXT || 13'h0000 || W/R || will be updated at the end of Ext Streaming
//*******************************************************************************************
// 8'h0F || REGISTER 0x0F ( 15) || || ||
//-------------------------------------------------------------------------------------------
// 8'h0F [15: 8] || INT_RPLY_SHORT_ADDR || 8'h10 || W/R ||
// 8'h0F [ 7: 0] || INT_RPLY_REG_ADDR || 8'h00 || W/R ||
//*******************************************************************************************
// 8'h10 || REGISTER 0x10 ( 16) || || ||
//-------------------------------------------------------------------------------------------
// 8'h10 [ 22] || BOOT_FLAG_SLEEP || 1'h0 || W/R ||
// 8'h10 [ 21] || BOOT_FLAG_ECC_ERROR || 1'h0 || W/R ||
// 8'h10 [ 20] || BOOT_FLAG_WRONG_HEADER || 1'h0 || W/R ||
// 8'h10 [ 19] || BOOT_FLAG_PWDN || 1'h0 || W/R ||
// 8'h10 [ 18] || BOOT_FLAG_INVALID_CMND || 1'h0 || W/R ||
// 8'h10 [ 17] || BOOT_FLAG_CHKSUM_ERROR || 1'h0 || W/R ||
// 8'h10 [ 16] || BOOT_FLAG_SUCCESS || 1'h0 || W/R ||
// 8'h10 [ 1: 0] || BOOT_REG_PATTERN || 2'h0 || W/R ||
//*******************************************************************************************
// 8'h11 || REGISTER 0x11 ( 17) || || ||
//-------------------------------------------------------------------------------------------
// 8'h11 [ 5] || FLASH_POWER_DO_VREFCOMP || 1'h1 || W/R ||
// 8'h11 [ 3] || FLASH_POWER_DO_FLSH || 1'h1 || W/R ||
// 8'h11 [ 2] || FLASH_POWER_IRQ_EN || 1'h1 || W/R ||
// 8'h11 [ 1] || FLASH_POWER_SEL_ON || 1'h1 || W/R || 1: Turn-On, 0: Turn-Off
// 8'h11 [ 0] || FLASH_POWER_GO || 1'h0 || W/R ||
//*******************************************************************************************
// 8'h12 || REGISTER 0x12 ( 18) || || ||
//-------------------------------------------------------------------------------------------
// 8'h12 [ 6] || IRQ_PWR_ON_WUP || 1'h0 || W/R || If 1, FSM will sends an IRQ when it's powering up the flash upon wake-up
// 8'h12 [ 5: 3] || SEL_PWR_ON_WUP || 3'h0 || W/R || 0: disable, 1: vclmt, 2: vclmt/lcap, 3: vclmt/flsh, 4: vclmt/flsh/lcap
// 8'h12 [ 2] || FLASH_AUTO_USE_CUSTOM || 1'h0 || W/R || If 1, Flash Auto-On/Off will use the setting in FLASH_POWER_DO_X
// 8'h12 [ 1] || FLASH_AUTO_OFF || 1'h0 || W/R || If 1, FSM will turn off Flash once finishing a GO operation or ping-pong streaming
// 8'h12 [ 0] || FLASH_AUTO_ON || 1'h0 || W/R || If 1, FSM will turn on Flash before starting a GO operation
//*******************************************************************************************
// 8'h13 || REGISTER 0x13 ( 19) || || ||
//-------------------------------------------------------------------------------------------
// 8'h13 [19: 1] || PP_STR_LIMIT || 19'h00000 || LC || Limit the number of words streamed. 0 means no-limit.
// 8'h13 [ 0] || PP_STR_EN || 1'h0 || LC || Ping-Pong Straming Enable
//*******************************************************************************************
// 8'h14 || REGISTER 0x14 ( 20) || || ||
//-------------------------------------------------------------------------------------------
// 8'h14 [ 4] || PP_NO_ERR_DETECTION || 1'h0 || W/R || If 1, it does not detect buffer_overrun error. Other errors can be stil detected, though.
// 8'h14 [ 3] || PP_USE_FAST_PROG || 1'h0 || W/R || If 1, hold flsh_prog and flsh_nvstr during the whole page program
// 8'h14 [ 2] || PP_WRAP || 1'h0 || W/R || If 1, PP_FLSH_ADDR will wrap around
// 8'h14 [ 1: 0] || PP_BIT_EN_EXT || 2'h1 || W/R ||
//*******************************************************************************************
// 8'h15 || REGISTER 0x15 ( 21) || || ||
//-------------------------------------------------------------------------------------------
// 8'h15 [17: 0] || PP_FLSH_ADDR || 18'h00000 || W/R ||
//*******************************************************************************************
// 8'h16 || REGISTER 0x16 ( 22) || || ||
//-------------------------------------------------------------------------------------------
// 8'h16 [18: 0] || PP_LENGTH_STREAMED || 19'h00000 || LC || Number of words received during Ping-Pong Streaming
//*******************************************************************************************
// 8'h17 || REGISTER 0x17 ( 23) || || ||
//-------------------------------------------------------------------------------------------
// 8'h17 [ 23] || PP_FLAG_END_OF_FLASH || 1'h0 || LC ||
// 8'h17 [ 22] || PP_FLAG_STR_LIMIT || 1'h0 || LC ||
// 8'h17 [ 21] || PP_FLAG_COPY_LIMIT || 1'h0 || LC ||
// 8'h17 [18: 0] || PP_LENGTH_COPIED || 19'h00000 || LC || Number of words copied to Flash during Ping-Pong Streaming
//*******************************************************************************************
// 8'h18 || REGISTER 0x18 ( 24) || || ||
//-------------------------------------------------------------------------------------------
// 8'h18 [ 5: 2] || CLK_RING_SEL || 4'hC || W/R ||
// 8'h18 [ 1: 0] || CLK_DIV_SEL || 2'h1 || W/R ||
//*******************************************************************************************
// 8'h19 || REGISTER 0x19 ( 25) || || ||
//-------------------------------------------------------------------------------------------
// 8'h19 [ 11] || DISABLE_BYPASS_MIRROR || 1'h1 || W/R ||
// 8'h19 [10: 7] || COMP_CTRL_I_1STG || 4'h8 || W/R ||
// 8'h19 [ 6: 3] || COMP_CTRL_I_2STG_BAR || 4'h0 || W/R ||
// 8'h19 [ 2: 0] || COMP_CTRL_VOUT || 3'h3 || W/R ||
//*******************************************************************************************
// 8'h1A || REGISTER 0x1A ( 26) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h1B || REGISTER 0x1B ( 27) || || ||
//-------------------------------------------------------------------------------------------
// 8'h1B [ 7: 0] || IRQ_PAYLOAD || 8'h00 || R ||
//*******************************************************************************************
// 8'h1C || REGISTER 0x1C ( 28) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h1D || REGISTER 0x1D ( 29) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h1E || REGISTER 0x1E ( 30) || || ||
//-------------------------------------------------------------------------------------------
// 8'h1E [23: 0] || FLS2LC_REG_WR_DATA || 24'h000000 || R ||
//*******************************************************************************************
// 8'h1F || REGISTER 0x1F ( 31) || || ||
//-------------------------------------------------------------------------------------------
// 8'h1F [ 0] || FORCE_RESETN || 1'h1 || W/R || If 0, FLPv3L_CTRL will be immediately reset (Asynchronous). Release of RESET does not do anything regardless of SEL_PWR_ON_WUP setting
//*******************************************************************************************
// 8'h20 || REGISTER 0x20 ( 32) || || ||
//-------------------------------------------------------------------------------------------
// 8'h20 [14:10] || FLSH_SET0 || 5'h04 || W/R ||
// 8'h20 [ 9: 5] || FLSH_SET1 || 5'h04 || W/R ||
// 8'h20 [ 4: 0] || FLSH_SNT || 5'h07 || W/R ||
//*******************************************************************************************
// 8'h21 || REGISTER 0x21 ( 33) || || ||
//-------------------------------------------------------------------------------------------
// 8'h21 [14:10] || FLSH_SPT0 || 5'h04 || W/R ||
// 8'h21 [ 9: 5] || FLSH_SPT1 || 5'h04 || W/R ||
// 8'h21 [ 4: 0] || FLSH_SPT2 || 5'h04 || W/R ||
//*******************************************************************************************
// 8'h22 || REGISTER 0x22 ( 34) || || ||
//-------------------------------------------------------------------------------------------
// 8'h22 [ 9: 5] || FLSH_SYT0 || 5'h07 || W/R ||
// 8'h22 [ 4: 0] || FLSH_SYT1 || 5'h07 || W/R ||
//*******************************************************************************************
// 8'h23 || REGISTER 0x23 ( 35) || || ||
//-------------------------------------------------------------------------------------------
// 8'h23 [19:15] || FLSH_SRT0 || 5'h01 || W/R ||
// 8'h23 [14:10] || FLSH_SRT1 || 5'h03 || W/R ||
// 8'h23 [ 9: 5] || FLSH_SRT2 || 5'h03 || W/R ||
// 8'h23 [ 4: 0] || FLSH_SRT3 || 5'h07 || W/R ||
//*******************************************************************************************
// 8'h24 || REGISTER 0x24 ( 36) || || ||
//-------------------------------------------------------------------------------------------
// 8'h24 [14:10] || FLSH_SRT4 || 5'h07 || W/R ||
// 8'h24 [ 9: 5] || FLSH_SRT5 || 5'h07 || W/R ||
// 8'h24 [ 4: 0] || FLSH_SRT6 || 5'h01 || W/R ||
//*******************************************************************************************
// 8'h25 || REGISTER 0x25 ( 37) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h26 || REGISTER 0x26 ( 38) || || ||
//-------------------------------------------------------------------------------------------
// 8'h26 [19:16] || FLSH_SPIG || 4'hD || W/R ||
// 8'h26 [15:12] || FLSH_SRIG || 4'h7 || W/R ||
// 8'h26 [11: 8] || FLSH_SVR0 || 4'h7 || W/R ||
// 8'h26 [ 7: 4] || FLSH_SVR1 || 4'h8 || W/R ||
// 8'h26 [ 3: 0] || FLSH_SVR2 || 4'h8 || W/R ||
//*******************************************************************************************
// 8'h27 || REGISTER 0x27 ( 39) || || ||
//-------------------------------------------------------------------------------------------
// 8'h27 [20:16] || FLSH_SHVE || 5'h01 || W/R ||
// 8'h27 [15:11] || FLSH_SHVP || 5'h03 || W/R ||
// 8'h27 [10: 6] || FLSH_SHVCT || 5'h0F || W/R ||
// 8'h27 [ 5: 0] || FLSH_SMV || 6'h08 || W/R ||
//*******************************************************************************************
// 8'h28 || REGISTER 0x28 ( 40) || || ||
//-------------------------------------------------------------------------------------------
// 8'h28 [ 9: 5] || FLSH_SMVCT0 || 5'h07 || W/R ||
// 8'h28 [ 4: 0] || FLSH_SMVCT1 || 5'h07 || W/R ||
//*******************************************************************************************
// 8'h29 || REGISTER 0x29 ( 41) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h2A || REGISTER 0x2A ( 42) || || ||
//-------------------------------------------------------------------------------------------
// 8'h2A [ 5: 0] || FLSH_SAB || 6'h02 || W/R ||
//*******************************************************************************************
// 8'h2B || REGISTER 0x2B ( 43) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h2C || REGISTER 0x2C ( 44) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h2D || REGISTER 0x2D ( 45) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h2E || REGISTER 0x2E ( 46) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h2F || REGISTER 0x2F ( 47) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h30 || REGISTER 0x30 ( 48) || || ||
//-------------------------------------------------------------------------------------------
// 8'h30 [23:16] || STR_WR_CH1_ALT_ADDR || 8'hF0 || W/R || Alert is suppressed by default
//*******************************************************************************************
// 8'h31 || REGISTER 0x31 ( 49) || || ||
//-------------------------------------------------------------------------------------------
// 8'h31 [23:16] || STR_WR_CH1_ALT_REG_WR || 8'h00 || W/R ||
//*******************************************************************************************
// 8'h32 || REGISTER 0x32 ( 50) || || ||
//-------------------------------------------------------------------------------------------
// 8'h32 [ 23] || STR_WR_CH1_EN || 1'h1 || W/R || Streaming is enabled by default
// 8'h32 [ 22] || STR_WR_CH1_WRP || 1'h1 || W/R || Wrapping is enabled by default
// 8'h32 [ 21] || STR_WR_CH1_DBLB || 1'h0 || W/R || Double Buffer is disabled by default
// 8'h32 [12: 0] || STR_WR_CH1_BUF_LEN || 13'h1FFF || W/R || 32kB = 8192 Words = (0x1FFF + 1)
//*******************************************************************************************
// 8'h33 || REGISTER 0x33 ( 51) || || ||
//-------------------------------------------------------------------------------------------
// 8'h33 [12: 0] || STR_WR_CH1_BUF_OFF || 13'h0000 || W/R ||
//*******************************************************************************************
// 8'h34 || REGISTER 0x34 ( 52) || || ||
//-------------------------------------------------------------------------------------------
// 8'h34 [23:16] || STR_WR_CH0_ALT_ADDR || 8'hF0 || W/R || Alert is suppressed by default
//*******************************************************************************************
// 8'h35 || REGISTER 0x35 ( 53) || || ||
//-------------------------------------------------------------------------------------------
// 8'h35 [23:16] || STR_WR_CH0_ALT_REG_WR || 8'h00 || W/R ||
//*******************************************************************************************
// 8'h36 || REGISTER 0x36 ( 54) || || ||
//-------------------------------------------------------------------------------------------
// 8'h36 [ 23] || STR_WR_CH0_EN || 1'h1 || W/R || Streaming is enabled by default
// 8'h36 [ 22] || STR_WR_CH0_WRP || 1'h1 || W/R || Wrapping is enabled by default
// 8'h36 [ 21] || STR_WR_CH0_DBLB || 1'h0 || W/R || Double Buffer is disabled by default
// 8'h36 [12: 0] || STR_WR_CH0_BUF_LEN || 13'h1FFF || W/R || 32kB = 8192 Words = (0x1FFF + 1)
//*******************************************************************************************
// 8'h37 || REGISTER 0x37 ( 55) || || ||
//-------------------------------------------------------------------------------------------
// 8'h37 [12: 0] || STR_WR_CH0_BUF_OFF || 13'h0000 || W/R ||
//*******************************************************************************************
// 8'h38 || REGISTER 0x38 ( 56) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h39 || REGISTER 0x39 ( 57) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h3A || REGISTER 0x3A ( 58) || || ||
//-------------------------------------------------------------------------------------------
// 8'h3A [ 23] || BLK_WR_EN || 1'h1 || W/R ||
//*******************************************************************************************
// 8'h3B || REGISTER 0x3B ( 59) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h3C || REGISTER 0x3C ( 60) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h3D || REGISTER 0x3D ( 61) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h3E || REGISTER 0x3E ( 62) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h3F || REGISTER 0x3F ( 63) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h40 || REGISTER 0x40 ( 64) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h41 || REGISTER 0x41 ( 65) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h42 || REGISTER 0x42 ( 66) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h43 || REGISTER 0x43 ( 67) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h44 || REGISTER 0x44 ( 68) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h45 || REGISTER 0x45 ( 69) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h46 || REGISTER 0x46 ( 70) || || ||
//-------------------------------------------------------------------------------------------
// !!--- EMPTY REGISTER ---!! || || ||
//*******************************************************************************************
// 8'h47 || REGISTER 0x47 ( 71) || || ||
//-------------------------------------------------------------------------------------------
// 8'h47 [ 23] || ACT_RST || 1'h0 || W/R ||
//*******************************************************************************************
module flpv3l_rf (
//Input
input RESETn,
input ISOLATE,
input [ 71:0] ADDR_IN,
input [ 23:0] DATA_IN,
//Output
//Register 0x00 ( 0)
output [ 4:0] Tcyc_read,
output [ 5:0] T3us,
output [ 5:0] T5us,
output [ 6:0] T10us,
//Register 0x01 ( 1)
output [15:0] Tcyc_prog,
output [ 7:0] Tprog,
//Register 0x02 ( 2)
output [15:0] Terase,
//Register 0x03 ( 3)
output [13:0] Thvcp_en,
output [ 9:0] Tben,
//Register 0x04 ( 4)
output [11:0] Tmvcp_en,
output [11:0] Tsc_en,
//Register 0x05 ( 5)
output [19:0] Tcap,
//Register 0x06 ( 6)
output [16:0] Tvref,
//Register 0x07 ( 7)
//output [12:0] SRAM_START_ADDR, // LAYER-CTRL
//Register 0x08 ( 8)
//output [17:0] FLSH_START_ADDR, // LAYER-CTRL
//Register 0x09 ( 9)
//output [12:0] LENGTH, // LAYER-CTRL
//output IRQ_EN, // LAYER-CTRL
//output [ 3:0] CMD, // LAYER-CTRL
//output GO, // LAYER-CTRL
//Register 0x0A ( 10)
output VREF_SLEEP,
output COMP_SLEEP,
output COMP_CLKENB,
output COMP_CLKEN, // Inverted Signal of COMP_CLKENB
output COMP_ISOL,
//Register 0x0C ( 12)
output WRAP_EXT,
output UPDATE_ADDR_EXT,
output [ 1:0] BIT_EN_EXT,
//Register 0x0D ( 13)
output [19:0] TIMEOUT_EXT,
//Register 0x0E ( 14)
output [12:0] SRAM_START_ADDR_EXT,
//Register 0x0F ( 15)
output [ 7:0] INT_RPLY_SHORT_ADDR,
output [ 7:0] INT_RPLY_REG_ADDR,
//Register 0x10 ( 16)
output BOOT_FLAG_SLEEP,
output BOOT_FLAG_ECC_ERROR,
output BOOT_FLAG_WRONG_HEADER,
output BOOT_FLAG_PWDN,
output BOOT_FLAG_INVALID_CMND,
output BOOT_FLAG_CHKSUM_ERROR,
output BOOT_FLAG_SUCCESS,
output [ 1:0] BOOT_REG_PATTERN,
//Register 0x11 ( 17)
output FLASH_POWER_DO_VREFCOMP,
output FLASH_POWER_DO_FLSH,
output FLASH_POWER_IRQ_EN,
output FLASH_POWER_SEL_ON,
output FLASH_POWER_GO,
//Register 0x12 ( 18)
output IRQ_PWR_ON_WUP,
output [ 2:0] SEL_PWR_ON_WUP,
output FLASH_AUTO_USE_CUSTOM,
output FLASH_AUTO_OFF,
output FLASH_AUTO_ON,
//Register 0x13 ( 19)
//output [18:0] PP_STR_LIMIT, // LAYER-CTRL
//output PP_STR_EN, // LAYER-CTRL
//Register 0x14 ( 20)
output PP_NO_ERR_DETECTION,
output PP_USE_FAST_PROG,
output PP_WRAP,
output [ 1:0] PP_BIT_EN_EXT,
//Register 0x15 ( 21)
output [17:0] PP_FLSH_ADDR,
//Register 0x16 ( 22)
//output [18:0] PP_LENGTH_STREAMED, // LAYER-CTRL
//Register 0x17 ( 23)
//output PP_FLAG_END_OF_FLASH, // LAYER-CTRL
//output PP_FLAG_STR_LIMIT, // LAYER-CTRL
//output PP_FLAG_COPY_LIMIT, // LAYER-CTRL
//output [18:0] PP_LENGTH_COPIED, // LAYER-CTRL
//Register 0x18 ( 24)
output [ 3:0] CLK_RING_SEL,
output [ 1:0] CLK_DIV_SEL,
//Register 0x19 ( 25)
output DISABLE_BYPASS_MIRROR,
output [ 3:0] COMP_CTRL_I_1STG,
output [ 3:0] COMP_CTRL_I_2STG_BAR,
output [ 2:0] COMP_CTRL_VOUT,
//Register 0x1B ( 27)
//output [ 7:0] IRQ_PAYLOAD, // READ-ONLY
//Register 0x1E ( 30)
//output [23:0] FLS2LC_REG_WR_DATA, // READ-ONLY
//Register 0x1F ( 31)
output FORCE_RESETN,
//Register 0x20 ( 32)
output [ 4:0] FLSH_SET0,
output [ 4:0] FLSH_SET1,
output [ 4:0] FLSH_SNT,
//Register 0x21 ( 33)
output [ 4:0] FLSH_SPT0,
output [ 4:0] FLSH_SPT1,
output [ 4:0] FLSH_SPT2,
//Register 0x22 ( 34)
output [ 4:0] FLSH_SYT0,
output [ 4:0] FLSH_SYT1,
//Register 0x23 ( 35)
output [ 4:0] FLSH_SRT0,
output [ 4:0] FLSH_SRT1,
output [ 4:0] FLSH_SRT2,
output [ 4:0] FLSH_SRT3,
//Register 0x24 ( 36)
output [ 4:0] FLSH_SRT4,
output [ 4:0] FLSH_SRT5,
output [ 4:0] FLSH_SRT6,
//Register 0x26 ( 38)
output [ 3:0] FLSH_SPIG,
output [ 3:0] FLSH_SRIG,
output [ 3:0] FLSH_SVR0,
output [ 3:0] FLSH_SVR1,
output [ 3:0] FLSH_SVR2,
//Register 0x27 ( 39)
output [ 4:0] FLSH_SHVE,
output [ 4:0] FLSH_SHVP,
output [ 4:0] FLSH_SHVCT,
output [ 5:0] FLSH_SMV,
//Register 0x28 ( 40)
output [ 4:0] FLSH_SMVCT0,
output [ 4:0] FLSH_SMVCT1,
//Register 0x2A ( 42)
output [ 5:0] FLSH_SAB,
//Register 0x30 ( 48)
output [ 7:0] STR_WR_CH1_ALT_ADDR,
//Register 0x31 ( 49)
output [ 7:0] STR_WR_CH1_ALT_REG_WR,
//Register 0x32 ( 50)
output STR_WR_CH1_EN,
output STR_WR_CH1_WRP,
output STR_WR_CH1_DBLB,
output [12:0] STR_WR_CH1_BUF_LEN,
//Register 0x33 ( 51)
output [12:0] STR_WR_CH1_BUF_OFF,
//Register 0x34 ( 52)
output [ 7:0] STR_WR_CH0_ALT_ADDR,
//Register 0x35 ( 53)
output [ 7:0] STR_WR_CH0_ALT_REG_WR,
//Register 0x36 ( 54)
output STR_WR_CH0_EN,
output STR_WR_CH0_WRP,
output STR_WR_CH0_DBLB,
output [12:0] STR_WR_CH0_BUF_LEN,
//Register 0x37 ( 55)
output [12:0] STR_WR_CH0_BUF_OFF,
//Register 0x3A ( 58)
output BLK_WR_EN,
//Register 0x47 ( 71)
output ACT_RST
);
//Internal Wires
wire isolate_n;
wire [ 71:0] addr_in_iso;
wire [ 71:0] addr_in_iso_buf;
wire [ 23:0] data_in_iso;
wire [ 23:0] data_in_iso_buf;
//****************************************************
// ISOLATE
//****************************************************
INVLLX8HVT_TSMC90 ISOLATE_INV_0 (.A(ISOLATE), .Y(isolate_n));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_071 (.A(isolate_n), .B(ADDR_IN[ 71]), .Y(addr_in_iso[ 71]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_070 (.A(isolate_n), .B(ADDR_IN[ 70]), .Y(addr_in_iso[ 70]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_069 (.A(isolate_n), .B(ADDR_IN[ 69]), .Y(addr_in_iso[ 69]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_068 (.A(isolate_n), .B(ADDR_IN[ 68]), .Y(addr_in_iso[ 68]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_067 (.A(isolate_n), .B(ADDR_IN[ 67]), .Y(addr_in_iso[ 67]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_066 (.A(isolate_n), .B(ADDR_IN[ 66]), .Y(addr_in_iso[ 66]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_065 (.A(isolate_n), .B(ADDR_IN[ 65]), .Y(addr_in_iso[ 65]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_064 (.A(isolate_n), .B(ADDR_IN[ 64]), .Y(addr_in_iso[ 64]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_063 (.A(isolate_n), .B(ADDR_IN[ 63]), .Y(addr_in_iso[ 63]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_062 (.A(isolate_n), .B(ADDR_IN[ 62]), .Y(addr_in_iso[ 62]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_061 (.A(isolate_n), .B(ADDR_IN[ 61]), .Y(addr_in_iso[ 61]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_060 (.A(isolate_n), .B(ADDR_IN[ 60]), .Y(addr_in_iso[ 60]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_059 (.A(isolate_n), .B(ADDR_IN[ 59]), .Y(addr_in_iso[ 59]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_058 (.A(isolate_n), .B(ADDR_IN[ 58]), .Y(addr_in_iso[ 58]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_057 (.A(isolate_n), .B(ADDR_IN[ 57]), .Y(addr_in_iso[ 57]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_056 (.A(isolate_n), .B(ADDR_IN[ 56]), .Y(addr_in_iso[ 56]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_055 (.A(isolate_n), .B(ADDR_IN[ 55]), .Y(addr_in_iso[ 55]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_054 (.A(isolate_n), .B(ADDR_IN[ 54]), .Y(addr_in_iso[ 54]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_053 (.A(isolate_n), .B(ADDR_IN[ 53]), .Y(addr_in_iso[ 53]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_052 (.A(isolate_n), .B(ADDR_IN[ 52]), .Y(addr_in_iso[ 52]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_051 (.A(isolate_n), .B(ADDR_IN[ 51]), .Y(addr_in_iso[ 51]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_050 (.A(isolate_n), .B(ADDR_IN[ 50]), .Y(addr_in_iso[ 50]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_049 (.A(isolate_n), .B(ADDR_IN[ 49]), .Y(addr_in_iso[ 49]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_048 (.A(isolate_n), .B(ADDR_IN[ 48]), .Y(addr_in_iso[ 48]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_047 (.A(isolate_n), .B(ADDR_IN[ 47]), .Y(addr_in_iso[ 47]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_046 (.A(isolate_n), .B(ADDR_IN[ 46]), .Y(addr_in_iso[ 46]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_045 (.A(isolate_n), .B(ADDR_IN[ 45]), .Y(addr_in_iso[ 45]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_044 (.A(isolate_n), .B(ADDR_IN[ 44]), .Y(addr_in_iso[ 44]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_043 (.A(isolate_n), .B(ADDR_IN[ 43]), .Y(addr_in_iso[ 43]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_042 (.A(isolate_n), .B(ADDR_IN[ 42]), .Y(addr_in_iso[ 42]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_041 (.A(isolate_n), .B(ADDR_IN[ 41]), .Y(addr_in_iso[ 41]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_040 (.A(isolate_n), .B(ADDR_IN[ 40]), .Y(addr_in_iso[ 40]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_039 (.A(isolate_n), .B(ADDR_IN[ 39]), .Y(addr_in_iso[ 39]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_038 (.A(isolate_n), .B(ADDR_IN[ 38]), .Y(addr_in_iso[ 38]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_037 (.A(isolate_n), .B(ADDR_IN[ 37]), .Y(addr_in_iso[ 37]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_036 (.A(isolate_n), .B(ADDR_IN[ 36]), .Y(addr_in_iso[ 36]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_035 (.A(isolate_n), .B(ADDR_IN[ 35]), .Y(addr_in_iso[ 35]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_034 (.A(isolate_n), .B(ADDR_IN[ 34]), .Y(addr_in_iso[ 34]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_033 (.A(isolate_n), .B(ADDR_IN[ 33]), .Y(addr_in_iso[ 33]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_032 (.A(isolate_n), .B(ADDR_IN[ 32]), .Y(addr_in_iso[ 32]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_031 (.A(isolate_n), .B(ADDR_IN[ 31]), .Y(addr_in_iso[ 31]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_030 (.A(isolate_n), .B(ADDR_IN[ 30]), .Y(addr_in_iso[ 30]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_029 (.A(isolate_n), .B(ADDR_IN[ 29]), .Y(addr_in_iso[ 29]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_028 (.A(isolate_n), .B(ADDR_IN[ 28]), .Y(addr_in_iso[ 28]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_027 (.A(isolate_n), .B(ADDR_IN[ 27]), .Y(addr_in_iso[ 27]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_026 (.A(isolate_n), .B(ADDR_IN[ 26]), .Y(addr_in_iso[ 26]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_025 (.A(isolate_n), .B(ADDR_IN[ 25]), .Y(addr_in_iso[ 25]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_024 (.A(isolate_n), .B(ADDR_IN[ 24]), .Y(addr_in_iso[ 24]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_023 (.A(isolate_n), .B(ADDR_IN[ 23]), .Y(addr_in_iso[ 23]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_022 (.A(isolate_n), .B(ADDR_IN[ 22]), .Y(addr_in_iso[ 22]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_021 (.A(isolate_n), .B(ADDR_IN[ 21]), .Y(addr_in_iso[ 21]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_020 (.A(isolate_n), .B(ADDR_IN[ 20]), .Y(addr_in_iso[ 20]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_019 (.A(isolate_n), .B(ADDR_IN[ 19]), .Y(addr_in_iso[ 19]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_018 (.A(isolate_n), .B(ADDR_IN[ 18]), .Y(addr_in_iso[ 18]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_017 (.A(isolate_n), .B(ADDR_IN[ 17]), .Y(addr_in_iso[ 17]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_016 (.A(isolate_n), .B(ADDR_IN[ 16]), .Y(addr_in_iso[ 16]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_015 (.A(isolate_n), .B(ADDR_IN[ 15]), .Y(addr_in_iso[ 15]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_014 (.A(isolate_n), .B(ADDR_IN[ 14]), .Y(addr_in_iso[ 14]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_013 (.A(isolate_n), .B(ADDR_IN[ 13]), .Y(addr_in_iso[ 13]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_012 (.A(isolate_n), .B(ADDR_IN[ 12]), .Y(addr_in_iso[ 12]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_011 (.A(isolate_n), .B(ADDR_IN[ 11]), .Y(addr_in_iso[ 11]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_010 (.A(isolate_n), .B(ADDR_IN[ 10]), .Y(addr_in_iso[ 10]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_009 (.A(isolate_n), .B(ADDR_IN[ 9]), .Y(addr_in_iso[ 9]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_008 (.A(isolate_n), .B(ADDR_IN[ 8]), .Y(addr_in_iso[ 8]));
//AND2LLX1HVT_TSMC90 ADDR_IN_AND_007 (.A(isolate_n), .B(ADDR_IN[ 7]), .Y(addr_in_iso[ 7]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_006 (.A(isolate_n), .B(ADDR_IN[ 6]), .Y(addr_in_iso[ 6]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_005 (.A(isolate_n), .B(ADDR_IN[ 5]), .Y(addr_in_iso[ 5]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_004 (.A(isolate_n), .B(ADDR_IN[ 4]), .Y(addr_in_iso[ 4]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_003 (.A(isolate_n), .B(ADDR_IN[ 3]), .Y(addr_in_iso[ 3]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_002 (.A(isolate_n), .B(ADDR_IN[ 2]), .Y(addr_in_iso[ 2]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_001 (.A(isolate_n), .B(ADDR_IN[ 1]), .Y(addr_in_iso[ 1]));
AND2LLX1HVT_TSMC90 ADDR_IN_AND_000 (.A(isolate_n), .B(ADDR_IN[ 0]), .Y(addr_in_iso[ 0]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_23 (.A(isolate_n), .B(DATA_IN[23]), .Y(data_in_iso[23]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_22 (.A(isolate_n), .B(DATA_IN[22]), .Y(data_in_iso[22]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_21 (.A(isolate_n), .B(DATA_IN[21]), .Y(data_in_iso[21]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_20 (.A(isolate_n), .B(DATA_IN[20]), .Y(data_in_iso[20]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_19 (.A(isolate_n), .B(DATA_IN[19]), .Y(data_in_iso[19]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_18 (.A(isolate_n), .B(DATA_IN[18]), .Y(data_in_iso[18]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_17 (.A(isolate_n), .B(DATA_IN[17]), .Y(data_in_iso[17]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_16 (.A(isolate_n), .B(DATA_IN[16]), .Y(data_in_iso[16]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_15 (.A(isolate_n), .B(DATA_IN[15]), .Y(data_in_iso[15]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_14 (.A(isolate_n), .B(DATA_IN[14]), .Y(data_in_iso[14]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_13 (.A(isolate_n), .B(DATA_IN[13]), .Y(data_in_iso[13]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_12 (.A(isolate_n), .B(DATA_IN[12]), .Y(data_in_iso[12]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_11 (.A(isolate_n), .B(DATA_IN[11]), .Y(data_in_iso[11]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_10 (.A(isolate_n), .B(DATA_IN[10]), .Y(data_in_iso[10]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_09 (.A(isolate_n), .B(DATA_IN[ 9]), .Y(data_in_iso[ 9]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_08 (.A(isolate_n), .B(DATA_IN[ 8]), .Y(data_in_iso[ 8]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_07 (.A(isolate_n), .B(DATA_IN[ 7]), .Y(data_in_iso[ 7]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_06 (.A(isolate_n), .B(DATA_IN[ 6]), .Y(data_in_iso[ 6]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_05 (.A(isolate_n), .B(DATA_IN[ 5]), .Y(data_in_iso[ 5]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_04 (.A(isolate_n), .B(DATA_IN[ 4]), .Y(data_in_iso[ 4]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_03 (.A(isolate_n), .B(DATA_IN[ 3]), .Y(data_in_iso[ 3]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_02 (.A(isolate_n), .B(DATA_IN[ 2]), .Y(data_in_iso[ 2]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_01 (.A(isolate_n), .B(DATA_IN[ 1]), .Y(data_in_iso[ 1]));
AND2LLX1HVT_TSMC90 DATA_IN_AND_00 (.A(isolate_n), .B(DATA_IN[ 0]), .Y(data_in_iso[ 0]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_071 (.A(addr_in_iso[ 71]), .Y(addr_in_iso_buf[ 71]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_070 (.A(addr_in_iso[ 70]), .Y(addr_in_iso_buf[ 70]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_069 (.A(addr_in_iso[ 69]), .Y(addr_in_iso_buf[ 69]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_068 (.A(addr_in_iso[ 68]), .Y(addr_in_iso_buf[ 68]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_067 (.A(addr_in_iso[ 67]), .Y(addr_in_iso_buf[ 67]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_066 (.A(addr_in_iso[ 66]), .Y(addr_in_iso_buf[ 66]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_065 (.A(addr_in_iso[ 65]), .Y(addr_in_iso_buf[ 65]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_064 (.A(addr_in_iso[ 64]), .Y(addr_in_iso_buf[ 64]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_063 (.A(addr_in_iso[ 63]), .Y(addr_in_iso_buf[ 63]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_062 (.A(addr_in_iso[ 62]), .Y(addr_in_iso_buf[ 62]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_061 (.A(addr_in_iso[ 61]), .Y(addr_in_iso_buf[ 61]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_060 (.A(addr_in_iso[ 60]), .Y(addr_in_iso_buf[ 60]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_059 (.A(addr_in_iso[ 59]), .Y(addr_in_iso_buf[ 59]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_058 (.A(addr_in_iso[ 58]), .Y(addr_in_iso_buf[ 58]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_057 (.A(addr_in_iso[ 57]), .Y(addr_in_iso_buf[ 57]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_056 (.A(addr_in_iso[ 56]), .Y(addr_in_iso_buf[ 56]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_055 (.A(addr_in_iso[ 55]), .Y(addr_in_iso_buf[ 55]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_054 (.A(addr_in_iso[ 54]), .Y(addr_in_iso_buf[ 54]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_053 (.A(addr_in_iso[ 53]), .Y(addr_in_iso_buf[ 53]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_052 (.A(addr_in_iso[ 52]), .Y(addr_in_iso_buf[ 52]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_051 (.A(addr_in_iso[ 51]), .Y(addr_in_iso_buf[ 51]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_050 (.A(addr_in_iso[ 50]), .Y(addr_in_iso_buf[ 50]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_049 (.A(addr_in_iso[ 49]), .Y(addr_in_iso_buf[ 49]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_048 (.A(addr_in_iso[ 48]), .Y(addr_in_iso_buf[ 48]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_047 (.A(addr_in_iso[ 47]), .Y(addr_in_iso_buf[ 47]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_046 (.A(addr_in_iso[ 46]), .Y(addr_in_iso_buf[ 46]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_045 (.A(addr_in_iso[ 45]), .Y(addr_in_iso_buf[ 45]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_044 (.A(addr_in_iso[ 44]), .Y(addr_in_iso_buf[ 44]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_043 (.A(addr_in_iso[ 43]), .Y(addr_in_iso_buf[ 43]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_042 (.A(addr_in_iso[ 42]), .Y(addr_in_iso_buf[ 42]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_041 (.A(addr_in_iso[ 41]), .Y(addr_in_iso_buf[ 41]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_040 (.A(addr_in_iso[ 40]), .Y(addr_in_iso_buf[ 40]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_039 (.A(addr_in_iso[ 39]), .Y(addr_in_iso_buf[ 39]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_038 (.A(addr_in_iso[ 38]), .Y(addr_in_iso_buf[ 38]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_037 (.A(addr_in_iso[ 37]), .Y(addr_in_iso_buf[ 37]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_036 (.A(addr_in_iso[ 36]), .Y(addr_in_iso_buf[ 36]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_035 (.A(addr_in_iso[ 35]), .Y(addr_in_iso_buf[ 35]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_034 (.A(addr_in_iso[ 34]), .Y(addr_in_iso_buf[ 34]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_033 (.A(addr_in_iso[ 33]), .Y(addr_in_iso_buf[ 33]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_032 (.A(addr_in_iso[ 32]), .Y(addr_in_iso_buf[ 32]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_031 (.A(addr_in_iso[ 31]), .Y(addr_in_iso_buf[ 31]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_030 (.A(addr_in_iso[ 30]), .Y(addr_in_iso_buf[ 30]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_029 (.A(addr_in_iso[ 29]), .Y(addr_in_iso_buf[ 29]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_028 (.A(addr_in_iso[ 28]), .Y(addr_in_iso_buf[ 28]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_027 (.A(addr_in_iso[ 27]), .Y(addr_in_iso_buf[ 27]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_026 (.A(addr_in_iso[ 26]), .Y(addr_in_iso_buf[ 26]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_025 (.A(addr_in_iso[ 25]), .Y(addr_in_iso_buf[ 25]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_024 (.A(addr_in_iso[ 24]), .Y(addr_in_iso_buf[ 24]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_023 (.A(addr_in_iso[ 23]), .Y(addr_in_iso_buf[ 23]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_022 (.A(addr_in_iso[ 22]), .Y(addr_in_iso_buf[ 22]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_021 (.A(addr_in_iso[ 21]), .Y(addr_in_iso_buf[ 21]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_020 (.A(addr_in_iso[ 20]), .Y(addr_in_iso_buf[ 20]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_019 (.A(addr_in_iso[ 19]), .Y(addr_in_iso_buf[ 19]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_018 (.A(addr_in_iso[ 18]), .Y(addr_in_iso_buf[ 18]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_017 (.A(addr_in_iso[ 17]), .Y(addr_in_iso_buf[ 17]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_016 (.A(addr_in_iso[ 16]), .Y(addr_in_iso_buf[ 16]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_015 (.A(addr_in_iso[ 15]), .Y(addr_in_iso_buf[ 15]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_014 (.A(addr_in_iso[ 14]), .Y(addr_in_iso_buf[ 14]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_013 (.A(addr_in_iso[ 13]), .Y(addr_in_iso_buf[ 13]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_012 (.A(addr_in_iso[ 12]), .Y(addr_in_iso_buf[ 12]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_011 (.A(addr_in_iso[ 11]), .Y(addr_in_iso_buf[ 11]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_010 (.A(addr_in_iso[ 10]), .Y(addr_in_iso_buf[ 10]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_009 (.A(addr_in_iso[ 9]), .Y(addr_in_iso_buf[ 9]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_008 (.A(addr_in_iso[ 8]), .Y(addr_in_iso_buf[ 8]));
//BUFLLX4HVT_TSMC90 BUF_ADDR_IN_007 (.A(addr_in_iso[ 7]), .Y(addr_in_iso_buf[ 7]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_006 (.A(addr_in_iso[ 6]), .Y(addr_in_iso_buf[ 6]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_005 (.A(addr_in_iso[ 5]), .Y(addr_in_iso_buf[ 5]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_004 (.A(addr_in_iso[ 4]), .Y(addr_in_iso_buf[ 4]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_003 (.A(addr_in_iso[ 3]), .Y(addr_in_iso_buf[ 3]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_002 (.A(addr_in_iso[ 2]), .Y(addr_in_iso_buf[ 2]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_001 (.A(addr_in_iso[ 1]), .Y(addr_in_iso_buf[ 1]));
BUFLLX4HVT_TSMC90 BUF_ADDR_IN_000 (.A(addr_in_iso[ 0]), .Y(addr_in_iso_buf[ 0]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_23 (.A(data_in_iso[23]), .Y(data_in_iso_buf[23]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_22 (.A(data_in_iso[22]), .Y(data_in_iso_buf[22]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_21 (.A(data_in_iso[21]), .Y(data_in_iso_buf[21]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_20 (.A(data_in_iso[20]), .Y(data_in_iso_buf[20]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_19 (.A(data_in_iso[19]), .Y(data_in_iso_buf[19]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_18 (.A(data_in_iso[18]), .Y(data_in_iso_buf[18]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_17 (.A(data_in_iso[17]), .Y(data_in_iso_buf[17]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_16 (.A(data_in_iso[16]), .Y(data_in_iso_buf[16]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_15 (.A(data_in_iso[15]), .Y(data_in_iso_buf[15]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_14 (.A(data_in_iso[14]), .Y(data_in_iso_buf[14]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_13 (.A(data_in_iso[13]), .Y(data_in_iso_buf[13]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_12 (.A(data_in_iso[12]), .Y(data_in_iso_buf[12]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_11 (.A(data_in_iso[11]), .Y(data_in_iso_buf[11]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_10 (.A(data_in_iso[10]), .Y(data_in_iso_buf[10]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_09 (.A(data_in_iso[ 9]), .Y(data_in_iso_buf[ 9]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_08 (.A(data_in_iso[ 8]), .Y(data_in_iso_buf[ 8]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_07 (.A(data_in_iso[ 7]), .Y(data_in_iso_buf[ 7]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_06 (.A(data_in_iso[ 6]), .Y(data_in_iso_buf[ 6]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_05 (.A(data_in_iso[ 5]), .Y(data_in_iso_buf[ 5]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_04 (.A(data_in_iso[ 4]), .Y(data_in_iso_buf[ 4]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_03 (.A(data_in_iso[ 3]), .Y(data_in_iso_buf[ 3]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_02 (.A(data_in_iso[ 2]), .Y(data_in_iso_buf[ 2]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_01 (.A(data_in_iso[ 1]), .Y(data_in_iso_buf[ 1]));
BUFLLX4HVT_TSMC90 BUF_DATA_IN_00 (.A(data_in_iso[ 0]), .Y(data_in_iso_buf[ 0]));
//****************************************************
// REGISTER 0x00 ( 0)
//****************************************************
//Tcyc_read (5'h1F)
DFFSNLLX1HVT_TSMC90 Tcyc_read_4 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[23]), .SN(RESETn), .Q(Tcyc_read[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_read_3 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[22]), .SN(RESETn), .Q(Tcyc_read[3]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_read_2 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[21]), .SN(RESETn), .Q(Tcyc_read[2]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_read_1 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[20]), .SN(RESETn), .Q(Tcyc_read[1]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_read_0 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[19]), .SN(RESETn), .Q(Tcyc_read[0]), .QN());
//T3us (6'h02)
DFFRNLLX1HVT_TSMC90 T3us_5 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(T3us[5]), .QN());
DFFRNLLX1HVT_TSMC90 T3us_4 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(T3us[4]), .QN());
DFFRNLLX1HVT_TSMC90 T3us_3 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(T3us[3]), .QN());
DFFRNLLX1HVT_TSMC90 T3us_2 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(T3us[2]), .QN());
DFFSNLLX1HVT_TSMC90 T3us_1 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[14]), .SN(RESETn), .Q(T3us[1]), .QN());
DFFRNLLX1HVT_TSMC90 T3us_0 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(T3us[0]), .QN());
//T5us (6'h04)
DFFRNLLX1HVT_TSMC90 T5us_5 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(T5us[5]), .QN());
DFFRNLLX1HVT_TSMC90 T5us_4 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(T5us[4]), .QN());
DFFRNLLX1HVT_TSMC90 T5us_3 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(T5us[3]), .QN());
DFFSNLLX1HVT_TSMC90 T5us_2 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(T5us[2]), .QN());
DFFRNLLX1HVT_TSMC90 T5us_1 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(T5us[1]), .QN());
DFFRNLLX1HVT_TSMC90 T5us_0 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(T5us[0]), .QN());
//T10us (7'h09)
DFFRNLLX1HVT_TSMC90 T10us_6 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(T10us[6]), .QN());
DFFRNLLX1HVT_TSMC90 T10us_5 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(T10us[5]), .QN());
DFFRNLLX1HVT_TSMC90 T10us_4 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(T10us[4]), .QN());
DFFSNLLX1HVT_TSMC90 T10us_3 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(T10us[3]), .QN());
DFFRNLLX1HVT_TSMC90 T10us_2 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(T10us[2]), .QN());
DFFRNLLX1HVT_TSMC90 T10us_1 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(T10us[1]), .QN());
DFFSNLLX1HVT_TSMC90 T10us_0 (.CLK(addr_in_iso_buf[0]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(T10us[0]), .QN());
//****************************************************
// REGISTER 0x01 ( 1)
//****************************************************
//Tcyc_prog (16'h007F)
DFFRNLLX1HVT_TSMC90 Tcyc_prog_15 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(Tcyc_prog[15]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_14 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(Tcyc_prog[14]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_13 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(Tcyc_prog[13]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_12 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(Tcyc_prog[12]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_11 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(Tcyc_prog[11]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_10 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(Tcyc_prog[10]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_9 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(Tcyc_prog[9]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_8 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(Tcyc_prog[8]), .QN());
DFFRNLLX1HVT_TSMC90 Tcyc_prog_7 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(Tcyc_prog[7]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_6 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[14]), .SN(RESETn), .Q(Tcyc_prog[6]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_5 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[13]), .SN(RESETn), .Q(Tcyc_prog[5]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_4 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(Tcyc_prog[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_3 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(Tcyc_prog[3]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_2 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(Tcyc_prog[2]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_1 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(Tcyc_prog[1]), .QN());
DFFSNLLX1HVT_TSMC90 Tcyc_prog_0 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(Tcyc_prog[0]), .QN());
//Tprog (8'h09)
DFFRNLLX1HVT_TSMC90 Tprog_7 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(Tprog[7]), .QN());
DFFRNLLX1HVT_TSMC90 Tprog_6 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(Tprog[6]), .QN());
DFFRNLLX1HVT_TSMC90 Tprog_5 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(Tprog[5]), .QN());
DFFRNLLX1HVT_TSMC90 Tprog_4 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(Tprog[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tprog_3 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(Tprog[3]), .QN());
DFFRNLLX1HVT_TSMC90 Tprog_2 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(Tprog[2]), .QN());
DFFRNLLX1HVT_TSMC90 Tprog_1 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(Tprog[1]), .QN());
DFFSNLLX1HVT_TSMC90 Tprog_0 (.CLK(addr_in_iso_buf[1]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(Tprog[0]), .QN());
//****************************************************
// REGISTER 0x02 ( 2)
//****************************************************
//Terase (16'h0100)
DFFRNLLX1HVT_TSMC90 Terase_15 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(Terase[15]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_14 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(Terase[14]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_13 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(Terase[13]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_12 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(Terase[12]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_11 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(Terase[11]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_10 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(Terase[10]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_9 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(Terase[9]), .QN());
DFFSNLLX1HVT_TSMC90 Terase_8 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(Terase[8]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_7 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(Terase[7]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_6 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(Terase[6]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_5 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(Terase[5]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_4 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(Terase[4]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_3 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(Terase[3]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_2 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(Terase[2]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_1 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(Terase[1]), .QN());
DFFRNLLX1HVT_TSMC90 Terase_0 (.CLK(addr_in_iso_buf[2]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(Terase[0]), .QN());
//****************************************************
// REGISTER 0x03 ( 3)
//****************************************************
//Thvcp_en (14'h03E8)
DFFRNLLX1HVT_TSMC90 Thvcp_en_13 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(Thvcp_en[13]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_12 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(Thvcp_en[12]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_11 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(Thvcp_en[11]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_10 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(Thvcp_en[10]), .QN());
DFFSNLLX1HVT_TSMC90 Thvcp_en_9 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[19]), .SN(RESETn), .Q(Thvcp_en[9]), .QN());
DFFSNLLX1HVT_TSMC90 Thvcp_en_8 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[18]), .SN(RESETn), .Q(Thvcp_en[8]), .QN());
DFFSNLLX1HVT_TSMC90 Thvcp_en_7 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[17]), .SN(RESETn), .Q(Thvcp_en[7]), .QN());
DFFSNLLX1HVT_TSMC90 Thvcp_en_6 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[16]), .SN(RESETn), .Q(Thvcp_en[6]), .QN());
DFFSNLLX1HVT_TSMC90 Thvcp_en_5 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[15]), .SN(RESETn), .Q(Thvcp_en[5]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_4 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(Thvcp_en[4]), .QN());
DFFSNLLX1HVT_TSMC90 Thvcp_en_3 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[13]), .SN(RESETn), .Q(Thvcp_en[3]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_2 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(Thvcp_en[2]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_1 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(Thvcp_en[1]), .QN());
DFFRNLLX1HVT_TSMC90 Thvcp_en_0 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(Thvcp_en[0]), .QN());
//Tben (10'h031)
DFFRNLLX1HVT_TSMC90 Tben_9 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(Tben[9]), .QN());
DFFRNLLX1HVT_TSMC90 Tben_8 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(Tben[8]), .QN());
DFFRNLLX1HVT_TSMC90 Tben_7 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(Tben[7]), .QN());
DFFRNLLX1HVT_TSMC90 Tben_6 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(Tben[6]), .QN());
DFFSNLLX1HVT_TSMC90 Tben_5 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(Tben[5]), .QN());
DFFSNLLX1HVT_TSMC90 Tben_4 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(Tben[4]), .QN());
DFFRNLLX1HVT_TSMC90 Tben_3 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(Tben[3]), .QN());
DFFRNLLX1HVT_TSMC90 Tben_2 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(Tben[2]), .QN());
DFFRNLLX1HVT_TSMC90 Tben_1 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(Tben[1]), .QN());
DFFSNLLX1HVT_TSMC90 Tben_0 (.CLK(addr_in_iso_buf[3]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(Tben[0]), .QN());
//****************************************************
// REGISTER 0x04 ( 4)
//****************************************************
//Tmvcp_en (12'h3E8)
DFFRNLLX1HVT_TSMC90 Tmvcp_en_11 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(Tmvcp_en[11]), .QN());
DFFRNLLX1HVT_TSMC90 Tmvcp_en_10 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(Tmvcp_en[10]), .QN());
DFFSNLLX1HVT_TSMC90 Tmvcp_en_9 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[21]), .SN(RESETn), .Q(Tmvcp_en[9]), .QN());
DFFSNLLX1HVT_TSMC90 Tmvcp_en_8 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[20]), .SN(RESETn), .Q(Tmvcp_en[8]), .QN());
DFFSNLLX1HVT_TSMC90 Tmvcp_en_7 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[19]), .SN(RESETn), .Q(Tmvcp_en[7]), .QN());
DFFSNLLX1HVT_TSMC90 Tmvcp_en_6 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[18]), .SN(RESETn), .Q(Tmvcp_en[6]), .QN());
DFFSNLLX1HVT_TSMC90 Tmvcp_en_5 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[17]), .SN(RESETn), .Q(Tmvcp_en[5]), .QN());
DFFRNLLX1HVT_TSMC90 Tmvcp_en_4 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(Tmvcp_en[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tmvcp_en_3 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[15]), .SN(RESETn), .Q(Tmvcp_en[3]), .QN());
DFFRNLLX1HVT_TSMC90 Tmvcp_en_2 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(Tmvcp_en[2]), .QN());
DFFRNLLX1HVT_TSMC90 Tmvcp_en_1 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(Tmvcp_en[1]), .QN());
DFFRNLLX1HVT_TSMC90 Tmvcp_en_0 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(Tmvcp_en[0]), .QN());
//Tsc_en (12'h3E8)
DFFRNLLX1HVT_TSMC90 Tsc_en_11 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(Tsc_en[11]), .QN());
DFFRNLLX1HVT_TSMC90 Tsc_en_10 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(Tsc_en[10]), .QN());
DFFSNLLX1HVT_TSMC90 Tsc_en_9 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(Tsc_en[9]), .QN());
DFFSNLLX1HVT_TSMC90 Tsc_en_8 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(Tsc_en[8]), .QN());
DFFSNLLX1HVT_TSMC90 Tsc_en_7 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(Tsc_en[7]), .QN());
DFFSNLLX1HVT_TSMC90 Tsc_en_6 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(Tsc_en[6]), .QN());
DFFSNLLX1HVT_TSMC90 Tsc_en_5 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(Tsc_en[5]), .QN());
DFFRNLLX1HVT_TSMC90 Tsc_en_4 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(Tsc_en[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tsc_en_3 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(Tsc_en[3]), .QN());
DFFRNLLX1HVT_TSMC90 Tsc_en_2 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(Tsc_en[2]), .QN());
DFFRNLLX1HVT_TSMC90 Tsc_en_1 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(Tsc_en[1]), .QN());
DFFRNLLX1HVT_TSMC90 Tsc_en_0 (.CLK(addr_in_iso_buf[4]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(Tsc_en[0]), .QN());
//****************************************************
// REGISTER 0x05 ( 5)
//****************************************************
//Tcap (20'h007CF)
DFFRNLLX1HVT_TSMC90 Tcap_19 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(Tcap[19]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_18 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(Tcap[18]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_17 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(Tcap[17]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_16 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(Tcap[16]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_15 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(Tcap[15]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_14 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(Tcap[14]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_13 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(Tcap[13]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_12 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(Tcap[12]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_11 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(Tcap[11]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_10 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(Tcap[10]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_9 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(Tcap[9]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_8 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(Tcap[8]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_7 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(Tcap[7]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_6 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(Tcap[6]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_5 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(Tcap[5]), .QN());
DFFRNLLX1HVT_TSMC90 Tcap_4 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(Tcap[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_3 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(Tcap[3]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_2 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(Tcap[2]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_1 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(Tcap[1]), .QN());
DFFSNLLX1HVT_TSMC90 Tcap_0 (.CLK(addr_in_iso_buf[5]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(Tcap[0]), .QN());
//****************************************************
// REGISTER 0x06 ( 6)
//****************************************************
//Tvref (17'h01F3F)
DFFRNLLX1HVT_TSMC90 Tvref_16 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(Tvref[16]), .QN());
DFFRNLLX1HVT_TSMC90 Tvref_15 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(Tvref[15]), .QN());
DFFRNLLX1HVT_TSMC90 Tvref_14 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(Tvref[14]), .QN());
DFFRNLLX1HVT_TSMC90 Tvref_13 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(Tvref[13]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_12 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(Tvref[12]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_11 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(Tvref[11]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_10 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(Tvref[10]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_9 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(Tvref[9]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_8 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(Tvref[8]), .QN());
DFFRNLLX1HVT_TSMC90 Tvref_7 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(Tvref[7]), .QN());
DFFRNLLX1HVT_TSMC90 Tvref_6 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(Tvref[6]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_5 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(Tvref[5]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_4 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(Tvref[4]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_3 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(Tvref[3]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_2 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(Tvref[2]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_1 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(Tvref[1]), .QN());
DFFSNLLX1HVT_TSMC90 Tvref_0 (.CLK(addr_in_iso_buf[6]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(Tvref[0]), .QN());
//****************************************************
// REGISTER 0x07 ( 7)
//****************************************************
//SRAM_START_ADDR (13'h0000)
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_12 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(SRAM_START_ADDR[12]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_11 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(SRAM_START_ADDR[11]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_10 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(SRAM_START_ADDR[10]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_9 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(SRAM_START_ADDR[9]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_8 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(SRAM_START_ADDR[8]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_7 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(SRAM_START_ADDR[7]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_6 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(SRAM_START_ADDR[6]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_5 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(SRAM_START_ADDR[5]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_4 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(SRAM_START_ADDR[4]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_3 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(SRAM_START_ADDR[3]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_2 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(SRAM_START_ADDR[2]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_1 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(SRAM_START_ADDR[1]), .QN());
//DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_0 (.CLK(addr_in_iso_buf[7]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(SRAM_START_ADDR[0]), .QN());
//****************************************************
// REGISTER 0x08 ( 8)
//****************************************************
//FLSH_START_ADDR (18'h00000)
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_17 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(FLSH_START_ADDR[17]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_16 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(FLSH_START_ADDR[16]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_15 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(FLSH_START_ADDR[15]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_14 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLSH_START_ADDR[14]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_13 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLSH_START_ADDR[13]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_12 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(FLSH_START_ADDR[12]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_11 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(FLSH_START_ADDR[11]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_10 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(FLSH_START_ADDR[10]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_9 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_START_ADDR[9]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_8 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_START_ADDR[8]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_7 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(FLSH_START_ADDR[7]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_6 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(FLSH_START_ADDR[6]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_5 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLSH_START_ADDR[5]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_4 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_START_ADDR[4]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_3 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_START_ADDR[3]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_2 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLSH_START_ADDR[2]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_1 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLSH_START_ADDR[1]), .QN());
//DFFRNLLX1HVT_TSMC90 FLSH_START_ADDR_0 (.CLK(addr_in_iso_buf[8]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLSH_START_ADDR[0]), .QN());
//****************************************************
// REGISTER 0x09 ( 9)
//****************************************************
//LENGTH (13'h0000)
//DFFRNLLX1HVT_TSMC90 LENGTH_12 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(LENGTH[12]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_11 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(LENGTH[11]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_10 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(LENGTH[10]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_9 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(LENGTH[9]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_8 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(LENGTH[8]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_7 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(LENGTH[7]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_6 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(LENGTH[6]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_5 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(LENGTH[5]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_4 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(LENGTH[4]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_3 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(LENGTH[3]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_2 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(LENGTH[2]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_1 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(LENGTH[1]), .QN());
//DFFRNLLX1HVT_TSMC90 LENGTH_0 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(LENGTH[0]), .QN());
//IRQ_EN (1'h0)
//DFFRNLLX1HVT_TSMC90 IRQ_EN_0 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(IRQ_EN), .QN());
//CMD (4'h0)
//DFFRNLLX1HVT_TSMC90 CMD_3 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(CMD[3]), .QN());
//DFFRNLLX1HVT_TSMC90 CMD_2 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(CMD[2]), .QN());
//DFFRNLLX1HVT_TSMC90 CMD_1 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(CMD[1]), .QN());
//DFFRNLLX1HVT_TSMC90 CMD_0 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(CMD[0]), .QN());
//GO (1'h0)
//DFFRNLLX1HVT_TSMC90 GO_0 (.CLK(addr_in_iso_buf[9]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(GO), .QN());
//****************************************************
// REGISTER 0x0A ( 10)
//****************************************************
//VREF_SLEEP (1'h1)
DFFSNLLX1HVT_TSMC90 VREF_SLEEP_0 (.CLK(addr_in_iso_buf[10]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(VREF_SLEEP), .QN());
//COMP_SLEEP (1'h1)
DFFSNLLX1HVT_TSMC90 COMP_SLEEP_0 (.CLK(addr_in_iso_buf[10]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(COMP_SLEEP), .QN());
//COMP_CLKENB (1'h1)
DFFSNLLX1HVT_TSMC90 COMP_CLKENB_0 (.CLK(addr_in_iso_buf[10]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(COMP_CLKENB), .QN(COMP_CLKEN));
//COMP_ISOL (1'h1)
DFFSNLLX1HVT_TSMC90 COMP_ISOL_0 (.CLK(addr_in_iso_buf[10]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(COMP_ISOL), .QN());
//****************************************************
// REGISTER 0x0B ( 11) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x0C ( 12)
//****************************************************
//WRAP_EXT (1'h0)
DFFRNLLX1HVT_TSMC90 WRAP_EXT_0 (.CLK(addr_in_iso_buf[12]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(WRAP_EXT), .QN());
//UPDATE_ADDR_EXT (1'h0)
DFFRNLLX1HVT_TSMC90 UPDATE_ADDR_EXT_0 (.CLK(addr_in_iso_buf[12]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(UPDATE_ADDR_EXT), .QN());
//BIT_EN_EXT (2'h1)
DFFRNLLX1HVT_TSMC90 BIT_EN_EXT_1 (.CLK(addr_in_iso_buf[12]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(BIT_EN_EXT[1]), .QN());
DFFSNLLX1HVT_TSMC90 BIT_EN_EXT_0 (.CLK(addr_in_iso_buf[12]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(BIT_EN_EXT[0]), .QN());
//****************************************************
// REGISTER 0x0D ( 13)
//****************************************************
//TIMEOUT_EXT (20'hFFFFF)
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_19 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[19]), .SN(RESETn), .Q(TIMEOUT_EXT[19]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_18 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[18]), .SN(RESETn), .Q(TIMEOUT_EXT[18]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_17 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[17]), .SN(RESETn), .Q(TIMEOUT_EXT[17]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_16 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[16]), .SN(RESETn), .Q(TIMEOUT_EXT[16]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_15 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[15]), .SN(RESETn), .Q(TIMEOUT_EXT[15]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_14 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[14]), .SN(RESETn), .Q(TIMEOUT_EXT[14]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_13 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[13]), .SN(RESETn), .Q(TIMEOUT_EXT[13]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_12 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(TIMEOUT_EXT[12]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_11 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(TIMEOUT_EXT[11]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_10 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(TIMEOUT_EXT[10]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_9 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(TIMEOUT_EXT[9]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_8 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(TIMEOUT_EXT[8]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_7 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(TIMEOUT_EXT[7]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_6 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(TIMEOUT_EXT[6]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_5 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(TIMEOUT_EXT[5]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_4 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(TIMEOUT_EXT[4]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_3 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(TIMEOUT_EXT[3]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_2 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(TIMEOUT_EXT[2]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_1 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(TIMEOUT_EXT[1]), .QN());
DFFSNLLX1HVT_TSMC90 TIMEOUT_EXT_0 (.CLK(addr_in_iso_buf[13]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(TIMEOUT_EXT[0]), .QN());
//****************************************************
// REGISTER 0x0E ( 14)
//****************************************************
//SRAM_START_ADDR_EXT (13'h0000)
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_12 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[12]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_11 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[11]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_10 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[10]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_9 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[9]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_8 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[8]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_7 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[7]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_6 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[6]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_5 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[5]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_4 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[4]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_3 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[3]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_2 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[2]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_1 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[1]), .QN());
DFFRNLLX1HVT_TSMC90 SRAM_START_ADDR_EXT_0 (.CLK(addr_in_iso_buf[14]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(SRAM_START_ADDR_EXT[0]), .QN());
//****************************************************
// REGISTER 0x0F ( 15)
//****************************************************
//INT_RPLY_SHORT_ADDR (8'h10)
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_7 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[7]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_6 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[6]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_5 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[5]), .QN());
DFFSNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_4 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(INT_RPLY_SHORT_ADDR[4]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_3 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[3]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_2 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[2]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_1 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[1]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_SHORT_ADDR_0 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(INT_RPLY_SHORT_ADDR[0]), .QN());
//INT_RPLY_REG_ADDR (8'h00)
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_7 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[7]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_6 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[6]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_5 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[5]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_4 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[4]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_3 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[3]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_2 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[2]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_1 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[1]), .QN());
DFFRNLLX1HVT_TSMC90 INT_RPLY_REG_ADDR_0 (.CLK(addr_in_iso_buf[15]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(INT_RPLY_REG_ADDR[0]), .QN());
//****************************************************
// REGISTER 0x10 ( 16)
//****************************************************
//BOOT_FLAG_SLEEP (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_SLEEP_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(BOOT_FLAG_SLEEP), .QN());
//BOOT_FLAG_ECC_ERROR (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_ECC_ERROR_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(BOOT_FLAG_ECC_ERROR), .QN());
//BOOT_FLAG_WRONG_HEADER (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_WRONG_HEADER_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(BOOT_FLAG_WRONG_HEADER), .QN());
//BOOT_FLAG_PWDN (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_PWDN_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(BOOT_FLAG_PWDN), .QN());
//BOOT_FLAG_INVALID_CMND (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_INVALID_CMND_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(BOOT_FLAG_INVALID_CMND), .QN());
//BOOT_FLAG_CHKSUM_ERROR (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_CHKSUM_ERROR_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(BOOT_FLAG_CHKSUM_ERROR), .QN());
//BOOT_FLAG_SUCCESS (1'h0)
DFFRNLLX1HVT_TSMC90 BOOT_FLAG_SUCCESS_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(BOOT_FLAG_SUCCESS), .QN());
//BOOT_REG_PATTERN (2'h0)
DFFRNLLX1HVT_TSMC90 BOOT_REG_PATTERN_1 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(BOOT_REG_PATTERN[1]), .QN());
DFFRNLLX1HVT_TSMC90 BOOT_REG_PATTERN_0 (.CLK(addr_in_iso_buf[16]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(BOOT_REG_PATTERN[0]), .QN());
//****************************************************
// REGISTER 0x11 ( 17)
//****************************************************
//FLASH_POWER_DO_VREFCOMP (1'h1)
DFFSNLLX1HVT_TSMC90 FLASH_POWER_DO_VREFCOMP_0 (.CLK(addr_in_iso_buf[17]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(FLASH_POWER_DO_VREFCOMP), .QN());
//FLASH_POWER_DO_FLSH (1'h1)
DFFSNLLX1HVT_TSMC90 FLASH_POWER_DO_FLSH_0 (.CLK(addr_in_iso_buf[17]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(FLASH_POWER_DO_FLSH), .QN());
//FLASH_POWER_IRQ_EN (1'h1)
DFFSNLLX1HVT_TSMC90 FLASH_POWER_IRQ_EN_0 (.CLK(addr_in_iso_buf[17]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(FLASH_POWER_IRQ_EN), .QN());
//FLASH_POWER_SEL_ON (1'h1)
DFFSNLLX1HVT_TSMC90 FLASH_POWER_SEL_ON_0 (.CLK(addr_in_iso_buf[17]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(FLASH_POWER_SEL_ON), .QN());
//FLASH_POWER_GO (1'h0)
DFFRNLLX1HVT_TSMC90 FLASH_POWER_GO_0 (.CLK(addr_in_iso_buf[17]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLASH_POWER_GO), .QN());
//****************************************************
// REGISTER 0x12 ( 18)
//****************************************************
//IRQ_PWR_ON_WUP (1'h0)
DFFRNLLX1HVT_TSMC90 IRQ_PWR_ON_WUP_0 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(IRQ_PWR_ON_WUP), .QN());
//SEL_PWR_ON_WUP (3'h0)
DFFRNLLX1HVT_TSMC90 SEL_PWR_ON_WUP_2 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(SEL_PWR_ON_WUP[2]), .QN());
DFFRNLLX1HVT_TSMC90 SEL_PWR_ON_WUP_1 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(SEL_PWR_ON_WUP[1]), .QN());
DFFRNLLX1HVT_TSMC90 SEL_PWR_ON_WUP_0 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(SEL_PWR_ON_WUP[0]), .QN());
//FLASH_AUTO_USE_CUSTOM (1'h0)
DFFRNLLX1HVT_TSMC90 FLASH_AUTO_USE_CUSTOM_0 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLASH_AUTO_USE_CUSTOM), .QN());
//FLASH_AUTO_OFF (1'h0)
DFFRNLLX1HVT_TSMC90 FLASH_AUTO_OFF_0 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLASH_AUTO_OFF), .QN());
//FLASH_AUTO_ON (1'h0)
DFFRNLLX1HVT_TSMC90 FLASH_AUTO_ON_0 (.CLK(addr_in_iso_buf[18]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLASH_AUTO_ON), .QN());
//****************************************************
// REGISTER 0x13 ( 19)
//****************************************************
//PP_STR_LIMIT (19'h00000)
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_18 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(PP_STR_LIMIT[18]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_17 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(PP_STR_LIMIT[17]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_16 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(PP_STR_LIMIT[16]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_15 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(PP_STR_LIMIT[15]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_14 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(PP_STR_LIMIT[14]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_13 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(PP_STR_LIMIT[13]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_12 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(PP_STR_LIMIT[12]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_11 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(PP_STR_LIMIT[11]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_10 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(PP_STR_LIMIT[10]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_9 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(PP_STR_LIMIT[9]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_8 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(PP_STR_LIMIT[8]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_7 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(PP_STR_LIMIT[7]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_6 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(PP_STR_LIMIT[6]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_5 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(PP_STR_LIMIT[5]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_4 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(PP_STR_LIMIT[4]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_3 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(PP_STR_LIMIT[3]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_2 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(PP_STR_LIMIT[2]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_1 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(PP_STR_LIMIT[1]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_STR_LIMIT_0 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(PP_STR_LIMIT[0]), .QN());
//PP_STR_EN (1'h0)
//DFFRNLLX1HVT_TSMC90 PP_STR_EN_0 (.CLK(addr_in_iso_buf[19]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(PP_STR_EN), .QN());
//****************************************************
// REGISTER 0x14 ( 20)
//****************************************************
//PP_NO_ERR_DETECTION (1'h0)
DFFRNLLX1HVT_TSMC90 PP_NO_ERR_DETECTION_0 (.CLK(addr_in_iso_buf[20]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(PP_NO_ERR_DETECTION), .QN());
//PP_USE_FAST_PROG (1'h0)
DFFRNLLX1HVT_TSMC90 PP_USE_FAST_PROG_0 (.CLK(addr_in_iso_buf[20]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(PP_USE_FAST_PROG), .QN());
//PP_WRAP (1'h0)
DFFRNLLX1HVT_TSMC90 PP_WRAP_0 (.CLK(addr_in_iso_buf[20]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(PP_WRAP), .QN());
//PP_BIT_EN_EXT (2'h1)
DFFRNLLX1HVT_TSMC90 PP_BIT_EN_EXT_1 (.CLK(addr_in_iso_buf[20]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(PP_BIT_EN_EXT[1]), .QN());
DFFSNLLX1HVT_TSMC90 PP_BIT_EN_EXT_0 (.CLK(addr_in_iso_buf[20]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(PP_BIT_EN_EXT[0]), .QN());
//****************************************************
// REGISTER 0x15 ( 21)
//****************************************************
//PP_FLSH_ADDR (18'h00000)
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_17 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(PP_FLSH_ADDR[17]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_16 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(PP_FLSH_ADDR[16]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_15 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(PP_FLSH_ADDR[15]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_14 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(PP_FLSH_ADDR[14]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_13 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(PP_FLSH_ADDR[13]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_12 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(PP_FLSH_ADDR[12]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_11 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(PP_FLSH_ADDR[11]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_10 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(PP_FLSH_ADDR[10]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_9 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(PP_FLSH_ADDR[9]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_8 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(PP_FLSH_ADDR[8]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_7 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(PP_FLSH_ADDR[7]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_6 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(PP_FLSH_ADDR[6]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_5 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(PP_FLSH_ADDR[5]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_4 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(PP_FLSH_ADDR[4]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_3 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(PP_FLSH_ADDR[3]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_2 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(PP_FLSH_ADDR[2]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_1 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(PP_FLSH_ADDR[1]), .QN());
DFFRNLLX1HVT_TSMC90 PP_FLSH_ADDR_0 (.CLK(addr_in_iso_buf[21]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(PP_FLSH_ADDR[0]), .QN());
//****************************************************
// REGISTER 0x16 ( 22)
//****************************************************
//PP_LENGTH_STREAMED (19'h00000)
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_18 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[18]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_17 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[17]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_16 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[16]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_15 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[15]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_14 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[14]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_13 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[13]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_12 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[12]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_11 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[11]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_10 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[10]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_9 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[9]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_8 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[8]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_7 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[7]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_6 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[6]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_5 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[5]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_4 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[4]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_3 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[3]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_2 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[2]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_1 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[1]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_STREAMED_0 (.CLK(addr_in_iso_buf[22]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(PP_LENGTH_STREAMED[0]), .QN());
//****************************************************
// REGISTER 0x17 ( 23)
//****************************************************
//PP_FLAG_END_OF_FLASH (1'h0)
//DFFRNLLX1HVT_TSMC90 PP_FLAG_END_OF_FLASH_0 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(PP_FLAG_END_OF_FLASH), .QN());
//PP_FLAG_STR_LIMIT (1'h0)
//DFFRNLLX1HVT_TSMC90 PP_FLAG_STR_LIMIT_0 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(PP_FLAG_STR_LIMIT), .QN());
//PP_FLAG_COPY_LIMIT (1'h0)
//DFFRNLLX1HVT_TSMC90 PP_FLAG_COPY_LIMIT_0 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(PP_FLAG_COPY_LIMIT), .QN());
//PP_LENGTH_COPIED (19'h00000)
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_18 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(PP_LENGTH_COPIED[18]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_17 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(PP_LENGTH_COPIED[17]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_16 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(PP_LENGTH_COPIED[16]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_15 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(PP_LENGTH_COPIED[15]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_14 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(PP_LENGTH_COPIED[14]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_13 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(PP_LENGTH_COPIED[13]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_12 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(PP_LENGTH_COPIED[12]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_11 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(PP_LENGTH_COPIED[11]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_10 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(PP_LENGTH_COPIED[10]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_9 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(PP_LENGTH_COPIED[9]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_8 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(PP_LENGTH_COPIED[8]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_7 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(PP_LENGTH_COPIED[7]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_6 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(PP_LENGTH_COPIED[6]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_5 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(PP_LENGTH_COPIED[5]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_4 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(PP_LENGTH_COPIED[4]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_3 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(PP_LENGTH_COPIED[3]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_2 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(PP_LENGTH_COPIED[2]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_1 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(PP_LENGTH_COPIED[1]), .QN());
//DFFRNLLX1HVT_TSMC90 PP_LENGTH_COPIED_0 (.CLK(addr_in_iso_buf[23]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(PP_LENGTH_COPIED[0]), .QN());
//****************************************************
// REGISTER 0x18 ( 24)
//****************************************************
//CLK_RING_SEL (4'hC)
DFFSNLLX1HVT_TSMC90 CLK_RING_SEL_3 (.CLK(addr_in_iso_buf[24]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(CLK_RING_SEL[3]), .QN());
DFFSNLLX1HVT_TSMC90 CLK_RING_SEL_2 (.CLK(addr_in_iso_buf[24]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(CLK_RING_SEL[2]), .QN());
DFFRNLLX1HVT_TSMC90 CLK_RING_SEL_1 (.CLK(addr_in_iso_buf[24]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(CLK_RING_SEL[1]), .QN());
DFFRNLLX1HVT_TSMC90 CLK_RING_SEL_0 (.CLK(addr_in_iso_buf[24]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(CLK_RING_SEL[0]), .QN());
//CLK_DIV_SEL (2'h1)
DFFRNLLX1HVT_TSMC90 CLK_DIV_SEL_1 (.CLK(addr_in_iso_buf[24]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(CLK_DIV_SEL[1]), .QN());
DFFSNLLX1HVT_TSMC90 CLK_DIV_SEL_0 (.CLK(addr_in_iso_buf[24]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(CLK_DIV_SEL[0]), .QN());
//****************************************************
// REGISTER 0x19 ( 25)
//****************************************************
//DISABLE_BYPASS_MIRROR (1'h1)
DFFSNLLX1HVT_TSMC90 DISABLE_BYPASS_MIRROR_0 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(DISABLE_BYPASS_MIRROR), .QN());
//COMP_CTRL_I_1STG (4'h8)
DFFSNLLX1HVT_TSMC90 COMP_CTRL_I_1STG_3 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(COMP_CTRL_I_1STG[3]), .QN());
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_1STG_2 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(COMP_CTRL_I_1STG[2]), .QN());
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_1STG_1 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(COMP_CTRL_I_1STG[1]), .QN());
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_1STG_0 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(COMP_CTRL_I_1STG[0]), .QN());
//COMP_CTRL_I_2STG_BAR (4'h0)
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_2STG_BAR_3 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(COMP_CTRL_I_2STG_BAR[3]), .QN());
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_2STG_BAR_2 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(COMP_CTRL_I_2STG_BAR[2]), .QN());
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_2STG_BAR_1 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(COMP_CTRL_I_2STG_BAR[1]), .QN());
DFFRNLLX1HVT_TSMC90 COMP_CTRL_I_2STG_BAR_0 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(COMP_CTRL_I_2STG_BAR[0]), .QN());
//COMP_CTRL_VOUT (3'h3)
DFFRNLLX1HVT_TSMC90 COMP_CTRL_VOUT_2 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(COMP_CTRL_VOUT[2]), .QN());
DFFSNLLX1HVT_TSMC90 COMP_CTRL_VOUT_1 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(COMP_CTRL_VOUT[1]), .QN());
DFFSNLLX1HVT_TSMC90 COMP_CTRL_VOUT_0 (.CLK(addr_in_iso_buf[25]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(COMP_CTRL_VOUT[0]), .QN());
//****************************************************
// REGISTER 0x1A ( 26) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x1B ( 27)
//****************************************************
//IRQ_PAYLOAD (8'h00)
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_7 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(IRQ_PAYLOAD[7]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_6 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(IRQ_PAYLOAD[6]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_5 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(IRQ_PAYLOAD[5]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_4 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(IRQ_PAYLOAD[4]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_3 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(IRQ_PAYLOAD[3]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_2 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(IRQ_PAYLOAD[2]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_1 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(IRQ_PAYLOAD[1]), .QN());
//DFFRNLLX1HVT_TSMC90 IRQ_PAYLOAD_0 (.CLK(addr_in_iso_buf[27]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(IRQ_PAYLOAD[0]), .QN());
//****************************************************
// REGISTER 0x1C ( 28) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x1D ( 29) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x1E ( 30)
//****************************************************
//FLS2LC_REG_WR_DATA (24'h000000)
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_23 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[23]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_22 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[22]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_21 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[21]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_20 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[20]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_19 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[19]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_18 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[18]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_17 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[17]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_16 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[16]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_15 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[15]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_14 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[14]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_13 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[13]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_12 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[12]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_11 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[11]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_10 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[10]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_9 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[9]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_8 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[8]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_7 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[7]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_6 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[6]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_5 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[5]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_4 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[4]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_3 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[3]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_2 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[2]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_1 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[1]), .QN());
//DFFRNLLX1HVT_TSMC90 FLS2LC_REG_WR_DATA_0 (.CLK(addr_in_iso_buf[30]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLS2LC_REG_WR_DATA[0]), .QN());
//****************************************************
// REGISTER 0x1F ( 31)
//****************************************************
//FORCE_RESETN (1'h1)
DFFSNLLX1HVT_TSMC90 FORCE_RESETN_0 (.CLK(addr_in_iso_buf[31]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(FORCE_RESETN), .QN());
//****************************************************
// REGISTER 0x20 ( 32)
//****************************************************
//FLSH_SET0 (5'h04)
DFFRNLLX1HVT_TSMC90 FLSH_SET0_4 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLSH_SET0[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SET0_3 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLSH_SET0[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SET0_2 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(FLSH_SET0[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SET0_1 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(FLSH_SET0[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SET0_0 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(FLSH_SET0[0]), .QN());
//FLSH_SET1 (5'h04)
DFFRNLLX1HVT_TSMC90 FLSH_SET1_4 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_SET1[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SET1_3 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_SET1[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SET1_2 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SET1[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SET1_1 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(FLSH_SET1[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SET1_0 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLSH_SET1[0]), .QN());
//FLSH_SNT (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SNT_4 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SNT[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SNT_3 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SNT[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SNT_2 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(FLSH_SNT[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SNT_1 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(FLSH_SNT[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SNT_0 (.CLK(addr_in_iso_buf[32]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(FLSH_SNT[0]), .QN());
//****************************************************
// REGISTER 0x21 ( 33)
//****************************************************
//FLSH_SPT0 (5'h04)
DFFRNLLX1HVT_TSMC90 FLSH_SPT0_4 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLSH_SPT0[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT0_3 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLSH_SPT0[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SPT0_2 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(FLSH_SPT0[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT0_1 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(FLSH_SPT0[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT0_0 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(FLSH_SPT0[0]), .QN());
//FLSH_SPT1 (5'h04)
DFFRNLLX1HVT_TSMC90 FLSH_SPT1_4 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_SPT1[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT1_3 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_SPT1[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SPT1_2 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SPT1[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT1_1 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(FLSH_SPT1[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT1_0 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLSH_SPT1[0]), .QN());
//FLSH_SPT2 (5'h04)
DFFRNLLX1HVT_TSMC90 FLSH_SPT2_4 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SPT2[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT2_3 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SPT2[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SPT2_2 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(FLSH_SPT2[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT2_1 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLSH_SPT2[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPT2_0 (.CLK(addr_in_iso_buf[33]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLSH_SPT2[0]), .QN());
//****************************************************
// REGISTER 0x22 ( 34)
//****************************************************
//FLSH_SYT0 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SYT0_4 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_SYT0[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SYT0_3 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_SYT0[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SYT0_2 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SYT0[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SYT0_1 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(FLSH_SYT0[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SYT0_0 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(FLSH_SYT0[0]), .QN());
//FLSH_SYT1 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SYT1_4 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SYT1[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SYT1_3 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SYT1[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SYT1_2 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(FLSH_SYT1[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SYT1_1 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(FLSH_SYT1[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SYT1_0 (.CLK(addr_in_iso_buf[34]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(FLSH_SYT1[0]), .QN());
//****************************************************
// REGISTER 0x23 ( 35)
//****************************************************
//FLSH_SRT0 (5'h01)
DFFRNLLX1HVT_TSMC90 FLSH_SRT0_4 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(FLSH_SRT0[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT0_3 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(FLSH_SRT0[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT0_2 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(FLSH_SRT0[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT0_1 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(FLSH_SRT0[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT0_0 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[15]), .SN(RESETn), .Q(FLSH_SRT0[0]), .QN());
//FLSH_SRT1 (5'h03)
DFFRNLLX1HVT_TSMC90 FLSH_SRT1_4 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLSH_SRT1[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT1_3 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLSH_SRT1[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT1_2 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(FLSH_SRT1[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT1_1 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(FLSH_SRT1[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT1_0 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(FLSH_SRT1[0]), .QN());
//FLSH_SRT2 (5'h03)
DFFRNLLX1HVT_TSMC90 FLSH_SRT2_4 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_SRT2[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT2_3 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_SRT2[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT2_2 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(FLSH_SRT2[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT2_1 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(FLSH_SRT2[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT2_0 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(FLSH_SRT2[0]), .QN());
//FLSH_SRT3 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SRT3_4 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SRT3[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT3_3 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SRT3[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT3_2 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(FLSH_SRT3[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT3_1 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(FLSH_SRT3[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT3_0 (.CLK(addr_in_iso_buf[35]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(FLSH_SRT3[0]), .QN());
//****************************************************
// REGISTER 0x24 ( 36)
//****************************************************
//FLSH_SRT4 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SRT4_4 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLSH_SRT4[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT4_3 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLSH_SRT4[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT4_2 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(FLSH_SRT4[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT4_1 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(FLSH_SRT4[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT4_0 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(FLSH_SRT4[0]), .QN());
//FLSH_SRT5 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SRT5_4 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_SRT5[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT5_3 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_SRT5[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT5_2 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SRT5[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT5_1 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(FLSH_SRT5[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT5_0 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(FLSH_SRT5[0]), .QN());
//FLSH_SRT6 (5'h01)
DFFRNLLX1HVT_TSMC90 FLSH_SRT6_4 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SRT6[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT6_3 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SRT6[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT6_2 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLSH_SRT6[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SRT6_1 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLSH_SRT6[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRT6_0 (.CLK(addr_in_iso_buf[36]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(FLSH_SRT6[0]), .QN());
//****************************************************
// REGISTER 0x25 ( 37) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x26 ( 38)
//****************************************************
//FLSH_SPIG (4'hD)
DFFSNLLX1HVT_TSMC90 FLSH_SPIG_3 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[19]), .SN(RESETn), .Q(FLSH_SPIG[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SPIG_2 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[18]), .SN(RESETn), .Q(FLSH_SPIG[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SPIG_1 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(FLSH_SPIG[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SPIG_0 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[16]), .SN(RESETn), .Q(FLSH_SPIG[0]), .QN());
//FLSH_SRIG (4'h7)
DFFRNLLX1HVT_TSMC90 FLSH_SRIG_3 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(FLSH_SRIG[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRIG_2 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[14]), .SN(RESETn), .Q(FLSH_SRIG[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRIG_1 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[13]), .SN(RESETn), .Q(FLSH_SRIG[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SRIG_0 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(FLSH_SRIG[0]), .QN());
//FLSH_SVR0 (4'h7)
DFFRNLLX1HVT_TSMC90 FLSH_SVR0_3 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(FLSH_SVR0[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SVR0_2 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(FLSH_SVR0[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SVR0_1 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(FLSH_SVR0[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SVR0_0 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(FLSH_SVR0[0]), .QN());
//FLSH_SVR1 (4'h8)
DFFSNLLX1HVT_TSMC90 FLSH_SVR1_3 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SVR1[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SVR1_2 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(FLSH_SVR1[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SVR1_1 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLSH_SVR1[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SVR1_0 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SVR1[0]), .QN());
//FLSH_SVR2 (4'h8)
DFFSNLLX1HVT_TSMC90 FLSH_SVR2_3 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(FLSH_SVR2[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SVR2_2 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLSH_SVR2[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SVR2_1 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLSH_SVR2[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SVR2_0 (.CLK(addr_in_iso_buf[38]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLSH_SVR2[0]), .QN());
//****************************************************
// REGISTER 0x27 ( 39)
//****************************************************
//FLSH_SHVE (5'h01)
DFFRNLLX1HVT_TSMC90 FLSH_SHVE_4 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(FLSH_SHVE[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SHVE_3 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(FLSH_SHVE[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SHVE_2 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(FLSH_SHVE[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SHVE_1 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(FLSH_SHVE[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVE_0 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[16]), .SN(RESETn), .Q(FLSH_SHVE[0]), .QN());
//FLSH_SHVP (5'h03)
DFFRNLLX1HVT_TSMC90 FLSH_SHVP_4 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[15]), .RN(RESETn), .Q(FLSH_SHVP[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SHVP_3 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[14]), .RN(RESETn), .Q(FLSH_SHVP[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SHVP_2 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[13]), .RN(RESETn), .Q(FLSH_SHVP[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVP_1 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(FLSH_SHVP[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVP_0 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(FLSH_SHVP[0]), .QN());
//FLSH_SHVCT (5'h0F)
DFFRNLLX1HVT_TSMC90 FLSH_SHVCT_4 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(FLSH_SHVCT[4]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVCT_3 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(FLSH_SHVCT[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVCT_2 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(FLSH_SHVCT[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVCT_1 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SHVCT[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SHVCT_0 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(FLSH_SHVCT[0]), .QN());
//FLSH_SMV (6'h08)
DFFRNLLX1HVT_TSMC90 FLSH_SMV_5 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLSH_SMV[5]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SMV_4 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SMV[4]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMV_3 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(FLSH_SMV[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SMV_2 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLSH_SMV[2]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SMV_1 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(FLSH_SMV[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SMV_0 (.CLK(addr_in_iso_buf[39]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLSH_SMV[0]), .QN());
//****************************************************
// REGISTER 0x28 ( 40)
//****************************************************
//FLSH_SMVCT0 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SMVCT0_4 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(FLSH_SMVCT0[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SMVCT0_3 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(FLSH_SMVCT0[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMVCT0_2 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(FLSH_SMVCT0[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMVCT0_1 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(FLSH_SMVCT0[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMVCT0_0 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(FLSH_SMVCT0[0]), .QN());
//FLSH_SMVCT1 (5'h07)
DFFRNLLX1HVT_TSMC90 FLSH_SMVCT1_4 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SMVCT1[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SMVCT1_3 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SMVCT1[3]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMVCT1_2 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(FLSH_SMVCT1[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMVCT1_1 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(FLSH_SMVCT1[1]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SMVCT1_0 (.CLK(addr_in_iso_buf[40]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(FLSH_SMVCT1[0]), .QN());
//****************************************************
// REGISTER 0x29 ( 41) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x2A ( 42)
//****************************************************
//FLSH_SAB (6'h02)
DFFRNLLX1HVT_TSMC90 FLSH_SAB_5 (.CLK(addr_in_iso_buf[42]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(FLSH_SAB[5]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SAB_4 (.CLK(addr_in_iso_buf[42]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(FLSH_SAB[4]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SAB_3 (.CLK(addr_in_iso_buf[42]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(FLSH_SAB[3]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SAB_2 (.CLK(addr_in_iso_buf[42]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(FLSH_SAB[2]), .QN());
DFFSNLLX1HVT_TSMC90 FLSH_SAB_1 (.CLK(addr_in_iso_buf[42]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(FLSH_SAB[1]), .QN());
DFFRNLLX1HVT_TSMC90 FLSH_SAB_0 (.CLK(addr_in_iso_buf[42]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(FLSH_SAB[0]), .QN());
//****************************************************
// REGISTER 0x2B ( 43) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x2C ( 44) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x2D ( 45) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x2E ( 46) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x2F ( 47) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x30 ( 48)
//****************************************************
//STR_WR_CH1_ALT_ADDR (8'hF0)
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_7 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[23]), .SN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[7]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_6 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[22]), .SN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[6]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_5 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[21]), .SN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[5]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_4 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[20]), .SN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[4]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_3 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[3]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_2 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[2]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_1 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[1]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_ADDR_0 (.CLK(addr_in_iso_buf[48]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(STR_WR_CH1_ALT_ADDR[0]), .QN());
//****************************************************
// REGISTER 0x31 ( 49)
//****************************************************
//STR_WR_CH1_ALT_REG_WR (8'h00)
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_7 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[7]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_6 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[6]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_5 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[5]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_4 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[4]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_3 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[3]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_2 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[2]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_1 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[1]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_ALT_REG_WR_0 (.CLK(addr_in_iso_buf[49]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(STR_WR_CH1_ALT_REG_WR[0]), .QN());
//****************************************************
// REGISTER 0x32 ( 50)
//****************************************************
//STR_WR_CH1_EN (1'h1)
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_EN_0 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[23]), .SN(RESETn), .Q(STR_WR_CH1_EN), .QN());
//STR_WR_CH1_WRP (1'h1)
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_WRP_0 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[22]), .SN(RESETn), .Q(STR_WR_CH1_WRP), .QN());
//STR_WR_CH1_DBLB (1'h0)
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_DBLB_0 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(STR_WR_CH1_DBLB), .QN());
//STR_WR_CH1_BUF_LEN (13'h1FFF)
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_12 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[12]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_11 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[11]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_10 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[10]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_9 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[9]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_8 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[8]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_7 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[7]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_6 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[6]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_5 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[5]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_4 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[4]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_3 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[3]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_2 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[2]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_1 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[1]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH1_BUF_LEN_0 (.CLK(addr_in_iso_buf[50]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(STR_WR_CH1_BUF_LEN[0]), .QN());
//****************************************************
// REGISTER 0x33 ( 51)
//****************************************************
//STR_WR_CH1_BUF_OFF (13'h0000)
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_12 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[12]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_11 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[11]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_10 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[10]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_9 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[9]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_8 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[8]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_7 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[7]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_6 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[6]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_5 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[5]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_4 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[4]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_3 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[3]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_2 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[2]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_1 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[1]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH1_BUF_OFF_0 (.CLK(addr_in_iso_buf[51]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(STR_WR_CH1_BUF_OFF[0]), .QN());
//****************************************************
// REGISTER 0x34 ( 52)
//****************************************************
//STR_WR_CH0_ALT_ADDR (8'hF0)
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_7 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[23]), .SN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[7]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_6 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[22]), .SN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[6]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_5 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[21]), .SN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[5]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_4 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[20]), .SN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[4]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_3 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[3]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_2 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[2]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_1 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[1]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_ADDR_0 (.CLK(addr_in_iso_buf[52]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(STR_WR_CH0_ALT_ADDR[0]), .QN());
//****************************************************
// REGISTER 0x35 ( 53)
//****************************************************
//STR_WR_CH0_ALT_REG_WR (8'h00)
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_7 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[7]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_6 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[22]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[6]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_5 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[5]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_4 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[20]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[4]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_3 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[19]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[3]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_2 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[18]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[2]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_1 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[17]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[1]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_ALT_REG_WR_0 (.CLK(addr_in_iso_buf[53]), .D(data_in_iso_buf[16]), .RN(RESETn), .Q(STR_WR_CH0_ALT_REG_WR[0]), .QN());
//****************************************************
// REGISTER 0x36 ( 54)
//****************************************************
//STR_WR_CH0_EN (1'h1)
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_EN_0 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[23]), .SN(RESETn), .Q(STR_WR_CH0_EN), .QN());
//STR_WR_CH0_WRP (1'h1)
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_WRP_0 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[22]), .SN(RESETn), .Q(STR_WR_CH0_WRP), .QN());
//STR_WR_CH0_DBLB (1'h0)
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_DBLB_0 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[21]), .RN(RESETn), .Q(STR_WR_CH0_DBLB), .QN());
//STR_WR_CH0_BUF_LEN (13'h1FFF)
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_12 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[12]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[12]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_11 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[11]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[11]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_10 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[10]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[10]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_9 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[9]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[9]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_8 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[8]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[8]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_7 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[7]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[7]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_6 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[6]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[6]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_5 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[5]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[5]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_4 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[4]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[4]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_3 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[3]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[3]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_2 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[2]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[2]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_1 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[1]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[1]), .QN());
DFFSNLLX1HVT_TSMC90 STR_WR_CH0_BUF_LEN_0 (.CLK(addr_in_iso_buf[54]), .D(data_in_iso_buf[0]), .SN(RESETn), .Q(STR_WR_CH0_BUF_LEN[0]), .QN());
//****************************************************
// REGISTER 0x37 ( 55)
//****************************************************
//STR_WR_CH0_BUF_OFF (13'h0000)
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_12 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[12]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[12]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_11 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[11]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[11]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_10 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[10]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[10]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_9 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[9]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[9]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_8 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[8]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[8]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_7 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[7]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[7]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_6 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[6]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[6]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_5 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[5]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[5]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_4 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[4]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[4]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_3 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[3]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[3]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_2 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[2]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[2]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_1 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[1]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[1]), .QN());
DFFRNLLX1HVT_TSMC90 STR_WR_CH0_BUF_OFF_0 (.CLK(addr_in_iso_buf[55]), .D(data_in_iso_buf[0]), .RN(RESETn), .Q(STR_WR_CH0_BUF_OFF[0]), .QN());
//****************************************************
// REGISTER 0x38 ( 56) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x39 ( 57) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x3A ( 58)
//****************************************************
//BLK_WR_EN (1'h1)
DFFSNLLX1HVT_TSMC90 BLK_WR_EN_0 (.CLK(addr_in_iso_buf[58]), .D(data_in_iso_buf[23]), .SN(RESETn), .Q(BLK_WR_EN), .QN());
//****************************************************
// REGISTER 0x3B ( 59) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x3C ( 60) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x3D ( 61) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x3E ( 62) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x3F ( 63) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x40 ( 64) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x41 ( 65) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x42 ( 66) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x43 ( 67) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x44 ( 68) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x45 ( 69) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x46 ( 70) - Empty Register
//****************************************************
//****************************************************
// REGISTER 0x47 ( 71)
//****************************************************
//ACT_RST (1'h0)
DFFRNLLX1HVT_TSMC90 ACT_RST_0 (.CLK(addr_in_iso_buf[71]), .D(data_in_iso_buf[23]), .RN(RESETn), .Q(ACT_RST), .QN());
endmodule // flpv3l_rf
|
module step_ex_cpf(clk, rst_, ena_, rdy_, reg_id,
r0_din, r0_we_,
r0_dout, r1_dout, r2_dout, r3_dout, r4_dout, r5_dout, fl_dout, pc_dout);
input clk;
input rst_;
input ena_;
output rdy_;
input[3:0] reg_id;
output[7:0] r0_din;
output r0_we_;
input[7:0] r0_dout, r1_dout, r2_dout, r3_dout, r4_dout, r5_dout, fl_dout, pc_dout;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg r0_din_en;
assign r0_din = r0_din_en ? regs_dout[reg_id] : 8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg state;
tri0[7:0] regs_dout[15:0];
assign regs_dout[0] = r0_dout;
assign regs_dout[1] = r1_dout;
assign regs_dout[2] = r2_dout;
assign regs_dout[3] = r3_dout;
assign regs_dout[4] = r4_dout;
assign regs_dout[5] = r5_dout;
assign regs_dout[10] = fl_dout;
assign regs_dout[14] = 8'hff;
assign regs_dout[15] = pc_dout;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
state <= 0;
end else if(!ena_) begin
rdy_en <= 0;
r0_din_en <= 1;
r0_we_en <= 0;
state <= 1;
end else if(state) begin
rdy_en <= 1;
r0_din_en <= 1;
r0_we_en <= 1;
state <= 0;
end else begin
rdy_en <= 0;
r0_din_en <= 0;
r0_we_en <= 0;
end
endmodule
|
//*******************************************************************************************
//Author: Zhiyoong Foo, Yejoong Kim
//Last Modified: Dec 16 2016
//Description: MBus CLK/DATA Swapper
// - Generates Data & Clock Flip Interrupt;
// - Maintains Last seen Clock State
//Update History: Mar 06 2013 - First Commit (Zhiyoong Foo)
// May 21 2016 - Included in MBus r03 (Yejoong Kim)
// Dec 16 2016 - Included in MBus r04 (Yejoong Kim)
//*******************************************************************************************
module flpv3l_mbus_swapper (
//Inputs
input CLK,
input RESETn,
input DATA,
input INT_FLAG_RESETn,
//Outputs
output reg LAST_CLK,
output reg INT_FLAG
);
//Internal Declerations
wire negp_reset;
wire posp_reset;
//Negative Phase Clock Resets
reg pose_negp_clk_0; //Positive Edge
reg nege_negp_clk_1; //Negative Edge
reg pose_negp_clk_2;
reg nege_negp_clk_3;
reg pose_negp_clk_4;
reg nege_negp_clk_5;
wire negp_int; //Negative Phase Interrupt
//Interrupt Reset
wire int_resetn;
assign negp_reset = ~( CLK && RESETn);
//////////////////////////////////////////
// Interrupt Generation
//////////////////////////////////////////
//Negative Phase Clock Resets
always @(posedge DATA or posedge negp_reset) begin
if (negp_reset) begin
pose_negp_clk_0 = 0;
pose_negp_clk_2 = 0;
pose_negp_clk_4 = 0;
end
else begin
pose_negp_clk_0 = 1;
pose_negp_clk_2 = nege_negp_clk_1;
pose_negp_clk_4 = nege_negp_clk_3;
end
end
always @(negedge DATA or posedge negp_reset) begin
if (negp_reset) begin
nege_negp_clk_1 = 0;
nege_negp_clk_3 = 0;
nege_negp_clk_5 = 0;
end
else begin
nege_negp_clk_1 = pose_negp_clk_0;
nege_negp_clk_3 = pose_negp_clk_2;
nege_negp_clk_5 = pose_negp_clk_4;
end
end
//Negative Phase Interrupt Generation
assign negp_int = pose_negp_clk_0 && nege_negp_clk_1 &&
pose_negp_clk_2 && nege_negp_clk_3 &&
pose_negp_clk_4 && nege_negp_clk_5;
//Interrupt Check & Clear
assign int_resetn = RESETn && INT_FLAG_RESETn;
always @(posedge negp_int or negedge int_resetn) begin
if (~int_resetn) INT_FLAG = 0;
else INT_FLAG = 1;
end
//////////////////////////////////////////
// Last Seen Clock
//////////////////////////////////////////
always @(posedge negp_int or negedge RESETn) begin
if (~RESETn) LAST_CLK = 0;
else LAST_CLK = CLK;
end
endmodule // flpv3l_mbus_swapper
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// YM2610 wrapper
// Clock enabled at 7.5 - 8.5MHz
module jt10(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input [1:0] addr,
input cs_n,
input wr_n,
output [7:0] dout,
output irq_n,
// ADPCM pins
output [19:0] adpcma_addr, // real hardware has 10 pins multiplexed through RMPX pin
output [3:0] adpcma_bank,
output adpcma_roe_n, // ADPCM-A ROM output enable
input [7:0] adpcma_data, // Data from RAM
output [23:0] adpcmb_addr, // real hardware has 12 pins multiplexed through PMPX pin
output adpcmb_roe_n, // ADPCM-B ROM output enable
input [7:0] adpcmb_data,
// Separated output
output [ 7:0] psg_A,
output [ 7:0] psg_B,
output [ 7:0] psg_C,
output signed [15:0] fm_snd,
// combined output
output [ 9:0] psg_snd,
output signed [15:0] snd_right,
output signed [15:0] snd_left,
output snd_sample
);
// Uses 6 FM channels but only 4 are outputted
jt12_top #(
.use_lfo(1),.use_ssg(1), .num_ch(6), .use_pcm(0), .use_adpcm(1),
.JT49_DIV(3) )
u_jt12(
.rst ( rst ), // rst should be at least 6 clk&cen cycles long
.clk ( clk ), // CPU clock
.cen ( cen ), // optional clock enable, it not needed leave as 1'b1
.din ( din ),
.addr ( addr ),
.cs_n ( cs_n ),
.wr_n ( wr_n ),
.dout ( dout ),
.irq_n ( irq_n ),
// ADPCM pins
.adpcma_addr ( adpcma_addr ), // real hardware has 10 pins multiplexed through RMPX pin
.adpcma_bank ( adpcma_bank ),
.adpcma_roe_n ( adpcma_roe_n ), // ADPCM-A ROM output enable
.adpcma_data ( adpcma_data ), // Data from RAM
.adpcmb_addr ( adpcmb_addr ), // real hardware has 12 pins multiplexed through PMPX pin
.adpcmb_roe_n ( adpcmb_roe_n ), // ADPCM-B ROM output enable
.adpcmb_data ( adpcmb_data ), // Data from RAM
// Separated output
.psg_A ( psg_A ),
.psg_B ( psg_B ),
.psg_C ( psg_C ),
.psg_snd ( psg_snd ),
.fm_snd_left ( fm_snd ),
.fm_snd_right (),
// Unused YM2203
.IOA_in (),
.IOB_in (),
// Sound output
.snd_right ( snd_right ),
.snd_left ( snd_left ),
.snd_sample ( snd_sample ),
// unused pins
.en_hifi_pcm ( 1'b0 ), // used only on YM2612 mode
.debug_view ( )
);
endmodule // jt03
|
/*
* Copyright (c) Mercury Federal Systems, Inc., Arlington VA., 2009-2010
*
* Mercury Federal Systems, Incorporated
* 1901 South Bell Street
* Suite 402
* Arlington, Virginia 22202
* United States of America
* Telephone 703-413-0781
* FAX 703-413-0784
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
//
// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24)
//
// On Tue Aug 17 11:59:04 EDT 2010
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS1_SThreadBusy O 1
// wsiS1_SReset_n O 1
// wsiM1_MCmd O 3
// wsiM1_MReqLast O 1
// wsiM1_MBurstPrecise O 1
// wsiM1_MBurstLength O 12
// wsiM1_MData O 256 reg
// wsiM1_MByteEn O 32 reg
// wsiM1_MReqInfo O 8
// wsiM1_MReset_n O 1
// wmemiM_MCmd O 3 reg
// wmemiM_MReqLast O 1 reg
// wmemiM_MAddr O 36 reg
// wmemiM_MBurstLength O 12 reg
// wmemiM_MDataValid O 1 reg
// wmemiM_MDataLast O 1 reg
// wmemiM_MData O 128 reg
// wmemiM_MDataByteEn O 16 reg
// wmemiM_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 20
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS1_MCmd I 3
// wsiS1_MBurstLength I 12
// wsiS1_MData I 256
// wsiS1_MByteEn I 32
// wsiS1_MReqInfo I 8
// wmemiM_SResp I 2
// wmemiM_SData I 128
// wsiS1_MReqLast I 1
// wsiS1_MBurstPrecise I 1
// wsiS1_MReset_n I 1 reg
// wsiM1_SThreadBusy I 1 reg
// wsiM1_SReset_n I 1 reg
// wmemiM_SRespLast I 1
// wmemiM_SCmdAccept I 1
// wmemiM_SDataAccept I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef ORIGINAL
module mkDelayWorker32B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo,
wsiS1_SThreadBusy,
wsiS1_SReset_n,
wsiS1_MReset_n,
wsiM1_MCmd,
wsiM1_MReqLast,
wsiM1_MBurstPrecise,
wsiM1_MBurstLength,
wsiM1_MData,
wsiM1_MByteEn,
wsiM1_MReqInfo,
wsiM1_SThreadBusy,
wsiM1_MReset_n,
wsiM1_SReset_n,
wmemiM_MCmd,
wmemiM_MReqLast,
wmemiM_MAddr,
wmemiM_MBurstLength,
wmemiM_MDataValid,
wmemiM_MDataLast,
wmemiM_MData,
wmemiM_MDataByteEn,
wmemiM_SResp,
wmemiM_SRespLast,
wmemiM_SData,
wmemiM_SCmdAccept,
wmemiM_SDataAccept,
wmemiM_MReset_n);
parameter [31 : 0] dlyCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [19 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS1_mCmd
input [2 : 0] wsiS1_MCmd;
// action method wsiS1_mReqLast
input wsiS1_MReqLast;
// action method wsiS1_mBurstPrecise
input wsiS1_MBurstPrecise;
// action method wsiS1_mBurstLength
input [11 : 0] wsiS1_MBurstLength;
// action method wsiS1_mData
input [255 : 0] wsiS1_MData;
// action method wsiS1_mByteEn
input [31 : 0] wsiS1_MByteEn;
// action method wsiS1_mReqInfo
input [7 : 0] wsiS1_MReqInfo;
// action method wsiS1_mDataInfo
// value method wsiS1_sThreadBusy
output wsiS1_SThreadBusy;
// value method wsiS1_sReset_n
output wsiS1_SReset_n;
// action method wsiS1_mReset_n
input wsiS1_MReset_n;
// value method wsiM1_mCmd
output [2 : 0] wsiM1_MCmd;
// value method wsiM1_mReqLast
output wsiM1_MReqLast;
// value method wsiM1_mBurstPrecise
output wsiM1_MBurstPrecise;
// value method wsiM1_mBurstLength
output [11 : 0] wsiM1_MBurstLength;
// value method wsiM1_mData
output [255 : 0] wsiM1_MData;
// value method wsiM1_mByteEn
output [31 : 0] wsiM1_MByteEn;
// value method wsiM1_mReqInfo
output [7 : 0] wsiM1_MReqInfo;
// value method wsiM1_mDataInfo
// action method wsiM1_sThreadBusy
input wsiM1_SThreadBusy;
// value method wsiM1_mReset_n
output wsiM1_MReset_n;
// action method wsiM1_sReset_n
input wsiM1_SReset_n;
// value method wmemiM_mCmd
output [2 : 0] wmemiM_MCmd;
// value method wmemiM_mReqLast
output wmemiM_MReqLast;
// value method wmemiM_mAddr
output [35 : 0] wmemiM_MAddr;
// value method wmemiM_mBurstLength
output [11 : 0] wmemiM_MBurstLength;
// value method wmemiM_mDataValid
output wmemiM_MDataValid;
// value method wmemiM_mDataLast
output wmemiM_MDataLast;
// value method wmemiM_mData
output [127 : 0] wmemiM_MData;
// value method wmemiM_mDataByteEn
output [15 : 0] wmemiM_MDataByteEn;
// action method wmemiM_sResp
input [1 : 0] wmemiM_SResp;
// action method wmemiM_sRespLast
input wmemiM_SRespLast;
// action method wmemiM_sData
input [127 : 0] wmemiM_SData;
// action method wmemiM_sCmdAccept
input wmemiM_SCmdAccept;
// action method wmemiM_sDataAccept
input wmemiM_SDataAccept;
// value method wmemiM_mReset_n
output wmemiM_MReset_n;
// signals for module outputs
wire [255 : 0] wsiM1_MData;
wire [127 : 0] wmemiM_MData;
wire [35 : 0] wmemiM_MAddr;
wire [31 : 0] wciS0_SData, wsiM1_MByteEn;
wire [15 : 0] wmemiM_MDataByteEn;
wire [11 : 0] wmemiM_MBurstLength, wsiM1_MBurstLength;
wire [7 : 0] wsiM1_MReqInfo;
wire [2 : 0] wmemiM_MCmd, wsiM1_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wmemiM_MDataLast,
wmemiM_MDataValid,
wmemiM_MReqLast,
wmemiM_MReset_n,
wsiM1_MBurstPrecise,
wsiM1_MReqLast,
wsiM1_MReset_n,
wsiS1_SReset_n,
wsiS1_SThreadBusy;
`else
`define NOT_EMPTY_delay.v
`include "delay_defs.v"
`endif
// inlined wires
wire [312 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [255 : 0] mesgWF_wDataIn$wget,
mesgWF_wDataOut$wget,
wsi_Es_mData_w$wget;
wire [145 : 0] wmemi_dhF_x_wire$wget;
wire [130 : 0] wmemi_wmemiResponse$wget;
wire [127 : 0] wmemi_Em_sData_w$wget;
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [59 : 0] wci_wciReq$wget;
wire [51 : 0] wmemi_reqF_x_wire$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mData_w$wget, wsi_Es_mByteEn_w$wget;
wire [24 : 0] dlyWordsStored_acc_v1$wget, dlyWordsStored_acc_v2$wget;
wire [19 : 0] wci_Es_mAddr_w$wget;
wire [15 : 0] dlyReadyToWrite_acc_v1$wget, dlyReadyToWrite_acc_v2$wget;
wire [11 : 0] wsi_Es_mBurstLength_w$wget;
wire [7 : 0] dlyReadCredit_acc_v1$wget,
dlyReadCredit_acc_v2$wget,
wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget;
wire [1 : 0] wmemi_Em_sResp_w$wget;
wire dlyReadCredit_acc_v1$whas,
dlyReadCredit_acc_v2$whas,
dlyReadyToWrite_acc_v1$whas,
dlyReadyToWrite_acc_v2$whas,
dlyWordsStored_acc_v1$whas,
dlyWordsStored_acc_v2$whas,
mesgWF_pwDequeue$whas,
mesgWF_pwEnqueue$whas,
mesgWF_wDataIn$whas,
mesgWF_wDataOut$whas,
wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wmemi_Em_sData_w$whas,
wmemi_Em_sRespLast_w$whas,
wmemi_Em_sResp_w$whas,
wmemi_dhF_dequeueing$whas,
wmemi_dhF_enqueueing$whas,
wmemi_dhF_x_wire$whas,
wmemi_operateD_1$wget,
wmemi_operateD_1$whas,
wmemi_peerIsReady_1$wget,
wmemi_peerIsReady_1$whas,
wmemi_reqF_dequeueing$whas,
wmemi_reqF_enqueueing$whas,
wmemi_reqF_x_wire$whas,
wmemi_sCmdAccept_w$wget,
wmemi_sCmdAccept_w$whas,
wmemi_sDataAccept_w$wget,
wmemi_sDataAccept_w$whas,
wmemi_wmemiResponse$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register bytesRead
reg [31 : 0] bytesRead;
wire [31 : 0] bytesRead$D_IN;
wire bytesRead$EN;
// register bytesThisMessage
reg [23 : 0] bytesThisMessage;
wire [23 : 0] bytesThisMessage$D_IN;
wire bytesThisMessage$EN;
// register bytesWritten
reg [31 : 0] bytesWritten;
wire [31 : 0] bytesWritten$D_IN;
wire bytesWritten$EN;
// register cyclesPassed
reg [31 : 0] cyclesPassed;
wire [31 : 0] cyclesPassed$D_IN;
wire cyclesPassed$EN;
// register dlyCtrl
reg [31 : 0] dlyCtrl;
wire [31 : 0] dlyCtrl$D_IN;
wire dlyCtrl$EN;
// register dlyHoldoffBytes
reg [31 : 0] dlyHoldoffBytes;
wire [31 : 0] dlyHoldoffBytes$D_IN;
wire dlyHoldoffBytes$EN;
// register dlyHoldoffCycles
reg [31 : 0] dlyHoldoffCycles;
wire [31 : 0] dlyHoldoffCycles$D_IN;
wire dlyHoldoffCycles$EN;
// register dlyRAG
reg [22 : 0] dlyRAG;
wire [22 : 0] dlyRAG$D_IN;
wire dlyRAG$EN;
// register dlyRdOpOther
reg [31 : 0] dlyRdOpOther;
wire [31 : 0] dlyRdOpOther$D_IN;
wire dlyRdOpOther$EN;
// register dlyRdOpZero
reg [31 : 0] dlyRdOpZero;
wire [31 : 0] dlyRdOpZero$D_IN;
wire dlyRdOpZero$EN;
// register dlyReadCredit_value
reg [7 : 0] dlyReadCredit_value;
wire [7 : 0] dlyReadCredit_value$D_IN;
wire dlyReadCredit_value$EN;
// register dlyReadyToWrite_value
reg [15 : 0] dlyReadyToWrite_value;
wire [15 : 0] dlyReadyToWrite_value$D_IN;
wire dlyReadyToWrite_value$EN;
// register dlyWAG
reg [22 : 0] dlyWAG;
wire [22 : 0] dlyWAG$D_IN;
wire dlyWAG$EN;
// register dlyWordsStored_value
reg [24 : 0] dlyWordsStored_value;
wire [24 : 0] dlyWordsStored_value$D_IN;
wire dlyWordsStored_value$EN;
// register mesgLengthSoFar
reg [13 : 0] mesgLengthSoFar;
wire [13 : 0] mesgLengthSoFar$D_IN;
wire mesgLengthSoFar$EN;
// register mesgRdCount
reg [31 : 0] mesgRdCount;
wire [31 : 0] mesgRdCount$D_IN;
wire mesgRdCount$EN;
// register mesgWF_rCache
reg [269 : 0] mesgWF_rCache;
wire [269 : 0] mesgWF_rCache$D_IN;
wire mesgWF_rCache$EN;
// register mesgWF_rRdPtr
reg [12 : 0] mesgWF_rRdPtr;
wire [12 : 0] mesgWF_rRdPtr$D_IN;
wire mesgWF_rRdPtr$EN;
// register mesgWF_rWrPtr
reg [12 : 0] mesgWF_rWrPtr;
wire [12 : 0] mesgWF_rWrPtr$D_IN;
wire mesgWF_rWrPtr$EN;
// register mesgWtCount
reg [31 : 0] mesgWtCount;
wire [31 : 0] mesgWtCount$D_IN;
wire mesgWtCount$EN;
// register rdSerAddr
reg [31 : 0] rdSerAddr;
wire [31 : 0] rdSerAddr$D_IN;
wire rdSerAddr$EN;
// register rdSerEmpty
reg rdSerEmpty;
wire rdSerEmpty$D_IN, rdSerEmpty$EN;
// register rdSerMeta
reg [31 : 0] rdSerMeta;
wire [31 : 0] rdSerMeta$D_IN;
wire rdSerMeta$EN;
// register rdSerPos
reg [1 : 0] rdSerPos;
wire [1 : 0] rdSerPos$D_IN;
wire rdSerPos$EN;
// register rdSerStage
reg [31 : 0] rdSerStage;
wire [31 : 0] rdSerStage$D_IN;
wire rdSerStage$EN;
// register rdSerStage_1
reg [31 : 0] rdSerStage_1;
wire [31 : 0] rdSerStage_1$D_IN;
wire rdSerStage_1$EN;
// register rdSerStage_2
reg [31 : 0] rdSerStage_2;
wire [31 : 0] rdSerStage_2$D_IN;
wire rdSerStage_2$EN;
// register rdSerStage_3
reg [31 : 0] rdSerStage_3;
wire [31 : 0] rdSerStage_3$D_IN;
wire rdSerStage_3$EN;
// register rdSerUnroll
reg [15 : 0] rdSerUnroll;
wire [15 : 0] rdSerUnroll$D_IN;
wire rdSerUnroll$EN;
// register rdSyncWord
reg rdSyncWord;
reg rdSyncWord$D_IN;
wire rdSyncWord$EN;
// register readMeta
reg [31 : 0] readMeta;
wire [31 : 0] readMeta$D_IN;
wire readMeta$EN;
// register tog50
reg tog50;
wire tog50$D_IN, tog50$EN;
// register unrollCnt
reg [15 : 0] unrollCnt;
wire [15 : 0] unrollCnt$D_IN;
wire unrollCnt$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wmemiRdReq
reg [31 : 0] wmemiRdReq;
wire [31 : 0] wmemiRdReq$D_IN;
wire wmemiRdReq$EN;
// register wmemiRdResp1
reg [31 : 0] wmemiRdResp1;
wire [31 : 0] wmemiRdResp1$D_IN;
wire wmemiRdResp1$EN;
// register wmemiRdResp2
reg [31 : 0] wmemiRdResp2;
wire [31 : 0] wmemiRdResp2$D_IN;
wire wmemiRdResp2$EN;
// register wmemiWrReq
reg [31 : 0] wmemiWrReq;
wire [31 : 0] wmemiWrReq$D_IN;
wire wmemiWrReq$EN;
// register wmemi_busyWithMessage
reg wmemi_busyWithMessage;
wire wmemi_busyWithMessage$D_IN, wmemi_busyWithMessage$EN;
// register wmemi_dhF_c_r
reg [1 : 0] wmemi_dhF_c_r;
wire [1 : 0] wmemi_dhF_c_r$D_IN;
wire wmemi_dhF_c_r$EN;
// register wmemi_dhF_q_0
reg [145 : 0] wmemi_dhF_q_0;
reg [145 : 0] wmemi_dhF_q_0$D_IN;
wire wmemi_dhF_q_0$EN;
// register wmemi_dhF_q_1
reg [145 : 0] wmemi_dhF_q_1;
reg [145 : 0] wmemi_dhF_q_1$D_IN;
wire wmemi_dhF_q_1$EN;
// register wmemi_errorSticky
reg wmemi_errorSticky;
wire wmemi_errorSticky$D_IN, wmemi_errorSticky$EN;
// register wmemi_operateD
reg wmemi_operateD;
wire wmemi_operateD$D_IN, wmemi_operateD$EN;
// register wmemi_peerIsReady
reg wmemi_peerIsReady;
wire wmemi_peerIsReady$D_IN, wmemi_peerIsReady$EN;
// register wmemi_reqF_c_r
reg [1 : 0] wmemi_reqF_c_r;
wire [1 : 0] wmemi_reqF_c_r$D_IN;
wire wmemi_reqF_c_r$EN;
// register wmemi_reqF_q_0
reg [51 : 0] wmemi_reqF_q_0;
reg [51 : 0] wmemi_reqF_q_0$D_IN;
wire wmemi_reqF_q_0$EN;
// register wmemi_reqF_q_1
reg [51 : 0] wmemi_reqF_q_1;
reg [51 : 0] wmemi_reqF_q_1$D_IN;
wire wmemi_reqF_q_1$EN;
// register wmemi_statusR
reg [7 : 0] wmemi_statusR;
wire [7 : 0] wmemi_statusR$D_IN;
wire wmemi_statusR$EN;
// register wmemi_trafficSticky
reg wmemi_trafficSticky;
wire wmemi_trafficSticky$D_IN, wmemi_trafficSticky$EN;
// register wrtSerAddr
reg [31 : 0] wrtSerAddr;
wire [31 : 0] wrtSerAddr$D_IN;
wire wrtSerAddr$EN;
// register wrtSerPos
reg [1 : 0] wrtSerPos;
wire [1 : 0] wrtSerPos$D_IN;
wire wrtSerPos$EN;
// register wrtSerStage
reg [31 : 0] wrtSerStage;
wire [31 : 0] wrtSerStage$D_IN;
wire wrtSerStage$EN;
// register wrtSerStage_1
reg [31 : 0] wrtSerStage_1;
wire [31 : 0] wrtSerStage_1$D_IN;
wire wrtSerStage_1$EN;
// register wrtSerStage_2
reg [31 : 0] wrtSerStage_2;
wire [31 : 0] wrtSerStage_2$D_IN;
wire wrtSerStage_2$EN;
// register wrtSerStage_3
reg [31 : 0] wrtSerStage_3;
wire [31 : 0] wrtSerStage_3$D_IN;
wire wrtSerStage_3$EN;
// register wrtSerUnroll
reg [15 : 0] wrtSerUnroll;
wire [15 : 0] wrtSerUnroll$D_IN;
wire wrtSerUnroll$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [312 : 0] wsiM_reqFifo_q_0;
reg [312 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [312 : 0] wsiM_reqFifo_q_1;
reg [312 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule mesgRF
wire [255 : 0] mesgRF$D_IN, mesgRF$D_OUT;
wire mesgRF$CLR, mesgRF$DEQ, mesgRF$EMPTY_N, mesgRF$ENQ, mesgRF$FULL_N;
// ports of submodule mesgWF_memory
wire [255 : 0] mesgWF_memory$DIA, mesgWF_memory$DIB, mesgWF_memory$DOB;
wire [11 : 0] mesgWF_memory$ADDRA, mesgWF_memory$ADDRB;
wire mesgWF_memory$ENA,
mesgWF_memory$ENB,
mesgWF_memory$WEA,
mesgWF_memory$WEB;
// ports of submodule metaRF
reg [31 : 0] metaRF$D_IN;
wire [31 : 0] metaRF$D_OUT;
wire metaRF$CLR, metaRF$DEQ, metaRF$EMPTY_N, metaRF$ENQ, metaRF$FULL_N;
// ports of submodule metaWF
wire [31 : 0] metaWF$D_IN, metaWF$D_OUT;
wire metaWF$CLR, metaWF$DEQ, metaWF$EMPTY_N, metaWF$ENQ, metaWF$FULL_N;
// ports of submodule wci_isReset
wire wci_isReset$VAL;
// ports of submodule wci_reqF
wire [59 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wide16Fa
wire [127 : 0] wide16Fa$D_IN, wide16Fa$D_OUT;
wire wide16Fa$CLR,
wide16Fa$DEQ,
wide16Fa$EMPTY_N,
wide16Fa$ENQ,
wide16Fa$FULL_N;
// ports of submodule wide16Fb
wire [127 : 0] wide16Fb$D_IN, wide16Fb$D_OUT;
wire wide16Fb$CLR,
wide16Fb$DEQ,
wide16Fb$EMPTY_N,
wide16Fb$ENQ,
wide16Fb$FULL_N;
// ports of submodule wide16Fc
wire [127 : 0] wide16Fc$D_IN, wide16Fc$D_OUT;
wire wide16Fc$CLR,
wide16Fc$DEQ,
wide16Fc$EMPTY_N,
wide16Fc$ENQ,
wide16Fc$FULL_N;
// ports of submodule wmemi_isReset
wire wmemi_isReset$VAL;
// ports of submodule wmemi_respF
wire [130 : 0] wmemi_respF$D_IN, wmemi_respF$D_OUT;
wire wmemi_respF$CLR,
wmemi_respF$DEQ,
wmemi_respF$EMPTY_N,
wmemi_respF$ENQ,
wmemi_respF$FULL_N;
// ports of submodule wsiM_isReset
wire wsiM_isReset$VAL;
// ports of submodule wsiS_isReset
wire wsiS_isReset$VAL;
// ports of submodule wsiS_reqFifo
wire [312 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_cycles_passed_count,
CAN_FIRE_RL_delay_Fb2Fc,
CAN_FIRE_RL_delay_read_req,
CAN_FIRE_RL_delay_read_resp,
CAN_FIRE_RL_delay_write_req,
CAN_FIRE_RL_dlyReadCredit_accumulate,
CAN_FIRE_RL_dlyReadyToWrite_accumulate,
CAN_FIRE_RL_dlyWordsStored_accumulate,
CAN_FIRE_RL_mesgWF_portA,
CAN_FIRE_RL_mesgWF_portB,
CAN_FIRE_RL_mesgWF_portB_read_data,
CAN_FIRE_RL_operating_actions,
CAN_FIRE_RL_rdSer_begin,
CAN_FIRE_RL_rdSer_body,
CAN_FIRE_RL_rdSer_sync,
CAN_FIRE_RL_wci_Es_doAlways_Req,
CAN_FIRE_RL_wci_cfrd,
CAN_FIRE_RL_wci_cfwr,
CAN_FIRE_RL_wci_ctlAckReg__dreg_update,
CAN_FIRE_RL_wci_ctl_op_complete,
CAN_FIRE_RL_wci_ctl_op_start,
CAN_FIRE_RL_wci_ctrl_EiI,
CAN_FIRE_RL_wci_ctrl_IsO,
CAN_FIRE_RL_wci_ctrl_OrE,
CAN_FIRE_RL_wci_reqF__updateLevelCounter,
CAN_FIRE_RL_wci_reqF_enq,
CAN_FIRE_RL_wci_request_decode,
CAN_FIRE_RL_wci_respF_both,
CAN_FIRE_RL_wci_respF_decCtr,
CAN_FIRE_RL_wci_respF_deq,
CAN_FIRE_RL_wci_respF_incCtr,
CAN_FIRE_RL_wci_sFlagReg__dreg_update,
CAN_FIRE_RL_wci_sThreadBusy_reg,
CAN_FIRE_RL_wmemi_Em_doAlways,
CAN_FIRE_RL_wmemi_dhF_both,
CAN_FIRE_RL_wmemi_dhF_decCtr,
CAN_FIRE_RL_wmemi_dhF_deq,
CAN_FIRE_RL_wmemi_dhF_incCtr,
CAN_FIRE_RL_wmemi_operateD__dreg_update,
CAN_FIRE_RL_wmemi_peerIsReady__dreg_update,
CAN_FIRE_RL_wmemi_reqF_both,
CAN_FIRE_RL_wmemi_reqF_decCtr,
CAN_FIRE_RL_wmemi_reqF_deq,
CAN_FIRE_RL_wmemi_reqF_incCtr,
CAN_FIRE_RL_wmemi_respAdvance,
CAN_FIRE_RL_wmemi_update_statusR,
CAN_FIRE_RL_wmrd_mesgBegin,
CAN_FIRE_RL_wmrd_mesgBodyResponse,
CAN_FIRE_RL_wmwt_mesg_ingress,
CAN_FIRE_RL_wrtSer_begin,
CAN_FIRE_RL_wrtSer_body,
CAN_FIRE_RL_wsiM_ext_status_assign,
CAN_FIRE_RL_wsiM_inc_tBusyCount,
CAN_FIRE_RL_wsiM_operateD__dreg_update,
CAN_FIRE_RL_wsiM_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiM_reqFifo_both,
CAN_FIRE_RL_wsiM_reqFifo_decCtr,
CAN_FIRE_RL_wsiM_reqFifo_deq,
CAN_FIRE_RL_wsiM_reqFifo_incCtr,
CAN_FIRE_RL_wsiM_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_update_statusR,
CAN_FIRE_RL_wsiS_backpressure,
CAN_FIRE_RL_wsiS_ext_status_assign,
CAN_FIRE_RL_wsiS_inc_tBusyCount,
CAN_FIRE_RL_wsiS_operateD__dreg_update,
CAN_FIRE_RL_wsiS_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsiS_reqFifo_enq,
CAN_FIRE_RL_wsiS_reqFifo_reset,
CAN_FIRE_RL_wsiS_update_statusR,
CAN_FIRE_RL_wsi_Es_doAlways,
CAN_FIRE_RL_wsipass_doMessagePush,
CAN_FIRE_wciS0_mAddr,
CAN_FIRE_wciS0_mAddrSpace,
CAN_FIRE_wciS0_mByteEn,
CAN_FIRE_wciS0_mCmd,
CAN_FIRE_wciS0_mData,
CAN_FIRE_wciS0_mFlag,
CAN_FIRE_wmemiM_sCmdAccept,
CAN_FIRE_wmemiM_sData,
CAN_FIRE_wmemiM_sDataAccept,
CAN_FIRE_wmemiM_sResp,
CAN_FIRE_wmemiM_sRespLast,
CAN_FIRE_wsiM1_sReset_n,
CAN_FIRE_wsiM1_sThreadBusy,
CAN_FIRE_wsiS1_mBurstLength,
CAN_FIRE_wsiS1_mBurstPrecise,
CAN_FIRE_wsiS1_mByteEn,
CAN_FIRE_wsiS1_mCmd,
CAN_FIRE_wsiS1_mData,
CAN_FIRE_wsiS1_mDataInfo,
CAN_FIRE_wsiS1_mReqInfo,
CAN_FIRE_wsiS1_mReqLast,
CAN_FIRE_wsiS1_mReset_n,
WILL_FIRE_RL_cycles_passed_count,
WILL_FIRE_RL_delay_Fb2Fc,
WILL_FIRE_RL_delay_read_req,
WILL_FIRE_RL_delay_read_resp,
WILL_FIRE_RL_delay_write_req,
WILL_FIRE_RL_dlyReadCredit_accumulate,
WILL_FIRE_RL_dlyReadyToWrite_accumulate,
WILL_FIRE_RL_dlyWordsStored_accumulate,
WILL_FIRE_RL_mesgWF_portA,
WILL_FIRE_RL_mesgWF_portB,
WILL_FIRE_RL_mesgWF_portB_read_data,
WILL_FIRE_RL_operating_actions,
WILL_FIRE_RL_rdSer_begin,
WILL_FIRE_RL_rdSer_body,
WILL_FIRE_RL_rdSer_sync,
WILL_FIRE_RL_wci_Es_doAlways_Req,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctlAckReg__dreg_update,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_reqF__updateLevelCounter,
WILL_FIRE_RL_wci_reqF_enq,
WILL_FIRE_RL_wci_request_decode,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_deq,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wci_sFlagReg__dreg_update,
WILL_FIRE_RL_wci_sThreadBusy_reg,
WILL_FIRE_RL_wmemi_Em_doAlways,
WILL_FIRE_RL_wmemi_dhF_both,
WILL_FIRE_RL_wmemi_dhF_decCtr,
WILL_FIRE_RL_wmemi_dhF_deq,
WILL_FIRE_RL_wmemi_dhF_incCtr,
WILL_FIRE_RL_wmemi_operateD__dreg_update,
WILL_FIRE_RL_wmemi_peerIsReady__dreg_update,
WILL_FIRE_RL_wmemi_reqF_both,
WILL_FIRE_RL_wmemi_reqF_decCtr,
WILL_FIRE_RL_wmemi_reqF_deq,
WILL_FIRE_RL_wmemi_reqF_incCtr,
WILL_FIRE_RL_wmemi_respAdvance,
WILL_FIRE_RL_wmemi_update_statusR,
WILL_FIRE_RL_wmrd_mesgBegin,
WILL_FIRE_RL_wmrd_mesgBodyResponse,
WILL_FIRE_RL_wmwt_mesg_ingress,
WILL_FIRE_RL_wrtSer_begin,
WILL_FIRE_RL_wrtSer_body,
WILL_FIRE_RL_wsiM_ext_status_assign,
WILL_FIRE_RL_wsiM_inc_tBusyCount,
WILL_FIRE_RL_wsiM_operateD__dreg_update,
WILL_FIRE_RL_wsiM_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiM_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_update_statusR,
WILL_FIRE_RL_wsiS_backpressure,
WILL_FIRE_RL_wsiS_ext_status_assign,
WILL_FIRE_RL_wsiS_inc_tBusyCount,
WILL_FIRE_RL_wsiS_operateD__dreg_update,
WILL_FIRE_RL_wsiS_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsiS_update_statusR,
WILL_FIRE_RL_wsi_Es_doAlways,
WILL_FIRE_RL_wsipass_doMessagePush,
WILL_FIRE_wciS0_mAddr,
WILL_FIRE_wciS0_mAddrSpace,
WILL_FIRE_wciS0_mByteEn,
WILL_FIRE_wciS0_mCmd,
WILL_FIRE_wciS0_mData,
WILL_FIRE_wciS0_mFlag,
WILL_FIRE_wmemiM_sCmdAccept,
WILL_FIRE_wmemiM_sData,
WILL_FIRE_wmemiM_sDataAccept,
WILL_FIRE_wmemiM_sResp,
WILL_FIRE_wmemiM_sRespLast,
WILL_FIRE_wsiM1_sReset_n,
WILL_FIRE_wsiM1_sThreadBusy,
WILL_FIRE_wsiS1_mBurstLength,
WILL_FIRE_wsiS1_mBurstPrecise,
WILL_FIRE_wsiS1_mByteEn,
WILL_FIRE_wsiS1_mCmd,
WILL_FIRE_wsiS1_mData,
WILL_FIRE_wsiS1_mDataInfo,
WILL_FIRE_wsiS1_mReqInfo,
WILL_FIRE_wsiS1_mReqLast,
WILL_FIRE_wsiS1_mReset_n;
// inputs to muxes for submodule ports
reg [127 : 0] MUX_wide16Fa$enq_1__VAL_1, MUX_wide16Fa$enq_1__VAL_2;
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [312 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [145 : 0] MUX_wmemi_dhF_q_0$write_1__VAL_1,
MUX_wmemi_dhF_q_0$write_1__VAL_2,
MUX_wmemi_dhF_q_1$write_1__VAL_1;
wire [51 : 0] MUX_wmemi_reqF_q_0$write_1__VAL_1,
MUX_wmemi_reqF_q_0$write_1__VAL_2,
MUX_wmemi_reqF_q_1$write_1__VAL_1,
MUX_wmemi_reqF_x_wire$wset_1__VAL_1,
MUX_wmemi_reqF_x_wire$wset_1__VAL_2;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [31 : 0] MUX_mesgRdCount$write_1__VAL_1,
MUX_mesgWtCount$write_1__VAL_1;
wire [24 : 0] MUX_dlyWordsStored_value$write_1__VAL_2;
wire [22 : 0] MUX_dlyRAG$write_1__VAL_1, MUX_dlyWAG$write_1__VAL_1;
wire [15 : 0] MUX_dlyReadyToWrite_value$write_1__VAL_2,
MUX_rdSerUnroll$write_1__VAL_2,
MUX_unrollCnt$write_1__VAL_1,
MUX_unrollCnt$write_1__VAL_2,
MUX_wrtSerUnroll$write_1__VAL_1;
wire [7 : 0] MUX_dlyReadCredit_value$write_1__VAL_2;
wire [1 : 0] MUX_rdSerPos$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wmemi_dhF_c_r$write_1__VAL_1,
MUX_wmemi_dhF_c_r$write_1__VAL_2,
MUX_wmemi_reqF_c_r$write_1__VAL_1,
MUX_wmemi_reqF_c_r$write_1__VAL_2,
MUX_wrtSerPos$write_1__VAL_1,
MUX_wrtSerPos$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_mesgRdCount$write_1__SEL_1,
MUX_mesgWtCount$write_1__SEL_1,
MUX_rdSerEmpty$write_1__PSEL_1,
MUX_rdSerEmpty$write_1__SEL_1,
MUX_rdSyncWord$write_1__VAL_1,
MUX_rdSyncWord$write_1__VAL_2,
MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wide16Fa$enq_1__SEL_1,
MUX_wmemi_dhF_q_0$write_1__SEL_2,
MUX_wmemi_dhF_q_1$write_1__SEL_2,
MUX_wmemi_reqF_q_0$write_1__SEL_2,
MUX_wmemi_reqF_q_1$write_1__SEL_2,
MUX_wrtSerStage$write_1__SEL_1,
MUX_wrtSerStage_1$write_1__SEL_1,
MUX_wrtSerStage_2$write_1__SEL_1,
MUX_wrtSerStage_3$write_1__SEL_1,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h22096, v__h2670, v__h2817, v__h3716;
reg [31 : 0] x_data__h22228;
reg CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1,
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q2;
wire [255 : 0] x__h15073, x__h17993;
wire [127 : 0] IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_mesgWF_w_ETC___d423,
IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_metaWF_f_ETC___d446,
x__h18132,
x__h18163,
x__h18794,
x__h18821;
wire [35 : 0] addr__h19478, addr__h19647;
wire [31 : 0] delayStatus__h21797,
rdat__h22255,
rdat__h22261,
rdat__h22267,
rdat__h22273,
rdat__h22397,
rdat__h22411,
rdat__h22419,
rdat__h22425,
rdat__h22439,
rdat__h22447,
rdat__h22453,
rdat__h22459,
rdat__h22465,
rdat__h22471,
rdat__h22482,
rdat__h22493,
rdat__h22504,
rdat__h22525,
rdat__h22580,
rdat__h22589,
rdat__h22598,
rdat__h22607,
v__h20254,
x_byteEn__h19977;
wire [26 : 0] x__h19536, x__h19692;
wire [23 : 0] btm__h17027, x__h22277;
wire [13 : 0] mesgLengthSoFar_05_PLUS_1___d985;
wire [12 : 0] x__h14965;
wire [11 : 0] x_burstLength__h19976;
wire [1 : 0] wrtSerPos_80_PLUS_1___d984;
wire IF_wrtSerPos_80_EQ_0_81_OR_wrtSerPos_80_EQ_1_8_ETC___d399,
NOT_mesgWF_rRdPtr_69_EQ_mesgWF_rWrPtr_71_74___d175,
NOT_mesgWF_rRdPtr_69_PLUS_2048_70_EQ_mesgWF_rW_ETC___d173,
NOT_wrtSerPos_80_EQ_3_87_88_AND_NOT_metaWF_fir_ETC___d434,
bytesWritten_6_ULT_dlyHoldoffBytes_6___d908,
cyclesPassed_54_ULT_dlyHoldoffCycles_8___d903,
dlyWordsStored_value_26_SLE_0_49_OR_bytesWritt_ETC___d164,
dlyWordsStored_value_26_SLE_0___d909,
dlyWordsStored_value_26_SLT_8388608___d165,
mesgRF_i_notFull__74_AND_NOT_rdSerEmpty_75_76__ETC___d285,
metaRF_i_notFull__18_AND_NOT_rdSerEmpty_75_76__ETC___d319,
wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d352,
wsiS_reqFifo_notFull__05_AND_wsiS_burstKind_85_ETC___d725;
// action method wciS0_mCmd
assign CAN_FIRE_wciS0_mCmd = 1'd1 ;
assign WILL_FIRE_wciS0_mCmd = 1'd1 ;
// action method wciS0_mAddrSpace
assign CAN_FIRE_wciS0_mAddrSpace = 1'd1 ;
assign WILL_FIRE_wciS0_mAddrSpace = 1'd1 ;
// action method wciS0_mByteEn
assign CAN_FIRE_wciS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wciS0_mByteEn = 1'd1 ;
// action method wciS0_mAddr
assign CAN_FIRE_wciS0_mAddr = 1'd1 ;
assign WILL_FIRE_wciS0_mAddr = 1'd1 ;
// action method wciS0_mData
assign CAN_FIRE_wciS0_mData = 1'd1 ;
assign WILL_FIRE_wciS0_mData = 1'd1 ;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy = wci_reqF_countReg > 2'd1 || wci_isReset$VAL ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// action method wciS0_mFlag
assign CAN_FIRE_wciS0_mFlag = 1'd1 ;
assign WILL_FIRE_wciS0_mFlag = 1'd1 ;
// action method wsiS1_mCmd
assign CAN_FIRE_wsiS1_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS1_mCmd = 1'd1 ;
// action method wsiS1_mReqLast
assign CAN_FIRE_wsiS1_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ;
// action method wsiS1_mBurstPrecise
assign CAN_FIRE_wsiS1_mBurstPrecise = 1'd1 ;
assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ;
// action method wsiS1_mBurstLength
assign CAN_FIRE_wsiS1_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS1_mBurstLength = 1'd1 ;
// action method wsiS1_mData
assign CAN_FIRE_wsiS1_mData = 1'd1 ;
assign WILL_FIRE_wsiS1_mData = 1'd1 ;
// action method wsiS1_mByteEn
assign CAN_FIRE_wsiS1_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS1_mByteEn = 1'd1 ;
// action method wsiS1_mReqInfo
assign CAN_FIRE_wsiS1_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS1_mReqInfo = 1'd1 ;
// action method wsiS1_mDataInfo
assign CAN_FIRE_wsiS1_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS1_mDataInfo = 1'd1 ;
// value method wsiS1_sThreadBusy
assign wsiS1_SThreadBusy =
!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget ;
// value method wsiS1_sReset_n
assign wsiS1_SReset_n = !wsiS_isReset$VAL && wsiS_operateD ;
// action method wsiS1_mReset_n
assign CAN_FIRE_wsiS1_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ;
// value method wsiM1_mCmd
assign wsiM1_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[312:310] ;
// value method wsiM1_mReqLast
assign wsiM1_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[309] ;
// value method wsiM1_mBurstPrecise
assign wsiM1_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[308] ;
// value method wsiM1_mBurstLength
assign wsiM1_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[307:296] ;
// value method wsiM1_mData
assign wsiM1_MData = wsiM_reqFifo_q_0[295:40] ;
// value method wsiM1_mByteEn
assign wsiM1_MByteEn = wsiM_reqFifo_q_0[39:8] ;
// value method wsiM1_mReqInfo
assign wsiM1_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// action method wsiM1_sThreadBusy
assign CAN_FIRE_wsiM1_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ;
// value method wsiM1_mReset_n
assign wsiM1_MReset_n = !wsiM_isReset$VAL && wsiM_operateD ;
// action method wsiM1_sReset_n
assign CAN_FIRE_wsiM1_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ;
// value method wmemiM_mCmd
assign wmemiM_MCmd = wmemi_reqF_q_0[51:49] ;
// value method wmemiM_mReqLast
assign wmemiM_MReqLast = wmemi_reqF_q_0[48] ;
// value method wmemiM_mAddr
assign wmemiM_MAddr = wmemi_reqF_q_0[47:12] ;
// value method wmemiM_mBurstLength
assign wmemiM_MBurstLength = wmemi_reqF_q_0[11:0] ;
// value method wmemiM_mDataValid
assign wmemiM_MDataValid = wmemi_dhF_q_0[145] ;
// value method wmemiM_mDataLast
assign wmemiM_MDataLast = wmemi_dhF_q_0[144] ;
// value method wmemiM_mData
assign wmemiM_MData = wmemi_dhF_q_0[143:16] ;
// value method wmemiM_mDataByteEn
assign wmemiM_MDataByteEn = wmemi_dhF_q_0[15:0] ;
// action method wmemiM_sResp
assign CAN_FIRE_wmemiM_sResp = 1'd1 ;
assign WILL_FIRE_wmemiM_sResp = 1'd1 ;
// action method wmemiM_sRespLast
assign CAN_FIRE_wmemiM_sRespLast = 1'd1 ;
assign WILL_FIRE_wmemiM_sRespLast = wmemiM_SRespLast ;
// action method wmemiM_sData
assign CAN_FIRE_wmemiM_sData = 1'd1 ;
assign WILL_FIRE_wmemiM_sData = 1'd1 ;
// action method wmemiM_sCmdAccept
assign CAN_FIRE_wmemiM_sCmdAccept = 1'd1 ;
assign WILL_FIRE_wmemiM_sCmdAccept = wmemiM_SCmdAccept ;
// action method wmemiM_sDataAccept
assign CAN_FIRE_wmemiM_sDataAccept = 1'd1 ;
assign WILL_FIRE_wmemiM_sDataAccept = wmemiM_SDataAccept ;
// value method wmemiM_mReset_n
assign wmemiM_MReset_n = !wmemi_isReset$VAL && wmemi_operateD ;
// submodule mesgRF
SizedFIFO #(.p1width(32'd256),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) mesgRF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(mesgRF$D_IN),
.ENQ(mesgRF$ENQ),
.DEQ(mesgRF$DEQ),
.CLR(mesgRF$CLR),
.D_OUT(mesgRF$D_OUT),
.FULL_N(mesgRF$FULL_N),
.EMPTY_N(mesgRF$EMPTY_N));
// submodule mesgWF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd12),
.DATA_WIDTH(32'd256),
.MEMSIZE(13'd4096)) mesgWF_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(mesgWF_memory$ADDRA),
.ADDRB(mesgWF_memory$ADDRB),
.DIA(mesgWF_memory$DIA),
.DIB(mesgWF_memory$DIB),
.WEA(mesgWF_memory$WEA),
.WEB(mesgWF_memory$WEB),
.ENA(mesgWF_memory$ENA),
.ENB(mesgWF_memory$ENB),
.DOA(),
.DOB(mesgWF_memory$DOB));
// submodule metaRF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) metaRF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaRF$D_IN),
.ENQ(metaRF$ENQ),
.DEQ(metaRF$DEQ),
.CLR(metaRF$CLR),
.D_OUT(metaRF$D_OUT),
.FULL_N(metaRF$FULL_N),
.EMPTY_N(metaRF$EMPTY_N));
// submodule metaWF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) metaWF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(metaWF$D_IN),
.ENQ(metaWF$ENQ),
.DEQ(metaWF$DEQ),
.CLR(metaWF$CLR),
.D_OUT(metaWF$D_OUT),
.FULL_N(metaWF$FULL_N),
.EMPTY_N(metaWF$EMPTY_N));
// submodule wci_isReset
ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset$VAL));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd60),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wide16Fa
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fa(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fa$D_IN),
.ENQ(wide16Fa$ENQ),
.DEQ(wide16Fa$DEQ),
.CLR(wide16Fa$CLR),
.D_OUT(wide16Fa$D_OUT),
.FULL_N(wide16Fa$FULL_N),
.EMPTY_N(wide16Fa$EMPTY_N));
// submodule wide16Fb
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fb(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fb$D_IN),
.ENQ(wide16Fb$ENQ),
.DEQ(wide16Fb$DEQ),
.CLR(wide16Fb$CLR),
.D_OUT(wide16Fb$D_OUT),
.FULL_N(wide16Fb$FULL_N),
.EMPTY_N(wide16Fb$EMPTY_N));
// submodule wide16Fc
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd15),
.p3cntr_width(32'd4),
.guarded(32'd1)) wide16Fc(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wide16Fc$D_IN),
.ENQ(wide16Fc$ENQ),
.DEQ(wide16Fc$DEQ),
.CLR(wide16Fc$CLR),
.D_OUT(wide16Fc$D_OUT),
.FULL_N(wide16Fc$FULL_N),
.EMPTY_N(wide16Fc$EMPTY_N));
// submodule wmemi_isReset
ResetToBool wmemi_isReset(.RST(wciS0_MReset_n), .VAL(wmemi_isReset$VAL));
// submodule wmemi_respF
FIFO2 #(.width(32'd131),
.guarded(32'd1)) wmemi_respF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmemi_respF$D_IN),
.ENQ(wmemi_respF$ENQ),
.DEQ(wmemi_respF$DEQ),
.CLR(wmemi_respF$CLR),
.D_OUT(wmemi_respF$D_OUT),
.FULL_N(wmemi_respF$FULL_N),
.EMPTY_N(wmemi_respF$EMPTY_N));
// submodule wsiM_isReset
ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset$VAL));
// submodule wsiS_isReset
ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset$VAL));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd313),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// rule RL_wsiS_backpressure
assign CAN_FIRE_RL_wsiS_backpressure =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign WILL_FIRE_RL_wsiS_backpressure = CAN_FIRE_RL_wsiS_backpressure ;
// rule RL_wci_request_decode
assign CAN_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
assign WILL_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
// rule RL_wci_ctl_op_start
assign CAN_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas ;
assign WILL_FIRE_RL_wci_ctl_op_start =
CAN_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign CAN_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ;
// rule RL_wci_ctrl_OrE
assign CAN_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ;
// rule RL_wmemi_update_statusR
assign CAN_FIRE_RL_wmemi_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wmemi_update_statusR = 1'd1 ;
// rule RL_wci_respF_deq
assign CAN_FIRE_RL_wci_respF_deq = 1'd1 ;
assign WILL_FIRE_RL_wci_respF_deq = 1'd1 ;
// rule RL_wci_sThreadBusy_reg
assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
// rule RL_wci_sFlagReg__dreg_update
assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
// rule RL_wsi_Es_doAlways
assign CAN_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
// rule RL_wsiS_update_statusR
assign CAN_FIRE_RL_wsiS_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiS_update_statusR = 1'd1 ;
// rule RL_wsiS_ext_status_assign
assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
// rule RL_wsiS_inc_tBusyCount
assign CAN_FIRE_RL_wsiS_inc_tBusyCount =
wsiS_operateD && wsiS_peerIsReady &&
(!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget) ;
assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// rule RL_wsiS_reqFifo_enq
assign CAN_FIRE_RL_wsiS_reqFifo_enq =
wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[312:310] == 3'd1 ;
assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// rule RL_wsiS_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiM_update_statusR
assign CAN_FIRE_RL_wsiM_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiM_update_statusR = 1'd1 ;
// rule RL_wsiM_ext_status_assign
assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wsiM_inc_tBusyCount
assign CAN_FIRE_RL_wsiM_inc_tBusyCount =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// rule RL_wsiM_reqFifo_deq
assign CAN_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_sThreadBusy_reg
assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
// rule RL_wsiM_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wmrd_mesgBodyResponse
assign CAN_FIRE_RL_wmrd_mesgBodyResponse =
wsiM_reqFifo_c_r != 2'd2 && mesgRF$EMPTY_N &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
unrollCnt != 16'd0 ;
assign WILL_FIRE_RL_wmrd_mesgBodyResponse =
CAN_FIRE_RL_wmrd_mesgBodyResponse ;
// rule RL_wmrd_mesgBegin
assign CAN_FIRE_RL_wmrd_mesgBegin =
metaRF$EMPTY_N && wci_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 &&
unrollCnt == 16'd0 ;
assign WILL_FIRE_RL_wmrd_mesgBegin = CAN_FIRE_RL_wmrd_mesgBegin ;
// rule RL_wsipass_doMessagePush
assign CAN_FIRE_RL_wsipass_doMessagePush =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ;
assign WILL_FIRE_RL_wsipass_doMessagePush =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ;
// rule RL_wsiM_reqFifo_both
assign CAN_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_x_wire$whas) &&
CAN_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ;
// rule RL_wci_Es_doAlways_Req
assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
// rule RL_wci_reqF_enq
assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq$wget[59:57] != 3'd0 ;
assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ;
// rule RL_wmemi_Em_doAlways
assign CAN_FIRE_RL_wmemi_Em_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wmemi_Em_doAlways = 1'd1 ;
// rule RL_rdSer_sync
assign CAN_FIRE_RL_rdSer_sync =
wci_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 && rdSyncWord ;
assign WILL_FIRE_RL_rdSer_sync = CAN_FIRE_RL_rdSer_sync ;
// rule RL_rdSer_body
assign CAN_FIRE_RL_rdSer_body =
mesgRF_i_notFull__74_AND_NOT_rdSerEmpty_75_76__ETC___d285 &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
rdSerUnroll != 16'd0 &&
!rdSyncWord ;
assign WILL_FIRE_RL_rdSer_body = CAN_FIRE_RL_rdSer_body ;
// rule RL_rdSer_begin
assign CAN_FIRE_RL_rdSer_begin =
metaRF_i_notFull__18_AND_NOT_rdSerEmpty_75_76__ETC___d319 &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
rdSerUnroll == 16'd0 &&
!rdSyncWord ;
assign WILL_FIRE_RL_rdSer_begin = CAN_FIRE_RL_rdSer_begin ;
// rule RL_delay_Fb2Fc
assign CAN_FIRE_RL_delay_Fb2Fc =
wide16Fc$FULL_N && wide16Fb$EMPTY_N && wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign WILL_FIRE_RL_delay_Fb2Fc = CAN_FIRE_RL_delay_Fb2Fc ;
// rule RL_delay_read_req
assign CAN_FIRE_RL_delay_read_req =
wmemi_reqF_c_r != 2'd2 && wmemi_operateD && wmemi_peerIsReady &&
wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d352 &&
(dlyReadCredit_value ^ 8'h80) > 8'd128 &&
wsiM_reqFifo_c_r != 2'd2 ;
assign WILL_FIRE_RL_delay_read_req = CAN_FIRE_RL_delay_read_req ;
// rule RL_delay_write_req
assign CAN_FIRE_RL_delay_write_req =
wmemi_reqF_c_r != 2'd2 && wmemi_dhF_c_r != 2'd2 &&
wmemi_operateD &&
wmemi_peerIsReady &&
wide16Fa$EMPTY_N &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
dlyWordsStored_value_26_SLE_0_49_OR_bytesWritt_ETC___d164 &&
dlyWordsStored_value_26_SLT_8388608___d165 ;
assign WILL_FIRE_RL_delay_write_req =
CAN_FIRE_RL_delay_write_req && !WILL_FIRE_RL_delay_read_req ;
// rule RL_wsiM_reqFifo_decCtr
assign CAN_FIRE_RL_wsiM_reqFifo_decCtr =
CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ;
// rule RL_wsiM_reqFifo_incCtr
assign CAN_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_x_wire$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ;
// rule RL_operating_actions
assign CAN_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
assign WILL_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
// rule RL_wsiS_operateD__dreg_update
assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
// rule RL_wsiM_operateD__dreg_update
assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
// rule RL_wrtSer_begin
assign CAN_FIRE_RL_wrtSer_begin =
metaWF$EMPTY_N &&
NOT_wrtSerPos_80_EQ_3_87_88_AND_NOT_metaWF_fir_ETC___d434 &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
wrtSerUnroll == 16'd0 ;
assign WILL_FIRE_RL_wrtSer_begin = CAN_FIRE_RL_wrtSer_begin ;
// rule RL_wmwt_mesg_ingress
assign CAN_FIRE_RL_wmwt_mesg_ingress =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
assign WILL_FIRE_RL_wmwt_mesg_ingress =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
// rule RL_wsiS_reqFifo_reset
assign CAN_FIRE_RL_wsiS_reqFifo_reset =
wsiS_reqFifo_r_enq$whas || wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo_reset = CAN_FIRE_RL_wsiS_reqFifo_reset ;
// rule RL_wsiS_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
wsiS_reqFifo_r_enq$whas != wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// rule RL_cycles_passed_count
assign CAN_FIRE_RL_cycles_passed_count = wsiS_statusR[0] ;
assign WILL_FIRE_RL_cycles_passed_count = CAN_FIRE_RL_cycles_passed_count ;
// rule RL_dlyReadCredit_accumulate
assign CAN_FIRE_RL_dlyReadCredit_accumulate = 1'd1 ;
assign WILL_FIRE_RL_dlyReadCredit_accumulate = 1'd1 ;
// rule RL_dlyWordsStored_accumulate
assign CAN_FIRE_RL_dlyWordsStored_accumulate = 1'd1 ;
assign WILL_FIRE_RL_dlyWordsStored_accumulate = 1'd1 ;
// rule RL_mesgWF_portB_read_data
assign CAN_FIRE_RL_mesgWF_portB_read_data = 1'd1 ;
assign WILL_FIRE_RL_mesgWF_portB_read_data = 1'd1 ;
// rule RL_wrtSer_body
assign CAN_FIRE_RL_wrtSer_body =
NOT_mesgWF_rRdPtr_69_EQ_mesgWF_rWrPtr_71_74___d175 &&
IF_wrtSerPos_80_EQ_0_81_OR_wrtSerPos_80_EQ_1_8_ETC___d399 &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 &&
wrtSerUnroll != 16'd0 ;
assign WILL_FIRE_RL_wrtSer_body = CAN_FIRE_RL_wrtSer_body ;
// rule RL_dlyReadyToWrite_accumulate
assign CAN_FIRE_RL_dlyReadyToWrite_accumulate = 1'd1 ;
assign WILL_FIRE_RL_dlyReadyToWrite_accumulate = 1'd1 ;
// rule RL_wci_ctrl_IsO
assign CAN_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ;
// rule RL_mesgWF_portB
assign CAN_FIRE_RL_mesgWF_portB = 1'd1 ;
assign WILL_FIRE_RL_mesgWF_portB = 1'd1 ;
// rule RL_mesgWF_portA
assign CAN_FIRE_RL_mesgWF_portA = 1'd1 ;
assign WILL_FIRE_RL_mesgWF_portA = 1'd1 ;
// rule RL_wmemi_dhF_deq
assign CAN_FIRE_RL_wmemi_dhF_deq = wmemiM_SDataAccept ;
assign WILL_FIRE_RL_wmemi_dhF_deq = wmemiM_SDataAccept ;
// rule RL_wmemi_respAdvance
assign CAN_FIRE_RL_wmemi_respAdvance =
wmemi_operateD && wmemi_peerIsReady &&
wmemi_wmemiResponse$wget[130:129] != 2'd0 ;
assign WILL_FIRE_RL_wmemi_respAdvance = CAN_FIRE_RL_wmemi_respAdvance ;
// rule RL_wmemi_peerIsReady__dreg_update
assign CAN_FIRE_RL_wmemi_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wmemi_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wmemi_operateD__dreg_update
assign CAN_FIRE_RL_wmemi_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wmemi_operateD__dreg_update = 1'd1 ;
// rule RL_delay_read_resp
assign CAN_FIRE_RL_delay_read_resp =
wmemi_respF$EMPTY_N && wide16Fb$FULL_N && wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign WILL_FIRE_RL_delay_read_resp = CAN_FIRE_RL_delay_read_resp ;
// rule RL_wci_ctl_op_complete
assign CAN_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctlAckReg__dreg_update
assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
// rule RL_wci_respF_both
assign CAN_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ;
// rule RL_wci_respF_decCtr
assign CAN_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ;
// rule RL_wci_respF_incCtr
assign CAN_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ;
// rule RL_wci_reqF__updateLevelCounter
assign CAN_FIRE_RL_wci_reqF__updateLevelCounter =
(wci_wciReq$wget[59:57] != 3'd0) != wci_reqF_r_deq$whas ;
assign WILL_FIRE_RL_wci_reqF__updateLevelCounter =
CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// rule RL_wmemi_reqF_deq
assign CAN_FIRE_RL_wmemi_reqF_deq = wmemiM_SCmdAccept ;
assign WILL_FIRE_RL_wmemi_reqF_deq = wmemiM_SCmdAccept ;
// rule RL_wmemi_dhF_both
assign CAN_FIRE_RL_wmemi_dhF_both =
((wmemi_dhF_c_r == 2'd1) ?
WILL_FIRE_RL_delay_write_req :
wmemi_dhF_c_r != 2'd2 || WILL_FIRE_RL_delay_write_req) &&
wmemi_dhF_dequeueing$whas &&
WILL_FIRE_RL_delay_write_req ;
assign WILL_FIRE_RL_wmemi_dhF_both = CAN_FIRE_RL_wmemi_dhF_both ;
// rule RL_wmemi_dhF_decCtr
assign CAN_FIRE_RL_wmemi_dhF_decCtr =
wmemi_dhF_dequeueing$whas && !WILL_FIRE_RL_delay_write_req ;
assign WILL_FIRE_RL_wmemi_dhF_decCtr = CAN_FIRE_RL_wmemi_dhF_decCtr ;
// rule RL_wmemi_dhF_incCtr
assign CAN_FIRE_RL_wmemi_dhF_incCtr =
((wmemi_dhF_c_r == 2'd0) ?
WILL_FIRE_RL_delay_write_req :
wmemi_dhF_c_r != 2'd1 || WILL_FIRE_RL_delay_write_req) &&
WILL_FIRE_RL_delay_write_req &&
!wmemi_dhF_dequeueing$whas ;
assign WILL_FIRE_RL_wmemi_dhF_incCtr = CAN_FIRE_RL_wmemi_dhF_incCtr ;
// rule RL_wmemi_reqF_both
assign CAN_FIRE_RL_wmemi_reqF_both =
((wmemi_reqF_c_r == 2'd1) ?
wmemi_reqF_x_wire$whas :
wmemi_reqF_c_r != 2'd2 || wmemi_reqF_x_wire$whas) &&
wmemi_reqF_dequeueing$whas &&
wmemi_reqF_enqueueing$whas ;
assign WILL_FIRE_RL_wmemi_reqF_both = CAN_FIRE_RL_wmemi_reqF_both ;
// rule RL_wmemi_reqF_incCtr
assign CAN_FIRE_RL_wmemi_reqF_incCtr =
((wmemi_reqF_c_r == 2'd0) ?
wmemi_reqF_x_wire$whas :
wmemi_reqF_c_r != 2'd1 || wmemi_reqF_x_wire$whas) &&
wmemi_reqF_enqueueing$whas &&
!wmemi_reqF_dequeueing$whas ;
assign WILL_FIRE_RL_wmemi_reqF_incCtr = CAN_FIRE_RL_wmemi_reqF_incCtr ;
// rule RL_wmemi_reqF_decCtr
assign CAN_FIRE_RL_wmemi_reqF_decCtr =
wmemi_reqF_dequeueing$whas && !wmemi_reqF_enqueueing$whas ;
assign WILL_FIRE_RL_wmemi_reqF_decCtr = CAN_FIRE_RL_wmemi_reqF_decCtr ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h0 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_unrollCnt$write_1__VAL_1 =
(metaRF$D_OUT[23:0] == 24'd0) ? 16'd1 : metaRF$D_OUT[20:5] ;
assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unrollCnt == 16'd1,
1'd1,
x_burstLength__h19976,
mesgRF$D_OUT,
x_byteEn__h19977,
readMeta[31:24] } ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
WILL_FIRE_RL_wmrd_mesgBodyResponse ?
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 :
wsiS_reqFifo$D_OUT ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 =
NOT_mesgWF_rRdPtr_69_PLUS_2048_70_EQ_mesgWF_rW_ETC___d173 &&
wsiS_reqFifo$EMPTY_N &&
(!wsiS_reqFifo$D_OUT[309] || metaWF$FULL_N) &&
wci_cState == 3'd2 &&
dlyCtrl[3:0] == 4'h7 ;
assign MUX_mesgRdCount$write_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ;
assign MUX_mesgWtCount$write_1__SEL_1 =
WILL_FIRE_RL_wmwt_mesg_ingress && wsiS_reqFifo$D_OUT[309] ;
assign MUX_dlyRAG$write_1__VAL_1 = dlyRAG + 23'd1 ;
assign MUX_dlyWAG$write_1__VAL_1 = dlyWAG + 23'd1 ;
assign MUX_mesgRdCount$write_1__VAL_1 = mesgRdCount + 32'd1 ;
assign MUX_mesgWtCount$write_1__VAL_1 = mesgWtCount + 32'd1 ;
assign MUX_rdSerPos$write_1__VAL_1 = rdSerPos + 2'd1 ;
assign MUX_rdSerUnroll$write_1__VAL_2 = rdSerUnroll - 16'd1 ;
assign MUX_rdSyncWord$write_1__VAL_1 =
rdSerPos != 2'd3 && rdSerUnroll == 16'd1 ;
assign MUX_wmemi_dhF_c_r$write_1__VAL_1 = wmemi_dhF_c_r - 2'd1 ;
assign MUX_wmemi_dhF_c_r$write_1__VAL_2 = wmemi_dhF_c_r + 2'd1 ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_1 = wmemi_reqF_c_r - 2'd1 ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_2 =
{ 2'd3, wide16Fa$D_OUT, 16'd65535 } ;
assign MUX_wmemi_dhF_q_0$write_1__VAL_1 =
(wmemi_dhF_c_r == 2'd1) ?
MUX_wmemi_dhF_q_0$write_1__VAL_2 :
wmemi_dhF_q_1 ;
assign MUX_wmemi_dhF_q_1$write_1__VAL_1 =
(wmemi_dhF_c_r == 2'd2) ?
MUX_wmemi_dhF_q_0$write_1__VAL_2 :
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign MUX_wmemi_reqF_c_r$write_1__VAL_2 = wmemi_reqF_c_r + 2'd1 ;
assign MUX_wmemi_reqF_x_wire$wset_1__VAL_1 = { 4'd5, addr__h19478, 12'd1 } ;
assign MUX_wmemi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, addr__h19647, 12'd1 } ;
assign MUX_wrtSerUnroll$write_1__VAL_1 = wrtSerUnroll - 16'd1 ;
assign MUX_wrtSerStage$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd0 ;
assign MUX_wrtSerStage_1$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd1 ;
assign MUX_wrtSerStage_2$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd2 ;
assign MUX_wrtSerStage_3$write_1__SEL_1 =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd3 ;
assign MUX_rdSerEmpty$write_1__PSEL_1 =
WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ;
assign MUX_rdSerEmpty$write_1__SEL_1 =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
assign MUX_rdSyncWord$write_1__VAL_2 =
rdSerPos != 2'd3 && v__h20254[23:0] == 24'd0 ;
assign MUX_wide16Fa$enq_1__SEL_1 =
WILL_FIRE_RL_wrtSer_begin &&
(wrtSerPos == 2'd3 || metaWF$D_OUT[23:0] == 24'd0) ;
always@(wrtSerPos or
IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_mesgWF_w_ETC___d423 or
x__h18132 or x__h18163)
begin
case (wrtSerPos)
2'd0: MUX_wide16Fa$enq_1__VAL_2 = x__h18132;
2'd1: MUX_wide16Fa$enq_1__VAL_2 = x__h18163;
default: MUX_wide16Fa$enq_1__VAL_2 =
IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_mesgWF_w_ETC___d423;
endcase
end
always@(wrtSerPos or
IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_metaWF_f_ETC___d446 or
x__h18794 or x__h18821)
begin
case (wrtSerPos)
2'd0: MUX_wide16Fa$enq_1__VAL_1 = x__h18794;
2'd1: MUX_wide16Fa$enq_1__VAL_1 = x__h18821;
default: MUX_wide16Fa$enq_1__VAL_1 =
IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_metaWF_f_ETC___d446;
endcase
end
assign MUX_wrtSerPos$write_1__VAL_1 =
(wrtSerUnroll == 16'd1) ? 2'd0 : wrtSerPos_80_PLUS_1___d984 ;
assign MUX_wrtSerPos$write_1__VAL_2 =
(metaWF$D_OUT[23:0] == 24'd0) ?
2'd0 :
wrtSerPos_80_PLUS_1___d984 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 = { 2'd1, x_data__h22228 } ;
always@(WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wmemi_dhF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ;
assign MUX_wmemi_dhF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ;
assign MUX_dlyReadCredit_value$write_1__VAL_2 =
dlyReadCredit_value +
(CAN_FIRE_RL_delay_read_req ? 8'd255 : 8'd0) +
(CAN_FIRE_RL_delay_Fb2Fc ? 8'd1 : 8'd0) ;
assign MUX_dlyReadyToWrite_value$write_1__VAL_2 =
dlyReadyToWrite_value +
(dlyReadyToWrite_acc_v1$whas ? 16'd1 : 16'd0) +
(WILL_FIRE_RL_delay_write_req ? 16'd65535 : 16'd0) ;
assign MUX_dlyWordsStored_value$write_1__VAL_2 =
dlyWordsStored_value +
(WILL_FIRE_RL_delay_write_req ? 25'd1 : 25'd0) +
(CAN_FIRE_RL_delay_read_req ? 25'd33554431 : 25'd0) ;
assign MUX_wmemi_reqF_q_0$write_1__VAL_2 =
WILL_FIRE_RL_delay_read_req ?
MUX_wmemi_reqF_x_wire$wset_1__VAL_1 :
MUX_wmemi_reqF_x_wire$wset_1__VAL_2 ;
assign MUX_wmemi_reqF_q_0$write_1__VAL_1 =
(wmemi_reqF_c_r == 2'd1) ?
MUX_wmemi_reqF_q_0$write_1__VAL_2 :
wmemi_reqF_q_1 ;
assign MUX_wmemi_reqF_q_1$write_1__VAL_1 =
(wmemi_reqF_c_r == 2'd2) ?
MUX_wmemi_reqF_q_0$write_1__VAL_2 :
52'h0AAAAAAAAAAAA ;
assign MUX_wmemi_reqF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ;
assign MUX_wmemi_reqF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_respF_x_wire$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wmemi_operateD_1$whas = wci_cState == 3'd2 ;
assign wmemi_operateD_1$wget = 1'd1 ;
assign wmemi_peerIsReady_1$wget = 1'b0 ;
assign wmemi_peerIsReady_1$whas = 1'b0 ;
assign wsiM_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM1_SThreadBusy ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
assign wsiM_peerIsReady_1$whas = wsiM1_SReset_n ;
assign wsiS_wsiReq$wget =
{ wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_reqFifo_r_enq$whas =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas = wsiS_reqFifo_r_enq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = wci_cState == 3'd2 ;
assign wsiS_peerIsReady_1$whas = wsiS1_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas = CAN_FIRE_RL_wsiS_backpressure ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsi_Es_mCmd_w$wget = wsiS1_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mReqLast_w$whas = wsiS1_MReqLast ;
assign wsi_Es_mBurstLength_w$wget = wsiS1_MBurstLength ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS1_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS1_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS1_MReqInfo ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wmrd_mesgBodyResponse ;
assign wsiM_reqFifo_x_wire$whas =
WILL_FIRE_RL_wmrd_mesgBodyResponse ||
WILL_FIRE_RL_wsipass_doMessagePush ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_wmwt_mesg_ingress ||
WILL_FIRE_RL_wsipass_doMessagePush ;
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wmemi_reqF_dequeueing$whas =
wmemiM_SCmdAccept && wmemi_reqF_c_r != 2'd0 ;
assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_2 ;
assign wmemi_dhF_dequeueing$whas =
wmemiM_SDataAccept && wmemi_dhF_c_r != 2'd0 ;
assign wmemi_wmemiResponse$wget =
{ wmemiM_SResp, wmemiM_SRespLast, wmemiM_SData } ;
assign wmemi_wmemiResponse$whas = 1'd1 ;
assign wmemi_sCmdAccept_w$wget = 1'd1 ;
assign wmemi_sCmdAccept_w$whas = wmemiM_SCmdAccept ;
assign wmemi_sDataAccept_w$wget = 1'd1 ;
assign wmemi_sDataAccept_w$whas = wmemiM_SDataAccept ;
assign mesgWF_pwEnqueue$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
assign mesgWF_wDataIn$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
assign mesgWF_wDataIn$wget = wsiS_reqFifo$D_OUT[295:40] ;
assign mesgWF_wDataOut$wget = x__h17993 ;
assign mesgWF_wDataOut$whas = 1'd1 ;
assign dlyWordsStored_acc_v1$wget = 25'd1 ;
assign dlyWordsStored_acc_v2$wget = 25'd33554431 ;
assign dlyReadCredit_acc_v1$wget = 8'd255 ;
assign dlyReadCredit_acc_v2$wget = 8'd1 ;
assign dlyReadCredit_acc_v2$whas = CAN_FIRE_RL_delay_Fb2Fc ;
assign dlyReadyToWrite_acc_v1$wget = 16'd1 ;
assign dlyReadyToWrite_acc_v2$wget = 16'd65535 ;
assign wmemi_Em_sResp_w$wget = wmemiM_SResp ;
assign wmemi_Em_sData_w$wget = wmemiM_SData ;
assign wmemi_Em_sResp_w$whas = 1'd1 ;
assign wmemi_Em_sRespLast_w$whas = wmemiM_SRespLast ;
assign wmemi_Em_sData_w$whas = 1'd1 ;
assign mesgWF_pwDequeue$whas = CAN_FIRE_RL_wrtSer_body ;
assign dlyReadyToWrite_acc_v1$whas =
WILL_FIRE_RL_wrtSer_begin || WILL_FIRE_RL_wrtSer_body ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wmemi_reqF_enqueueing$whas =
WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_delay_read_req ;
assign wmemi_reqF_x_wire$wget = MUX_wmemi_reqF_q_0$write_1__VAL_2 ;
assign wmemi_reqF_x_wire$whas =
WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_delay_write_req ;
assign wmemi_dhF_enqueueing$whas = WILL_FIRE_RL_delay_write_req ;
assign wmemi_dhF_x_wire$whas = WILL_FIRE_RL_delay_write_req ;
assign dlyWordsStored_acc_v1$whas = WILL_FIRE_RL_delay_write_req ;
assign dlyWordsStored_acc_v2$whas = CAN_FIRE_RL_delay_read_req ;
assign dlyReadCredit_acc_v1$whas = CAN_FIRE_RL_delay_read_req ;
assign dlyReadyToWrite_acc_v2$whas = WILL_FIRE_RL_delay_write_req ;
// register bytesRead
assign bytesRead$D_IN = bytesRead + 32'd32 ;
assign bytesRead$EN =
MUX_rdSerEmpty$write_1__PSEL_1 && bytesRead != 32'hFFFFFFFF ;
// register bytesThisMessage
assign bytesThisMessage$EN = MUX_mesgWtCount$write_1__SEL_1 ;
assign bytesThisMessage$D_IN = btm__h17027 ;
// register bytesWritten
assign bytesWritten$D_IN = bytesWritten + 32'd32 ;
assign bytesWritten$EN =
WILL_FIRE_RL_wmwt_mesg_ingress && bytesWritten < 32'hFFFFFFDF ;
// register cyclesPassed
assign cyclesPassed$D_IN = cyclesPassed + 32'd1 ;
assign cyclesPassed$EN = wsiS_statusR[0] && cyclesPassed != 32'hFFFFFFFF ;
// register dlyCtrl
assign dlyCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign dlyCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h0 ;
// register dlyHoldoffBytes
assign dlyHoldoffBytes$D_IN = wci_reqF$D_OUT[31:0] ;
assign dlyHoldoffBytes$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h00004 ;
// register dlyHoldoffCycles
assign dlyHoldoffCycles$D_IN = wci_reqF$D_OUT[31:0] ;
assign dlyHoldoffCycles$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h00008 ;
// register dlyRAG
assign dlyRAG$D_IN =
WILL_FIRE_RL_delay_read_req ? MUX_dlyRAG$write_1__VAL_1 : 23'd0 ;
assign dlyRAG$EN =
WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_wci_ctrl_IsO ;
// register dlyRdOpOther
assign dlyRdOpOther$D_IN = dlyRdOpOther + 32'd1 ;
assign dlyRdOpOther$EN =
WILL_FIRE_RL_rdSer_begin && v__h20254[31:24] != 8'd0 ;
// register dlyRdOpZero
assign dlyRdOpZero$D_IN = dlyRdOpZero + 32'd1 ;
assign dlyRdOpZero$EN =
WILL_FIRE_RL_rdSer_begin && v__h20254[31:24] == 8'd0 ;
// register dlyReadCredit_value
assign dlyReadCredit_value$EN = 1'b1 ;
assign dlyReadCredit_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
8'd12 :
MUX_dlyReadCredit_value$write_1__VAL_2 ;
// register dlyReadyToWrite_value
assign dlyReadyToWrite_value$EN = 1'b1 ;
assign dlyReadyToWrite_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
16'd0 :
MUX_dlyReadyToWrite_value$write_1__VAL_2 ;
// register dlyWAG
assign dlyWAG$D_IN =
WILL_FIRE_RL_delay_write_req ?
MUX_dlyWAG$write_1__VAL_1 :
23'd0 ;
assign dlyWAG$EN =
WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_wci_ctrl_IsO ;
// register dlyWordsStored_value
assign dlyWordsStored_value$EN = 1'b1 ;
assign dlyWordsStored_value$D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
25'd0 :
MUX_dlyWordsStored_value$write_1__VAL_2 ;
// register mesgLengthSoFar
assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
assign mesgLengthSoFar$D_IN =
wsiS_reqFifo$D_OUT[309] ?
14'd0 :
mesgLengthSoFar_05_PLUS_1___d985 ;
// register mesgRdCount
assign mesgRdCount$D_IN =
MUX_mesgRdCount$write_1__SEL_1 ?
MUX_mesgRdCount$write_1__VAL_1 :
32'd0 ;
assign mesgRdCount$EN =
WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgWF_rCache
assign mesgWF_rCache$D_IN = { 1'd1, mesgWF_rWrPtr, x__h15073 } ;
assign mesgWF_rCache$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
// register mesgWF_rRdPtr
assign mesgWF_rRdPtr$D_IN = x__h14965 ;
assign mesgWF_rRdPtr$EN = CAN_FIRE_RL_wrtSer_body ;
// register mesgWF_rWrPtr
assign mesgWF_rWrPtr$D_IN = mesgWF_rWrPtr + 13'd1 ;
assign mesgWF_rWrPtr$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
// register mesgWtCount
assign mesgWtCount$D_IN =
MUX_mesgWtCount$write_1__SEL_1 ?
MUX_mesgWtCount$write_1__VAL_1 :
32'd0 ;
assign mesgWtCount$EN =
WILL_FIRE_RL_wmwt_mesg_ingress && wsiS_reqFifo$D_OUT[309] ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register rdSerAddr
assign rdSerAddr$D_IN = 32'h0 ;
assign rdSerAddr$EN = 1'b0 ;
// register rdSerEmpty
assign rdSerEmpty$D_IN = !MUX_rdSerEmpty$write_1__SEL_1 ;
assign rdSerEmpty$EN =
(WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body) &&
(rdSerEmpty || rdSerPos == 2'd0) ||
WILL_FIRE_RL_rdSer_sync ;
// register rdSerMeta
assign rdSerMeta$D_IN = metaRF$D_IN ;
assign rdSerMeta$EN = CAN_FIRE_RL_rdSer_begin ;
// register rdSerPos
assign rdSerPos$D_IN =
MUX_rdSerEmpty$write_1__PSEL_1 ?
MUX_rdSerPos$write_1__VAL_1 :
2'd0 ;
assign rdSerPos$EN =
WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ||
WILL_FIRE_RL_rdSer_sync ;
// register rdSerStage
assign rdSerStage$D_IN = wide16Fc$D_OUT[31:0] ;
assign rdSerStage$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_1
assign rdSerStage_1$D_IN = wide16Fc$D_OUT[63:32] ;
assign rdSerStage_1$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_2
assign rdSerStage_2$D_IN = wide16Fc$D_OUT[95:64] ;
assign rdSerStage_2$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerStage_3
assign rdSerStage_3$D_IN = wide16Fc$D_OUT[127:96] ;
assign rdSerStage_3$EN =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
// register rdSerUnroll
assign rdSerUnroll$EN = MUX_rdSerEmpty$write_1__PSEL_1 ;
assign rdSerUnroll$D_IN =
WILL_FIRE_RL_rdSer_begin ?
v__h20254[20:5] :
MUX_rdSerUnroll$write_1__VAL_2 ;
// register rdSyncWord
assign rdSyncWord$EN =
WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin ||
WILL_FIRE_RL_rdSer_sync ;
always@(WILL_FIRE_RL_rdSer_body or
MUX_rdSyncWord$write_1__VAL_1 or
WILL_FIRE_RL_rdSer_begin or
MUX_rdSyncWord$write_1__VAL_2 or WILL_FIRE_RL_rdSer_sync)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rdSer_body:
rdSyncWord$D_IN = MUX_rdSyncWord$write_1__VAL_1;
WILL_FIRE_RL_rdSer_begin:
rdSyncWord$D_IN = MUX_rdSyncWord$write_1__VAL_2;
WILL_FIRE_RL_rdSer_sync: rdSyncWord$D_IN = 1'd0;
default: rdSyncWord$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
// register readMeta
assign readMeta$D_IN = metaRF$D_OUT ;
assign readMeta$EN = CAN_FIRE_RL_wmrd_mesgBegin ;
// register tog50
assign tog50$D_IN = !tog50 ;
assign tog50$EN = wci_cState == 3'd2 ;
// register unrollCnt
assign unrollCnt$D_IN =
WILL_FIRE_RL_wmrd_mesgBegin ?
MUX_unrollCnt$write_1__VAL_1 :
MUX_unrollCnt$write_1__VAL_2 ;
assign unrollCnt$EN =
WILL_FIRE_RL_wmrd_mesgBegin ||
WILL_FIRE_RL_wmrd_mesgBodyResponse ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[59:57] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_respF_q_1
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wmemiRdReq
assign wmemiRdReq$D_IN = wmemiRdReq + 32'd1 ;
assign wmemiRdReq$EN = CAN_FIRE_RL_delay_read_req ;
// register wmemiRdResp1
assign wmemiRdResp1$D_IN = wmemiRdResp1 + 32'd1 ;
assign wmemiRdResp1$EN = CAN_FIRE_RL_delay_read_resp ;
// register wmemiRdResp2
assign wmemiRdResp2$D_IN = wmemiRdResp2 + 32'd1 ;
assign wmemiRdResp2$EN = CAN_FIRE_RL_delay_Fb2Fc ;
// register wmemiWrReq
assign wmemiWrReq$D_IN = wmemiWrReq + 32'd1 ;
assign wmemiWrReq$EN = WILL_FIRE_RL_delay_write_req ;
// register wmemi_busyWithMessage
assign wmemi_busyWithMessage$D_IN = 1'b0 ;
assign wmemi_busyWithMessage$EN = 1'b0 ;
// register wmemi_dhF_c_r
assign wmemi_dhF_c_r$D_IN =
WILL_FIRE_RL_wmemi_dhF_decCtr ?
MUX_wmemi_dhF_c_r$write_1__VAL_1 :
MUX_wmemi_dhF_c_r$write_1__VAL_2 ;
assign wmemi_dhF_c_r$EN =
WILL_FIRE_RL_wmemi_dhF_decCtr || WILL_FIRE_RL_wmemi_dhF_incCtr ;
// register wmemi_dhF_q_0
always@(WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_0$write_1__VAL_1 or
MUX_wmemi_dhF_q_0$write_1__SEL_2 or
MUX_wmemi_dhF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1;
MUX_wmemi_dhF_q_0$write_1__SEL_2:
wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_0$D_IN = wmemi_dhF_q_1;
default: wmemi_dhF_q_0$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_dhF_q_0$EN =
WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_dhF_q_1
always@(WILL_FIRE_RL_wmemi_dhF_both or
MUX_wmemi_dhF_q_1$write_1__VAL_1 or
MUX_wmemi_dhF_q_1$write_1__SEL_2 or
MUX_wmemi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_dhF_both:
wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_1;
MUX_wmemi_dhF_q_1$write_1__SEL_2:
wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_dhF_decCtr:
wmemi_dhF_q_1$D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: wmemi_dhF_q_1$D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_dhF_q_1$EN =
WILL_FIRE_RL_wmemi_dhF_both ||
WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ||
WILL_FIRE_RL_wmemi_dhF_decCtr ;
// register wmemi_errorSticky
assign wmemi_errorSticky$D_IN = 1'd1 ;
assign wmemi_errorSticky$EN =
WILL_FIRE_RL_wmemi_respAdvance && !wmemi_respF$FULL_N ;
// register wmemi_operateD
assign wmemi_operateD$D_IN = wci_cState == 3'd2 ;
assign wmemi_operateD$EN = 1'd1 ;
// register wmemi_peerIsReady
assign wmemi_peerIsReady$D_IN = 1'b1 ;
assign wmemi_peerIsReady$EN = 1'd1 ;
// register wmemi_reqF_c_r
assign wmemi_reqF_c_r$D_IN =
WILL_FIRE_RL_wmemi_reqF_decCtr ?
MUX_wmemi_reqF_c_r$write_1__VAL_1 :
MUX_wmemi_reqF_c_r$write_1__VAL_2 ;
assign wmemi_reqF_c_r$EN =
WILL_FIRE_RL_wmemi_reqF_decCtr ||
WILL_FIRE_RL_wmemi_reqF_incCtr ;
// register wmemi_reqF_q_0
always@(WILL_FIRE_RL_wmemi_reqF_both or
MUX_wmemi_reqF_q_0$write_1__VAL_1 or
MUX_wmemi_reqF_q_0$write_1__SEL_2 or
MUX_wmemi_reqF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_reqF_both:
wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_1;
MUX_wmemi_reqF_q_0$write_1__SEL_2:
wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_0$D_IN = wmemi_reqF_q_1;
default: wmemi_reqF_q_0$D_IN =
52'hAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_reqF_q_0$EN =
WILL_FIRE_RL_wmemi_reqF_both ||
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_reqF_q_1
always@(WILL_FIRE_RL_wmemi_reqF_both or
MUX_wmemi_reqF_q_1$write_1__VAL_1 or
MUX_wmemi_reqF_q_1$write_1__SEL_2 or
MUX_wmemi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmemi_reqF_both:
wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_1$write_1__VAL_1;
MUX_wmemi_reqF_q_1$write_1__SEL_2:
wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_1$D_IN = 52'h0AAAAAAAAAAAA;
default: wmemi_reqF_q_1$D_IN =
52'hAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_reqF_q_1$EN =
WILL_FIRE_RL_wmemi_reqF_both ||
WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ||
WILL_FIRE_RL_wmemi_reqF_decCtr ;
// register wmemi_statusR
assign wmemi_statusR$D_IN =
{ wmemi_isReset$VAL,
!wmemi_peerIsReady,
!wmemi_operateD,
wmemi_errorSticky,
3'd0,
wmemi_trafficSticky } ;
assign wmemi_statusR$EN = 1'd1 ;
// register wmemi_trafficSticky
assign wmemi_trafficSticky$D_IN = 1'd1 ;
assign wmemi_trafficSticky$EN = wmemiM_SCmdAccept ;
// register wrtSerAddr
assign wrtSerAddr$D_IN = 32'h0 ;
assign wrtSerAddr$EN = 1'b0 ;
// register wrtSerPos
assign wrtSerPos$EN =
WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ;
assign wrtSerPos$D_IN =
WILL_FIRE_RL_wrtSer_body ?
MUX_wrtSerPos$write_1__VAL_1 :
MUX_wrtSerPos$write_1__VAL_2 ;
// register wrtSerStage
assign wrtSerStage$D_IN =
MUX_wrtSerStage$write_1__SEL_1 ? x__h17993[31:0] : metaWF$D_OUT ;
assign wrtSerStage$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd0 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd0 ;
// register wrtSerStage_1
assign wrtSerStage_1$D_IN =
MUX_wrtSerStage_1$write_1__SEL_1 ?
x__h17993[31:0] :
metaWF$D_OUT ;
assign wrtSerStage_1$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd1 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd1 ;
// register wrtSerStage_2
assign wrtSerStage_2$D_IN =
MUX_wrtSerStage_2$write_1__SEL_1 ?
x__h17993[31:0] :
metaWF$D_OUT ;
assign wrtSerStage_2$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd2 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd2 ;
// register wrtSerStage_3
assign wrtSerStage_3$D_IN =
MUX_wrtSerStage_3$write_1__SEL_1 ?
x__h17993[31:0] :
metaWF$D_OUT ;
assign wrtSerStage_3$EN =
WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'd3 ||
WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'd3 ;
// register wrtSerUnroll
assign wrtSerUnroll$D_IN =
WILL_FIRE_RL_wrtSer_body ?
MUX_wrtSerUnroll$write_1__VAL_1 :
metaWF$D_OUT[20:5] ;
assign wrtSerUnroll$EN =
WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[309]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[309] ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[309] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM1_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// register wsiM_reqFifo_q_1
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset$VAL,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[312:310] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
wsiS_reqFifo_notFull__05_AND_wsiS_burstKind_85_ETC___d725 ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'd1 ;
assign wsiS_errorSticky$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo$FULL_N ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[309] ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_wsiReq$wget[309] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = wci_cState == 3'd2 ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[309] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS1_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
wsiS_reqFifo_r_enq$whas ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N ||
WILL_FIRE_RL_wmwt_mesg_ingress ||
WILL_FIRE_RL_wsipass_doMessagePush ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset$VAL,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = wsiS_reqFifo_r_enq$whas ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[309] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = wsiS_reqFifo_r_enq$whas ;
// submodule mesgRF
assign mesgRF$DEQ = CAN_FIRE_RL_wmrd_mesgBodyResponse ;
assign mesgRF$ENQ = CAN_FIRE_RL_rdSer_body ;
assign mesgRF$CLR = 1'b0 ;
assign mesgRF$D_IN = { 224'd0, v__h20254 } ;
// submodule mesgWF_memory
assign mesgWF_memory$WEA = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ;
assign mesgWF_memory$ADDRA = mesgWF_rWrPtr[11:0] ;
assign mesgWF_memory$DIA = x__h15073 ;
assign mesgWF_memory$WEB = 1'd0 ;
assign mesgWF_memory$DIB =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign mesgWF_memory$ENA = 1'd1 ;
assign mesgWF_memory$ENB = 1'd1 ;
assign mesgWF_memory$ADDRB =
CAN_FIRE_RL_wrtSer_body ? x__h14965[11:0] : mesgWF_rRdPtr[11:0] ;
// submodule metaRF
always@(rdSerPos or
rdSerStage_3 or wide16Fc$D_OUT or rdSerStage_1 or rdSerStage_2)
begin
case (rdSerPos)
2'd0: metaRF$D_IN = wide16Fc$D_OUT[31:0];
2'd1: metaRF$D_IN = rdSerStage_1;
2'd2: metaRF$D_IN = rdSerStage_2;
2'd3: metaRF$D_IN = rdSerStage_3;
endcase
end
assign metaRF$DEQ = CAN_FIRE_RL_wmrd_mesgBegin ;
assign metaRF$CLR = 1'b0 ;
assign metaRF$ENQ = CAN_FIRE_RL_rdSer_begin ;
// submodule metaWF
assign metaWF$ENQ = MUX_mesgWtCount$write_1__SEL_1 ;
assign metaWF$CLR = 1'b0 ;
assign metaWF$DEQ = CAN_FIRE_RL_wrtSer_begin ;
assign metaWF$D_IN = { wsiS_reqFifo$D_OUT[7:0], btm__h17027 } ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$ENQ = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wide16Fa
assign wide16Fa$CLR = 1'b0 ;
assign wide16Fa$ENQ =
WILL_FIRE_RL_wrtSer_begin &&
(wrtSerPos == 2'd3 || metaWF$D_OUT[23:0] == 24'd0) ||
WILL_FIRE_RL_wrtSer_body &&
(wrtSerPos == 2'd3 || wrtSerUnroll == 16'd1) ;
assign wide16Fa$D_IN =
MUX_wide16Fa$enq_1__SEL_1 ?
MUX_wide16Fa$enq_1__VAL_1 :
MUX_wide16Fa$enq_1__VAL_2 ;
assign wide16Fa$DEQ = WILL_FIRE_RL_delay_write_req ;
// submodule wide16Fb
assign wide16Fb$D_IN = wmemi_respF$D_OUT[127:0] ;
assign wide16Fb$DEQ = CAN_FIRE_RL_delay_Fb2Fc ;
assign wide16Fb$ENQ = CAN_FIRE_RL_delay_read_resp ;
assign wide16Fb$CLR = 1'b0 ;
// submodule wide16Fc
assign wide16Fc$D_IN = wide16Fb$D_OUT ;
assign wide16Fc$ENQ = CAN_FIRE_RL_delay_Fb2Fc ;
assign wide16Fc$DEQ =
MUX_rdSerEmpty$write_1__PSEL_1 &&
(rdSerEmpty || rdSerPos == 2'd0) ;
assign wide16Fc$CLR = 1'b0 ;
// submodule wmemi_respF
assign wmemi_respF$D_IN = wmemi_wmemiResponse$wget ;
assign wmemi_respF$DEQ = CAN_FIRE_RL_delay_read_resp ;
assign wmemi_respF$ENQ =
WILL_FIRE_RL_wmemi_respAdvance && wmemi_respF$FULL_N ;
assign wmemi_respF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$ENQ = wsiS_reqFifo_r_enq$whas ;
assign wsiS_reqFifo$CLR = 1'b0 ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
// remaining internal signals
assign IF_wrtSerPos_80_EQ_0_81_OR_wrtSerPos_80_EQ_1_8_ETC___d399 =
CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 &&
(wrtSerPos != 2'd3 && wrtSerUnroll != 16'd1 ||
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q2) ;
assign IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_mesgWF_w_ETC___d423 =
{ (wrtSerPos == 2'd2) ? 32'h0 : x__h17993[31:0],
(wrtSerPos == 2'd2) ? x__h17993[31:0] : wrtSerStage_2,
wrtSerStage_1,
wrtSerStage } ;
assign IF_wrtSerPos_80_EQ_2_83_THEN_0x0_ELSE_metaWF_f_ETC___d446 =
{ (wrtSerPos == 2'd2) ? 32'h0 : metaWF$D_OUT,
(wrtSerPos == 2'd2) ? metaWF$D_OUT : wrtSerStage_2,
wrtSerStage_1,
wrtSerStage } ;
assign NOT_mesgWF_rRdPtr_69_EQ_mesgWF_rWrPtr_71_74___d175 =
mesgWF_rRdPtr != mesgWF_rWrPtr ;
assign NOT_mesgWF_rRdPtr_69_PLUS_2048_70_EQ_mesgWF_rW_ETC___d173 =
mesgWF_rRdPtr + 13'd2048 != mesgWF_rWrPtr ;
assign NOT_wrtSerPos_80_EQ_3_87_88_AND_NOT_metaWF_fir_ETC___d434 =
wrtSerPos != 2'd3 && metaWF$D_OUT[23:0] != 24'd0 ||
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q2 ;
assign addr__h19478 = { 9'd0, x__h19536 } ;
assign addr__h19647 = { 9'd0, x__h19692 } ;
assign btm__h17027 =
{ wsiS_reqFifo$D_OUT[308] ?
{ 7'd0, wsiS_reqFifo$D_OUT[307:296] } :
{ 5'd0, mesgLengthSoFar_05_PLUS_1___d985 },
5'd0 } ;
assign bytesWritten_6_ULT_dlyHoldoffBytes_6___d908 =
bytesWritten < dlyHoldoffBytes ;
assign cyclesPassed_54_ULT_dlyHoldoffCycles_8___d903 =
cyclesPassed < dlyHoldoffCycles ;
assign delayStatus__h21797 =
{ 14'h0,
!dlyWordsStored_value_26_SLE_0___d909 &&
!bytesWritten_6_ULT_dlyHoldoffBytes_6___d908 &&
!cyclesPassed_54_ULT_dlyHoldoffCycles_8___d903,
dlyWordsStored_value_26_SLE_0_49_OR_bytesWritt_ETC___d164,
dlyWordsStored_value_26_SLT_8388608___d165,
wsiM_reqFifo_c_r != 2'd2,
metaWF$FULL_N,
metaWF$EMPTY_N,
NOT_mesgWF_rRdPtr_69_PLUS_2048_70_EQ_mesgWF_rW_ETC___d173,
NOT_mesgWF_rRdPtr_69_EQ_mesgWF_rWrPtr_71_74___d175,
metaRF$FULL_N,
metaRF$EMPTY_N,
mesgRF$FULL_N,
mesgRF$EMPTY_N,
wide16Fa$FULL_N,
wide16Fa$EMPTY_N,
wide16Fb$FULL_N,
wide16Fb$EMPTY_N,
wide16Fc$FULL_N,
wide16Fc$EMPTY_N } ;
assign dlyWordsStored_value_26_SLE_0_49_OR_bytesWritt_ETC___d164 =
dlyWordsStored_value_26_SLE_0___d909 ||
bytesWritten_6_ULT_dlyHoldoffBytes_6___d908 ||
cyclesPassed_54_ULT_dlyHoldoffCycles_8___d903 ||
wsiM_reqFifo_c_r == 2'd2 ||
tog50 ;
assign dlyWordsStored_value_26_SLE_0___d909 =
(dlyWordsStored_value ^ 25'h1000000) <= 25'd16777216 ;
assign dlyWordsStored_value_26_SLT_8388608___d165 =
(dlyWordsStored_value ^ 25'h1000000) < 25'd25165824 ;
assign mesgLengthSoFar_05_PLUS_1___d985 = mesgLengthSoFar + 14'd1 ;
assign mesgRF_i_notFull__74_AND_NOT_rdSerEmpty_75_76__ETC___d285 =
mesgRF$FULL_N &&
(!rdSerEmpty && rdSerPos != 2'd0 || wide16Fc$EMPTY_N) ;
assign metaRF_i_notFull__18_AND_NOT_rdSerEmpty_75_76__ETC___d319 =
metaRF$FULL_N &&
(!rdSerEmpty && rdSerPos != 2'd0 || wide16Fc$EMPTY_N) ;
assign rdat__h22255 = hasDebugLogic ? mesgWtCount : 32'd0 ;
assign rdat__h22261 = hasDebugLogic ? mesgRdCount : 32'd0 ;
assign rdat__h22267 = hasDebugLogic ? bytesWritten : 32'd0 ;
assign rdat__h22273 = hasDebugLogic ? { 8'd0, x__h22277 } : 32'd0 ;
assign rdat__h22397 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h22411 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h22419 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h22425 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h22439 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h22447 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h22453 = hasDebugLogic ? wmemiWrReq : 32'd0 ;
assign rdat__h22459 = hasDebugLogic ? wmemiRdReq : 32'd0 ;
assign rdat__h22465 = hasDebugLogic ? wmemiRdResp1 : 32'd0 ;
assign rdat__h22471 =
hasDebugLogic ?
{ {7{dlyWordsStored_value[24]}}, dlyWordsStored_value } :
32'd0 ;
assign rdat__h22482 =
hasDebugLogic ?
{ {24{dlyReadCredit_value[7]}}, dlyReadCredit_value } :
32'd0 ;
assign rdat__h22493 = hasDebugLogic ? { 9'd0, dlyWAG } : 32'd0 ;
assign rdat__h22504 = hasDebugLogic ? { 9'd0, dlyRAG } : 32'd0 ;
assign rdat__h22525 = hasDebugLogic ? wmemiRdResp2 : 32'd0 ;
assign rdat__h22580 =
{ {16{dlyReadyToWrite_value[15]}}, dlyReadyToWrite_value } ;
assign rdat__h22589 = { 16'd0, wrtSerUnroll } ;
assign rdat__h22598 = { 8'd0, bytesThisMessage } ;
assign rdat__h22607 = { 18'd0, mesgLengthSoFar } ;
assign v__h20254 = metaRF$D_IN ;
assign wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d352 =
wci_cState == 3'd2 && dlyCtrl[3:0] == 4'h7 &&
!dlyWordsStored_value_26_SLE_0___d909 &&
!bytesWritten_6_ULT_dlyHoldoffBytes_6___d908 &&
!cyclesPassed_54_ULT_dlyHoldoffCycles_8___d903 ;
assign wrtSerPos_80_PLUS_1___d984 = wrtSerPos + 2'd1 ;
assign wsiS_reqFifo_notFull__05_AND_wsiS_burstKind_85_ETC___d725 =
wsiS_reqFifo$FULL_N &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[309]) ;
assign x__h14965 = mesgWF_rRdPtr + 13'd1 ;
assign x__h15073 =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_2 ?
wsiS_reqFifo$D_OUT[295:40] :
256'd0 ;
assign x__h17993 =
(mesgWF_rCache[269] && mesgWF_rCache[268:256] == mesgWF_rRdPtr) ?
mesgWF_rCache[255:0] :
mesgWF_memory$DOB ;
assign x__h18132 = { 96'd0, x__h17993[31:0] } ;
assign x__h18163 = { 64'd0, x__h17993[31:0], wrtSerStage } ;
assign x__h18794 = { 96'd0, metaWF$D_OUT } ;
assign x__h18821 = { 64'd0, metaWF$D_OUT, wrtSerStage } ;
assign x__h19536 = { dlyRAG, 4'h0 } ;
assign x__h19692 = { dlyWAG, 4'h0 } ;
assign x__h22277 = { wmemi_statusR, wsiS_statusR, wsiM_statusR } ;
assign x_burstLength__h19976 =
(readMeta[23:0] == 24'd0) ? 12'd1 : readMeta[16:5] ;
assign x_byteEn__h19977 = (readMeta[23:0] == 24'd0) ? 32'd0 : 32'hFFFFFFFF ;
always@(wrtSerPos)
begin
case (wrtSerPos)
2'd0, 2'd1, 2'd2, 2'd3: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'd1;
endcase
end
always@(wrtSerPos or wide16Fa$FULL_N)
begin
case (wrtSerPos)
2'd0, 2'd1, 2'd2:
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q2 =
wide16Fa$FULL_N;
2'd3:
CASE_wrtSerPos_NOT_wrtSerPos_EQ_3_OR_wide16Fa_ETC__q2 =
wrtSerPos != 2'd3 || wide16Fa$FULL_N;
endcase
end
always@(wci_reqF$D_OUT or
dlyCtrl or
dlyHoldoffBytes or
dlyHoldoffCycles or
rdat__h22255 or
rdat__h22261 or
rdat__h22267 or
rdat__h22273 or
rdat__h22397 or
rdat__h22411 or
rdat__h22419 or
rdat__h22425 or
rdat__h22439 or
rdat__h22447 or
rdat__h22453 or
rdat__h22459 or
rdat__h22465 or
rdat__h22471 or
rdat__h22482 or
rdat__h22493 or
rdat__h22504 or
dlyRdOpZero or
dlyRdOpOther or
rdat__h22525 or
delayStatus__h21797 or
rdat__h22580 or rdat__h22589 or rdat__h22598 or rdat__h22607)
begin
case (wci_reqF$D_OUT[51:32])
20'h0: x_data__h22228 = dlyCtrl;
20'h00004: x_data__h22228 = dlyHoldoffBytes;
20'h00008: x_data__h22228 = dlyHoldoffCycles;
20'h0000C: x_data__h22228 = rdat__h22255;
20'h00010: x_data__h22228 = rdat__h22261;
20'h00014: x_data__h22228 = rdat__h22267;
20'h00018: x_data__h22228 = rdat__h22273;
20'h0001C: x_data__h22228 = 32'd0;
20'h00020: x_data__h22228 = rdat__h22397;
20'h00024: x_data__h22228 = rdat__h22411;
20'h00028: x_data__h22228 = rdat__h22419;
20'h0002C: x_data__h22228 = rdat__h22425;
20'h00030: x_data__h22228 = rdat__h22439;
20'h00034: x_data__h22228 = rdat__h22447;
20'h00038: x_data__h22228 = rdat__h22453;
20'h0003C: x_data__h22228 = rdat__h22459;
20'h00040: x_data__h22228 = rdat__h22465;
20'h00044: x_data__h22228 = rdat__h22471;
20'h00048: x_data__h22228 = rdat__h22482;
20'h0004C: x_data__h22228 = rdat__h22493;
20'h00050: x_data__h22228 = rdat__h22504;
20'h00058: x_data__h22228 = dlyRdOpZero;
20'h0005C: x_data__h22228 = dlyRdOpOther;
20'h00060: x_data__h22228 = rdat__h22525;
20'h00064: x_data__h22228 = delayStatus__h21797;
20'h00068: x_data__h22228 = rdat__h22580;
20'h0006C: x_data__h22228 = rdat__h22589;
20'h00070: x_data__h22228 = rdat__h22598;
20'h00074: x_data__h22228 = rdat__h22607;
default: x_data__h22228 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (!wciS0_MReset_n)
begin
bytesRead <= `BSV_ASSIGNMENT_DELAY 32'd0;
bytesThisMessage <= `BSV_ASSIGNMENT_DELAY 24'd0;
bytesWritten <= `BSV_ASSIGNMENT_DELAY 32'd0;
cyclesPassed <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyCtrl <= `BSV_ASSIGNMENT_DELAY dlyCtrlInit;
dlyHoldoffBytes <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyHoldoffCycles <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyRAG <= `BSV_ASSIGNMENT_DELAY 23'd0;
dlyRdOpOther <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyRdOpZero <= `BSV_ASSIGNMENT_DELAY 32'd0;
dlyReadCredit_value <= `BSV_ASSIGNMENT_DELAY 8'd0;
dlyReadyToWrite_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
dlyWAG <= `BSV_ASSIGNMENT_DELAY 23'd0;
dlyWordsStored_value <= `BSV_ASSIGNMENT_DELAY 25'd0;
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
mesgRdCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
mesgWF_rCache <= `BSV_ASSIGNMENT_DELAY
270'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mesgWF_rRdPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
mesgWF_rWrPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
mesgWtCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdSerAddr <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdSerEmpty <= `BSV_ASSIGNMENT_DELAY 1'd1;
rdSerPos <= `BSV_ASSIGNMENT_DELAY 2'd0;
rdSerUnroll <= `BSV_ASSIGNMENT_DELAY 16'd0;
rdSyncWord <= `BSV_ASSIGNMENT_DELAY 1'd0;
tog50 <= `BSV_ASSIGNMENT_DELAY 1'd0;
unrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'd7;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY
146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA;
wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA;
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wrtSerAddr <= `BSV_ASSIGNMENT_DELAY 32'd0;
wrtSerPos <= `BSV_ASSIGNMENT_DELAY 2'd0;
wrtSerUnroll <= `BSV_ASSIGNMENT_DELAY 16'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (bytesRead$EN) bytesRead <= `BSV_ASSIGNMENT_DELAY bytesRead$D_IN;
if (bytesThisMessage$EN)
bytesThisMessage <= `BSV_ASSIGNMENT_DELAY bytesThisMessage$D_IN;
if (bytesWritten$EN)
bytesWritten <= `BSV_ASSIGNMENT_DELAY bytesWritten$D_IN;
if (cyclesPassed$EN)
cyclesPassed <= `BSV_ASSIGNMENT_DELAY cyclesPassed$D_IN;
if (dlyCtrl$EN) dlyCtrl <= `BSV_ASSIGNMENT_DELAY dlyCtrl$D_IN;
if (dlyHoldoffBytes$EN)
dlyHoldoffBytes <= `BSV_ASSIGNMENT_DELAY dlyHoldoffBytes$D_IN;
if (dlyHoldoffCycles$EN)
dlyHoldoffCycles <= `BSV_ASSIGNMENT_DELAY dlyHoldoffCycles$D_IN;
if (dlyRAG$EN) dlyRAG <= `BSV_ASSIGNMENT_DELAY dlyRAG$D_IN;
if (dlyRdOpOther$EN)
dlyRdOpOther <= `BSV_ASSIGNMENT_DELAY dlyRdOpOther$D_IN;
if (dlyRdOpZero$EN)
dlyRdOpZero <= `BSV_ASSIGNMENT_DELAY dlyRdOpZero$D_IN;
if (dlyReadCredit_value$EN)
dlyReadCredit_value <= `BSV_ASSIGNMENT_DELAY
dlyReadCredit_value$D_IN;
if (dlyReadyToWrite_value$EN)
dlyReadyToWrite_value <= `BSV_ASSIGNMENT_DELAY
dlyReadyToWrite_value$D_IN;
if (dlyWAG$EN) dlyWAG <= `BSV_ASSIGNMENT_DELAY dlyWAG$D_IN;
if (dlyWordsStored_value$EN)
dlyWordsStored_value <= `BSV_ASSIGNMENT_DELAY
dlyWordsStored_value$D_IN;
if (mesgLengthSoFar$EN)
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar$D_IN;
if (mesgRdCount$EN)
mesgRdCount <= `BSV_ASSIGNMENT_DELAY mesgRdCount$D_IN;
if (mesgWF_rCache$EN)
mesgWF_rCache <= `BSV_ASSIGNMENT_DELAY mesgWF_rCache$D_IN;
if (mesgWF_rRdPtr$EN)
mesgWF_rRdPtr <= `BSV_ASSIGNMENT_DELAY mesgWF_rRdPtr$D_IN;
if (mesgWF_rWrPtr$EN)
mesgWF_rWrPtr <= `BSV_ASSIGNMENT_DELAY mesgWF_rWrPtr$D_IN;
if (mesgWtCount$EN)
mesgWtCount <= `BSV_ASSIGNMENT_DELAY mesgWtCount$D_IN;
if (rdSerAddr$EN) rdSerAddr <= `BSV_ASSIGNMENT_DELAY rdSerAddr$D_IN;
if (rdSerEmpty$EN)
rdSerEmpty <= `BSV_ASSIGNMENT_DELAY rdSerEmpty$D_IN;
if (rdSerPos$EN) rdSerPos <= `BSV_ASSIGNMENT_DELAY rdSerPos$D_IN;
if (rdSerUnroll$EN)
rdSerUnroll <= `BSV_ASSIGNMENT_DELAY rdSerUnroll$D_IN;
if (rdSyncWord$EN)
rdSyncWord <= `BSV_ASSIGNMENT_DELAY rdSyncWord$D_IN;
if (tog50$EN) tog50 <= `BSV_ASSIGNMENT_DELAY tog50$D_IN;
if (unrollCnt$EN) unrollCnt <= `BSV_ASSIGNMENT_DELAY unrollCnt$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wmemiRdReq$EN)
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY wmemiRdReq$D_IN;
if (wmemiRdResp1$EN)
wmemiRdResp1 <= `BSV_ASSIGNMENT_DELAY wmemiRdResp1$D_IN;
if (wmemiRdResp2$EN)
wmemiRdResp2 <= `BSV_ASSIGNMENT_DELAY wmemiRdResp2$D_IN;
if (wmemiWrReq$EN)
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY wmemiWrReq$D_IN;
if (wmemi_busyWithMessage$EN)
wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY
wmemi_busyWithMessage$D_IN;
if (wmemi_dhF_c_r$EN)
wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_c_r$D_IN;
if (wmemi_dhF_q_0$EN)
wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_0$D_IN;
if (wmemi_dhF_q_1$EN)
wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_1$D_IN;
if (wmemi_errorSticky$EN)
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemi_errorSticky$D_IN;
if (wmemi_operateD$EN)
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD$D_IN;
if (wmemi_peerIsReady$EN)
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady$D_IN;
if (wmemi_reqF_c_r$EN)
wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_c_r$D_IN;
if (wmemi_reqF_q_0$EN)
wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_0$D_IN;
if (wmemi_reqF_q_1$EN)
wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_1$D_IN;
if (wmemi_trafficSticky$EN)
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wmemi_trafficSticky$D_IN;
if (wrtSerAddr$EN)
wrtSerAddr <= `BSV_ASSIGNMENT_DELAY wrtSerAddr$D_IN;
if (wrtSerPos$EN) wrtSerPos <= `BSV_ASSIGNMENT_DELAY wrtSerPos$D_IN;
if (wrtSerUnroll$EN)
wrtSerUnroll <= `BSV_ASSIGNMENT_DELAY wrtSerUnroll$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (rdSerMeta$EN) rdSerMeta <= `BSV_ASSIGNMENT_DELAY rdSerMeta$D_IN;
if (rdSerStage$EN) rdSerStage <= `BSV_ASSIGNMENT_DELAY rdSerStage$D_IN;
if (rdSerStage_1$EN)
rdSerStage_1 <= `BSV_ASSIGNMENT_DELAY rdSerStage_1$D_IN;
if (rdSerStage_2$EN)
rdSerStage_2 <= `BSV_ASSIGNMENT_DELAY rdSerStage_2$D_IN;
if (rdSerStage_3$EN)
rdSerStage_3 <= `BSV_ASSIGNMENT_DELAY rdSerStage_3$D_IN;
if (readMeta$EN) readMeta <= `BSV_ASSIGNMENT_DELAY readMeta$D_IN;
if (wmemi_statusR$EN)
wmemi_statusR <= `BSV_ASSIGNMENT_DELAY wmemi_statusR$D_IN;
if (wrtSerStage$EN) wrtSerStage <= `BSV_ASSIGNMENT_DELAY wrtSerStage$D_IN;
if (wrtSerStage_1$EN)
wrtSerStage_1 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_1$D_IN;
if (wrtSerStage_2$EN)
wrtSerStage_2 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_2$D_IN;
if (wrtSerStage_3$EN)
wrtSerStage_3 <= `BSV_ASSIGNMENT_DELAY wrtSerStage_3$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
bytesRead = 32'hAAAAAAAA;
bytesThisMessage = 24'hAAAAAA;
bytesWritten = 32'hAAAAAAAA;
cyclesPassed = 32'hAAAAAAAA;
dlyCtrl = 32'hAAAAAAAA;
dlyHoldoffBytes = 32'hAAAAAAAA;
dlyHoldoffCycles = 32'hAAAAAAAA;
dlyRAG = 23'h2AAAAA;
dlyRdOpOther = 32'hAAAAAAAA;
dlyRdOpZero = 32'hAAAAAAAA;
dlyReadCredit_value = 8'hAA;
dlyReadyToWrite_value = 16'hAAAA;
dlyWAG = 23'h2AAAAA;
dlyWordsStored_value = 25'h0AAAAAA;
mesgLengthSoFar = 14'h2AAA;
mesgRdCount = 32'hAAAAAAAA;
mesgWF_rCache =
270'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mesgWF_rRdPtr = 13'h0AAA;
mesgWF_rWrPtr = 13'h0AAA;
mesgWtCount = 32'hAAAAAAAA;
rdSerAddr = 32'hAAAAAAAA;
rdSerEmpty = 1'h0;
rdSerMeta = 32'hAAAAAAAA;
rdSerPos = 2'h2;
rdSerStage = 32'hAAAAAAAA;
rdSerStage_1 = 32'hAAAAAAAA;
rdSerStage_2 = 32'hAAAAAAAA;
rdSerStage_3 = 32'hAAAAAAAA;
rdSerUnroll = 16'hAAAA;
rdSyncWord = 1'h0;
readMeta = 32'hAAAAAAAA;
tog50 = 1'h0;
unrollCnt = 16'hAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wmemiRdReq = 32'hAAAAAAAA;
wmemiRdResp1 = 32'hAAAAAAAA;
wmemiRdResp2 = 32'hAAAAAAAA;
wmemiWrReq = 32'hAAAAAAAA;
wmemi_busyWithMessage = 1'h0;
wmemi_dhF_c_r = 2'h2;
wmemi_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_errorSticky = 1'h0;
wmemi_operateD = 1'h0;
wmemi_peerIsReady = 1'h0;
wmemi_reqF_c_r = 2'h2;
wmemi_reqF_q_0 = 52'hAAAAAAAAAAAAA;
wmemi_reqF_q_1 = 52'hAAAAAAAAAAAAA;
wmemi_statusR = 8'hAA;
wmemi_trafficSticky = 1'h0;
wrtSerAddr = 32'hAAAAAAAA;
wrtSerPos = 2'h2;
wrtSerStage = 32'hAAAAAAAA;
wrtSerStage_1 = 32'hAAAAAAAA;
wrtSerStage_2 = 32'hAAAAAAAA;
wrtSerStage_3 = 32'hAAAAAAAA;
wrtSerUnroll = 16'hAAAA;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3716 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3716,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DelayWorker.bsv\", line 443, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/DelayWorker.bsv\", line 392, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DelayWorker.bsv\", line 392, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h22096 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting DelayWorker dlyCtrl:%0x",
v__h22096,
dlyCtrl);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/DelayWorker.bsv\", line 430, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_OrE fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DelayWorker.bsv\", line 430, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/DelayWorker.bsv\", line 430, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_cfrd fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h2817 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h2817,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h2670 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h2670,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/DelayWorker.bsv\", line 381, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/DelayWorker.bsv\", line 381, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DelayWorker.bsv\", line 381, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/DelayWorker.bsv\", line 381, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_cfrd fired in the same clock\n cycle.\n");
end
// synopsys translate_on
endmodule // mkDelayWorker32B
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_TB_V
|
// cog
// 2014_08_10 - added patch for reset problem - PIK33/CGRACEY
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
ADD
instruction mnem oper R C Z +- C D S
----------------------------------------------------------------------------
000000 ZC0ICCCC DDDDDDDDD SSSSSSSSS WRBYTE D,S _______ __________
000000 ZC1ICCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S B______ __________
000001 ZC0ICCCC DDDDDDDDD SSSSSSSSS WRWORD D,S _______ __________
000001 ZC1ICCCC DDDDDDDDD SSSSSSSSS RDWORD D,S B______ __________
000010 ZC0ICCCC DDDDDDDDD SSSSSSSSS WRLONG D,S _______ __________
000010 ZC1ICCCC DDDDDDDDD SSSSSSSSS RDLONG D,S B______ __________
000011 ZCRICCCC DDDDDDDDD SSSSSSSSS SYSOP D,S B__B___ __________
000100 ZCRICCCC DDDDDDDDD SSSSSSSSS * <MUL> D,S M__M__Z __________
000101 ZCRICCCC DDDDDDDDD SSSSSSSSS * <MULS> D,S M__M__Z __________
000110 ZCRICCCC DDDDDDDDD SSSSSSSSS * <ENC> D,S E_____Z __________
000111 ZCRICCCC DDDDDDDDD SSSSSSSSS * <ONES> D,S E_____Z __________
001000 ZCRICCCC DDDDDDDDD SSSSSSSSS ROR D,S R__R__Z __________
001001 ZCRICCCC DDDDDDDDD SSSSSSSSS ROL D,S R__R__Z __________
001010 ZCRICCCC DDDDDDDDD SSSSSSSSS SHR D,S R__R__Z __________
001011 ZCRICCCC DDDDDDDDD SSSSSSSSS SHL D,S R__R__Z __________
001100 ZCRICCCC DDDDDDDDD SSSSSSSSS RCR D,S R__R__Z __________
001101 ZCRICCCC DDDDDDDDD SSSSSSSSS RCL D,S R__R__Z __________
001110 ZCRICCCC DDDDDDDDD SSSSSSSSS SAR D,S R__R__Z __________
001111 ZCRICCCC DDDDDDDDD SSSSSSSSS REV D,S R__R__Z __________
010000 ZCRICCCC DDDDDDDDD SSSSSSSSS MINS D,S L__As_Z 1__0__1__1
010001 ZCRICCCC DDDDDDDDD SSSSSSSSS MAXS D,S L__As_Z 1__0__1__1
010010 ZCRICCCC DDDDDDDDD SSSSSSSSS MIN D,S L__Au_Z 1__0__1__1
010011 ZCRICCCC DDDDDDDDD SSSSSSSSS MAX D,S L__Au_Z 1__0__1__1
010100 ZCRICCCC DDDDDDDDD SSSSSSSSS MOVS D,S L______ __________
010101 ZCRICCCC DDDDDDDDD SSSSSSSSS MOVD D,S L______ __________
010110 ZCRICCCC DDDDDDDDD SSSSSSSSS MOVI D,S L______ __________
010111 ZCRICCCC DDDDDDDDD SSSSSSSSS JMPRET D,S L______ __________
011000 ZCRICCCC DDDDDDDDD SSSSSSSSS AND D,S L__L__Z __________
011001 ZCRICCCC DDDDDDDDD SSSSSSSSS ANDN D,S L__L__Z __________
011010 ZCRICCCC DDDDDDDDD SSSSSSSSS OR D,S L__L__Z __________
011011 ZCRICCCC DDDDDDDDD SSSSSSSSS XOR D,S L__L__Z __________
011100 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXC D,S L__L__Z __________
011101 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXNC D,S L__L__Z __________
011110 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXZ D,S L__L__Z __________
011111 ZCRICCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S L__L__Z __________
100000 ZCRICCCC DDDDDDDDD SSSSSSSSS ADD D,S A__Au_Z 0__0__1__1
100001 ZCRICCCC DDDDDDDDD SSSSSSSSS SUB D,S A__Au_Z 1__0__1__1
100010 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDABS D,S A__Au_Z M__0__1__1
100011 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBABS D,S A__Au_Z Mn_0__1__1
100100 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMC D,S A__Ao_Z C__0__1__1
100101 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMNC D,S A__Ao_Z Cn_0__1__1
100110 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMZ D,S A__Ao_Z Z__0__1__1
100111 ZCRICCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S A__Ao_Z Zn_0__1__1
101000 ZCRICCCC DDDDDDDDD SSSSSSSSS MOV D,S A__Am_Z 0__0__0__1
101001 ZCRICCCC DDDDDDDDD SSSSSSSSS NEG D,S A__Am_Z 1__0__0__1
101010 ZCRICCCC DDDDDDDDD SSSSSSSSS ABS D,S A__Am_Z M__0__0__1
101011 ZCRICCCC DDDDDDDDD SSSSSSSSS ABSNEG D,S A__Am_Z Mn_0__0__1
101100 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGC D,S A__Am_Z C__0__0__1
101101 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGNC D,S A__Am_Z Cn_0__0__1
101110 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGZ D,S A__Am_Z Z__0__0__1
101111 ZCRICCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S A__Am_Z Zn_0__0__1
110000 ZCRICCCC DDDDDDDDD SSSSSSSSS CMPS D,S A__As_Z 1__0__1__1
110001 ZCRICCCC DDDDDDDDD SSSSSSSSS CMPSX D,S A__As_Z& 1__C__1__1
110010 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDX D,S A__Au_Z& 0__C__1__1
110011 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBX D,S A__Au_Z& 1__C__1__1
110100 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDS D,S A__Ao_Z 0__0__1__1
110101 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBS D,S A__Ao_Z 1__0__1__1
110110 ZCRICCCC DDDDDDDDD SSSSSSSSS ADDSX D,S A__Ao_Z& 0__C__1__1
110111 ZCRICCCC DDDDDDDDD SSSSSSSSS SUBSX D,S A__Ao_Z& 1__C__1__1
111000 ZCRICCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S A__Ac_Z 1__0__1__1
111001 ZCRICCCC DDDDDDDDD SSSSSSSSS DJNZ D,S A__Au_Z 1__1__1__0
111010 ZCRICCCC DDDDDDDDD SSSSSSSSS TJNZ D,S A__Au_Z 1__0__1__0
111011 ZCRICCCC DDDDDDDDD SSSSSSSSS TJZ D,S A__Au_Z 1__0__1__0
111100 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S _______ __________
111101 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S _______ __________
111110 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S A__Au_Z 0__0__1__1
111111 ZCRICCCC DDDDDDDDD SSSSSSSSS WAITVID D,S _______ __________
----------------------------------------------------------------------------
* future instructions
ZCR effects
----------------------------------------------------------------------------
000 nz, nc, nr
001 nz, nc, r
010 nz, c, nr
011 nz, c, r
100 z, nc, nr
101 z, nc, r
110 z, c, nr
111 z, c, r
CCCC condition (easier-to-read list)
----------------------------------------------------------------------------
0000 never 1111 always (default)
0001 nc & nz 1100 if_c if_b
0010 nc & z 0011 if_nc if_ae
0011 nc 1010 if_z if_e
0100 c & nz 0101 if_nz if_ne
0101 nz 1000 if_c_and_z if_z_and_c
0110 c <> z 0100 if_c_and_nz if_nz_and_c
0111 nc | nz 0010 if_nc_and_z if_z_and_nc
1000 c & z 0001 if_nc_and_nz if_nz_and_nc if_a
1001 c = z 1110 if_c_or_z if_z_or_c if_be
1010 z 1101 if_c_or_nz if_nz_or_c
1011 nc | z 1011 if_nc_or_z if_z_or_nc
1100 c 0111 if_nc_or_nz if_nz_or_nc
1101 c | nz 1001 if_c_eq_z if_z_eq_c
1110 c | z 0110 if_c_ne_z if_z_ne_c
1111 always 0000 never
I SSSSSSSSS source operand
----------------------------------------------------------------------------
0 SSSSSSSSS register
1 #SSSSSSSSS immediate, zero-extended
DDDDDDDDD destination operand
----------------------------------------------------------------------------
DDDDDDDDD register
*/
`include "cog_ram.v"
`include "cog_alu.v"
`include "cog_ctr.v"
`include "cog_vid.v"
module cog
(
input nres, // reset
input clk_pll, // clocks
input clk_cog,
input ena_bus,
input ptr_w, // pointers
input [27:0] ptr_d,
input ena, // control
input bus_sel, // bus
output bus_r,
output bus_e,
output bus_w,
output [1:0] bus_s,
output [15:0] bus_a,
output [31:0] bus_d,
input [31:0] bus_q,
input bus_c,
input bus_ack,
input [31:0] cnt, // counter
input [7:0] pll_in, // pll's
output pll_out,
input [31:0] pin_in, // pins
output [31:0] pin_out,
output [31:0] pin_dir
);
parameter oh = 31;
parameter ol = 26;
parameter wz = 25;
parameter wc = 24;
parameter wr = 23;
parameter im = 22;
parameter ch = 21;
parameter cl = 18;
parameter dh = 17;
parameter dl = 9;
parameter sh = 8;
parameter sl = 0;
// pointers
reg [27:0] ptr;
always @(posedge clk_cog or negedge nres)
if (!nres)
ptr <= 27'b00000000000000_11111000000000;
else if (ena_bus && ptr_w)
ptr <= ptr_d;
// load/run
reg run;
always @(posedge clk_cog or negedge ena)
if (!ena)
run <= 1'b0;
else if (m[3] && (&px))
run <= 1'b1;
// state
reg [4:0] m;
always @(posedge clk_cog or negedge ena)
if (!ena)
m <= 5'b0;
else
m <= { (m[2] || m[4]) && waiti, // m[4] = wait
(m[2] || m[4]) && !waiti, // m[3] = write d
m[1], // m[2] = read next instruction
m[0], // m[1] = read d
!m[4] && !m[2] && !m[1] && !m[0] }; // m[0] = read s
// process
reg [8:0] p;
reg c;
reg z;
always @(posedge clk_cog or negedge ena)
if (!ena)
p <= 1'b0;
else if (m[3] && !(cond && jump_cancel))
p <= px + 1'b1;
always @(posedge clk_cog or negedge ena)
if (!ena)
c <= 1'b0;
else if (m[3] && cond && i[wc])
c <= alu_co;
always @(posedge clk_cog or negedge ena)
if (!ena)
z <= 1'b0;
else if (m[3] && cond && i[wz])
z <= alu_zo;
// addressable registers
//
// addr read write
// ------------------------
//
// 000-1EF RAM RAM
//
// 1F0 PAR RAM
// 1F1 CNT RAM
// 1F2 INA RAM
// 1F3 INB * RAM
// 1F4 RAM RAM+OUTA
// 1F5 RAM RAM+OUTB *
// 1F6 RAM RAM+DIRA
// 1F7 RAM RAM+DIRB *
// 1F8 RAM RAM+CTRA
// 1F9 RAM RAM+CTRB
// 1FA RAM RAM+FRQA
// 1FB RAM RAM+FRQB
// 1FC PHSA RAM+PHSA
// 1FD PHSB RAM+PHSB
// 1FE RAM RAM+VCFG
// 1FF RAM RAM+VSCL
//
// * future 64-pin version
wire wio = m[3] && cond && i[wr] && (&i[dh:dl+4]);
wire setouta = wio && i[dl+3:dl] == 4'h4;
wire setdira = wio && i[dl+3:dl] == 4'h6;
wire setctra = wio && i[dl+3:dl] == 4'h8;
wire setctrb = wio && i[dl+3:dl] == 4'h9;
wire setfrqa = wio && i[dl+3:dl] == 4'hA;
wire setfrqb = wio && i[dl+3:dl] == 4'hB;
wire setphsa = wio && i[dl+3:dl] == 4'hC;
wire setphsb = wio && i[dl+3:dl] == 4'hD;
wire setvid = wio && i[dl+3:dl] == 4'hE;
wire setscl = wio && i[dl+3:dl] == 4'hF;
// register ram
wire ram_ena = m[0] || m[1] || m[2] || m[3] && cond && i[wr];
wire ram_w = m[3] && alu_wr;
wire [8:0] ram_a = m[2] ? px
: m[0] ? i[sh:sl]
: i[dh:dl];
wire [31:0] ram_q;
cog_ram cog_ram_ ( .clk (clk_cog),
.ena (ram_ena),
.w (ram_w),
.a (ram_a),
.d (alu_r),
.q (ram_q) );
// outa/dira
reg [31:0] outa;
reg [31:0] dira;
always @(posedge clk_cog)
if (setouta)
outa <= alu_r;
always @(posedge clk_cog or negedge ena)
if (!ena)
dira <= 32'b0;
else if (setdira)
dira <= alu_r;
// ctra/ctrb
wire [32:0] phsa;
wire [31:0] ctra_pin_out;
wire plla;
cog_ctr cog_ctra ( .clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena (ena),
.setctr (setctra),
.setfrq (setfrqa),
.setphs (setphsa),
.data (alu_r),
.pin_in (pin_in),
.phs (phsa),
.pin_out (ctra_pin_out),
.pll (plla) );
wire [32:0] phsb;
wire [31:0] ctrb_pin_out;
wire pllb;
cog_ctr cog_ctrb ( .clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena (ena),
.setctr (setctrb),
.setfrq (setfrqb),
.setphs (setphsb),
.data (alu_r),
.pin_in (pin_in),
.phs (phsb),
.pin_out (ctrb_pin_out),
.pll (pllb) );
assign pll_out = plla;
// vid
wire vidack;
wire [31:0] vid_pin_out;
cog_vid cog_vid_ ( .clk_cog (clk_cog),
.clk_vid (plla),
.ena (ena),
.setvid (setvid),
.setscl (setscl),
.data (alu_r),
.pixel (s),
.color (d),
.aural (pll_in),
.carrier (pllb),
.ack (vidack),
.pin_out (vid_pin_out) );
// instruction
reg [31:0] ix;
always @(posedge clk_cog)
if (m[3])
ix <= ram_q;
wire [31:0] i = run ? ix : {14'b000010_001_0_0001, p, 9'b000000000};
// source
reg [31:0] sy;
reg [31:0] s;
always @(posedge clk_cog)
if (m[1])
sy <= ram_q;
wire [31:0] sx = i[im] ? {23'b0, i[sh:sl]}
: i[sh:sl] == 9'h1F0 ? {16'b0, ptr[27:14], 2'b0}
: i[sh:sl] == 9'h1F1 ? cnt
: i[sh:sl] == 9'h1F2 ? pin_in
: i[sh:sl] == 9'h1FC ? phsa[31:0]
: i[sh:sl] == 9'h1FD ? phsb[31:0]
: sy;
always @(posedge clk_cog)
if (m[2])
s <= sx;
// destination
reg [31:0] d;
always @(posedge clk_cog)
if (m[2])
d <= ram_q;
// condition
wire [3:0] condx = i[ch:cl];
wire cond = condx[{c, z}] && !cancel;
// jump/next
reg cancel;
wire dz = ~|d[31:1];
wire [1:0] jumpx = i[oh:ol] == 6'b010111 ? {1'b1, 1'b0} // retjmp
: i[oh:ol] == 6'b111001 ? {1'b1, dz && d[0]} // djnz
: i[oh:ol] == 6'b111010 ? {1'b1, dz && !d[0]} // tjnz
: i[oh:ol] == 6'b111011 ? {1'b1, !(dz && !d[0])} // tjz
: {1'b0, 1'b0}; // no jump
wire jump = jumpx[1];
wire jump_cancel = jumpx[0];
wire [8:0] px = cond && jump ? sx[8:0] : p;
always @(posedge clk_cog or negedge ena)
if (!ena)
cancel <= 1'b0;
else if (m[3])
cancel <= cond && jump_cancel || &px;
// bus interface
assign bus_r = !bus_sel ? 1'b0 : run;
assign bus_e = !bus_sel ? 1'b0 : i[oh:ol+2] == 4'b0000__ && m[4];
assign bus_w = !bus_sel ? 1'b0 : !i[wr];
assign bus_s = !bus_sel ? 2'b0 : i[ol+1:ol];
assign bus_a = !bus_sel ? 16'b0 : run ? s[15:0] : {ptr[13:0] + {5'b0, p}, s[1:0]};
assign bus_d = !bus_sel ? 32'b0 : d;
// alu interface
wire alu_wr;
wire [31:0] alu_r;
wire alu_co;
wire alu_zo;
cog_alu cog_alu_ ( .i (i[oh:ol]),
.s (s),
.d (d),
.p (p),
.run (run),
.ci (c),
.zi (z),
.bus_q (bus_q),
.bus_c (bus_c),
.wr (alu_wr),
.r (alu_r),
.co (alu_co),
.zo (alu_zo) );
// pin/count match
reg match;
always @(posedge clk_cog)
match <= m[4] && (i[ol+1:ol] == 2'b01 ^ (i[ol+1] ? cnt : pin_in & s) == d);
// wait
wire waitx = i[oh:ol+2] == 4'b0000__ ? !bus_ack
: i[oh:ol+1] == 5'b11110_ ? !match
: i[oh:ol+0] == 6'b111110 ? !match
: i[oh:ol+0] == 6'b111111 ? !vidack
: 1'b0;
wire waiti = cond && waitx;
// pins
assign pin_out = (outa | ctra_pin_out | ctrb_pin_out | vid_pin_out) & dira;
assign pin_dir = dira;
endmodule
|
module basic_checker_32
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(mem_size_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter cache_pkt_width_lp= `bsg_cache_pkt_width(addr_width_p,data_width_p)
)
(
input clk_i
, input reset_i
, input en_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input v_i
, input ready_o
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
bsg_cache_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
logic [data_width_p-1:0] shadow_mem [mem_size_p-1:0];
logic [data_width_p-1:0] result [*];
wire [addr_width_p-1:0] cache_pkt_word_addr = cache_pkt.addr[addr_width_p-1:2];
// store logic
logic [data_width_p-1:0] store_data;
logic [data_mask_width_lp-1:0] store_mask;
always_comb begin
case (cache_pkt.opcode)
SW: begin
store_data = cache_pkt.data;
store_mask = 4'b1111;
end
SH: begin
store_data = {2{cache_pkt.data[15:0]}};
store_mask = {
{2{ cache_pkt.addr[1]}},
{2{~cache_pkt.addr[1]}}
};
end
SB: begin
store_data = {4{cache_pkt.data[7:0]}};
store_mask = {
cache_pkt.addr[1] & cache_pkt.addr[0],
cache_pkt.addr[1] & ~cache_pkt.addr[0],
~cache_pkt.addr[1] & cache_pkt.addr[0],
~cache_pkt.addr[1] & ~cache_pkt.addr[0]
};
end
SM: begin
store_data = cache_pkt.data;
store_mask = cache_pkt.mask;
end
default: begin
store_data = '0;
store_mask = '0;
end
endcase
end
// load logic
logic [data_width_p-1:0] load_data, load_data_final;
logic [7:0] byte_sel;
logic [15:0] half_sel;
assign load_data = shadow_mem[cache_pkt_word_addr];
bsg_mux #(
.els_p(4)
,.width_p(8)
) byte_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1:0])
,.data_o(byte_sel)
);
bsg_mux #(
.els_p(2)
,.width_p(16)
) half_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1])
,.data_o(half_sel)
);
logic [data_width_p-1:0] load_mask;
bsg_expand_bitmask #(
.in_width_p(4)
,.expand_p(8)
) eb (
.i(cache_pkt.mask)
,.o(load_mask)
);
always_comb begin
case (cache_pkt.opcode)
LW: load_data_final = load_data;
LH: load_data_final = {{16{half_sel[15]}}, half_sel};
LB: load_data_final = {{24{byte_sel[7]}}, byte_sel};
LHU: load_data_final = {{16{1'b0}}, half_sel};
LBU: load_data_final = {{24{1'b0}}, byte_sel};
LM: load_data_final = load_data & load_mask;
default: load_data_final = '0;
endcase
end
integer send_id, recv_id;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
send_id <= '0;
recv_id <= '0;
for (integer i = 0; i < mem_size_p; i++)
shadow_mem[i] = '0;
end
else begin
if (en_i) begin
// input recorder
if (v_i & ready_o) begin
case (cache_pkt.opcode)
TAGST: begin
result[send_id] = '0;
send_id++;
end
LM, LW, LH, LB, LHU, LBU: begin
result[send_id] = load_data_final;
send_id++;
end
SW, SH, SB, SM: begin
result[send_id] = '0;
send_id++;
for (integer i = 0; i < data_mask_width_lp; i++)
if (store_mask[i])
shadow_mem[cache_pkt_word_addr][8*i+:8] <= store_data[8*i+:8];
end
AMOSWAP_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= cache_pkt.data;
end
AMOADD_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= cache_pkt.data + load_data;
end
AMOXOR_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= cache_pkt.data ^ load_data;
end
AMOAND_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= cache_pkt.data & load_data;
end
AMOOR_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= cache_pkt.data | load_data;
end
AMOMIN_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= (signed'(cache_pkt.data) < signed'(load_data))
? cache_pkt.data
: load_data;
end
AMOMAX_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= (signed'(cache_pkt.data) > signed'(load_data))
? cache_pkt.data
: load_data;
end
AMOMINU_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= (cache_pkt.data < load_data)
? cache_pkt.data
: load_data;
end
AMOMAXU_W: begin
result[send_id] <= load_data;
send_id <= send_id + 1;
shadow_mem[cache_pkt_word_addr] <= (cache_pkt.data > load_data)
? cache_pkt.data
: load_data;
end
ALOCK, AUNLOCK, TAGFL, AFLINV, AFL: begin
result[send_id] = '0;
send_id++;
end
endcase
end
// output checker
if (v_o & yumi_i) begin
assert(result[recv_id] == data_o)
else $fatal("[BSG_FATAL] output does not match expected result. Id=%d, Expected: %x. Actual: %x.",
recv_id, result[recv_id], data_o);
recv_id++;
end
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(basic_checker_32)
|
////////////////////////////////////////////////////////////////////////////////
// //
// Copyright 2006, 2007 Dennis van Weeren //
// //
// This file is part of Minimig //
// //
// Minimig is free software; you can redistribute it and/or modify //
// it under the terms of the GNU General Public License as published by //
// the Free Software Foundation; either version 3 of the License, or //
// (at your option) any later version. //
// //
// Minimig is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// This is the bitplane parallel to serial converter & scroller //
// //
////////////////////////////////////////////////////////////////////////////////
module denise_bitplane_shifter
(
input wire clk, // 35ns pixel clock
input wire clk7_en, // 7MHz clock enable
input wire c1, // clock phase signals
input wire c3, // clock phase signals
input wire load, // load shift register signal
input wire hires, // high resolution select
input wire shres, // super high resolution select (takes priority over hires)
input wire [ 2-1:0] fmode, // AGA fetch mode
input wire [ 64-1:0] data_in, // parallel load data input
input wire [ 8-1:0] scroll, // scrolling value
output wire out // shift register output
);
// local signals
reg [ 6-1:0] fmode_mask; // fetchmode mask
reg [64-1:0] shifter; // main shifter
reg [64-1:0] scroller; // scroller shifter
reg shift; // shifter enable
reg [ 6-1:0] select; // shifter pixel select
wire scroller_out; // scroller output
reg [ 8-1:0] sh_scroller; // superhires scroller
reg [ 3-1:0] sh_select; // superhires scroller pixel select
// fetchmode mask
always @ (*) begin
case(fmode[1:0])
2'b00 : fmode_mask = 6'b00_1111;
2'b01,
2'b10 : fmode_mask = 6'b01_1111;
2'b11 : fmode_mask = 6'b11_1111;
endcase
end
// main shifter and scroller control
always @ (*) begin
if (shres) begin
// super hires mode
shift = 1'b1; // shifter always enabled
select[5:0] = scroll[5:0] & fmode_mask;
end else if (hires) begin
// hires mode
shift = ~c1 ^ c3; // shifter enabled every other clock cycle
select[5:0] = scroll[6:1] & fmode_mask;
end else begin
// lowres mode
shift = ~c1 & ~c3; // shifter enabled once every 4 clock cycles
select[5:0] = scroll[7:2] & fmode_mask;
end
end
// main shifter
always @ (posedge clk) begin
if (load && !c1 && !c3) begin
// load new data into shifter
shifter[63:0] <= data_in[63:0];
end else if (shift) begin
// shift already loaded data
shifter[63:0] <= {shifter[62:0],1'b0};
end
end
// main scroller
always @ (posedge clk) begin
if (shift) begin
// shift scroller data
scroller[63:0] <= {scroller[62:0],shifter[63]};
end
end
// main scroller output
assign scroller_out = scroller[select];
// superhires scroller control // TODO test if this is correct
always @ (*) begin
if (shres) begin
sh_select = 3'b011;
end else if (hires) begin
sh_select = {1'b1, scroll[0], 1'b1}; // MSB bit should probably be 0, this is a hack for kickstart screen ...
end else begin
sh_select = {1'b0, scroll[1:0]};
end
end
// superhires scroller
always @ (posedge clk) begin
sh_scroller[7:0] <= {sh_scroller[6:0], scroller_out};
end
// superhires scroller output
assign out = sh_scroller[sh_select];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_0_V
`define SKY130_FD_SC_HD__OR2_0_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_0 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_0_V
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=10 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=5 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=comm_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_comm_pll_comm_pll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module comm_pll_altpll1
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 10,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 5,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 1,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //comm_pll_altpll1
//VALID FILE
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [11:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [19:0] gpio_wire;
// instantiations
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
.dio_p ({ gpio_wire,
gpio_bd}));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module instruction_decoder_testbench();
reg[31:0] instruction_data;
wire[3:0] opcode;
wire input_type_1;
wire[1:0] input_register_selector_1;
wire[7:0] input_immediate_1;
wire input_type_2;
wire[1:0] input_register_selector_2;
wire[7:0] input_immediate_2;
wire[1:0] output_register_selector;
instruction_decoder id(instruction_data, opcode,
input_type_1, input_register_selector_1,
input_immediate_1, input_type_2,
input_register_selector_2, input_immediate_2,
output_register_selector);
initial
begin
#0 assign instruction_data = 'h00000000;
$display("opcode\treg s1\treg s2\treg d\timm 1\timm 2");
$monitor("%b\t%d\t%d\t%d\t%d\t%d",
opcode, input_register_selector_1, input_register_selector_2,
output_register_selector,
input_immediate_1, input_immediate_2);
/* 0 | r0 | i 255 | r0 | 0 */
#1 assign instruction_data = 'b00000010000001111111110000000000;
/* 1 | r3 | i 42 | r0 | 0 */
#2 assign instruction_data = 'b00010110000001001010100100000000;
/* 2 | i 1 | r0 | r0 | 0 */
#3 assign instruction_data = 'b00101000000010000000001000000000;
/* 3 | i 255 | r2 | r0 | 0 */
#4 assign instruction_data = 'b00111111111110100000001100000000;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dmac_regmap_request #(
parameter DISABLE_DEBUG_REGISTERS = 0,
parameter BYTES_PER_BEAT_WIDTH_DEST = 1,
parameter BYTES_PER_BEAT_WIDTH_SRC = 1,
parameter BYTES_PER_BURST_WIDTH = 7,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_LENGTH_WIDTH = 24,
parameter DMA_LENGTH_ALIGN = 3,
parameter DMA_CYCLIC = 0,
parameter HAS_DEST_ADDR = 1,
parameter HAS_SRC_ADDR = 1,
parameter DMA_2D_TRANSFER = 0,
parameter SYNC_TRANSFER_START = 0
) (
input clk,
input reset,
// Interrupts
output up_sot,
output up_eot,
// Register map interface
input up_wreq,
input up_rreq,
input [8:0] up_waddr,
input [31:0] up_wdata,
input [8:0] up_raddr,
output reg [31:0] up_rdata,
// Control interface
input ctrl_enable,
// DMA request interface
output request_valid,
input request_ready,
output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address,
output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address,
output [DMA_LENGTH_WIDTH-1:0] request_x_length,
output [DMA_LENGTH_WIDTH-1:0] request_y_length,
output [DMA_LENGTH_WIDTH-1:0] request_dest_stride,
output [DMA_LENGTH_WIDTH-1:0] request_src_stride,
output request_sync_transfer_start,
output request_last,
// DMA response interface
input response_eot,
input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length,
input response_partial,
input response_valid,
output reg response_ready = 1'b1
);
localparam MEASURED_LENGTH_WIDTH = (DMA_2D_TRANSFER == 1) ? 32 : DMA_LENGTH_WIDTH;
// DMA transfer signals
reg up_dma_req_valid = 1'b0;
wire up_dma_req_ready;
reg [1:0] up_transfer_id = 2'b0;
reg [1:0] up_transfer_id_eot = 2'b0;
reg [3:0] up_transfer_done_bitmap = 4'b0;
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = {DMA_LENGTH_ALIGN{1'b1}};
reg up_dma_cyclic = DMA_CYCLIC ? 1'b1 : 1'b0;
reg up_dma_last = 1'b1;
reg up_dma_enable_tlen_reporting = 1'b0;
wire up_tlf_s_ready;
reg up_tlf_s_valid = 1'b0;
wire [MEASURED_LENGTH_WIDTH+2-1:0] up_tlf_data;
wire up_tlf_valid;
wire up_tlf_rd;
reg up_partial_length_valid = 1'b0;
reg [MEASURED_LENGTH_WIDTH-1:0] up_measured_transfer_length = 'h0;
reg up_clear_tl = 1'b0;
reg [1:0] up_transfer_id_eot_d = 'h0;
wire up_bl_partial;
assign request_dest_address = up_dma_dest_address;
assign request_src_address = up_dma_src_address;
assign request_x_length = up_dma_x_length;
assign request_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0;
assign request_last = up_dma_last;
always @(posedge clk) begin
if (reset == 1'b1) begin
up_dma_src_address <= 'h00;
up_dma_dest_address <= 'h00;
up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= 'h00;
up_dma_req_valid <= 1'b0;
up_dma_cyclic <= DMA_CYCLIC ? 1'b1 : 1'b0;
up_dma_last <= 1'b1;
up_dma_enable_tlen_reporting <= 1'b0;
end else begin
if (ctrl_enable == 1'b1) begin
if (up_wreq == 1'b1 && up_waddr == 9'h102) begin
up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
end else if (up_sot == 1'b1) begin
up_dma_req_valid <= 1'b0;
end
end else begin
up_dma_req_valid <= 1'b0;
end
if (up_wreq == 1'b1) begin
case (up_waddr)
9'h103: begin
if (DMA_CYCLIC) up_dma_cyclic <= up_wdata[0];
up_dma_last <= up_wdata[1];
up_dma_enable_tlen_reporting <= up_wdata[2];
end
9'h104: up_dma_dest_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
9'h105: up_dma_src_address <= up_wdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
endcase
end
end
end
always @(*) begin
case (up_raddr)
9'h101: up_rdata <= up_transfer_id;
9'h102: up_rdata <= up_dma_req_valid;
9'h103: up_rdata <= {29'h00, up_dma_enable_tlen_reporting, up_dma_last, up_dma_cyclic}; // Flags
9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
9'h106: up_rdata <= up_dma_x_length;
9'h107: up_rdata <= request_y_length;
9'h108: up_rdata <= request_dest_stride;
9'h109: up_rdata <= request_src_stride;
9'h10a: up_rdata <= {up_partial_length_valid,27'b0,up_transfer_done_bitmap};
9'h10b: up_rdata <= up_transfer_id_eot;
9'h10c: up_rdata <= 32'h0;
9'h112: up_rdata <= up_measured_transfer_length;
9'h113: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH-1 : 0]; // Length
9'h114: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH+: 2]; // ID
default: up_rdata <= 32'h00;
endcase
end
generate
if (DMA_2D_TRANSFER == 1) begin
reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
up_dma_y_length <= 'h00;
up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= 'h00;
up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= 'h00;
end else if (up_wreq == 1'b1) begin
case (up_waddr)
9'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
9'h108: up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
9'h109: up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
endcase
end
end
assign request_y_length = up_dma_y_length;
assign request_dest_stride = up_dma_dest_stride;
assign request_src_stride = up_dma_src_stride;
end else begin
assign request_y_length = 'h0;
assign request_dest_stride = 'h0;
assign request_src_stride = 'h0;
end
endgenerate
// In cyclic mode the same transfer is submitted over and over again
assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
assign up_eot = up_dma_cyclic ? 1'b0 : response_eot & response_valid & response_ready;
assign request_valid = up_dma_req_valid;
assign up_dma_req_ready = request_ready;
// Request ID and Request done bitmap handling
always @(posedge clk) begin
if (ctrl_enable == 1'b0) begin
up_transfer_id <= 2'h0;
up_transfer_id_eot <= 2'h0;
up_transfer_done_bitmap <= 4'h0;
end else begin
if (up_sot == 1'b1) begin
up_transfer_id <= up_transfer_id + 1'b1;
up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
end
if (up_eot == 1'b1) begin
up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
end
end
end
assign up_tlf_rd = up_rreq && up_raddr == 'h114;
assign up_bl_partial = response_valid & response_ready & response_partial & up_dma_enable_tlen_reporting;
always @(posedge clk) begin
if (ctrl_enable == 1'b0) begin
up_partial_length_valid <= 1'b0;
end else begin
if (up_bl_partial == 1'b1) begin
up_partial_length_valid <= 1'b1;
end else if (up_tlf_rd == 1'b1) begin
up_partial_length_valid <= 1'b0;
end else if (up_tlf_valid == 1'b1) begin
up_partial_length_valid <= 1'b1;
end
end
end
always @(posedge clk)
begin
if (response_valid == 1'b1 & response_ready == 1'b1) begin
up_measured_transfer_length <= up_measured_transfer_length + response_measured_burst_length + 1'b1;
up_transfer_id_eot_d <= up_transfer_id_eot;
end else if (up_clear_tl == 1'b1) begin
up_measured_transfer_length <= 'h0;
end
end
always @(posedge clk)
begin
if (ctrl_enable == 1'b0) begin
response_ready <= 1'b1;
end else if (response_ready == 1'b1) begin
response_ready <= ~response_valid;
end else if (up_tlf_s_ready == 1'b1) begin
response_ready <= 1'b1;
end
end
always @(posedge clk)
begin
if (response_valid == 1'b1 && response_ready == 1'b1) begin
up_tlf_s_valid <= up_bl_partial;
up_clear_tl <= up_eot;
end else if (up_tlf_s_ready == 1'b1) begin
up_tlf_s_valid <= 1'b0;
end
end
// Buffer the length and transfer ID of partial transfers
util_axis_fifo #(
.DATA_WIDTH(MEASURED_LENGTH_WIDTH + 2),
.ADDRESS_WIDTH(2),
.ASYNC_CLK(0)
) i_transfer_lenghts_fifo (
.s_axis_aclk(clk),
.s_axis_aresetn(ctrl_enable),
.s_axis_valid(up_tlf_s_valid),
.s_axis_ready(up_tlf_s_ready),
.s_axis_empty(),
.s_axis_data({up_transfer_id_eot_d, up_measured_transfer_length}),
.s_axis_room(),
.m_axis_aclk(clk),
.m_axis_aresetn(ctrl_enable),
.m_axis_valid(up_tlf_valid),
.m_axis_ready(up_tlf_rd & up_tlf_valid),
.m_axis_data(up_tlf_data),
.m_axis_level()
);
endmodule
|
module AXIAccelWrapper(input clk, input reset,
output csr_AWREADY,
input csr_AWVALID,
input [31:0] csr_AWADDR,
input [2:0] csr_AWPROT,
output csr_WREADY,
input csr_WVALID,
input [31:0] csr_WDATA,
input [3:0] csr_WSTRB,
input csr_BREADY,
output csr_BVALID,
output[1:0] csr_BRESP,
output csr_ARREADY,
input csr_ARVALID,
input [31:0] csr_ARADDR,
input [2:0] csr_ARPROT,
input csr_RREADY,
output csr_RVALID,
output[31:0] csr_RDATA,
output[1:0] csr_RRESP,
input mem3_AWREADY,
output mem3_AWVALID,
output[31:0] mem3_AWADDR,
output[2:0] mem3_AWSIZE,
output[7:0] mem3_AWLEN,
output[1:0] mem3_AWBURST,
output[4:0] mem3_AWID,
output mem3_AWLOCK,
output[3:0] mem3_AWCACHE,
output[2:0] mem3_AWPROT,
output[3:0] mem3_AWQOS,
input mem3_WREADY,
output mem3_WVALID,
output[63:0] mem3_WDATA,
output[7:0] mem3_WSTRB,
output mem3_WLAST,
output mem3_BREADY,
input mem3_BVALID,
input [4:0] mem3_BID,
input [1:0] mem3_BRESP,
input mem3_ARREADY,
output mem3_ARVALID,
output[31:0] mem3_ARADDR,
output[2:0] mem3_ARSIZE,
output[7:0] mem3_ARLEN,
output[1:0] mem3_ARBURST,
output[4:0] mem3_ARID,
output mem3_ARLOCK,
output[3:0] mem3_ARCACHE,
output[2:0] mem3_ARPROT,
output[3:0] mem3_ARQOS,
output mem3_RREADY,
input mem3_RVALID,
input [63:0] mem3_RDATA,
input [4:0] mem3_RID,
input mem3_RLAST,
input [1:0] mem3_RRESP,
input mem2_AWREADY,
output mem2_AWVALID,
output[31:0] mem2_AWADDR,
output[2:0] mem2_AWSIZE,
output[7:0] mem2_AWLEN,
output[1:0] mem2_AWBURST,
output[4:0] mem2_AWID,
output mem2_AWLOCK,
output[3:0] mem2_AWCACHE,
output[2:0] mem2_AWPROT,
output[3:0] mem2_AWQOS,
input mem2_WREADY,
output mem2_WVALID,
output[63:0] mem2_WDATA,
output[7:0] mem2_WSTRB,
output mem2_WLAST,
output mem2_BREADY,
input mem2_BVALID,
input [4:0] mem2_BID,
input [1:0] mem2_BRESP,
input mem2_ARREADY,
output mem2_ARVALID,
output[31:0] mem2_ARADDR,
output[2:0] mem2_ARSIZE,
output[7:0] mem2_ARLEN,
output[1:0] mem2_ARBURST,
output[4:0] mem2_ARID,
output mem2_ARLOCK,
output[3:0] mem2_ARCACHE,
output[2:0] mem2_ARPROT,
output[3:0] mem2_ARQOS,
output mem2_RREADY,
input mem2_RVALID,
input [63:0] mem2_RDATA,
input [4:0] mem2_RID,
input mem2_RLAST,
input [1:0] mem2_RRESP,
input mem1_AWREADY,
output mem1_AWVALID,
output[31:0] mem1_AWADDR,
output[2:0] mem1_AWSIZE,
output[7:0] mem1_AWLEN,
output[1:0] mem1_AWBURST,
output[4:0] mem1_AWID,
output mem1_AWLOCK,
output[3:0] mem1_AWCACHE,
output[2:0] mem1_AWPROT,
output[3:0] mem1_AWQOS,
input mem1_WREADY,
output mem1_WVALID,
output[63:0] mem1_WDATA,
output[7:0] mem1_WSTRB,
output mem1_WLAST,
output mem1_BREADY,
input mem1_BVALID,
input [4:0] mem1_BID,
input [1:0] mem1_BRESP,
input mem1_ARREADY,
output mem1_ARVALID,
output[31:0] mem1_ARADDR,
output[2:0] mem1_ARSIZE,
output[7:0] mem1_ARLEN,
output[1:0] mem1_ARBURST,
output[4:0] mem1_ARID,
output mem1_ARLOCK,
output[3:0] mem1_ARCACHE,
output[2:0] mem1_ARPROT,
output[3:0] mem1_ARQOS,
output mem1_RREADY,
input mem1_RVALID,
input [63:0] mem1_RDATA,
input [4:0] mem1_RID,
input mem1_RLAST,
input [1:0] mem1_RRESP,
input mem0_AWREADY,
output mem0_AWVALID,
output[31:0] mem0_AWADDR,
output[2:0] mem0_AWSIZE,
output[7:0] mem0_AWLEN,
output[1:0] mem0_AWBURST,
output[4:0] mem0_AWID,
output mem0_AWLOCK,
output[3:0] mem0_AWCACHE,
output[2:0] mem0_AWPROT,
output[3:0] mem0_AWQOS,
input mem0_WREADY,
output mem0_WVALID,
output[63:0] mem0_WDATA,
output[7:0] mem0_WSTRB,
output mem0_WLAST,
output mem0_BREADY,
input mem0_BVALID,
input [4:0] mem0_BID,
input [1:0] mem0_BRESP,
input mem0_ARREADY,
output mem0_ARVALID,
output[31:0] mem0_ARADDR,
output[2:0] mem0_ARSIZE,
output[7:0] mem0_ARLEN,
output[1:0] mem0_ARBURST,
output[4:0] mem0_ARID,
output mem0_ARLOCK,
output[3:0] mem0_ARCACHE,
output[2:0] mem0_ARPROT,
output[3:0] mem0_ARQOS,
output mem0_RREADY,
input mem0_RVALID,
input [63:0] mem0_RDATA,
input [4:0] mem0_RID,
input mem0_RLAST,
input [1:0] mem0_RRESP
);
endmodule
|
`include "../lib/full_adder.v"
module add (
output cout,
output [31:0] sum,
input [31:0] a, b,
input cin
);
wire [30:0] carry;
full_adder addr0 (.cout(carry[ 0]), .sum(sum[ 0]), .a(a[ 0]), .b(b[ 0]), .cin(cin ));
full_adder addr1 (.cout(carry[ 1]), .sum(sum[ 1]), .a(a[ 1]), .b(b[ 1]), .cin(carry[ 0]));
full_adder addr2 (.cout(carry[ 2]), .sum(sum[ 2]), .a(a[ 2]), .b(b[ 2]), .cin(carry[ 1]));
full_adder addr3 (.cout(carry[ 3]), .sum(sum[ 3]), .a(a[ 3]), .b(b[ 3]), .cin(carry[ 2]));
full_adder addr4 (.cout(carry[ 4]), .sum(sum[ 4]), .a(a[ 4]), .b(b[ 4]), .cin(carry[ 3]));
full_adder addr5 (.cout(carry[ 5]), .sum(sum[ 5]), .a(a[ 5]), .b(b[ 5]), .cin(carry[ 4]));
full_adder addr6 (.cout(carry[ 6]), .sum(sum[ 6]), .a(a[ 6]), .b(b[ 6]), .cin(carry[ 5]));
full_adder addr7 (.cout(carry[ 7]), .sum(sum[ 7]), .a(a[ 7]), .b(b[ 7]), .cin(carry[ 6]));
full_adder addr8 (.cout(carry[ 8]), .sum(sum[ 8]), .a(a[ 8]), .b(b[ 8]), .cin(carry[ 7]));
full_adder addr9 (.cout(carry[ 9]), .sum(sum[ 9]), .a(a[ 9]), .b(b[ 9]), .cin(carry[ 8]));
full_adder addr10 (.cout(carry[10]), .sum(sum[10]), .a(a[10]), .b(b[10]), .cin(carry[ 9]));
full_adder addr11 (.cout(carry[11]), .sum(sum[11]), .a(a[11]), .b(b[11]), .cin(carry[10]));
full_adder addr12 (.cout(carry[12]), .sum(sum[12]), .a(a[12]), .b(b[12]), .cin(carry[11]));
full_adder addr13 (.cout(carry[13]), .sum(sum[13]), .a(a[13]), .b(b[13]), .cin(carry[12]));
full_adder addr14 (.cout(carry[14]), .sum(sum[14]), .a(a[14]), .b(b[14]), .cin(carry[13]));
full_adder addr15 (.cout(carry[15]), .sum(sum[15]), .a(a[15]), .b(b[15]), .cin(carry[14]));
full_adder addr16 (.cout(carry[16]), .sum(sum[16]), .a(a[16]), .b(b[16]), .cin(carry[15]));
full_adder addr17 (.cout(carry[17]), .sum(sum[17]), .a(a[17]), .b(b[17]), .cin(carry[16]));
full_adder addr18 (.cout(carry[18]), .sum(sum[18]), .a(a[18]), .b(b[18]), .cin(carry[17]));
full_adder addr19 (.cout(carry[19]), .sum(sum[19]), .a(a[19]), .b(b[19]), .cin(carry[18]));
full_adder addr20 (.cout(carry[20]), .sum(sum[20]), .a(a[20]), .b(b[20]), .cin(carry[19]));
full_adder addr21 (.cout(carry[21]), .sum(sum[21]), .a(a[21]), .b(b[21]), .cin(carry[20]));
full_adder addr22 (.cout(carry[22]), .sum(sum[22]), .a(a[22]), .b(b[22]), .cin(carry[21]));
full_adder addr23 (.cout(carry[23]), .sum(sum[23]), .a(a[23]), .b(b[23]), .cin(carry[22]));
full_adder addr24 (.cout(carry[24]), .sum(sum[24]), .a(a[24]), .b(b[24]), .cin(carry[23]));
full_adder addr25 (.cout(carry[25]), .sum(sum[25]), .a(a[25]), .b(b[25]), .cin(carry[24]));
full_adder addr26 (.cout(carry[26]), .sum(sum[26]), .a(a[26]), .b(b[26]), .cin(carry[25]));
full_adder addr27 (.cout(carry[27]), .sum(sum[27]), .a(a[27]), .b(b[27]), .cin(carry[26]));
full_adder addr28 (.cout(carry[28]), .sum(sum[28]), .a(a[28]), .b(b[28]), .cin(carry[27]));
full_adder addr29 (.cout(carry[29]), .sum(sum[29]), .a(a[29]), .b(b[29]), .cin(carry[28]));
full_adder addr30 (.cout(carry[30]), .sum(sum[30]), .a(a[30]), .b(b[30]), .cin(carry[29]));
full_adder addr31 (.cout(cout ), .sum(sum[31]), .a(a[31]), .b(b[31]), .cin(carry[30]));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR2_BEHAVIORAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTDDIO_IN%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_in
// ============================================================
// File Name: rgmii_in4.v
// Megafunction Name(s):
// altddio_in
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 176 04/19/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_rgmii_in4 (
aclr,
datain,
inclock,
dataout_h,
dataout_l);
input aclr;
input [3:0] datain;
input inclock;
output [3:0] dataout_h;
output [3:0] dataout_l;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] dataout_h = sub_wire0[3:0];
wire [3:0] dataout_l = sub_wire1[3:0];
altddio_in altddio_in_component (
.datain (datain),
.inclock (inclock),
.aclr (aclr),
.dataout_h (sub_wire0),
.dataout_l (sub_wire1),
.aset (1'b0),
.inclocken (1'b1));
defparam
altddio_in_component.intended_device_family = "Stratix II",
altddio_in_component.invert_input_clocks = "OFF",
altddio_in_component.lpm_type = "altddio_in",
altddio_in_component.width = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_qpll_drp.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_qpll_drp.v
// Description : QPLL DRP Module for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL DRP Module ---------------------------------------------------
module pcie3_7x_0_qpll_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter LOAD_CNT_MAX = 2'd3, // Load max count
parameter INDEX_MAX = 3'd6 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_OVRD,
input DRP_GEN3,
input DRP_QPLLLOCK,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 7:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output DRP_QPLLRESET,
output [ 5:0] DRP_CRSCODE,
output [ 8:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 2:0] index = 3'd0;
reg mode = 1'd0;
reg [ 5:0] crscode = 6'd0;
//---------- Output Registers --------------------------
reg [ 7:0] addr = 8'd0;
reg [15:0] di = 16'd0;
reg done = 1'd0;
reg [ 8:0] fsm = 7'd1;
//---------- DRP Address -------------------------------
localparam ADDR_QPLL_FBDIV = 8'h36;
localparam ADDR_QPLL_CFG = 8'h32;
localparam ADDR_QPLL_LPF = 8'h31;
localparam ADDR_CRSCODE = 8'h88;
localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
localparam ADDR_QPLL_LOCK_CFG = 8'h34;
//---------- DRP Mask ----------------------------------
localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
//---------- DRP Data for Normal QPLLLOCK Mode ---------
localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
//---------- DRP Data for Optimize QPLLLOCK Mode -------
localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
//---------- Select QPLL Feedback Divider --------------
// N = 100 for 100 MHz ref clk and 10Gb/s line rate
// N = 80 for 125 MHz ref clk and 10Gb/s line rate
// N = 40 for 250 MHz ref clk and 10Gb/s line rate
//------------------------------------------------------
// N = 80 for 100 MHz ref clk and 8Gb/s line rate
// N = 64 for 125 MHz ref clk and 8Gb/s line rate
// N = 32 for 250 MHz ref clk and 8Gb/s line rate
//------------------------------------------------------
localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
//---------- Select QPLL Configuration ---------------------------
// QPLL_CFG[6] = 0 for upper band
// = 1 for lower band
//----------------------------------------------------------------
localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
localparam GEN3_QPLL_CFG = 16'b0000000001000000;
//---------- Select QPLL LPF -------------------------------------
localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
//---------- DRP Data ----------------------------------
wire [15:0] data_qpll_fbdiv;
wire [15:0] data_qpll_cfg;
wire [15:0] data_qpll_lpf;
wire [15:0] data_qpll_coarse_freq_ovrd;
wire [15:0] data_qpll_coarse_freq_ovrd_en;
wire [15:0] data_qpll_lock_cfg;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 9'b000000001;
localparam FSM_LOAD = 9'b000000010;
localparam FSM_READ = 9'b000000100;
localparam FSM_RRDY = 9'b000001000;
localparam FSM_WRITE = 9'b000010000;
localparam FSM_WRDY = 9'b000100000;
localparam FSM_DONE = 9'b001000000;
localparam FSM_QPLLRESET = 9'b010000000;
localparam FSM_QPLLLOCK = 9'b100000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= 1'd0;
gen3_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
start_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= 1'd0;
gen3_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
start_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= DRP_OVRD;
gen3_reg1 <= DRP_GEN3;
qplllock_reg1 <= DRP_QPLLLOCK;
start_reg1 <= DRP_START;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= ovrd_reg1;
gen3_reg2 <= gen3_reg1;
qplllock_reg2 <= qplllock_reg1;
start_reg2 <= start_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
else
begin
case (index)
//--------------------------------------------------
3'd0 :
begin
addr <= ADDR_QPLL_FBDIV;
di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
crscode <= crscode;
end
//--------------------------------------------------
3'd1 :
begin
addr <= ADDR_QPLL_CFG;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
crscode <= crscode;
end
//--------------------------------------------------
3'd2 :
begin
addr <= ADDR_QPLL_LPF;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
crscode <= crscode;
end
//--------------------------------------------------
3'd3 :
begin
addr <= ADDR_CRSCODE;
di <= do_reg2;
//---------- Latch CRS Code --------------------
if (ovrd_reg2)
crscode <= do_reg2[6:1];
else
crscode <= crscode;
end
//--------------------------------------------------
3'd4 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
crscode <= crscode;
end
//--------------------------------------------------
3'd5 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
crscode <= crscode;
end
//--------------------------------------------------
3'd6 :
begin
addr <= ADDR_QPLL_LOCK_CFG;
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
crscode <= crscode;
end
//--------------------------------------------------
default :
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
endcase
end
end
//---------- QPLL DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd1;
done <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
begin
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 3'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- QPLL Reset ----------------------------
FSM_QPLLRESET :
begin
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- QPLL Reset ----------------------------
FSM_QPLLLOCK :
begin
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- QPLL DRP Output ---------------------------------------------------
assign DRP_ADDR = addr;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di;
assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
assign DRP_DONE = done;
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
assign DRP_CRSCODE = crscode;
assign DRP_FSM = fsm;
endmodule
|
module vga(
mclk,
hsync,
vsync,
standard,
emphasized,
background,
write_address,
write_data,
write_enable,
color
);
// Input
input wire mclk;
input wire[3:0] standard;
input wire[3:0] emphasized;
input wire[3:0] background;
input wire[11:0] write_address;
input wire[7:0] write_data;
input wire write_enable;
// Output
output wire hsync;
output wire vsync;
output wire[7:0] color;
// Interconnect
wire clk25mhz;
wire[9:0] hindex;
wire[9:0] vindex;
wire[9:0] font_address;
wire[11:0] char_address;
wire[13:0] font_data;
wire[7:0] char_data;
// Modules
vga_framebuffer vga_framebuffer_inst (
.clka(mclk),
.wea(write_enable),
.addra(write_address),
.dina(write_data),
.clkb(mclk),
.addrb(char_address),
.doutb(char_data)
);
vga_font vga_font_inst (
.clka(mclk),
.addra(font_address),
.douta(font_data)
);
vga_clocking vga_clocking_inst(
.mclk(mclk),
.clk25mhz(clk25mhz)
);
vga_timing vga_timing_inst(
.clk25mhz(clk25mhz),
.hindex(hindex),
.vindex(vindex),
.hsync(hsync),
.vsync(vsync)
);
vga_text vga_text_inst(
.clk25mhz(clk25mhz),
.hindex(hindex),
.vindex(vindex),
.standard(standard),
.emphasized(emphasized),
.background(background),
.char_data(char_data),
.font_data(font_data),
.char_address(char_address),
.font_address(font_address),
.color(color)
);
endmodule
|
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this start_of_frametware and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is furnished
to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//ft_fifo_interface.v
`timescale 1ns/1ps
`define IN_FIFO_DATA_SIZE 9
`define IN_FIFO_ADDRESS_WIDTH 10
`define OUT_FIFO_DATA_SIZE 8
`define OUT_FIFO_ADDRESS_WIDTH 10
`define BUFFER_SIZE 2
module ft_fifo_interface (
//boilerplate
rst,
clk,
//incomming FIFO
in_fifo_read,
in_fifo_count,
in_fifo_ready,
in_fifo_activate,
in_fifo_data,
start_of_frame,
//outgoing FIFO
out_fifo_write,
out_fifo_write_size,
out_fifo_ready,
out_fifo_activate,
out_fifo_starved,
out_fifo_data,
//FTDI FIFO interface
ftdi_clk,
ftdi_data,
ftdi_txe_n,
ftdi_wr_n,
ftdi_rd_n,
ftdi_rde_n,
ftdi_oe_n,
ftdi_suspend_n,
ftdi_siwu,
debug
);
//boilerplate
input rst;
input clk;
//in fifo
input in_fifo_read;
output [23:0] in_fifo_count;
output in_fifo_ready;
input in_fifo_activate;
output [7:0] in_fifo_data;
output start_of_frame;
//out fifo
input out_fifo_write;
output [23:0] out_fifo_write_size;
output [1:0] out_fifo_ready;
input [1:0] out_fifo_activate;
output out_fifo_starved;
input [7:0] out_fifo_data;
//FTDI interface
input ftdi_clk;
inout [7:0] ftdi_data;
input ftdi_txe_n;
output ftdi_wr_n;
input ftdi_rde_n;
output ftdi_oe_n;
output ftdi_rd_n;
input ftdi_suspend_n;
output ftdi_siwu;
//Debug
output [15:0] debug;
//local wires/registers
wire ftdi_transmit_ready;
wire ftdi_read_available;
reg ftdi_output_enable;
//PART OF THE ASYNCHRONOUS WRITE APPROACH
wire ftdi_write_strobe;
//reg ftdi_write_strobe;
wire ftdi_read_strobe;
reg ftdi_send_immediately;
wire ftdi_suspend;
reg prev_ftdi_read_available;
reg ftdi_start_of_frame;
//read state machine
parameter IDLE = 0;
parameter WAIT_FOR_FTDI = 1;
parameter FTDI_ENABLE_OUTPUT = 2;
parameter FTDI_READ = 3;
reg [1:0] read_state;
wire read_busy;
reg [23:0] if_write_count;
reg enable_reading;
//reg [(`OUT_FIFO_DATA_SIZE - 1):0] ftdi_out_data;
wire [(`OUT_FIFO_DATA_SIZE - 1):0] ftdi_out_data;
//write state machine
parameter PRESTROBE_FIFO = 1;
parameter FIFO_READY = 2;
parameter SEND_TO_FTDI = 3;
reg [1:0] write_state;
wire write_busy;
reg [23:0] out_data_count;
reg prestrobe;
//reg [(`OUT_FIFO_DATA_SIZE) -1 :0] data_buffer [(`BUFFER_SIZE) - 1: 0];
//ping pong FIFO wires/registers
wire [(`IN_FIFO_DATA_SIZE) - 1: 0] if_write_data;
wire [1:0] if_write_ready;
reg [1:0] if_write_activate;
wire [23:0] if_write_fifo_size;
wire if_write_strobe;
wire if_starved;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [(`IN_FIFO_DATA_SIZE) - 1: 0] if_read_data;
wire [23:0] if_read_count;
wire [(`OUT_FIFO_DATA_SIZE) - 1: 0]of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_write_fifo_size;
wire of_write_strobe;
//PART OF THE ASYNCHRONOUS FTDI WRITE APPROACH
wire of_read_strobe;
//reg of_read_strobe;
wire of_read_ready;
reg of_read_activate;
wire [23:0] of_read_count;
wire [(`OUT_FIFO_DATA_SIZE) - 1: 0]of_read_data;
wire [15:0] wdebug;
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH(`IN_FIFO_DATA_SIZE),
.ADDRESS_WIDTH(`IN_FIFO_ADDRESS_WIDTH)
) fifo_in (
.reset(rst),
//write side
.write_clock(ftdi_clk),
.write_data(if_write_data),
.write_ready(if_write_ready),
.write_activate(if_write_activate),
.write_fifo_size(if_write_fifo_size),
.write_strobe(if_write_strobe),
.starved(if_starved),
//read side
.read_clock(clk),
.read_strobe(if_read_strobe),
.read_ready(if_read_ready),
.read_activate(if_read_activate),
.read_count(if_read_count),
.read_data(if_read_data)
);
//Output FIFO
ppfifo # (
.DATA_WIDTH(`OUT_FIFO_DATA_SIZE),
.ADDRESS_WIDTH(`OUT_FIFO_ADDRESS_WIDTH)
) fifo_out (
.reset(rst),
//write side
.write_clock(clk),
.write_data(of_write_data),
.write_ready(of_write_ready),
.write_activate(of_write_activate),
.write_fifo_size(of_write_fifo_size),
.write_strobe(of_write_strobe),
.starved(out_fifo_starved),
//read side
.read_clock(ftdi_clk),
.read_strobe(of_read_strobe & ftdi_transmit_ready),
.read_ready(of_read_ready),
.read_activate(of_read_activate),
.read_count(of_read_count),
.read_data(of_read_data)
);
//asynchronous logic
//this is just for readibility
assign ftdi_transmit_ready = ~ftdi_txe_n;
assign ftdi_read_available = ~ftdi_rde_n;
assign ftdi_oe_n = ~ftdi_output_enable;
assign ftdi_wr_n = ~ftdi_write_strobe;
assign ftdi_rd_n = ~ftdi_read_strobe;
assign ftdi_siwu = ~ftdi_send_immediately;
assign ftdi_suspend = ~ftdi_suspend_n;
//local wires for input FIFO to the external interface
assign if_read_strobe = in_fifo_read;
assign if_read_activate = in_fifo_activate;
assign in_fifo_count = if_read_count;
assign in_fifo_ready = if_read_ready;
assign start_of_frame = if_read_data[8];
assign in_fifo_data = if_read_data[7:0];
//tieing FTDI data directly to the input FIFO
assign if_write_data[8] = ftdi_start_of_frame;
assign if_write_data[7:0] = ftdi_data;
assign if_write_strobe = ftdi_read_strobe;
//output ppfifo
assign of_write_data = out_fifo_data[7:0];
assign out_fifo_ready = of_write_ready;
assign of_write_activate = out_fifo_activate;
assign out_fifo_write_size = of_write_fifo_size;
assign of_write_strobe = out_fifo_write;
//busy signals
assign read_busy = (read_state != IDLE) && (read_state != WAIT_FOR_FTDI);
assign write_busy = (write_state != IDLE);
//logic to stop writing to the FIFO when the FTDI chip is empty
assign ftdi_read_strobe = (if_write_activate != 0) &&
enable_reading &&
ftdi_read_available;
//NOTE ftdi_read_strobe is tied to if_write_strobe
//SYNCHRONOUS WRITE TO FTDI STATEMENTS
assign ftdi_data = (ftdi_output_enable) ? 8'hZZ : ftdi_out_data;
//ASYNCHRONOUS WRITE TO FTDI STATEMENTS
assign ftdi_out_data = of_read_data;
assign ftdi_write_strobe = of_read_strobe;
assign of_read_strobe = (!read_busy && ftdi_transmit_ready && (out_data_count > 0) && (write_state == SEND_TO_FTDI));
assign debug = wdebug;
//synchronous logic
assign wdebug[1:0] = read_state[1:0];
assign wdebug[3:2] = if_write_ready[1:0];
assign wdebug[5:4] = if_write_activate[1:0];
assign wdebug[6] = (if_write_count > 0);
assign wdebug[7] = if_write_strobe;
assign wdebug[9:8] = write_state[1:0];
assign wdebug[10] = of_read_ready;
assign wdebug[11] = of_read_activate;
assign wdebug[12] = (out_data_count > 0);
assign wdebug[13] = read_busy;
assign wdebug[14] = write_busy;
assign wdebug[15] = ftdi_start_of_frame;
//logic for detecting the start of a frame detect
always @ (posedge ftdi_clk) begin
if (rst) begin
prev_ftdi_read_available <= 0;
ftdi_start_of_frame <= 0;
end
else begin
if (ftdi_read_available && ~prev_ftdi_read_available) begin
//just transitioned to the start of a frame
ftdi_start_of_frame <= 1;
end
//lower the start of frame when I see the write strobe
if (if_write_strobe) begin
ftdi_start_of_frame <= 0;
end
prev_ftdi_read_available <= ftdi_read_available;
end
end
always @ (posedge ftdi_clk) begin
if (rst) begin
read_state <= IDLE;
ftdi_output_enable <= 0;
if_write_count <= 0;
if_write_activate <= 0;
enable_reading <= 0;
end
else begin
enable_reading <= 0;
case (read_state)
IDLE: begin
//get a FIFO
if (if_write_ready > 0) begin
if (if_write_ready[0]) begin
if_write_activate[0] <= 1;
end
else begin
if_write_activate[1] <= 1;
end
if_write_count <= if_write_fifo_size - 1;
read_state <= WAIT_FOR_FTDI;
end
end
WAIT_FOR_FTDI: begin
if (!write_busy && ftdi_read_available) begin
read_state <= FTDI_ENABLE_OUTPUT;
end
end
FTDI_ENABLE_OUTPUT: begin
//pass through state
ftdi_output_enable <= 1;
read_state <= FTDI_READ;
end
FTDI_READ: begin
//see if the read is starved and we have at least 9 bytes
//enough for a minimum transaction
enable_reading <= 1;
if (if_write_count == 0) begin
//filled up the in FIFO
enable_reading <= 0;
if_write_activate <= 0;
ftdi_output_enable <= 0;
read_state <= IDLE;
end
else if (if_write_strobe) begin
if_write_count <= if_write_count - 1;
end
//if the FTDI chip is empty release the write FIFO and disable the output enable
if (!ftdi_read_available) begin
ftdi_output_enable <= 0;
read_state <= IDLE;
//deactivate any currently used FIFOs
if_write_activate <= 0;
end
end
default: begin
ftdi_output_enable <= 0;
read_state <= IDLE;
end
endcase
end
end
integer i;
always @ (posedge ftdi_clk) begin
if (rst) begin
//of_read_strobe <= 0;
of_read_activate <= 0;
ftdi_send_immediately <= 0;
out_data_count <= 0;
write_state <= IDLE;
end
else begin
//of_read_strobe <= 0;
ftdi_send_immediately <= 0;
case (write_state)
IDLE: begin
if (of_read_ready) begin
out_data_count <= of_read_count;
write_state <= FIFO_READY;
of_read_activate <= 1;
end
end
FIFO_READY: begin
write_state <= SEND_TO_FTDI;
end
SEND_TO_FTDI: begin
if (out_data_count == 0) begin
of_read_activate <= 0;
write_state <= IDLE;
end
else if (of_read_strobe) begin
//of_read_strobe <= 1;
out_data_count <= out_data_count - 1;
end
end
default: begin
of_read_activate <= 0;
write_state <= IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:31:49 11/28/2014
// Design Name:
// Module Name: multiplicadorPuntoFijo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module multiplicadorPuntoFijo #(parameter Width = 24, Magnitud = 4, Precision = 19, Signo = 1)
(EnableMul,In,Coeff,OutMul,Error);
input EnableMul;
input signed [Width-1:0] In,Coeff;
output reg signed [Width-1:0] OutMul = 0;
output Error;
reg signed [2*Width-1:0] AuxMul = 0;
reg Overflow = 0;
reg Underflow = 0;
always @* begin //Se ejecuta la multiplicación**************************************************
if (EnableMul) begin
AuxMul <= In * Coeff; // Se almacena el resultado en un temporal
end
else begin
AuxMul <= 0;
end
end
always @* begin // Detección de Overflow y underflow****************************************+
if (~In[Width-1] && ~Coeff[Width-1] && AuxMul[2*Width -1 - Magnitud - Signo]) begin
Overflow <= 1;
Underflow <= 0;
end
else if(In[Width-1] && Coeff[Width-1] && AuxMul[2*Width -1 - Magnitud - Signo]) begin
Overflow <= 1;
Underflow <= 0;
end
else if(~In[Width-1] && Coeff[Width-1] && ~AuxMul[2*Width -1 - Magnitud - Signo]) begin
Overflow <= 0;
Underflow <= 1;
end
else if(In[Width-1] && ~Coeff[Width-1] && ~AuxMul[2*Width -1 - Magnitud - Signo]) begin
Overflow <= 0;
Underflow <= 1;
end
else begin
Overflow <= 0;
Underflow <= 0;
end
end
always @* begin // Se ejecuta la salida ***************************************************************
if (In == 0 || Coeff==0) begin
OutMul <= 0;
end
else begin
if (Overflow) begin
OutMul <= 2**(Width-1) -1; // En caso que se multipliquen 2 numeros positivos y de negativo; Significa que hubo overflow
end
else begin
if (Underflow) begin
OutMul <= -2**(Width-1); // En caso que se multipliquen 1 numero negativo y el otro positivo y el resultado de positivo, sugnifica que hay underflow
end
else begin
OutMul <= AuxMul[2*Width -1 - Magnitud - Signo : Precision]; // Si no hay ni overflow ni underflow Salida es igual a resultado temporal
end
end
end
end
//****************************Errorrrrrrrrr*************************
assign Error = Overflow | Underflow;
//**********************************************************FIN DE EJECUCION MULTIPLICADOR*********************************************************
endmodule
|
`timescale 1ns / 100ps
/* This module creates a byte-wide assembly of GPIA_BIT_INs.
*/
module GPIA_BYTE_IN(
input [7:0] out_i,
input [7:0] inp_i,
input [7:0] ddr_i,
input stb_i,
output [7:0] q_o
);
GPIA_BIT_IN bit0(
.out_i(out_i[0]),
.inp_i(inp_i[0]),
.ddr_i(ddr_i[0]),
.stb_i(stb_i),
.q_o(q_o[0])
);
GPIA_BIT_IN bit1(
.out_i(out_i[1]),
.inp_i(inp_i[1]),
.ddr_i(ddr_i[1]),
.stb_i(stb_i),
.q_o(q_o[1])
);
GPIA_BIT_IN bit2(
.out_i(out_i[2]),
.inp_i(inp_i[2]),
.ddr_i(ddr_i[2]),
.stb_i(stb_i),
.q_o(q_o[2])
);
GPIA_BIT_IN bit3(
.out_i(out_i[3]),
.inp_i(inp_i[3]),
.ddr_i(ddr_i[3]),
.stb_i(stb_i),
.q_o(q_o[3])
);
GPIA_BIT_IN bit4(
.out_i(out_i[4]),
.inp_i(inp_i[4]),
.ddr_i(ddr_i[4]),
.stb_i(stb_i),
.q_o(q_o[4])
);
GPIA_BIT_IN bit5(
.out_i(out_i[5]),
.inp_i(inp_i[5]),
.ddr_i(ddr_i[5]),
.stb_i(stb_i),
.q_o(q_o[5])
);
GPIA_BIT_IN bit6(
.out_i(out_i[6]),
.inp_i(inp_i[6]),
.ddr_i(ddr_i[6]),
.stb_i(stb_i),
.q_o(q_o[6])
);
GPIA_BIT_IN bit7(
.out_i(out_i[7]),
.inp_i(inp_i[7]),
.ddr_i(ddr_i[7]),
.stb_i(stb_i),
.q_o(q_o[7])
);
endmodule
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : iReg.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 5, 2008 ** //
// ** Description : Internal Register for Newton core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 5, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Register 0 functional modification ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Register 1 and Register 2 counter modify to use ** //
// ** Write Enable bits ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** FileName : ** //
// ** Notes : Change interrupt signal to be only one clock long ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module iReg
(/*AUTOARG*/
// Outputs
ESCR, WPTR, ICNT, FREQ, OCNT, FCNT,
// Inputs
clk, arst, idata, iaddr, iwe, FIR_WE, WFIFO_WE
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter r0setclr = 15; // Register 0 set/clr bit
parameter initWM = 8'h60;
// parameter ModuleVersion = 2;
// DATA TYPE - INPUTS AND OUTPUTS
input clk; // 100MHz Clock from BUS
input arst; // Asynchronous Reset (positive logic)
input [15:0] idata;
input [13:0] iaddr;
input iwe;
input FIR_WE;
input WFIFO_WE;
output [15:0] ESCR;
output [15:0] WPTR;
output [15:0] ICNT;
output [15:0] FREQ;
output [15:0] OCNT;
output [15:0] FCNT;
// DATA TYPE - INTERNAL REG
reg OVFL_MSK; // Overflow Mask
reg WMI_MSK; // WMI Mask
reg OVFL; // Overflow for CPTR
reg WMI; // Watermark Interrupt
reg [15:0] ICNT; // Counts the numbers of inputs
reg [7:0] OCNT_WM; // Output counter watermark
reg [7:0] OCNT_int; // Counts the numbers of outputs
reg FIR_WE_dly1;
reg [10:0] CPTR;
reg [15:0] FCNT;
reg SYNC;
// reg iReg_intr_d1;
// reg iReg_intr_1d;
reg [6:0] FREQ_int;
reg NEWFREQ;
reg START;
// DATA TYPE - INTERNAL WIRES
wire setclr;
wire reg0w;
wire reg1w;
wire reg2w;
wire reg3w;
wire reg4w;
//**************************************************************************//
//* REG 1 *//
//**************************************************************************//
assign setclr = reg0w & idata[r0setclr];
assign reg0w = (iaddr[2:0] == 3'h1) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL_MSK <= 1'b0;
else if (reg0w & idata[10])
OVFL_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI_MSK <= 1'b0;
else if (reg0w & idata[9])
WMI_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL <= 1'b0;
else if (CPTR[10] == 1'b1) // BRAM pointer overflows
OVFL <= 1'b1;
else if (reg0w & idata[2])
OVFL <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
START <= 1'b0;
else if (reg0w & idata[3])
START <= idata[r0setclr];
else if (WMI | (FCNT[11:0] == 12'b1111_1111_1110))
START <= 1'b0;
else
START <= START;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FIR_WE_dly1 <= 1'b0;
else
FIR_WE_dly1 <= FIR_WE;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI <= 1'b0;
else if (FIR_WE_dly1 & (OCNT_int[7:0] == OCNT_WM[7:0])) // Output counter overflows
WMI <= 1'b1;
else if (reg0w & idata[1])
WMI <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SYNC <= 1'b0;
else if (reg0w & idata[0])
SYNC <= idata[r0setclr];
// Read out
assign ESCR[15:0] = {setclr, 4'd0, OVFL_MSK, WMI_MSK, 5'd0, START,
OVFL, WMI, SYNC};
//**************************************************************************//
//* REG 2 *//
//**************************************************************************//
/*always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SPTR[9:0] <= 10'd0;
else if (Bus2IP_WrCE[1])
SPTR[9:0] <= idata[25:16];*/
assign reg1w = (iaddr[2:0] == 3'h2) & iwe;
always @ (posedge clk or posedge SYNC)
if (SYNC != 1'b0)
CPTR[10:0] <= 11'd0;
else if (OVFL == 1'b1)
CPTR[10] <= 1'b0;
// else if (SYNC)
// CPTR[10:0] <= 11'd0;
else
CPTR[10:0] <= CPTR[10:0] + FIR_WE; //Pointer to BRAM address
// Readout
assign WPTR[15:0] = {6'd0, CPTR[9:0]};
//**************************************************************************//
//* REG 3 *//
//**************************************************************************//
assign reg2w = (iaddr[2:0] == 3'h3) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
ICNT[15:0] <= 16'd0;
else if (reg2w)
ICNT[15:0] <= idata[15:0];
else
ICNT[15:0] <= ICNT[15:0] + WFIFO_WE;
//**************************************************************************//
//* REG 4 *//
//**************************************************************************//
assign reg3w = (iaddr[2:0] == 3'h4) & iwe;
assign setclrf = reg3w & idata[7];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FREQ_int[6:0] <= 7'h41; //Resets to frequency 65MHz
else if (setclrf)
FREQ_int[6:0] <= idata[6:0];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
NEWFREQ <= 1'b0;
else if (reg3w )
NEWFREQ <= idata[14];
assign FREQ[15:0] = {1'b0, NEWFREQ, 6'd0, setclrf, FREQ_int[6:0]};
//**************************************************************************//
//* REG 5 *//
//**************************************************************************//
assign reg4w = (iaddr[2:0] == 3'h5) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_WM[7:0] <= initWM;
else if (reg4w)
OCNT_WM[7:0] <= idata[15:8];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_int[7:0] <= 8'd0;
else if (reg4w)
OCNT_int[7:0] <= idata[7:0];
else
OCNT_int[7:0] <= OCNT_int[7:0] + FIR_WE;
// Read out
assign OCNT[15:0] = {OCNT_WM[7:0], OCNT_int[7:0]};
//**************************************************************************//
//* REG 6 *//
//**************************************************************************//
assign reg5w = (iaddr[2:0] == 3'h6) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FCNT[15:0] <= 16'd0;
else if (reg5w)
FCNT[15:0] <= idata[15:0];
else if (START)
FCNT[15:0] <= FCNT[15:0] + 1;
//**************************************************************************//
//* Read Out *//
//**************************************************************************//
//always @ (/*AS*/Bus2IP_RdCE or ESCR or ICNT or OCNT or WPTR)
/*begin
IP2Bus_Data_int[31:0] = 32'b0;
case (1'b1)
Bus2IP_RdCE[0] : IP2Bus_Data_int[31:0] = ESCR[31:0];
Bus2IP_RdCE[1] : IP2Bus_Data_int[31:0] = WPTR[31:0];
Bus2IP_RdCE[2] : IP2Bus_Data_int[31:0] = ICNT[31:0];
Bus2IP_RdCE[3] : IP2Bus_Data_int[31:0] = OCNT[31:0];
endcase // case (1'b1)
end*/
// assign iReg2IP_RdAck = |Bus2IP_RdCE[0:3];
// assign IP2Bus_WrAck = |Bus2IP_WrCE[0:3];
endmodule // iReg
|
`include "bsg_defines.v"
`include "config_defs.v"
`define half_period 1
module cfg_tag_tb();
// double underscore __ separates test packet for each node
localparam test_vector_bits_lp = 319;
localparam test_vector_lp = 319'b0_0_001101010101_0_101010101001_0_110100000110_0_00000001_0_00111101_0_10__0_0_001001010101_0_101010101111_0_111100000000_0_00000001_0_00111101_0_10__0_0_000101010101_0_101010101001_0_111100000110_0_00000001_0_00111101_0_10__0_0_000001010101_0_101010101111_0_111100000000_0_00000001_0_00111101_0_10__0_0_111101010101_0_101010101111_0_111100000000_0_00000001_0_00111101_0_10__11111111111111;
logic clk_cfg;
logic rst_cfg;
logic clk;
logic rst_dst;
config_s test_config;
logic credit, valid,credit_t;
logic [31:0] data;
logic [2:0] credit_counter;
// clock and reset generator
initial begin
clk_cfg = 1;
rst_cfg = 1;
clk = 1;
rst_dst = 1;
#15 rst_cfg = 0;
#10 rst_dst = 0;
#10 rst_dst = 1;
#10 rst_dst = 0;
$display ("---------------------------------------------- reset -------------------------------------------------\n");
// Display some signals for debug
$display ("valid\t data \t\t cfg_tag_data exp_ID\n");
$monitor ("%b\t %h\t\t %h\t\t %d\n" , valid , data,cfg_tag_inst.data,cfg_tag_inst.cfgtagGW.exp_ID_r);
#1000000 $finish;
end
always #15 begin
clk_cfg = ~clk_cfg;
end
always #5 begin
clk = ~clk;
end
cfgtag #(.packet_ID_width_p(4)
,.RELAY_NUM(5)
)
cfg_tag_inst (.clk(clk)
,.reset(rst_dst)
,.cfg_clk_i(clk_cfg)
,.cfg_bit_i(test_config.cfg_bit)
,.credit_i(credit)
,.valid_o(valid)
,.data_o(data)
);
// instantiate config_setter to read configuration bits from localparams
config_setter #(.setter_vector_p(test_vector_lp),
.setter_vector_bits_p(test_vector_bits_lp) )
inst_setter (.clk_i(clk_cfg),
.reset_i(rst_cfg),
.config_o(test_config) ); // not connected in simulation testbench
// Keeps count of how many elements are in the FIFO.
fifo_counter #(3) crdit_cnt (.up_count(valid), // validIn
.down_count(credit), // thanksIn
.num_entries(credit_counter),
.reset(rst_cfg),
.clk(clk));
vcsdumper dumpp ();
// The packets become available to the core at positive edge of the clock, to be synchronous
always_ff @ (posedge clk)
begin
credit_t <= valid;
credit <= credit_t;
end
always @ (negedge clk)
if (credit_counter>3'b100)
begin
$display ("credit run out\n");
$stop;
end
endmodule
|
`timescale 1ns / 1ps
`include "zpu_core_defines.v"
/* MODULE: zpu_core
DESCRIPTION: Contains ZPU cpu
AUTHOR: Antonio J. Anton (aj <at> anro-ingenieros.com)
REVISION HISTORY:
Revision 1.0, 14/09/2009
Initial public release
COPYRIGHT:
Copyright (c) 2009 Antonio J. Anton
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.*/
// --------- MICROPROGRAMMED ZPU CORE ---------------
// all signals are polled on clk rising edge
// all signals positive
module zpu_core (
`ifdef ENABLE_CPU_INTERRUPTS
interrupt, // interrupt request
`endif
clk, // clock on rising edge
reset, // reset on rising edge
mem_read, // request memory read
mem_write, // request memory write
mem_done, // memory operation completed
mem_addr, // memory address
mem_data_read, // data readed
mem_data_write, // data written
byte_select // byte select on memory operation
);
input clk;
input reset;
output mem_read;
output mem_write;
input mem_done;
input [31:0] mem_data_read;
output [31:0] mem_data_write;
output [31:0] mem_addr;
output [3:0] byte_select;
`ifdef ENABLE_CPU_INTERRUPTS
input interrupt;
`endif
wire clk;
wire reset;
wire mem_read;
wire mem_write;
wire mem_done;
wire [31:0] mem_data_read;
wire [31:0] mem_data_write;
wire [31:0] mem_addr;
`ifdef ENABLE_CPU_INTERRUPTS
wire interrupt;
`endif
`ifdef ENABLE_BYTE_SELECT
// ------ unaligned byte/halfword memory operations -----
/// TODO: think rewriting into microcode or in a less resource wasting way
reg [3:0] byte_select;
wire byte_op;
wire halfw_op;
reg [31:0] mem_data_read_int; // aligned data from memory
reg [31:0] mem_data_write_out; // write data already aligned
wire [31:0] mem_data_write_int; // write data from cpu to be aligned
// --- byte select logic ---
always @(mem_addr[1:0] or byte_op or halfw_op)
begin
casez( { mem_addr[1:0], byte_op, halfw_op } )
4'b00_1_? : byte_select <= 4'b0001; // byte select
4'b01_1_? : byte_select <= 4'b0010;
4'b10_1_? : byte_select <= 4'b0100;
4'b11_1_? : byte_select <= 4'b1000;
4'b0?_0_1 : byte_select <= 4'b0011; // half word select
4'b1?_0_1 : byte_select <= 4'b1100;
default : byte_select <= 4'b1111; // word select
endcase
end
// --- input data to cpu ---
always @(mem_data_read or mem_addr[1:0] or byte_op or halfw_op)
begin
casez( { mem_addr[1:0], byte_op, halfw_op } )
4'b00_1_? : mem_data_read_int <= { 24'b0, mem_data_read[7:0] }; // 8 bit read
4'b01_1_? : mem_data_read_int <= { 24'b0, mem_data_read[15:8] };
4'b10_1_? : mem_data_read_int <= { 24'b0, mem_data_read[23:16] };
4'b11_1_? : mem_data_read_int <= { 24'b0, mem_data_read[31:24] };
4'b0?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[7:0], mem_data_read[15:8] }; // 16 bit read
4'b1?_0_1 : mem_data_read_int <= { 16'b0, mem_data_read[23:16], mem_data_read[31:24] };
default : mem_data_read_int <= { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] }; // 32 bit access (default)
endcase
end
// --- output data from cpu ---
assign mem_data_write = mem_data_write_out;
always @(mem_data_write_int or mem_addr[1:0] or byte_op or halfw_op)
begin
casez( {mem_addr[1:0], byte_op, halfw_op } )
4'b00_1_? : mem_data_write_out <= { 24'bX, mem_data_write_int[7:0] }; // 8 bit write
4'b01_1_? : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], 8'bX };
4'b10_1_? : mem_data_write_out <= { 8'bX, mem_data_write_int[7:0], 16'bX };
4'b11_1_? : mem_data_write_out <= { mem_data_write_int[7:0], 24'bX };
4'b0?_0_1 : mem_data_write_out <= { 16'bX, mem_data_write_int[7:0], mem_data_write_int[15:8] }; // 16 bit write
4'b1?_0_1 : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], 16'bX };
default : mem_data_write_out <= { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
endcase
end
`else
// -------- only 32 bit memory access --------
wire [3:0] byte_select = 4'b1111; // all memory operations are 32 bit wide
wire [31:0] mem_data_read_int; // no byte/halfword memory access by HW
wire [31:0] mem_data_write_int; // byte and halfword memory access must be emulated
// ----- reorder bytes due to MSB-LSB configuration -----
assign mem_data_read_int = { mem_data_read[7:0], mem_data_read[15:8], mem_data_read[23:16], mem_data_read[31:24] };
assign mem_data_write = { mem_data_write_int[7:0], mem_data_write_int[15:8], mem_data_write_int[23:16], mem_data_write_int[31:24] };
`endif
// ------ datapath registers and connections -----------
reg [31:0] pc; // program counter (byte align)
reg [31:0] sp; // stack counter (word align)
reg [31:0] a; // operand (address_out, data_out, alu_in)
reg [31:0] b; // operand (address_out)
reg idim; // im opcode being processed
reg [7:0] opcode; // opcode being processed
reg [31:2] pc_cached; // cached PC
reg [31:0] opcode_cache; // cached opcodes (current word)
`ifdef ENABLE_CPU_INTERRUPTS
reg int_requested; // interrupt has been requested
reg on_interrupt; // serving interrupt
wire exit_interrupt; // microcode says this is poppc_interrupt
wire enter_interrupt; // microcode says we are entering interrupt
`endif
wire [1:0] sel_opcode = pc[1:0]; // which opcode is selected
wire sel_read; // mux for data-in
wire [1:0] sel_alu; // mux for alu
wire [1:0] sel_addr; // mux for addr
wire w_pc; // write PC
`ifdef ENABLE_PC_INCREMENT
wire w_pc_increment; // write PC+1
`endif
wire w_sp; // write SP
wire w_a; // write A (from ALU result)
wire w_a_mem; // write A (from MEM read)
wire w_b; // write B
wire w_op; // write OPCODE (opcode cache)
wire set_idim; // set IDIM
wire clear_idim; // clear IDIM
wire is_op_cached = (pc[31:2] == pc_cached) ? 1'b1 : 1'b0; // is opcode available?
wire a_is_zero; // A == 0
wire a_is_neg; // A[31] == 1
wire busy; // busy signal to microcode sequencer (stalls cpu)
reg [`MC_MEM_BITS-1:0] mc_pc; // microcode PC
initial mc_pc <= `MC_ADDR_RESET-1;
wire [`MC_BITS-1:0] mc_op; // current microcode operation
// memory addr / write ports
assign mem_addr = (sel_addr == `SEL_ADDR_SP) ? sp :
(sel_addr == `SEL_ADDR_A) ? a :
(sel_addr == `SEL_ADDR_B) ? b : pc;
assign mem_data_write_int = a; // only A can be written to memory
// ------- alu instantiation -------
wire [31:0] alu_a;
wire [31:0] alu_b;
wire [31:0] alu_r;
wire [`ALU_OP_WIDTH-1:0] alu_op;
wire alu_done;
// alu inputs multiplexors
// constant in microcode is sign extended (in order to implement substractions like adds)
assign alu_a = (sel_read == `SEL_READ_DATA) ? mem_data_read_int : mem_addr;
assign alu_b = (sel_alu == `SEL_ALU_MC_CONST) ? { {25{mc_op[`P_ADDR+6]}} , mc_op[`P_ADDR+6:`P_ADDR] } : // most priority
(sel_alu == `SEL_ALU_A) ? a :
(sel_alu == `SEL_ALU_B) ? b : { {24{1'b0}} , opcode }; // `SEL_ALU_OPCODE is less priority
zpu_core_alu alu(
.alu_a(alu_a),
.alu_b(alu_b),
.alu_r(alu_r),
.alu_op(alu_op),
.flag_idim(idim),
.clk(clk),
.done(alu_done)
);
// -------- pc : program counter --------
always @(posedge clk)
begin
if(w_pc) pc <= alu_r;
`ifdef ENABLE_PC_INCREMENT // microcode optimization
else if(w_pc_increment) pc <= pc + 1; // usually pc=pc+1
`endif
end
// -------- sp : stack pointer --------
always @(posedge clk)
begin
if(w_sp) sp <= alu_r;
end
// -------- a : acumulator register ---------
always @(posedge clk)
begin
if(w_a) a <= alu_r;
else if(w_a_mem) a <= mem_data_read_int;
end
// alu results over a register instead of alu result
// in order to improve speed
assign a_is_zero = (a == 0);
assign a_is_neg = a[31];
// -------- b : auxiliary register ---------
always @(posedge clk)
begin
if(w_b) b <= alu_r;
end
// -------- opcode and opcode_cache --------
always @(posedge clk)
begin
if(w_op)
begin
opcode_cache <= alu_r; // store all opcodes in the word
pc_cached <= pc[31:2]; // store PC address of cached opcodes
end
end
// -------- opcode : based on pc[1:0] ---------
always @(sel_opcode or opcode_cache) // select current opcode from
begin // the cached opcode word
case(sel_opcode)
0 : opcode <= opcode_cache[31:24];
1 : opcode <= opcode_cache[23:16];
2 : opcode <= opcode_cache[15:8];
3 : opcode <= opcode_cache[7:0];
endcase
end
// ------- idim : immediate opcode handling ----------
always @(posedge clk)
begin
if(set_idim) idim <= 1'b1;
else if(clear_idim) idim <= 1'b0;
end
`ifdef ENABLE_CPU_INTERRUPTS
// ------ on interrupt status bit -----
always @(posedge clk)
begin
if(reset | exit_interrupt) on_interrupt <= 1'b0;
else if(enter_interrupt) on_interrupt <= 1'b1;
end
`endif
// ------ microcode execution unit --------
assign sel_read = mc_op[`P_SEL_READ]; // map datapath signals with microcode program bits
assign sel_alu = mc_op[`P_SEL_ALU+1:`P_SEL_ALU];
assign sel_addr = mc_op[`P_SEL_ADDR+1:`P_SEL_ADDR];
assign alu_op = mc_op[`P_ALU+3:`P_ALU];
assign w_sp = mc_op[`P_W_SP] & ~busy;
assign w_pc = mc_op[`P_W_PC] & ~busy;
assign w_a = mc_op[`P_W_A] & ~busy;
assign w_a_mem = mc_op[`P_W_A_MEM] & ~busy;
assign w_b = mc_op[`P_W_B] & ~busy;
assign w_op = mc_op[`P_W_OPCODE] & ~busy;
assign mem_read = mc_op[`P_MEM_R];
assign mem_write = mc_op[`P_MEM_W];
assign set_idim = mc_op[`P_SET_IDIM] & ~busy;
assign clear_idim= mc_op[`P_CLEAR_IDIM] & ~busy;
`ifdef ENABLE_BYTE_SELECT
assign byte_op = mc_op[`P_BYTE];
assign halfw_op = mc_op[`P_HALFWORD];
`endif
`ifdef ENABLE_PC_INCREMENT
assign w_pc_increment = mc_op[`P_PC_INCREMENT] & ~busy;
`endif
`ifdef ENABLE_CPU_INTERRUPTS
assign exit_interrupt = mc_op[`P_EXIT_INT] & ~busy;
assign enter_interrupt = mc_op[`P_ENTER_INT] & ~busy;
`endif
wire cond_op_not_cached = mc_op[`P_OP_NOT_CACHED]; // conditional: true if opcode not cached
wire cond_a_zero = mc_op[`P_A_ZERO]; // conditional: true if A is zero
wire cond_a_neg = mc_op[`P_A_NEG]; // conditional: true if A is negative
wire decode = mc_op[`P_DECODE]; // decode means jumps to apropiate microcode based on zpu opcode
wire branch = mc_op[`P_BRANCH]; // unconditional jump inside microcode
wire [`MC_MEM_BITS-1:0] mc_goto = { mc_op[`P_ADDR+6:`P_ADDR], 2'b00 }; // microcode goto (goto = high 7 bits)
wire [`MC_MEM_BITS-1:0] mc_entry = { opcode[6:0], 2'b00 }; // microcode entry point for opcode
reg [`MC_MEM_BITS-1:0] next_mc_pc; // next microcode operation to be executed
initial next_mc_pc <= `MC_ADDR_RESET-1;
wire cond_branch = (cond_op_not_cached & ~is_op_cached) | // sum of all conditionals
(cond_a_zero & a_is_zero) |
(cond_a_neg & a_is_neg);
assign busy = ((mem_read | mem_write) & ~mem_done) | ~alu_done; // busy signal for microcode sequencer
// ------- handle interrupts ---------
`ifdef ENABLE_CPU_INTERRUPTS
always @(posedge clk)
begin
if(reset | on_interrupt) int_requested <= 0;
else if(interrupt & ~on_interrupt & ~int_requested) int_requested <= 1; // interrupt requested
end
`endif
// ----- calculate next microcode address (next, decode, branch, specific opcode, etc.) -----
always @(reset or mc_pc or mc_goto or opcode[7:4] or idim or
decode or branch or cond_branch or mc_entry or busy
`ifdef ENABLE_CPU_INTERRUPTS
or int_requested
`endif
)
begin
// default, next microcode instruction
next_mc_pc <= mc_pc + 1;
if(reset) next_mc_pc <= `MC_ADDR_RESET;
else if(~busy)
begin
// get next microcode instruction
if(branch | cond_branch) next_mc_pc <= mc_goto;
else if(decode) // decode: entry point of a new zpu opcode
begin
`ifdef ENABLE_CPU_INTERRUPTS
if(int_requested & ~idim) next_mc_pc <= `MC_ADDR_INTERRUPT; // microde to enter interrupt mode
else
`endif
if(opcode[7] == `OP_IM) next_mc_pc <= (idim ? `MC_ADDR_IM_IDIM : `MC_ADDR_IM_NOIDIM);
else if(opcode[7:5] == `OP_STORESP) next_mc_pc <= `MC_ADDR_STORESP;
else if(opcode[7:5] == `OP_LOADSP) next_mc_pc <= `MC_ADDR_LOADSP;
else if(opcode[7:4] == `OP_ADDSP) next_mc_pc <= `MC_ADDR_ADDSP;
else next_mc_pc <= mc_entry; // includes EMULATE opcodes
end
end
else next_mc_pc <= mc_pc; // in case of cpu stalled (busy=1)
end
// set microcode program counter
always @(posedge clk) mc_pc <= next_mc_pc;
// ----- microcode program ------
zpu_core_rom microcode (
.addr(next_mc_pc),
.data(mc_op),
.clk(clk)
);
// -------------- ZPU debugger --------------------
`ifdef ZPU_CORE_DEBUG
//synthesis translate_off
// ---- register operation dump ----
always @(posedge clk)
begin
if(~reset)
begin
if(w_pc) $display("zpu_core: set PC=0x%h", alu.alu_r);
`ifdef ENABLE_PC_INCREMENT
if(w_pc_increment) $display("zpu_core: set PC=0x%h (PC+1)", pc);
`endif
if(w_sp) $display("zpu_core: set SP=0x%h", alu.alu_r);
if(w_a) $display("zpu_core: set A=0x%h", alu.alu_r);
if(w_a_mem) $display("zpu_core: set A=0x%h (from MEM)", mem_data_read_int);
if(w_b) $display("zpu_core: set B=0x%h", alu.alu_r);
if(w_op & ~is_op_cached) $display("zpu_core: set opcode_cache=0x%h, pc_cached=0x%h", alu.alu_r, {pc[31:2], 2'b0});
`ifdef ENABLE_CPU_INTERRUPTS
if(~busy & mc_pc == `MC_ADDR_INTERRUPT) $display("zpu_core: ***** ENTERING INTERRUPT MICROCODE ******");
if(~busy & exit_interrupt) $display("zpu_core: ***** INTERRUPT FLAG CLEARED *****");
if(~busy & enter_interrupt) $display("zpu_core: ***** INTERRUPT FLAG SET *****");
`endif
if(set_idim & ~idim) $display("zpu_core: IDIM=1");
if(clear_idim & idim) $display("zpu_core: IDIM=0");
// ---- microcode debug ----
`ifdef ZPU_CORE_DEBUG_MICROCODE
if(~busy)
begin
$display("zpu_core: mc_op[%d]=0b%b", mc_pc, mc_op);
if(branch) $display("zpu_core: microcode: branch=%d", mc_goto);
if(cond_branch) $display("zpu_core: microcode: CONDITION branch=%d", mc_goto);
if(decode) $display("zpu_core: decoding opcode=0x%h (0b%b) : branch to=%d ", opcode, opcode, mc_entry);
end
else $display("zpu_core: busy");
`endif
// ---- cpu abort in case of unaligned memory access ---
`ifdef ASSERT_NON_ALIGNMENT
/* unaligned word access (except PC) */
if(sel_addr != `SEL_ADDR_PC & mem_addr[1:0] != 2'b00 & (mem_read | mem_write) & !byte_op & !halfw_op)
begin
$display("zpu_core: unaligned word operation at addr=0x%x", mem_addr);
$finish;
end
/* unaligned halfword access */
if(mem_addr[0] & (mem_read | mem_write) & !byte_op & halfw_op)
begin
$display("zpu_core: unaligned halfword operation at addr=0x%x", mem_addr);
$finish;
end
`endif
end
end
// ----- opcode dissasembler ------
always @(posedge clk)
begin
if(~busy)
case(mc_pc)
0 : begin
$display("zpu_core: ------ breakpoint ------");
$finish;
end
4 : $display("zpu_core: ------ shiftleft ------");
8 : $display("zpu_core: ------ pushsp ------");
12 : $display("zpu_core: ------ popint ------");
16 : $display("zpu_core: ------ poppc ------");
20 : $display("zpu_core: ------ add ------");
24 : $display("zpu_core: ------ and ------");
28 : $display("zpu_core: ------ or ------");
32 : $display("zpu_core: ------ load ------");
36 : $display("zpu_core: ------ not ------");
40 : $display("zpu_core: ------ flip ------");
44 : $display("zpu_core: ------ nop ------");
48 : $display("zpu_core: ------ store ------");
52 : $display("zpu_core: ------ popsp ------");
56 : $display("zpu_core: ------ ipsum ------");
60 : $display("zpu_core: ------ sncpy ------");
`MC_ADDR_IM_NOIDIM : $display("zpu_core: ------ im 0x%h (1st) ------", opcode[6:0] );
`MC_ADDR_IM_IDIM : $display("zpu_core: ------ im 0x%h (cont) ------", opcode[6:0] );
`MC_ADDR_STORESP : $display("zpu_core: ------ storesp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
`MC_ADDR_LOADSP : $display("zpu_core: ------ loadsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
`MC_ADDR_ADDSP : $display("zpu_core: ------ addsp 0x%h ------", { ~opcode[4], opcode[3:0], 2'b0 } );
`MC_ADDR_EMULATE : $display("zpu_core: ------ emulate 0x%h ------", b[2:0]); // opcode[5:0] );
128 : $display("zpu_core: ------ mcpy ------");
132 : $display("zpu_core: ------ mset ------");
136 : $display("zpu_core: ------ loadh ------");
140 : $display("zpu_core: ------ storeh ------");
144 : $display("zpu_core: ------ lessthan ------");
148 : $display("zpu_core: ------ lessthanorequal ------");
152 : $display("zpu_core: ------ ulessthan ------");
156 : $display("zpu_core: ------ ulessthanorequal ------");
160 : $display("zpu_core: ------ swap ------");
164 : $display("zpu_core: ------ mult ------");
168 : $display("zpu_core: ------ lshiftright ------");
172 : $display("zpu_core: ------ ashiftleft ------");
176 : $display("zpu_core: ------ ashiftright ------");
180 : $display("zpu_core: ------ call ------");
184 : $display("zpu_core: ------ eq ------");
188 : $display("zpu_core: ------ neq ------");
192 : $display("zpu_core: ------ neg ------");
196 : $display("zpu_core: ------ sub ------");
200 : $display("zpu_core: ------ xor ------");
204 : $display("zpu_core: ------ loadb ------");
208 : $display("zpu_core: ------ storeb ------");
212 : $display("zpu_core: ------ div ------");
216 : $display("zpu_core: ------ mod ------");
220 : $display("zpu_core: ------ eqbranch ------");
224 : $display("zpu_core: ------ neqbranch ------");
228 : $display("zpu_core: ------ poppcrel ------");
232 : $display("zpu_core: ------ config ------");
236 : $display("zpu_core: ------ pushpc ------");
240 : $display("zpu_core: ------ syscall_emulate ------");
244 : $display("zpu_core: ------ pushspadd ------");
248 : $display("zpu_core: ------ halfmult ------");
252 : $display("zpu_core: ------ callpcrel ------");
//default : $display("zpu_core: mc_pc=0x%h", decode_mcpc);
endcase
end
//synthesis translate_on
`endif
endmodule
// --------- ZPU CORE ALU UNIT ---------------
module zpu_core_alu(
alu_a, // parameter A
alu_b, // parameter B
alu_r, // computed result
flag_idim, // for IMM alu op
alu_op, // ALU operation
clk, // clock for syncronous multicycle operations
done // done signal for alu operation
);
input [31:0] alu_a;
input [31:0] alu_b;
input [`ALU_OP_WIDTH-1:0] alu_op;
input flag_idim;
output [31:0] alu_r;
input clk;
output done;
wire [31:0] alu_a;
wire [31:0] alu_b;
wire [`ALU_OP_WIDTH-1:0] alu_op;
wire flag_idim;
reg [31:0] alu_r;
wire clk;
reg done;
`ifdef ENABLE_MULT
// implement 32 bit pipeline multiplier
reg mul_running;
reg [2:0] mul_counter;
wire mul_done = (mul_counter == 3);
reg [31:0] mul_result, mul_tmp1;
reg [31:0] a_in, b_in;
always@(posedge clk)
begin
a_in <= 0;
b_in <= 0;
mul_tmp1 <= 0;
mul_result <= 0;
mul_counter <= 0;
if(mul_running)
begin // infer pipeline multiplier
a_in <= alu_a;
b_in <= alu_b;
mul_tmp1 <= a_in * b_in;
mul_result <= mul_tmp1;
mul_counter <= mul_counter + 1;
end
end
`endif
`ifdef ENABLE_DIV
// implement 32 bit divider
// Unsigned/Signed division based on Patterson and Hennessy's algorithm.
// Description: Calculates quotient. The "sign" input determines whether
// signs (two's complement) should be taken into consideration.
// references: http://www.ece.lsu.edu/ee3755/2002/l07.html
reg [63:0] qr;
wire [33:0] diff;
wire [31:0] quotient;
wire [31:0] dividend;
wire [31:0] divider;
reg [6:0] bit;
wire div_done;
reg div_running;
reg divide_sign;
reg negative_output;
assign div_done = !bit;
assign diff = qr[63:31] - {1'b0, divider};
assign quotient = (!negative_output) ? qr[31:0] : ~qr[31:0] + 1'b1;
assign dividend = (!divide_sign || !alu_a[31]) ? alu_a : ~alu_a + 1'b1;
assign divider = (!divide_sign || !alu_b[31]) ? alu_b : ~alu_b + 1'b1;
always@(posedge clk)
begin
bit <= 7'b1_000000; // divider stopped
if(div_running)
begin
if(bit[6]) // divider started: initialize registers
begin
bit <= 7'd32;
qr <= { 32'd0, dividend };
negative_output <= divide_sign && ((alu_b[31] && !alu_a[31]) || (!alu_b[31] && alu_a[31]));
end
else // step by step divide
begin
if( diff[32] ) qr <= { qr[62:0], 1'd0 };
else qr <= { diff[31:0], qr[30:0], 1'd1 };
bit <= bit - 1;
end
end
end
`endif
`ifdef ENABLE_BARREL
// implement 32 bit barrel shift
// alu_b[6] == 1 ? left(only arithmetic) : right
// alu_b[5] == 1 ? logical : arithmetic
reg bs_running;
reg [31:0] bs_result;
reg [4:0] bs_counter; // 5 bits
wire bs_left = alu_b[6];
wire bs_logical = alu_b[5];
wire [4:0] bs_moves = alu_b[4:0];
wire bs_done = (bs_counter == bs_moves);
always @(posedge clk)
begin
bs_counter <= 0;
bs_result <= alu_a;
if(bs_running)
begin
if(bs_left) bs_result <= { bs_result[30:0], 1'b0 }; // shift left
else
begin
if(bs_logical) bs_result <= { 1'b0, bs_result[31:1] }; // shift logical right
else bs_result <= { bs_result[31], bs_result[31], bs_result[30:1] };// shift arithmetic right
end
bs_counter <= bs_counter + 1;
end
end
`endif
// ----- alu add/sub -----
reg [31:0] alu_b_tmp;
always @(alu_b or alu_op)
begin
alu_b_tmp <= alu_b; // by default, ALU_B as is
if(alu_op == `ALU_PLUS_OFFSET) alu_b_tmp <= { {25{1'b0}}, ~alu_b[4], alu_b[3:0], 2'b0 }; // ALU_B is an offset if ALU_PLUS_OFFSET operation
end
reg [31:0] alu_r_addsub; // compute R=A+B or A-B based on opcode (ALU_PLUSxx / ALU_SUB-CMP)
always @(alu_a or alu_b_tmp or alu_op)
begin
`ifdef ENABLE_CMP
if(alu_op == `ALU_CMP_SIGNED || alu_op == `ALU_CMP_UNSIGNED) // in case of sub or cmp --> operation is '-'
begin
alu_r_addsub <= alu_a - alu_b_tmp;
end
else
`endif
begin
alu_r_addsub <= alu_a + alu_b_tmp; // by default '+' operation
end
end
`ifdef ENABLE_CMP
// handle overflow/underflow exceptions in ALU_CMP_SIGNED
reg cmp_exception;
always @(alu_a[31] or alu_b[31] or alu_r_addsub[31])
begin
cmp_exception <= 0;
if( (alu_a[31] == 0 && alu_b[31] == 1 && alu_r_addsub[31] == 1) ||
(alu_a[31] == 1 && alu_b[31] == 0 && alu_r_addsub[31] == 0) ) cmp_exception <= 1;
end
`endif
// ----- alu operation selection -----
always @(alu_a or alu_b or alu_op or flag_idim or alu_r_addsub
`ifdef ENABLE_CMP
or cmp_exception
`endif
`ifdef ENABLE_MULT
or mul_done or mul_result
`endif
`ifdef ENABLE_BARREL
or bs_done or bs_result
`endif
`ifdef ENABLE_DIV
or div_done or div_result
`endif
)
begin
done <= 1; // default alu operations are 1 cycle
`ifdef ENABLE_MULT
mul_running <= 0;
`endif
`ifdef ENABLE_BARREL
bs_running <= 0;
`endif
`ifdef ENABLE_DIV
div_running <= 0;
`endif
alu_r <= alu_r_addsub; // ALU_PLUS, ALU_PLUS_OFFSET, ALU_SUB and part of ALU_CMP
case(alu_op)
`ALU_NOP : alu_r <= alu_a;
`ALU_NOP_B : alu_r <= alu_b;
`ALU_AND : alu_r <= alu_a & alu_b;
`ALU_OR : alu_r <= alu_a | alu_b;
`ALU_NOT : alu_r <= ~alu_a;
`ALU_FLIP : alu_r <= { alu_a[0], alu_a[1], alu_a[2], alu_a[3], alu_a[4], alu_a[5], alu_a[6], alu_a[7],
alu_a[8],alu_a[9],alu_a[10],alu_a[11],alu_a[12],alu_a[13],alu_a[14],alu_a[15],
alu_a[16],alu_a[17],alu_a[18],alu_a[19],alu_a[20],alu_a[21],alu_a[22],alu_a[23],
alu_a[24],alu_a[25],alu_a[26],alu_a[27],alu_a[28],alu_a[29],alu_a[30],alu_a[31] };
`ALU_IM : if(flag_idim) alu_r <= { alu_a[24:0], alu_b[6:0] };
else alu_r <= { {25{alu_b[6]}}, alu_b[6:0] };
`ifdef ENABLE_CMP
`ALU_CMP_UNSIGNED:if( (alu_a[31] == alu_b[31] && cmp_exception) ||
(alu_a[31] != alu_b[31] && ~cmp_exception) )
begin
alu_r[31] <= ~alu_r_addsub[31];
end
`ALU_CMP_SIGNED : if(cmp_exception)
begin
alu_r[31] <= ~alu_r_addsub[31];
end
`endif
`ifdef ENABLE_XOR
`ALU_XOR : alu_r <= alu_a ^ alu_b;
`endif
`ifdef ENABLE_A_SHIFT
`ALU_A_SHIFT_RIGHT: alu_r <= { alu_a[31], alu_a[31], alu_a[30:1] }; // arithmetic shift left
`endif
`ifdef ENABLE_MULT
`ALU_MULT : begin
mul_running <= ~mul_done;
done <= mul_done;
alu_r <= mul_result;
end
`endif
`ifdef ENABLE_BARREL
`ALU_BARREL : begin
bs_running <= ~bs_done;
done <= bs_done;
alu_r <= bs_result;
end
`endif
`ifdef ENABLE_DIV
`ALU_DIV : begin
div_running<= ~div_done;
done <= div_done;
alu_r <= quotient;
end
`ALU_MOD : begin
div_running<= ~div_done;
done <= div_done;
alu_r <= qr[31:0];
end
`endif
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O21BAI_BEHAVIORAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_BEHAVIORAL_V |
(** * Rel: Properties of Relations *)
Require Export SfLib.
(** This short, optional chapter develops some basic definitions and a
few theorems about binary relations in Coq. The key definitions
are repeated where they are actually used (in the [Smallstep]
chapter), so readers who are already comfortable with these ideas
can safely skim or skip this chapter. However, relations are also
a good source of exercises for developing facility with Coq's
basic reasoning facilities, so it may be useful to look at it just
after the [Logic] chapter. *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-than-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====> Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m *)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** As anyone knows who has taken an undergraduate discrete math
course, there is a lot to be said about relations in general --
ways of classifying relations (are they reflexive, transitive,
etc.), theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. For example... *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined earlier is a partial
function. *)
Print next_nat.
(* ====> Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n) *)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed.
(** However, the [<=] relation on numbers is not a partial function.
In short: Assume, for a contradiction, that [<=] is a partial
function. But then, since [0 <= 0] and [0 <= 1], it follows that
[0 = 1]. This is nonsense, so our assumption was
contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
{ (* Proof of assertion *)
apply Hc with (x := 0).
- apply le_n.
- apply le_S. apply le_n. }
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in earlier is not a partial
function. *)
Theorem total_relation_not_a_partial_function :
~ (partial_function total_relation).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
{ (* Proof of assertion *)
apply Hc with (x := 0).
- apply tot.
- apply tot. }
inversion Nonsense.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined earlier is a partial
function. *)
Theorem empty_relation_is_a_partial_function :
partial_function empty_relation.
Proof.
unfold partial_function.
intros.
inversion H0.
Qed.
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
- (* le_n *) apply Hnm.
- (* le_S *) apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *)
- apply le_S. apply Hnm.
- apply le_trans with (a := (S n)) (b := (S m)) (c := (S m')).
+ apply le_S. apply Hnm.
+ apply le_S. apply Hm'o.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional 8 *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
unfold not. unfold symmetric. intros.
assert (1 <= 0) as Nonsense.
{ apply H. apply le_S. apply le_n. }
inversion Nonsense.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional 9 *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
unfold antisymmetric.
intros a.
induction a.
- intros. destruct b.
+ reflexivity.
+ inversion H0.
- intros.
inversion H.
+ reflexivity.
+ inversion H0.
* rewrite <- H2 in H3. rewrite H3. reflexivity.
* apply eq_S. apply IHa.
{
apply le_Sn_le. apply H1.
}
{
rewrite <- H2 in H0. apply le_Sn_le. rewrite H2. apply H4.
}
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
- (* refl *) apply le_reflexive.
- split.
+ (* antisym *) apply le_antisymmetric.
+ (* transitive. *) apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
- (* -> *)
intro H. induction H.
+ (* le_n *) apply rt_refl.
+ (* le_S *)
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
- (* <- *)
intro H. induction H.
+ (* rt_step *) inversion H. apply le_S. apply le_n.
+ (* rt_refl *) apply le_n.
+ (* rt_trans *)
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
intros.
induction H.
- apply H0.
- apply rsc_step with y.
* apply H.
* apply IHrefl_step_closure. apply H0.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
split.
- intros. induction H.
+ apply rsc_step with y.
* apply H.
* apply rsc_refl.
+ apply rsc_refl.
+ apply rsc_trans with y.
* apply IHclos_refl_trans1.
* apply IHclos_refl_trans2.
- intros. induction H.
+ apply rt_refl.
+ apply rt_trans with y.
* apply rt_step. apply H.
* apply IHrefl_step_closure.
Qed.
(** [] *)
(** $Date: 2015-08-10 18:00:14 +0200 (Mon, 10 Aug 2015) $ *)
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Dilate_32_32_1080_1920_s (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_src_rows_V_read,
p_src_cols_V_read,
p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 8'b1;
parameter ap_ST_st2_fsm_1 = 8'b10;
parameter ap_ST_st3_fsm_2 = 8'b100;
parameter ap_ST_st4_fsm_3 = 8'b1000;
parameter ap_ST_st5_fsm_4 = 8'b10000;
parameter ap_ST_st6_fsm_5 = 8'b100000;
parameter ap_ST_pp0_stg0_fsm_6 = 8'b1000000;
parameter ap_ST_st20_fsm_7 = 8'b10000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv11_5 = 11'b101;
parameter ap_const_lv11_2 = 11'b10;
parameter ap_const_lv11_7FD = 11'b11111111101;
parameter ap_const_lv12_3 = 12'b11;
parameter ap_const_lv11_7FF = 11'b11111111111;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv11_4 = 11'b100;
parameter ap_const_lv12_FFC = 12'b111111111100;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv12_FFF = 12'b111111111111;
parameter ap_const_lv12_FFB = 12'b111111111011;
parameter ap_const_lv12_FFA = 12'b111111111010;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] p_src_rows_V_read;
input [11:0] p_src_cols_V_read;
input [7:0] p_src_data_stream_0_V_dout;
input p_src_data_stream_0_V_empty_n;
output p_src_data_stream_0_V_read;
input [7:0] p_src_data_stream_1_V_dout;
input p_src_data_stream_1_V_empty_n;
output p_src_data_stream_1_V_read;
input [7:0] p_src_data_stream_2_V_dout;
input p_src_data_stream_2_V_empty_n;
output p_src_data_stream_2_V_read;
output [7:0] p_dst_data_stream_0_V_din;
input p_dst_data_stream_0_V_full_n;
output p_dst_data_stream_0_V_write;
output [7:0] p_dst_data_stream_1_V_din;
input p_dst_data_stream_1_V_full_n;
output p_dst_data_stream_1_V_write;
output [7:0] p_dst_data_stream_2_V_din;
input p_dst_data_stream_2_V_full_n;
output p_dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [7:0] ap_CS_fsm = 8'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_27;
reg [10:0] p_025_0_i_i_reg_656;
reg ap_sig_bdd_67;
wire [10:0] tmp_fu_884_p1;
reg [10:0] tmp_reg_2745;
wire [10:0] tmp_107_fu_888_p1;
reg [10:0] tmp_107_reg_2751;
wire [12:0] cols_assign_cast2_fu_892_p1;
reg [12:0] cols_assign_cast2_reg_2757;
wire [1:0] tmp_40_fu_896_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_85;
wire [1:0] tmp_42_fu_908_p2;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_94;
wire [1:0] tmp_45_fu_920_p2;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_103;
wire [10:0] heightloop_fu_932_p2;
reg [10:0] heightloop_reg_3051;
wire [0:0] tmp_46_fu_926_p2;
wire [10:0] widthloop_fu_937_p2;
reg [10:0] widthloop_reg_3056;
wire [11:0] tmp_52_cast_fu_947_p1;
reg [11:0] tmp_52_cast_reg_3061;
wire [11:0] p_neg226_i_i_fu_951_p2;
reg [11:0] p_neg226_i_i_reg_3068;
wire [1:0] tmp_108_fu_956_p1;
reg [1:0] tmp_108_reg_3076;
wire [10:0] ref_fu_960_p2;
reg [10:0] ref_reg_3084;
wire [11:0] ref_cast_fu_965_p1;
reg [11:0] ref_cast_reg_3089;
wire [1:0] tmp_110_fu_969_p1;
reg [1:0] tmp_110_reg_3094;
wire [11:0] tmp_53_cast_cast3_fu_973_p1;
reg [11:0] tmp_53_cast_cast3_reg_3099;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_133;
wire [10:0] i_V_fu_982_p2;
reg [10:0] i_V_reg_3108;
wire [0:0] tmp_50_fu_988_p2;
reg [0:0] tmp_50_reg_3113;
wire [0:0] tmp_48_fu_977_p2;
wire [11:0] ImagLoc_y_fu_994_p2;
reg [11:0] ImagLoc_y_reg_3118;
wire [0:0] or_cond_2_fu_1021_p2;
reg [0:0] or_cond_2_reg_3126;
reg [0:0] tmp_112_reg_3131;
wire [1:0] tmp_52_fu_1035_p3;
reg [1:0] tmp_52_reg_3135;
wire [1:0] tmp_113_fu_1049_p1;
reg [1:0] tmp_113_reg_3149;
wire [1:0] tmp_115_fu_1053_p1;
reg [1:0] tmp_115_reg_3155;
wire [11:0] y_2_2_fu_1062_p2;
reg [11:0] y_2_2_reg_3162;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_162;
wire [11:0] y_2_2_1_fu_1067_p2;
reg [11:0] y_2_2_1_reg_3169;
wire [0:0] brmerge_fu_1072_p2;
reg [0:0] brmerge_reg_3176;
wire [0:0] tmp_53_fu_1081_p2;
reg [0:0] tmp_53_reg_3180;
reg ap_sig_cseq_ST_pp0_stg0_fsm_6;
reg ap_sig_bdd_175;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it5;
reg [0:0] or_cond2_reg_3206;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it5;
reg [0:0] or_cond2_1_reg_3228;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5;
reg [0:0] or_cond2_2_reg_3248;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5;
reg ap_sig_bdd_218;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg [0:0] or_cond219_i_i_reg_3189;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11;
reg ap_sig_bdd_244;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it6;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it7;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it8;
reg [0:0] ap_reg_ppstg_tmp_53_reg_3180_pp0_it9;
wire [10:0] j_V_fu_1086_p2;
wire [0:0] or_cond219_i_i_fu_1108_p2;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9;
reg [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10;
wire [11:0] ImagLoc_x_fu_1113_p2;
reg [11:0] ImagLoc_x_reg_3193;
wire [0:0] tmp_57_fu_1133_p2;
reg [0:0] tmp_57_reg_3202;
reg [0:0] ap_reg_ppstg_tmp_57_reg_3202_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_57_reg_3202_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_57_reg_3202_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_57_reg_3202_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_57_reg_3202_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_57_reg_3202_pp0_it6;
wire [0:0] or_cond2_fu_1138_p2;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it6;
reg [0:0] tmp_119_reg_3210;
reg [0:0] ap_reg_ppstg_tmp_119_reg_3210_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_119_reg_3210_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_119_reg_3210_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_119_reg_3210_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_119_reg_3210_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_119_reg_3210_pp0_it6;
wire [0:0] tmp_58_fu_1152_p2;
reg [0:0] tmp_58_reg_3214;
reg [0:0] ap_reg_ppstg_tmp_58_reg_3214_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_58_reg_3214_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_58_reg_3214_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_58_reg_3214_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_58_reg_3214_pp0_it5;
wire [1:0] col_assign_fu_1157_p2;
reg [1:0] col_assign_reg_3218;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it1;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it2;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it3;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it4;
reg [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it5;
wire [0:0] tmp_170_1_fu_1168_p2;
reg [0:0] tmp_170_1_reg_3224;
reg [0:0] ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6;
wire [0:0] or_cond2_1_fu_1173_p2;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6;
reg [0:0] tmp_124_reg_3232;
reg [0:0] ap_reg_ppstg_tmp_124_reg_3232_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_124_reg_3232_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_124_reg_3232_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_124_reg_3232_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_124_reg_3232_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_124_reg_3232_pp0_it6;
wire [0:0] tmp_173_1_fu_1187_p2;
reg [0:0] tmp_173_1_reg_3236;
reg [0:0] ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5;
wire [1:0] tmp_128_fu_1197_p1;
reg [1:0] tmp_128_reg_3240;
reg [1:0] ap_reg_ppstg_tmp_128_reg_3240_pp0_it1;
reg [1:0] ap_reg_ppstg_tmp_128_reg_3240_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_128_reg_3240_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_128_reg_3240_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_128_reg_3240_pp0_it5;
wire [0:0] tmp_170_2_fu_1207_p2;
reg [0:0] tmp_170_2_reg_3244;
reg [0:0] ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6;
wire [0:0] or_cond2_2_fu_1212_p2;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4;
reg [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6;
reg [0:0] tmp_133_reg_3252;
reg [0:0] ap_reg_ppstg_tmp_133_reg_3252_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_133_reg_3252_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_133_reg_3252_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_133_reg_3252_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_133_reg_3252_pp0_it5;
reg [0:0] ap_reg_ppstg_tmp_133_reg_3252_pp0_it6;
wire [0:0] tmp_173_2_fu_1226_p2;
reg [0:0] tmp_173_2_reg_3256;
reg [0:0] ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it1;
reg [0:0] ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it2;
reg [0:0] ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it3;
reg [0:0] ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it4;
reg [0:0] ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5;
wire [1:0] tmp_137_fu_1236_p1;
reg [1:0] tmp_137_reg_3260;
reg [1:0] ap_reg_ppstg_tmp_137_reg_3260_pp0_it1;
reg [1:0] ap_reg_ppstg_tmp_137_reg_3260_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_137_reg_3260_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_137_reg_3260_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_137_reg_3260_pp0_it5;
wire [1:0] tmp_131_fu_1244_p1;
reg [1:0] tmp_131_reg_3264;
reg [1:0] ap_reg_ppstg_tmp_131_reg_3264_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_131_reg_3264_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_131_reg_3264_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_131_reg_3264_pp0_it5;
wire [1:0] tmp_140_fu_1252_p1;
reg [1:0] tmp_140_reg_3270;
reg [1:0] ap_reg_ppstg_tmp_140_reg_3270_pp0_it2;
reg [1:0] ap_reg_ppstg_tmp_140_reg_3270_pp0_it3;
reg [1:0] ap_reg_ppstg_tmp_140_reg_3270_pp0_it4;
reg [1:0] ap_reg_ppstg_tmp_140_reg_3270_pp0_it5;
wire [1:0] tmp_122_fu_1256_p1;
reg [1:0] tmp_122_reg_3276;
wire [1:0] tmp_127_fu_1260_p1;
reg [1:0] tmp_127_reg_3281;
wire [1:0] tmp_136_fu_1264_p1;
reg [1:0] tmp_136_reg_3286;
wire [14:0] grp_image_filter_borderInterpolate_fu_692_ap_return;
reg [14:0] x_reg_3291;
wire [1:0] tmp_118_fu_1268_p1;
reg [1:0] tmp_118_reg_3296;
reg [1:0] ap_reg_ppstg_tmp_118_reg_3296_pp0_it5;
wire [1:0] locy_0_2_t_fu_1272_p2;
reg [1:0] locy_0_2_t_reg_3301;
reg [1:0] ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5;
reg [1:0] ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6;
wire [14:0] grp_image_filter_borderInterpolate_fu_700_ap_return;
reg [14:0] x_1_reg_3305;
reg [14:0] ap_reg_ppstg_x_1_reg_3305_pp0_it5;
wire [1:0] locy_1_2_t_fu_1276_p2;
reg [1:0] locy_1_2_t_reg_3313;
reg [1:0] ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5;
reg [1:0] ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6;
wire [14:0] grp_image_filter_borderInterpolate_fu_708_ap_return;
reg [14:0] x_2_reg_3317;
reg [14:0] ap_reg_ppstg_x_2_reg_3317_pp0_it5;
wire [1:0] locy_2_2_t_fu_1280_p2;
reg [1:0] locy_2_2_t_reg_3325;
reg [1:0] ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5;
reg [1:0] ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6;
reg [10:0] k_buf_0_val_0_addr_reg_3329;
reg [10:0] k_buf_0_val_1_addr_reg_3335;
reg [10:0] k_buf_0_val_2_addr_reg_3341;
wire [7:0] k_buf_0_val_0_q0;
reg [7:0] right_border_buf_0_val_2_0_reg_3377;
wire [7:0] k_buf_0_val_1_q0;
reg [7:0] right_border_buf_0_val_1_0_reg_3382;
wire [7:0] k_buf_0_val_2_q0;
reg [7:0] src_kernel_win_0_val_2_0_reg_3390;
wire [1:0] tmp_120_fu_1311_p1;
reg [1:0] tmp_120_reg_3397;
wire [1:0] tmp_121_fu_1315_p1;
reg [1:0] tmp_121_reg_3403;
wire [1:0] col_assign_8_fu_1319_p2;
reg [1:0] col_assign_8_reg_3409;
wire [7:0] k_buf_1_val_0_q0;
reg [7:0] right_border_buf_1_val_2_0_reg_3415;
wire [7:0] k_buf_1_val_1_q0;
reg [7:0] right_border_buf_1_val_1_0_reg_3420;
wire [7:0] k_buf_1_val_2_q0;
reg [7:0] src_kernel_win_1_val_2_0_reg_3428;
wire [1:0] tmp_125_fu_1423_p1;
reg [1:0] tmp_125_reg_3435;
wire [1:0] tmp_126_fu_1427_p1;
reg [1:0] tmp_126_reg_3441;
wire [0:0] tmp_129_fu_1440_p3;
reg [0:0] tmp_129_reg_3447;
wire [1:0] col_assign_8_1_t1_fu_1450_p2;
reg [1:0] col_assign_8_1_t1_reg_3453;
wire [7:0] col_buf_1_val_0_0_25_fu_1475_p3;
reg [7:0] col_buf_1_val_0_0_25_reg_3457;
wire [0:0] sel_tmp59_fu_1489_p2;
reg [0:0] sel_tmp59_reg_3463;
wire [0:0] sel_tmp60_fu_1495_p2;
reg [0:0] sel_tmp60_reg_3469;
wire [7:0] k_buf_2_val_0_q0;
reg [7:0] right_border_buf_2_val_2_0_reg_3474;
wire [7:0] k_buf_2_val_1_q0;
reg [7:0] right_border_buf_2_val_1_0_reg_3479;
wire [7:0] k_buf_2_val_2_q0;
reg [7:0] src_kernel_win_2_val_2_0_reg_3487;
wire [1:0] tmp_134_fu_1609_p1;
reg [1:0] tmp_134_reg_3494;
wire [1:0] tmp_135_fu_1613_p1;
reg [1:0] tmp_135_reg_3500;
wire [0:0] tmp_138_fu_1626_p3;
reg [0:0] tmp_138_reg_3506;
wire [1:0] col_assign_8_2_t1_fu_1636_p2;
reg [1:0] col_assign_8_2_t1_reg_3512;
wire [7:0] col_buf_2_val_0_0_25_fu_1661_p3;
reg [7:0] col_buf_2_val_0_0_25_reg_3516;
wire [0:0] sel_tmp71_fu_1675_p2;
reg [0:0] sel_tmp71_reg_3522;
wire [0:0] sel_tmp72_fu_1681_p2;
reg [0:0] sel_tmp72_reg_3528;
reg [7:0] src_kernel_win_0_val_0_1_18_reg_3533;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it8;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it10;
reg [7:0] src_kernel_win_0_val_1_1_18_reg_3540;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_1_1_18_reg_3540_pp0_it8;
reg [7:0] src_kernel_win_1_val_0_1_18_reg_3547;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it8;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it10;
reg [7:0] src_kernel_win_1_val_1_1_18_reg_3554;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_1_1_18_reg_3554_pp0_it8;
reg [7:0] src_kernel_win_2_val_0_1_18_reg_3561;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it8;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it10;
reg [7:0] src_kernel_win_2_val_1_1_18_reg_3568;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_1_1_18_reg_3568_pp0_it8;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587;
reg [7:0] src_kernel_win_0_val_0_1_lo_reg_3593;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11;
reg [7:0] src_kernel_win_0_val_1_1_lo_reg_3599;
reg [7:0] ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9;
reg [7:0] src_kernel_win_0_val_1_2_lo_reg_3605;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610;
wire [0:0] tmp_220_0_1_fu_2364_p2;
reg [0:0] tmp_220_0_1_reg_3615;
reg [7:0] src_kernel_win_1_val_0_1_lo_reg_3620;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11;
reg [7:0] src_kernel_win_1_val_1_1_lo_reg_3626;
reg [7:0] ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9;
reg [7:0] src_kernel_win_1_val_1_2_lo_reg_3632;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637;
wire [0:0] tmp_220_1_1_fu_2394_p2;
reg [0:0] tmp_220_1_1_reg_3642;
reg [7:0] src_kernel_win_2_val_0_1_lo_reg_3647;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11;
reg [7:0] src_kernel_win_2_val_1_1_lo_reg_3653;
reg [7:0] ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9;
reg [7:0] src_kernel_win_2_val_1_2_lo_reg_3659;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664;
wire [0:0] tmp_220_2_1_fu_2424_p2;
reg [0:0] tmp_220_2_1_reg_3669;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686;
reg [7:0] src_kernel_win_0_val_0_2_lo_reg_3692;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697;
wire [0:0] tmp_220_0_2_fu_2506_p2;
reg [0:0] tmp_220_0_2_reg_3702;
reg [7:0] src_kernel_win_1_val_0_2_lo_reg_3707;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712;
wire [0:0] tmp_220_1_2_fu_2525_p2;
reg [0:0] tmp_220_1_2_reg_3717;
reg [7:0] src_kernel_win_2_val_0_2_lo_reg_3722;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727;
wire [0:0] tmp_220_2_2_fu_2544_p2;
reg [0:0] tmp_220_2_2_reg_3732;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3;
reg [7:0] temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749;
wire [10:0] k_buf_0_val_0_address0;
reg k_buf_0_val_0_ce0;
wire [10:0] k_buf_0_val_0_address1;
reg k_buf_0_val_0_ce1;
reg k_buf_0_val_0_we1;
wire [7:0] k_buf_0_val_0_d1;
wire [10:0] k_buf_0_val_1_address0;
reg k_buf_0_val_1_ce0;
wire [10:0] k_buf_0_val_1_address1;
reg k_buf_0_val_1_ce1;
reg k_buf_0_val_1_we1;
wire [7:0] k_buf_0_val_1_d1;
wire [10:0] k_buf_0_val_2_address0;
reg k_buf_0_val_2_ce0;
wire [10:0] k_buf_0_val_2_address1;
reg k_buf_0_val_2_ce1;
reg k_buf_0_val_2_we1;
wire [7:0] k_buf_0_val_2_d1;
wire [10:0] k_buf_1_val_0_address0;
reg k_buf_1_val_0_ce0;
wire [10:0] k_buf_1_val_0_address1;
reg k_buf_1_val_0_ce1;
reg k_buf_1_val_0_we1;
wire [7:0] k_buf_1_val_0_d1;
wire [10:0] k_buf_1_val_1_address0;
reg k_buf_1_val_1_ce0;
reg [10:0] k_buf_1_val_1_address1;
reg k_buf_1_val_1_ce1;
reg k_buf_1_val_1_we1;
wire [7:0] k_buf_1_val_1_d1;
wire [10:0] k_buf_1_val_2_address0;
reg k_buf_1_val_2_ce0;
wire [10:0] k_buf_1_val_2_address1;
reg k_buf_1_val_2_ce1;
reg k_buf_1_val_2_we1;
wire [7:0] k_buf_1_val_2_d1;
wire [10:0] k_buf_2_val_0_address0;
reg k_buf_2_val_0_ce0;
wire [10:0] k_buf_2_val_0_address1;
reg k_buf_2_val_0_ce1;
reg k_buf_2_val_0_we1;
wire [7:0] k_buf_2_val_0_d1;
wire [10:0] k_buf_2_val_1_address0;
reg k_buf_2_val_1_ce0;
reg [10:0] k_buf_2_val_1_address1;
reg k_buf_2_val_1_ce1;
reg k_buf_2_val_1_we1;
wire [7:0] k_buf_2_val_1_d1;
wire [10:0] k_buf_2_val_2_address0;
reg k_buf_2_val_2_ce0;
wire [10:0] k_buf_2_val_2_address1;
reg k_buf_2_val_2_ce1;
reg k_buf_2_val_2_we1;
wire [7:0] k_buf_2_val_2_d1;
wire [11:0] grp_image_filter_borderInterpolate_fu_668_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_668_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_668_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_668_ap_return;
reg grp_image_filter_borderInterpolate_fu_668_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_676_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_676_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_676_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_676_ap_return;
reg grp_image_filter_borderInterpolate_fu_676_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_684_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_684_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_684_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_684_ap_return;
reg grp_image_filter_borderInterpolate_fu_684_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_692_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_692_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_692_borderType;
reg grp_image_filter_borderInterpolate_fu_692_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_700_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_700_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_700_borderType;
reg grp_image_filter_borderInterpolate_fu_700_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_708_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_708_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_708_borderType;
reg grp_image_filter_borderInterpolate_fu_708_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_716_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_716_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_716_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_716_ap_return;
reg grp_image_filter_borderInterpolate_fu_716_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_724_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_724_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_724_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_724_ap_return;
reg grp_image_filter_borderInterpolate_fu_724_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_732_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_732_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_732_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_732_ap_return;
reg grp_image_filter_borderInterpolate_fu_732_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_740_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_740_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_740_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_740_ap_return;
reg grp_image_filter_borderInterpolate_fu_740_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_748_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_748_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_748_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_748_ap_return;
reg grp_image_filter_borderInterpolate_fu_748_ap_ce;
wire [11:0] grp_image_filter_borderInterpolate_fu_756_p;
wire [11:0] grp_image_filter_borderInterpolate_fu_756_len;
wire [4:0] grp_image_filter_borderInterpolate_fu_756_borderType;
wire [14:0] grp_image_filter_borderInterpolate_fu_756_ap_return;
reg grp_image_filter_borderInterpolate_fu_756_ap_ce;
reg [1:0] tmp_39_reg_612;
wire [0:0] tmp_41_fu_902_p2;
reg [1:0] tmp_s_reg_623;
wire [0:0] tmp_43_fu_914_p2;
reg [1:0] tmp_44_reg_634;
reg [10:0] p_012_0_i_i_reg_645;
reg ap_sig_cseq_ST_st20_fsm_7;
reg ap_sig_bdd_951;
wire [63:0] tmp_55_fu_1287_p1;
wire signed [63:0] tmp_163_1_fu_1294_p1;
wire signed [63:0] tmp_163_2_fu_1300_p1;
wire [63:0] tmp_205_1_fu_1516_p1;
wire [10:0] k_buf_1_val_1_addr_3_gep_fu_554_p3;
wire [63:0] tmp_205_2_fu_1702_p1;
wire [10:0] k_buf_2_val_1_addr_3_gep_fu_594_p3;
reg [7:0] right_border_buf_0_val_0_0_fu_178;
reg [7:0] right_border_buf_0_val_0_1_fu_182;
reg [7:0] right_border_buf_0_val_0_2_fu_186;
reg [7:0] right_border_buf_1_val_0_0_fu_190;
reg [7:0] right_border_buf_1_val_0_1_fu_194;
reg [7:0] right_border_buf_1_val_0_2_fu_198;
reg [7:0] right_border_buf_2_val_0_0_fu_202;
reg [7:0] right_border_buf_2_val_0_1_fu_206;
reg [7:0] right_border_buf_2_val_0_2_fu_210;
reg [7:0] col_buf_0_val_0_0_fu_214;
reg [7:0] col_buf_1_val_0_0_fu_218;
reg [7:0] col_buf_2_val_0_0_fu_222;
reg [7:0] src_kernel_win_0_val_0_1_fu_226;
wire [7:0] src_kernel_win_0_val_0_1_15_fu_1838_p3;
wire [7:0] col_buf_0_val_0_0_25_fu_1926_p3;
reg [7:0] src_kernel_win_0_val_0_2_fu_230;
reg [7:0] col_buf_2_val_0_0_18_fu_234;
reg [7:0] src_kernel_win_0_val_2_1_fu_238;
reg [7:0] src_kernel_win_0_val_1_1_fu_242;
wire [7:0] src_kernel_win_0_val_1_1_15_fu_1870_p3;
wire [7:0] right_border_buf_0_val_1_2_27_fu_1943_p3;
reg [7:0] src_kernel_win_0_val_1_2_fu_246;
reg [7:0] col_buf_2_val_0_0_19_fu_250;
reg [7:0] src_kernel_win_0_val_2_2_fu_254;
reg [7:0] col_buf_2_val_0_0_20_fu_258;
reg [7:0] src_kernel_win_1_val_0_1_fu_262;
wire [7:0] src_kernel_win_1_val_0_1_15_fu_2017_p3;
wire [7:0] src_kernel_win_1_val_0_1_16_fu_2084_p3;
reg [7:0] src_kernel_win_1_val_0_2_fu_266;
reg [7:0] right_border_buf_2_val_1_2_28_fu_270;
wire [7:0] right_border_buf_2_val_1_2_37_fu_1763_p3;
reg [7:0] src_kernel_win_1_val_2_1_fu_274;
reg [7:0] src_kernel_win_1_val_1_1_fu_278;
wire [7:0] src_kernel_win_1_val_1_1_15_fu_2049_p3;
wire [7:0] src_kernel_win_1_val_1_1_16_fu_2105_p3;
reg [7:0] src_kernel_win_1_val_1_2_fu_282;
reg [7:0] right_border_buf_2_val_1_2_29_fu_286;
wire [7:0] right_border_buf_2_val_1_2_35_fu_1746_p3;
reg [7:0] src_kernel_win_1_val_2_2_fu_290;
reg [7:0] right_border_buf_2_val_1_2_30_fu_294;
wire [7:0] right_border_buf_2_val_1_2_33_fu_1724_p3;
reg [7:0] src_kernel_win_2_val_0_1_fu_298;
wire [7:0] src_kernel_win_2_val_0_1_15_fu_2183_p3;
wire [7:0] src_kernel_win_2_val_0_1_16_fu_2250_p3;
reg [7:0] src_kernel_win_2_val_0_2_fu_302;
reg [7:0] col_buf_1_val_0_0_18_fu_306;
reg [7:0] src_kernel_win_2_val_2_1_fu_310;
reg [7:0] src_kernel_win_2_val_1_1_fu_314;
wire [7:0] src_kernel_win_2_val_1_1_15_fu_2215_p3;
wire [7:0] src_kernel_win_2_val_1_1_16_fu_2271_p3;
reg [7:0] src_kernel_win_2_val_1_2_fu_318;
reg [7:0] col_buf_1_val_0_0_19_fu_322;
reg [7:0] src_kernel_win_2_val_2_2_fu_326;
reg [7:0] col_buf_1_val_0_0_20_fu_330;
reg [7:0] right_border_buf_0_val_1_2_21_fu_334;
wire [7:0] right_border_buf_0_val_1_2_26_fu_1391_p3;
reg [7:0] right_border_buf_0_val_1_2_22_fu_338;
wire [7:0] right_border_buf_0_val_1_2_10_fu_1382_p3;
reg [7:0] right_border_buf_0_val_1_2_23_fu_342;
wire [7:0] right_border_buf_0_val_1_2_8_fu_1365_p3;
reg [7:0] col_buf_0_val_0_0_18_fu_346;
reg [7:0] col_buf_0_val_0_0_19_fu_350;
reg [7:0] col_buf_0_val_0_0_20_fu_354;
reg [7:0] right_border_buf_1_val_1_2_20_fu_358;
wire [7:0] right_border_buf_1_val_1_2_27_fu_1577_p3;
reg [7:0] right_border_buf_1_val_1_2_21_fu_362;
wire [7:0] right_border_buf_1_val_1_2_26_fu_1568_p3;
reg [7:0] right_border_buf_1_val_1_2_22_fu_366;
wire [7:0] right_border_buf_1_val_1_2_10_fu_1551_p3;
wire [10:0] tmp_47_fu_942_p2;
wire [10:0] tmp_111_fu_1000_p4;
wire [0:0] icmp_fu_1010_p2;
wire [0:0] tmp_165_2_fu_1016_p2;
wire [10:0] p_i_i_fu_1042_p3;
wire [0:0] tmp_51_fu_1057_p2;
wire [9:0] tmp_116_fu_1092_p4;
wire [0:0] icmp3_fu_1102_p2;
wire [11:0] tmp_56_cast_fu_1077_p1;
wire signed [12:0] ImagLoc_x_cast3_fu_1123_p1;
wire [0:0] tmp_56_fu_1127_p2;
wire [1:0] tmp_117_fu_1119_p1;
wire [0:0] tmp_168_1_fu_1162_p2;
wire [11:0] col_assign_1_fu_1192_p2;
wire [0:0] tmp_168_2_fu_1201_p2;
wire [11:0] col_assign_2_fu_1231_p2;
wire [11:0] col_assign_9_1_fu_1240_p2;
wire [11:0] col_assign_9_2_fu_1248_p2;
wire signed [31:0] x_ext_fu_1284_p1;
wire [0:0] sel_tmp24_fu_1347_p2;
wire [0:0] sel_tmp26_fu_1360_p2;
wire [7:0] right_border_buf_0_val_1_2_7_fu_1352_p3;
wire [7:0] right_border_buf_0_val_1_2_9_fu_1374_p3;
wire [1:0] tmp_130_fu_1447_p1;
wire [0:0] sel_tmp48_fu_1455_p2;
wire [0:0] sel_tmp50_fu_1469_p2;
wire [7:0] col_buf_1_val_0_0_21_fu_1461_p3;
wire [0:0] sel_tmp58_fu_1483_p2;
wire signed [31:0] x_1_ext_fu_1415_p1;
wire [0:0] sel_tmp36_fu_1533_p2;
wire [0:0] sel_tmp38_fu_1546_p2;
wire [7:0] right_border_buf_1_val_1_2_9_fu_1538_p3;
wire [7:0] right_border_buf_1_val_1_2_25_fu_1560_p3;
wire [1:0] tmp_139_fu_1633_p1;
wire [0:0] sel_tmp67_fu_1641_p2;
wire [0:0] sel_tmp68_fu_1655_p2;
wire [7:0] col_buf_2_val_0_0_21_fu_1647_p3;
wire [0:0] sel_tmp70_fu_1669_p2;
wire signed [31:0] x_2_ext_fu_1601_p1;
wire [0:0] sel_tmp73_fu_1719_p2;
wire [0:0] sel_tmp74_fu_1733_p2;
wire [7:0] right_border_buf_2_val_1_2_34_fu_1738_p3;
wire [7:0] right_border_buf_2_val_1_2_36_fu_1755_p3;
wire [0:0] sel_tmp8_fu_1821_p2;
wire [1:0] locy_fu_1814_p2;
wire [0:0] sel_tmp10_fu_1832_p2;
wire [7:0] sel_tmp9_fu_1825_p3;
wire [0:0] sel_tmp12_fu_1853_p2;
wire [1:0] locy_0_1_t_fu_1846_p2;
wire [0:0] sel_tmp14_fu_1864_p2;
wire [7:0] sel_tmp13_fu_1857_p3;
wire [0:0] sel_tmp_fu_1908_p2;
wire [0:0] sel_tmp2_fu_1921_p2;
wire [7:0] col_buf_0_val_0_0_21_fu_1913_p3;
wire [7:0] right_border_buf_0_val_1_2_fu_1935_p3;
wire [0:0] tmp_220_0_0_1_fu_1979_p2;
wire [0:0] sel_tmp16_fu_2000_p2;
wire [1:0] locy_1_0_t_fu_1993_p2;
wire [0:0] sel_tmp18_fu_2011_p2;
wire [7:0] sel_tmp17_fu_2004_p3;
wire [0:0] sel_tmp20_fu_2032_p2;
wire [1:0] locy_1_1_t_fu_2025_p2;
wire [0:0] sel_tmp22_fu_2043_p2;
wire [7:0] sel_tmp21_fu_2036_p3;
wire [7:0] sel_tmp56_fu_2078_p3;
wire [7:0] right_border_buf_1_val_1_2_fu_2091_p3;
wire [7:0] right_border_buf_1_val_1_2_7_fu_2098_p3;
wire [0:0] tmp_220_1_0_1_fu_2145_p2;
wire [0:0] sel_tmp61_fu_2166_p2;
wire [1:0] locy_2_0_t_fu_2159_p2;
wire [0:0] sel_tmp63_fu_2177_p2;
wire [7:0] sel_tmp62_fu_2170_p3;
wire [0:0] sel_tmp64_fu_2198_p2;
wire [1:0] locy_2_1_t_fu_2191_p2;
wire [0:0] sel_tmp66_fu_2209_p2;
wire [7:0] sel_tmp65_fu_2202_p3;
wire [7:0] sel_tmp69_fu_2244_p3;
wire [7:0] right_border_buf_2_val_1_2_fu_2257_p3;
wire [7:0] right_border_buf_2_val_1_2_3_fu_2264_p3;
wire [0:0] tmp_220_2_0_1_fu_2311_p2;
wire [0:0] tmp_220_0_0_2_fu_2352_p2;
wire [0:0] tmp_220_1_0_2_fu_2382_p2;
wire [0:0] tmp_220_2_0_2_fu_2412_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3;
wire [0:0] tmp_220_0_1_1_fu_2447_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3;
wire [0:0] tmp_220_1_1_1_fu_2464_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3;
wire [0:0] tmp_220_2_1_1_fu_2481_p2;
wire [0:0] tmp_220_0_1_2_fu_2496_p2;
wire [0:0] tmp_220_1_1_2_fu_2515_p2;
wire [0:0] tmp_220_2_1_2_fu_2534_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3;
wire [0:0] tmp_220_0_2_1_fu_2567_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3;
wire [0:0] tmp_220_1_2_1_fu_2584_p2;
wire [7:0] temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3;
wire [0:0] tmp_220_2_2_1_fu_2601_p2;
wire [0:0] tmp_220_0_2_2_fu_2613_p2;
wire [0:0] tmp_220_1_2_2_fu_2624_p2;
wire [0:0] tmp_220_2_2_2_fu_2635_p2;
reg [7:0] ap_NS_fsm;
reg ap_sig_bdd_967;
reg ap_sig_bdd_979;
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_0_val_0_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_0_val_0_address0 ),
.ce0( k_buf_0_val_0_ce0 ),
.q0( k_buf_0_val_0_q0 ),
.address1( k_buf_0_val_0_address1 ),
.ce1( k_buf_0_val_0_ce1 ),
.we1( k_buf_0_val_0_we1 ),
.d1( k_buf_0_val_0_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_0_val_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_0_val_1_address0 ),
.ce0( k_buf_0_val_1_ce0 ),
.q0( k_buf_0_val_1_q0 ),
.address1( k_buf_0_val_1_address1 ),
.ce1( k_buf_0_val_1_ce1 ),
.we1( k_buf_0_val_1_we1 ),
.d1( k_buf_0_val_1_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_0_val_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_0_val_2_address0 ),
.ce0( k_buf_0_val_2_ce0 ),
.q0( k_buf_0_val_2_q0 ),
.address1( k_buf_0_val_2_address1 ),
.ce1( k_buf_0_val_2_ce1 ),
.we1( k_buf_0_val_2_we1 ),
.d1( k_buf_0_val_2_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_1_val_0_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_1_val_0_address0 ),
.ce0( k_buf_1_val_0_ce0 ),
.q0( k_buf_1_val_0_q0 ),
.address1( k_buf_1_val_0_address1 ),
.ce1( k_buf_1_val_0_ce1 ),
.we1( k_buf_1_val_0_we1 ),
.d1( k_buf_1_val_0_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_1_val_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_1_val_1_address0 ),
.ce0( k_buf_1_val_1_ce0 ),
.q0( k_buf_1_val_1_q0 ),
.address1( k_buf_1_val_1_address1 ),
.ce1( k_buf_1_val_1_ce1 ),
.we1( k_buf_1_val_1_we1 ),
.d1( k_buf_1_val_1_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_1_val_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_1_val_2_address0 ),
.ce0( k_buf_1_val_2_ce0 ),
.q0( k_buf_1_val_2_q0 ),
.address1( k_buf_1_val_2_address1 ),
.ce1( k_buf_1_val_2_ce1 ),
.we1( k_buf_1_val_2_we1 ),
.d1( k_buf_1_val_2_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_2_val_0_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_2_val_0_address0 ),
.ce0( k_buf_2_val_0_ce0 ),
.q0( k_buf_2_val_0_q0 ),
.address1( k_buf_2_val_0_address1 ),
.ce1( k_buf_2_val_0_ce1 ),
.we1( k_buf_2_val_0_we1 ),
.d1( k_buf_2_val_0_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_2_val_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_2_val_1_address0 ),
.ce0( k_buf_2_val_1_ce0 ),
.q0( k_buf_2_val_1_q0 ),
.address1( k_buf_2_val_1_address1 ),
.ce1( k_buf_2_val_1_ce1 ),
.we1( k_buf_2_val_1_we1 ),
.d1( k_buf_2_val_1_d1 )
);
image_filter_Filter2D_k_buf_0_val_0 #(
.DataWidth( 8 ),
.AddressRange( 1920 ),
.AddressWidth( 11 ))
k_buf_2_val_2_U(
.clk( ap_clk ),
.reset( ap_rst ),
.address0( k_buf_2_val_2_address0 ),
.ce0( k_buf_2_val_2_ce0 ),
.q0( k_buf_2_val_2_q0 ),
.address1( k_buf_2_val_2_address1 ),
.ce1( k_buf_2_val_2_ce1 ),
.we1( k_buf_2_val_2_we1 ),
.d1( k_buf_2_val_2_d1 )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_668(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_668_p ),
.len( grp_image_filter_borderInterpolate_fu_668_len ),
.borderType( grp_image_filter_borderInterpolate_fu_668_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_668_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_668_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_676(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_676_p ),
.len( grp_image_filter_borderInterpolate_fu_676_len ),
.borderType( grp_image_filter_borderInterpolate_fu_676_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_676_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_676_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_684(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_684_p ),
.len( grp_image_filter_borderInterpolate_fu_684_len ),
.borderType( grp_image_filter_borderInterpolate_fu_684_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_684_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_684_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_692(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_692_p ),
.len( grp_image_filter_borderInterpolate_fu_692_len ),
.borderType( grp_image_filter_borderInterpolate_fu_692_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_692_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_692_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_700(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_700_p ),
.len( grp_image_filter_borderInterpolate_fu_700_len ),
.borderType( grp_image_filter_borderInterpolate_fu_700_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_700_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_700_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_708(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_708_p ),
.len( grp_image_filter_borderInterpolate_fu_708_len ),
.borderType( grp_image_filter_borderInterpolate_fu_708_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_708_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_708_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_716(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_716_p ),
.len( grp_image_filter_borderInterpolate_fu_716_len ),
.borderType( grp_image_filter_borderInterpolate_fu_716_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_716_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_716_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_724(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_724_p ),
.len( grp_image_filter_borderInterpolate_fu_724_len ),
.borderType( grp_image_filter_borderInterpolate_fu_724_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_724_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_724_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_732(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_732_p ),
.len( grp_image_filter_borderInterpolate_fu_732_len ),
.borderType( grp_image_filter_borderInterpolate_fu_732_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_732_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_732_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_740(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_740_p ),
.len( grp_image_filter_borderInterpolate_fu_740_len ),
.borderType( grp_image_filter_borderInterpolate_fu_740_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_740_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_740_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_748(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_748_p ),
.len( grp_image_filter_borderInterpolate_fu_748_len ),
.borderType( grp_image_filter_borderInterpolate_fu_748_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_748_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_748_ap_ce )
);
image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_756(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p( grp_image_filter_borderInterpolate_fu_756_p ),
.len( grp_image_filter_borderInterpolate_fu_756_len ),
.borderType( grp_image_filter_borderInterpolate_fu_756_borderType ),
.ap_return( grp_image_filter_borderInterpolate_fu_756_ap_return ),
.ap_ce( grp_image_filter_borderInterpolate_fu_756_ap_ce )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_48_fu_977_p2))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_53_fu_1081_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
if (~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_7)) begin
p_012_0_i_i_reg_645 <= i_V_reg_3108;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(tmp_46_fu_926_p2 == ap_const_lv1_0))) begin
p_012_0_i_i_reg_645 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2))) begin
p_025_0_i_i_reg_656 <= j_V_fu_1086_p2;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
p_025_0_i_i_reg_656 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
src_kernel_win_0_val_0_1_fu_226 <= right_border_buf_0_val_2_0_reg_3377;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & (col_assign_8_reg_3409 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & (col_assign_8_reg_3409 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & ~(col_assign_8_reg_3409 == ap_const_lv2_1) & ~(col_assign_8_reg_3409 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_0_1_fu_226 <= col_buf_0_val_0_0_25_fu_1926_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_0_1_fu_226 <= src_kernel_win_0_val_0_1_15_fu_1838_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
src_kernel_win_0_val_1_1_fu_242 <= right_border_buf_0_val_1_0_reg_3382;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & (col_assign_8_reg_3409 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & (col_assign_8_reg_3409 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & ~(col_assign_8_reg_3409 == ap_const_lv2_1) & ~(col_assign_8_reg_3409 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_1_1_fu_242 <= right_border_buf_0_val_1_2_27_fu_1943_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_0_val_1_1_fu_242 <= src_kernel_win_0_val_1_1_15_fu_1870_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & ~(col_assign_8_reg_3409 == ap_const_lv2_1) & ~(col_assign_8_reg_3409 == ap_const_lv2_0))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_2_fu_186;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & (col_assign_8_reg_3409 == ap_const_lv2_0))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_0_fu_178;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it6) & (col_assign_8_reg_3409 == ap_const_lv2_1))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_1_fu_182;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
src_kernel_win_0_val_2_1_fu_238 <= src_kernel_win_0_val_2_0_reg_3390;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0))) begin
src_kernel_win_0_val_2_1_fu_238 <= col_buf_0_val_0_0_fu_214;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1))) begin
src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_1_0_reg_3382;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
src_kernel_win_1_val_0_1_fu_262 <= right_border_buf_1_val_2_0_reg_3415;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & (col_assign_8_1_t1_reg_3453 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & (col_assign_8_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & ~(col_assign_8_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_8_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_129_reg_3447)))) begin
src_kernel_win_1_val_0_1_fu_262 <= src_kernel_win_1_val_0_1_16_fu_2084_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_1_val_0_1_fu_262 <= src_kernel_win_1_val_0_1_15_fu_2017_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
src_kernel_win_1_val_1_1_fu_278 <= right_border_buf_1_val_1_0_reg_3420;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & (col_assign_8_1_t1_reg_3453 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & (col_assign_8_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & ~(col_assign_8_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_8_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_129_reg_3447)))) begin
src_kernel_win_1_val_1_1_fu_278 <= src_kernel_win_1_val_1_1_16_fu_2105_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_1_val_1_1_fu_278 <= src_kernel_win_1_val_1_1_15_fu_2049_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_129_reg_3447))) begin
src_kernel_win_1_val_2_1_fu_274 <= ap_const_lv8_0;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & ~(col_assign_8_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_8_1_t1_reg_3453 == ap_const_lv2_0))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_2_fu_198;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & (col_assign_8_1_t1_reg_3453 == ap_const_lv2_0))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_0_fu_190;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_129_reg_3447) & (col_assign_8_1_t1_reg_3453 == ap_const_lv2_1))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_1_fu_194;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
src_kernel_win_1_val_2_1_fu_274 <= src_kernel_win_1_val_2_0_reg_3428;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0))) begin
src_kernel_win_1_val_2_1_fu_274 <= col_buf_1_val_0_0_fu_218;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1))) begin
src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_1_0_reg_3420;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
src_kernel_win_2_val_0_1_fu_298 <= right_border_buf_2_val_2_0_reg_3474;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & (col_assign_8_2_t1_reg_3512 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & (col_assign_8_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & ~(col_assign_8_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_8_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_138_reg_3506)))) begin
src_kernel_win_2_val_0_1_fu_298 <= src_kernel_win_2_val_0_1_16_fu_2250_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_2_val_0_1_fu_298 <= src_kernel_win_2_val_0_1_15_fu_2183_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
src_kernel_win_2_val_1_1_fu_314 <= right_border_buf_2_val_1_0_reg_3479;
end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & (col_assign_8_2_t1_reg_3512 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & (col_assign_8_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & ~(col_assign_8_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_8_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_138_reg_3506)))) begin
src_kernel_win_2_val_1_1_fu_314 <= src_kernel_win_2_val_1_1_16_fu_2271_p3;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)))) begin
src_kernel_win_2_val_1_1_fu_314 <= src_kernel_win_2_val_1_1_15_fu_2215_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_138_reg_3506))) begin
src_kernel_win_2_val_2_1_fu_310 <= ap_const_lv8_0;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & ~(col_assign_8_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_8_2_t1_reg_3512 == ap_const_lv2_0))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_2_fu_210;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & (col_assign_8_2_t1_reg_3512 == ap_const_lv2_0))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_0_fu_202;
end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_138_reg_3506) & (col_assign_8_2_t1_reg_3512 == ap_const_lv2_1))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_1_fu_206;
end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
src_kernel_win_2_val_2_1_fu_310 <= src_kernel_win_2_val_2_0_reg_3487;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0))) begin
src_kernel_win_2_val_2_1_fu_310 <= col_buf_2_val_0_0_fu_222;
end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1))) begin
src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_1_0_reg_3479;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_67)) begin
tmp_39_reg_612 <= ap_const_lv2_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == tmp_41_fu_902_p2))) begin
tmp_39_reg_612 <= tmp_40_fu_896_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_43_fu_914_p2))) begin
tmp_44_reg_634 <= ap_const_lv2_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (tmp_46_fu_926_p2 == ap_const_lv1_0))) begin
tmp_44_reg_634 <= tmp_45_fu_920_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == tmp_41_fu_902_p2))) begin
tmp_s_reg_623 <= ap_const_lv2_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_43_fu_914_p2))) begin
tmp_s_reg_623 <= tmp_42_fu_908_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2))) begin
ImagLoc_x_reg_3193 <= ImagLoc_x_fu_1113_p2;
or_cond219_i_i_reg_3189 <= or_cond219_i_i_fu_1108_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == tmp_48_fu_977_p2))) begin
ImagLoc_y_reg_3118 <= ImagLoc_y_fu_994_p2;
or_cond_2_reg_3126 <= or_cond_2_fu_1021_p2;
tmp_112_reg_3131 <= ImagLoc_y_fu_994_p2[ap_const_lv32_B];
tmp_113_reg_3149 <= tmp_113_fu_1049_p1;
tmp_115_reg_3155 <= tmp_115_fu_1053_p1;
tmp_50_reg_3113 <= tmp_50_fu_988_p2;
tmp_52_reg_3135 <= tmp_52_fu_1035_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
ap_reg_ppstg_col_assign_reg_3218_pp0_it1 <= col_assign_reg_3218;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1 <= or_cond219_i_i_reg_3189;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1 <= or_cond2_1_reg_3228;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1 <= or_cond2_2_reg_3248;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it1 <= or_cond2_reg_3206;
ap_reg_ppstg_tmp_119_reg_3210_pp0_it1 <= tmp_119_reg_3210;
ap_reg_ppstg_tmp_124_reg_3232_pp0_it1 <= tmp_124_reg_3232;
ap_reg_ppstg_tmp_128_reg_3240_pp0_it1 <= tmp_128_reg_3240;
ap_reg_ppstg_tmp_133_reg_3252_pp0_it1 <= tmp_133_reg_3252;
ap_reg_ppstg_tmp_137_reg_3260_pp0_it1 <= tmp_137_reg_3260;
ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it1 <= tmp_170_1_reg_3224;
ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it1 <= tmp_170_2_reg_3244;
ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it1 <= tmp_173_1_reg_3236;
ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it1 <= tmp_173_2_reg_3256;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 <= tmp_53_reg_3180;
ap_reg_ppstg_tmp_57_reg_3202_pp0_it1 <= tmp_57_reg_3202;
ap_reg_ppstg_tmp_58_reg_3214_pp0_it1 <= tmp_58_reg_3214;
tmp_53_reg_3180 <= tmp_53_fu_1081_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
ap_reg_ppstg_col_assign_reg_3218_pp0_it2 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it1;
ap_reg_ppstg_col_assign_reg_3218_pp0_it3 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it2;
ap_reg_ppstg_col_assign_reg_3218_pp0_it4 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it3;
ap_reg_ppstg_col_assign_reg_3218_pp0_it5 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it4;
ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5 <= locy_0_2_t_reg_3301;
ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 <= ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5;
ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5 <= locy_1_2_t_reg_3313;
ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 <= ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5;
ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5 <= locy_2_2_t_reg_3325;
ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 <= ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7;
ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4;
ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4;
ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it1;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it3 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it2;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it4 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it3;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it4;
ap_reg_ppstg_or_cond2_reg_3206_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it5;
ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it10 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it9;
ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it8 <= src_kernel_win_0_val_0_1_18_reg_3533;
ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it9 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it8;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9 <= src_kernel_win_0_val_0_1_lo_reg_3593;
ap_reg_ppstg_src_kernel_win_0_val_1_1_18_reg_3540_pp0_it8 <= src_kernel_win_0_val_1_1_18_reg_3540;
ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9 <= src_kernel_win_0_val_1_1_lo_reg_3599;
ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it10 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it9;
ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it8 <= src_kernel_win_1_val_0_1_18_reg_3547;
ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it9 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it8;
ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9;
ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10;
ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9 <= src_kernel_win_1_val_0_1_lo_reg_3620;
ap_reg_ppstg_src_kernel_win_1_val_1_1_18_reg_3554_pp0_it8 <= src_kernel_win_1_val_1_1_18_reg_3554;
ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9 <= src_kernel_win_1_val_1_1_lo_reg_3626;
ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it10 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it9;
ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it8 <= src_kernel_win_2_val_0_1_18_reg_3561;
ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it9 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it8;
ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9;
ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10;
ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9 <= src_kernel_win_2_val_0_1_lo_reg_3647;
ap_reg_ppstg_src_kernel_win_2_val_1_1_18_reg_3568_pp0_it8 <= src_kernel_win_2_val_1_1_18_reg_3568;
ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9 <= src_kernel_win_2_val_1_1_lo_reg_3653;
ap_reg_ppstg_tmp_118_reg_3296_pp0_it5 <= tmp_118_reg_3296;
ap_reg_ppstg_tmp_119_reg_3210_pp0_it2 <= ap_reg_ppstg_tmp_119_reg_3210_pp0_it1;
ap_reg_ppstg_tmp_119_reg_3210_pp0_it3 <= ap_reg_ppstg_tmp_119_reg_3210_pp0_it2;
ap_reg_ppstg_tmp_119_reg_3210_pp0_it4 <= ap_reg_ppstg_tmp_119_reg_3210_pp0_it3;
ap_reg_ppstg_tmp_119_reg_3210_pp0_it5 <= ap_reg_ppstg_tmp_119_reg_3210_pp0_it4;
ap_reg_ppstg_tmp_119_reg_3210_pp0_it6 <= ap_reg_ppstg_tmp_119_reg_3210_pp0_it5;
ap_reg_ppstg_tmp_124_reg_3232_pp0_it2 <= ap_reg_ppstg_tmp_124_reg_3232_pp0_it1;
ap_reg_ppstg_tmp_124_reg_3232_pp0_it3 <= ap_reg_ppstg_tmp_124_reg_3232_pp0_it2;
ap_reg_ppstg_tmp_124_reg_3232_pp0_it4 <= ap_reg_ppstg_tmp_124_reg_3232_pp0_it3;
ap_reg_ppstg_tmp_124_reg_3232_pp0_it5 <= ap_reg_ppstg_tmp_124_reg_3232_pp0_it4;
ap_reg_ppstg_tmp_124_reg_3232_pp0_it6 <= ap_reg_ppstg_tmp_124_reg_3232_pp0_it5;
ap_reg_ppstg_tmp_128_reg_3240_pp0_it2 <= ap_reg_ppstg_tmp_128_reg_3240_pp0_it1;
ap_reg_ppstg_tmp_128_reg_3240_pp0_it3 <= ap_reg_ppstg_tmp_128_reg_3240_pp0_it2;
ap_reg_ppstg_tmp_128_reg_3240_pp0_it4 <= ap_reg_ppstg_tmp_128_reg_3240_pp0_it3;
ap_reg_ppstg_tmp_128_reg_3240_pp0_it5 <= ap_reg_ppstg_tmp_128_reg_3240_pp0_it4;
ap_reg_ppstg_tmp_131_reg_3264_pp0_it2 <= tmp_131_reg_3264;
ap_reg_ppstg_tmp_131_reg_3264_pp0_it3 <= ap_reg_ppstg_tmp_131_reg_3264_pp0_it2;
ap_reg_ppstg_tmp_131_reg_3264_pp0_it4 <= ap_reg_ppstg_tmp_131_reg_3264_pp0_it3;
ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 <= ap_reg_ppstg_tmp_131_reg_3264_pp0_it4;
ap_reg_ppstg_tmp_133_reg_3252_pp0_it2 <= ap_reg_ppstg_tmp_133_reg_3252_pp0_it1;
ap_reg_ppstg_tmp_133_reg_3252_pp0_it3 <= ap_reg_ppstg_tmp_133_reg_3252_pp0_it2;
ap_reg_ppstg_tmp_133_reg_3252_pp0_it4 <= ap_reg_ppstg_tmp_133_reg_3252_pp0_it3;
ap_reg_ppstg_tmp_133_reg_3252_pp0_it5 <= ap_reg_ppstg_tmp_133_reg_3252_pp0_it4;
ap_reg_ppstg_tmp_133_reg_3252_pp0_it6 <= ap_reg_ppstg_tmp_133_reg_3252_pp0_it5;
ap_reg_ppstg_tmp_137_reg_3260_pp0_it2 <= ap_reg_ppstg_tmp_137_reg_3260_pp0_it1;
ap_reg_ppstg_tmp_137_reg_3260_pp0_it3 <= ap_reg_ppstg_tmp_137_reg_3260_pp0_it2;
ap_reg_ppstg_tmp_137_reg_3260_pp0_it4 <= ap_reg_ppstg_tmp_137_reg_3260_pp0_it3;
ap_reg_ppstg_tmp_137_reg_3260_pp0_it5 <= ap_reg_ppstg_tmp_137_reg_3260_pp0_it4;
ap_reg_ppstg_tmp_140_reg_3270_pp0_it2 <= tmp_140_reg_3270;
ap_reg_ppstg_tmp_140_reg_3270_pp0_it3 <= ap_reg_ppstg_tmp_140_reg_3270_pp0_it2;
ap_reg_ppstg_tmp_140_reg_3270_pp0_it4 <= ap_reg_ppstg_tmp_140_reg_3270_pp0_it3;
ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 <= ap_reg_ppstg_tmp_140_reg_3270_pp0_it4;
ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it2 <= ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it1;
ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it3 <= ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it2;
ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it4 <= ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it3;
ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it5 <= ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it4;
ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it6 <= ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it5;
ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it2 <= ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it1;
ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it3 <= ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it2;
ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it4 <= ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it3;
ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it5 <= ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it4;
ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it6 <= ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it5;
ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it2 <= ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it1;
ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it3 <= ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it2;
ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it4 <= ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it3;
ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5 <= ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it4;
ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it2 <= ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it1;
ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it3 <= ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it2;
ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it4 <= ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it3;
ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5 <= ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it4;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it1;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it2;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it4 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it3;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it4;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it6 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it5;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it7 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it6;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it8 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it7;
ap_reg_ppstg_tmp_53_reg_3180_pp0_it9 <= ap_reg_ppstg_tmp_53_reg_3180_pp0_it8;
ap_reg_ppstg_tmp_57_reg_3202_pp0_it2 <= ap_reg_ppstg_tmp_57_reg_3202_pp0_it1;
ap_reg_ppstg_tmp_57_reg_3202_pp0_it3 <= ap_reg_ppstg_tmp_57_reg_3202_pp0_it2;
ap_reg_ppstg_tmp_57_reg_3202_pp0_it4 <= ap_reg_ppstg_tmp_57_reg_3202_pp0_it3;
ap_reg_ppstg_tmp_57_reg_3202_pp0_it5 <= ap_reg_ppstg_tmp_57_reg_3202_pp0_it4;
ap_reg_ppstg_tmp_57_reg_3202_pp0_it6 <= ap_reg_ppstg_tmp_57_reg_3202_pp0_it5;
ap_reg_ppstg_tmp_58_reg_3214_pp0_it2 <= ap_reg_ppstg_tmp_58_reg_3214_pp0_it1;
ap_reg_ppstg_tmp_58_reg_3214_pp0_it3 <= ap_reg_ppstg_tmp_58_reg_3214_pp0_it2;
ap_reg_ppstg_tmp_58_reg_3214_pp0_it4 <= ap_reg_ppstg_tmp_58_reg_3214_pp0_it3;
ap_reg_ppstg_tmp_58_reg_3214_pp0_it5 <= ap_reg_ppstg_tmp_58_reg_3214_pp0_it4;
ap_reg_ppstg_x_1_reg_3305_pp0_it5 <= x_1_reg_3305;
ap_reg_ppstg_x_2_reg_3317_pp0_it5 <= x_2_reg_3317;
src_kernel_win_0_val_0_1_18_reg_3533 <= src_kernel_win_0_val_0_1_fu_226;
src_kernel_win_0_val_1_1_18_reg_3540 <= src_kernel_win_0_val_1_1_fu_242;
src_kernel_win_1_val_0_1_18_reg_3547 <= src_kernel_win_1_val_0_1_fu_262;
src_kernel_win_1_val_1_1_18_reg_3554 <= src_kernel_win_1_val_1_1_fu_278;
src_kernel_win_2_val_0_1_18_reg_3561 <= src_kernel_win_2_val_0_1_fu_298;
src_kernel_win_2_val_1_1_18_reg_3568 <= src_kernel_win_2_val_1_1_fu_314;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
brmerge_reg_3176 <= brmerge_fu_1072_p2;
y_2_2_1_reg_3169 <= y_2_2_1_fu_1067_p2;
y_2_2_reg_3162 <= y_2_2_fu_1062_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_124_reg_3232_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_1_reg_3224_pp0_it5))) begin
col_assign_8_1_t1_reg_3453 <= col_assign_8_1_t1_fu_1450_p2;
col_buf_1_val_0_0_25_reg_3457 <= col_buf_1_val_0_0_25_fu_1475_p3;
sel_tmp59_reg_3463 <= sel_tmp59_fu_1489_p2;
sel_tmp60_reg_3469 <= sel_tmp60_fu_1495_p2;
tmp_129_reg_3447 <= ap_reg_ppstg_x_1_reg_3305_pp0_it5[ap_const_lv32_E];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_133_reg_3252_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_170_2_reg_3244_pp0_it5))) begin
col_assign_8_2_t1_reg_3512 <= col_assign_8_2_t1_fu_1636_p2;
col_buf_2_val_0_0_25_reg_3516 <= col_buf_2_val_0_0_25_fu_1661_p3;
sel_tmp71_reg_3522 <= sel_tmp71_fu_1675_p2;
sel_tmp72_reg_3528 <= sel_tmp72_fu_1681_p2;
tmp_138_reg_3506 <= ap_reg_ppstg_x_2_reg_3317_pp0_it5[ap_const_lv32_E];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_119_reg_3210_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_57_reg_3202_pp0_it5))) begin
col_assign_8_reg_3409 <= col_assign_8_fu_1319_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_fu_1138_p2) & (ap_const_lv1_0 == tmp_58_fu_1152_p2))) begin
col_assign_reg_3218 <= col_assign_fu_1157_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0))) begin
col_buf_0_val_0_0_18_fu_346 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_0_fu_178 <= k_buf_0_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1))) begin
col_buf_0_val_0_0_19_fu_350 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_1_fu_182 <= k_buf_0_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0))) begin
col_buf_0_val_0_0_20_fu_354 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_2_fu_186 <= k_buf_0_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
col_buf_0_val_0_0_fu_214 <= k_buf_0_val_0_q0;
col_buf_1_val_0_0_fu_218 <= k_buf_1_val_0_q0;
col_buf_2_val_0_0_fu_222 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_0))) begin
col_buf_1_val_0_0_18_fu_306 <= k_buf_1_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_1))) begin
col_buf_1_val_0_0_19_fu_322 <= k_buf_1_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_0))) begin
col_buf_1_val_0_0_20_fu_330 <= k_buf_1_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_0))) begin
col_buf_2_val_0_0_18_fu_234 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_1))) begin
col_buf_2_val_0_0_19_fu_250 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_0))) begin
col_buf_2_val_0_0_20_fu_258 <= k_buf_2_val_0_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_67)) begin
cols_assign_cast2_reg_2757[0] <= cols_assign_cast2_fu_892_p1[0];
cols_assign_cast2_reg_2757[1] <= cols_assign_cast2_fu_892_p1[1];
cols_assign_cast2_reg_2757[2] <= cols_assign_cast2_fu_892_p1[2];
cols_assign_cast2_reg_2757[3] <= cols_assign_cast2_fu_892_p1[3];
cols_assign_cast2_reg_2757[4] <= cols_assign_cast2_fu_892_p1[4];
cols_assign_cast2_reg_2757[5] <= cols_assign_cast2_fu_892_p1[5];
cols_assign_cast2_reg_2757[6] <= cols_assign_cast2_fu_892_p1[6];
cols_assign_cast2_reg_2757[7] <= cols_assign_cast2_fu_892_p1[7];
cols_assign_cast2_reg_2757[8] <= cols_assign_cast2_fu_892_p1[8];
cols_assign_cast2_reg_2757[9] <= cols_assign_cast2_fu_892_p1[9];
cols_assign_cast2_reg_2757[10] <= cols_assign_cast2_fu_892_p1[10];
cols_assign_cast2_reg_2757[11] <= cols_assign_cast2_fu_892_p1[11];
tmp_107_reg_2751 <= tmp_107_fu_888_p1;
tmp_reg_2745 <= tmp_fu_884_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(tmp_46_fu_926_p2 == ap_const_lv1_0))) begin
heightloop_reg_3051 <= heightloop_fu_932_p2;
p_neg226_i_i_reg_3068 <= p_neg226_i_i_fu_951_p2;
ref_cast_reg_3089[0] <= ref_cast_fu_965_p1[0];
ref_cast_reg_3089[1] <= ref_cast_fu_965_p1[1];
ref_cast_reg_3089[2] <= ref_cast_fu_965_p1[2];
ref_cast_reg_3089[3] <= ref_cast_fu_965_p1[3];
ref_cast_reg_3089[4] <= ref_cast_fu_965_p1[4];
ref_cast_reg_3089[5] <= ref_cast_fu_965_p1[5];
ref_cast_reg_3089[6] <= ref_cast_fu_965_p1[6];
ref_cast_reg_3089[7] <= ref_cast_fu_965_p1[7];
ref_cast_reg_3089[8] <= ref_cast_fu_965_p1[8];
ref_cast_reg_3089[9] <= ref_cast_fu_965_p1[9];
ref_cast_reg_3089[10] <= ref_cast_fu_965_p1[10];
ref_reg_3084 <= ref_fu_960_p2;
tmp_108_reg_3076 <= tmp_108_fu_956_p1;
tmp_110_reg_3094 <= tmp_110_fu_969_p1;
tmp_52_cast_reg_3061[0] <= tmp_52_cast_fu_947_p1[0];
tmp_52_cast_reg_3061[1] <= tmp_52_cast_fu_947_p1[1];
tmp_52_cast_reg_3061[2] <= tmp_52_cast_fu_947_p1[2];
tmp_52_cast_reg_3061[3] <= tmp_52_cast_fu_947_p1[3];
tmp_52_cast_reg_3061[4] <= tmp_52_cast_fu_947_p1[4];
tmp_52_cast_reg_3061[5] <= tmp_52_cast_fu_947_p1[5];
tmp_52_cast_reg_3061[6] <= tmp_52_cast_fu_947_p1[6];
tmp_52_cast_reg_3061[7] <= tmp_52_cast_fu_947_p1[7];
tmp_52_cast_reg_3061[8] <= tmp_52_cast_fu_947_p1[8];
tmp_52_cast_reg_3061[9] <= tmp_52_cast_fu_947_p1[9];
tmp_52_cast_reg_3061[10] <= tmp_52_cast_fu_947_p1[10];
widthloop_reg_3056 <= widthloop_fu_937_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
i_V_reg_3108 <= i_V_fu_982_p2;
tmp_53_cast_cast3_reg_3099[0] <= tmp_53_cast_cast3_fu_973_p1[0];
tmp_53_cast_cast3_reg_3099[1] <= tmp_53_cast_cast3_fu_973_p1[1];
tmp_53_cast_cast3_reg_3099[2] <= tmp_53_cast_cast3_fu_973_p1[2];
tmp_53_cast_cast3_reg_3099[3] <= tmp_53_cast_cast3_fu_973_p1[3];
tmp_53_cast_cast3_reg_3099[4] <= tmp_53_cast_cast3_fu_973_p1[4];
tmp_53_cast_cast3_reg_3099[5] <= tmp_53_cast_cast3_fu_973_p1[5];
tmp_53_cast_cast3_reg_3099[6] <= tmp_53_cast_cast3_fu_973_p1[6];
tmp_53_cast_cast3_reg_3099[7] <= tmp_53_cast_cast3_fu_973_p1[7];
tmp_53_cast_cast3_reg_3099[8] <= tmp_53_cast_cast3_fu_973_p1[8];
tmp_53_cast_cast3_reg_3099[9] <= tmp_53_cast_cast3_fu_973_p1[9];
tmp_53_cast_cast3_reg_3099[10] <= tmp_53_cast_cast3_fu_973_p1[10];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))) begin
k_buf_0_val_0_addr_reg_3329 <= tmp_55_fu_1287_p1;
k_buf_0_val_1_addr_reg_3335 <= tmp_55_fu_1287_p1;
k_buf_0_val_2_addr_reg_3341 <= tmp_55_fu_1287_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3))) begin
locy_0_2_t_reg_3301 <= locy_0_2_t_fu_1272_p2;
locy_1_2_t_reg_3313 <= locy_1_2_t_fu_1276_p2;
locy_2_2_t_reg_3325 <= locy_2_2_t_fu_1280_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2))) begin
or_cond2_1_reg_3228 <= or_cond2_1_fu_1173_p2;
or_cond2_2_reg_3248 <= or_cond2_2_fu_1212_p2;
or_cond2_reg_3206 <= or_cond2_fu_1138_p2;
tmp_170_1_reg_3224 <= tmp_170_1_fu_1168_p2;
tmp_170_2_reg_3244 <= tmp_170_2_fu_1207_p2;
tmp_57_reg_3202 <= tmp_57_fu_1133_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
right_border_buf_0_val_1_0_reg_3382 <= k_buf_0_val_1_q0;
right_border_buf_0_val_2_0_reg_3377 <= k_buf_0_val_0_q0;
right_border_buf_1_val_1_0_reg_3420 <= k_buf_1_val_1_q0;
right_border_buf_1_val_2_0_reg_3415 <= k_buf_1_val_0_q0;
right_border_buf_2_val_1_0_reg_3479 <= k_buf_2_val_1_q0;
right_border_buf_2_val_2_0_reg_3474 <= k_buf_2_val_0_q0;
src_kernel_win_0_val_2_0_reg_3390 <= k_buf_0_val_2_q0;
src_kernel_win_1_val_2_0_reg_3428 <= k_buf_1_val_2_q0;
src_kernel_win_2_val_2_0_reg_3487 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0)))) begin
right_border_buf_0_val_1_2_21_fu_334 <= right_border_buf_0_val_1_2_26_fu_1391_p3;
right_border_buf_0_val_1_2_22_fu_338 <= right_border_buf_0_val_1_2_10_fu_1382_p3;
right_border_buf_0_val_1_2_23_fu_342 <= right_border_buf_0_val_1_2_8_fu_1365_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_128_reg_3240_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_1_val_0_0_fu_190 <= k_buf_1_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_128_reg_3240_pp0_it5 == ap_const_lv2_1))) begin
right_border_buf_1_val_0_1_fu_194 <= k_buf_1_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_128_reg_3240_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_128_reg_3240_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_1_val_0_2_fu_198 <= k_buf_1_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_0)))) begin
right_border_buf_1_val_1_2_20_fu_358 <= right_border_buf_1_val_1_2_27_fu_1577_p3;
right_border_buf_1_val_1_2_21_fu_362 <= right_border_buf_1_val_1_2_26_fu_1568_p3;
right_border_buf_1_val_1_2_22_fu_366 <= right_border_buf_1_val_1_2_10_fu_1551_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_137_reg_3260_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_2_val_0_0_fu_202 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_137_reg_3260_pp0_it5 == ap_const_lv2_1))) begin
right_border_buf_2_val_0_1_fu_206 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_137_reg_3260_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_137_reg_3260_pp0_it5 == ap_const_lv2_0))) begin
right_border_buf_2_val_0_2_fu_210 <= k_buf_2_val_2_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_0)))) begin
right_border_buf_2_val_1_2_28_fu_270 <= right_border_buf_2_val_1_2_37_fu_1763_p3;
right_border_buf_2_val_1_2_29_fu_286 <= right_border_buf_2_val_1_2_35_fu_1746_p3;
right_border_buf_2_val_1_2_30_fu_294 <= right_border_buf_2_val_1_2_33_fu_1724_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7))) begin
src_kernel_win_0_val_0_1_lo_reg_3593 <= src_kernel_win_0_val_0_1_fu_226;
src_kernel_win_0_val_1_1_lo_reg_3599 <= src_kernel_win_0_val_1_1_fu_242;
src_kernel_win_0_val_1_2_lo_reg_3605 <= src_kernel_win_0_val_1_2_fu_246;
src_kernel_win_1_val_0_1_lo_reg_3620 <= src_kernel_win_1_val_0_1_fu_262;
src_kernel_win_1_val_1_1_lo_reg_3626 <= src_kernel_win_1_val_1_1_fu_278;
src_kernel_win_1_val_1_2_lo_reg_3632 <= src_kernel_win_1_val_1_2_fu_282;
src_kernel_win_2_val_0_1_lo_reg_3647 <= src_kernel_win_2_val_0_1_fu_298;
src_kernel_win_2_val_1_1_lo_reg_3653 <= src_kernel_win_2_val_1_1_fu_314;
src_kernel_win_2_val_1_2_lo_reg_3659 <= src_kernel_win_2_val_1_2_fu_318;
temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610 <= temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3;
temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637 <= temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3;
temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664 <= temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3;
tmp_220_0_1_reg_3615 <= tmp_220_0_1_fu_2364_p2;
tmp_220_1_1_reg_3642 <= tmp_220_1_1_fu_2394_p2;
tmp_220_2_1_reg_3669 <= tmp_220_2_1_fu_2424_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it9))) begin
src_kernel_win_0_val_0_2_fu_230 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it9;
src_kernel_win_1_val_0_2_fu_266 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it9;
src_kernel_win_2_val_0_2_fu_302 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it9;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9))) begin
src_kernel_win_0_val_0_2_lo_reg_3692 <= src_kernel_win_0_val_0_2_fu_230;
src_kernel_win_1_val_0_2_lo_reg_3707 <= src_kernel_win_1_val_0_2_fu_266;
src_kernel_win_2_val_0_2_lo_reg_3722 <= src_kernel_win_2_val_0_2_fu_302;
temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697 <= temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3;
temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712 <= temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3;
temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727 <= temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3;
tmp_220_0_2_reg_3702 <= tmp_220_0_2_fu_2506_p2;
tmp_220_1_2_reg_3717 <= tmp_220_1_2_fu_2525_p2;
tmp_220_2_2_reg_3732 <= tmp_220_2_2_fu_2544_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it8) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it7))) begin
src_kernel_win_0_val_1_2_fu_246 <= src_kernel_win_0_val_1_1_18_reg_3540;
src_kernel_win_1_val_1_2_fu_282 <= src_kernel_win_1_val_1_1_18_reg_3554;
src_kernel_win_2_val_1_2_fu_318 <= src_kernel_win_2_val_1_1_18_reg_3568;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6))) begin
src_kernel_win_0_val_2_2_fu_254 <= src_kernel_win_0_val_2_1_fu_238;
src_kernel_win_1_val_2_2_fu_290 <= src_kernel_win_1_val_2_1_fu_274;
src_kernel_win_2_val_2_2_fu_326 <= src_kernel_win_2_val_2_1_fu_310;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6))) begin
temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575 <= temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3;
temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581 <= temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3;
temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587 <= temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8))) begin
temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674 <= temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3;
temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680 <= temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3;
temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686 <= temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10))) begin
temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737 <= temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3;
temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743 <= temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3;
temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749 <= temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3))) begin
tmp_118_reg_3296 <= tmp_118_fu_1268_p1;
x_1_reg_3305 <= grp_image_filter_borderInterpolate_fu_700_ap_return;
x_2_reg_3317 <= grp_image_filter_borderInterpolate_fu_708_ap_return;
x_reg_3291 <= grp_image_filter_borderInterpolate_fu_692_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_fu_1138_p2))) begin
tmp_119_reg_3210 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_112_reg_3131))) begin
tmp_120_reg_3397 <= tmp_120_fu_1311_p1;
tmp_121_reg_3403 <= tmp_121_fu_1315_p1;
tmp_125_reg_3435 <= tmp_125_fu_1423_p1;
tmp_126_reg_3441 <= tmp_126_fu_1427_p1;
tmp_134_reg_3494 <= tmp_134_fu_1609_p1;
tmp_135_reg_3500 <= tmp_135_fu_1613_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131))) begin
tmp_122_reg_3276 <= tmp_122_fu_1256_p1;
tmp_127_reg_3281 <= tmp_127_fu_1260_p1;
tmp_136_reg_3286 <= tmp_136_fu_1264_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_1_fu_1173_p2))) begin
tmp_124_reg_3232 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_1_fu_1173_p2) & (ap_const_lv1_0 == tmp_173_1_fu_1187_p2))) begin
tmp_128_reg_3240 <= tmp_128_fu_1197_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_reg_3180) & ~(ap_const_lv1_0 == or_cond2_1_reg_3228) & (ap_const_lv1_0 == tmp_173_1_reg_3236))) begin
tmp_131_reg_3264 <= tmp_131_fu_1244_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_2_fu_1212_p2))) begin
tmp_133_reg_3252 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_2_fu_1212_p2) & (ap_const_lv1_0 == tmp_173_2_fu_1226_p2))) begin
tmp_137_reg_3260 <= tmp_137_fu_1236_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_reg_3180) & ~(ap_const_lv1_0 == or_cond2_2_reg_3248) & (ap_const_lv1_0 == tmp_173_2_reg_3256))) begin
tmp_140_reg_3270 <= tmp_140_fu_1252_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_1_fu_1173_p2))) begin
tmp_173_1_reg_3236 <= tmp_173_1_fu_1187_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_2_fu_1212_p2))) begin
tmp_173_2_reg_3256 <= tmp_173_2_fu_1226_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_fu_1138_p2))) begin
tmp_58_reg_3214 <= tmp_58_fu_1152_p2;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st5_fsm_4 or tmp_48_fu_977_p2)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_48_fu_977_p2)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st5_fsm_4 or tmp_48_fu_977_p2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_48_fu_977_p2))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_6 assign process. ///
always @ (ap_sig_bdd_175)
begin
if (ap_sig_bdd_175) begin
ap_sig_cseq_ST_pp0_stg0_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_6 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_27)
begin
if (ap_sig_bdd_27) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st20_fsm_7 assign process. ///
always @ (ap_sig_bdd_951)
begin
if (ap_sig_bdd_951) begin
ap_sig_cseq_ST_st20_fsm_7 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st20_fsm_7 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_94)
begin
if (ap_sig_bdd_94) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_103)
begin
if (ap_sig_bdd_103) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_133)
begin
if (ap_sig_bdd_133) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st6_fsm_5 assign process. ///
always @ (ap_sig_bdd_162)
begin
if (ap_sig_bdd_162) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_668_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or tmp_53_fu_1081_p2 or tmp_53_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_53_reg_3180) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it1))))) begin
grp_image_filter_borderInterpolate_fu_668_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_668_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_676_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or tmp_53_fu_1081_p2 or tmp_53_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_53_reg_3180) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it1))))) begin
grp_image_filter_borderInterpolate_fu_676_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_676_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_684_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or tmp_53_fu_1081_p2 or tmp_53_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_53_fu_1081_p2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_53_reg_3180) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it1))))) begin
grp_image_filter_borderInterpolate_fu_684_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_684_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_692_ap_ce assign process. ///
always @ (tmp_53_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_53_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it1)))) begin
grp_image_filter_borderInterpolate_fu_692_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_692_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_700_ap_ce assign process. ///
always @ (tmp_53_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_53_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it1)))) begin
grp_image_filter_borderInterpolate_fu_700_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_700_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_708_ap_ce assign process. ///
always @ (tmp_53_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_53_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it1)))) begin
grp_image_filter_borderInterpolate_fu_708_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_708_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_716_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_716_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_716_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_724_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_724_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_724_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_732_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_732_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_732_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_740_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_740_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_740_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_748_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_748_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_748_ap_ce = ap_const_logic_0;
end
end
/// grp_image_filter_borderInterpolate_fu_756_ap_ce assign process. ///
always @ (tmp_112_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it4)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_112_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it4))))) begin
grp_image_filter_borderInterpolate_fu_756_ap_ce = ap_const_logic_1;
end else begin
grp_image_filter_borderInterpolate_fu_756_ap_ce = ap_const_logic_0;
end
end
/// k_buf_0_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_0_ce0 = ap_const_logic_1;
end else begin
k_buf_0_val_0_ce0 = ap_const_logic_0;
end
end
/// k_buf_0_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_0_ce1 = ap_const_logic_1;
end else begin
k_buf_0_val_0_ce1 = ap_const_logic_0;
end
end
/// k_buf_0_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_0_we1 = ap_const_logic_1;
end else begin
k_buf_0_val_0_we1 = ap_const_logic_0;
end
end
/// k_buf_0_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_1_ce0 = ap_const_logic_1;
end else begin
k_buf_0_val_1_ce0 = ap_const_logic_0;
end
end
/// k_buf_0_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)))) begin
k_buf_0_val_1_ce1 = ap_const_logic_1;
end else begin
k_buf_0_val_1_ce1 = ap_const_logic_0;
end
end
/// k_buf_0_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)))) begin
k_buf_0_val_1_we1 = ap_const_logic_1;
end else begin
k_buf_0_val_1_we1 = ap_const_logic_0;
end
end
/// k_buf_0_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_0_val_2_ce0 = ap_const_logic_1;
end else begin
k_buf_0_val_2_ce0 = ap_const_logic_0;
end
end
/// k_buf_0_val_2_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)))) begin
k_buf_0_val_2_ce1 = ap_const_logic_1;
end else begin
k_buf_0_val_2_ce1 = ap_const_logic_0;
end
end
/// k_buf_0_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_58_reg_3214_pp0_it5)))) begin
k_buf_0_val_2_we1 = ap_const_logic_1;
end else begin
k_buf_0_val_2_we1 = ap_const_logic_0;
end
end
/// k_buf_1_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_0_ce0 = ap_const_logic_1;
end else begin
k_buf_1_val_0_ce0 = ap_const_logic_0;
end
end
/// k_buf_1_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_0_ce1 = ap_const_logic_1;
end else begin
k_buf_1_val_0_ce1 = ap_const_logic_0;
end
end
/// k_buf_1_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_0_we1 = ap_const_logic_1;
end else begin
k_buf_1_val_0_we1 = ap_const_logic_0;
end
end
/// k_buf_1_val_1_address1 assign process. ///
always @ (ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5 or tmp_205_1_fu_1516_p1 or k_buf_1_val_1_addr_3_gep_fu_554_p3 or ap_sig_bdd_967)
begin
if (ap_sig_bdd_967) begin
if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)) begin
k_buf_1_val_1_address1 = k_buf_1_val_1_addr_3_gep_fu_554_p3;
end else if ((ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)) begin
k_buf_1_val_1_address1 = tmp_205_1_fu_1516_p1;
end else begin
k_buf_1_val_1_address1 = 'bx;
end
end else begin
k_buf_1_val_1_address1 = 'bx;
end
end
/// k_buf_1_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_1_ce0 = ap_const_logic_1;
end else begin
k_buf_1_val_1_ce0 = ap_const_logic_0;
end
end
/// k_buf_1_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)))) begin
k_buf_1_val_1_ce1 = ap_const_logic_1;
end else begin
k_buf_1_val_1_ce1 = ap_const_logic_0;
end
end
/// k_buf_1_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_173_1_reg_3236_pp0_it5)))) begin
k_buf_1_val_1_we1 = ap_const_logic_1;
end else begin
k_buf_1_val_1_we1 = ap_const_logic_0;
end
end
/// k_buf_1_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_2_ce0 = ap_const_logic_1;
end else begin
k_buf_1_val_2_ce0 = ap_const_logic_0;
end
end
/// k_buf_1_val_2_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_2_ce1 = ap_const_logic_1;
end else begin
k_buf_1_val_2_ce1 = ap_const_logic_0;
end
end
/// k_buf_1_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_1_val_2_we1 = ap_const_logic_1;
end else begin
k_buf_1_val_2_we1 = ap_const_logic_0;
end
end
/// k_buf_2_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_0_ce0 = ap_const_logic_1;
end else begin
k_buf_2_val_0_ce0 = ap_const_logic_0;
end
end
/// k_buf_2_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_0_ce1 = ap_const_logic_1;
end else begin
k_buf_2_val_0_ce1 = ap_const_logic_0;
end
end
/// k_buf_2_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_0_we1 = ap_const_logic_1;
end else begin
k_buf_2_val_0_we1 = ap_const_logic_0;
end
end
/// k_buf_2_val_1_address1 assign process. ///
always @ (ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5 or tmp_205_2_fu_1702_p1 or k_buf_2_val_1_addr_3_gep_fu_594_p3 or ap_sig_bdd_979)
begin
if (ap_sig_bdd_979) begin
if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)) begin
k_buf_2_val_1_address1 = k_buf_2_val_1_addr_3_gep_fu_594_p3;
end else if ((ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)) begin
k_buf_2_val_1_address1 = tmp_205_2_fu_1702_p1;
end else begin
k_buf_2_val_1_address1 = 'bx;
end
end else begin
k_buf_2_val_1_address1 = 'bx;
end
end
/// k_buf_2_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_1_ce0 = ap_const_logic_1;
end else begin
k_buf_2_val_1_ce0 = ap_const_logic_0;
end
end
/// k_buf_2_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)))) begin
k_buf_2_val_1_ce1 = ap_const_logic_1;
end else begin
k_buf_2_val_1_ce1 = ap_const_logic_0;
end
end
/// k_buf_2_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)
begin
if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_173_2_reg_3256_pp0_it5)))) begin
k_buf_2_val_1_we1 = ap_const_logic_1;
end else begin
k_buf_2_val_1_we1 = ap_const_logic_0;
end
end
/// k_buf_2_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_2_ce0 = ap_const_logic_1;
end else begin
k_buf_2_val_2_ce0 = ap_const_logic_0;
end
end
/// k_buf_2_val_2_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_2_ce1 = ap_const_logic_1;
end else begin
k_buf_2_val_2_ce1 = ap_const_logic_0;
end
end
/// k_buf_2_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
k_buf_2_val_2_we1 = ap_const_logic_1;
end else begin
k_buf_2_val_2_we1 = ap_const_logic_0;
end
end
/// p_dst_data_stream_0_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_dst_data_stream_0_V_write = ap_const_logic_1;
end else begin
p_dst_data_stream_0_V_write = ap_const_logic_0;
end
end
/// p_dst_data_stream_1_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_dst_data_stream_1_V_write = ap_const_logic_1;
end else begin
p_dst_data_stream_1_V_write = ap_const_logic_0;
end
end
/// p_dst_data_stream_2_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_dst_data_stream_2_V_write = ap_const_logic_1;
end else begin
p_dst_data_stream_2_V_write = ap_const_logic_0;
end
end
/// p_src_data_stream_0_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_src_data_stream_0_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_0_V_read = ap_const_logic_0;
end
end
/// p_src_data_stream_1_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_src_data_stream_1_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_1_V_read = ap_const_logic_0;
end
end
/// p_src_data_stream_2_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
p_src_data_stream_2_V_read = ap_const_logic_1;
end else begin
p_src_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_67 or tmp_46_fu_926_p2 or tmp_48_fu_977_p2 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or tmp_41_fu_902_p2 or tmp_43_fu_914_p2)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_67) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(ap_const_lv1_0 == tmp_41_fu_902_p2)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if (~(ap_const_lv1_0 == tmp_43_fu_914_p2)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st4_fsm_3 :
begin
if (~(tmp_46_fu_926_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
end
ap_ST_st5_fsm_4 :
begin
if ((ap_const_lv1_0 == tmp_48_fu_977_p2)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
end
ap_ST_st6_fsm_5 :
begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
end
ap_ST_pp0_stg0_fsm_6 :
begin
if ((~((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it11)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it11)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)))) begin
ap_NS_fsm = ap_ST_st20_fsm_7;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
end
end
ap_ST_st20_fsm_7 :
begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ImagLoc_x_cast3_fu_1123_p1 = $signed(ImagLoc_x_fu_1113_p2);
assign ImagLoc_x_fu_1113_p2 = ($signed(tmp_56_cast_fu_1077_p1) + $signed(ap_const_lv12_FFF));
assign ImagLoc_y_fu_994_p2 = ($signed(tmp_53_cast_cast3_fu_973_p1) + $signed(ap_const_lv12_FFC));
/// ap_sig_bdd_103 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_103 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_133 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_133 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_162 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_162 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_175 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_175 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_218 assign process. ///
always @ (p_src_data_stream_0_V_empty_n or p_src_data_stream_1_V_empty_n or p_src_data_stream_2_V_empty_n or brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5)
begin
ap_sig_bdd_218 = (((p_src_data_stream_0_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (p_src_data_stream_1_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (p_src_data_stream_2_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5)));
end
/// ap_sig_bdd_244 assign process. ///
always @ (p_dst_data_stream_0_V_full_n or p_dst_data_stream_1_V_full_n or p_dst_data_stream_2_V_full_n or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11)
begin
ap_sig_bdd_244 = (((p_dst_data_stream_0_V_full_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11)) | (~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (p_dst_data_stream_1_V_full_n == ap_const_logic_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (p_dst_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_27 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_27 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_67 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_67 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_85 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_85 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_94 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_94 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_951 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_951 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end
/// ap_sig_bdd_967 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
ap_sig_bdd_967 = (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6));
end
/// ap_sig_bdd_979 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_53_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
ap_sig_bdd_979 = (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6));
end
assign brmerge_fu_1072_p2 = (tmp_51_fu_1057_p2 | or_cond_2_reg_3126);
assign col_assign_1_fu_1192_p2 = (ImagLoc_x_fu_1113_p2 + p_neg226_i_i_reg_3068);
assign col_assign_2_fu_1231_p2 = (ImagLoc_x_fu_1113_p2 + p_neg226_i_i_reg_3068);
assign col_assign_8_1_t1_fu_1450_p2 = (tmp_130_fu_1447_p1 + tmp_108_reg_3076);
assign col_assign_8_2_t1_fu_1636_p2 = (tmp_139_fu_1633_p1 + tmp_108_reg_3076);
assign col_assign_8_fu_1319_p2 = (ap_reg_ppstg_tmp_118_reg_3296_pp0_it5 + tmp_108_reg_3076);
assign col_assign_9_1_fu_1240_p2 = (ImagLoc_x_reg_3193 + p_neg226_i_i_reg_3068);
assign col_assign_9_2_fu_1248_p2 = (ImagLoc_x_reg_3193 + p_neg226_i_i_reg_3068);
assign col_assign_fu_1157_p2 = (tmp_117_fu_1119_p1 + tmp_108_reg_3076);
assign col_buf_0_val_0_0_21_fu_1913_p3 = ((sel_tmp_fu_1908_p2)? col_buf_0_val_0_0_19_fu_350: col_buf_0_val_0_0_20_fu_354);
assign col_buf_0_val_0_0_25_fu_1926_p3 = ((sel_tmp2_fu_1921_p2)? col_buf_0_val_0_0_18_fu_346: col_buf_0_val_0_0_21_fu_1913_p3);
assign col_buf_1_val_0_0_21_fu_1461_p3 = ((sel_tmp48_fu_1455_p2)? col_buf_1_val_0_0_19_fu_322: col_buf_1_val_0_0_18_fu_306);
assign col_buf_1_val_0_0_25_fu_1475_p3 = ((sel_tmp50_fu_1469_p2)? col_buf_1_val_0_0_20_fu_330: col_buf_1_val_0_0_21_fu_1461_p3);
assign col_buf_2_val_0_0_21_fu_1647_p3 = ((sel_tmp67_fu_1641_p2)? col_buf_2_val_0_0_19_fu_250: col_buf_2_val_0_0_18_fu_234);
assign col_buf_2_val_0_0_25_fu_1661_p3 = ((sel_tmp68_fu_1655_p2)? col_buf_2_val_0_0_20_fu_258: col_buf_2_val_0_0_21_fu_1647_p3);
assign cols_assign_cast2_fu_892_p1 = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_668_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_668_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_668_p = y_2_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_676_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_676_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_676_p = y_2_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_684_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_684_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_684_p = y_2_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_692_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_692_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_692_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_700_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_700_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_700_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_708_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_708_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_708_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_716_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_716_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_716_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_724_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_724_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_724_p = y_2_2_reg_3162;
assign grp_image_filter_borderInterpolate_fu_732_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_732_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_732_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_740_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_740_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_740_p = y_2_2_reg_3162;
assign grp_image_filter_borderInterpolate_fu_748_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_748_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_748_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_756_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_756_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_756_p = y_2_2_reg_3162;
assign heightloop_fu_932_p2 = (tmp_reg_2745 + ap_const_lv11_5);
assign i_V_fu_982_p2 = (p_012_0_i_i_reg_645 + ap_const_lv11_1);
assign icmp3_fu_1102_p2 = (tmp_116_fu_1092_p4 != ap_const_lv10_0? 1'b1: 1'b0);
assign icmp_fu_1010_p2 = ($signed(tmp_111_fu_1000_p4) > $signed(11'b00000000000)? 1'b1: 1'b0);
assign j_V_fu_1086_p2 = (p_025_0_i_i_reg_656 + ap_const_lv11_1);
assign k_buf_0_val_0_address0 = tmp_55_fu_1287_p1;
assign k_buf_0_val_0_address1 = k_buf_0_val_0_addr_reg_3329;
assign k_buf_0_val_0_d1 = p_src_data_stream_0_V_dout;
assign k_buf_0_val_1_address0 = tmp_55_fu_1287_p1;
assign k_buf_0_val_1_address1 = k_buf_0_val_1_addr_reg_3335;
assign k_buf_0_val_1_d1 = k_buf_0_val_0_q0;
assign k_buf_0_val_2_address0 = tmp_55_fu_1287_p1;
assign k_buf_0_val_2_address1 = k_buf_0_val_2_addr_reg_3341;
assign k_buf_0_val_2_d1 = k_buf_0_val_1_q0;
assign k_buf_1_val_0_address0 = tmp_163_1_fu_1294_p1;
assign k_buf_1_val_0_address1 = tmp_205_1_fu_1516_p1;
assign k_buf_1_val_0_d1 = p_src_data_stream_1_V_dout;
assign k_buf_1_val_1_addr_3_gep_fu_554_p3 = tmp_205_1_fu_1516_p1;
assign k_buf_1_val_1_address0 = tmp_163_1_fu_1294_p1;
assign k_buf_1_val_1_d1 = k_buf_1_val_0_q0;
assign k_buf_1_val_2_address0 = tmp_163_1_fu_1294_p1;
assign k_buf_1_val_2_address1 = tmp_205_1_fu_1516_p1;
assign k_buf_1_val_2_d1 = k_buf_1_val_1_q0;
assign k_buf_2_val_0_address0 = tmp_163_2_fu_1300_p1;
assign k_buf_2_val_0_address1 = tmp_205_2_fu_1702_p1;
assign k_buf_2_val_0_d1 = p_src_data_stream_2_V_dout;
assign k_buf_2_val_1_addr_3_gep_fu_594_p3 = tmp_205_2_fu_1702_p1;
assign k_buf_2_val_1_address0 = tmp_163_2_fu_1300_p1;
assign k_buf_2_val_1_d1 = k_buf_2_val_0_q0;
assign k_buf_2_val_2_address0 = tmp_163_2_fu_1300_p1;
assign k_buf_2_val_2_address1 = tmp_205_2_fu_1702_p1;
assign k_buf_2_val_2_d1 = k_buf_2_val_1_q0;
assign locy_0_1_t_fu_1846_p2 = (tmp_115_reg_3155 - tmp_121_reg_3403);
assign locy_0_2_t_fu_1272_p2 = (tmp_115_reg_3155 - tmp_122_reg_3276);
assign locy_1_0_t_fu_1993_p2 = (tmp_52_reg_3135 - tmp_125_reg_3435);
assign locy_1_1_t_fu_2025_p2 = (tmp_52_reg_3135 - tmp_126_reg_3441);
assign locy_1_2_t_fu_1276_p2 = (tmp_52_reg_3135 - tmp_127_reg_3281);
assign locy_2_0_t_fu_2159_p2 = (tmp_52_reg_3135 - tmp_134_reg_3494);
assign locy_2_1_t_fu_2191_p2 = (tmp_52_reg_3135 - tmp_135_reg_3500);
assign locy_2_2_t_fu_1280_p2 = (tmp_52_reg_3135 - tmp_136_reg_3286);
assign locy_fu_1814_p2 = (tmp_113_reg_3149 - tmp_120_reg_3397);
assign or_cond219_i_i_fu_1108_p2 = (tmp_50_reg_3113 & icmp3_fu_1102_p2);
assign or_cond2_1_fu_1173_p2 = (tmp_168_1_fu_1162_p2 & tmp_170_1_fu_1168_p2);
assign or_cond2_2_fu_1212_p2 = (tmp_168_2_fu_1201_p2 & tmp_170_2_fu_1207_p2);
assign or_cond2_fu_1138_p2 = (tmp_56_fu_1127_p2 & tmp_57_fu_1133_p2);
assign or_cond_2_fu_1021_p2 = (icmp_fu_1010_p2 & tmp_165_2_fu_1016_p2);
assign p_dst_data_stream_0_V_din = ((tmp_220_0_2_2_fu_2613_p2)? ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11: temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737);
assign p_dst_data_stream_1_V_din = ((tmp_220_1_2_2_fu_2624_p2)? ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11: temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743);
assign p_dst_data_stream_2_V_din = ((tmp_220_2_2_2_fu_2635_p2)? ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11: temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749);
assign p_i_i_fu_1042_p3 = ((tmp_165_2_fu_1016_p2)? ap_const_lv11_2: ref_reg_3084);
assign p_neg226_i_i_fu_951_p2 = (ap_const_lv12_3 - p_src_cols_V_read);
assign ref_cast_fu_965_p1 = ref_fu_960_p2;
assign ref_fu_960_p2 = ($signed(tmp_reg_2745) + $signed(ap_const_lv11_7FF));
assign right_border_buf_0_val_1_2_10_fu_1382_p3 = ((sel_tmp26_fu_1360_p2)? right_border_buf_0_val_1_2_22_fu_338: right_border_buf_0_val_1_2_9_fu_1374_p3);
assign right_border_buf_0_val_1_2_26_fu_1391_p3 = ((sel_tmp26_fu_1360_p2)? k_buf_0_val_1_q0: right_border_buf_0_val_1_2_21_fu_334);
assign right_border_buf_0_val_1_2_27_fu_1943_p3 = ((sel_tmp2_fu_1921_p2)? right_border_buf_0_val_1_2_21_fu_334: right_border_buf_0_val_1_2_fu_1935_p3);
assign right_border_buf_0_val_1_2_7_fu_1352_p3 = ((sel_tmp24_fu_1347_p2)? right_border_buf_0_val_1_2_23_fu_342: k_buf_0_val_1_q0);
assign right_border_buf_0_val_1_2_8_fu_1365_p3 = ((sel_tmp26_fu_1360_p2)? right_border_buf_0_val_1_2_23_fu_342: right_border_buf_0_val_1_2_7_fu_1352_p3);
assign right_border_buf_0_val_1_2_9_fu_1374_p3 = ((sel_tmp24_fu_1347_p2)? k_buf_0_val_1_q0: right_border_buf_0_val_1_2_22_fu_338);
assign right_border_buf_0_val_1_2_fu_1935_p3 = ((sel_tmp_fu_1908_p2)? right_border_buf_0_val_1_2_22_fu_338: right_border_buf_0_val_1_2_23_fu_342);
assign right_border_buf_1_val_1_2_10_fu_1551_p3 = ((sel_tmp38_fu_1546_p2)? right_border_buf_1_val_1_2_22_fu_366: right_border_buf_1_val_1_2_9_fu_1538_p3);
assign right_border_buf_1_val_1_2_25_fu_1560_p3 = ((sel_tmp36_fu_1533_p2)? k_buf_1_val_1_q0: right_border_buf_1_val_1_2_21_fu_362);
assign right_border_buf_1_val_1_2_26_fu_1568_p3 = ((sel_tmp38_fu_1546_p2)? right_border_buf_1_val_1_2_21_fu_362: right_border_buf_1_val_1_2_25_fu_1560_p3);
assign right_border_buf_1_val_1_2_27_fu_1577_p3 = ((sel_tmp38_fu_1546_p2)? k_buf_1_val_1_q0: right_border_buf_1_val_1_2_20_fu_358);
assign right_border_buf_1_val_1_2_7_fu_2098_p3 = ((tmp_129_reg_3447)? ap_const_lv8_0: right_border_buf_1_val_1_2_fu_2091_p3);
assign right_border_buf_1_val_1_2_9_fu_1538_p3 = ((sel_tmp36_fu_1533_p2)? right_border_buf_1_val_1_2_22_fu_366: k_buf_1_val_1_q0);
assign right_border_buf_1_val_1_2_fu_2091_p3 = ((sel_tmp60_reg_3469)? right_border_buf_1_val_1_2_21_fu_362: right_border_buf_1_val_1_2_22_fu_366);
assign right_border_buf_2_val_1_2_33_fu_1724_p3 = ((sel_tmp73_fu_1719_p2)? k_buf_2_val_1_q0: right_border_buf_2_val_1_2_30_fu_294);
assign right_border_buf_2_val_1_2_34_fu_1738_p3 = ((sel_tmp74_fu_1733_p2)? k_buf_2_val_1_q0: right_border_buf_2_val_1_2_29_fu_286);
assign right_border_buf_2_val_1_2_35_fu_1746_p3 = ((sel_tmp73_fu_1719_p2)? right_border_buf_2_val_1_2_29_fu_286: right_border_buf_2_val_1_2_34_fu_1738_p3);
assign right_border_buf_2_val_1_2_36_fu_1755_p3 = ((sel_tmp74_fu_1733_p2)? right_border_buf_2_val_1_2_28_fu_270: k_buf_2_val_1_q0);
assign right_border_buf_2_val_1_2_37_fu_1763_p3 = ((sel_tmp73_fu_1719_p2)? right_border_buf_2_val_1_2_28_fu_270: right_border_buf_2_val_1_2_36_fu_1755_p3);
assign right_border_buf_2_val_1_2_3_fu_2264_p3 = ((tmp_138_reg_3506)? ap_const_lv8_0: right_border_buf_2_val_1_2_fu_2257_p3);
assign right_border_buf_2_val_1_2_fu_2257_p3 = ((sel_tmp72_reg_3528)? right_border_buf_2_val_1_2_29_fu_286: right_border_buf_2_val_1_2_28_fu_270);
assign sel_tmp10_fu_1832_p2 = (locy_fu_1814_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp12_fu_1853_p2 = (tmp_115_reg_3155 == tmp_121_reg_3403? 1'b1: 1'b0);
assign sel_tmp13_fu_1857_p3 = ((sel_tmp12_fu_1853_p2)? col_buf_0_val_0_0_fu_214: src_kernel_win_0_val_2_0_reg_3390);
assign sel_tmp14_fu_1864_p2 = (locy_0_1_t_fu_1846_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp16_fu_2000_p2 = (tmp_52_reg_3135 == tmp_125_reg_3435? 1'b1: 1'b0);
assign sel_tmp17_fu_2004_p3 = ((sel_tmp16_fu_2000_p2)? col_buf_1_val_0_0_fu_218: src_kernel_win_1_val_2_0_reg_3428);
assign sel_tmp18_fu_2011_p2 = (locy_1_0_t_fu_1993_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp20_fu_2032_p2 = (tmp_52_reg_3135 == tmp_126_reg_3441? 1'b1: 1'b0);
assign sel_tmp21_fu_2036_p3 = ((sel_tmp20_fu_2032_p2)? col_buf_1_val_0_0_fu_218: src_kernel_win_1_val_2_0_reg_3428);
assign sel_tmp22_fu_2043_p2 = (locy_1_1_t_fu_2025_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp24_fu_1347_p2 = (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp26_fu_1360_p2 = (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp2_fu_1921_p2 = (col_assign_8_reg_3409 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp36_fu_1533_p2 = (ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp38_fu_1546_p2 = (ap_reg_ppstg_tmp_131_reg_3264_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp48_fu_1455_p2 = (col_assign_8_1_t1_fu_1450_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp50_fu_1469_p2 = (col_assign_8_1_t1_fu_1450_p2 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp56_fu_2078_p3 = ((tmp_129_reg_3447)? ap_const_lv8_0: col_buf_1_val_0_0_25_reg_3457);
assign sel_tmp58_fu_1483_p2 = (tmp_129_fu_1440_p3 ^ ap_const_lv1_1);
assign sel_tmp59_fu_1489_p2 = (sel_tmp50_fu_1469_p2 & sel_tmp58_fu_1483_p2);
assign sel_tmp60_fu_1495_p2 = (sel_tmp48_fu_1455_p2 & sel_tmp58_fu_1483_p2);
assign sel_tmp61_fu_2166_p2 = (tmp_52_reg_3135 == tmp_134_reg_3494? 1'b1: 1'b0);
assign sel_tmp62_fu_2170_p3 = ((sel_tmp61_fu_2166_p2)? col_buf_2_val_0_0_fu_222: src_kernel_win_2_val_2_0_reg_3487);
assign sel_tmp63_fu_2177_p2 = (locy_2_0_t_fu_2159_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp64_fu_2198_p2 = (tmp_52_reg_3135 == tmp_135_reg_3500? 1'b1: 1'b0);
assign sel_tmp65_fu_2202_p3 = ((sel_tmp64_fu_2198_p2)? col_buf_2_val_0_0_fu_222: src_kernel_win_2_val_2_0_reg_3487);
assign sel_tmp66_fu_2209_p2 = (locy_2_1_t_fu_2191_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp67_fu_1641_p2 = (col_assign_8_2_t1_fu_1636_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp68_fu_1655_p2 = (col_assign_8_2_t1_fu_1636_p2 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp69_fu_2244_p3 = ((tmp_138_reg_3506)? ap_const_lv8_0: col_buf_2_val_0_0_25_reg_3516);
assign sel_tmp70_fu_1669_p2 = (tmp_138_fu_1626_p3 ^ ap_const_lv1_1);
assign sel_tmp71_fu_1675_p2 = (sel_tmp68_fu_1655_p2 & sel_tmp70_fu_1669_p2);
assign sel_tmp72_fu_1681_p2 = (sel_tmp67_fu_1641_p2 & sel_tmp70_fu_1669_p2);
assign sel_tmp73_fu_1719_p2 = (ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp74_fu_1733_p2 = (ap_reg_ppstg_tmp_140_reg_3270_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp8_fu_1821_p2 = (tmp_113_reg_3149 == tmp_120_reg_3397? 1'b1: 1'b0);
assign sel_tmp9_fu_1825_p3 = ((sel_tmp8_fu_1821_p2)? col_buf_0_val_0_0_fu_214: src_kernel_win_0_val_2_0_reg_3390);
assign sel_tmp_fu_1908_p2 = (col_assign_8_reg_3409 == ap_const_lv2_1? 1'b1: 1'b0);
assign src_kernel_win_0_val_0_1_15_fu_1838_p3 = ((sel_tmp10_fu_1832_p2)? right_border_buf_0_val_1_0_reg_3382: sel_tmp9_fu_1825_p3);
assign src_kernel_win_0_val_1_1_15_fu_1870_p3 = ((sel_tmp14_fu_1864_p2)? right_border_buf_0_val_1_0_reg_3382: sel_tmp13_fu_1857_p3);
assign src_kernel_win_1_val_0_1_15_fu_2017_p3 = ((sel_tmp18_fu_2011_p2)? right_border_buf_1_val_1_0_reg_3420: sel_tmp17_fu_2004_p3);
assign src_kernel_win_1_val_0_1_16_fu_2084_p3 = ((sel_tmp59_reg_3463)? col_buf_1_val_0_0_25_reg_3457: sel_tmp56_fu_2078_p3);
assign src_kernel_win_1_val_1_1_15_fu_2049_p3 = ((sel_tmp22_fu_2043_p2)? right_border_buf_1_val_1_0_reg_3420: sel_tmp21_fu_2036_p3);
assign src_kernel_win_1_val_1_1_16_fu_2105_p3 = ((sel_tmp59_reg_3463)? right_border_buf_1_val_1_2_20_fu_358: right_border_buf_1_val_1_2_7_fu_2098_p3);
assign src_kernel_win_2_val_0_1_15_fu_2183_p3 = ((sel_tmp63_fu_2177_p2)? right_border_buf_2_val_1_0_reg_3479: sel_tmp62_fu_2170_p3);
assign src_kernel_win_2_val_0_1_16_fu_2250_p3 = ((sel_tmp71_reg_3522)? col_buf_2_val_0_0_25_reg_3516: sel_tmp69_fu_2244_p3);
assign src_kernel_win_2_val_1_1_15_fu_2215_p3 = ((sel_tmp66_fu_2209_p2)? right_border_buf_2_val_1_0_reg_3479: sel_tmp65_fu_2202_p3);
assign src_kernel_win_2_val_1_1_16_fu_2271_p3 = ((sel_tmp71_reg_3522)? right_border_buf_2_val_1_2_30_fu_294: right_border_buf_2_val_1_2_3_fu_2264_p3);
assign temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3 = ((tmp_220_0_0_1_fu_1979_p2)? src_kernel_win_0_val_2_1_fu_238: src_kernel_win_0_val_2_2_fu_254);
assign temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3 = ((tmp_220_0_0_2_fu_2352_p2)? src_kernel_win_0_val_2_1_fu_238: temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575);
assign temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3 = ((tmp_220_0_1_1_fu_2447_p2)? ap_reg_ppstg_src_kernel_win_0_val_1_1_18_reg_3540_pp0_it8: temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3);
assign temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3 = ((tmp_220_0_1_2_fu_2496_p2)? ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9: temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674);
assign temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3 = ((tmp_220_0_1_reg_3615)? src_kernel_win_0_val_1_2_lo_reg_3605: temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610);
assign temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3 = ((tmp_220_0_2_1_fu_2567_p2)? ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it10: temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3);
assign temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3 = ((tmp_220_0_2_reg_3702)? src_kernel_win_0_val_0_2_lo_reg_3692: temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697);
assign temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3 = ((tmp_220_1_0_1_fu_2145_p2)? src_kernel_win_1_val_2_1_fu_274: src_kernel_win_1_val_2_2_fu_290);
assign temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3 = ((tmp_220_1_0_2_fu_2382_p2)? src_kernel_win_1_val_2_1_fu_274: temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581);
assign temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3 = ((tmp_220_1_1_1_fu_2464_p2)? ap_reg_ppstg_src_kernel_win_1_val_1_1_18_reg_3554_pp0_it8: temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3);
assign temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3 = ((tmp_220_1_1_2_fu_2515_p2)? ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9: temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680);
assign temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3 = ((tmp_220_1_1_reg_3642)? src_kernel_win_1_val_1_2_lo_reg_3632: temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637);
assign temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3 = ((tmp_220_1_2_1_fu_2584_p2)? ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it10: temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3);
assign temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3 = ((tmp_220_1_2_reg_3717)? src_kernel_win_1_val_0_2_lo_reg_3707: temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712);
assign temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3 = ((tmp_220_2_0_1_fu_2311_p2)? src_kernel_win_2_val_2_1_fu_310: src_kernel_win_2_val_2_2_fu_326);
assign temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3 = ((tmp_220_2_0_2_fu_2412_p2)? src_kernel_win_2_val_2_1_fu_310: temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587);
assign temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3 = ((tmp_220_2_1_1_fu_2481_p2)? ap_reg_ppstg_src_kernel_win_2_val_1_1_18_reg_3568_pp0_it8: temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3);
assign temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3 = ((tmp_220_2_1_2_fu_2534_p2)? ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9: temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686);
assign temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3 = ((tmp_220_2_1_reg_3669)? src_kernel_win_2_val_1_2_lo_reg_3659: temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664);
assign temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3 = ((tmp_220_2_2_1_fu_2601_p2)? ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it10: temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3);
assign temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3 = ((tmp_220_2_2_reg_3732)? src_kernel_win_2_val_0_2_lo_reg_3722: temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727);
assign tmp_107_fu_888_p1 = p_src_cols_V_read[10:0];
assign tmp_108_fu_956_p1 = p_neg226_i_i_fu_951_p2[1:0];
assign tmp_110_fu_969_p1 = ref_fu_960_p2[1:0];
assign tmp_111_fu_1000_p4 = {{ImagLoc_y_fu_994_p2[ap_const_lv32_B : ap_const_lv32_1]}};
assign tmp_113_fu_1049_p1 = p_i_i_fu_1042_p3[1:0];
assign tmp_115_fu_1053_p1 = p_i_i_fu_1042_p3[1:0];
assign tmp_116_fu_1092_p4 = {{p_025_0_i_i_reg_656[ap_const_lv32_A : ap_const_lv32_1]}};
assign tmp_117_fu_1119_p1 = ImagLoc_x_fu_1113_p2[1:0];
assign tmp_118_fu_1268_p1 = grp_image_filter_borderInterpolate_fu_692_ap_return[1:0];
assign tmp_120_fu_1311_p1 = grp_image_filter_borderInterpolate_fu_716_ap_return[1:0];
assign tmp_121_fu_1315_p1 = grp_image_filter_borderInterpolate_fu_724_ap_return[1:0];
assign tmp_122_fu_1256_p1 = grp_image_filter_borderInterpolate_fu_668_ap_return[1:0];
assign tmp_125_fu_1423_p1 = grp_image_filter_borderInterpolate_fu_732_ap_return[1:0];
assign tmp_126_fu_1427_p1 = grp_image_filter_borderInterpolate_fu_740_ap_return[1:0];
assign tmp_127_fu_1260_p1 = grp_image_filter_borderInterpolate_fu_676_ap_return[1:0];
assign tmp_128_fu_1197_p1 = col_assign_1_fu_1192_p2[1:0];
assign tmp_129_fu_1440_p3 = ap_reg_ppstg_x_1_reg_3305_pp0_it5[ap_const_lv32_E];
assign tmp_130_fu_1447_p1 = ap_reg_ppstg_x_1_reg_3305_pp0_it5[1:0];
assign tmp_131_fu_1244_p1 = col_assign_9_1_fu_1240_p2[1:0];
assign tmp_134_fu_1609_p1 = grp_image_filter_borderInterpolate_fu_748_ap_return[1:0];
assign tmp_135_fu_1613_p1 = grp_image_filter_borderInterpolate_fu_756_ap_return[1:0];
assign tmp_136_fu_1264_p1 = grp_image_filter_borderInterpolate_fu_684_ap_return[1:0];
assign tmp_137_fu_1236_p1 = col_assign_2_fu_1231_p2[1:0];
assign tmp_138_fu_1626_p3 = ap_reg_ppstg_x_2_reg_3317_pp0_it5[ap_const_lv32_E];
assign tmp_139_fu_1633_p1 = ap_reg_ppstg_x_2_reg_3317_pp0_it5[1:0];
assign tmp_140_fu_1252_p1 = col_assign_9_2_fu_1248_p2[1:0];
assign tmp_163_1_fu_1294_p1 = $signed(x_1_reg_3305);
assign tmp_163_2_fu_1300_p1 = $signed(x_2_reg_3317);
assign tmp_165_2_fu_1016_p2 = ($signed(ImagLoc_y_fu_994_p2) < $signed(ref_cast_reg_3089)? 1'b1: 1'b0);
assign tmp_168_1_fu_1162_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_168_2_fu_1201_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_170_1_fu_1168_p2 = ($signed(ImagLoc_x_cast3_fu_1123_p1) < $signed(cols_assign_cast2_reg_2757)? 1'b1: 1'b0);
assign tmp_170_2_fu_1207_p2 = ($signed(ImagLoc_x_cast3_fu_1123_p1) < $signed(cols_assign_cast2_reg_2757)? 1'b1: 1'b0);
assign tmp_173_1_fu_1187_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_52_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_173_2_fu_1226_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_52_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_205_1_fu_1516_p1 = $unsigned(x_1_ext_fu_1415_p1);
assign tmp_205_2_fu_1702_p1 = $unsigned(x_2_ext_fu_1601_p1);
assign tmp_220_0_0_1_fu_1979_p2 = (src_kernel_win_0_val_2_1_fu_238 > src_kernel_win_0_val_2_2_fu_254? 1'b1: 1'b0);
assign tmp_220_0_0_2_fu_2352_p2 = (src_kernel_win_0_val_2_1_fu_238 > temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575? 1'b1: 1'b0);
assign tmp_220_0_1_1_fu_2447_p2 = (ap_reg_ppstg_src_kernel_win_0_val_1_1_18_reg_3540_pp0_it8 > temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3? 1'b1: 1'b0);
assign tmp_220_0_1_2_fu_2496_p2 = (ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9 > temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674? 1'b1: 1'b0);
assign tmp_220_0_1_fu_2364_p2 = (src_kernel_win_0_val_1_2_fu_246 > temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3? 1'b1: 1'b0);
assign tmp_220_0_2_1_fu_2567_p2 = (ap_reg_ppstg_src_kernel_win_0_val_0_1_18_reg_3533_pp0_it10 > temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3? 1'b1: 1'b0);
assign tmp_220_0_2_2_fu_2613_p2 = (ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11 > temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737? 1'b1: 1'b0);
assign tmp_220_0_2_fu_2506_p2 = (src_kernel_win_0_val_0_2_fu_230 > temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3? 1'b1: 1'b0);
assign tmp_220_1_0_1_fu_2145_p2 = (src_kernel_win_1_val_2_1_fu_274 > src_kernel_win_1_val_2_2_fu_290? 1'b1: 1'b0);
assign tmp_220_1_0_2_fu_2382_p2 = (src_kernel_win_1_val_2_1_fu_274 > temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581? 1'b1: 1'b0);
assign tmp_220_1_1_1_fu_2464_p2 = (ap_reg_ppstg_src_kernel_win_1_val_1_1_18_reg_3554_pp0_it8 > temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3? 1'b1: 1'b0);
assign tmp_220_1_1_2_fu_2515_p2 = (ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9 > temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680? 1'b1: 1'b0);
assign tmp_220_1_1_fu_2394_p2 = (src_kernel_win_1_val_1_2_fu_282 > temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3? 1'b1: 1'b0);
assign tmp_220_1_2_1_fu_2584_p2 = (ap_reg_ppstg_src_kernel_win_1_val_0_1_18_reg_3547_pp0_it10 > temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3? 1'b1: 1'b0);
assign tmp_220_1_2_2_fu_2624_p2 = (ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11 > temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743? 1'b1: 1'b0);
assign tmp_220_1_2_fu_2525_p2 = (src_kernel_win_1_val_0_2_fu_266 > temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3? 1'b1: 1'b0);
assign tmp_220_2_0_1_fu_2311_p2 = (src_kernel_win_2_val_2_1_fu_310 > src_kernel_win_2_val_2_2_fu_326? 1'b1: 1'b0);
assign tmp_220_2_0_2_fu_2412_p2 = (src_kernel_win_2_val_2_1_fu_310 > temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587? 1'b1: 1'b0);
assign tmp_220_2_1_1_fu_2481_p2 = (ap_reg_ppstg_src_kernel_win_2_val_1_1_18_reg_3568_pp0_it8 > temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3? 1'b1: 1'b0);
assign tmp_220_2_1_2_fu_2534_p2 = (ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9 > temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686? 1'b1: 1'b0);
assign tmp_220_2_1_fu_2424_p2 = (src_kernel_win_2_val_1_2_fu_318 > temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3? 1'b1: 1'b0);
assign tmp_220_2_2_1_fu_2601_p2 = (ap_reg_ppstg_src_kernel_win_2_val_0_1_18_reg_3561_pp0_it10 > temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3? 1'b1: 1'b0);
assign tmp_220_2_2_2_fu_2635_p2 = (ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11 > temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749? 1'b1: 1'b0);
assign tmp_220_2_2_fu_2544_p2 = (src_kernel_win_2_val_0_2_fu_302 > temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3? 1'b1: 1'b0);
assign tmp_40_fu_896_p2 = (tmp_39_reg_612 + ap_const_lv2_1);
assign tmp_41_fu_902_p2 = (tmp_39_reg_612 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_42_fu_908_p2 = (tmp_s_reg_623 + ap_const_lv2_1);
assign tmp_43_fu_914_p2 = (tmp_s_reg_623 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_45_fu_920_p2 = (tmp_44_reg_634 + ap_const_lv2_1);
assign tmp_46_fu_926_p2 = (tmp_44_reg_634 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_47_fu_942_p2 = ($signed(tmp_107_reg_2751) + $signed(ap_const_lv11_7FD));
assign tmp_48_fu_977_p2 = (p_012_0_i_i_reg_645 < heightloop_reg_3051? 1'b1: 1'b0);
assign tmp_50_fu_988_p2 = (p_012_0_i_i_reg_645 > ap_const_lv11_4? 1'b1: 1'b0);
assign tmp_51_fu_1057_p2 = ($signed(ImagLoc_y_reg_3118) < $signed(12'b111111111111)? 1'b1: 1'b0);
assign tmp_52_cast_fu_947_p1 = tmp_47_fu_942_p2;
assign tmp_52_fu_1035_p3 = ((tmp_165_2_fu_1016_p2)? ap_const_lv2_2: tmp_110_reg_3094);
assign tmp_53_cast_cast3_fu_973_p1 = p_012_0_i_i_reg_645;
assign tmp_53_fu_1081_p2 = (p_025_0_i_i_reg_656 < widthloop_reg_3056? 1'b1: 1'b0);
assign tmp_55_fu_1287_p1 = $unsigned(x_ext_fu_1284_p1);
assign tmp_56_cast_fu_1077_p1 = p_025_0_i_i_reg_656;
assign tmp_56_fu_1127_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_57_fu_1133_p2 = ($signed(ImagLoc_x_cast3_fu_1123_p1) < $signed(cols_assign_cast2_reg_2757)? 1'b1: 1'b0);
assign tmp_58_fu_1152_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_52_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_fu_884_p1 = p_src_rows_V_read[10:0];
assign widthloop_fu_937_p2 = (tmp_107_reg_2751 + ap_const_lv11_2);
assign x_1_ext_fu_1415_p1 = $signed(ap_reg_ppstg_x_1_reg_3305_pp0_it5);
assign x_2_ext_fu_1601_p1 = $signed(ap_reg_ppstg_x_2_reg_3317_pp0_it5);
assign x_ext_fu_1284_p1 = $signed(x_reg_3291);
assign y_2_2_1_fu_1067_p2 = ($signed(tmp_53_cast_cast3_reg_3099) + $signed(ap_const_lv12_FFA));
assign y_2_2_fu_1062_p2 = ($signed(tmp_53_cast_cast3_reg_3099) + $signed(ap_const_lv12_FFB));
always @ (posedge ap_clk)
begin
cols_assign_cast2_reg_2757[12] <= 1'b0;
tmp_52_cast_reg_3061[11] <= 1'b0;
ref_cast_reg_3089[11] <= 1'b0;
tmp_53_cast_cast3_reg_3099[11] <= 1'b0;
end
endmodule //image_filter_Dilate_32_32_1080_1920_s
|
// fir8dec.v: 8x FIR decimator with TDM I/Q I/O
// 07-17-16 E. Brombaugh
module fir8dec #(
parameter isz = 16, // input data size
osz = 16, // output data size
psz = 8, // pointer size
csz = 16, // coeff data size
clen = 246, // coeff data length
agrw = 3 // accumulator growth
)
(
input clk, // System clock
input reset, // System POR
input ena, // New sample available on input
input signed [isz-1:0] iq_in, // Input data
output reg valid, // New output sample ready
output reg signed [osz-1:0] qi_out // Output data - reverse order
);
//------------------------------
// write address generator
//------------------------------
reg [psz:0] w_addr;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
w_addr <= {psz+1{1'd0}};
end
else
begin
if(ena == 1'b1)
begin
w_addr <= w_addr + 1;
end
end
end
//------------------------------
// MAC control state machine
//------------------------------
`define sm_wait 3'b000
`define sm_macq 3'b001
`define sm_maci 3'b010
`define sm_dmpq 3'b011
`define sm_dmpi 3'b100
reg [2:0] state;
reg mac_ena, dump;
reg [psz:0] r_addr;
reg [psz-1:0] c_addr;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
state <= `sm_wait;
mac_ena <= 1'b0;
dump <= 1'b0;
r_addr <= {psz+1{1'd0}};
c_addr <= {psz{1'd0}};
end
else
begin
case(state)
`sm_wait :
begin
// halt and hold
if(w_addr[3:0] == 4'b1111)
begin
// start a MAC sequence every 16 entries (8 samples)
state <= `sm_macq;
mac_ena <= 1'b1;
r_addr <= w_addr;
c_addr <= {psz{1'd0}};
end
end
`sm_macq :
begin
// Accumulate Q and advance to I
state <= `sm_maci;
r_addr <= r_addr - 1;
end
`sm_maci :
begin
// Accumulate I
if(c_addr != clen)
begin
// advance to next coeff
state <= `sm_macq;
r_addr <= r_addr - 1;
c_addr <= c_addr + 1;
end
else
begin
// finish mac and advance to dump Q
state <= `sm_dmpq;
mac_ena <= 1'b0;
dump <= 1'b1;
end
end
`sm_dmpq :
begin
// advance to dump 1
state <= `sm_dmpi;
end
`sm_dmpi :
begin
// finish dump and return to wait
state <= `sm_wait;
dump <= 1'b0;
end
default :
begin
state <= `sm_wait;
mac_ena <= 1'b0;
dump <= 1'b0;
end
endcase
end
end
//------------------------------
// input buffer memory
//------------------------------
reg signed [isz-1:0] buf_mem [511:0];
reg signed [isz-1:0] r_data;
always @(posedge clk) // Write memory.
begin
if(ena == 1'b1)
begin
buf_mem[w_addr] <= iq_in;
end
end
always @(posedge clk) // Read memory.
begin
r_data <= buf_mem[r_addr];
end
//------------------------------
// coeff ROM
//------------------------------
reg signed [csz-1:0] coeff_rom[0:255];
reg signed [csz-1:0] c_data;
initial
begin
$readmemh("../src/fir8dec_coeff.memh", coeff_rom);
end
always @(posedge clk)
begin
c_data <= coeff_rom[c_addr];
end
//------------------------------
// MAC
//------------------------------
reg [2:0] mac_ena_pipe;
reg [2:0] dump_pipe;
reg signed [csz+isz-1:0] mult;
reg signed [csz+isz+agrw-1:0] acc_a, acc_b;
wire signed [csz+isz+agrw-1:0] rnd_const = 1<<(csz+1);
wire signed [osz-1:0] qi_sat;
// Saturate accum output
sat #(.isz(agrw+osz-2), .osz(osz))
u_sat(.in(acc_b[csz+isz+agrw-1:csz+2]), .out(qi_sat));
always @(posedge clk)
begin
if(reset == 1'b1)
begin
mac_ena_pipe <= 3'b000;
dump_pipe <= 3'b000;
mult <= {csz+isz{1'b0}};
acc_a <= rnd_const;
acc_b <= rnd_const;
valid <= 1'b0;
qi_out <= {osz{1'b0}};
end
else
begin
// shift pipes
mac_ena_pipe <= {mac_ena_pipe[1:0],mac_ena};
dump_pipe <= {dump_pipe[1:0],dump};
// multiplier always runs
mult <= r_data * c_data;
// accumulator
if(mac_ena_pipe[1] == 1'b1)
begin
// two-term accumulate
acc_a <= acc_b + {{agrw{mult[csz+isz-1]}},mult};
acc_b <= acc_a;
end
else
begin
// clear to round constant
acc_a <= rnd_const;
acc_b <= acc_a;
end
// output
if(dump_pipe[1] == 1'b1)
begin
qi_out <= qi_sat;
end
// valid
valid <= dump_pipe[1];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_ls__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ls__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_FUNCTIONAL_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module timestamp640_core
#(
parameter ABUSWIDTH = 16,
parameter IDENTIFIER = 4'b0001,
parameter CLKDV = 4
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK320,
input wire CLK160,
input wire CLK40,
input wire DI,
input wire EXT_ENABLE,
input wire [63:0] EXT_TIMESTAMP,
output wire [63:0] TIMESTAMP_OUT,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire FIFO_READ_TRAILING,
output wire FIFO_EMPTY_TRAILING,
output wire [31:0] FIFO_DATA_TRAILING
);
localparam VERSION = 3;
//output format:
//31-28: ID, 27-24: 0x1, 23-0: 23-0th bit of timestamp data
//31-28: ID, 27-24: 0x2, 23-0: 47-24th bit of timestamp data
//31-28: ID, 27-24: 0x3, 23-8: tot 7-0: 55-48th bit of timestamp data
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN, CONF_EXT_ENABLE;
reg CONF_EXT_TIMESTAMP,CONF_EN_TRAILING,CONF_EN_INVERT;
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_EXT_TIMESTAMP <=0;
CONF_EXT_ENABLE <= 0;
CONF_EN_TRAILING <=0;
CONF_EN_INVERT <=0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
CONF_EXT_TIMESTAMP <=BUS_DATA_IN[1];
CONF_EXT_ENABLE <=BUS_DATA_IN[2];
CONF_EN_TRAILING <=BUS_DATA_IN[3];
CONF_EN_INVERT <=BUS_DATA_IN[4];
end
end
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {3'b0,CONF_EN_INVERT,
CONF_EN_TRAILING,CONF_EXT_ENABLE,CONF_EXT_TIMESTAMP,CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(CLK40), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire EN_SYNC;
assign EN_SYNC= CONF_EN | ( EXT_ENABLE & CONF_EXT_ENABLE);
reg [7:0] sync_cnt;
always@(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
reg [63:0] INT_TIMESTAMP;
wire [63:0] TIMESTAMP;
always@(posedge CLK40) begin
if(RST_SYNC)
INT_TIMESTAMP <= 0;
else
INT_TIMESTAMP <= INT_TIMESTAMP + 1;
end
assign TIMESTAMP = CONF_EXT_TIMESTAMP ? EXT_TIMESTAMP: INT_TIMESTAMP;
// de-serialize
wire [CLKDV*4-1:0] TDC, TDC_DES;
reg [CLKDV*4-1:0] TDC_DES_PREV;
ddr_des #(.CLKDV(CLKDV)) iddr_des_tdc(.CLK2X(CLK320), .CLK(CLK160), .WCLK(CLK40), .IN(DI), .OUT(TDC), .OUT_FAST());
assign TDC_DES = CONF_EN_INVERT ? ~TDC : TDC;
always @ (posedge CLK40)
TDC_DES_PREV <= TDC_DES;
wire [CLKDV*4:0] TDC_TO_COUNT;
assign TDC_TO_COUNT[CLKDV*4] = TDC_DES_PREV[0];
assign TDC_TO_COUNT[CLKDV*4-1:0] = TDC_DES;
reg [3:0] RISING_EDGES_CNT, FALLING_EDGES_CNT;
reg [3:0] RISING_POS, FALLING_POS;
integer i;
always @ (*) begin
FALLING_EDGES_CNT = 0;
RISING_EDGES_CNT = 0;
RISING_POS = 0;
FALLING_POS = 0;
for (i=0; i<16; i=i+1) begin
if ((TDC_TO_COUNT[16-i-1] == 1) && (TDC_TO_COUNT[16-i]==0)) begin
if (RISING_EDGES_CNT == 0)
RISING_POS = i;
RISING_EDGES_CNT = RISING_EDGES_CNT + 1;
end
if ((TDC_TO_COUNT[i] == 0) && (TDC_TO_COUNT[i+1]==1)) begin
if (FALLING_EDGES_CNT == 0)
FALLING_POS = 15 - i;
FALLING_EDGES_CNT = FALLING_EDGES_CNT + 1;
end
end
end
reg WAITING_FOR_TRAILING;
always@(posedge CLK40)
if(RST)
WAITING_FOR_TRAILING <= 0;
else if(RISING_EDGES_CNT < FALLING_EDGES_CNT)
WAITING_FOR_TRAILING <= 0;
else if( (RISING_EDGES_CNT > FALLING_EDGES_CNT) & EN_SYNC)
WAITING_FOR_TRAILING <= 1;
reg [67:0] LAST_RISING;
always@(posedge CLK40)
if(RST)
LAST_RISING <= 0;
else if (RISING_EDGES_CNT > 0 )
LAST_RISING <= {TIMESTAMP, RISING_POS};
reg [67:0] LAST_FALLING;
always@(posedge CLK40)
if(RST)
LAST_FALLING <= 0;
else if (FALLING_EDGES_CNT > 0)
LAST_FALLING <= {TIMESTAMP, FALLING_POS};
wire RISING;
assign RISING = (RISING_EDGES_CNT > 0 & EN_SYNC );
wire FALLING;
assign FALLING = (FALLING_EDGES_CNT > 0 & CONF_EN_TRAILING & EN_SYNC );
reg [2:0] FALLING_FF;
reg [2:0] RISING_FF;
wire FALLING_SYNC;
wire RISING_SYNC;
always@(posedge CLK40)
if(RST) begin
FALLING_FF <= 3'b0;
RISING_FF <= 3'b0;
end
else begin
FALLING_FF <= {FALLING_FF[1:0], FALLING};
RISING_FF <= {RISING_FF[1:0], RISING};
end
assign RISING_SYNC = RISING_FF[0] & ~RISING_FF[1];
assign FALLING_SYNC = FALLING_FF[0] & ~FALLING_FF[1];
wire [71:0] cdc_data_in;
assign cdc_data_in = {4'b0,LAST_RISING} ;
wire [71:0] cdc_data_in_f;
assign cdc_data_in_f = {4'b0,LAST_FALLING} ;
wire cdc_fifo_write;
assign cdc_fifo_write = RISING_SYNC ;
wire cdc_fifo_write_f;
assign cdc_fifo_write_f = CONF_EN_TRAILING ? FALLING_SYNC: 1'b0;
wire fifo_full,fifo_write,cdc_fifo_empty;
wire fifo_full_f,fifo_write_f,cdc_fifo_empty_f;
wire wfull,wfull_f;
always@(posedge CLK40) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
else if (wfull_f && cdc_fifo_write_f && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
end
////////////// write fifo (rising)
wire [71:0] cdc_data_out;
wire cdc_fifo_read;
cdc_syncfifo
#(.DSIZE(72), .ASIZE(8))
cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data_in),
.winc(cdc_fifo_write), .wclk(CLK40), .wrst(RST_LONG),
.rinc(cdc_fifo_read), .rclk(BUS_CLK), .rrst(RST_LONG)
);
reg [1:0] byte2_cnt, byte2_cnt_prev;
always@(posedge BUS_CLK)
byte2_cnt_prev <= byte2_cnt;
assign cdc_fifo_read = (byte2_cnt_prev==0 & byte2_cnt!=0);
assign fifo_write = byte2_cnt_prev != 0;
always@(posedge BUS_CLK)
if(RST)
byte2_cnt <= 0;
else if(!cdc_fifo_empty && !fifo_full && byte2_cnt == 0 )
byte2_cnt <= 3;
else if (!fifo_full & byte2_cnt != 0)
byte2_cnt <= byte2_cnt - 1;
reg [71:0] data_buf;
always@(posedge BUS_CLK)
if(cdc_fifo_read)
data_buf <= cdc_data_out;
wire [31:0] fifo_write_data_byte [3:0];
assign fifo_write_data_byte[0]={IDENTIFIER,4'b0001,data_buf[23:0]};
assign fifo_write_data_byte[1]={IDENTIFIER,4'b0010,data_buf[47:24]};
assign fifo_write_data_byte[2]={IDENTIFIER,4'b0011,data_buf[71:48]};
wire [31:0] fifo_data_in;
assign fifo_data_in = fifo_write_data_byte[byte2_cnt];
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(fifo_write),
.read(FIFO_READ),
.data_in(fifo_data_in),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]), .size()
);
////////////// write fifo (falling)
wire [71:0] cdc_data_out_f;
wire cdc_fifo_read_f;
cdc_syncfifo
#(.DSIZE(72), .ASIZE(8))
cdc_syncfifo_i_f
(
.rdata(cdc_data_out_f),
.wfull(wfull_f),
.rempty(cdc_fifo_empty_f),
.wdata(cdc_data_in_f),
.winc(cdc_fifo_write_f), .wclk(CLK40), .wrst(RST_LONG),
.rinc(cdc_fifo_read_f), .rclk(BUS_CLK), .rrst(RST_LONG)
);
reg [1:0] byte2_cnt_f, byte2_cnt_prev_f;
always@(posedge BUS_CLK)
byte2_cnt_prev_f <= byte2_cnt_f;
assign cdc_fifo_read_f = (byte2_cnt_prev_f==0 & byte2_cnt_f!=0);
assign fifo_write_f = byte2_cnt_prev_f != 0;
always@(posedge BUS_CLK)
if(RST)
byte2_cnt_f <= 0;
else if(!cdc_fifo_empty_f && !fifo_full_f && byte2_cnt_f == 0 )
byte2_cnt_f <= 3;
else if (!fifo_full_f & byte2_cnt_f != 0)
byte2_cnt_f <= byte2_cnt_f - 1;
reg [71:0] data_buf_f;
always@(posedge BUS_CLK)
if(cdc_fifo_read_f)
data_buf_f <= cdc_data_out_f;
wire [31:0] fifo_write_data_byte_f [3:0];
assign fifo_write_data_byte_f[0]={IDENTIFIER,4'b0101,data_buf_f[23:0]};
assign fifo_write_data_byte_f[1]={IDENTIFIER,4'b0110,data_buf_f[47:24]};
assign fifo_write_data_byte_f[2]={IDENTIFIER,4'b0111,data_buf_f[71:48]};
wire [31:0] fifo_data_in_f;
assign fifo_data_in_f = fifo_write_data_byte_f[byte2_cnt_f];
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i_f
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(fifo_write_f),
.read(FIFO_READ_TRAILING),
.data_in(fifo_data_in_f),
.full(fifo_full_f),
.empty(FIFO_EMPTY_TRAILING),
.data_out(FIFO_DATA_TRAILING[31:0]), .size()
);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97 #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* Codec interface */
input ac97_sin,
output ac97_sout,
output ac97_sync,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Interrupts */
output crrequest_irq,
output crreply_irq,
output dmar_irq,
output dmaw_irq,
/* DMA */
output [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o
);
wire up_stb;
wire up_ack;
wire up_sync;
wire up_sdata;
wire down_ready;
wire down_stb;
wire down_sync;
wire down_sdata;
ac97_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ac97_clk(ac97_clk),
.ac97_rst_n(ac97_rst_n),
.ac97_sin(ac97_sin),
.ac97_sout(ac97_sout),
.ac97_sync(ac97_sync),
.up_stb(up_stb),
.up_ack(up_ack),
.up_sync(up_sync),
.up_data(up_sdata),
.down_ready(down_ready),
.down_stb(down_stb),
.down_sync(down_sync),
.down_data(down_sdata)
);
wire down_en;
wire down_next_frame;
wire down_addr_valid;
wire [19:0] down_addr;
wire down_data_valid;
wire [19:0] down_data;
wire down_pcmleft_valid;
wire [19:0] down_pcmleft;
wire down_pcmright_valid;
wire [19:0] down_pcmright;
ac97_framer framer(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
/* to transceiver */
.down_ready(down_ready),
.down_stb(down_stb),
.down_sync(down_sync),
.down_data(down_sdata),
/* frame data */
.en(down_en),
.next_frame(down_next_frame),
.addr_valid(down_addr_valid),
.addr(down_addr),
.data_valid(down_data_valid),
.data(down_data),
.pcmleft_valid(down_pcmleft_valid),
.pcmleft(down_pcmleft),
.pcmright_valid(down_pcmright_valid),
.pcmright(down_pcmright)
);
wire up_en;
wire up_next_frame;
wire up_frame_valid;
wire up_addr_valid;
wire [19:0] up_addr;
wire up_data_valid;
wire [19:0] up_data;
wire up_pcmleft_valid;
wire [19:0] up_pcmleft;
wire up_pcmright_valid;
wire [19:0] up_pcmright;
ac97_deframer deframer(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.up_stb(up_stb),
.up_ack(up_ack),
.up_sync(up_sync),
.up_data(up_sdata),
.en(up_en),
.next_frame(up_next_frame),
.frame_valid(up_frame_valid),
.addr_valid(up_addr_valid),
.addr(up_addr),
.data_valid(up_data_valid),
.data(up_data),
.pcmleft_valid(up_pcmleft_valid),
.pcmleft(up_pcmleft),
.pcmright_valid(up_pcmright_valid),
.pcmright(up_pcmright)
);
wire dmar_en;
wire [29:0] dmar_addr;
wire [15:0] dmar_remaining;
wire dmar_next;
wire dmaw_en;
wire [29:0] dmaw_addr;
wire [15:0] dmaw_remaining;
wire dmaw_next;
ac97_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.crrequest_irq(crrequest_irq),
.crreply_irq(crreply_irq),
.dmar_irq(dmar_irq),
.dmaw_irq(dmaw_irq),
.down_en(down_en),
.down_next_frame(down_next_frame),
.down_addr_valid(down_addr_valid),
.down_addr(down_addr),
.down_data_valid(down_data_valid),
.down_data(down_data),
.up_en(up_en),
.up_next_frame(up_next_frame),
.up_frame_valid(up_frame_valid),
.up_addr_valid(up_addr_valid),
.up_addr(up_addr),
.up_data_valid(up_data_valid),
.up_data(up_data),
.dmar_en(dmar_en),
.dmar_addr(dmar_addr),
.dmar_remaining(dmar_remaining),
.dmar_next(dmar_next),
.dmaw_en(dmaw_en),
.dmaw_addr(dmaw_addr),
.dmaw_remaining(dmaw_remaining),
.dmaw_next(dmaw_next)
);
ac97_dma dma(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wbm_adr_o(wbm_adr_o),
.wbm_cti_o(wbm_cti_o),
.wbm_we_o(wbm_we_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.down_en(down_en),
.down_next_frame(down_next_frame),
.down_pcmleft_valid(down_pcmleft_valid),
.down_pcmleft(down_pcmleft),
.down_pcmright_valid(down_pcmright_valid),
.down_pcmright(down_pcmright),
.up_en(up_en),
.up_next_frame(up_next_frame),
.up_frame_valid(up_frame_valid),
.up_pcmleft_valid(up_pcmleft_valid),
.up_pcmleft(up_pcmleft),
.up_pcmright_valid(up_pcmright_valid),
.up_pcmright(up_pcmright),
.dmar_en(dmar_en),
.dmar_addr(dmar_addr),
.dmar_remaining(dmar_remaining),
.dmar_next(dmar_next),
.dmaw_en(dmaw_en),
.dmaw_addr(dmaw_addr),
.dmaw_remaining(dmaw_remaining),
.dmaw_next(dmaw_next)
);
endmodule
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ([email protected])
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: mem_ctrl.v (tranlate from mem_ctrl.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ([email protected])
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from mem_ctrl.vhd
// 2004/10/27 yfchen 1.2 minor coding style change
// 2004/10/29 yfchen 1.3 fix mem_byte_sel bug when read
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Memory Controller
// AUTHOR: Steve Rhoads ([email protected])
// DATE CREATED: 1/31/01
// FILENAME: mem_ctrl.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Memory controller for the Plasma CPU.
// Supports Big or Little Endian mode.
// Four cycles for a write unless a(31)='1' then two cycles.
// This entity could implement interfaces to:
// Data cache
// Address cache
// Memory management unit (MMU)
// DRAM controller
//-------------------------------------------------------------------
`include "yf32_define.v"
module mem_ctrl (clk, reset, pause_in, nullify_op, address_pc, opcode_out,
address_data, mem_source, data_write, data_read, pause_out,
mem_address, mem_data_w, mem_data_r, mem_byte_sel, mem_write,address_next_out);
parameter ACCURATE_TIMING = 1'b0;
parameter STATE_FETCH = 2'b00;
parameter STATE_ADDR = 2'b01;
parameter STATE_WRITE = 2'b10;
parameter STATE_PAUSE = 2'b11;
input clk;
input reset;
input pause_in;
input nullify_op;
input [31:0] address_pc;
input [31:0] address_data;
input [ 3:0] mem_source;
input [31:0] data_write;
input [31:0] mem_data_r;
output [31:0] opcode_out;
output [31:0] data_read;
output pause_out;
output [31:0] mem_address;
output [31:0] mem_data_w;
output [ 3:0] mem_byte_sel;
output mem_write;
output [31:0] address_next_out;
wire [ 1:0] little_endian = `mem_byte_ordering;
reg [31:0] opcode_out;
reg [31:0] data_read;
reg pause_out;
reg [31:0] mem_address;
reg [31:0] mem_data_w;
reg [ 3:0] mem_byte_sel;
reg mem_write;
reg [31:0] opcode_reg;
reg [31:0] next_opcode_reg;
reg [ 1:0] mem_state_reg;
//ACCURATE_TIMING notes:
//The VHDL compiler's timing calculation isn't able to realize that
//memory reads take two clock cycles. It notices that reg_bank:reg_dest
//is dependent on mem_ctrl:mem_data_r which is dependent on
//mem_ctrl:mem_address which is dependent on alu:c_alu. However,
//this dependency is only true for memory read or write cycles
//which are multiple clock cycles. Enabling ACCURATE_TIMING
//creates an additional 32-bit register that does nothing other
//than letting the VHDL compiler accurately predict the maximum
//clock speed.
reg [31:0] address_reg;
reg write_reg;
reg [ 3:0] byte_sel_reg;
reg [ 1:0] mem_state_next_sig;
reg [31:0] opcode_next_sig;
reg write_next_sig;
reg [ 3:0] byte_sel_next_sig;
reg [31:0] data;
reg [31:0] opcode_next;
reg [ 3:0] byte_sel_next;
reg [ 3:0] byte_sel;
reg write_next;
reg write_line;
reg [ 1:0] mem_state_next;
reg pause;
reg [31:0] address;
reg [ 1:0] bits;
reg [31:0] mem_data_w_v;
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_state_reg <= STATE_FETCH ;
opcode_reg <= `ZERO ;
next_opcode_reg <= `ZERO ;
end else begin
mem_state_reg <= mem_state_next_sig ;
opcode_reg <= opcode_next_sig ;
if (mem_state_reg == STATE_FETCH)
next_opcode_reg <= mem_data_r ;
end
end
`ifdef ACCURATE_TIMING
always @(posedge clk or posedge reset)
begin
if (reset) begin
address_reg <= 0;
write_reg <= 0;
byte_sel_reg <= 0;
else begin
address_reg <= address_data ;
write_reg <= write_next_sig ;
byte_sel_reg <= byte_sel_next_sig ;
end
end
`else
always @(address_data or write_next_sig or byte_sel_next_sig)
begin
address_reg = address_data ;
write_reg = write_next_sig ;
byte_sel_reg = byte_sel_next_sig ;
end
`endif
always @(reset or pause_in or nullify_op or address_pc or address_data or
mem_source or data_write or mem_data_r or opcode_reg or
next_opcode_reg or mem_state_reg or address_reg or write_reg or
byte_sel_reg or little_endian)
begin
byte_sel_next = 4'b0000;
write_next = 1'b0;
pause = 1'b0;
mem_state_next = mem_state_reg;
data = `ZERO;
mem_data_w_v = `ZERO;
case (mem_source) // synopsys parallel_case
`mem_read32 :
begin
data = mem_data_r;
byte_sel_next = 4'b1111; // yfchen modified
end
`mem_read16, `mem_read16s :
begin
if (address_reg[1] == little_endian[1]) begin
data[15:0] = mem_data_r[31:16];
byte_sel_next = 4'b1100; // yfchen modified
end else begin
data[15:0] = mem_data_r[15:0];
byte_sel_next = 4'b0011; // yfchen modified
end
if (mem_source == `mem_read16 | ~data[15]) begin
data[31:16] = 16'h0000; //`ZERO[31:16];
end else begin
data[31:16] = 16'hFFFF; //`ONES[31:16];
end
end
`mem_read8, `mem_read8s :
begin
bits = address_reg[1:0] ^ little_endian;
case (bits) // synopsys parallel_case
2'b00 : data[7:0] = mem_data_r[31:24];
2'b01 : data[7:0] = mem_data_r[23:16];
2'b10 : data[7:0] = mem_data_r[15: 8];
default: data[7:0] = mem_data_r[ 7: 0];
endcase
if (mem_source == `mem_read8 | ~data[7]) begin
data[31:8] = 24'h000000; //`ZERO[31:8];
end else begin
data[31:8] = 24'hffffff; //`ONES[31:8];
end
case (bits) // yfchen modified
2'b00 : byte_sel_next = 4'b1000;
2'b01 : byte_sel_next = 4'b0100;
2'b10 : byte_sel_next = 4'b0010;
default : byte_sel_next = 4'b0001;
endcase
end
`mem_write32 :
begin
write_next = 1'b1;
mem_data_w_v = data_write;
byte_sel_next = 4'b1111;
end
`mem_write16 :
begin
write_next = 1'b1;
mem_data_w_v = {data_write[15:0], data_write[15:0]};
if (address_data[1] == little_endian[1]) begin
byte_sel_next = 4'b1100;
end else begin
byte_sel_next = 4'b0011;
end
end
`mem_write8 :
begin
write_next = 1'b1;
mem_data_w_v = {data_write[7:0], data_write[7:0],
data_write[7:0], data_write[7:0]};
bits = address_data[1:0] ^ little_endian;
case (bits)
2'b00 : byte_sel_next = 4'b1000;
2'b01 : byte_sel_next = 4'b0100;
2'b10 : byte_sel_next = 4'b0010;
default : byte_sel_next = 4'b0001;
endcase
end
default :
begin
end
endcase
byte_sel_next_sig <= byte_sel_next ;
write_next_sig <= write_next ;
opcode_next = opcode_reg;
case (mem_state_reg) // synopsys parallel_case
//State Machine
STATE_FETCH :
begin
address = address_pc;
write_line = 1'b0;
byte_sel = 4'b0000;
// mem_state_next = STATE_ADDR;
// opcode_next = mem_data_r;
if (mem_source == `mem_fetch) begin
//opcode fetch
mem_state_next = STATE_FETCH;
if (~pause_in)
opcode_next = mem_data_r;
end else begin
//memory read or write
pause = 1'b1;
if (~pause_in)
mem_state_next = STATE_ADDR;
end
end
STATE_ADDR :
begin
//address lines pre-hold
address = address_reg;
write_line = write_reg;
if (write_reg & address_reg[31])
begin
pause = 1'b1;
byte_sel = 4'b0000;
if (pause_in == 1'b0) begin
mem_state_next = STATE_WRITE; //4 cycle access
end
end else begin
byte_sel = byte_sel_reg;
if (~pause_in) begin
opcode_next = next_opcode_reg;
mem_state_next = STATE_FETCH; //2 cycle access
end
end
end
STATE_WRITE :
begin
pause = 1'b1;
address = address_reg;
write_line = write_reg;
byte_sel = byte_sel_reg;
if (~pause_in) begin
mem_state_next = STATE_PAUSE;
end
end
default :
begin
//STATE_PAUSE address lines post-hold
address = address_reg;
write_line = write_reg;
byte_sel = 4'b0000;
if (~pause_in) begin
opcode_next = next_opcode_reg;
mem_state_next = STATE_FETCH;
end
end
endcase
if (nullify_op & ~pause_in)
opcode_next = `ZERO; //NOP after beql
mem_state_next_sig <= mem_state_next;
opcode_next_sig <= opcode_next;
if (reset) write_line = 1'b0;
opcode_out <= opcode_reg;
data_read <= data;
pause_out <= pause;
mem_byte_sel <= byte_sel;
mem_address <= address;
mem_write <= write_line;
mem_data_w <= mem_data_w_v ;
//`ifdef mem_dat_w_TRISTATE
// if (~write_line)
// mem_data_w <= `HIGH_Z ; //ZERO;
//`endif
end //data_proc
assign address_next_out = address_reg;
endmodule
|
// vim: ts=4 sw=4 noexpandtab
/*
* Profibus PHY
*
* Copyright (c) 2019 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`ifndef PROFIBUS_PHY_MOD_V_
`define PROFIBUS_PHY_MOD_V_
`include "uart_mod.v"
`include "spi_slave_mod.v"
`include "block_ram_mod.v"
/* Host SPI message format:
*
* Data message master to slave:
* Byte 0 1 2...
* [0xAA] [FLG] [DATA] ...
* | | |
* | | |> from 1 up to 255 Profibus telegram bytes
* | |> Flags
* |> Start of message magic constant
*
* Data message slave to master:
* Byte 0 1 2 ... 9 10
* [0x55] [FLG] [DATA0] ... [DATA7] [LEN]
* | | | |
* | | | |> Number of DATA bytes
* | | |> from 1 up to 8 Profibus telegram bytes
* | |> Flags
* |> Start of message magic constant
*
* Control message:
* Byte 0 1 2 3 4 5 6 7
* [MAGC] [FLG] [CTRL] [DATA0] [DATA1] [DATA2] [DATA3] [CRC]
* | | | | | | | |
* | | | | | | | |> CRC-8
* | | | | | | |> Control data byte 3 (LSB)
* | | | | | |> Control data byte 2
* | | | | |> Control data byte 1
* | | | |> Control data byte 0 (MSB)
* | | |> Control identifier
* | |> Flags
* |> Start of message magic constant.
* 0xAA if master to slave.
* 0x55 if slave to master.
*
* FLG: bit 7: odd parity of FLG bits 0-6
* FLG: bit 6: unused (set to 0)
* FLG: bit 5: unused (set to 0)
* FLG: bit 4: unused (set to 0)
* FLG: bit 3: A reset occurred. Get STATUS to see details.
* FLG: bit 2: New STATUS available
* FLG: bit 1: Control message
* FLG: bit 0: Start of telegram
*
* CRC polynomial: x^8 + x^2 + x^1 + 1
*
* Padding byte: 0x00
*/
module profibus_telegram_length (
input clk,
input n_reset,
input [7:0] in_byte,
input new_byte,
output reg length_valid,
output reg [7:0] length,
output reg error,
);
localparam STATE_START = 0;
localparam STATE_LE = 1;
localparam STATE_LER = 2;
localparam SD1 = 8'h10;
localparam SD2 = 8'h68;
localparam SD3 = 8'hA2;
localparam SD4 = 8'hDC;
localparam SC = 8'hE5;
reg [7:0] byte_le;
reg [1:0] state;
initial begin
length_valid <= 0;
length <= 0;
error <= 0;
byte_le <= 0;
state <= STATE_START;
end
always @(posedge clk) begin
if (n_reset) begin
case (state)
STATE_START: begin
if (new_byte) begin
if (in_byte == SD1) begin
length <= 6;
error <= 0;
length_valid <= 1;
end else if (in_byte == SD2) begin
length <= 0;
error <= 0;
length_valid <= 0;
state <= STATE_LE;
end else if (in_byte == SD3) begin
length <= 14;
error <= 0;
length_valid <= 1;
end else if (in_byte == SD4) begin
length <= 3;
error <= 0;
length_valid <= 1;
end else if (in_byte == SC) begin
length <= 1;
error <= 0;
length_valid <= 1;
end else begin
length <= 0;
error <= 1;
length_valid <= 0;
end
end
end
STATE_LE: begin
if (new_byte) begin
if (in_byte >= 4 && in_byte <= 249) begin
byte_le <= in_byte;
state <= STATE_LER;
end else begin
error <= 1;
length_valid <= 0;
state <= STATE_START;
end
end
end
STATE_LER: begin
if (new_byte) begin
if (in_byte == byte_le) begin
length <= byte_le + 6;
error <= 0;
length_valid <= 1;
state <= STATE_START;
end else begin
error <= 1;
length_valid <= 0;
state <= STATE_START;
end
end
end
default: begin
length_valid <= 0;
length <= 0;
error <= 0;
byte_le <= 0;
state <= STATE_START;
end
endcase
end else begin
/* Reset */
length_valid <= 0;
length <= 0;
error <= 0;
byte_le <= 0;
state <= STATE_START;
end
end
endmodule
module profibus_phy #(
parameter SPI_CPOL = 0, /* SPI clock polarity. Can be 0 or 1. */
parameter SPI_CPHA = 0, /* SPI clock phase. Can be 0 or 1. */
parameter SPI_MSB_FIRST = 1, /* MSB transmit first enable. Can be 0 or 1. */
) (
input clk, /* clock */
input n_reset, /* Not reset */
/* Host parallel interface: */
output rx_irq_edge, /* Received data available (edge trigger) */
output rx_irq_level, /* Received data available (level trigger) */
/* Host SPI bus interface: */
input mosi, /* SPI bus MOSI signal */
output miso, /* SPI bus MISO signal */
input sck, /* SPI bus clock signal */
input ss, /* SPI bus slave select signal */
/* Profibus RS485 bus: */
input rx, /* Raw receive signal line */
output rx_active, /* PB receive in progress (optional) */
output rx_error, /* PB receive error (optional) */
output tx, /* Raw transmit signal line */
output tx_active, /* PB transmit in progress (optional) */
output tx_error, /* PB transmit error (optional) */
`ifdef DEBUG
/* Debug interface: */
output reg debug,
`endif
);
`include "parity_func.v"
`include "crc8_func.v"
localparam TXBUF_ADDR_BITS = 8;
localparam RXBUF_ADDR_BITS = 8;
/* Start of SPI message magic constant. */
localparam SPI_MS_MAGIC = 8'hAA; /* Master to slave */
localparam SPI_SM_MAGIC = 8'h55; /* Slave to master */
/* SPI message FLG bits */
localparam SPI_FLG_START = 0;
localparam SPI_FLG_CTRL = 1;
localparam SPI_FLG_NEWSTAT = 2;
localparam SPI_FLG_RESET = 3;
localparam SPI_FLG_UNUSED4 = 4;
localparam SPI_FLG_UNUSED5 = 5;
localparam SPI_FLG_UNUSED6 = 6;
localparam SPI_FLG_PARITY = 7;
/* SPI control message IDs. */
localparam SPICTRL_NOP = 0;
localparam SPICTRL_PING = 1;
localparam SPICTRL_PONG = 2;
localparam SPICTRL_SOFTRESET = 3;
localparam SPICTRL_GETSTATUS = 4;
localparam SPICTRL_STATUS = 5;
localparam SPICTRL_GETBAUD = 6;
localparam SPICTRL_BAUD = 7;
/* Status message data bits */
localparam SPISTAT_PONRESET = 0;
localparam SPISTAT_HARDRESET = 1;
localparam SPISTAT_SOFTRESET = 2;
localparam SPISTAT_TXOVR = 3;
localparam SPISTAT_RXOVR = 4;
localparam SPISTAT_CTRLCRCERR = 5;
/***********************************************************/
/* General part */
/***********************************************************/
/* Power-on-reset, hard-reset and soft-reset status. */
reg n_poweronreset_status;
reg n_hardreset_status;
reg softreset_status;
/* Soft-reset trigger. */
reg softreset;
wire any_reset_status;
assign any_reset_status = ~n_poweronreset_status | ~n_hardreset_status | softreset_status;
/* SPICTRL_STATUS should be fetched, if 1. */
wire new_status_available;
assign new_status_available = any_reset_status | tx_buf_overflow_get() |
rx_buf_overflow_get() | spirx_ctrl_crcerr_get();
initial begin
n_poweronreset_status <= 0;
n_hardreset_status <= 0;
softreset_status <= 0;
softreset <= 0;
end
/***********************************************************/
/* Data buffer: Profibus transmit buffer */
/***********************************************************/
reg [TXBUF_ADDR_BITS - 1 : 0] tx_buf_wr_addr;
wire [TXBUF_ADDR_BITS - 1 : 0] tx_buf_wr_addr_next;
reg [7:0] tx_buf_wr_data;
reg tx_buf_wr;
reg [TXBUF_ADDR_BITS - 1 : 0] tx_buf_rd_addr;
wire [7:0] tx_buf_rd_data;
reg [1:0] tx_buf_overflow;
block_ram #(
.ADDR_WIDTH(TXBUF_ADDR_BITS),
.DATA_WIDTH(8),
.MEM_BYTES(1 << TXBUF_ADDR_BITS),
) tx_buf (
.clk(clk),
.addr0(tx_buf_wr_addr),
.wr_data0(tx_buf_wr_data),
.wr0(tx_buf_wr),
.addr1(tx_buf_rd_addr),
.rd_data1(tx_buf_rd_data),
);
assign tx_buf_wr_addr_next = tx_buf_wr_addr + 1;
initial begin
tx_buf_wr_addr <= 0;
tx_buf_wr_data <= 0;
tx_buf_wr <= 0;
tx_buf_rd_addr <= 0;
tx_buf_overflow <= 0;
end
function automatic tx_buf_overflow_get;
begin tx_buf_overflow_get = tx_buf_overflow[0] ^ tx_buf_overflow[1]; end
endfunction
task automatic tx_buf_overflow_set;
begin tx_buf_overflow[0] <= ~tx_buf_overflow[1]; end
endtask
task automatic tx_buf_overflow_reset;
begin tx_buf_overflow[1] <= tx_buf_overflow[0]; end
endtask
/***********************************************************/
/* Data buffer: Profibus receive buffer */
/***********************************************************/
localparam RXBUF_SOT_BIT = 8; /* Start-of-telegram marker bit. */
reg [RXBUF_ADDR_BITS - 1 : 0] rx_buf_wr_addr;
wire [RXBUF_ADDR_BITS - 1 : 0] rx_buf_wr_addr_next;
reg [8:0] rx_buf_wr_data;
reg rx_buf_wr;
reg [RXBUF_ADDR_BITS - 1 : 0] rx_buf_rd_addr;
wire [8:0] rx_buf_rd_data;
reg [1:0] rx_buf_overflow;
block_ram #(
.ADDR_WIDTH(RXBUF_ADDR_BITS),
.DATA_WIDTH(9),
.MEM_BYTES(1 << RXBUF_ADDR_BITS),
) rx_buf (
.clk(clk),
.addr0(rx_buf_wr_addr),
.wr_data0(rx_buf_wr_data),
.wr0(rx_buf_wr),
.addr1(rx_buf_rd_addr),
.rd_data1(rx_buf_rd_data),
);
assign rx_buf_wr_addr_next = rx_buf_wr_addr + 1;
initial begin
rx_buf_wr_addr <= 0;
rx_buf_wr_data <= 0;
rx_buf_wr <= 0;
rx_buf_rd_addr <= 0;
rx_buf_overflow <= 0;
end
function automatic rx_buf_overflow_get;
begin rx_buf_overflow_get = rx_buf_overflow[0] ^ rx_buf_overflow[1]; end
endfunction
task automatic rx_buf_overflow_set;
begin rx_buf_overflow[0] <= ~rx_buf_overflow[1]; end
endtask
task automatic rx_buf_overflow_reset;
begin rx_buf_overflow[1] <= rx_buf_overflow[0]; end
endtask
/***********************************************************/
/* UART module */
/***********************************************************/
wire uart_rx_irq;
wire [7:0] uart_rx_data;
wire uart_rx_parity_ok;
wire uart_rx_frame_error;
wire uart_rx_active;
wire uart_tx_irq;
wire uart_tx_active;
wire uart_tx_pending;
reg [7:0] uart_tx_data;
reg uart_tx_trigger;
reg [23:0] uart_clks_per_sym;
uart_half_duplex #(
.DATABITS(8),
.PARITY_EVEN(1),
.STOP(1),
.ACTIVE_LOW(0),
) uart (
.clk(clk),
.n_reset(n_reset),
.clks_per_sym(uart_clks_per_sym),
.rx(rx),
.rx_irq(uart_rx_irq),
.rx_active(uart_rx_active),
.rx_data(uart_rx_data),
.rx_parity_ok(uart_rx_parity_ok),
.rx_frame_error(uart_rx_frame_error),
.tx(tx),
.tx_irq(uart_tx_irq),
.tx_active(uart_tx_active),
.tx_pending(uart_tx_pending),
.tx_data(uart_tx_data),
.tx_trigger(uart_tx_trigger),
);
assign rx_active = uart_rx_active;
assign rx_error = ~uart_rx_parity_ok | uart_rx_frame_error;
assign tx_active = uart_tx_active;
assign tx_error = spirx_lencalc_error;
initial begin
uart_tx_data <= 0;
uart_tx_trigger <= 0;
uart_clks_per_sym <= 0;
end
/***********************************************************/
/* SPI module */
/***********************************************************/
wire spi_rx_irq;
wire spi_tx_irq;
wire [7:0] spi_rx_data;
reg [7:0] spi_tx_data;
spi_slave #(
.WORDSIZE(8),
.CPOL(SPI_CPOL),
.CPHA(SPI_CPHA),
.MSB_FIRST(SPI_MSB_FIRST),
) spi (
.clk(clk),
.mosi(mosi),
.miso(miso),
.sck(sck),
.ss(ss),
.rx_irq(spi_rx_irq),
.rx_data(spi_rx_data),
.tx_data(spi_tx_data),
);
assign spi_tx_irq = spi_rx_irq;
initial begin
spi_tx_data <= 0;
end
/***********************************************************/
/* UART receive */
/* This process receives data from the Profibus line */
/* and puts it into the Profibus receive buffer. */
/***********************************************************/
reg [23:0] tsyn_clks;
/* Receive interrupts */
assign rx_irq_edge = rx_buf_wr;
assign rx_irq_level = rx_buf_wr | (rx_buf_wr_addr != rx_buf_rd_addr);
initial begin
tsyn_clks <= 0;
end
always @(posedge clk) begin
if (n_reset & ~softreset) begin
if (uart_rx_irq) begin
if (uart_rx_parity_ok & ~uart_rx_frame_error) begin
if (rx_buf_wr_addr_next != rx_buf_rd_addr) begin
rx_buf_wr_data[7:0] <= uart_rx_data;
/* Start-of-telegram bit. */
rx_buf_wr_data[RXBUF_SOT_BIT] <= (timer_idle_saved >= tsyn_clks);
rx_buf_wr <= 1;
end else begin
/* RX buffer overflow. */
rx_buf_overflow_set();
end
end
end else begin
if (rx_buf_wr) begin
rx_buf_wr <= 0;
rx_buf_wr_addr <= rx_buf_wr_addr_next;
end
end
end else begin
/* Reset */
rx_buf_wr <= 0;
rx_buf_wr_addr <= 0;
end
end
/***********************************************************/
/* UART transmit. */
/* This process transmits data to the Profibus line */
/* from the Profibus transmit buffer. */
/***********************************************************/
always @(posedge clk) begin
if (n_reset & ~softreset) begin
if (uart_tx_trigger) begin
uart_tx_trigger <= 0;
end else begin
/* Check if new TX data is pending. */
if (tx_buf_rd_addr != tx_buf_wr_addr) begin
/* Check if we are able to transmit. */
if (~uart_tx_active & ~uart_tx_pending) begin
/* Transmit the byte to the PB line. */
uart_tx_data <= tx_buf_rd_data;
uart_tx_trigger <= 1;
tx_buf_rd_addr <= tx_buf_rd_addr + 1;
end
end
end
end else begin
/* Reset */
uart_tx_data <= 0;
uart_tx_trigger <= 0;
tx_buf_rd_addr <= 0;
end
end
/***********************************************************/
/* SPI receive. */
/* This process receives data from the host SPI bus */
/* and puts it into the Profibus transmit buffer. */
/***********************************************************/
localparam SPIRX_BEGIN = 0;
localparam SPIRX_FLG = 1;
localparam SPIRX_DATA = 2;
localparam SPIRX_CTRL = 3;
localparam SPIRX_CTRL_DATA = 4;
localparam SPIRX_CRC = 5;
localparam SPIRX_CTRL_EXEC = 6;
reg [2:0] spirx_state;
reg [7:0] spirx_len;
reg spirx_len_valid;
reg [7:0] spirx_bytecount;
reg [7:0] spirx_ctrl;
reg [31:0] spirx_ctrl_data;
reg [7:0] spirx_crc;
reg [1:0] spirx_ctrl_crcerr;
/* Length calculation of PB frames. */
wire spirx_lencalc_n_reset_wire;
reg spirx_lencalc_n_reset;
reg [7:0] spirx_lencalc_byte;
reg spirx_lencalc_new;
wire spirx_lencalc_valid;
wire [7:0] spirx_lencalc_length;
wire spirx_lencalc_error;
profibus_telegram_length spirx_lencalc (
.clk(clk),
.n_reset(spirx_lencalc_n_reset_wire),
.in_byte(spirx_lencalc_byte),
.new_byte(spirx_lencalc_new),
.length_valid(spirx_lencalc_valid),
.length(spirx_lencalc_length),
.error(spirx_lencalc_error),
);
assign spirx_lencalc_n_reset_wire = spirx_lencalc_n_reset & ~softreset & n_reset;
initial begin
spirx_state <= SPIRX_BEGIN;
spirx_len <= 0;
spirx_len_valid <= 0;
spirx_bytecount <= 0;
spirx_ctrl <= 0;
spirx_ctrl_data <= 0;
spirx_crc <= 0;
spirx_ctrl_crcerr <= 0;
spirx_lencalc_n_reset <= 0;
spirx_lencalc_byte <= 0;
spirx_lencalc_new <= 0;
end
function automatic spirx_ctrl_crcerr_get;
begin spirx_ctrl_crcerr_get = spirx_ctrl_crcerr[0] ^ spirx_ctrl_crcerr[1]; end
endfunction
task automatic spirx_ctrl_crcerr_set;
begin spirx_ctrl_crcerr[0] <= ~spirx_ctrl_crcerr[1]; end
endtask
task automatic spirx_ctrl_crcerr_reset;
begin spirx_ctrl_crcerr[1] <= spirx_ctrl_crcerr[0]; end
endtask
always @(posedge clk) begin
if (n_reset & ~softreset) begin
case (spirx_state)
SPIRX_BEGIN: begin
/* Wait for start of SPI receive. */
if (spi_rx_irq) begin
if (spi_rx_data == SPI_MS_MAGIC) begin
spirx_ctrl <= 0;
spirx_ctrl_data <= 0;
spirx_len <= 0;
spirx_len_valid <= 0;
spirx_crc <= 8'hFF;
spirx_state <= SPIRX_FLG;
end
end
if (tx_buf_wr) begin
tx_buf_wr_addr <= tx_buf_wr_addr + 1;
tx_buf_wr <= 0;
end
spirx_lencalc_byte <= 0;
spirx_lencalc_new <= 0;
spirx_lencalc_n_reset <= 0;
end
SPIRX_FLG: begin
/* Flags field. */
if (spi_rx_irq) begin
/* Check the FLG checksum. */
if (parity8(ODD,
spi_rx_data[0],
spi_rx_data[1],
spi_rx_data[2],
spi_rx_data[3],
spi_rx_data[4],
spi_rx_data[5],
spi_rx_data[6],
spi_rx_data[7]) == 0) begin
if (spi_rx_data[SPI_FLG_CTRL]) begin
/* We have a control message. */
spirx_bytecount <= 0;
spirx_state <= SPIRX_CTRL;
end else begin
/* Begin PB data. */
spirx_lencalc_n_reset <= 1;
spirx_bytecount <= 0;
spirx_state <= SPIRX_DATA;
end
end else begin
/* Incorrect checksum. */
spirx_state <= SPIRX_BEGIN;
end
end
end
SPIRX_DATA: begin
/* Receive data bytes. */
if (spirx_len_valid) begin
/* spirx_len is valid.
* Check if we received all bytes. */
if (spirx_bytecount >= spirx_len) begin
spirx_state <= SPIRX_BEGIN;
end
end else begin
/* Try to calculate the telegram length. */
spirx_lencalc_byte <= spi_rx_data;
spirx_lencalc_new <= spi_rx_irq;
if (spirx_lencalc_error) begin
/* Failed to calculate the length. Abort. */
spirx_lencalc_n_reset <= 0;
spirx_state <= SPIRX_BEGIN;
end else if (spirx_lencalc_valid) begin
/* Successfully calculated the data length. */
spirx_len <= spirx_lencalc_length;
spirx_len_valid <= 1;
spirx_lencalc_n_reset <= 0;
end
end
if (tx_buf_wr) begin
/* Increment TX buffer pointer. */
tx_buf_wr_addr <= tx_buf_wr_addr + 1;
tx_buf_wr <= 0;
end else begin
/* Did we receive a byte? */
if (spi_rx_irq) begin
if (tx_buf_wr_addr_next != tx_buf_rd_addr) begin
/* Put the new byte into the TX buffer. */
tx_buf_wr_data <= spi_rx_data;
tx_buf_wr <= 1;
spirx_bytecount <= spirx_bytecount + 1;
end else begin
/* TX buffer overflow. */
tx_buf_overflow_set();
spirx_bytecount <= spirx_bytecount + 1;
end
end
end
end
SPIRX_CTRL: begin
/* Receive control command byte. */
if (spi_rx_irq) begin
spirx_ctrl <= spi_rx_data;
spirx_crc <= crc8(spirx_crc, spi_rx_data);
spirx_state <= SPIRX_CTRL_DATA;
end
end
SPIRX_CTRL_DATA: begin
/* Receive control data bytes. */
if (spi_rx_irq) begin
spirx_ctrl_data <= (spirx_ctrl_data << 8) | spi_rx_data;
spirx_crc <= crc8(spirx_crc, spi_rx_data);
if (spirx_bytecount >= 4 - 1) begin
spirx_state <= SPIRX_CRC;
end
spirx_bytecount <= spirx_bytecount + 1;
end
end
SPIRX_CRC: begin
/* Receive CRC byte. */
if (spi_rx_irq) begin
if (spi_rx_data == spirx_crc) begin
spirx_state <= SPIRX_CTRL_EXEC;
end else begin
/* Incorrect CRC. Do not run the control command. */
spirx_ctrl_crcerr_set();
spirx_state <= SPIRX_BEGIN;
end
end
end
SPIRX_CTRL_EXEC: begin
/* Handle received control message. */
case (spirx_ctrl)
SPICTRL_NOP: begin
/* NOP command. Do nothing. */
spirx_state <= SPIRX_BEGIN;
end
SPICTRL_PING: begin
/* PING command. Send PONG. */
if (spitx_ctrl_pending == spitx_ctrl_pending_ack) begin
spitx_ctrl_reply <= SPICTRL_PONG;
spitx_ctrl_reply_data <= 0;
spitx_ctrl_pending <= ~spitx_ctrl_pending_ack;
spirx_state <= SPIRX_BEGIN;
end
end
SPICTRL_PONG: begin
/* Ignore. */
spirx_state <= SPIRX_BEGIN;
end
SPICTRL_SOFTRESET: begin
/* Trigger a soft reset. */
softreset <= 1;
spirx_state <= SPIRX_BEGIN;
end
SPICTRL_GETSTATUS: begin
if (spitx_ctrl_pending == spitx_ctrl_pending_ack) begin
spitx_ctrl_reply <= SPICTRL_STATUS;
spitx_ctrl_reply_data[SPISTAT_PONRESET] <= ~n_poweronreset_status;
spitx_ctrl_reply_data[SPISTAT_HARDRESET] <= ~n_hardreset_status;
spitx_ctrl_reply_data[SPISTAT_SOFTRESET] <= softreset_status;
spitx_ctrl_reply_data[SPISTAT_TXOVR] <= tx_buf_overflow_get();
spitx_ctrl_reply_data[SPISTAT_RXOVR] <= rx_buf_overflow_get();
spitx_ctrl_reply_data[SPISTAT_CTRLCRCERR] <= spirx_ctrl_crcerr_get();
spitx_ctrl_reply_data[31:6] <= 0;
spitx_ctrl_pending <= ~spitx_ctrl_pending_ack;
/* Reset all error states. */
tx_buf_overflow_reset();
rx_buf_overflow_reset();
spirx_ctrl_crcerr_reset();
/* Reset all reset status bits */
n_poweronreset_status <= 1;
n_hardreset_status <= 1;
softreset_status <= 0;
spirx_state <= SPIRX_BEGIN;
end
end
SPICTRL_STATUS: begin
/* Ignore. */
spirx_state <= SPIRX_BEGIN;
end
SPICTRL_GETBAUD: begin
if (spitx_ctrl_pending == spitx_ctrl_pending_ack) begin
spitx_ctrl_reply <= SPICTRL_BAUD;
spitx_ctrl_reply_data[31:24] <= 0;
spitx_ctrl_reply_data[23:0] <= spirx_ctrl_data[23:0];
spitx_ctrl_pending <= ~spitx_ctrl_pending_ack;
spirx_state <= SPIRX_BEGIN;
end
end
SPICTRL_BAUD: begin
if (spitx_ctrl_pending == spitx_ctrl_pending_ack) begin
spitx_ctrl_reply <= SPICTRL_BAUD;
spitx_ctrl_reply_data[31:24] <= 0;
spitx_ctrl_reply_data[23:0] <= spirx_ctrl_data[23:0];
spitx_ctrl_pending <= ~spitx_ctrl_pending_ack;
/* Set the new baud rate. */
uart_clks_per_sym[23:0] <= spirx_ctrl_data[23:0];
/* Set the new TSYN timing.
* The number of TSYN clks is:
* clks_per_symbol * 33
*/
tsyn_clks <= (spirx_ctrl_data[23:0] << 5) + spirx_ctrl_data[23:0];
spirx_state <= SPIRX_BEGIN;
end
end
default: begin
/* Unknown control command. */
spirx_state <= SPIRX_BEGIN;
end
endcase
end
default: begin
/* Invalid case. */
spirx_ctrl <= 0;
spirx_ctrl_data <= 0;
tx_buf_wr_addr <= 0;
tx_buf_wr_data <= 0;
tx_buf_wr <= 0;
spirx_state <= SPIRX_BEGIN;
spirx_lencalc_n_reset <= 0;
end
endcase
end else begin
/* Reset */
spirx_ctrl <= 0;
spirx_ctrl_data <= 0;
tx_buf_wr_addr <= 0;
tx_buf_wr_data <= 0;
tx_buf_wr <= 0;
spirx_state <= SPIRX_BEGIN;
spirx_lencalc_n_reset <= 0;
rx_buf_overflow_reset();
tx_buf_overflow_reset();
spirx_ctrl_crcerr_reset();
softreset_status <= softreset;
n_hardreset_status <= n_reset;
n_poweronreset_status <= 1;
softreset <= 0;
end
end
/***********************************************************/
/* SPI transmit. */
/* This process transmits data to the host SPI bus */
/* from the Profibus receive buffer. */
/***********************************************************/
reg [7:0] spitx_ctrl_reply;
reg [31:0] spitx_ctrl_reply_data;
reg spitx_ctrl_pending;
reg spitx_ctrl_pending_ack;
reg [7:0] spitx_bytecount;
reg [7:0] spitx_len;
reg spitx_tail;
reg spitx_ctrl_running;
reg spitx_data_running;
reg [7:0] spitx_crc;
initial begin
spitx_ctrl_reply <= 0;
spitx_ctrl_reply_data <= 0;
spitx_ctrl_pending <= 0;
spitx_ctrl_pending_ack <= 0;
spitx_bytecount <= 0;
spitx_len <= 0;
spitx_ctrl_running <= 0;
spitx_data_running <= 0;
spitx_crc <= 0;
end
always @(posedge clk) begin
if (n_reset & ~softreset) begin
/* Are we currently not transmitting a data frame
* and is a control frame pending? */
if (~spitx_data_running &&
spitx_ctrl_pending != spitx_ctrl_pending_ack) begin
if (spi_tx_irq) begin
case (spitx_bytecount)
0: begin
spi_tx_data <= SPI_SM_MAGIC;
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
1: begin
spi_tx_data[SPI_FLG_START] <= 0;
spi_tx_data[SPI_FLG_CTRL] <= 1;
spi_tx_data[SPI_FLG_NEWSTAT] <= new_status_available;
spi_tx_data[SPI_FLG_RESET] <= any_reset_status;
spi_tx_data[SPI_FLG_UNUSED4] <= 0;
spi_tx_data[SPI_FLG_UNUSED5] <= 0;
spi_tx_data[SPI_FLG_UNUSED6] <= 0;
spi_tx_data[SPI_FLG_PARITY] <= parity8(ODD, 0,
0,
1,
new_status_available,
any_reset_status,
0,
0,
0);
spitx_crc <= 8'hFF;
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
2: begin
spi_tx_data <= spitx_ctrl_reply;
spitx_crc <= crc8(spitx_crc, spitx_ctrl_reply);
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
3: begin
spi_tx_data <= spitx_ctrl_reply_data[31:24];
spitx_crc <= crc8(spitx_crc, spitx_ctrl_reply_data[31:24]);
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
4: begin
spi_tx_data <= spitx_ctrl_reply_data[23:16];
spitx_crc <= crc8(spitx_crc, spitx_ctrl_reply_data[23:16]);
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
5: begin
spi_tx_data <= spitx_ctrl_reply_data[15:8];
spitx_crc <= crc8(spitx_crc, spitx_ctrl_reply_data[15:8]);
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
6: begin
spi_tx_data <= spitx_ctrl_reply_data[7:0];
spitx_crc <= crc8(spitx_crc, spitx_ctrl_reply_data[7:0]);
spitx_bytecount <= spitx_bytecount + 1;
spitx_ctrl_running <= 1;
end
7: begin
spi_tx_data <= spitx_crc;
spitx_bytecount <= 0;
spitx_ctrl_running <= 0;
spitx_ctrl_pending_ack <= spitx_ctrl_pending;
end
default: begin
spitx_bytecount <= 0;
spitx_ctrl_running <= 0;
spitx_ctrl_pending_ack <= spitx_ctrl_pending;
end
endcase
end
/* Are we currently not transmitting a control frame
* and is a data frame pending? */
end else if ((~spitx_ctrl_running &&
rx_buf_wr_addr != rx_buf_rd_addr) ||
spitx_data_running) begin
if (spi_tx_irq) begin
/* We have a new PB telegram byte. Send it to the host. */
if (spitx_bytecount == 0) begin
spi_tx_data <= SPI_SM_MAGIC;
spitx_bytecount <= spitx_bytecount + 1;
spitx_len <= 0;
spitx_tail <= 0;
spitx_data_running <= 1;
end else if (spitx_bytecount == 1) begin
spi_tx_data[SPI_FLG_START] = rx_buf_rd_data[RXBUF_SOT_BIT];
spi_tx_data[SPI_FLG_CTRL] = 0;
spi_tx_data[SPI_FLG_NEWSTAT] = new_status_available;
spi_tx_data[SPI_FLG_RESET] = any_reset_status;
spi_tx_data[SPI_FLG_UNUSED4] = 0;
spi_tx_data[SPI_FLG_UNUSED5] = 0;
spi_tx_data[SPI_FLG_UNUSED6] = 0;
spi_tx_data[SPI_FLG_PARITY] = parity8(ODD, 0,
rx_buf_rd_data[RXBUF_SOT_BIT],
0,
new_status_available,
any_reset_status,
0,
0,
0);
spitx_bytecount <= spitx_bytecount + 1;
spitx_data_running <= 1;
end else if (spitx_bytecount >= 2 && spitx_bytecount <= 9) begin
if (spitx_tail ||
(rx_buf_wr_addr == rx_buf_rd_addr) ||
(spitx_bytecount >= 3 && rx_buf_rd_data[RXBUF_SOT_BIT])) begin
spi_tx_data <= 0;
spitx_bytecount <= spitx_bytecount + 1;
spitx_tail <= 1;
end else begin
spi_tx_data <= rx_buf_rd_data;
rx_buf_rd_addr <= rx_buf_rd_addr + 1;
spitx_bytecount <= spitx_bytecount + 1;
spitx_len <= spitx_len + 1;
end
spitx_data_running <= 1;
end else begin
spi_tx_data <= spitx_len;
spitx_bytecount <= 0;
spitx_data_running <= 0;
end
end
end else begin
/* No frame pending. */
if (spi_tx_irq) begin
spi_tx_data <= 0;
end
spitx_bytecount <= 0;
spitx_data_running <= 0;
spitx_ctrl_running <= 0;
end
end else begin
/* Reset. */
spi_tx_data <= 0;
spitx_bytecount <= 0;
spitx_len <= 0;
spitx_tail <= 0;
spitx_ctrl_running <= 0;
spitx_data_running <= 0;
spitx_ctrl_pending_ack <= spitx_ctrl_pending;
spitx_crc <= 0;
end
end
/***********************************************************/
/* PB timekeeping. */
/***********************************************************/
reg timer_idle_active;
reg [23:0] timer_idle;
reg [23:0] timer_idle_saved;
localparam TIMER_MAX = 24'hFFFFFF;
initial begin
timer_idle_active <= 0;
timer_idle <= 0;
timer_idle_saved <= TIMER_MAX;
end
always @(posedge clk) begin
if (n_reset & ~softreset) begin
if (uart_tx_active | uart_tx_irq |
uart_rx_active | uart_rx_irq) begin
/* A PB transmission is active. Reset idle timer. */
if (timer_idle_active) begin
timer_idle_saved <= timer_idle;
end
timer_idle_active <= 0;
timer_idle <= 0;
end else begin
/* PB is idle, increment the idle timer. Avoid overflow. */
if (timer_idle < TIMER_MAX) begin
timer_idle <= timer_idle + 1;
end
timer_idle_active <= 1;
end
end else begin
timer_idle_active <= 0;
timer_idle <= 0;
timer_idle_saved <= TIMER_MAX;
end
end
endmodule
`endif /* PROFIBUS_PHY_MOD_V_ */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND2B_PP_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O221A_FUNCTIONAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o221a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_4_V
`define SKY130_FD_SC_LP__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_TB_V
`define SKY130_FD_SC_LS__FILL_DIODE_TB_V
/**
* fill_diode: Fill diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__fill_diode dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_TB_V
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////
// Module Name: lab1_tb
/////////////////////////////////////////////////////////////////
module lab1_tb(
);
reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;
integer i;
lab1 dut(.led(leds),.swt(switches));
function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction
initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end
endmodule
|
`timescale 1 ns / 100 ps
`include "design/mips_regFile.v"
module reg_file_tb();
parameter ClockDelay = 2;
reg [4:0] rdAddr0, rdAddr1, wrAddr;
reg [31:0] wrData;
reg we, clk, rst_n, halted;
wire [31:0] rdData0, rdData1;
integer i;
mips_regFile regFile(clk, rst_n, rdAddr0, rdAddr1, we, wrAddr, wrData, halted, rdData0, rdData1);
initial begin
clk = 0;
rst_n = 1;
end
always #(ClockDelay/2) clk = ~clk;
initial
begin
$dumpfile("reg_file_tb.vcd");
$dumpvars;
#(ClockDelay);
rst_n = 0;
halted = 0;
#(ClockDelay);
rst_n = 1;
// for (i = 0; i < 32; i = i + 1) begin
// rdAddr0 = i;
// rdAddr1 = i;
// #(ClockDelay);
// end
we = 0;
rdAddr0 = 0;
rdAddr1 = 0;
wrAddr = 0;
wrData = 32'hA0;
#(ClockDelay);
we = 1;
#(ClockDelay);
we = 0;
#(ClockDelay);
for (i = 1; i < 32; i = i + 1) begin
we = 0;
rdAddr0 = i - 1;
rdAddr1 = i;
wrAddr = i;
wrData = i * 32'h01020408;
#(ClockDelay);
we = 1;
#(ClockDelay);
end
for (i = 1; i < 32; i = i + 1) begin
we = 1;
rdAddr0 = 0;
rdAddr1 = 0;
wrAddr = i;
wrData = 0;
#(ClockDelay);
end
for (i = 0; i < 32; i = i + 1) begin
we = 1;
rdAddr0 = i;
rdAddr1 = i;
wrAddr = i;
wrData = i * 32'h100 + i;
#(ClockDelay);
end
#(ClockDelay);
halted = 1;
#(ClockDelay);
rst_n = 1;
$finish;
end
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
- (* ANum *) reflexivity.
- (* APlus *) destruct a1.
+ (* a1 = ANum n *) destruct n.
* (* n = 0 *) simpl. apply IHa2.
* (* n <> 0 *) simpl. rewrite IHa2. reflexivity.
+ (* a1 = APlus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMinus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMult a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
- (* AMinus *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
- (* AMult *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
- (* n=0 *) simpl. reflexivity.
- (* n=Sn' *) simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
- (* ANum *) reflexivity.
- (* APlus *)
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
- (* APlus *)
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical also has a more general form than the simple
[T;T'] we've seen above, which is sometimes also useful. If [T],
[T1], ..., [Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
(*
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
*)
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
- (* APlus *)
destruct a1;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
+ (* ANum *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
(* FILL IN HERE *) admit.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Leibniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoint]s. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
- (* -> *)
intros H.
induction H; simpl.
+ (* E_ANum *)
reflexivity.
+ (* E_APlus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMinus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMult *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
- (* <- *)
generalize dependent n.
induction a;
simpl; intros; subst.
+ (* ANum *)
apply E_ANum.
+ (* APlus *)
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMinus *)
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMult *)
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
- (* -> *)
intros H; induction H; subst; reflexivity.
- (* <- *)
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(*
Inductive bevalR:
(* FILL IN HERE *)
*)
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (n2 > 0) ->
(mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
- (* n1 = n2 *)
left. rewrite Heq. reflexivity.
- (* n1 <> n2 *)
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
- (* x = x *)
reflexivity.
- (* x <> x (impossible) *)
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| IFB b THEN c ELSE c FI
| WHILE b DO c END
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b)
then ceval_fun st (c; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
- (* assignment command *)
apply E_Ass. reflexivity.
- (* if command *)
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
induction E1;
intros st2 E2; inversion E2; subst.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption.
- (* E_IfTrue, b1 evaluates to true *)
apply IHE1. assumption.
- (* E_IfTrue, b1 evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse, b1 evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse, b1 evaluates to false *)
apply IHE1. assumption.
- (* E_WhileEnd, b1 evaluates to false *)
reflexivity.
- (* E_WhileEnd, b1 evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
- (* E_WhileLoop, b1 evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* E_WhileLoop, b1 evaluates to true *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
compiler implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;;
Y ::= 1;;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK;; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date$ *)
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* FSM: finite state machine
* halt if $ctrl == 0$
*/
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [27:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [5:0] state;
parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
wire [5:0] dest, src1, src2; wire [7:0] times; wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
reg [7:0] count;
always @ (posedge clk)
if (reset)
state<=START;
else
case (state)
START:
state<=READ_SRC1;
READ_SRC1:
state<=READ_SRC2;
READ_SRC2:
if (times==0) state<=DON; else state<=CALC;
CALC:
if (count==1) state<=WAIT;
WAIT:
state<=WRITE;
WRITE:
state<=READ_SRC1;
endcase
/* we support two loops */
parameter LOOP1_START = 9'd21,
LOOP1_END = 9'd116,
LOOP2_START = 9'd290,
LOOP2_END = 9'd303;
reg [249:0] loop1, loop2;
always @ (posedge clk)
if (reset) rom_addr<=0;
else if (state==WAIT)
begin
if(rom_addr == LOOP1_END && loop1[0])
rom_addr <= LOOP1_START;
else if(rom_addr == LOOP2_END && loop2[0])
rom_addr <= LOOP2_START;
else
rom_addr <= rom_addr + 1'd1;
end
always @ (posedge clk)
if (reset) loop1 <= ~0;
else if(state==WAIT && rom_addr==LOOP1_END)
loop1 <= loop1 >> 1;
always @ (posedge clk)
if (reset) loop2 <= ~0;
else if(state==WAIT && rom_addr==LOOP2_END)
loop2 <= loop2 >> 1;
always @ (posedge clk)
if (reset)
count <= 0;
else if (state==READ_SRC1)
count <= times;
else if (state==CALC)
count <= count - 1'd1;
always @ (posedge clk)
if (reset) done<=0;
else if (state==DON) done<=1;
else done<=0;
always @ (state, src1, src2)
case (state)
READ_SRC1: ram_a_addr=src1;
READ_SRC2: ram_a_addr=src2;
default: ram_a_addr=0;
endcase
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @ (posedge clk)
case (state)
READ_SRC1:
case (op)
ADD: pe<=11'b11001000000;
SUB: pe<=11'b11001000000;
CUBIC: pe<=11'b11111000000;
MULT: pe<=11'b11110000000;
default: pe<=0;
endcase
READ_SRC2:
case (op)
ADD: pe<=11'b00110000000;
SUB: pe<=11'b00110000000;
CUBIC: pe<=0;
MULT: pe<=11'b00001000000;
default: pe<=0;
endcase
CALC:
case (op)
ADD: pe<=11'b00000010001;
SUB: pe<=11'b00000010001;
CUBIC: pe<=11'b01010000001;
MULT: pe<=11'b00000111111;
default: pe<=0;
endcase
default:
pe<=0;
endcase
always @ (state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr=CMD_ADD;
SUB: ram_b_addr=CMD_SUB;
CUBIC: ram_b_addr=CMD_CUBIC;
default: ram_b_addr=0;
endcase
READ_SRC2: ram_b_addr=src2;
WRITE: ram_b_addr=dest;
default: ram_b_addr=0;
endcase
assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
endmodule
|
`include "elink_constants.v"
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
// Inputs
reset, tx_lclk, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access, tx_burst
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
//###########
//# reset, clocks
//##########
input reset; //sync reset for io
input tx_lclk; //fast clock for io
input tx_lclk90; //fast 90deg shifted lclk
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [PW-1:0] tx_packet;
input tx_access;
input tx_burst;
output tx_io_wait;
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [7:0] tx_pointer;
reg [15:0] tx_data16;
reg tx_access_reg;
reg tx_frame;
reg tx_io_wait_reg;
reg [PW-1:0] tx_packet_reg;
reg [63:0] tx_double;
reg [2:0] tx_state_reg;
reg [2:0] tx_state;
//############
//# WIRES
//############
wire new_tran;
wire access;
wire write;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [7:0] txo_data;
wire txo_frame;
wire txo_lclk90;
reg tx_io_wait;
//#############################
//# Transmit state machine
//#############################
`define IDLE 3'b000
`define CYCLE1 3'b001
`define CYCLE2 3'b010
`define CYCLE3 3'b011
`define CYCLE4 3'b100
`define CYCLE5 3'b101
`define CYCLE6 3'b110
`define CYCLE7 3'b111
always @ (posedge tx_lclk)
if(reset)
tx_state[2:0] <= `IDLE;
else
case (tx_state[2:0])
`IDLE : tx_state[2:0] <= tx_access ? `CYCLE1 : `IDLE;
`CYCLE1 : tx_state[2:0] <= `CYCLE2;
`CYCLE2 : tx_state[2:0] <= `CYCLE3;
`CYCLE3 : tx_state[2:0] <= `CYCLE4;
`CYCLE4 : tx_state[2:0] <= `CYCLE5;
`CYCLE5 : tx_state[2:0] <= `CYCLE6;
`CYCLE6 : tx_state[2:0] <= `CYCLE7;
`CYCLE7 : tx_state[2:0] <= tx_burst ? `CYCLE4 : `IDLE;
endcase // case (tx_state)
assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
//Creating wait pulse for slow clock domain
always @ (posedge tx_lclk)
if(reset | ~tx_access)
tx_io_wait <= 1'b0;
else if ((tx_state[2:0] ==`CYCLE4) & ~tx_burst)
tx_io_wait <= 1'b1;
else if (tx_state[2:0]==`CYCLE7)
tx_io_wait <= 1'b0;
//Create frame signal for output
always @ (posedge tx_lclk)
begin
tx_state_reg[2:0] <= tx_state[2:0];
tx_frame <= |(tx_state_reg[2:0]);
end
//#############################
//# 2 CYCLE PACKET PIPELINE
//#############################
always @ (posedge tx_lclk)
if (tx_access)
tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
packet2emesh p2e (.access_out (access),
.write_out (write),
.datamode_out (datamode[1:0]),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (tx_packet_reg[PW-1:0]));
always @ (posedge tx_lclk)
if (tx_new_frame)
tx_double[63:0] <= {16'b0,//16
~write,7'b0,ctrlmode[3:0],//12
dstaddr[31:0],datamode[1:0],write,access};//36
else if(tx_state[2:0]==`CYCLE4)
tx_double[63:0] <= {data[31:0],srcaddr[31:0]};
//#############################
//# SELECTING DATA FOR TRANSMIT
//#############################
always @ (posedge tx_lclk)
case(tx_state_reg[2:0])
//Cycle1
3'b001: tx_data16[15:0] <= tx_double[47:32];
//Cycle2
3'b010: tx_data16[15:0] <= tx_double[31:16];
//Cycle3
3'b011: tx_data16[15:0] <= tx_double[15:0];
//Cycle4
3'b100: tx_data16[15:0] <= tx_double[63:48];
//Cycle5
3'b101: tx_data16[15:0] <= tx_double[47:32];
//Cycle6
3'b110: tx_data16[15:0] <= tx_double[31:16];
//Cycle7
3'b111: tx_data16[15:0] <= tx_double[15:0];
default tx_data16[15:0] <= 16'b0;
endcase // case (tx_state[2:0])
//#############################
//# ODDR DRIVERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data[i]),
.C (tx_lclk),
.CE (1'b1),
.D1 (tx_data16[i+8]),
.D2 (tx_data16[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE ("SYNC"))
oddr_frame (
.Q (txo_frame),
.C (tx_lclk),
.CE (1'b1),
.D1 (tx_frame),
.D2 (tx_frame),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
//##############################
//# OUTPUT BUFFERS
//##############################
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data[7:0])
);
OBUFDS obufds_frame ( .O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame)
);
OBUFDS obufds_lclk ( .O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
//################################
//# Wait Input Buffers
//################################
generate
if(ETYPE==1)
begin
assign tx_wr_wait = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait));
end
endgenerate
//TODO: Come up with cleaner defines for this
//Parallella and other platforms...
`ifdef TODO
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define low_pos(x,y) `high_pos(x,y) - 63
`define high_pos(x,y) 1599 - 64*(5*y+x)
`define add_1(x) (x == 4 ? 0 : x + 1)
`define add_2(x) (x == 3 ? 0 : x == 4 ? 1 : x + 2)
`define sub_1(x) (x == 0 ? 4 : x - 1)
`define rot_up(in, n) {in[63-n:0], in[63:63-n+1]}
`define rot_up_1(in) {in[62:0], in[63]}
module round2in1(in, round_const_1, round_const_2, out);
input [1599:0] in;
input [63:0] round_const_1, round_const_2;
output [1599:0] out;
/* "a ~ g" for round 1 */
wire [63:0] a[4:0][4:0];
wire [63:0] b[4:0];
wire [63:0] c[4:0][4:0], d[4:0][4:0], e[4:0][4:0], f[4:0][4:0], g[4:0][4:0];
/* "aa ~ gg" for round 2 */
wire [63:0] bb[4:0];
wire [63:0] cc[4:0][4:0], dd[4:0][4:0], ee[4:0][4:0], ff[4:0][4:0], gg[4:0][4:0];
genvar x, y;
/* assign "a[x][y][z] == in[w(5y+x)+z]" */
generate
for(y=0; y<5; y=y+1)
begin : L0
for(x=0; x<5; x=x+1)
begin : L1
assign a[x][y] = in[`high_pos(x,y) : `low_pos(x,y)];
end
end
endgenerate
/* calc "b[x] == a[x][0] ^ a[x][1] ^ ... ^ a[x][4]" */
generate
for(x=0; x<5; x=x+1)
begin : L2
assign b[x] = a[x][0] ^ a[x][1] ^ a[x][2] ^ a[x][3] ^ a[x][4];
end
endgenerate
/* calc "c == theta(a)" */
generate
for(y=0; y<5; y=y+1)
begin : L3
for(x=0; x<5; x=x+1)
begin : L4
assign c[x][y] = a[x][y] ^ b[`sub_1(x)] ^ `rot_up_1(b[`add_1(x)]);
end
end
endgenerate
/* calc "d == rho(c)" */
assign d[0][0] = c[0][0];
assign d[1][0] = `rot_up_1(c[1][0]);
assign d[2][0] = `rot_up(c[2][0], 62);
assign d[3][0] = `rot_up(c[3][0], 28);
assign d[4][0] = `rot_up(c[4][0], 27);
assign d[0][1] = `rot_up(c[0][1], 36);
assign d[1][1] = `rot_up(c[1][1], 44);
assign d[2][1] = `rot_up(c[2][1], 6);
assign d[3][1] = `rot_up(c[3][1], 55);
assign d[4][1] = `rot_up(c[4][1], 20);
assign d[0][2] = `rot_up(c[0][2], 3);
assign d[1][2] = `rot_up(c[1][2], 10);
assign d[2][2] = `rot_up(c[2][2], 43);
assign d[3][2] = `rot_up(c[3][2], 25);
assign d[4][2] = `rot_up(c[4][2], 39);
assign d[0][3] = `rot_up(c[0][3], 41);
assign d[1][3] = `rot_up(c[1][3], 45);
assign d[2][3] = `rot_up(c[2][3], 15);
assign d[3][3] = `rot_up(c[3][3], 21);
assign d[4][3] = `rot_up(c[4][3], 8);
assign d[0][4] = `rot_up(c[0][4], 18);
assign d[1][4] = `rot_up(c[1][4], 2);
assign d[2][4] = `rot_up(c[2][4], 61);
assign d[3][4] = `rot_up(c[3][4], 56);
assign d[4][4] = `rot_up(c[4][4], 14);
/* calc "e == pi(d)" */
assign e[0][0] = d[0][0];
assign e[0][2] = d[1][0];
assign e[0][4] = d[2][0];
assign e[0][1] = d[3][0];
assign e[0][3] = d[4][0];
assign e[1][3] = d[0][1];
assign e[1][0] = d[1][1];
assign e[1][2] = d[2][1];
assign e[1][4] = d[3][1];
assign e[1][1] = d[4][1];
assign e[2][1] = d[0][2];
assign e[2][3] = d[1][2];
assign e[2][0] = d[2][2];
assign e[2][2] = d[3][2];
assign e[2][4] = d[4][2];
assign e[3][4] = d[0][3];
assign e[3][1] = d[1][3];
assign e[3][3] = d[2][3];
assign e[3][0] = d[3][3];
assign e[3][2] = d[4][3];
assign e[4][2] = d[0][4];
assign e[4][4] = d[1][4];
assign e[4][1] = d[2][4];
assign e[4][3] = d[3][4];
assign e[4][0] = d[4][4];
/* calc "f = chi(e)" */
generate
for(y=0; y<5; y=y+1)
begin : L5
for(x=0; x<5; x=x+1)
begin : L6
assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]);
end
end
endgenerate
/* calc "g = iota(f)" */
generate
for(x=0; x<64; x=x+1)
begin : L60
if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63)
assign g[0][0][x] = f[0][0][x] ^ round_const_1[x];
else
assign g[0][0][x] = f[0][0][x];
end
endgenerate
generate
for(y=0; y<5; y=y+1)
begin : L7
for(x=0; x<5; x=x+1)
begin : L8
if(x!=0 || y!=0)
assign g[x][y] = f[x][y];
end
end
endgenerate
/* round 2 */
/* calc "bb[x] == g[x][0] ^ g[x][1] ^ ... ^ g[x][4]" */
generate
for(x=0; x<5; x=x+1)
begin : L12
assign bb[x] = g[x][0] ^ g[x][1] ^ g[x][2] ^ g[x][3] ^ g[x][4];
end
endgenerate
/* calc "cc == theta(g)" */
generate
for(y=0; y<5; y=y+1)
begin : L13
for(x=0; x<5; x=x+1)
begin : L14
assign cc[x][y] = g[x][y] ^ bb[`sub_1(x)] ^ `rot_up_1(bb[`add_1(x)]);
end
end
endgenerate
/* calc "dd == rho(cc)" */
assign dd[0][0] = cc[0][0];
assign dd[1][0] = `rot_up_1(cc[1][0]);
assign dd[2][0] = `rot_up(cc[2][0], 62);
assign dd[3][0] = `rot_up(cc[3][0], 28);
assign dd[4][0] = `rot_up(cc[4][0], 27);
assign dd[0][1] = `rot_up(cc[0][1], 36);
assign dd[1][1] = `rot_up(cc[1][1], 44);
assign dd[2][1] = `rot_up(cc[2][1], 6);
assign dd[3][1] = `rot_up(cc[3][1], 55);
assign dd[4][1] = `rot_up(cc[4][1], 20);
assign dd[0][2] = `rot_up(cc[0][2], 3);
assign dd[1][2] = `rot_up(cc[1][2], 10);
assign dd[2][2] = `rot_up(cc[2][2], 43);
assign dd[3][2] = `rot_up(cc[3][2], 25);
assign dd[4][2] = `rot_up(cc[4][2], 39);
assign dd[0][3] = `rot_up(cc[0][3], 41);
assign dd[1][3] = `rot_up(cc[1][3], 45);
assign dd[2][3] = `rot_up(cc[2][3], 15);
assign dd[3][3] = `rot_up(cc[3][3], 21);
assign dd[4][3] = `rot_up(cc[4][3], 8);
assign dd[0][4] = `rot_up(cc[0][4], 18);
assign dd[1][4] = `rot_up(cc[1][4], 2);
assign dd[2][4] = `rot_up(cc[2][4], 61);
assign dd[3][4] = `rot_up(cc[3][4], 56);
assign dd[4][4] = `rot_up(cc[4][4], 14);
/* calc "ee == pi(dd)" */
assign ee[0][0] = dd[0][0];
assign ee[0][2] = dd[1][0];
assign ee[0][4] = dd[2][0];
assign ee[0][1] = dd[3][0];
assign ee[0][3] = dd[4][0];
assign ee[1][3] = dd[0][1];
assign ee[1][0] = dd[1][1];
assign ee[1][2] = dd[2][1];
assign ee[1][4] = dd[3][1];
assign ee[1][1] = dd[4][1];
assign ee[2][1] = dd[0][2];
assign ee[2][3] = dd[1][2];
assign ee[2][0] = dd[2][2];
assign ee[2][2] = dd[3][2];
assign ee[2][4] = dd[4][2];
assign ee[3][4] = dd[0][3];
assign ee[3][1] = dd[1][3];
assign ee[3][3] = dd[2][3];
assign ee[3][0] = dd[3][3];
assign ee[3][2] = dd[4][3];
assign ee[4][2] = dd[0][4];
assign ee[4][4] = dd[1][4];
assign ee[4][1] = dd[2][4];
assign ee[4][3] = dd[3][4];
assign ee[4][0] = dd[4][4];
/* calc "ff = chi(ee)" */
generate
for(y=0; y<5; y=y+1)
begin : L15
for(x=0; x<5; x=x+1)
begin : L16
assign ff[x][y] = ee[x][y] ^ ((~ ee[`add_1(x)][y]) & ee[`add_2(x)][y]);
end
end
endgenerate
/* calc "gg = iota(ff)" */
generate
for(x=0; x<64; x=x+1)
begin : L160
if(x==0 || x==1 || x==3 || x==7 || x==15 || x==31 || x==63)
assign gg[0][0][x] = ff[0][0][x] ^ round_const_2[x];
else
assign gg[0][0][x] = ff[0][0][x];
end
endgenerate
generate
for(y=0; y<5; y=y+1)
begin : L17
for(x=0; x<5; x=x+1)
begin : L18
if(x!=0 || y!=0)
assign gg[x][y] = ff[x][y];
end
end
endgenerate
/* assign "out[w(5y+x)+z] == out_var[x][y][z]" */
generate
for(y=0; y<5; y=y+1)
begin : L99
for(x=0; x<5; x=x+1)
begin : L100
assign out[`high_pos(x,y) : `low_pos(x,y)] = gg[x][y];
end
end
endgenerate
endmodule
`undef low_pos
`undef high_pos
`undef add_1
`undef add_2
`undef sub_1
`undef rot_up
`undef rot_up_1
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_4_V
`define SKY130_FD_SC_HDLL__A31O_4_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31o_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_4_V
|
//# 35 inputs
//# 49 outputs
//# 179 D-type flipflops
//# 1775 inverters
//# 1004 gates (0 ANDs + 0 NANDs + 239 ORs + 765 NORs)
module s5378(GND,VDD,CK,n3065gat,n3066gat,n3067gat,n3068gat,n3069gat,n3070gat,
n3071gat,
n3072gat,n3073gat,n3074gat,n3075gat,n3076gat,n3077gat,n3078gat,n3079gat,
n3080gat,n3081gat,n3082gat,n3083gat,n3084gat,n3085gat,n3086gat,n3087gat,
n3088gat,n3089gat,n3090gat,n3091gat,n3092gat,n3093gat,n3094gat,n3095gat,
n3097gat,n3098gat,n3099gat,n3100gat,n3104gat,n3105gat,n3106gat,n3107gat,
n3108gat,n3109gat,n3110gat,n3111gat,n3112gat,n3113gat,n3114gat,n3115gat,
n3116gat,n3117gat,n3118gat,n3119gat,n3120gat,n3121gat,n3122gat,n3123gat,
n3124gat,n3125gat,n3126gat,n3127gat,n3128gat,n3129gat,n3130gat,n3131gat,
n3132gat,n3133gat,n3134gat,n3135gat,n3136gat,n3137gat,n3138gat,n3139gat,
n3140gat,n3141gat,n3142gat,n3143gat,n3144gat,n3145gat,n3146gat,n3147gat,
n3148gat,n3149gat,n3150gat,n3151gat,n3152gat);
input GND,VDD,CK,n3065gat,n3066gat,n3067gat,n3068gat,n3069gat,n3070gat,
n3071gat,n3072gat,
n3073gat,n3074gat,n3075gat,n3076gat,n3077gat,n3078gat,n3079gat,n3080gat,
n3081gat,n3082gat,n3083gat,n3084gat,n3085gat,n3086gat,n3087gat,n3088gat,
n3089gat,n3090gat,n3091gat,n3092gat,n3093gat,n3094gat,n3095gat,n3097gat,
n3098gat,n3099gat,n3100gat;
output n3104gat,n3105gat,n3106gat,n3107gat,n3108gat,n3109gat,n3110gat,n3111gat,
n3112gat,n3113gat,n3114gat,n3115gat,n3116gat,n3117gat,n3118gat,n3119gat,
n3120gat,n3121gat,n3122gat,n3123gat,n3124gat,n3125gat,n3126gat,n3127gat,
n3128gat,n3129gat,n3130gat,n3131gat,n3132gat,n3133gat,n3134gat,n3135gat,
n3136gat,n3137gat,n3138gat,n3139gat,n3140gat,n3141gat,n3142gat,n3143gat,
n3144gat,n3145gat,n3146gat,n3147gat,n3148gat,n3149gat,n3150gat,n3151gat,
n3152gat;
wire n673gat,n2897gat,n398gat,n2782gat,n402gat,n2790gat,n919gat,n2670gat,
n846gat,n2793gat,n394gat,n703gat,n722gat,n726gat,n2510gat,n748gat,n271gat,
n2732gat,n160gat,n2776gat,n337gat,n2735gat,n842gat,n2673gat,n341gat,
n2779gat,n2522gat,n43gat,n2472gat,n1620gat,n2319gat,n2470gat,n1821gat,
n1827gat,n1825gat,n2029gat,n1816gat,n1829gat,n2027gat,n283gat,n165gat,
n279gat,n1026gat,n275gat,n2476gat,n55gat,n1068gat,n2914gat,n957gat,
n2928gat,n861gat,n2927gat,n1294gat,n2896gat,n1241gat,n2922gat,n1298gat,
n865gat,n2894gat,n1080gat,n2921gat,n1148gat,n2895gat,n2468gat,n933gat,
n618gat,n491gat,n622gat,n626gat,n834gat,n3064gat,n707gat,n3055gat,n838gat,
n3063gat,n830gat,n3062gat,n614gat,n3056gat,n2526gat,n504gat,n680gat,
n2913gat,n816gat,n2920gat,n580gat,n2905gat,n824gat,n3057gat,n820gat,
n3059gat,n883gat,n3058gat,n584gat,n2898gat,n684gat,n3060gat,n699gat,
n3061gat,n2464gat,n567gat,n2399gat,n3048gat,n2343gat,n3049gat,n2203gat,
n3051gat,n2562gat,n3047gat,n2207gat,n3050gat,n2626gat,n3040gat,n2490gat,
n3044gat,n2622gat,n3042gat,n2630gat,n3037gat,n2543gat,n3041gat,n2102gat,
n1606gat,n1880gat,n3052gat,n1763gat,n1610gat,n2155gat,n1858gat,n1035gat,
n2918gat,n1121gat,n2952gat,n1072gat,n2919gat,n1282gat,n2910gat,n1226gat,
n2907gat,n931gat,n2911gat,n1135gat,n2912gat,n1045gat,n2909gat,n1197gat,
n2908gat,n2518gat,n2971gat,n667gat,n2904gat,n659gat,n2891gat,n553gat,
n2903gat,n777gat,n2915gat,n561gat,n2901gat,n366gat,n2890gat,n322gat,
n2888gat,n318gat,n2887gat,n314gat,n2886gat,n2599gat,n3010gat,n2588gat,
n3016gat,n2640gat,n3054gat,n2658gat,n2579gat,n2495gat,n3036gat,n2390gat,
n3034gat,n2270gat,n3031gat,n2339gat,n3035gat,n2502gat,n2646gat,n2634gat,
n3053gat,n2506gat,n2613gat,n1834gat,n1625gat,n1767gat,n1626gat,n2084gat,
n1603gat,n2143gat,n2541gat,n2061gat,n2557gat,n2139gat,n2487gat,n1899gat,
n2532gat,n1850gat,n2628gat,n2403gat,n2397gat,n2394gat,n2341gat,n2440gat,
n2560gat,n2407gat,n2205gat,n2347gat,n2201gat,n1389gat,n1793gat,n2021gat,
n1781gat,n1394gat,n1516gat,n1496gat,n1392gat,n2091gat,n1685gat,n1332gat,
n1565gat,n1740gat,n1330gat,n2179gat,n1945gat,n2190gat,n2268gat,n2135gat,
n2337gat,n2262gat,n2388gat,n2182gat,n1836gat,n1433gat,n2983gat,n1316gat,
n1431gat,n1363gat,n1314gat,n1312gat,n1361gat,n1775gat,n1696gat,n1871gat,
n2009gat,n2592gat,n1773gat,n1508gat,n1636gat,n1678gat,n1712gat,n2309gat,
n3000gat,n2450gat,n2307gat,n2446gat,n2661gat,n2095gat,n827gat,n2176gat,
n2093gat,n2169gat,n2174gat,n2454gat,n2163gat,n2040gat,n1777gat,n2044gat,
n2015gat,n2037gat,n2042gat,n2025gat,n2017gat,n2099gat,n2023gat,n2266gat,
n2493gat,n2033gat,n2035gat,n2110gat,n2031gat,n2125gat,n2108gat,n2121gat,
n2123gat,n2117gat,n2119gat,n1975gat,n2632gat,n2644gat,n2638gat,n156gat,
n612gat,n152gat,n705gat,n331gat,n822gat,n388gat,n881gat,n463gat,n818gat,
n327gat,n682gat,n384gat,n697gat,n256gat,n836gat,n470gat,n828gat,n148gat,
n832gat,n2458gat,n2590gat,n2514gat,n2456gat,n1771gat,n1613gat,n1336gat,
n1391gat,n1748gat,n1927gat,n1675gat,n1713gat,n1807gat,n1717gat,n1340gat,
n1567gat,n1456gat,n1564gat,n1525gat,n1632gat,n1462gat,n1915gat,n1596gat,
n1800gat,n1588gat,n1593gat,II1,n2717gat,n2715gat,II5,n2725gat,n2723gat,
n296gat,n421gat,II11,n2768gat,II14,n2767gat,n373gat,II18,n2671gat,n2669gat,
II23,n2845gat,n2844gat,II27,n2668gat,II30,n2667gat,n856gat,II44,n672gat,
II47,n2783gat,II50,n396gat,II62,n2791gat,II65,II76,n401gat,n1645gat,
n1499gat,II81,II92,n918gat,n1553gat,n1616gat,II97,n2794gat,II100,II111,
n845gat,n1559gat,n1614gat,n1643gat,n1641gat,n1651gat,n1642gat,n1562gat,
n1556gat,n1560gat,n1557gat,n1640gat,n1639gat,n1566gat,n1605gat,n1554gat,
n1555gat,n1722gat,n1558gat,n392gat,II149,n702gat,n1319gat,n1256gat,n720gat,
II171,n725gat,n1447gat,n1117gat,n1627gat,n1618gat,II178,n721gat,n1380gat,
n1114gat,n1628gat,n1621gat,n701gat,n1446gat,n1318gat,n1705gat,n1619gat,
n1706gat,n1622gat,II192,n2856gat,n2854gat,II196,n1218gat,II199,n2861gat,
n2859gat,II203,n1219gat,II206,n2864gat,n2862gat,II210,n1220gat,II214,
n2860gat,II217,n1221gat,II220,n2863gat,II223,n1222gat,II227,n2855gat,II230,
n1223gat,n640gat,n1213gat,II237,n753gat,II240,n2716gat,II243,n2869gat,
n2867gat,II248,n2868gat,II253,n2906gat,n754gat,II256,n2724gat,II259,
n2728gat,n2726gat,II264,n2727gat,n422gat,n2889gat,II270,n755gat,n747gat,
II275,n756gat,II278,n757gat,II282,n758gat,n2508gat,II297,n2733gat,II300,
II311,n270gat,II314,n263gat,II317,n2777gat,II320,II331,n159gat,II334,
n264gat,II337,n2736gat,II340,II351,n336gat,II354,n265gat,n158gat,II359,
n266gat,n335gat,II363,n267gat,n269gat,II368,n268gat,n41gat,n258gat,II375,
n48gat,II378,n1018gat,II381,n2674gat,II384,II395,n841gat,II398,n1019gat,
II401,n1020gat,n840gat,II406,n1021gat,II409,n1022gat,n724gat,II414,
n1023gat,II420,n1013gat,n49gat,II423,n2780gat,II426,II437,n340gat,II440,
n480gat,II443,n481gat,II446,n393gat,II449,n482gat,II453,n483gat,II456,
n484gat,n339gat,II461,n485gat,n42gat,n475gat,II468,n50gat,n162gat,II473,
n51gat,II476,n52gat,II480,n53gat,n2520gat,n1448gat,n1376gat,n1701gat,
n1617gat,n1379gat,n1377gat,n1615gat,n1624gat,n1500gat,n1113gat,n1503gat,
n1501gat,n1779gat,n1623gat,II509,n2730gat,II512,n2729gat,n2317gat,n1819gat,
n1823gat,n1817gat,II572,n1828gat,II576,n2851gat,II579,n2850gat,II583,
n2786gat,n2785gat,n92gat,n637gat,n529gat,n293gat,n361gat,II591,n2722gat,
II594,n2721gat,n297gat,II606,n282gat,II609,n172gat,II620,n164gat,II623,
n173gat,II634,n278gat,II637,n174gat,n163gat,II642,n175gat,n277gat,II646,
n176gat,n281gat,II651,n177gat,n54gat,n167gat,II658,n60gat,II661,n911gat,
II672,n1025gat,II675,n912gat,II678,n913gat,n1024gat,II683,n914gat,n917gat,
II687,n915gat,n844gat,II692,n916gat,II698,n906gat,n61gat,II709,n274gat,
II712,n348gat,II715,n349gat,II718,n397gat,II721,n350gat,n400gat,II726,
n351gat,II729,n352gat,n273gat,II734,n353gat,n178gat,n343gat,II741,n62gat,
n66gat,II746,n63gat,II749,n64gat,II753,n65gat,n2474gat,II768,n2832gat,
II771,n2831gat,n2731gat,II776,n2719gat,n2718gat,II790,n1067gat,II793,
n949gat,II796,n2839gat,n2838gat,n2775gat,II812,n956gat,II815,n950gat,II818,
n2712gat,n2711gat,n2734gat,II834,n860gat,II837,n951gat,n955gat,II842,
n952gat,n859gat,II846,n953gat,n1066gat,II851,n954gat,n857gat,n944gat,II858,
n938gat,n2792gat,II863,n2847gat,n2846gat,II877,n1293gat,II880,n1233gat,
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n2738gat,n2385gat,II4554,n2741gat,n2737gat,n1286gat,II4558,n2687gat,
n2685gat,n1328gat,n1381gat,n1384gat,II4566,n2694gat,n2690gat,n1382gat,
n1451gat,n1453gat,II4573,n2693gat,n2689gat,n927gat,n925gat,n1452gat,II4580,
n2702gat,n2698gat,n923gat,n921gat,n1890gat,II4587,n2701gat,n2697gat,
n850gat,n739gat,n1841gat,II4594,n2709gat,n2706gat,n922gat,n848gat,n2047gat,
II4601,n2708gat,n2705gat,n924gat,n849gat,n2050gat,II4608,n2799gat,n2796gat,
n1118gat,n1032gat,n2054gat,II4615,n2798gat,n2795gat,II4620,n1745gat,
n2806gat,II4623,n2802gat,II4626,n1870gat,n1086gat,II4630,n2805gat,II4633,
n2801gat,n67gat,n85gat,n71gat,n180gat,n1840gat,II4642,n2812gat,n2809gat,
n76gat,n82gat,n14gat,n186gat,n1842gat,II4651,n2822gat,n2819gat,II4654,
II4657,II4660,II4663,II4666,II4669,II4672,II4675,II4678,II4681,II4684,
II4687,II4690,II4693,II4696,II4699,II4702,II4705,II4708,II4711,II4714,
II4717,II4720,II4723,II4726,II4729,II4732,II4735,II4738,II4741,II4744,
II4747,II4750,II4753,II4756,II4759,II4762,II4765,II4768,II4771,II4774,
II4777,II4780,II4783,II4786,II4789,II4792,II4795,II4798,n648gat,n442gat,
n1214gat,n1215gat,n1216gat,n1217gat,n745gat,n638gat,n423gat,n362gat,
n749gat,n750gat,n751gat,n752gat,n259gat,n260gat,n261gat,n262gat,n1014gat,
n1015gat,n1016gat,n1017gat,n476gat,n477gat,n478gat,n479gat,n44gat,n45gat,
n46gat,n47gat,n168gat,n169gat,n170gat,n171gat,n907gat,n908gat,n909gat,
n910gat,n344gat,n345gat,n346gat,n347gat,n56gat,n57gat,n58gat,n59gat,
n768gat,n655gat,n963gat,n868gat,n962gat,n959gat,n945gat,n946gat,n947gat,
n948gat,n647gat,n441gat,n967gat,n792gat,n1229gat,n1230gat,n1231gat,
n1232gat,n443gat,n439gat,n966gat,n790gat,n444gat,n440gat,n1051gat,n1052gat,
n1053gat,n1054gat,n934gat,n935gat,n936gat,n937gat,n710gat,n711gat,n712gat,
n713gat,n729gat,n730gat,n731gat,n732gat,n494gat,n495gat,n496gat,n497gat,
n505gat,n506gat,n507gat,n508gat,II1277,n767gat,n653gat,n867gat,n771gat,
n964gat,n961gat,n804gat,n805gat,n806gat,n807gat,n587gat,n588gat,n589gat,
n590gat,n447gat,n445gat,n687gat,n688gat,n689gat,n690gat,n568gat,n569gat,
n570gat,n571gat,II1515,II1584,n1692gat,II1723,II1733,n2428gat,n769gat,
n1076gat,n766gat,n1185gat,n1186gat,n1187gat,n1188gat,n645gat,n646gat,
n1383gat,n1327gat,n651gat,n652gat,n765gat,n1202gat,n1203gat,n1204gat,
n1205gat,n1270gat,n1271gat,n1272gat,n1273gat,n763gat,n1287gat,n1285gat,
n793gat,n556gat,n795gat,n656gat,n794gat,n773gat,n965gat,n960gat,n780gat,
n781gat,n782gat,n783gat,n555gat,n450gat,n654gat,n557gat,n874gat,n132gat,
n649gat,n449gat,n791gat,n650gat,n774gat,n764gat,n222gat,n223gat,n224gat,
n225gat,n121gat,n122gat,n123gat,n124gat,n2460gat,n2423gat,n2569gat,
n2570gat,n2571gat,n2572gat,n2410gat,n2411gat,n2412gat,n2413gat,n2580gat,
n2581gat,n2567gat,n2499gat,n299gat,n207gat,n2647gat,n2648gat,n2602gat,
n2603gat,n2604gat,n2605gat,n2546gat,n2547gat,n2548gat,n2549gat,n2614gat,
n2615gat,n2461gat,n2421gat,n2930gat,n1153gat,n1151gat,n982gat,n877gat,
n2957gat,n1159gat,n1158gat,n1156gat,n1155gat,n1443gat,n1325gat,n1321gat,
n1320gat,n1368gat,n1258gat,n1373gat,n1372gat,n2978gat,n1441gat,n1440gat,
n1371gat,n1367gat,n2982gat,n1504gat,n1502gat,n1250gat,n1103gat,n1304gat,
n1249gat,n1246gat,n1161gat,n1291gat,n1245gat,n2973gat,n1352gat,n1351gat,
n1303gat,n1302gat,n1163gat,n1102gat,n1101gat,n996gat,n1104gat,n887gat,
n1305gat,n1162gat,n2977gat,n1360gat,n1359gat,n1358gat,n1357gat,II2720,
II2735,II2812,n1703gat,n1778gat,n1609gat,II2831,II2889,II2925,II2934,
n1733gat,n1581gat,n2079gat,n2073gat,n1574gat,n1573gat,n2992gat,n1723gat,
n1647gat,n1646gat,n2986gat,n1650gat,n1649gat,n1563gat,n2991gat,n1654gat,
n1653gat,n1644gat,II3148,II3178,n2981gat,n1413gat,n1408gat,n1407gat,
n2258gat,n2255gat,n2132gat,n2130gat,n3007gat,n2250gat,n2249gat,n1710gat,
n1630gat,n1894gat,n1847gat,n1846gat,n2055gat,n1967gat,n1959gat,n1957gat,
n2211gat,n2210gat,n2053gat,n1964gat,n2350gat,n2282gat,n2213gat,n2150gat,
n2149gat,n2995gat,n1962gat,n2999gat,n1972gat,n1971gat,n3011gat,n2331gat,
n3015gat,n2566gat,n2565gat,n141gat,n38gat,n37gat,n1074gat,n872gat,n234gat,
n137gat,n378gat,n377gat,n250gat,n249gat,n248gat,n869gat,n453gat,n448gat,
n251gat,n244gat,n974gat,n973gat,n870gat,n246gat,n245gat,n460gat,n459gat,
n975gat,n972gat,n969gat,n145gat,n143gat,n971gat,n970gat,n968gat,n142gat,
n40gat,n39gat,n772gat,n451gat,n446gat,n139gat,n136gat,n391gat,n390gat,
n1083gat,n1077gat,n242gat,n240gat,n871gat,n797gat,n324gat,n238gat,n237gat,
n1082gat,n796gat,n1599gat,II3999,n1586gat,n1755gat,II4023,n1470gat,
n1400gat,n1399gat,n1398gat,II4144,n1467gat,n1466gat,n2985gat,n1686gat,
n1533gat,n1532gat,n1531gat,II4216,n2931gat,n1100gat,n994gat,n989gat,
n880gat,n2943gat,n1012gat,n905gat,n1003gat,n902gat,n1099gat,n998gat,
n995gat,n980gat,n2960gat,n1175gat,n1174gat,n1001gat,n999gat,n2969gat,
n1323gat,n1264gat,n981gat,n890gat,n889gat,n886gat,n892gat,n891gat,n2942gat,
n904gat,n903gat,n1152gat,n1092gat,n997gat,n993gat,n900gat,n895gat,n1094gat,
n1093gat,n988gat,n984gat,n2965gat,n1267gat,n1257gat,n1178gat,n1116gat,
n2961gat,n1375gat,n1324gat,n1091gat,n1088gat,n992gat,n987gat,n899gat,
n896gat,n2967gat,n1262gat,n1260gat,n1098gat,n1090gat,n986gat,n885gat,
n901gat,n893gat,n1097gat,n1089gat,n1087gat,n991gat,n2968gat,n1326gat,
n1261gat,n1177gat,n1115gat,n2944gat,n977gat,n2945gat,n1096gat,n1095gat,
n990gat,n979gat,n2962gat,n1176gat,n1173gat,n1004gat,n1000gat,n1029gat,
n1028gat,n1031gat,n1030gat,n1011gat,n1181gat,n1010gat,n1005gat,n1182gat,
n73gat,n70gat,n77gat,n13gat,n1935gat,n197gat,n22gat,n93gat,n2239gat,
n2433gat,n2427gat,n2583gat,n2650gat,n2617gat,n1598gat,n1154gat,n1411gat,
n1498gat,n1607gat,n1428gat,n1794gat,n1796gat,n1792gat,n1406gat,n2664gat,
n1926gat,n1916gat,n1994gat,n1924gat,n1758gat,n200gat,n196gat,n2018gat,
n89gat,n1471gat,n1472gat,n1600gat,n1397gat,n2005gat,n1818gat,n1510gat,
n1459gat,n1458gat,n1602gat,n520gat,n519gat,n410gat,n354gat,n408gat,n526gat,
n531gat,n530gat,n359gat,n420gat,n801gat,n879gat,n1255gat,n1009gat,n409gat,
n292gat,n419gat,n1243gat,n1171gat,n1244gat,n1265gat,n1254gat,n1008gat,
n1253gat,n1266gat,n1200gat,n1172gat,n1251gat,n1259gat,n1212gat,n1263gat,
n978gat,n1199gat,n1252gat,n1757gat;
dff DFF_0(CK,n673gat,n2897gat);
dff DFF_1(CK,n398gat,n2782gat);
dff DFF_2(CK,n402gat,n2790gat);
dff DFF_3(CK,n919gat,n2670gat);
dff DFF_4(CK,n846gat,n2793gat);
dff DFF_5(CK,n394gat,n2782gat);
dff DFF_6(CK,n703gat,n2790gat);
dff DFF_7(CK,n722gat,n2670gat);
dff DFF_8(CK,n726gat,n2793gat);
dff DFF_9(CK,n2510gat,n748gat);
dff DFF_10(CK,n271gat,n2732gat);
dff DFF_11(CK,n160gat,n2776gat);
dff DFF_12(CK,n337gat,n2735gat);
dff DFF_13(CK,n842gat,n2673gat);
dff DFF_14(CK,n341gat,n2779gat);
dff DFF_15(CK,n2522gat,n43gat);
dff DFF_16(CK,n2472gat,n1620gat);
dff DFF_17(CK,n2319gat,n2470gat);
dff DFF_18(CK,n1821gat,n1827gat);
dff DFF_19(CK,n1825gat,n1827gat);
dff DFF_20(CK,n2029gat,n1816gat);
dff DFF_21(CK,n1829gat,n2027gat);
dff DFF_22(CK,n283gat,n2732gat);
dff DFF_23(CK,n165gat,n2776gat);
dff DFF_24(CK,n279gat,n2735gat);
dff DFF_25(CK,n1026gat,n2673gat);
dff DFF_26(CK,n275gat,n2779gat);
dff DFF_27(CK,n2476gat,n55gat);
dff DFF_28(CK,n1068gat,n2914gat);
dff DFF_29(CK,n957gat,n2928gat);
dff DFF_30(CK,n861gat,n2927gat);
dff DFF_31(CK,n1294gat,n2896gat);
dff DFF_32(CK,n1241gat,n2922gat);
dff DFF_33(CK,n1298gat,n2897gat);
dff DFF_34(CK,n865gat,n2894gat);
dff DFF_35(CK,n1080gat,n2921gat);
dff DFF_36(CK,n1148gat,n2895gat);
dff DFF_37(CK,n2468gat,n933gat);
dff DFF_38(CK,n618gat,n2790gat);
dff DFF_39(CK,n491gat,n2782gat);
dff DFF_40(CK,n622gat,n2793gat);
dff DFF_41(CK,n626gat,n2670gat);
dff DFF_42(CK,n834gat,n3064gat);
dff DFF_43(CK,n707gat,n3055gat);
dff DFF_44(CK,n838gat,n3063gat);
dff DFF_45(CK,n830gat,n3062gat);
dff DFF_46(CK,n614gat,n3056gat);
dff DFF_47(CK,n2526gat,n504gat);
dff DFF_48(CK,n680gat,n2913gat);
dff DFF_49(CK,n816gat,n2920gat);
dff DFF_50(CK,n580gat,n2905gat);
dff DFF_51(CK,n824gat,n3057gat);
dff DFF_52(CK,n820gat,n3059gat);
dff DFF_53(CK,n883gat,n3058gat);
dff DFF_54(CK,n584gat,n2898gat);
dff DFF_55(CK,n684gat,n3060gat);
dff DFF_56(CK,n699gat,n3061gat);
dff DFF_57(CK,n2464gat,n567gat);
dff DFF_58(CK,n2399gat,n3048gat);
dff DFF_59(CK,n2343gat,n3049gat);
dff DFF_60(CK,n2203gat,n3051gat);
dff DFF_61(CK,n2562gat,n3047gat);
dff DFF_62(CK,n2207gat,n3050gat);
dff DFF_63(CK,n2626gat,n3040gat);
dff DFF_64(CK,n2490gat,n3044gat);
dff DFF_65(CK,n2622gat,n3042gat);
dff DFF_66(CK,n2630gat,n3037gat);
dff DFF_67(CK,n2543gat,n3041gat);
dff DFF_68(CK,n2102gat,n1606gat);
dff DFF_69(CK,n1880gat,n3052gat);
dff DFF_70(CK,n1763gat,n1610gat);
dff DFF_71(CK,n2155gat,n1858gat);
dff DFF_72(CK,n1035gat,n2918gat);
dff DFF_73(CK,n1121gat,n2952gat);
dff DFF_74(CK,n1072gat,n2919gat);
dff DFF_75(CK,n1282gat,n2910gat);
dff DFF_76(CK,n1226gat,n2907gat);
dff DFF_77(CK,n931gat,n2911gat);
dff DFF_78(CK,n1135gat,n2912gat);
dff DFF_79(CK,n1045gat,n2909gat);
dff DFF_80(CK,n1197gat,n2908gat);
dff DFF_81(CK,n2518gat,n2971gat);
dff DFF_82(CK,n667gat,n2904gat);
dff DFF_83(CK,n659gat,n2891gat);
dff DFF_84(CK,n553gat,n2903gat);
dff DFF_85(CK,n777gat,n2915gat);
dff DFF_86(CK,n561gat,n2901gat);
dff DFF_87(CK,n366gat,n2890gat);
dff DFF_88(CK,n322gat,n2888gat);
dff DFF_89(CK,n318gat,n2887gat);
dff DFF_90(CK,n314gat,n2886gat);
dff DFF_91(CK,n2599gat,n3010gat);
dff DFF_92(CK,n2588gat,n3016gat);
dff DFF_93(CK,n2640gat,n3054gat);
dff DFF_94(CK,n2658gat,n2579gat);
dff DFF_95(CK,n2495gat,n3036gat);
dff DFF_96(CK,n2390gat,n3034gat);
dff DFF_97(CK,n2270gat,n3031gat);
dff DFF_98(CK,n2339gat,n3035gat);
dff DFF_99(CK,n2502gat,n2646gat);
dff DFF_100(CK,n2634gat,n3053gat);
dff DFF_101(CK,n2506gat,n2613gat);
dff DFF_102(CK,n1834gat,n1625gat);
dff DFF_103(CK,n1767gat,n1626gat);
dff DFF_104(CK,n2084gat,n1603gat);
dff DFF_105(CK,n2143gat,n2541gat);
dff DFF_106(CK,n2061gat,n2557gat);
dff DFF_107(CK,n2139gat,n2487gat);
dff DFF_108(CK,n1899gat,n2532gat);
dff DFF_109(CK,n1850gat,n2628gat);
dff DFF_110(CK,n2403gat,n2397gat);
dff DFF_111(CK,n2394gat,n2341gat);
dff DFF_112(CK,n2440gat,n2560gat);
dff DFF_113(CK,n2407gat,n2205gat);
dff DFF_114(CK,n2347gat,n2201gat);
dff DFF_115(CK,n1389gat,n1793gat);
dff DFF_116(CK,n2021gat,n1781gat);
dff DFF_117(CK,n1394gat,n1516gat);
dff DFF_118(CK,n1496gat,n1392gat);
dff DFF_119(CK,n2091gat,n1685gat);
dff DFF_120(CK,n1332gat,n1565gat);
dff DFF_121(CK,n1740gat,n1330gat);
dff DFF_122(CK,n2179gat,n1945gat);
dff DFF_123(CK,n2190gat,n2268gat);
dff DFF_124(CK,n2135gat,n2337gat);
dff DFF_125(CK,n2262gat,n2388gat);
dff DFF_126(CK,n2182gat,n1836gat);
dff DFF_127(CK,n1433gat,n2983gat);
dff DFF_128(CK,n1316gat,n1431gat);
dff DFF_129(CK,n1363gat,n1314gat);
dff DFF_130(CK,n1312gat,n1361gat);
dff DFF_131(CK,n1775gat,n1696gat);
dff DFF_132(CK,n1871gat,n2009gat);
dff DFF_133(CK,n2592gat,n1773gat);
dff DFF_134(CK,n1508gat,n1636gat);
dff DFF_135(CK,n1678gat,n1712gat);
dff DFF_136(CK,n2309gat,n3000gat);
dff DFF_137(CK,n2450gat,n2307gat);
dff DFF_138(CK,n2446gat,n2661gat);
dff DFF_139(CK,n2095gat,n827gat);
dff DFF_140(CK,n2176gat,n2093gat);
dff DFF_141(CK,n2169gat,n2174gat);
dff DFF_142(CK,n2454gat,n2163gat);
dff DFF_143(CK,n2040gat,n1777gat);
dff DFF_144(CK,n2044gat,n2015gat);
dff DFF_145(CK,n2037gat,n2042gat);
dff DFF_146(CK,n2025gat,n2017gat);
dff DFF_147(CK,n2099gat,n2023gat);
dff DFF_148(CK,n2266gat,n2493gat);
dff DFF_149(CK,n2033gat,n2035gat);
dff DFF_150(CK,n2110gat,n2031gat);
dff DFF_151(CK,n2125gat,n2108gat);
dff DFF_152(CK,n2121gat,n2123gat);
dff DFF_153(CK,n2117gat,n2119gat);
dff DFF_154(CK,n1975gat,n2632gat);
dff DFF_155(CK,n2644gat,n2638gat);
dff DFF_156(CK,n156gat,n612gat);
dff DFF_157(CK,n152gat,n705gat);
dff DFF_158(CK,n331gat,n822gat);
dff DFF_159(CK,n388gat,n881gat);
dff DFF_160(CK,n463gat,n818gat);
dff DFF_161(CK,n327gat,n682gat);
dff DFF_162(CK,n384gat,n697gat);
dff DFF_163(CK,n256gat,n836gat);
dff DFF_164(CK,n470gat,n828gat);
dff DFF_165(CK,n148gat,n832gat);
dff DFF_166(CK,n2458gat,n2590gat);
dff DFF_167(CK,n2514gat,n2456gat);
dff DFF_168(CK,n1771gat,n1613gat);
dff DFF_169(CK,n1336gat,n1391gat);
dff DFF_170(CK,n1748gat,n1927gat);
dff DFF_171(CK,n1675gat,n1713gat);
dff DFF_172(CK,n1807gat,n1717gat);
dff DFF_173(CK,n1340gat,n1567gat);
dff DFF_174(CK,n1456gat,n1564gat);
dff DFF_175(CK,n1525gat,n1632gat);
dff DFF_176(CK,n1462gat,n1915gat);
dff DFF_177(CK,n1596gat,n1800gat);
dff DFF_178(CK,n1588gat,n1593gat);
not NOT_0(II1,n3088gat);
not NOT_1(n2717gat,II1);
not NOT_2(n2715gat,n2717gat);
not NOT_3(II5,n3087gat);
not NOT_4(n2725gat,II5);
not NOT_5(n2723gat,n2725gat);
not NOT_6(n296gat,n421gat);
not NOT_7(II11,n3093gat);
not NOT_8(n2768gat,II11);
not NOT_9(II14,n2768gat);
not NOT_10(n2767gat,II14);
not NOT_11(n373gat,n2767gat);
not NOT_12(II18,n3072gat);
not NOT_13(n2671gat,II18);
not NOT_14(n2669gat,n2671gat);
not NOT_15(II23,n3081gat);
not NOT_16(n2845gat,II23);
not NOT_17(n2844gat,n2845gat);
not NOT_18(II27,n3095gat);
not NOT_19(n2668gat,II27);
not NOT_20(II30,n2668gat);
not NOT_21(n2667gat,II30);
not NOT_22(n856gat,n2667gat);
not NOT_23(II44,n673gat);
not NOT_24(n672gat,II44);
not NOT_25(II47,n3069gat);
not NOT_26(n2783gat,II47);
not NOT_27(II50,n2783gat);
not NOT_28(n2782gat,II50);
not NOT_29(n396gat,n398gat);
not NOT_30(II62,n3070gat);
not NOT_31(n2791gat,II62);
not NOT_32(II65,n2791gat);
not NOT_33(n2790gat,II65);
not NOT_34(II76,n402gat);
not NOT_35(n401gat,II76);
not NOT_36(n1645gat,n1499gat);
not NOT_37(II81,n2671gat);
not NOT_38(n2670gat,II81);
not NOT_39(II92,n919gat);
not NOT_40(n918gat,II92);
not NOT_41(n1553gat,n1616gat);
not NOT_42(II97,n3071gat);
not NOT_43(n2794gat,II97);
not NOT_44(II100,n2794gat);
not NOT_45(n2793gat,II100);
not NOT_46(II111,n846gat);
not NOT_47(n845gat,II111);
not NOT_48(n1559gat,n1614gat);
not NOT_49(n1643gat,n1641gat);
not NOT_50(n1651gat,n1642gat);
not NOT_51(n1562gat,n1556gat);
not NOT_52(n1560gat,n1557gat);
not NOT_53(n1640gat,n1639gat);
not NOT_54(n1566gat,n1605gat);
not NOT_55(n1554gat,n1555gat);
not NOT_56(n1722gat,n1558gat);
not NOT_57(n392gat,n394gat);
not NOT_58(II149,n703gat);
not NOT_59(n702gat,II149);
not NOT_60(n1319gat,n1256gat);
not NOT_61(n720gat,n722gat);
not NOT_62(II171,n726gat);
not NOT_63(n725gat,II171);
not NOT_64(n1447gat,n1117gat);
not NOT_65(n1627gat,n1618gat);
not NOT_66(II178,n722gat);
not NOT_67(n721gat,II178);
not NOT_68(n1380gat,n1114gat);
not NOT_69(n1628gat,n1621gat);
not NOT_70(n701gat,n703gat);
not NOT_71(n1446gat,n1318gat);
not NOT_72(n1705gat,n1619gat);
not NOT_73(n1706gat,n1622gat);
not NOT_74(II192,n3083gat);
not NOT_75(n2856gat,II192);
not NOT_76(n2854gat,n2856gat);
not NOT_77(II196,n2854gat);
not NOT_78(n1218gat,II196);
not NOT_79(II199,n3085gat);
not NOT_80(n2861gat,II199);
not NOT_81(n2859gat,n2861gat);
not NOT_82(II203,n2859gat);
not NOT_83(n1219gat,II203);
not NOT_84(II206,n3084gat);
not NOT_85(n2864gat,II206);
not NOT_86(n2862gat,n2864gat);
not NOT_87(II210,n2862gat);
not NOT_88(n1220gat,II210);
not NOT_89(II214,n2861gat);
not NOT_90(n2860gat,II214);
not NOT_91(II217,n2860gat);
not NOT_92(n1221gat,II217);
not NOT_93(II220,n2864gat);
not NOT_94(n2863gat,II220);
not NOT_95(II223,n2863gat);
not NOT_96(n1222gat,II223);
not NOT_97(II227,n2856gat);
not NOT_98(n2855gat,II227);
not NOT_99(II230,n2855gat);
not NOT_100(n1223gat,II230);
not NOT_101(n640gat,n1213gat);
not NOT_102(II237,n640gat);
not NOT_103(n753gat,II237);
not NOT_104(II240,n2717gat);
not NOT_105(n2716gat,II240);
not NOT_106(II243,n3089gat);
not NOT_107(n2869gat,II243);
not NOT_108(n2867gat,n2869gat);
not NOT_109(II248,n2869gat);
not NOT_110(n2868gat,II248);
not NOT_111(II253,n2906gat);
not NOT_112(n754gat,II253);
not NOT_113(II256,n2725gat);
not NOT_114(n2724gat,II256);
not NOT_115(II259,n3086gat);
not NOT_116(n2728gat,II259);
not NOT_117(n2726gat,n2728gat);
not NOT_118(II264,n2728gat);
not NOT_119(n2727gat,II264);
not NOT_120(n422gat,n2889gat);
not NOT_121(II270,n422gat);
not NOT_122(n755gat,II270);
not NOT_123(n747gat,n2906gat);
not NOT_124(II275,n747gat);
not NOT_125(n756gat,II275);
not NOT_126(II278,n2889gat);
not NOT_127(n757gat,II278);
not NOT_128(II282,n1213gat);
not NOT_129(n758gat,II282);
not NOT_130(n2508gat,n2510gat);
not NOT_131(II297,n3065gat);
not NOT_132(n2733gat,II297);
not NOT_133(II300,n2733gat);
not NOT_134(n2732gat,II300);
not NOT_135(II311,n271gat);
not NOT_136(n270gat,II311);
not NOT_137(II314,n270gat);
not NOT_138(n263gat,II314);
not NOT_139(II317,n3067gat);
not NOT_140(n2777gat,II317);
not NOT_141(II320,n2777gat);
not NOT_142(n2776gat,II320);
not NOT_143(II331,n160gat);
not NOT_144(n159gat,II331);
not NOT_145(II334,n159gat);
not NOT_146(n264gat,II334);
not NOT_147(II337,n3066gat);
not NOT_148(n2736gat,II337);
not NOT_149(II340,n2736gat);
not NOT_150(n2735gat,II340);
not NOT_151(II351,n337gat);
not NOT_152(n336gat,II351);
not NOT_153(II354,n336gat);
not NOT_154(n265gat,II354);
not NOT_155(n158gat,n160gat);
not NOT_156(II359,n158gat);
not NOT_157(n266gat,II359);
not NOT_158(n335gat,n337gat);
not NOT_159(II363,n335gat);
not NOT_160(n267gat,II363);
not NOT_161(n269gat,n271gat);
not NOT_162(II368,n269gat);
not NOT_163(n268gat,II368);
not NOT_164(n41gat,n258gat);
not NOT_165(II375,n41gat);
not NOT_166(n48gat,II375);
not NOT_167(II378,n725gat);
not NOT_168(n1018gat,II378);
not NOT_169(II381,n3073gat);
not NOT_170(n2674gat,II381);
not NOT_171(II384,n2674gat);
not NOT_172(n2673gat,II384);
not NOT_173(II395,n842gat);
not NOT_174(n841gat,II395);
not NOT_175(II398,n841gat);
not NOT_176(n1019gat,II398);
not NOT_177(II401,n721gat);
not NOT_178(n1020gat,II401);
not NOT_179(n840gat,n842gat);
not NOT_180(II406,n840gat);
not NOT_181(n1021gat,II406);
not NOT_182(II409,n720gat);
not NOT_183(n1022gat,II409);
not NOT_184(n724gat,n726gat);
not NOT_185(II414,n724gat);
not NOT_186(n1023gat,II414);
not NOT_187(II420,n1013gat);
not NOT_188(n49gat,II420);
not NOT_189(II423,n3068gat);
not NOT_190(n2780gat,II423);
not NOT_191(II426,n2780gat);
not NOT_192(n2779gat,II426);
not NOT_193(II437,n341gat);
not NOT_194(n340gat,II437);
not NOT_195(II440,n340gat);
not NOT_196(n480gat,II440);
not NOT_197(II443,n702gat);
not NOT_198(n481gat,II443);
not NOT_199(II446,n394gat);
not NOT_200(n393gat,II446);
not NOT_201(II449,n393gat);
not NOT_202(n482gat,II449);
not NOT_203(II453,n701gat);
not NOT_204(n483gat,II453);
not NOT_205(II456,n392gat);
not NOT_206(n484gat,II456);
not NOT_207(n339gat,n341gat);
not NOT_208(II461,n339gat);
not NOT_209(n485gat,II461);
not NOT_210(n42gat,n475gat);
not NOT_211(II468,n42gat);
not NOT_212(n50gat,II468);
not NOT_213(n162gat,n1013gat);
not NOT_214(II473,n162gat);
not NOT_215(n51gat,II473);
not NOT_216(II476,n475gat);
not NOT_217(n52gat,II476);
not NOT_218(II480,n258gat);
not NOT_219(n53gat,II480);
not NOT_220(n2520gat,n2522gat);
not NOT_221(n1448gat,n1376gat);
not NOT_222(n1701gat,n1617gat);
not NOT_223(n1379gat,n1377gat);
not NOT_224(n1615gat,n1624gat);
not NOT_225(n1500gat,n1113gat);
not NOT_226(n1503gat,n1501gat);
not NOT_227(n1779gat,n1623gat);
not NOT_228(II509,n3099gat);
not NOT_229(n2730gat,II509);
not NOT_230(II512,n2730gat);
not NOT_231(n2729gat,II512);
not NOT_232(n2470gat,n2472gat);
not NOT_233(n2317gat,n2319gat);
not NOT_234(n1819gat,n1821gat);
not NOT_235(n1823gat,n1825gat);
not NOT_236(n1816gat,n1817gat);
not NOT_237(n2027gat,n2029gat);
not NOT_238(II572,n1829gat);
not NOT_239(n1828gat,II572);
not NOT_240(II576,n3100gat);
not NOT_241(n2851gat,II576);
not NOT_242(II579,n2851gat);
not NOT_243(n2850gat,II579);
not NOT_244(II583,n2786gat);
not NOT_245(n2785gat,II583);
not NOT_246(n92gat,n2785gat);
not NOT_247(n637gat,n529gat);
not NOT_248(n293gat,n361gat);
not NOT_249(II591,n3094gat);
not NOT_250(n2722gat,II591);
not NOT_251(II594,n2722gat);
not NOT_252(n2721gat,II594);
not NOT_253(n297gat,n2721gat);
not NOT_254(II606,n283gat);
not NOT_255(n282gat,II606);
not NOT_256(II609,n282gat);
not NOT_257(n172gat,II609);
not NOT_258(II620,n165gat);
not NOT_259(n164gat,II620);
not NOT_260(II623,n164gat);
not NOT_261(n173gat,II623);
not NOT_262(II634,n279gat);
not NOT_263(n278gat,II634);
not NOT_264(II637,n278gat);
not NOT_265(n174gat,II637);
not NOT_266(n163gat,n165gat);
not NOT_267(II642,n163gat);
not NOT_268(n175gat,II642);
not NOT_269(n277gat,n279gat);
not NOT_270(II646,n277gat);
not NOT_271(n176gat,II646);
not NOT_272(n281gat,n283gat);
not NOT_273(II651,n281gat);
not NOT_274(n177gat,II651);
not NOT_275(n54gat,n167gat);
not NOT_276(II658,n54gat);
not NOT_277(n60gat,II658);
not NOT_278(II661,n845gat);
not NOT_279(n911gat,II661);
not NOT_280(II672,n1026gat);
not NOT_281(n1025gat,II672);
not NOT_282(II675,n1025gat);
not NOT_283(n912gat,II675);
not NOT_284(II678,n918gat);
not NOT_285(n913gat,II678);
not NOT_286(n1024gat,n1026gat);
not NOT_287(II683,n1024gat);
not NOT_288(n914gat,II683);
not NOT_289(n917gat,n919gat);
not NOT_290(II687,n917gat);
not NOT_291(n915gat,II687);
not NOT_292(n844gat,n846gat);
not NOT_293(II692,n844gat);
not NOT_294(n916gat,II692);
not NOT_295(II698,n906gat);
not NOT_296(n61gat,II698);
not NOT_297(II709,n275gat);
not NOT_298(n274gat,II709);
not NOT_299(II712,n274gat);
not NOT_300(n348gat,II712);
not NOT_301(II715,n401gat);
not NOT_302(n349gat,II715);
not NOT_303(II718,n398gat);
not NOT_304(n397gat,II718);
not NOT_305(II721,n397gat);
not NOT_306(n350gat,II721);
not NOT_307(n400gat,n402gat);
not NOT_308(II726,n400gat);
not NOT_309(n351gat,II726);
not NOT_310(II729,n396gat);
not NOT_311(n352gat,II729);
not NOT_312(n273gat,n275gat);
not NOT_313(II734,n273gat);
not NOT_314(n353gat,II734);
not NOT_315(n178gat,n343gat);
not NOT_316(II741,n178gat);
not NOT_317(n62gat,II741);
not NOT_318(n66gat,n906gat);
not NOT_319(II746,n66gat);
not NOT_320(n63gat,II746);
not NOT_321(II749,n343gat);
not NOT_322(n64gat,II749);
not NOT_323(II753,n167gat);
not NOT_324(n65gat,II753);
not NOT_325(n2474gat,n2476gat);
not NOT_326(II768,n3090gat);
not NOT_327(n2832gat,II768);
not NOT_328(II771,n2832gat);
not NOT_329(n2831gat,II771);
not NOT_330(n2731gat,n2733gat);
not NOT_331(II776,n3074gat);
not NOT_332(n2719gat,II776);
not NOT_333(n2718gat,n2719gat);
not NOT_334(II790,n1068gat);
not NOT_335(n1067gat,II790);
not NOT_336(II793,n1067gat);
not NOT_337(n949gat,II793);
not NOT_338(II796,n3076gat);
not NOT_339(n2839gat,II796);
not NOT_340(n2838gat,n2839gat);
not NOT_341(n2775gat,n2777gat);
not NOT_342(II812,n957gat);
not NOT_343(n956gat,II812);
not NOT_344(II815,n956gat);
not NOT_345(n950gat,II815);
not NOT_346(II818,n3075gat);
not NOT_347(n2712gat,II818);
not NOT_348(n2711gat,n2712gat);
not NOT_349(n2734gat,n2736gat);
not NOT_350(II834,n861gat);
not NOT_351(n860gat,II834);
not NOT_352(II837,n860gat);
not NOT_353(n951gat,II837);
not NOT_354(n955gat,n957gat);
not NOT_355(II842,n955gat);
not NOT_356(n952gat,II842);
not NOT_357(n859gat,n861gat);
not NOT_358(II846,n859gat);
not NOT_359(n953gat,II846);
not NOT_360(n1066gat,n1068gat);
not NOT_361(II851,n1066gat);
not NOT_362(n954gat,II851);
not NOT_363(n857gat,n944gat);
not NOT_364(II858,n857gat);
not NOT_365(n938gat,II858);
not NOT_366(n2792gat,n2794gat);
not NOT_367(II863,n3080gat);
not NOT_368(n2847gat,II863);
not NOT_369(n2846gat,n2847gat);
not NOT_370(II877,n1294gat);
not NOT_371(n1293gat,II877);
not NOT_372(II880,n1293gat);
not NOT_373(n1233gat,II880);
not NOT_374(n2672gat,n2674gat);
not NOT_375(II885,n3082gat);
not NOT_376(n2853gat,II885);
not NOT_377(n2852gat,n2853gat);
not NOT_378(II899,n1241gat);
not NOT_379(n1240gat,II899);
not NOT_380(II902,n1240gat);
not NOT_381(n1234gat,II902);
not NOT_382(II913,n1298gat);
not NOT_383(n1297gat,II913);
not NOT_384(II916,n1297gat);
not NOT_385(n1235gat,II916);
not NOT_386(n1239gat,n1241gat);
not NOT_387(II921,n1239gat);
not NOT_388(n1236gat,II921);
not NOT_389(n1296gat,n1298gat);
not NOT_390(II925,n1296gat);
not NOT_391(n1237gat,II925);
not NOT_392(n1292gat,n1294gat);
not NOT_393(II930,n1292gat);
not NOT_394(n1238gat,II930);
not NOT_395(II936,n1228gat);
not NOT_396(n939gat,II936);
not NOT_397(n2778gat,n2780gat);
not NOT_398(II941,n3077gat);
not NOT_399(n2837gat,II941);
not NOT_400(n2836gat,n2837gat);
not NOT_401(II955,n865gat);
not NOT_402(n864gat,II955);
not NOT_403(II958,n864gat);
not NOT_404(n1055gat,II958);
not NOT_405(n2789gat,n2791gat);
not NOT_406(II963,n3079gat);
not NOT_407(n2841gat,II963);
not NOT_408(n2840gat,n2841gat);
not NOT_409(II977,n1080gat);
not NOT_410(n1079gat,II977);
not NOT_411(II980,n1079gat);
not NOT_412(n1056gat,II980);
not NOT_413(n2781gat,n2783gat);
not NOT_414(II985,n3078gat);
not NOT_415(n2843gat,II985);
not NOT_416(n2842gat,n2843gat);
not NOT_417(II999,n1148gat);
not NOT_418(n1147gat,II999);
not NOT_419(II1002,n1147gat);
not NOT_420(n1057gat,II1002);
not NOT_421(n1078gat,n1080gat);
not NOT_422(II1007,n1078gat);
not NOT_423(n1058gat,II1007);
not NOT_424(n1146gat,n1148gat);
not NOT_425(II1011,n1146gat);
not NOT_426(n1059gat,II1011);
not NOT_427(n863gat,n865gat);
not NOT_428(II1016,n863gat);
not NOT_429(n1060gat,II1016);
not NOT_430(n928gat,n1050gat);
not NOT_431(II1023,n928gat);
not NOT_432(n940gat,II1023);
not NOT_433(n858gat,n1228gat);
not NOT_434(II1028,n858gat);
not NOT_435(n941gat,II1028);
not NOT_436(II1031,n1050gat);
not NOT_437(n942gat,II1031);
not NOT_438(II1035,n944gat);
not NOT_439(n943gat,II1035);
not NOT_440(n2466gat,n2468gat);
not NOT_441(n2720gat,n2722gat);
not NOT_442(n740gat,n2667gat);
not NOT_443(n2784gat,n2786gat);
not NOT_444(n743gat,n746gat);
not NOT_445(n294gat,n360gat);
not NOT_446(n374gat,n2767gat);
not NOT_447(n616gat,n618gat);
not NOT_448(II1067,n616gat);
not NOT_449(n501gat,II1067);
not NOT_450(n489gat,n491gat);
not NOT_451(II1079,n489gat);
not NOT_452(n502gat,II1079);
not NOT_453(II1082,n618gat);
not NOT_454(n617gat,II1082);
not NOT_455(II1085,n617gat);
not NOT_456(n499gat,II1085);
not NOT_457(II1088,n491gat);
not NOT_458(n490gat,II1088);
not NOT_459(II1091,n490gat);
not NOT_460(n500gat,II1091);
not NOT_461(n620gat,n622gat);
not NOT_462(II1103,n620gat);
not NOT_463(n738gat,II1103);
not NOT_464(n624gat,n626gat);
not NOT_465(II1115,n624gat);
not NOT_466(n737gat,II1115);
not NOT_467(II1118,n622gat);
not NOT_468(n621gat,II1118);
not NOT_469(II1121,n621gat);
not NOT_470(n733gat,II1121);
not NOT_471(II1124,n626gat);
not NOT_472(n625gat,II1124);
not NOT_473(II1127,n625gat);
not NOT_474(n735gat,II1127);
not NOT_475(II1138,n834gat);
not NOT_476(n833gat,II1138);
not NOT_477(II1141,n833gat);
not NOT_478(n714gat,II1141);
not NOT_479(II1152,n707gat);
not NOT_480(n706gat,II1152);
not NOT_481(II1155,n706gat);
not NOT_482(n715gat,II1155);
not NOT_483(II1166,n838gat);
not NOT_484(n837gat,II1166);
not NOT_485(II1169,n837gat);
not NOT_486(n716gat,II1169);
not NOT_487(n705gat,n707gat);
not NOT_488(II1174,n705gat);
not NOT_489(n717gat,II1174);
not NOT_490(n836gat,n838gat);
not NOT_491(II1178,n836gat);
not NOT_492(n718gat,II1178);
not NOT_493(n832gat,n834gat);
not NOT_494(II1183,n832gat);
not NOT_495(n719gat,II1183);
not NOT_496(n515gat,n709gat);
not NOT_497(II1190,n515gat);
not NOT_498(n509gat,II1190);
not NOT_499(II1201,n830gat);
not NOT_500(n829gat,II1201);
not NOT_501(II1204,n829gat);
not NOT_502(n734gat,II1204);
not NOT_503(n828gat,n830gat);
not NOT_504(II1209,n828gat);
not NOT_505(n736gat,II1209);
not NOT_506(II1216,n728gat);
not NOT_507(n510gat,II1216);
not NOT_508(II1227,n614gat);
not NOT_509(n613gat,II1227);
not NOT_510(II1230,n613gat);
not NOT_511(n498gat,II1230);
not NOT_512(n612gat,n614gat);
not NOT_513(II1236,n612gat);
not NOT_514(n503gat,II1236);
not NOT_515(n404gat,n493gat);
not NOT_516(II1243,n404gat);
not NOT_517(n511gat,II1243);
not NOT_518(n405gat,n728gat);
not NOT_519(II1248,n405gat);
not NOT_520(n512gat,II1248);
not NOT_521(II1251,n493gat);
not NOT_522(n513gat,II1251);
not NOT_523(II1255,n709gat);
not NOT_524(n514gat,II1255);
not NOT_525(n2524gat,n2526gat);
not NOT_526(n17gat,n564gat);
not NOT_527(n79gat,n86gat);
not NOT_528(n219gat,n78gat);
not NOT_529(n563gat,II1278);
not NOT_530(n289gat,n563gat);
not NOT_531(n179gat,n287gat);
not NOT_532(n188gat,n288gat);
not NOT_533(n72gat,n181gat);
not NOT_534(n111gat,n182gat);
not NOT_535(II1302,n680gat);
not NOT_536(n679gat,II1302);
not NOT_537(II1305,n679gat);
not NOT_538(n808gat,II1305);
not NOT_539(II1319,n816gat);
not NOT_540(n815gat,II1319);
not NOT_541(II1322,n815gat);
not NOT_542(n809gat,II1322);
not NOT_543(II1336,n580gat);
not NOT_544(n579gat,II1336);
not NOT_545(II1339,n579gat);
not NOT_546(n810gat,II1339);
not NOT_547(n814gat,n816gat);
not NOT_548(II1344,n814gat);
not NOT_549(n811gat,II1344);
not NOT_550(n578gat,n580gat);
not NOT_551(II1348,n578gat);
not NOT_552(n812gat,II1348);
not NOT_553(n678gat,n680gat);
not NOT_554(II1353,n678gat);
not NOT_555(n813gat,II1353);
not NOT_556(n677gat,n803gat);
not NOT_557(II1360,n677gat);
not NOT_558(n572gat,II1360);
not NOT_559(II1371,n824gat);
not NOT_560(n823gat,II1371);
not NOT_561(II1374,n823gat);
not NOT_562(n591gat,II1374);
not NOT_563(II1385,n820gat);
not NOT_564(n819gat,II1385);
not NOT_565(II1388,n819gat);
not NOT_566(n592gat,II1388);
not NOT_567(II1399,n883gat);
not NOT_568(n882gat,II1399);
not NOT_569(II1402,n882gat);
not NOT_570(n593gat,II1402);
not NOT_571(n818gat,n820gat);
not NOT_572(II1407,n818gat);
not NOT_573(n594gat,II1407);
not NOT_574(n881gat,n883gat);
not NOT_575(II1411,n881gat);
not NOT_576(n595gat,II1411);
not NOT_577(n822gat,n824gat);
not NOT_578(II1416,n822gat);
not NOT_579(n596gat,II1416);
not NOT_580(II1422,n586gat);
not NOT_581(n573gat,II1422);
not NOT_582(II1436,n584gat);
not NOT_583(n583gat,II1436);
not NOT_584(II1439,n583gat);
not NOT_585(n691gat,II1439);
not NOT_586(II1450,n684gat);
not NOT_587(n683gat,II1450);
not NOT_588(II1453,n683gat);
not NOT_589(n692gat,II1453);
not NOT_590(II1464,n699gat);
not NOT_591(n698gat,II1464);
not NOT_592(II1467,n698gat);
not NOT_593(n693gat,II1467);
not NOT_594(n682gat,n684gat);
not NOT_595(II1472,n682gat);
not NOT_596(n694gat,II1472);
not NOT_597(n697gat,n699gat);
not NOT_598(II1476,n697gat);
not NOT_599(n695gat,II1476);
not NOT_600(n582gat,n584gat);
not NOT_601(II1481,n582gat);
not NOT_602(n696gat,II1481);
not NOT_603(n456gat,n686gat);
not NOT_604(II1488,n456gat);
not NOT_605(n574gat,II1488);
not NOT_606(n565gat,n586gat);
not NOT_607(II1493,n565gat);
not NOT_608(n575gat,II1493);
not NOT_609(II1496,n686gat);
not NOT_610(n576gat,II1496);
not NOT_611(II1500,n803gat);
not NOT_612(n577gat,II1500);
not NOT_613(n2462gat,n2464gat);
not NOT_614(n2665gat,II1516);
not NOT_615(n2596gat,n2665gat);
not NOT_616(n189gat,n286gat);
not NOT_617(n194gat,n187gat);
not NOT_618(n21gat,n15gat);
not NOT_619(II1538,n2399gat);
not NOT_620(n2398gat,II1538);
not NOT_621(n2353gat,n2398gat);
not NOT_622(II1550,n2343gat);
not NOT_623(n2342gat,II1550);
not NOT_624(n2284gat,n2342gat);
not NOT_625(n2201gat,n2203gat);
not NOT_626(n2354gat,n2201gat);
not NOT_627(n2560gat,n2562gat);
not NOT_628(n2356gat,n2560gat);
not NOT_629(n2205gat,n2207gat);
not NOT_630(n2214gat,n2205gat);
not NOT_631(n2286gat,II1585);
not NOT_632(n2624gat,n2626gat);
not NOT_633(II1606,n2490gat);
not NOT_634(n2489gat,II1606);
not NOT_635(II1617,n2622gat);
not NOT_636(n2621gat,II1617);
not NOT_637(n2533gat,n2534gat);
not NOT_638(II1630,n2630gat);
not NOT_639(n2629gat,II1630);
not NOT_640(n2486gat,n2629gat);
not NOT_641(n2541gat,n2543gat);
not NOT_642(n2429gat,n2541gat);
not NOT_643(n2432gat,n2430gat);
not NOT_644(II1655,n2102gat);
not NOT_645(n2101gat,II1655);
not NOT_646(n1693gat,n2101gat);
not NOT_647(II1667,n1880gat);
not NOT_648(n1879gat,II1667);
not NOT_649(n1698gat,n1934gat);
not NOT_650(n1543gat,n1606gat);
not NOT_651(II1683,n1763gat);
not NOT_652(n1762gat,II1683);
not NOT_653(n1673gat,n2989gat);
not NOT_654(n1858gat,n1673gat);
not NOT_655(II1698,n2155gat);
not NOT_656(n2154gat,II1698);
not NOT_657(n2488gat,n2490gat);
not NOT_658(II1703,n2626gat);
not NOT_659(n2625gat,II1703);
not NOT_660(n2530gat,n2531gat);
not NOT_661(II1708,n2543gat);
not NOT_662(n2542gat,II1708);
not NOT_663(n2482gat,n2542gat);
not NOT_664(n2426gat,n2480gat);
not NOT_665(n2153gat,n2155gat);
not NOT_666(n2341gat,n2343gat);
not NOT_667(n2355gat,n2341gat);
not NOT_668(II1719,n2562gat);
not NOT_669(n2561gat,II1719);
not NOT_670(n2443gat,n2561gat);
not NOT_671(n2289gat,II1724);
not NOT_672(n2148gat,II1734);
not NOT_673(n855gat,n2148gat);
not NOT_674(n759gat,n855gat);
not NOT_675(II1749,n1035gat);
not NOT_676(n1034gat,II1749);
not NOT_677(II1752,n1034gat);
not NOT_678(n1189gat,II1752);
not NOT_679(n1075gat,n855gat);
not NOT_680(II1766,n1121gat);
not NOT_681(n1120gat,II1766);
not NOT_682(II1769,n1120gat);
not NOT_683(n1190gat,II1769);
not NOT_684(n760gat,n855gat);
not NOT_685(II1783,n1072gat);
not NOT_686(n1071gat,II1783);
not NOT_687(II1786,n1071gat);
not NOT_688(n1191gat,II1786);
not NOT_689(n1119gat,n1121gat);
not NOT_690(II1791,n1119gat);
not NOT_691(n1192gat,II1791);
not NOT_692(n1070gat,n1072gat);
not NOT_693(II1795,n1070gat);
not NOT_694(n1193gat,II1795);
not NOT_695(n1033gat,n1035gat);
not NOT_696(II1800,n1033gat);
not NOT_697(n1194gat,II1800);
not NOT_698(n1183gat,n1184gat);
not NOT_699(II1807,n1183gat);
not NOT_700(n1274gat,II1807);
not NOT_701(n644gat,n855gat);
not NOT_702(n1280gat,n1282gat);
not NOT_703(n641gat,n855gat);
not NOT_704(II1833,n1226gat);
not NOT_705(n1225gat,II1833);
not NOT_706(II1837,n1282gat);
not NOT_707(n1281gat,II1837);
not NOT_708(n1224gat,n1226gat);
not NOT_709(II1843,n2970gat);
not NOT_710(n1275gat,II1843);
not NOT_711(n761gat,n855gat);
not NOT_712(II1857,n931gat);
not NOT_713(n930gat,II1857);
not NOT_714(II1860,n930gat);
not NOT_715(n1206gat,II1860);
not NOT_716(n762gat,n855gat);
not NOT_717(II1874,n1135gat);
not NOT_718(n1134gat,II1874);
not NOT_719(II1877,n1134gat);
not NOT_720(n1207gat,II1877);
not NOT_721(n643gat,n855gat);
not NOT_722(II1891,n1045gat);
not NOT_723(n1044gat,II1891);
not NOT_724(II1894,n1044gat);
not NOT_725(n1208gat,II1894);
not NOT_726(n1133gat,n1135gat);
not NOT_727(II1899,n1133gat);
not NOT_728(n1209gat,II1899);
not NOT_729(n1043gat,n1045gat);
not NOT_730(II1903,n1043gat);
not NOT_731(n1210gat,II1903);
not NOT_732(n929gat,n931gat);
not NOT_733(II1908,n929gat);
not NOT_734(n1211gat,II1908);
not NOT_735(n1268gat,n1201gat);
not NOT_736(II1915,n1268gat);
not NOT_737(n1276gat,II1915);
not NOT_738(n1329gat,n2970gat);
not NOT_739(II1920,n1329gat);
not NOT_740(n1277gat,II1920);
not NOT_741(II1923,n1201gat);
not NOT_742(n1278gat,II1923);
not NOT_743(II1927,n1184gat);
not NOT_744(n1279gat,II1927);
not NOT_745(n1284gat,n1269gat);
not NOT_746(n642gat,n855gat);
not NOT_747(n1195gat,n1197gat);
not NOT_748(II1947,n1197gat);
not NOT_749(n1196gat,II1947);
not NOT_750(n2516gat,n2518gat);
not NOT_751(II1961,n2516gat);
not NOT_752(n3017gat,II1961);
not NOT_753(n851gat,n853gat);
not NOT_754(n1725gat,n2148gat);
not NOT_755(n664gat,n1725gat);
not NOT_756(n852gat,n854gat);
not NOT_757(II1981,n667gat);
not NOT_758(n666gat,II1981);
not NOT_759(n368gat,n1725gat);
not NOT_760(II1996,n659gat);
not NOT_761(n658gat,II1996);
not NOT_762(II1999,n658gat);
not NOT_763(n784gat,II1999);
not NOT_764(n662gat,n1725gat);
not NOT_765(II2014,n553gat);
not NOT_766(n552gat,II2014);
not NOT_767(II2017,n552gat);
not NOT_768(n785gat,II2017);
not NOT_769(n661gat,n1725gat);
not NOT_770(II2032,n777gat);
not NOT_771(n776gat,II2032);
not NOT_772(II2035,n776gat);
not NOT_773(n786gat,II2035);
not NOT_774(n551gat,n553gat);
not NOT_775(II2040,n551gat);
not NOT_776(n787gat,II2040);
not NOT_777(n775gat,n777gat);
not NOT_778(II2044,n775gat);
not NOT_779(n788gat,II2044);
not NOT_780(n657gat,n659gat);
not NOT_781(II2049,n657gat);
not NOT_782(n789gat,II2049);
not NOT_783(n35gat,n779gat);
not NOT_784(II2056,n35gat);
not NOT_785(n125gat,II2056);
not NOT_786(n558gat,n1725gat);
not NOT_787(n559gat,n561gat);
not NOT_788(n371gat,n1725gat);
not NOT_789(II2084,n366gat);
not NOT_790(n365gat,II2084);
not NOT_791(II2088,n561gat);
not NOT_792(n560gat,II2088);
not NOT_793(n364gat,n366gat);
not NOT_794(II2094,n2876gat);
not NOT_795(n126gat,II2094);
not NOT_796(n663gat,n1725gat);
not NOT_797(II2109,n322gat);
not NOT_798(n321gat,II2109);
not NOT_799(II2112,n321gat);
not NOT_800(n226gat,II2112);
not NOT_801(n370gat,n1725gat);
not NOT_802(II2127,n318gat);
not NOT_803(n317gat,II2127);
not NOT_804(II2130,n317gat);
not NOT_805(n227gat,II2130);
not NOT_806(n369gat,n1725gat);
not NOT_807(II2145,n314gat);
not NOT_808(n313gat,II2145);
not NOT_809(II2148,n313gat);
not NOT_810(n228gat,II2148);
not NOT_811(n316gat,n318gat);
not NOT_812(II2153,n316gat);
not NOT_813(n229gat,II2153);
not NOT_814(n312gat,n314gat);
not NOT_815(II2157,n312gat);
not NOT_816(n230gat,II2157);
not NOT_817(n320gat,n322gat);
not NOT_818(II2162,n320gat);
not NOT_819(n231gat,II2162);
not NOT_820(n34gat,n221gat);
not NOT_821(II2169,n34gat);
not NOT_822(n127gat,II2169);
not NOT_823(n133gat,n2876gat);
not NOT_824(II2174,n133gat);
not NOT_825(n128gat,II2174);
not NOT_826(II2177,n221gat);
not NOT_827(n129gat,II2177);
not NOT_828(II2181,n779gat);
not NOT_829(n130gat,II2181);
not NOT_830(n665gat,n667gat);
not NOT_831(n1601gat,n120gat);
not NOT_832(n2597gat,n2599gat);
not NOT_833(n2595gat,n2594gat);
not NOT_834(n2586gat,n2588gat);
not NOT_835(II2213,n2342gat);
not NOT_836(n2573gat,II2213);
not NOT_837(n2638gat,n2640gat);
not NOT_838(II2225,n2638gat);
not NOT_839(n2574gat,II2225);
not NOT_840(II2228,n2561gat);
not NOT_841(n2575gat,II2228);
not NOT_842(II2232,n2640gat);
not NOT_843(n2639gat,II2232);
not NOT_844(II2235,n2639gat);
not NOT_845(n2576gat,II2235);
not NOT_846(II2238,n2560gat);
not NOT_847(n2577gat,II2238);
not NOT_848(II2242,n2341gat);
not NOT_849(n2578gat,II2242);
not NOT_850(II2248,n2568gat);
not NOT_851(n2582gat,II2248);
not NOT_852(II2251,n2207gat);
not NOT_853(n2206gat,II2251);
not NOT_854(II2254,n2206gat);
not NOT_855(n2414gat,II2254);
not NOT_856(II2257,n2398gat);
not NOT_857(n2415gat,II2257);
not NOT_858(II2260,n2203gat);
not NOT_859(n2202gat,II2260);
not NOT_860(II2263,n2202gat);
not NOT_861(n2416gat,II2263);
not NOT_862(n2397gat,n2399gat);
not NOT_863(II2268,n2397gat);
not NOT_864(n2417gat,II2268);
not NOT_865(II2271,n2201gat);
not NOT_866(n2418gat,II2271);
not NOT_867(II2275,n2205gat);
not NOT_868(n2419gat,II2275);
not NOT_869(II2281,n2409gat);
not NOT_870(n2585gat,II2281);
not NOT_871(n2656gat,n2658gat);
not NOT_872(n2493gat,n2495gat);
not NOT_873(n2388gat,n2390gat);
not NOT_874(II2316,n2390gat);
not NOT_875(n2389gat,II2316);
not NOT_876(II2319,n2495gat);
not NOT_877(n2494gat,II2319);
not NOT_878(II2324,n3014gat);
not NOT_879(n2649gat,II2324);
not NOT_880(n2268gat,n2270gat);
not NOT_881(II2344,n2339gat);
not NOT_882(n2338gat,II2344);
not NOT_883(n2337gat,n2339gat);
not NOT_884(II2349,n2270gat);
not NOT_885(n2269gat,II2349);
not NOT_886(II2354,n2880gat);
not NOT_887(n2652gat,II2354);
not NOT_888(n2500gat,n2502gat);
not NOT_889(n2620gat,n2622gat);
not NOT_890(n2612gat,n2620gat);
not NOT_891(II2372,n2612gat);
not NOT_892(n2606gat,II2372);
not NOT_893(n2532gat,n2625gat);
not NOT_894(II2376,n2532gat);
not NOT_895(n2607gat,II2376);
not NOT_896(n2540gat,n2488gat);
not NOT_897(II2380,n2540gat);
not NOT_898(n2608gat,II2380);
not NOT_899(n2536gat,n2624gat);
not NOT_900(II2385,n2536gat);
not NOT_901(n2609gat,II2385);
not NOT_902(n2487gat,n2489gat);
not NOT_903(II2389,n2487gat);
not NOT_904(n2610gat,II2389);
not NOT_905(n2557gat,n2621gat);
not NOT_906(II2394,n2557gat);
not NOT_907(n2611gat,II2394);
not NOT_908(II2400,n2601gat);
not NOT_909(n2616gat,II2400);
not NOT_910(II2403,n2629gat);
not NOT_911(n2550gat,II2403);
not NOT_912(II2414,n2634gat);
not NOT_913(n2633gat,II2414);
not NOT_914(II2417,n2633gat);
not NOT_915(n2551gat,II2417);
not NOT_916(II2420,n2542gat);
not NOT_917(n2552gat,II2420);
not NOT_918(n2632gat,n2634gat);
not NOT_919(II2425,n2632gat);
not NOT_920(n2553gat,II2425);
not NOT_921(II2428,n2541gat);
not NOT_922(n2554gat,II2428);
not NOT_923(n2628gat,n2630gat);
not NOT_924(II2433,n2628gat);
not NOT_925(n2555gat,II2433);
not NOT_926(II2439,n2545gat);
not NOT_927(n2619gat,II2439);
not NOT_928(n2504gat,n2506gat);
not NOT_929(n2660gat,n2655gat);
not NOT_930(n1528gat,n2293gat);
not NOT_931(n1523gat,n2219gat);
not NOT_932(n1592gat,n1529gat);
not NOT_933(n2666gat,n1704gat);
not NOT_934(n2422gat,n3013gat);
not NOT_935(n2290gat,n2202gat);
not NOT_936(n2081gat,n2218gat);
not NOT_937(n2285gat,n2397gat);
not NOT_938(n2359gat,n2358gat);
not NOT_939(n1414gat,n1415gat);
not NOT_940(n566gat,n364gat);
not NOT_941(n1480gat,n2292gat);
not NOT_942(n1301gat,n1416gat);
not NOT_943(n1150gat,n312gat);
not NOT_944(n873gat,n316gat);
not NOT_945(n2011gat,n2306gat);
not NOT_946(n1478gat,n1481gat);
not NOT_947(n875gat,n559gat);
not NOT_948(n1410gat,n2357gat);
not NOT_949(n876gat,n1347gat);
not NOT_950(n1160gat,n1484gat);
not NOT_951(n1084gat,n657gat);
not NOT_952(n983gat,n320gat);
not NOT_953(n1482gat,n2363gat);
not NOT_954(n1157gat,n1483gat);
not NOT_955(n985gat,n775gat);
not NOT_956(n1530gat,n2364gat);
not NOT_957(n1307gat,n1308gat);
not NOT_958(n1085gat,n551gat);
not NOT_959(n1479gat,n2291gat);
not NOT_960(n1348gat,n1349gat);
not NOT_961(n2217gat,n2206gat);
not NOT_962(n1591gat,n2223gat);
not NOT_963(n1437gat,n1438gat);
not NOT_964(n1832gat,n1834gat);
not NOT_965(n1765gat,n1767gat);
not NOT_966(n1878gat,n1880gat);
not NOT_967(n1442gat,n1831gat);
not NOT_968(n1444gat,n1442gat);
not NOT_969(n1378gat,n2975gat);
not NOT_970(n1322gat,n2974gat);
not NOT_971(n1439gat,n1486gat);
not NOT_972(n1370gat,n1426gat);
not NOT_973(n1369gat,n2966gat);
not NOT_974(n1366gat,n1365gat);
not NOT_975(n1374gat,n2979gat);
not NOT_976(n2162gat,n2220gat);
not NOT_977(n1450gat,n1423gat);
not NOT_978(n1427gat,n1608gat);
not NOT_979(n1603gat,n1831gat);
not NOT_980(n2082gat,n2084gat);
not NOT_981(n1449gat,n1494gat);
not NOT_982(n1590gat,n1603gat);
not NOT_983(n1248gat,n2954gat);
not NOT_984(n1418gat,n1417gat);
not NOT_985(n1306gat,n2964gat);
not NOT_986(n1353gat,n1419gat);
not NOT_987(n1247gat,n2958gat);
not NOT_988(n1355gat,n1422gat);
not NOT_989(n1300gat,n2963gat);
not NOT_990(n1487gat,n1485gat);
not NOT_991(n1164gat,n2953gat);
not NOT_992(n1356gat,n1354gat);
not NOT_993(n1436gat,n1435gat);
not NOT_994(n1106gat,n2949gat);
not NOT_995(n1425gat,n1421gat);
not NOT_996(n1105gat,n2934gat);
not NOT_997(n1424gat,n1420gat);
not NOT_998(n1309gat,n2959gat);
not NOT_999(II2672,n2143gat);
not NOT_1000(n2142gat,II2672);
not NOT_1001(n1788gat,n2142gat);
not NOT_1002(II2684,n2061gat);
not NOT_1003(n2060gat,II2684);
not NOT_1004(n1786gat,n2060gat);
not NOT_1005(II2696,n2139gat);
not NOT_1006(n2138gat,II2696);
not NOT_1007(n1839gat,n2138gat);
not NOT_1008(n1897gat,n1899gat);
not NOT_1009(n1884gat,n1897gat);
not NOT_1010(n1848gat,n1850gat);
not NOT_1011(n1783gat,n1848gat);
not NOT_1012(n1548gat,II2721);
not NOT_1013(n1719gat,n1548gat);
not NOT_1014(n2137gat,n2139gat);
not NOT_1015(n1633gat,n2137gat);
not NOT_1016(n2059gat,n2061gat);
not NOT_1017(n1785gat,n2059gat);
not NOT_1018(II2731,n1850gat);
not NOT_1019(n1849gat,II2731);
not NOT_1020(n1784gat,n1849gat);
not NOT_1021(n1716gat,II2736);
not NOT_1022(n1635gat,n1716gat);
not NOT_1023(n2401gat,n2403gat);
not NOT_1024(n1989gat,n2401gat);
not NOT_1025(n2392gat,n2394gat);
not NOT_1026(n1918gat,n2392gat);
not NOT_1027(II2771,n2440gat);
not NOT_1028(n2439gat,II2771);
not NOT_1029(n1986gat,n2439gat);
not NOT_1030(n1866gat,n1865gat);
not NOT_1031(II2785,n2407gat);
not NOT_1032(n2406gat,II2785);
not NOT_1033(n2216gat,n2406gat);
not NOT_1034(n2345gat,n2347gat);
not NOT_1035(n1988gat,n2345gat);
not NOT_1036(n1735gat,n1861gat);
not NOT_1037(n1387gat,n1389gat);
not NOT_1038(n1694gat,II2813);
not NOT_1039(n1777gat,n1694gat);
not NOT_1040(n1781gat,n1780gat);
not NOT_1041(n2019gat,n2021gat);
not NOT_1042(n1549gat,II2832);
not NOT_1043(n1551gat,n1549gat);
not NOT_1044(II2837,n2347gat);
not NOT_1045(n2346gat,II2837);
not NOT_1046(n2152gat,n2346gat);
not NOT_1047(n2405gat,n2407gat);
not NOT_1048(n2351gat,n2405gat);
not NOT_1049(II2843,n2403gat);
not NOT_1050(n2402gat,II2843);
not NOT_1051(n2212gat,n2402gat);
not NOT_1052(II2847,n2394gat);
not NOT_1053(n2393gat,II2847);
not NOT_1054(n1991gat,n2393gat);
not NOT_1055(n1665gat,n1666gat);
not NOT_1056(n1517gat,n1578gat);
not NOT_1057(n1392gat,n1394gat);
not NOT_1058(II2873,n1496gat);
not NOT_1059(n1495gat,II2873);
not NOT_1060(n1685gat,n1604gat);
not NOT_1061(II2885,n2091gat);
not NOT_1062(n2090gat,II2885);
not NOT_1063(n1550gat,II2890);
not NOT_1064(n1552gat,n1550gat);
not NOT_1065(n1330gat,n1332gat);
not NOT_1066(n1738gat,n1740gat);
not NOT_1067(II2915,n1740gat);
not NOT_1068(n1739gat,II2915);
not NOT_1069(n1925gat,n1920gat);
not NOT_1070(n1917gat,n1921gat);
not NOT_1071(n2141gat,n2143gat);
not NOT_1072(n1787gat,n2141gat);
not NOT_1073(n1717gat,II2926);
not NOT_1074(n1859gat,n1717gat);
not NOT_1075(n1922gat,n1798gat);
not NOT_1076(n1713gat,II2935);
not NOT_1077(n1743gat,n1713gat);
not NOT_1078(n1923gat,n1864gat);
not NOT_1079(n1945gat,n1690gat);
not NOT_1080(II2953,n2179gat);
not NOT_1081(n2178gat,II2953);
not NOT_1082(n1661gat,n1660gat);
not NOT_1083(n1572gat,n1576gat);
not NOT_1084(n2438gat,n2440gat);
not NOT_1085(n2283gat,n2438gat);
not NOT_1086(n1520gat,n1582gat);
not NOT_1087(n1580gat,n1577gat);
not NOT_1088(n1990gat,n2988gat);
not NOT_1089(II2978,n2190gat);
not NOT_1090(n2189gat,II2978);
not NOT_1091(II2989,n2135gat);
not NOT_1092(n2134gat,II2989);
not NOT_1093(II3000,n2262gat);
not NOT_1094(n2261gat,II3000);
not NOT_1095(n2128gat,n2129gat);
not NOT_1096(n1836gat,n1695gat);
not NOT_1097(II3016,n2182gat);
not NOT_1098(n2181gat,II3016);
not NOT_1099(n1431gat,n1433gat);
not NOT_1100(n1314gat,n1316gat);
not NOT_1101(n1361gat,n1363gat);
not NOT_1102(II3056,n1312gat);
not NOT_1103(n1311gat,II3056);
not NOT_1104(n1707gat,n1626gat);
not NOT_1105(n1773gat,n1775gat);
not NOT_1106(n1659gat,n2987gat);
not NOT_1107(n1515gat,n1521gat);
not NOT_1108(n1736gat,n1737gat);
not NOT_1109(n1658gat,n2216gat);
not NOT_1110(n1724gat,n1732gat);
not NOT_1111(n1662gat,n1663gat);
not NOT_1112(n1656gat,n1655gat);
not NOT_1113(n1670gat,n1667gat);
not NOT_1114(n1569gat,n1570gat);
not NOT_1115(n1568gat,n1575gat);
not NOT_1116(n1727gat,n1728gat);
not NOT_1117(n1797gat,n1801gat);
not NOT_1118(n1730gat,n1731gat);
not NOT_1119(n1561gat,n1571gat);
not NOT_1120(n1668gat,n1734gat);
not NOT_1121(n1742gat,n2216gat);
not NOT_1122(n1671gat,n1669gat);
not NOT_1123(n1652gat,n1657gat);
not NOT_1124(n1648gat,n1729gat);
not NOT_1125(n1790gat,n1726gat);
not NOT_1126(n2004gat,n1929gat);
not NOT_1127(n1869gat,n1871gat);
not NOT_1128(II3143,n2592gat);
not NOT_1129(n2591gat,II3143);
not NOT_1130(n1584gat,n2989gat);
not NOT_1131(n1714gat,II3149);
not NOT_1132(n1718gat,n1714gat);
not NOT_1133(II3163,n1508gat);
not NOT_1134(n1507gat,II3163);
not NOT_1135(n1396gat,n1401gat);
not NOT_1136(II3168,n1394gat);
not NOT_1137(n1393gat,II3168);
not NOT_1138(n1409gat,n1476gat);
not NOT_1139(II3174,n1899gat);
not NOT_1140(n1898gat,II3174);
not NOT_1141(n1838gat,n1898gat);
not NOT_1142(n1712gat,II3179);
not NOT_1143(II3191,n1678gat);
not NOT_1144(n1677gat,II3191);
not NOT_1145(n2000gat,n1412gat);
not NOT_1146(n2001gat,n1412gat);
not NOT_1147(n1999gat,n2001gat);
not NOT_1148(n2307gat,n2309gat);
not NOT_1149(II3211,n2663gat);
not NOT_1150(n3018gat,II3211);
not NOT_1151(n2448gat,n2450gat);
not NOT_1152(n2661gat,n2662gat);
not NOT_1153(n2444gat,n2446gat);
not NOT_1154(II3235,n2238gat);
not NOT_1155(n3019gat,II3235);
not NOT_1156(n1310gat,n1312gat);
not NOT_1157(n199gat,n87gat);
not NOT_1158(n195gat,n184gat);
not NOT_1159(n827gat,n204gat);
not NOT_1160(n2093gat,n2095gat);
not NOT_1161(n2174gat,n2176gat);
not NOT_1162(II3273,n2169gat);
not NOT_1163(n2168gat,II3273);
not NOT_1164(n2452gat,n2454gat);
not NOT_1165(n1691gat,n2452gat);
not NOT_1166(II3287,n1691gat);
not NOT_1167(n3020gat,II3287);
not NOT_1168(II3290,n1691gat);
not NOT_1169(n3021gat,II3290);
not NOT_1170(II3293,n1691gat);
not NOT_1171(n3022gat,II3293);
not NOT_1172(n1699gat,n2452gat);
not NOT_1173(II3297,n1699gat);
not NOT_1174(n3023gat,II3297);
not NOT_1175(II3300,n1699gat);
not NOT_1176(n3024gat,II3300);
not NOT_1177(II3303,n1691gat);
not NOT_1178(n3025gat,II3303);
not NOT_1179(II3306,n1699gat);
not NOT_1180(n3026gat,II3306);
not NOT_1181(II3309,n1699gat);
not NOT_1182(n3027gat,II3309);
not NOT_1183(II3312,n1699gat);
not NOT_1184(n3028gat,II3312);
not NOT_1185(II3315,n1869gat);
not NOT_1186(n3029gat,II3315);
not NOT_1187(II3318,n1869gat);
not NOT_1188(n3030gat,II3318);
not NOT_1189(n2260gat,n2262gat);
not NOT_1190(n2257gat,n2189gat);
not NOT_1191(n2188gat,n2190gat);
not NOT_1192(n2187gat,n3004gat);
not NOT_1193(II3336,n2040gat);
not NOT_1194(n2039gat,II3336);
not NOT_1195(II3339,n1775gat);
not NOT_1196(n1774gat,II3339);
not NOT_1197(II3342,n1316gat);
not NOT_1198(n1315gat,II3342);
not NOT_1199(n2042gat,n2044gat);
not NOT_1200(n2035gat,n2037gat);
not NOT_1201(n2023gat,n2025gat);
not NOT_1202(n2097gat,n2099gat);
not NOT_1203(n1855gat,n2014gat);
not NOT_1204(II3387,n2194gat);
not NOT_1205(n3031gat,II3387);
not NOT_1206(II3390,n2261gat);
not NOT_1207(n3032gat,II3390);
not NOT_1208(n2256gat,n3032gat);
not NOT_1209(II3394,n2260gat);
not NOT_1210(n3033gat,II3394);
not NOT_1211(n2251gat,n3033gat);
not NOT_1212(n2184gat,n3003gat);
not NOT_1213(II3401,n2192gat);
not NOT_1214(n3034gat,II3401);
not NOT_1215(n2133gat,n2135gat);
not NOT_1216(n2131gat,n2185gat);
not NOT_1217(n2049gat,n3001gat);
not NOT_1218(II3412,n2057gat);
not NOT_1219(n3035gat,II3412);
not NOT_1220(n2253gat,n2189gat);
not NOT_1221(n2252gat,n2260gat);
not NOT_1222(n2248gat,n3006gat);
not NOT_1223(n2264gat,n2266gat);
not NOT_1224(II3429,n2266gat);
not NOT_1225(n2265gat,II3429);
not NOT_1226(n2492gat,n2329gat);
not NOT_1227(II3436,n2492gat);
not NOT_1228(n3036gat,II3436);
not NOT_1229(n1709gat,n1849gat);
not NOT_1230(n1845gat,n2141gat);
not NOT_1231(n1891gat,n2059gat);
not NOT_1232(n1963gat,n2137gat);
not NOT_1233(n1886gat,n1897gat);
not NOT_1234(n1968gat,n1958gat);
not NOT_1235(n1629gat,n1895gat);
not NOT_1236(n1631gat,n1848gat);
not NOT_1237(n1711gat,n2990gat);
not NOT_1238(n2200gat,n2078gat);
not NOT_1239(n2437gat,n2195gat);
not NOT_1240(II3457,n2556gat);
not NOT_1241(n3037gat,II3457);
not NOT_1242(n1956gat,n1898gat);
not NOT_1243(II3461,n1956gat);
not NOT_1244(n3038gat,II3461);
not NOT_1245(n1954gat,n3038gat);
not NOT_1246(II3465,n1886gat);
not NOT_1247(n3039gat,II3465);
not NOT_1248(n1888gat,n3039gat);
not NOT_1249(n2048gat,n2994gat);
not NOT_1250(II3472,n2539gat);
not NOT_1251(n3040gat,II3472);
not NOT_1252(n1969gat,n2142gat);
not NOT_1253(n1893gat,n2060gat);
not NOT_1254(n1892gat,n2993gat);
not NOT_1255(II3483,n2436gat);
not NOT_1256(n3041gat,II3483);
not NOT_1257(n2056gat,n2998gat);
not NOT_1258(II3491,n2387gat);
not NOT_1259(n3042gat,II3491);
not NOT_1260(II3494,n1963gat);
not NOT_1261(n3043gat,II3494);
not NOT_1262(n1960gat,n3043gat);
not NOT_1263(n1887gat,n2138gat);
not NOT_1264(n1961gat,n2996gat);
not NOT_1265(II3504,n2330gat);
not NOT_1266(n3044gat,II3504);
not NOT_1267(n2199gat,n2147gat);
not NOT_1268(II3509,n2438gat);
not NOT_1269(n3045gat,II3509);
not NOT_1270(n2332gat,n3045gat);
not NOT_1271(II3513,n2439gat);
not NOT_1272(n3046gat,II3513);
not NOT_1273(n2259gat,n3046gat);
not NOT_1274(n2328gat,n3008gat);
not NOT_1275(II3520,n2498gat);
not NOT_1276(n3047gat,II3520);
not NOT_1277(n2151gat,n2193gat);
not NOT_1278(n2209gat,n3005gat);
not NOT_1279(II3530,n2396gat);
not NOT_1280(n3048gat,II3530);
not NOT_1281(n2052gat,n2393gat);
not NOT_1282(n2058gat,n2997gat);
not NOT_1283(II3539,n2198gat);
not NOT_1284(n3049gat,II3539);
not NOT_1285(n2349gat,n2215gat);
not NOT_1286(n2281gat,n3009gat);
not NOT_1287(II3549,n2197gat);
not NOT_1288(n3050gat,II3549);
not NOT_1289(n2146gat,n3002gat);
not NOT_1290(II3558,n2196gat);
not NOT_1291(n3051gat,II3558);
not NOT_1292(n2031gat,n2033gat);
not NOT_1293(n2108gat,n2110gat);
not NOT_1294(II3587,n2125gat);
not NOT_1295(n2124gat,II3587);
not NOT_1296(n2123gat,n2125gat);
not NOT_1297(n2119gat,n2121gat);
not NOT_1298(n2115gat,n2117gat);
not NOT_1299(II3610,n1882gat);
not NOT_1300(n3052gat,II3610);
not NOT_1301(II3621,n1975gat);
not NOT_1302(n1974gat,II3621);
not NOT_1303(n1955gat,n1956gat);
not NOT_1304(n1970gat,n1896gat);
not NOT_1305(n1973gat,n1975gat);
not NOT_1306(n2558gat,n2559gat);
not NOT_1307(II3635,n2558gat);
not NOT_1308(n3053gat,II3635);
not NOT_1309(II3646,n2644gat);
not NOT_1310(n2643gat,II3646);
not NOT_1311(n2333gat,n2438gat);
not NOT_1312(n2564gat,n2352gat);
not NOT_1313(n2642gat,n2644gat);
not NOT_1314(n2636gat,n2637gat);
not NOT_1315(II3660,n2636gat);
not NOT_1316(n3054gat,II3660);
not NOT_1317(n88gat,n84gat);
not NOT_1318(n375gat,n110gat);
not NOT_1319(II3677,n156gat);
not NOT_1320(n155gat,II3677);
not NOT_1321(n253gat,n1702gat);
not NOT_1322(n150gat,n152gat);
not NOT_1323(II3691,n152gat);
not NOT_1324(n151gat,II3691);
not NOT_1325(n243gat,n1702gat);
not NOT_1326(n233gat,n243gat);
not NOT_1327(n154gat,n156gat);
not NOT_1328(n800gat,n2874gat);
not NOT_1329(II3703,n2917gat);
not NOT_1330(n3055gat,II3703);
not NOT_1331(n235gat,n2878gat);
not NOT_1332(II3713,n2892gat);
not NOT_1333(n3056gat,II3713);
not NOT_1334(n372gat,n212gat);
not NOT_1335(n329gat,n331gat);
not NOT_1336(II3736,n388gat);
not NOT_1337(n387gat,II3736);
not NOT_1338(n334gat,n1700gat);
not NOT_1339(n386gat,n388gat);
not NOT_1340(II3742,n331gat);
not NOT_1341(n330gat,II3742);
not NOT_1342(n1430gat,n1700gat);
not NOT_1343(n1490gat,n1430gat);
not NOT_1344(n452gat,n2885gat);
not NOT_1345(II3754,n2900gat);
not NOT_1346(n3057gat,II3754);
not NOT_1347(n333gat,n2883gat);
not NOT_1348(II3765,n2929gat);
not NOT_1349(n3058gat,II3765);
not NOT_1350(II3777,n463gat);
not NOT_1351(n462gat,II3777);
not NOT_1352(n325gat,n327gat);
not NOT_1353(n457gat,n2884gat);
not NOT_1354(n461gat,n463gat);
not NOT_1355(n458gat,n2902gat);
not NOT_1356(II3801,n2925gat);
not NOT_1357(n3059gat,II3801);
not NOT_1358(n144gat,n247gat);
not NOT_1359(II3808,n327gat);
not NOT_1360(n326gat,II3808);
not NOT_1361(n878gat,n2879gat);
not NOT_1362(II3817,n2916gat);
not NOT_1363(n3060gat,II3817);
not NOT_1364(n382gat,n384gat);
not NOT_1365(II3831,n384gat);
not NOT_1366(n383gat,II3831);
not NOT_1367(n134gat,n2875gat);
not NOT_1368(II3841,n2899gat);
not NOT_1369(n3061gat,II3841);
not NOT_1370(n254gat,n256gat);
not NOT_1371(n252gat,n2877gat);
not NOT_1372(n468gat,n470gat);
not NOT_1373(II3867,n470gat);
not NOT_1374(n469gat,II3867);
not NOT_1375(n381gat,n2893gat);
not NOT_1376(II3876,n2926gat);
not NOT_1377(n3062gat,II3876);
not NOT_1378(n241gat,n140gat);
not NOT_1379(II3882,n256gat);
not NOT_1380(n255gat,II3882);
not NOT_1381(n802gat,n2882gat);
not NOT_1382(II3891,n2924gat);
not NOT_1383(n3063gat,II3891);
not NOT_1384(n146gat,n148gat);
not NOT_1385(II3904,n148gat);
not NOT_1386(n147gat,II3904);
not NOT_1387(n380gat,n2881gat);
not NOT_1388(II3914,n2923gat);
not NOT_1389(n3064gat,II3914);
not NOT_1390(n69gat,n68gat);
not NOT_1391(n1885gat,n2048gat);
not NOT_1392(II3923,n2710gat);
not NOT_1393(n2707gat,II3923);
not NOT_1394(n16gat,n564gat);
not NOT_1395(n295gat,n357gat);
not NOT_1396(n11gat,n12gat);
not NOT_1397(n1889gat,n1961gat);
not NOT_1398(II3935,n2704gat);
not NOT_1399(n2700gat,II3935);
not NOT_1400(n2051gat,n2056gat);
not NOT_1401(II3941,n2684gat);
not NOT_1402(n2680gat,II3941);
not NOT_1403(n1350gat,n1831gat);
not NOT_1404(II3945,n1350gat);
not NOT_1405(n2696gat,II3945);
not NOT_1406(II3948,n2696gat);
not NOT_1407(n2692gat,II3948);
not NOT_1408(II3951,n2448gat);
not NOT_1409(n2683gat,II3951);
not NOT_1410(II3954,n2683gat);
not NOT_1411(n2679gat,II3954);
not NOT_1412(II3957,n2450gat);
not NOT_1413(n2449gat,II3957);
not NOT_1414(n1754gat,n2449gat);
not NOT_1415(II3962,n2830gat);
not NOT_1416(n2827gat,II3962);
not NOT_1417(n2590gat,n2592gat);
not NOT_1418(n2456gat,n2458gat);
not NOT_1419(n2512gat,n2514gat);
not NOT_1420(n1544gat,n1625gat);
not NOT_1421(n1769gat,n1771gat);
not NOT_1422(n1683gat,n1756gat);
not NOT_1423(n2167gat,n2169gat);
not NOT_1424(n2013gat,II4000);
not NOT_1425(n1791gat,n2013gat);
not NOT_1426(n2691gat,n2695gat);
not NOT_1427(n1518gat,n1694gat);
not NOT_1428(n2699gat,n2703gat);
not NOT_1429(n2159gat,n1412gat);
not NOT_1430(n2478gat,n2579gat);
not NOT_1431(II4014,n2744gat);
not NOT_1432(n2740gat,II4014);
not NOT_1433(n2158gat,n1412gat);
not NOT_1434(n2186gat,n2613gat);
not NOT_1435(II4020,n2800gat);
not NOT_1436(n2797gat,II4020);
not NOT_1437(n2288gat,II4024);
not NOT_1438(n1513gat,n2288gat);
not NOT_1439(n2537gat,n2538gat);
not NOT_1440(n2442gat,n2483gat);
not NOT_1441(n1334gat,n1336gat);
not NOT_1442(II4055,n1748gat);
not NOT_1443(n1747gat,II4055);
not NOT_1444(II4067,n1675gat);
not NOT_1445(n1674gat,II4067);
not NOT_1446(n1403gat,n1402gat);
not NOT_1447(II4081,n1807gat);
not NOT_1448(n1806gat,II4081);
not NOT_1449(n1634gat,n1712gat);
not NOT_1450(n1338gat,n1340gat);
not NOT_1451(II4105,n1456gat);
not NOT_1452(n1455gat,II4105);
not NOT_1453(II4108,n1340gat);
not NOT_1454(n1339gat,II4108);
not NOT_1455(n1505gat,n2980gat);
not NOT_1456(II4117,n1505gat);
not NOT_1457(n2758gat,II4117);
not NOT_1458(n2755gat,n2758gat);
not NOT_1459(n1546gat,n2980gat);
not NOT_1460(II4122,n1546gat);
not NOT_1461(n2752gat,II4122);
not NOT_1462(n2748gat,n2752gat);
not NOT_1463(n2012gat,n2016gat);
not NOT_1464(n2002gat,n2008gat);
not NOT_1465(II4129,n3097gat);
not NOT_1466(n2858gat,II4129);
not NOT_1467(n2857gat,n2858gat);
not NOT_1468(II4135,n3098gat);
not NOT_1469(n2766gat,II4135);
not NOT_1470(II4138,n2766gat);
not NOT_1471(n2765gat,II4138);
not NOT_1472(n1684gat,n1759gat);
not NOT_1473(n1632gat,II4145);
not NOT_1474(II4157,n1525gat);
not NOT_1475(n1524gat,II4157);
not NOT_1476(n1862gat,n1863gat);
not NOT_1477(n1919gat,n1860gat);
not NOT_1478(n1460gat,n1462gat);
not NOT_1479(II4185,n1596gat);
not NOT_1480(n1595gat,II4185);
not NOT_1481(n1454gat,n1469gat);
not NOT_1482(n1468gat,n1519gat);
not NOT_1483(II4194,n1462gat);
not NOT_1484(n1461gat,II4194);
not NOT_1485(n1477gat,n2984gat);
not NOT_1486(n1594gat,n1596gat);
not NOT_1487(II4212,n1588gat);
not NOT_1488(n1587gat,II4212);
not NOT_1489(n1681gat,II4217);
not NOT_1490(II4222,n1761gat);
not NOT_1491(n2751gat,II4222);
not NOT_1492(n2747gat,n2751gat);
not NOT_1493(II4227,n1760gat);
not NOT_1494(n2743gat,II4227);
not NOT_1495(n2739gat,n2743gat);
not NOT_1496(n1978gat,n2286gat);
not NOT_1497(II4233,n1721gat);
not NOT_1498(n2808gat,II4233);
not NOT_1499(II4236,n2808gat);
not NOT_1500(n2804gat,II4236);
not NOT_1501(n517gat,n518gat);
not NOT_1502(n417gat,n418gat);
not NOT_1503(n413gat,n411gat);
not NOT_1504(n412gat,n522gat);
not NOT_1505(n406gat,n516gat);
not NOT_1506(n407gat,n355gat);
not NOT_1507(n290gat,n525gat);
not NOT_1508(n527gat,n356gat);
not NOT_1509(n416gat,n415gat);
not NOT_1510(n528gat,n521gat);
not NOT_1511(n358gat,n532gat);
not NOT_1512(n639gat,n523gat);
not NOT_1513(n1111gat,n635gat);
not NOT_1514(n524gat,n414gat);
not NOT_1515(n1112gat,n630gat);
not NOT_1516(n741gat,n629gat);
not NOT_1517(n633gat,n634gat);
not NOT_1518(n926gat,n632gat);
not NOT_1519(n670gat,n636gat);
not NOT_1520(n1123gat,n632gat);
not NOT_1521(n1007gat,n635gat);
not NOT_1522(n1006gat,n630gat);
not NOT_1523(II4309,n2941gat);
not NOT_1524(n2814gat,II4309);
not NOT_1525(II4312,n2814gat);
not NOT_1526(n2811gat,II4312);
not NOT_1527(n1002gat,n2946gat);
not NOT_1528(II4329,n2950gat);
not NOT_1529(n2813gat,II4329);
not NOT_1530(II4332,n2813gat);
not NOT_1531(n2810gat,II4332);
not NOT_1532(n888gat,n2933gat);
not NOT_1533(II4349,n2935gat);
not NOT_1534(n2818gat,II4349);
not NOT_1535(II4352,n2818gat);
not NOT_1536(n2816gat,II4352);
not NOT_1537(n898gat,n2940gat);
not NOT_1538(II4369,n2937gat);
not NOT_1539(n2817gat,II4369);
not NOT_1540(II4372,n2817gat);
not NOT_1541(n2815gat,II4372);
not NOT_1542(n1179gat,n2947gat);
not NOT_1543(II4389,n2956gat);
not NOT_1544(n2824gat,II4389);
not NOT_1545(II4392,n2824gat);
not NOT_1546(n2821gat,II4392);
not NOT_1547(n897gat,n2939gat);
not NOT_1548(II4409,n2938gat);
not NOT_1549(n2823gat,II4409);
not NOT_1550(II4412,n2823gat);
not NOT_1551(n2820gat,II4412);
not NOT_1552(n894gat,n2932gat);
not NOT_1553(II4429,n2936gat);
not NOT_1554(n2829gat,II4429);
not NOT_1555(II4432,n2829gat);
not NOT_1556(n2826gat,II4432);
not NOT_1557(n1180gat,n2948gat);
not NOT_1558(II4449,n2955gat);
not NOT_1559(n2828gat,II4449);
not NOT_1560(II4452,n2828gat);
not NOT_1561(n2825gat,II4452);
not NOT_1562(n671gat,n673gat);
not NOT_1563(n628gat,n631gat);
not NOT_1564(n976gat,n628gat);
not NOT_1565(II4475,n2951gat);
not NOT_1566(n2807gat,II4475);
not NOT_1567(II4478,n2807gat);
not NOT_1568(n2803gat,II4478);
not NOT_1569(n2127gat,n2389gat);
not NOT_1570(II4482,n2127gat);
not NOT_1571(n2682gat,II4482);
not NOT_1572(II4485,n2682gat);
not NOT_1573(n2678gat,II4485);
not NOT_1574(n2046gat,n2269gat);
not NOT_1575(II4489,n2046gat);
not NOT_1576(n2681gat,II4489);
not NOT_1577(II4492,n2681gat);
not NOT_1578(n2677gat,II4492);
not NOT_1579(n1708gat,n2338gat);
not NOT_1580(II4496,n1708gat);
not NOT_1581(n2688gat,II4496);
not NOT_1582(II4499,n2688gat);
not NOT_1583(n2686gat,II4499);
not NOT_1584(n455gat,n291gat);
not NOT_1585(n2237gat,n2646gat);
not NOT_1586(II4506,n2764gat);
not NOT_1587(n2763gat,II4506);
not NOT_1588(n1782gat,n2971gat);
not NOT_1589(II4512,n2762gat);
not NOT_1590(n2760gat,II4512);
not NOT_1591(n2325gat,n3010gat);
not NOT_1592(II4518,n2761gat);
not NOT_1593(n2759gat,II4518);
not NOT_1594(n2245gat,n504gat);
not NOT_1595(II4524,n2757gat);
not NOT_1596(n2754gat,II4524);
not NOT_1597(n2244gat,n567gat);
not NOT_1598(II4530,n2756gat);
not NOT_1599(n2753gat,II4530);
not NOT_1600(n2243gat,n55gat);
not NOT_1601(II4536,n2750gat);
not NOT_1602(n2746gat,II4536);
not NOT_1603(n2246gat,n933gat);
not NOT_1604(II4542,n2749gat);
not NOT_1605(n2745gat,II4542);
not NOT_1606(n2384gat,n43gat);
not NOT_1607(II4548,n2742gat);
not NOT_1608(n2738gat,II4548);
not NOT_1609(n2385gat,n748gat);
not NOT_1610(II4554,n2741gat);
not NOT_1611(n2737gat,II4554);
not NOT_1612(n1286gat,n1269gat);
not NOT_1613(II4558,n1286gat);
not NOT_1614(n2687gat,II4558);
not NOT_1615(n2685gat,n2687gat);
not NOT_1616(n1328gat,n1224gat);
not NOT_1617(n1381gat,n1328gat);
not NOT_1618(n1384gat,n2184gat);
not NOT_1619(II4566,n2694gat);
not NOT_1620(n2690gat,II4566);
not NOT_1621(n1382gat,n1280gat);
not NOT_1622(n1451gat,n1382gat);
not NOT_1623(n1453gat,n2187gat);
not NOT_1624(II4573,n2693gat);
not NOT_1625(n2689gat,II4573);
not NOT_1626(n927gat,n1133gat);
not NOT_1627(n925gat,n927gat);
not NOT_1628(n1452gat,n2049gat);
not NOT_1629(II4580,n2702gat);
not NOT_1630(n2698gat,II4580);
not NOT_1631(n923gat,n1043gat);
not NOT_1632(n921gat,n923gat);
not NOT_1633(n1890gat,n2328gat);
not NOT_1634(II4587,n2701gat);
not NOT_1635(n2697gat,II4587);
not NOT_1636(n850gat,n929gat);
not NOT_1637(n739gat,n850gat);
not NOT_1638(n1841gat,n2058gat);
not NOT_1639(II4594,n2709gat);
not NOT_1640(n2706gat,II4594);
not NOT_1641(n922gat,n1119gat);
not NOT_1642(n848gat,n922gat);
not NOT_1643(n2047gat,n2209gat);
not NOT_1644(II4601,n2708gat);
not NOT_1645(n2705gat,II4601);
not NOT_1646(n924gat,n1070gat);
not NOT_1647(n849gat,n924gat);
not NOT_1648(n2050gat,n2146gat);
not NOT_1649(II4608,n2799gat);
not NOT_1650(n2796gat,II4608);
not NOT_1651(n1118gat,n1033gat);
not NOT_1652(n1032gat,n1118gat);
not NOT_1653(n2054gat,n2281gat);
not NOT_1654(II4615,n2798gat);
not NOT_1655(n2795gat,II4615);
not NOT_1656(II4620,n1745gat);
not NOT_1657(n2806gat,II4620);
not NOT_1658(II4623,n2806gat);
not NOT_1659(n2802gat,II4623);
not NOT_1660(II4626,n1871gat);
not NOT_1661(n1870gat,II4626);
not NOT_1662(n1086gat,n1870gat);
not NOT_1663(II4630,n1086gat);
not NOT_1664(n2805gat,II4630);
not NOT_1665(II4633,n2805gat);
not NOT_1666(n2801gat,II4633);
not NOT_1667(n67gat,n85gat);
not NOT_1668(n71gat,n180gat);
not NOT_1669(n1840gat,n1892gat);
not NOT_1670(II4642,n2812gat);
not NOT_1671(n2809gat,II4642);
not NOT_1672(n76gat,n82gat);
not NOT_1673(n14gat,n186gat);
not NOT_1674(n1842gat,n1711gat);
not NOT_1675(II4651,n2822gat);
not NOT_1676(n2819gat,II4651);
not NOT_1677(II4654,n2819gat);
not NOT_1678(n3104gat,II4654);
not NOT_1679(II4657,n2809gat);
not NOT_1680(n3105gat,II4657);
not NOT_1681(II4660,n2801gat);
not NOT_1682(n3106gat,II4660);
not NOT_1683(II4663,n2802gat);
not NOT_1684(n3107gat,II4663);
not NOT_1685(II4666,n2795gat);
not NOT_1686(n3108gat,II4666);
not NOT_1687(II4669,n2796gat);
not NOT_1688(n3109gat,II4669);
not NOT_1689(II4672,n2705gat);
not NOT_1690(n3110gat,II4672);
not NOT_1691(II4675,n2706gat);
not NOT_1692(n3111gat,II4675);
not NOT_1693(II4678,n2697gat);
not NOT_1694(n3112gat,II4678);
not NOT_1695(II4681,n2698gat);
not NOT_1696(n3113gat,II4681);
not NOT_1697(II4684,n2689gat);
not NOT_1698(n3114gat,II4684);
not NOT_1699(II4687,n2690gat);
not NOT_1700(n3115gat,II4687);
not NOT_1701(II4690,n2685gat);
not NOT_1702(n3116gat,II4690);
not NOT_1703(II4693,n2737gat);
not NOT_1704(n3117gat,II4693);
not NOT_1705(II4696,n2738gat);
not NOT_1706(n3118gat,II4696);
not NOT_1707(II4699,n2745gat);
not NOT_1708(n3119gat,II4699);
not NOT_1709(II4702,n2746gat);
not NOT_1710(n3120gat,II4702);
not NOT_1711(II4705,n2753gat);
not NOT_1712(n3121gat,II4705);
not NOT_1713(II4708,n2754gat);
not NOT_1714(n3122gat,II4708);
not NOT_1715(II4711,n2759gat);
not NOT_1716(n3123gat,II4711);
not NOT_1717(II4714,n2760gat);
not NOT_1718(n3124gat,II4714);
not NOT_1719(II4717,n2763gat);
not NOT_1720(n3125gat,II4717);
not NOT_1721(II4720,n2686gat);
not NOT_1722(n3126gat,II4720);
not NOT_1723(II4723,n2677gat);
not NOT_1724(n3127gat,II4723);
not NOT_1725(II4726,n2678gat);
not NOT_1726(n3128gat,II4726);
not NOT_1727(II4729,n2803gat);
not NOT_1728(n3129gat,II4729);
not NOT_1729(II4732,n2825gat);
not NOT_1730(n3130gat,II4732);
not NOT_1731(II4735,n2826gat);
not NOT_1732(n3131gat,II4735);
not NOT_1733(II4738,n2820gat);
not NOT_1734(n3132gat,II4738);
not NOT_1735(II4741,n2821gat);
not NOT_1736(n3133gat,II4741);
not NOT_1737(II4744,n2815gat);
not NOT_1738(n3134gat,II4744);
not NOT_1739(II4747,n2816gat);
not NOT_1740(n3135gat,II4747);
not NOT_1741(II4750,n2810gat);
not NOT_1742(n3136gat,II4750);
not NOT_1743(II4753,n2811gat);
not NOT_1744(n3137gat,II4753);
not NOT_1745(II4756,n2804gat);
not NOT_1746(n3138gat,II4756);
not NOT_1747(II4759,n2739gat);
not NOT_1748(n3139gat,II4759);
not NOT_1749(II4762,n2747gat);
not NOT_1750(n3140gat,II4762);
not NOT_1751(II4765,n2748gat);
not NOT_1752(n3141gat,II4765);
not NOT_1753(II4768,n2755gat);
not NOT_1754(n3142gat,II4768);
not NOT_1755(II4771,n2797gat);
not NOT_1756(n3143gat,II4771);
not NOT_1757(II4774,n2740gat);
not NOT_1758(n3144gat,II4774);
not NOT_1759(II4777,n2699gat);
not NOT_1760(n3145gat,II4777);
not NOT_1761(II4780,n2691gat);
not NOT_1762(n3146gat,II4780);
not NOT_1763(II4783,n2827gat);
not NOT_1764(n3147gat,II4783);
not NOT_1765(II4786,n2679gat);
not NOT_1766(n3148gat,II4786);
not NOT_1767(II4789,n2692gat);
not NOT_1768(n3149gat,II4789);
not NOT_1769(II4792,n2680gat);
not NOT_1770(n3150gat,II4792);
not NOT_1771(II4795,n2700gat);
not NOT_1772(n3151gat,II4795);
not NOT_1773(II4798,n2707gat);
not NOT_1774(n3152gat,II4798);
or OR2_0(n2897gat,n648gat,n442gat);
or OR4_0(n1213gat,n1214gat,n1215gat,n1216gat,n1217gat);
or OR2_1(n2906gat,n745gat,n638gat);
or OR2_2(n2889gat,n423gat,n362gat);
or OR4_1(n748gat,n749gat,n750gat,n751gat,n752gat);
or OR4_2(n258gat,n259gat,n260gat,n261gat,n262gat);
or OR4_3(n1013gat,n1014gat,n1015gat,n1016gat,n1017gat);
or OR4_4(n475gat,n476gat,n477gat,n478gat,n479gat);
or OR4_5(n43gat,n44gat,n45gat,n46gat,n47gat);
or OR2_3(n2786gat,n3091gat,n3092gat);
or OR4_6(n167gat,n168gat,n169gat,n170gat,n171gat);
or OR4_7(n906gat,n907gat,n908gat,n909gat,n910gat);
or OR4_8(n343gat,n344gat,n345gat,n346gat,n347gat);
or OR4_9(n55gat,n56gat,n57gat,n58gat,n59gat);
or OR2_4(n2914gat,n768gat,n655gat);
or OR2_5(n2928gat,n963gat,n868gat);
or OR2_6(n2927gat,n962gat,n959gat);
or OR4_10(n944gat,n945gat,n946gat,n947gat,n948gat);
or OR2_7(n2896gat,n647gat,n441gat);
or OR2_8(n2922gat,n967gat,n792gat);
or OR4_11(n1228gat,n1229gat,n1230gat,n1231gat,n1232gat);
or OR2_9(n2894gat,n443gat,n439gat);
or OR2_10(n2921gat,n966gat,n790gat);
or OR2_11(n2895gat,n444gat,n440gat);
or OR4_12(n1050gat,n1051gat,n1052gat,n1053gat,n1054gat);
or OR4_13(n933gat,n934gat,n935gat,n936gat,n937gat);
or OR4_14(n709gat,n710gat,n711gat,n712gat,n713gat);
or OR4_15(n728gat,n729gat,n730gat,n731gat,n732gat);
or OR4_16(n493gat,n494gat,n495gat,n496gat,n497gat);
or OR4_17(n504gat,n505gat,n506gat,n507gat,n508gat);
or OR3_0(II1277,n2860gat,n2855gat,n2863gat);
or OR3_1(II1278,n740gat,n3030gat,II1277);
or OR2_12(n2913gat,n767gat,n653gat);
or OR2_13(n2920gat,n867gat,n771gat);
or OR2_14(n2905gat,n964gat,n961gat);
or OR4_18(n803gat,n804gat,n805gat,n806gat,n807gat);
or OR4_19(n586gat,n587gat,n588gat,n589gat,n590gat);
or OR2_15(n2898gat,n447gat,n445gat);
or OR4_20(n686gat,n687gat,n688gat,n689gat,n690gat);
or OR4_21(n567gat,n568gat,n569gat,n570gat,n571gat);
or OR3_2(II1515,n2474gat,n2524gat,n2831gat);
or OR3_3(II1516,n2466gat,n2462gat,II1515);
or OR3_4(II1584,n2353gat,n2284gat,n2354gat);
or OR3_5(II1585,n2356gat,n2214gat,II1584);
or OR2_16(n2989gat,n1693gat,n1692gat);
or OR3_6(II1723,n2354gat,n2353gat,n2214gat);
or OR3_7(II1724,n2355gat,n2443gat,II1723);
or OR3_8(II1733,n2286gat,n2428gat,n2289gat);
or OR3_9(II1734,n1604gat,n2214gat,II1733);
or OR2_17(n2918gat,n769gat,n759gat);
or OR2_18(n2952gat,n1076gat,n1075gat);
or OR2_19(n2919gat,n766gat,n760gat);
or OR4_22(n1184gat,n1185gat,n1186gat,n1187gat,n1188gat);
or OR2_20(n2910gat,n645gat,n644gat);
or OR2_21(n2907gat,n646gat,n641gat);
or OR2_22(n2970gat,n1383gat,n1327gat);
or OR2_23(n2911gat,n761gat,n651gat);
or OR2_24(n2912gat,n762gat,n652gat);
or OR2_25(n2909gat,n765gat,n643gat);
or OR4_23(n1201gat,n1202gat,n1203gat,n1204gat,n1205gat);
or OR4_24(n1269gat,n1270gat,n1271gat,n1272gat,n1273gat);
or OR2_26(n2908gat,n763gat,n642gat);
or OR2_27(n2971gat,n1287gat,n1285gat);
or OR3_10(n2904gat,n793gat,n664gat,n556gat);
or OR3_11(n2891gat,n795gat,n656gat,n368gat);
or OR3_12(n2903gat,n794gat,n773gat,n662gat);
or OR3_13(n2915gat,n965gat,n960gat,n661gat);
or OR4_25(n779gat,n780gat,n781gat,n782gat,n783gat);
or OR3_14(n2901gat,n558gat,n555gat,n450gat);
or OR3_15(n2890gat,n654gat,n557gat,n371gat);
or OR2_28(n2876gat,n874gat,n132gat);
or OR3_16(n2888gat,n663gat,n649gat,n449gat);
or OR3_17(n2887gat,n791gat,n650gat,n370gat);
or OR3_18(n2886gat,n774gat,n764gat,n369gat);
or OR4_26(n221gat,n222gat,n223gat,n224gat,n225gat);
or OR4_27(n120gat,n121gat,n122gat,n123gat,n124gat);
or OR2_29(n3010gat,n2460gat,n2423gat);
or OR2_30(n3016gat,n2596gat,n2595gat);
or OR4_28(n2568gat,n2569gat,n2570gat,n2571gat,n2572gat);
or OR4_29(n2409gat,n2410gat,n2411gat,n2412gat,n2413gat);
or OR2_31(n2579gat,n2580gat,n2581gat);
or OR2_32(n3014gat,n2567gat,n2499gat);
or OR2_33(n2880gat,n299gat,n207gat);
or OR2_34(n2646gat,n2647gat,n2648gat);
or OR4_30(n2601gat,n2602gat,n2603gat,n2604gat,n2605gat);
or OR4_31(n2545gat,n2546gat,n2547gat,n2548gat,n2549gat);
or OR2_35(n2613gat,n2614gat,n2615gat);
or OR2_36(n3013gat,n2461gat,n2421gat);
or OR4_32(n2930gat,n1153gat,n1151gat,n982gat,n877gat);
or OR4_33(n2957gat,n1159gat,n1158gat,n1156gat,n1155gat);
or OR2_37(n2975gat,n1443gat,n1325gat);
or OR2_38(n2974gat,n1321gat,n1320gat);
or OR2_39(n2966gat,n1368gat,n1258gat);
or OR2_40(n2979gat,n1373gat,n1372gat);
or OR4_34(n2978gat,n1441gat,n1440gat,n1371gat,n1367gat);
or OR2_41(n2982gat,n1504gat,n1502gat);
or OR2_42(n2954gat,n1250gat,n1103gat);
or OR2_43(n2964gat,n1304gat,n1249gat);
or OR2_44(n2958gat,n1246gat,n1161gat);
or OR2_45(n2963gat,n1291gat,n1245gat);
or OR4_35(n2973gat,n1352gat,n1351gat,n1303gat,n1302gat);
or OR2_46(n2953gat,n1163gat,n1102gat);
or OR2_47(n2949gat,n1101gat,n996gat);
or OR2_48(n2934gat,n1104gat,n887gat);
or OR2_49(n2959gat,n1305gat,n1162gat);
or OR4_36(n2977gat,n1360gat,n1359gat,n1358gat,n1357gat);
or OR3_19(II2720,n1788gat,n1786gat,n1839gat);
or OR3_20(II2721,n1884gat,n1783gat,II2720);
or OR3_21(II2735,n1788gat,n1884gat,n1633gat);
or OR3_22(II2736,n1785gat,n1784gat,II2735);
or OR3_23(II2812,n1703gat,n1704gat,n1778gat);
or OR4_37(II2813,n1609gat,n1702gat,n1700gat,II2812);
or OR3_24(II2831,n1839gat,n1786gat,n1788gat);
or OR3_25(II2832,n1884gat,n1784gat,II2831);
or OR3_26(II2889,n1784gat,n1633gat,n1884gat);
or OR3_27(II2890,n1788gat,n1786gat,II2889);
or OR3_28(II2925,n1784gat,n1785gat,n1633gat);
or OR3_29(II2926,n1884gat,n1787gat,II2925);
or OR3_30(II2934,n1784gat,n1839gat,n1788gat);
or OR3_31(II2935,n1785gat,n1884gat,II2934);
or OR2_50(n2988gat,n1733gat,n1581gat);
or OR2_51(n2983gat,n2079gat,n2073gat);
or OR2_52(n2987gat,n1574gat,n1573gat);
or OR3_32(n2992gat,n1723gat,n1647gat,n1646gat);
or OR3_33(n2986gat,n1650gat,n1649gat,n1563gat);
or OR3_34(n2991gat,n1654gat,n1653gat,n1644gat);
or OR3_35(II3148,n1839gat,n1884gat,n1784gat);
or OR3_36(II3149,n1786gat,n1787gat,II3148);
or OR3_37(II3178,n1838gat,n1785gat,n1788gat);
or OR3_38(II3179,n1839gat,n1784gat,II3178);
or OR3_39(n2981gat,n1413gat,n1408gat,n1407gat);
or OR2_53(n3000gat,n2000gat,n1999gat);
or OR3_40(n3004gat,n2258gat,n2257gat,n2255gat);
or OR2_54(n3003gat,n2256gat,n2251gat);
or OR2_55(n3001gat,n2132gat,n2130gat);
or OR2_56(n3006gat,n2253gat,n2252gat);
or OR2_57(n3007gat,n2250gat,n2249gat);
or OR2_58(n2990gat,n1710gat,n1630gat);
or OR2_59(n2994gat,n1954gat,n1888gat);
or OR3_41(n2993gat,n1894gat,n1847gat,n1846gat);
or OR2_60(n2998gat,n2055gat,n1967gat);
or OR3_42(n2996gat,n1960gat,n1959gat,n1957gat);
or OR2_61(n3008gat,n2332gat,n2259gat);
or OR2_62(n3005gat,n2211gat,n2210gat);
or OR3_43(n2997gat,n2053gat,n2052gat,n1964gat);
or OR2_63(n3009gat,n2350gat,n2282gat);
or OR3_44(n3002gat,n2213gat,n2150gat,n2149gat);
or OR2_64(n2995gat,n1962gat,n1955gat);
or OR2_65(n2999gat,n1972gat,n1971gat);
or OR2_66(n3011gat,n2333gat,n2331gat);
or OR2_67(n3015gat,n2566gat,n2565gat);
or OR3_45(n2874gat,n141gat,n38gat,n37gat);
or OR2_68(n2917gat,n1074gat,n872gat);
or OR2_69(n2878gat,n234gat,n137gat);
or OR2_70(n2892gat,n378gat,n377gat);
or OR3_46(n2885gat,n250gat,n249gat,n248gat);
or OR3_47(n2900gat,n869gat,n453gat,n448gat);
or OR2_71(n2883gat,n251gat,n244gat);
or OR3_48(n2929gat,n974gat,n973gat,n870gat);
or OR2_72(n2884gat,n246gat,n245gat);
or OR2_73(n2902gat,n460gat,n459gat);
or OR3_49(n2925gat,n975gat,n972gat,n969gat);
or OR2_74(n2879gat,n145gat,n143gat);
or OR3_50(n2916gat,n971gat,n970gat,n968gat);
or OR3_51(n2875gat,n142gat,n40gat,n39gat);
or OR3_52(n2899gat,n772gat,n451gat,n446gat);
or OR2_75(n2877gat,n139gat,n136gat);
or OR2_76(n2893gat,n391gat,n390gat);
or OR2_77(n2926gat,n1083gat,n1077gat);
or OR2_78(n2882gat,n242gat,n240gat);
or OR2_79(n2924gat,n871gat,n797gat);
or OR3_53(n2881gat,n324gat,n238gat,n237gat);
or OR2_80(n2923gat,n1082gat,n796gat);
or OR2_81(n2710gat,n69gat,n1885gat);
or OR2_82(n2704gat,n11gat,n1889gat);
or OR2_83(n2684gat,n1599gat,n2051gat);
or OR2_84(n2830gat,n2444gat,n1754gat);
or OR3_54(II3999,n2167gat,n2031gat,n2174gat);
or OR4_38(II4000,n2108gat,n2093gat,n2035gat,II3999);
or OR2_85(n2695gat,n1586gat,n1791gat);
or OR2_86(n2703gat,n1755gat,n1518gat);
or OR2_87(n2744gat,n2159gat,n2478gat);
or OR2_88(n2800gat,n2158gat,n2186gat);
or OR3_55(II4023,n2443gat,n2290gat,n2214gat);
or OR3_56(II4024,n2353gat,n2284gat,II4023);
or OR4_39(n2980gat,n1470gat,n1400gat,n1399gat,n1398gat);
or OR3_57(II4144,n1633gat,n1838gat,n1786gat);
or OR3_58(II4145,n1788gat,n1784gat,II4144);
or OR2_89(n2984gat,n1467gat,n1466gat);
or OR4_40(n2985gat,n1686gat,n1533gat,n1532gat,n1531gat);
or OR3_59(II4216,n1427gat,n1595gat,n1677gat);
or OR3_60(II4217,n1392gat,n2989gat,II4216);
or OR4_41(n2931gat,n1100gat,n994gat,n989gat,n880gat);
or OR2_90(n2943gat,n1012gat,n905gat);
or OR2_91(n2941gat,n1003gat,n902gat);
or OR4_42(n2946gat,n1099gat,n998gat,n995gat,n980gat);
or OR2_92(n2960gat,n1175gat,n1174gat);
or OR2_93(n2950gat,n1001gat,n999gat);
or OR2_94(n2969gat,n1323gat,n1264gat);
or OR4_43(n2933gat,n981gat,n890gat,n889gat,n886gat);
or OR2_95(n2935gat,n892gat,n891gat);
or OR2_96(n2942gat,n904gat,n903gat);
or OR4_44(n2940gat,n1152gat,n1092gat,n997gat,n993gat);
or OR2_97(n2937gat,n900gat,n895gat);
or OR4_45(n2947gat,n1094gat,n1093gat,n988gat,n984gat);
or OR2_98(n2965gat,n1267gat,n1257gat);
or OR2_99(n2956gat,n1178gat,n1116gat);
or OR2_100(n2961gat,n1375gat,n1324gat);
or OR4_46(n2939gat,n1091gat,n1088gat,n992gat,n987gat);
or OR2_101(n2938gat,n899gat,n896gat);
or OR2_102(n2967gat,n1262gat,n1260gat);
or OR4_47(n2932gat,n1098gat,n1090gat,n986gat,n885gat);
or OR2_103(n2936gat,n901gat,n893gat);
or OR4_48(n2948gat,n1097gat,n1089gat,n1087gat,n991gat);
or OR2_104(n2968gat,n1326gat,n1261gat);
or OR2_105(n2955gat,n1177gat,n1115gat);
or OR2_106(n2944gat,n977gat,n976gat);
or OR4_49(n2945gat,n1096gat,n1095gat,n990gat,n979gat);
or OR2_107(n2962gat,n1176gat,n1173gat);
or OR2_108(n2951gat,n1004gat,n1000gat);
or OR2_109(n2764gat,n1029gat,n2237gat);
or OR2_110(n2762gat,n1028gat,n1782gat);
or OR2_111(n2761gat,n1031gat,n2325gat);
or OR2_112(n2757gat,n1030gat,n2245gat);
or OR2_113(n2756gat,n1011gat,n2244gat);
or OR2_114(n2750gat,n1181gat,n2243gat);
or OR2_115(n2749gat,n1010gat,n2246gat);
or OR2_116(n2742gat,n1005gat,n2384gat);
or OR2_117(n2741gat,n1182gat,n2385gat);
or OR2_118(n2694gat,n1381gat,n1384gat);
or OR2_119(n2693gat,n1451gat,n1453gat);
or OR2_120(n2702gat,n925gat,n1452gat);
or OR2_121(n2701gat,n921gat,n1890gat);
or OR2_122(n2709gat,n739gat,n1841gat);
or OR2_123(n2708gat,n848gat,n2047gat);
or OR2_124(n2799gat,n849gat,n2050gat);
or OR2_125(n2798gat,n1032gat,n2054gat);
or OR3_61(n2812gat,n73gat,n70gat,n1840gat);
or OR3_62(n2822gat,n77gat,n13gat,n1842gat);
nor NOR2_0(n421gat,n2715gat,n2723gat);
nor NOR2_1(n648gat,n373gat,n2669gat);
nor NOR2_2(n442gat,n2844gat,n856gat);
nor NOR2_3(n1499gat,n396gat,n401gat);
nor NOR2_4(n1616gat,n918gat,n396gat);
nor NOR2_5(n1614gat,n396gat,n845gat);
nor NOR3_0(n1641gat,n1645gat,n1553gat,n1559gat);
nor NOR3_1(n1642gat,n1559gat,n1616gat,n1645gat);
nor NOR3_2(n1556gat,n1614gat,n1645gat,n1616gat);
nor NOR3_3(n1557gat,n1553gat,n1645gat,n1614gat);
nor NOR3_4(n1639gat,n1499gat,n1559gat,n1553gat);
nor NOR4_0(n1605gat,n1614gat,n1616gat,n1499gat,n396gat);
nor NOR3_5(n1555gat,n1616gat,n1559gat,n1499gat);
nor NOR3_6(n1558gat,n1614gat,n1553gat,n1499gat);
nor NOR2_6(n1256gat,n392gat,n702gat);
nor NOR2_7(n1117gat,n720gat,n725gat);
nor NOR2_8(n1618gat,n1319gat,n1447gat);
nor NOR2_9(n1114gat,n725gat,n721gat);
nor NOR2_10(n1621gat,n1319gat,n1380gat);
nor NOR2_11(n1318gat,n392gat,n701gat);
nor NOR2_12(n1619gat,n1447gat,n1446gat);
nor NOR2_13(n1622gat,n1380gat,n1446gat);
nor NOR3_7(n1214gat,n1218gat,n1219gat,n1220gat);
nor NOR3_8(n1215gat,n1218gat,n1221gat,n1222gat);
nor NOR3_9(n1216gat,n1223gat,n1219gat,n1222gat);
nor NOR3_10(n1217gat,n1223gat,n1221gat,n1220gat);
nor NOR2_14(n745gat,n2716gat,n2867gat);
nor NOR2_15(n638gat,n2715gat,n2868gat);
nor NOR2_16(n423gat,n2724gat,n2726gat);
nor NOR2_17(n362gat,n2723gat,n2727gat);
nor NOR3_11(n749gat,n753gat,n754gat,n755gat);
nor NOR3_12(n750gat,n753gat,n756gat,n757gat);
nor NOR3_13(n751gat,n758gat,n754gat,n757gat);
nor NOR3_14(n752gat,n758gat,n756gat,n755gat);
nor NOR3_15(n259gat,n263gat,n264gat,n265gat);
nor NOR3_16(n260gat,n263gat,n266gat,n267gat);
nor NOR3_17(n261gat,n268gat,n264gat,n267gat);
nor NOR3_18(n262gat,n268gat,n266gat,n265gat);
nor NOR3_19(n1014gat,n1018gat,n1019gat,n1020gat);
nor NOR3_20(n1015gat,n1018gat,n1021gat,n1022gat);
nor NOR3_21(n1016gat,n1023gat,n1019gat,n1022gat);
nor NOR3_22(n1017gat,n1023gat,n1021gat,n1020gat);
nor NOR3_23(n476gat,n480gat,n481gat,n482gat);
nor NOR3_24(n477gat,n480gat,n483gat,n484gat);
nor NOR3_25(n478gat,n485gat,n481gat,n484gat);
nor NOR3_26(n479gat,n485gat,n483gat,n482gat);
nor NOR3_27(n44gat,n48gat,n49gat,n50gat);
nor NOR3_28(n45gat,n48gat,n51gat,n52gat);
nor NOR3_29(n46gat,n53gat,n49gat,n52gat);
nor NOR3_30(n47gat,n53gat,n51gat,n50gat);
nor NOR2_18(n1376gat,n724gat,n720gat);
nor NOR2_19(n1617gat,n1319gat,n1448gat);
nor NOR2_20(n1377gat,n724gat,n721gat);
nor NOR2_21(n1624gat,n1319gat,n1379gat);
nor NOR2_22(n1113gat,n393gat,n701gat);
nor NOR2_23(n1501gat,n1448gat,n1500gat);
nor NOR2_24(n1623gat,n1379gat,n1446gat);
nor NOR2_25(n1620gat,n1448gat,n1446gat);
nor NOR2_26(n1827gat,n2729gat,n2317gat);
nor NOR2_27(n1817gat,n1819gat,n1823gat);
nor NOR2_28(n1935gat,n1816gat,n1828gat);
nor NOR2_29(n529gat,n2724gat,n2715gat);
nor NOR2_30(n361gat,n2859gat,n2726gat);
nor NOR3_31(n168gat,n172gat,n173gat,n174gat);
nor NOR3_32(n169gat,n172gat,n175gat,n176gat);
nor NOR3_33(n170gat,n177gat,n173gat,n176gat);
nor NOR3_34(n171gat,n177gat,n175gat,n174gat);
nor NOR3_35(n907gat,n911gat,n912gat,n913gat);
nor NOR3_36(n908gat,n911gat,n914gat,n915gat);
nor NOR3_37(n909gat,n916gat,n912gat,n915gat);
nor NOR3_38(n910gat,n916gat,n914gat,n913gat);
nor NOR3_39(n344gat,n348gat,n349gat,n350gat);
nor NOR3_40(n345gat,n348gat,n351gat,n352gat);
nor NOR3_41(n346gat,n353gat,n349gat,n352gat);
nor NOR3_42(n347gat,n353gat,n351gat,n350gat);
nor NOR3_43(n56gat,n60gat,n61gat,n62gat);
nor NOR3_44(n57gat,n60gat,n63gat,n64gat);
nor NOR3_45(n58gat,n65gat,n61gat,n64gat);
nor NOR3_46(n59gat,n65gat,n63gat,n62gat);
nor NOR2_31(n768gat,n373gat,n2731gat);
nor NOR2_32(n655gat,n856gat,n2718gat);
nor NOR2_33(n963gat,n856gat,n2838gat);
nor NOR2_34(n868gat,n2775gat,n373gat);
nor NOR2_35(n962gat,n856gat,n2711gat);
nor NOR2_36(n959gat,n373gat,n2734gat);
nor NOR3_47(n945gat,n949gat,n950gat,n951gat);
nor NOR3_48(n946gat,n949gat,n952gat,n953gat);
nor NOR3_49(n947gat,n954gat,n950gat,n953gat);
nor NOR3_50(n948gat,n954gat,n952gat,n951gat);
nor NOR2_37(n647gat,n2792gat,n373gat);
nor NOR2_38(n441gat,n856gat,n2846gat);
nor NOR2_39(n967gat,n373gat,n2672gat);
nor NOR2_40(n792gat,n2852gat,n856gat);
nor NOR3_51(n1229gat,n1233gat,n1234gat,n1235gat);
nor NOR3_52(n1230gat,n1233gat,n1236gat,n1237gat);
nor NOR3_53(n1231gat,n1238gat,n1234gat,n1237gat);
nor NOR3_54(n1232gat,n1238gat,n1236gat,n1235gat);
nor NOR2_41(n443gat,n2778gat,n373gat);
nor NOR2_42(n439gat,n856gat,n2836gat);
nor NOR2_43(n966gat,n2789gat,n373gat);
nor NOR2_44(n790gat,n856gat,n2840gat);
nor NOR2_45(n444gat,n373gat,n2781gat);
nor NOR2_46(n440gat,n856gat,n2842gat);
nor NOR3_55(n1051gat,n1055gat,n1056gat,n1057gat);
nor NOR3_56(n1052gat,n1055gat,n1058gat,n1059gat);
nor NOR3_57(n1053gat,n1060gat,n1056gat,n1059gat);
nor NOR3_58(n1054gat,n1060gat,n1058gat,n1057gat);
nor NOR3_59(n934gat,n938gat,n939gat,n940gat);
nor NOR3_60(n935gat,n938gat,n941gat,n942gat);
nor NOR3_61(n936gat,n943gat,n939gat,n942gat);
nor NOR3_62(n937gat,n943gat,n941gat,n940gat);
nor NOR2_47(n746gat,n2716gat,n2723gat);
nor NOR2_48(n360gat,n2859gat,n2727gat);
nor NOR3_63(n710gat,n714gat,n715gat,n716gat);
nor NOR3_64(n711gat,n714gat,n717gat,n718gat);
nor NOR3_65(n712gat,n719gat,n715gat,n718gat);
nor NOR3_66(n713gat,n719gat,n717gat,n716gat);
nor NOR3_67(n729gat,n733gat,n734gat,n735gat);
nor NOR3_68(n730gat,n733gat,n736gat,n737gat);
nor NOR3_69(n731gat,n738gat,n734gat,n737gat);
nor NOR3_70(n732gat,n738gat,n736gat,n735gat);
nor NOR3_71(n494gat,n498gat,n499gat,n500gat);
nor NOR3_72(n495gat,n498gat,n501gat,n502gat);
nor NOR3_73(n496gat,n503gat,n499gat,n502gat);
nor NOR3_74(n497gat,n503gat,n501gat,n500gat);
nor NOR3_75(n505gat,n509gat,n510gat,n511gat);
nor NOR3_76(n506gat,n509gat,n512gat,n513gat);
nor NOR3_77(n507gat,n514gat,n510gat,n513gat);
nor NOR3_78(n508gat,n514gat,n512gat,n511gat);
nor NOR4_1(n564gat,n3029gat,n2863gat,n2855gat,n374gat);
nor NOR3_79(n86gat,n743gat,n294gat,n17gat);
nor NOR2_49(n78gat,n2784gat,n79gat);
nor NOR2_50(n767gat,n219gat,n2731gat);
nor NOR2_51(n286gat,n289gat,n2723gat);
nor NOR2_52(n287gat,n289gat,n2715gat);
nor NOR2_53(n288gat,n289gat,n2726gat);
nor NOR3_80(n181gat,n286gat,n179gat,n188gat);
nor NOR2_54(n182gat,n72gat,n2720gat);
nor NOR2_55(n653gat,n2718gat,n111gat);
nor NOR2_56(n867gat,n219gat,n2775gat);
nor NOR2_57(n771gat,n2838gat,n111gat);
nor NOR2_58(n964gat,n111gat,n2711gat);
nor NOR2_59(n961gat,n219gat,n2734gat);
nor NOR3_81(n804gat,n808gat,n809gat,n810gat);
nor NOR3_82(n805gat,n808gat,n811gat,n812gat);
nor NOR3_83(n806gat,n813gat,n809gat,n812gat);
nor NOR3_84(n807gat,n813gat,n811gat,n810gat);
nor NOR3_85(n587gat,n591gat,n592gat,n593gat);
nor NOR3_86(n588gat,n591gat,n594gat,n595gat);
nor NOR3_87(n589gat,n596gat,n592gat,n595gat);
nor NOR3_88(n590gat,n596gat,n594gat,n593gat);
nor NOR2_60(n447gat,n2836gat,n111gat);
nor NOR2_61(n445gat,n2778gat,n219gat);
nor NOR3_89(n687gat,n691gat,n692gat,n693gat);
nor NOR3_90(n688gat,n691gat,n694gat,n695gat);
nor NOR3_91(n689gat,n696gat,n692gat,n695gat);
nor NOR3_92(n690gat,n696gat,n694gat,n693gat);
nor NOR3_93(n568gat,n572gat,n573gat,n574gat);
nor NOR3_94(n569gat,n572gat,n575gat,n576gat);
nor NOR3_95(n570gat,n577gat,n573gat,n576gat);
nor NOR3_96(n571gat,n577gat,n575gat,n574gat);
nor NOR3_97(n187gat,n189gat,n287gat,n188gat);
nor NOR2_62(n197gat,n194gat,n297gat);
nor NOR3_98(n15gat,n637gat,n17gat,n293gat);
nor NOR2_63(n22gat,n92gat,n21gat);
nor NOR2_64(n93gat,n197gat,n22gat);
nor NOR2_65(n769gat,n93gat,n2731gat);
nor NOR3_99(n2534gat,n2624gat,n2489gat,n2621gat);
nor NOR3_100(n2430gat,n2533gat,n2486gat,n2429gat);
nor NOR2_66(n1606gat,n3020gat,n270gat);
nor NOR2_67(n2239gat,n2850gat,n3019gat);
nor NOR3_101(n1934gat,n2470gat,n1935gat,n2239gat);
nor NOR2_68(n1610gat,n1698gat,n1543gat);
nor NOR2_69(n1692gat,n1879gat,n1762gat);
nor NOR2_70(n2433gat,n2432gat,n2154gat);
nor NOR3_102(n2531gat,n2488gat,n2625gat,n2621gat);
nor NOR3_103(n2480gat,n2530gat,n2482gat,n2486gat);
nor NOR2_71(n2427gat,n2426gat,n2153gat);
nor NOR2_72(n2428gat,n2433gat,n2427gat);
nor NOR2_73(n1778gat,n3026gat,n1779gat);
nor NOR2_74(n1609gat,n1503gat,n3025gat);
nor NOR2_75(n1702gat,n3024gat,n1615gat);
nor NOR2_76(n1700gat,n1701gat,n3023gat);
nor NOR4_2(n1604gat,n1778gat,n1609gat,n1702gat,n1700gat);
nor NOR2_77(n1076gat,n93gat,n2775gat);
nor NOR2_78(n766gat,n93gat,n2734gat);
nor NOR3_104(n1185gat,n1189gat,n1190gat,n1191gat);
nor NOR3_105(n1186gat,n1189gat,n1192gat,n1193gat);
nor NOR3_106(n1187gat,n1194gat,n1190gat,n1193gat);
nor NOR3_107(n1188gat,n1194gat,n1192gat,n1191gat);
nor NOR2_79(n645gat,n2792gat,n93gat);
nor NOR2_80(n646gat,n93gat,n2669gat);
nor NOR2_81(n1383gat,n1280gat,n1225gat);
nor NOR2_82(n1327gat,n1281gat,n1224gat);
nor NOR2_83(n651gat,n93gat,n2778gat);
nor NOR2_84(n652gat,n2789gat,n93gat);
nor NOR2_85(n765gat,n2781gat,n93gat);
nor NOR3_108(n1202gat,n1206gat,n1207gat,n1208gat);
nor NOR3_109(n1203gat,n1206gat,n1209gat,n1210gat);
nor NOR3_110(n1204gat,n1211gat,n1207gat,n1210gat);
nor NOR3_111(n1205gat,n1211gat,n1209gat,n1208gat);
nor NOR3_112(n1270gat,n1274gat,n1275gat,n1276gat);
nor NOR3_113(n1271gat,n1274gat,n1277gat,n1278gat);
nor NOR3_114(n1272gat,n1279gat,n1275gat,n1278gat);
nor NOR3_115(n1273gat,n1279gat,n1277gat,n1276gat);
nor NOR2_86(n763gat,n2672gat,n93gat);
nor NOR2_87(n1287gat,n1284gat,n1195gat);
nor NOR2_88(n1285gat,n1196gat,n1269gat);
nor NOR2_89(n853gat,n740gat,n2148gat);
nor NOR2_90(n793gat,n2852gat,n851gat);
nor NOR2_91(n854gat,n2148gat,n374gat);
nor NOR2_92(n556gat,n2672gat,n852gat);
nor NOR2_93(n795gat,n2731gat,n852gat);
nor NOR2_94(n656gat,n851gat,n2718gat);
nor NOR2_95(n794gat,n852gat,n2775gat);
nor NOR2_96(n773gat,n851gat,n2838gat);
nor NOR2_97(n965gat,n2711gat,n851gat);
nor NOR2_98(n960gat,n2734gat,n852gat);
nor NOR3_116(n780gat,n784gat,n785gat,n786gat);
nor NOR3_117(n781gat,n784gat,n787gat,n788gat);
nor NOR3_118(n782gat,n789gat,n785gat,n788gat);
nor NOR3_119(n783gat,n789gat,n787gat,n786gat);
nor NOR2_99(n555gat,n852gat,n2792gat);
nor NOR2_100(n450gat,n851gat,n2846gat);
nor NOR2_101(n654gat,n851gat,n2844gat);
nor NOR2_102(n557gat,n2669gat,n852gat);
nor NOR2_103(n874gat,n559gat,n365gat);
nor NOR2_104(n132gat,n560gat,n364gat);
nor NOR2_105(n649gat,n2778gat,n852gat);
nor NOR2_106(n449gat,n2836gat,n851gat);
nor NOR2_107(n791gat,n851gat,n2840gat);
nor NOR2_108(n650gat,n852gat,n2789gat);
nor NOR2_109(n774gat,n2842gat,n851gat);
nor NOR2_110(n764gat,n852gat,n2781gat);
nor NOR3_120(n222gat,n226gat,n227gat,n228gat);
nor NOR3_121(n223gat,n226gat,n229gat,n230gat);
nor NOR3_122(n224gat,n231gat,n227gat,n230gat);
nor NOR3_123(n225gat,n231gat,n229gat,n228gat);
nor NOR3_124(n121gat,n125gat,n126gat,n127gat);
nor NOR3_125(n122gat,n125gat,n128gat,n129gat);
nor NOR3_126(n123gat,n130gat,n126gat,n129gat);
nor NOR3_127(n124gat,n130gat,n128gat,n127gat);
nor NOR2_111(n2460gat,n666gat,n120gat);
nor NOR2_112(n2423gat,n665gat,n1601gat);
nor NOR3_128(n2594gat,n3017gat,n2520gat,n2597gat);
nor NOR3_129(n2569gat,n2573gat,n2574gat,n2575gat);
nor NOR3_130(n2570gat,n2573gat,n2576gat,n2577gat);
nor NOR3_131(n2571gat,n2578gat,n2574gat,n2577gat);
nor NOR3_132(n2572gat,n2578gat,n2576gat,n2575gat);
nor NOR3_133(n2410gat,n2414gat,n2415gat,n2416gat);
nor NOR3_134(n2411gat,n2414gat,n2417gat,n2418gat);
nor NOR3_135(n2412gat,n2419gat,n2415gat,n2418gat);
nor NOR3_136(n2413gat,n2419gat,n2417gat,n2416gat);
nor NOR2_113(n2583gat,n2582gat,n2585gat);
nor NOR2_114(n2580gat,n2582gat,n2583gat);
nor NOR2_115(n2581gat,n2583gat,n2585gat);
nor NOR2_116(n2567gat,n2493gat,n2388gat);
nor NOR2_117(n2499gat,n2389gat,n2494gat);
nor NOR2_118(n299gat,n2268gat,n2338gat);
nor NOR2_119(n207gat,n2337gat,n2269gat);
nor NOR2_120(n2650gat,n2649gat,n2652gat);
nor NOR2_121(n2647gat,n2649gat,n2650gat);
nor NOR2_122(n2648gat,n2650gat,n2652gat);
nor NOR3_137(n2602gat,n2606gat,n2607gat,n2608gat);
nor NOR3_138(n2603gat,n2606gat,n2609gat,n2610gat);
nor NOR3_139(n2604gat,n2611gat,n2607gat,n2610gat);
nor NOR3_140(n2605gat,n2611gat,n2609gat,n2608gat);
nor NOR3_141(n2546gat,n2550gat,n2551gat,n2552gat);
nor NOR3_142(n2547gat,n2550gat,n2553gat,n2554gat);
nor NOR3_143(n2548gat,n2555gat,n2551gat,n2554gat);
nor NOR3_144(n2549gat,n2555gat,n2553gat,n2552gat);
nor NOR2_123(n2617gat,n2616gat,n2619gat);
nor NOR2_124(n2614gat,n2616gat,n2617gat);
nor NOR2_125(n2615gat,n2617gat,n2619gat);
nor NOR4_3(n2655gat,n2508gat,n2656gat,n2500gat,n2504gat);
nor NOR3_145(n2293gat,n2353gat,n2284gat,n2443gat);
nor NOR2_126(n2219gat,n2354gat,n2214gat);
nor NOR2_127(n1529gat,n1528gat,n1523gat);
nor NOR2_128(n1704gat,n3027gat,n1706gat);
nor NOR2_129(n2461gat,n120gat,n2666gat);
nor NOR2_130(n2421gat,n1601gat,n1704gat);
nor NOR2_131(n1598gat,n1592gat,n2422gat);
nor NOR2_132(n2218gat,n2214gat,n2290gat);
nor NOR3_146(n2358gat,n2285gat,n2356gat,n2355gat);
nor NOR2_133(n1415gat,n2081gat,n2359gat);
nor NOR2_134(n1153gat,n1414gat,n566gat);
nor NOR3_147(n2292gat,n2443gat,n2284gat,n2285gat);
nor NOR2_135(n1416gat,n2081gat,n1480gat);
nor NOR2_136(n1151gat,n1301gat,n1150gat);
nor NOR3_148(n2306gat,n2356gat,n2284gat,n2285gat);
nor NOR2_137(n1481gat,n2081gat,n2011gat);
nor NOR2_138(n982gat,n873gat,n1478gat);
nor NOR3_149(n2357gat,n2285gat,n2355gat,n2443gat);
nor NOR2_139(n1347gat,n2081gat,n1410gat);
nor NOR2_140(n877gat,n875gat,n876gat);
nor NOR2_141(n1484gat,n2081gat,n1528gat);
nor NOR2_142(n1159gat,n1160gat,n1084gat);
nor NOR3_150(n2363gat,n2353gat,n2356gat,n2355gat);
nor NOR2_143(n1483gat,n2081gat,n1482gat);
nor NOR2_144(n1158gat,n983gat,n1157gat);
nor NOR3_151(n2364gat,n2353gat,n2284gat,n2356gat);
nor NOR2_145(n1308gat,n2081gat,n1530gat);
nor NOR2_146(n1156gat,n985gat,n1307gat);
nor NOR3_152(n2291gat,n2353gat,n2355gat,n2443gat);
nor NOR2_147(n1349gat,n1479gat,n2081gat);
nor NOR2_148(n1155gat,n1085gat,n1348gat);
nor NOR3_153(n1154gat,n1598gat,n2930gat,n2957gat);
nor NOR2_149(n1703gat,n1705gat,n3028gat);
nor NOR2_150(n1608gat,n1704gat,n1703gat);
nor NOR2_151(n1411gat,n1154gat,n1608gat);
nor NOR2_152(n2223gat,n2354gat,n2217gat);
nor NOR2_153(n1438gat,n1591gat,n1480gat);
nor NOR2_154(n1625gat,n3021gat,n1628gat);
nor NOR2_155(n1626gat,n1627gat,n3022gat);
nor NOR3_154(n1831gat,n1832gat,n1765gat,n1878gat);
nor NOR2_156(n1443gat,n1442gat,n706gat);
nor NOR2_157(n1325gat,n1444gat,n164gat);
nor NOR2_158(n1441gat,n1437gat,n1378gat);
nor NOR2_159(n1321gat,n1442gat,n837gat);
nor NOR2_160(n1320gat,n1444gat,n278gat);
nor NOR2_161(n1486gat,n1482gat,n1591gat);
nor NOR2_162(n1440gat,n1322gat,n1439gat);
nor NOR2_163(n1426gat,n2011gat,n1591gat);
nor NOR2_164(n1368gat,n1442gat,n613gat);
nor NOR2_165(n1258gat,n274gat,n1444gat);
nor NOR2_166(n1371gat,n1370gat,n1369gat);
nor NOR2_167(n1365gat,n1479gat,n1591gat);
nor NOR2_168(n1373gat,n833gat,n1442gat);
nor NOR2_169(n1372gat,n282gat,n1444gat);
nor NOR2_170(n1367gat,n1366gat,n1374gat);
nor NOR2_171(n2220gat,n2290gat,n2217gat);
nor NOR2_172(n1423gat,n2162gat,n1530gat);
nor NOR2_173(n1498gat,n1609gat,n1427gat);
nor NOR2_174(n1504gat,n1450gat,n1498gat);
nor NOR2_175(n1607gat,n2082gat,n1609gat);
nor NOR2_176(n1494gat,n1528gat,n2162gat);
nor NOR2_177(n1502gat,n1607gat,n1449gat);
nor NOR2_178(n1250gat,n1603gat,n815gat);
nor NOR2_179(n1103gat,n956gat,n1590gat);
nor NOR2_180(n1417gat,n2162gat,n1480gat);
nor NOR2_181(n1352gat,n1248gat,n1418gat);
nor NOR2_182(n1304gat,n1590gat,n1067gat);
nor NOR2_183(n1249gat,n679gat,n1603gat);
nor NOR2_184(n1419gat,n2162gat,n1479gat);
nor NOR2_185(n1351gat,n1306gat,n1353gat);
nor NOR2_186(n1246gat,n864gat,n1590gat);
nor NOR2_187(n1161gat,n583gat,n1603gat);
nor NOR2_188(n1422gat,n2011gat,n2162gat);
nor NOR2_189(n1303gat,n1247gat,n1355gat);
nor NOR2_190(n1291gat,n1603gat,n579gat);
nor NOR2_191(n1245gat,n1590gat,n860gat);
nor NOR2_192(n1485gat,n1482gat,n2162gat);
nor NOR2_193(n1302gat,n1300gat,n1487gat);
nor NOR2_194(n1163gat,n882gat,n1603gat);
nor NOR2_195(n1102gat,n1297gat,n1590gat);
nor NOR2_196(n1354gat,n1591gat,n1530gat);
nor NOR2_197(n1360gat,n1164gat,n1356gat);
nor NOR2_198(n1435gat,n1591gat,n1528gat);
nor NOR2_199(n1101gat,n1590gat,n1293gat);
nor NOR2_200(n996gat,n1603gat,n823gat);
nor NOR2_201(n1359gat,n1436gat,n1106gat);
nor NOR2_202(n1421gat,n2162gat,n2359gat);
nor NOR2_203(n1104gat,n1079gat,n1590gat);
nor NOR2_204(n887gat,n1603gat,n683gat);
nor NOR2_205(n1358gat,n1425gat,n1105gat);
nor NOR2_206(n1420gat,n1410gat,n2162gat);
nor NOR2_207(n1305gat,n1147gat,n1590gat);
nor NOR2_208(n1162gat,n698gat,n1603gat);
nor NOR2_209(n1357gat,n1424gat,n1309gat);
nor NOR4_4(n1428gat,n2978gat,n2982gat,n2973gat,n2977gat);
nor NOR2_210(n1794gat,n1673gat,n1719gat);
nor NOR2_211(n1796gat,n1858gat,n1635gat);
nor NOR2_212(n1792gat,n1794gat,n1796gat);
nor NOR3_155(n1865gat,n1989gat,n1918gat,n1986gat);
nor NOR3_156(n1861gat,n1866gat,n2216gat,n1988gat);
nor NOR2_213(n1793gat,n1792gat,n1735gat);
nor NOR2_214(n1406gat,n1428gat,n1387gat);
nor NOR3_157(n1780gat,n1777gat,n1625gat,n1626gat);
nor NOR2_215(n2016gat,n2019gat,n1878gat);
nor NOR2_216(n2664gat,n2850gat,n3018gat);
nor NOR3_158(n1666gat,n1986gat,n2212gat,n1991gat);
nor NOR3_159(n1578gat,n2152gat,n2351gat,n1665gat);
nor NOR2_217(n1516gat,n1551gat,n1517gat);
nor NOR3_160(n1864gat,n1858gat,n1495gat,n2090gat);
nor NOR2_218(n1565gat,n1735gat,n1552gat);
nor NOR2_219(n1921gat,n1738gat,n1673gat);
nor NOR2_220(n1798gat,n1739gat,n1673gat);
nor NOR3_161(n1920gat,n1864gat,n1921gat,n1798gat);
nor NOR2_221(n1926gat,n1925gat,n1635gat);
nor NOR2_222(n1916gat,n1917gat,n1859gat);
nor NOR2_223(n1994gat,n1719gat,n1922gat);
nor NOR2_224(n1924gat,n1743gat,n1923gat);
nor NOR4_5(n2078gat,n1926gat,n1916gat,n1994gat,n1924gat);
nor NOR2_225(n1690gat,n1700gat,n1702gat);
nor NOR3_162(n1660gat,n1918gat,n1986gat,n2212gat);
nor NOR3_163(n1576gat,n2351gat,n1988gat,n1661gat);
nor NOR2_226(n1733gat,n1673gat,n1572gat);
nor NOR3_164(n1582gat,n2283gat,n1991gat,n2212gat);
nor NOR3_165(n1577gat,n1520gat,n2351gat,n1988gat);
nor NOR2_227(n1581gat,n1858gat,n1580gat);
nor NOR3_166(n2129gat,n2189gat,n2134gat,n2261gat);
nor NOR4_6(n2079gat,n2078gat,n2178gat,n1990gat,n2128gat);
nor NOR4_7(n1695gat,n1609gat,n1778gat,n1704gat,n1703gat);
nor NOR3_167(n2073gat,n2078gat,n1990gat,n2181gat);
nor NOR2_228(n1696gat,n1707gat,n1698gat);
nor NOR2_229(n1758gat,n1311gat,n1773gat);
nor NOR3_168(n1574gat,n1719gat,n1673gat,n1444gat);
nor NOR3_169(n1573gat,n1444gat,n1858gat,n1635gat);
nor NOR2_230(n1521gat,n2283gat,n1991gat);
nor NOR2_231(n1737gat,n2212gat,n2152gat);
nor NOR3_170(n1732gat,n1515gat,n1736gat,n1658gat);
nor NOR3_171(n1723gat,n1659gat,n1722gat,n1724gat);
nor NOR2_232(n1663gat,n1986gat,n1918gat);
nor NOR3_172(n1655gat,n1736gat,n1662gat,n1658gat);
nor NOR3_173(n1647gat,n1656gat,n1659gat,n1554gat);
nor NOR2_233(n1667gat,n1991gat,n1986gat);
nor NOR3_174(n1570gat,n1736gat,n1658gat,n1670gat);
nor NOR3_175(n1646gat,n1569gat,n1659gat,n1566gat);
nor NOR2_234(n1575gat,n1918gat,n2283gat);
nor NOR3_176(n1728gat,n1568gat,n1736gat,n1658gat);
nor NOR3_177(n1650gat,n1727gat,n1659gat,n1640gat);
nor NOR2_235(n1801gat,n2152gat,n1989gat);
nor NOR3_178(n1731gat,n1658gat,n1515gat,n1797gat);
nor NOR3_179(n1649gat,n1560gat,n1659gat,n1730gat);
nor NOR3_180(n1571gat,n1670gat,n1658gat,n1797gat);
nor NOR3_181(n1563gat,n1561gat,n1562gat,n1659gat);
nor NOR2_236(n1734gat,n1988gat,n2212gat);
nor NOR3_182(n1669gat,n1668gat,n1742gat,n1670gat);
nor NOR2_237(n1654gat,n1671gat,n1659gat);
nor NOR3_183(n1657gat,n1662gat,n1797gat,n1658gat);
nor NOR3_184(n1653gat,n1651gat,n1652gat,n1659gat);
nor NOR3_185(n1729gat,n1658gat,n1797gat,n1568gat);
nor NOR3_186(n1644gat,n1643gat,n1648gat,n1659gat);
nor NOR3_187(n1726gat,n2992gat,n2986gat,n2991gat);
nor NOR2_238(n1929gat,n1758gat,n1790gat);
nor NOR3_188(n2009gat,n2016gat,n2664gat,n2004gat);
nor NOR3_189(n1413gat,n1869gat,n672gat,n2591gat);
nor NOR2_239(n1636gat,n1584gat,n1718gat);
nor NOR2_240(n1401gat,n1584gat,n1590gat);
nor NOR3_190(n1408gat,n1507gat,n1396gat,n1393gat);
nor NOR2_241(n1476gat,n1858gat,n1590gat);
nor NOR3_191(n1407gat,n1393gat,n1409gat,n1677gat);
nor NOR3_192(n1412gat,n1411gat,n1406gat,n2981gat);
nor NOR3_193(n2663gat,n2586gat,n2660gat,n2307gat);
nor NOR2_242(n2662gat,n2660gat,n2586gat);
nor NOR2_243(n2238gat,n2448gat,n2444gat);
nor NOR3_194(n87gat,n743gat,n17gat,n293gat);
nor NOR2_244(n200gat,n199gat,n92gat);
nor NOR3_195(n184gat,n189gat,n188gat,n179gat);
nor NOR2_245(n196gat,n297gat,n195gat);
nor NOR2_246(n204gat,n200gat,n196gat);
nor NOR4_8(n2163gat,n1790gat,n1310gat,n2664gat,n2168gat);
nor NOR2_247(n2258gat,n2260gat,n2189gat);
nor NOR2_248(n2255gat,n2261gat,n2188gat);
nor NOR3_196(n2015gat,n2039gat,n1774gat,n1315gat);
nor NOR2_249(n2017gat,n1790gat,n2016gat);
nor NOR2_250(n2018gat,n2016gat,n2097gat);
nor NOR4_9(n2014gat,n2035gat,n2093gat,n2018gat,n2664gat);
nor NOR2_251(n2194gat,n2187gat,n1855gat);
nor NOR2_252(n2192gat,n2184gat,n1855gat);
nor NOR2_253(n2185gat,n2261gat,n2189gat);
nor NOR2_254(n2132gat,n2133gat,n2131gat);
nor NOR2_255(n2130gat,n2134gat,n2185gat);
nor NOR2_256(n2057gat,n2049gat,n1855gat);
nor NOR2_257(n2250gat,n2248gat,n2264gat);
nor NOR2_258(n2249gat,n2265gat,n3006gat);
nor NOR2_259(n2329gat,n1855gat,n3007gat);
nor NOR2_260(n1958gat,n1963gat,n1886gat);
nor NOR3_197(n1895gat,n1845gat,n1891gat,n1968gat);
nor NOR2_261(n1710gat,n1709gat,n1629gat);
nor NOR2_262(n1630gat,n1895gat,n1631gat);
nor NOR2_263(n2195gat,n2200gat,n1855gat);
nor NOR2_264(n2556gat,n1711gat,n2437gat);
nor NOR2_265(n2539gat,n2048gat,n2437gat);
nor NOR3_198(n1894gat,n1968gat,n1891gat,n1969gat);
nor NOR2_266(n1847gat,n1958gat,n1845gat);
nor NOR2_267(n1846gat,n1845gat,n1893gat);
nor NOR2_268(n2436gat,n2437gat,n1892gat);
nor NOR2_269(n2055gat,n1891gat,n1958gat);
nor NOR2_270(n1967gat,n1893gat,n1968gat);
nor NOR2_271(n2387gat,n2056gat,n2437gat);
nor NOR2_272(n1959gat,n1956gat,n1963gat);
nor NOR2_273(n1957gat,n1886gat,n1887gat);
nor NOR2_274(n2330gat,n2437gat,n1961gat);
nor NOR2_275(n2147gat,n2988gat,n1855gat);
nor NOR2_276(n2498gat,n2199gat,n2328gat);
nor NOR2_277(n2193gat,n2393gat,n2439gat);
nor NOR2_278(n2211gat,n2193gat,n2402gat);
nor NOR2_279(n2210gat,n2401gat,n2151gat);
nor NOR2_280(n2396gat,n2199gat,n2209gat);
nor NOR2_281(n2053gat,n2393gat,n2438gat);
nor NOR2_282(n1964gat,n2392gat,n2439gat);
nor NOR2_283(n2198gat,n2199gat,n2058gat);
nor NOR3_199(n2215gat,n2346gat,n2151gat,n2402gat);
nor NOR2_284(n2350gat,n2405gat,n2349gat);
nor NOR2_285(n2282gat,n2406gat,n2215gat);
nor NOR2_286(n2197gat,n2199gat,n2281gat);
nor NOR3_200(n2213gat,n2402gat,n2151gat,n2345gat);
nor NOR2_287(n2150gat,n2401gat,n2346gat);
nor NOR2_288(n2149gat,n2193gat,n2346gat);
nor NOR2_289(n2196gat,n2199gat,n2146gat);
nor NOR3_201(n1882gat,n2124gat,n2115gat,n2239gat);
nor NOR2_290(n1962gat,n1963gat,n1893gat);
nor NOR2_291(n1896gat,n2995gat,n1895gat);
nor NOR2_292(n1972gat,n1974gat,n1970gat);
nor NOR2_293(n1971gat,n1896gat,n1973gat);
nor NOR2_294(n2559gat,n2999gat,n2437gat);
nor NOR2_295(n2331gat,n2393gat,n2401gat);
nor NOR2_296(n2352gat,n3011gat,n2215gat);
nor NOR2_297(n2566gat,n2643gat,n2564gat);
nor NOR2_298(n2565gat,n2352gat,n2642gat);
nor NOR2_299(n2637gat,n3015gat,n2199gat);
nor NOR3_202(n84gat,n296gat,n17gat,n294gat);
nor NOR2_300(n89gat,n88gat,n2784gat);
nor NOR2_301(n110gat,n182gat,n89gat);
nor NOR2_302(n1074gat,n2775gat,n110gat);
nor NOR3_203(n141gat,n155gat,n253gat,n150gat);
nor NOR2_303(n38gat,n151gat,n233gat);
nor NOR2_304(n37gat,n151gat,n154gat);
nor NOR2_305(n872gat,n375gat,n800gat);
nor NOR2_306(n234gat,n155gat,n233gat);
nor NOR2_307(n137gat,n154gat,n253gat);
nor NOR2_308(n378gat,n375gat,n235gat);
nor NOR2_309(n377gat,n110gat,n2778gat);
nor NOR2_310(n869gat,n219gat,n2792gat);
nor NOR2_311(n212gat,n182gat,n78gat);
nor NOR3_204(n250gat,n329gat,n387gat,n334gat);
nor NOR2_312(n249gat,n386gat,n330gat);
nor NOR2_313(n248gat,n330gat,n1490gat);
nor NOR2_314(n453gat,n372gat,n452gat);
nor NOR2_315(n448gat,n111gat,n2846gat);
nor NOR2_316(n974gat,n2844gat,n111gat);
nor NOR2_317(n251gat,n1490gat,n387gat);
nor NOR2_318(n244gat,n334gat,n386gat);
nor NOR2_319(n973gat,n372gat,n333gat);
nor NOR2_320(n870gat,n2669gat,n219gat);
nor NOR2_321(n975gat,n111gat,n2852gat);
nor NOR3_205(n246gat,n330gat,n325gat,n334gat);
nor NOR2_322(n245gat,n386gat,n334gat);
nor NOR2_323(n460gat,n462gat,n2884gat);
nor NOR2_324(n459gat,n457gat,n461gat);
nor NOR2_325(n972gat,n372gat,n458gat);
nor NOR2_326(n969gat,n219gat,n2672gat);
nor NOR2_327(n971gat,n111gat,n2840gat);
nor NOR3_206(n247gat,n334gat,n387gat,n330gat);
nor NOR2_328(n145gat,n144gat,n325gat);
nor NOR2_329(n143gat,n326gat,n247gat);
nor NOR2_330(n970gat,n372gat,n878gat);
nor NOR2_331(n968gat,n2789gat,n219gat);
nor NOR2_332(n772gat,n111gat,n2842gat);
nor NOR3_207(n142gat,n382gat,n326gat,n144gat);
nor NOR2_333(n40gat,n325gat,n383gat);
nor NOR2_334(n39gat,n383gat,n247gat);
nor NOR2_335(n451gat,n134gat,n372gat);
nor NOR2_336(n446gat,n219gat,n2781gat);
nor NOR3_208(n139gat,n253gat,n151gat,n254gat);
nor NOR2_337(n136gat,n253gat,n154gat);
nor NOR2_338(n391gat,n252gat,n468gat);
nor NOR2_339(n390gat,n469gat,n2877gat);
nor NOR2_340(n1083gat,n381gat,n375gat);
nor NOR2_341(n1077gat,n110gat,n2672gat);
nor NOR3_209(n140gat,n151gat,n253gat,n155gat);
nor NOR2_342(n242gat,n254gat,n241gat);
nor NOR2_343(n240gat,n255gat,n140gat);
nor NOR2_344(n871gat,n802gat,n375gat);
nor NOR2_345(n797gat,n110gat,n2734gat);
nor NOR3_210(n324gat,n255gat,n146gat,n241gat);
nor NOR2_346(n238gat,n147gat,n254gat);
nor NOR2_347(n237gat,n140gat,n147gat);
nor NOR2_348(n1082gat,n375gat,n380gat);
nor NOR2_349(n796gat,n2731gat,n110gat);
nor NOR3_211(n85gat,n17gat,n294gat,n637gat);
nor NOR3_212(n180gat,n286gat,n188gat,n287gat);
nor NOR2_350(n68gat,n85gat,n180gat);
nor NOR3_213(n186gat,n189gat,n287gat,n288gat);
nor NOR2_351(n357gat,n2726gat,n2860gat);
nor NOR3_214(n82gat,n16gat,n295gat,n637gat);
nor NOR2_352(n12gat,n186gat,n82gat);
nor NOR2_353(n1599gat,n1691gat,n336gat);
nor NOR2_354(n1613gat,n1544gat,n1698gat);
nor NOR3_215(n1756gat,n2512gat,n1769gat,n1773gat);
nor NOR2_355(n1586gat,n1869gat,n1683gat);
nor NOR3_216(n1755gat,n1769gat,n1773gat,n2512gat);
nor NOR3_217(n2538gat,n2620gat,n2625gat,n2488gat);
nor NOR3_218(n2483gat,n2537gat,n2482gat,n2486gat);
nor NOR2_356(n1391gat,n1513gat,n2442gat);
nor NOR3_219(n1471gat,n1334gat,n1858gat,n1604gat);
nor NOR2_357(n1469gat,n1858gat,n1608gat);
nor NOR3_220(n1472gat,n1476gat,n1471gat,n1469gat);
nor NOR2_358(n1927gat,n1790gat,n1635gat);
nor NOR2_359(n1470gat,n1472gat,n1747gat);
nor NOR3_221(n1402gat,n1858gat,n1393gat,n1604gat);
nor NOR2_360(n1400gat,n1674gat,n1403gat);
nor NOR2_361(n1567gat,n1634gat,n1735gat);
nor NOR3_222(n1399gat,n1806gat,n1338gat,n1584gat);
nor NOR4_10(n1564gat,n1584gat,n1719gat,n1790gat,n1576gat);
nor NOR2_362(n1600gat,n1685gat,n1427gat);
nor NOR3_223(n1519gat,n1584gat,n1339gat,n1600gat);
nor NOR2_363(n1397gat,n1519gat,n1401gat);
nor NOR2_364(n1398gat,n1455gat,n1397gat);
nor NOR2_365(n2008gat,n2012gat,n1774gat);
nor NOR2_366(n2005gat,n2002gat,n2857gat);
nor NOR2_367(n1818gat,n1823gat,n2005gat);
nor NOR3_224(n1759gat,n1818gat,n1935gat,n2765gat);
nor NOR3_225(n1686gat,n1774gat,n1869gat,n1684gat);
nor NOR2_368(n1533gat,n1524gat,n1403gat);
nor NOR3_226(n1863gat,n1991gat,n2283gat,n1989gat);
nor NOR3_227(n1860gat,n1988gat,n2216gat,n1862gat);
nor NOR2_369(n1915gat,n1859gat,n1919gat);
nor NOR2_370(n1510gat,n1584gat,n1460gat);
nor NOR2_371(n1800gat,n1635gat,n1919gat);
nor NOR2_372(n1459gat,n1595gat,n1454gat);
nor NOR2_373(n1458gat,n1510gat,n1459gat);
nor NOR2_374(n1532gat,n1677gat,n1458gat);
nor NOR2_375(n1467gat,n2289gat,n1468gat);
nor NOR3_228(n1466gat,n1392gat,n1461gat,n1396gat);
nor NOR2_376(n1531gat,n1507gat,n1477gat);
nor NOR2_377(n1593gat,n1551gat,n1310gat);
nor NOR3_229(n1602gat,n1594gat,n1587gat,n2989gat);
nor NOR3_230(n1761gat,n2985gat,n1602gat,n1681gat);
nor NOR3_231(n1760gat,n1681gat,n1602gat,n2985gat);
nor NOR3_232(n1721gat,n2442gat,n1690gat,n1978gat);
nor NOR2_378(n520gat,n374gat,n2862gat);
nor NOR2_379(n519gat,n2854gat,n374gat);
nor NOR2_380(n518gat,n520gat,n519gat);
nor NOR2_381(n418gat,n374gat,n2723gat);
nor NOR2_382(n411gat,n374gat,n2726gat);
nor NOR2_383(n522gat,n374gat,n2859gat);
nor NOR2_384(n516gat,n374gat,n2715gat);
nor NOR4_11(n410gat,n417gat,n413gat,n412gat,n406gat);
nor NOR2_385(n354gat,n411gat,n522gat);
nor NOR3_233(n355gat,n517gat,n410gat,n354gat);
nor NOR2_386(n408gat,n516gat,n407gat);
nor NOR2_387(n526gat,n2859gat,n740gat);
nor NOR2_388(n531gat,n740gat,n2854gat);
nor NOR2_389(n530gat,n2862gat,n740gat);
nor NOR3_234(n525gat,n526gat,n531gat,n530gat);
nor NOR2_390(n356gat,n2726gat,n740gat);
nor NOR2_391(n415gat,n2723gat,n740gat);
nor NOR2_392(n521gat,n740gat,n2715gat);
nor NOR3_235(n532gat,n527gat,n416gat,n528gat);
nor NOR2_393(n359gat,n290gat,n358gat);
nor NOR2_394(n420gat,n408gat,n359gat);
nor NOR2_395(n523gat,n522gat,n356gat);
nor NOR2_396(n634gat,n418gat,n521gat);
nor NOR2_397(n414gat,n411gat,n415gat);
nor NOR3_236(n635gat,n639gat,n634gat,n414gat);
nor NOR2_398(n1100gat,n1297gat,n1111gat);
nor NOR3_237(n630gat,n634gat,n523gat,n524gat);
nor NOR2_399(n994gat,n1112gat,n882gat);
nor NOR3_238(n629gat,n414gat,n634gat,n523gat);
nor NOR2_400(n989gat,n721gat,n741gat);
nor NOR3_239(n632gat,n414gat,n523gat,n633gat);
nor NOR2_401(n880gat,n926gat,n566gat);
nor NOR3_240(n636gat,n414gat,n633gat,n639gat);
nor NOR2_402(n801gat,n672gat,n670gat);
nor NOR2_403(n879gat,n2931gat,n801gat);
nor NOR2_404(n1003gat,n420gat,n879gat);
nor NOR2_405(n1255gat,n1123gat,n1225gat);
nor NOR2_406(n1012gat,n1007gat,n918gat);
nor NOR2_407(n905gat,n625gat,n1006gat);
nor NOR2_408(n1009gat,n1255gat,n2943gat);
nor NOR2_409(n409gat,n406gat,n407gat);
nor NOR2_410(n292gat,n415gat,n356gat);
nor NOR2_411(n291gat,n290gat,n292gat);
nor NOR2_412(n419gat,n409gat,n291gat);
nor NOR2_413(n902gat,n1009gat,n419gat);
nor NOR2_414(n1099gat,n1111gat,n1293gat);
nor NOR2_415(n998gat,n725gat,n741gat);
nor NOR2_416(n995gat,n823gat,n1112gat);
nor NOR2_417(n980gat,n875gat,n926gat);
nor NOR2_418(n1001gat,n420gat,n1002gat);
nor NOR2_419(n1175gat,n621gat,n1006gat);
nor NOR2_420(n1174gat,n845gat,n1007gat);
nor NOR2_421(n1243gat,n1281gat,n1123gat);
nor NOR2_422(n1171gat,n2960gat,n1243gat);
nor NOR2_423(n999gat,n419gat,n1171gat);
nor NOR2_424(n1244gat,n1123gat,n1134gat);
nor NOR2_425(n1323gat,n1007gat,n401gat);
nor NOR2_426(n1264gat,n1006gat,n617gat);
nor NOR2_427(n1265gat,n1244gat,n2969gat);
nor NOR2_428(n892gat,n419gat,n1265gat);
nor NOR2_429(n981gat,n926gat,n873gat);
nor NOR2_430(n890gat,n741gat,n702gat);
nor NOR2_431(n889gat,n1111gat,n1079gat);
nor NOR2_432(n886gat,n683gat,n1112gat);
nor NOR2_433(n891gat,n420gat,n888gat);
nor NOR2_434(n904gat,n1006gat,n490gat);
nor NOR2_435(n903gat,n1007gat,n397gat);
nor NOR2_436(n1254gat,n1123gat,n1044gat);
nor NOR2_437(n1008gat,n2942gat,n1254gat);
nor NOR2_438(n900gat,n419gat,n1008gat);
nor NOR2_439(n1152gat,n926gat,n1150gat);
nor NOR2_440(n1092gat,n1147gat,n1111gat);
nor NOR2_441(n997gat,n741gat,n393gat);
nor NOR2_442(n993gat,n1112gat,n698gat);
nor NOR2_443(n895gat,n420gat,n898gat);
nor NOR2_444(n1094gat,n1112gat,n583gat);
nor NOR2_445(n1093gat,n1111gat,n864gat);
nor NOR2_446(n988gat,n340gat,n741gat);
nor NOR2_447(n984gat,n926gat,n983gat);
nor NOR2_448(n1178gat,n420gat,n1179gat);
nor NOR2_449(n1267gat,n613gat,n1006gat);
nor NOR2_450(n1257gat,n1007gat,n274gat);
nor NOR2_451(n1253gat,n930gat,n1123gat);
nor NOR2_452(n1266gat,n2965gat,n1253gat);
nor NOR2_453(n1116gat,n419gat,n1266gat);
nor NOR2_454(n1375gat,n1006gat,n706gat);
nor NOR2_455(n1324gat,n164gat,n1007gat);
nor NOR2_456(n1200gat,n1120gat,n1123gat);
nor NOR2_457(n1172gat,n2961gat,n1200gat);
nor NOR2_458(n899gat,n419gat,n1172gat);
nor NOR2_459(n1091gat,n1111gat,n956gat);
nor NOR2_460(n1088gat,n1085gat,n926gat);
nor NOR2_461(n992gat,n815gat,n1112gat);
nor NOR2_462(n987gat,n741gat,n159gat);
nor NOR2_463(n896gat,n897gat,n420gat);
nor NOR2_464(n1262gat,n837gat,n1006gat);
nor NOR2_465(n1260gat,n1007gat,n278gat);
nor NOR2_466(n1251gat,n1123gat,n1071gat);
nor NOR2_467(n1259gat,n2967gat,n1251gat);
nor NOR2_468(n901gat,n419gat,n1259gat);
nor NOR2_469(n1098gat,n336gat,n741gat);
nor NOR2_470(n1090gat,n1111gat,n860gat);
nor NOR2_471(n986gat,n985gat,n926gat);
nor NOR2_472(n885gat,n579gat,n1112gat);
nor NOR2_473(n893gat,n894gat,n420gat);
nor NOR2_474(n1097gat,n270gat,n741gat);
nor NOR2_475(n1089gat,n1067gat,n1111gat);
nor NOR2_476(n1087gat,n926gat,n1084gat);
nor NOR2_477(n991gat,n1112gat,n679gat);
nor NOR2_478(n1177gat,n1180gat,n420gat);
nor NOR2_479(n1212gat,n1123gat,n1034gat);
nor NOR2_480(n1326gat,n1007gat,n282gat);
nor NOR2_481(n1261gat,n833gat,n1006gat);
nor NOR2_482(n1263gat,n1212gat,n2968gat);
nor NOR2_483(n1115gat,n1263gat,n419gat);
nor NOR2_484(n977gat,n670gat,n671gat);
nor NOR3_241(n631gat,n523gat,n633gat,n524gat);
nor NOR2_485(n1096gat,n819gat,n1112gat);
nor NOR2_486(n1095gat,n1240gat,n1111gat);
nor NOR2_487(n990gat,n841gat,n741gat);
nor NOR2_488(n979gat,n1601gat,n926gat);
nor NOR2_489(n978gat,n2944gat,n2945gat);
nor NOR2_490(n1004gat,n978gat,n420gat);
nor NOR2_491(n1199gat,n1123gat,n1284gat);
nor NOR2_492(n1176gat,n829gat,n1006gat);
nor NOR2_493(n1173gat,n1007gat,n1025gat);
nor NOR2_494(n1252gat,n1199gat,n2962gat);
nor NOR2_495(n1000gat,n419gat,n1252gat);
nor NOR2_496(n1029gat,n978gat,n455gat);
nor NOR2_497(n1028gat,n455gat,n879gat);
nor NOR2_498(n1031gat,n1002gat,n455gat);
nor NOR2_499(n1030gat,n455gat,n888gat);
nor NOR2_500(n1011gat,n455gat,n898gat);
nor NOR2_501(n1181gat,n455gat,n1179gat);
nor NOR2_502(n1010gat,n897gat,n455gat);
nor NOR2_503(n1005gat,n894gat,n455gat);
nor NOR2_504(n1182gat,n1180gat,n455gat);
nor NOR2_505(n1757gat,n1773gat,n1769gat);
nor NOR2_506(n1745gat,n1869gat,n1757gat);
nor NOR2_507(n73gat,n67gat,n2784gat);
nor NOR2_508(n70gat,n71gat,n2720gat);
nor NOR2_509(n77gat,n76gat,n2784gat);
nor NOR2_510(n13gat,n2720gat,n14gat);
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:42 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_2_sim_netlist.v
// Design : gcd_block_design_processing_system7_0_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "gcd_block_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [0:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_WP;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "gcd_block_design_processing_system7_0_2.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(SDIO0_WP),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "gcd_block_design_processing_system7_0_2.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_BEHAVIORAL_V |
/******************************************************************************
* File Name : ec_alu.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : This file contains the module for ALU of the
* elliptic curve processor for the curve
* y^2 + xy = x^3 + a.x^2 + b
* where a = 1
******************************************************************************/
`timescale 1ns / 1ps
`ifndef __ECALU_V__
`define __ECALU_V__
//`include "ff/multiplier.v"
//`include "ff/sqr.v"
//`include "mux8.v"
//`include "mux4.v"
/*---------------------------------------------------------------------------
* Module Name : ec_alu
* Synopsis : Elliptic Curve ALU
* Finite field elements are instantiated over here
* 1. Multiplier
* 2. Squarers
*--------------------------------------------------------------------------*/
module ec_alu(cw, a0, a1, a2, a3, c0, c1);
input wire [232:0] a0, a1, a2, a3; /* the inputs to the alu */
input wire [9:0] cw; /* the control word */
output wire [232:0] c0, c1; /* the alu outputs */
/* Temporary results */
wire [232:0] a0sq, a0qu;
wire [232:0] a1sq, a1qu;
wire [232:0] a2sq, a2qu;
wire [232:0] sa2, sa4, sa5, sa7, sa8, sa8_1;
wire [232:0] sc1;
wire [232:0] sd2, sd2_1;
/* Multiplier inputs and output */
wire [232:0] minA, minB, mout;
multiplier mul(minA, minB, mout);
squarer sq1_p0(a0, a0sq);
squarer sq_p1(a1, a1sq);
squarer sq_p2(a2, a2sq);
squarer sq2_p2(a2sq, a2qu);
squarer sq2_p1(a1sq, a1qu);
squarer sq2_p3(a0sq, a0qu);
/* Choose the inputs to the Multiplier */
mux8 muxA(a0, a0sq, a2, sa7, sd2, a1, a1qu, 233'd0, cw[2:0], minA);
mux8 muxB(a1, a1sq, sa4, sa8, sd2_1, a3, a2qu,a1qu, cw[5:3], minB);
/* Choose the outputs of the ALU */
mux4 muxC(mout, sa2, a1sq, sc1, cw[7:6], c0);
mux4 muxD(sa8_1, sa5, a1qu, sd2, cw[9:8], c1);
assign sa2 = mout ^ a2;
assign sa4 = a1sq ^ a2;
assign sa5 = mout ^ a2sq ^ a0;
assign sa7 = a0 ^ a2;
assign sa8 = a1 ^ a3;
assign sa8_1 = mout ^ a0;
assign sc1 = mout ^ a3;
assign sd2 = a0qu ^ a1;
assign sd2_1 = a2sq ^ a3 ^ a1;
endmodule
`endif
|
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Licznik robienia kawki
//////////////////////////////////////////////////////////////////////////////////
module counter(clk, count_in, count_out, count_secs);
input clk;
input [3:0] count_in;
output reg count_out;
output wire [6:0]count_secs; // przekazanie pozosta³ego czasu (w sekundach) do modu³u g³ownego
// potrzebna do wywietlacza - 7 bit = max 127 sek (wystarczy)
reg [22:0] count_to_0 = 0; //rejestr 23 bitowy, przy zegarze 50kHz wystarczy na odliczanie od 167 sekund
// pozostaje przeliczyæ czasy
// 1 s = 1 000 000 000 ns
// 1 s = 1 000 000 us
parameter tick_every = 20; // parametr co ile nastêpuje tick zegara (w us)
integer mc = 1000000/tick_every; // mno¿nik dla czasu w sekundach (czêstotliwoæ w Hz)
// wysy³amy pozosta³y czas do modu³u top (w sekundach)
assign count_secs = count_to_0/mc;
always @(count_in)
begin
case (count_in)
`LICZNIK_RESET: // reset licznika
begin
count_out <= `NIC_NIE_ODLICZAM;
count_to_0 <= 0;
end
`ODLICZ_KUBEK: // maszyna podstawia kubek
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KUBEK*mc;
end
`ODLICZ_KAWA_OP1: // maszyna mieli kawê dla opcji 1
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA1*mc;
end
`ODLICZ_KAWA_OP2: // maszyna mieli kawê dla opcji 2
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA2*mc;
end
`ODLICZ_KAWA_OP3: // maszyna mieli kawê dla opcji 3
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA3*mc;
end
`ODLICZ_WODA_OP1: // maszyna wlewa wrz¹tek dla opcji 1
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA1*mc;
end
`ODLICZ_WODA_OP2: // maszyna wlewa wrz¹tek dla opcji 2
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA2*mc;
end
`ODLICZ_WODA_OP3: // maszyna wlewa wrz¹tek dla opcji 3
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA3*mc;
end
`ODLICZ_MLEKO: // maszyna spienia mleko
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_MLEKO*mc;
end
`ODLICZ_NAPELN: // maszyna wype³nia przewody wod¹
begin
count_out <= `ODLICZAM;
count_to_0 <= `CZAS_NAPELN*mc;
end
`ODLICZ_CZYSC: // maszyna usuwa zu¿yt¹ kawê, czyci instalacjê, usuwa wodê z przewodów
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_CZYSC*mc;
end
endcase;
end
always @(negedge clk) // odliczanie do 0
begin
if(count_out == `ODLICZAM && count_to_0 > 0)
count_to_0 <= count_to_0 - 1;
else
count_out <= `SKONCZYLEM_ODLICZAC; // skoñczylimy odliczaæ
end
endmodule |
// P-A unit (ALU and friends)
module pa(
input clk_sys,
input [0:15] ir,
input [0:15] bus_ki,
input [0:15] rdt,
input w_dt,
input mwa,
input mwb,
input mwc,
input bwa,
input bwb,
output [0:15] ddt,
output [0:15] w,
input saryt,
input sab,
input scb,
input sb,
input sd,
output s0,
output carry,
input p16,
input saa,
input sca,
output j$,
output exx,
input wx,
input eat0,
input axy,
output at15,
output exy,
input w_ac,
input strob1,
input strob1b,
input strob2,
input strob2b,
input as2,
input am1,
input apb,
input amb,
input ap1,
output s_1,
output wzi,
output zs,
input arm4,
input w_ar,
input arp1,
output arz,
input icp1,
input w_ic,
input off,
input baa,
input bab,
input bac,
input ab,
input aa,
input [0:15] l,
input barnb,
input [0:15] kl,
input ic_ad,
output [0:15] dad,
input ar_ad,
output zga
);
bus_w BUS_W(
.mwc(mwc),
.mwb(mwb),
.mwa(mwa),
.bwa(bwa),
.bwb(bwb),
.ir(ir),
.kl(kl),
.rdt(rdt),
.ki(bus_ki),
.at(at),
.ac(ac),
.a(a),
.w(w)
);
assign ddt = w_dt ? w : 16'd0;
wire [0:15] f;
wire zsum;
alu ALU(
.p16_(~p16),
.a(a),
.ac(ac),
.saryt(saryt),
.sd(sd),
.sb(sb),
.scb(scb),
.sab(sab),
.sca(sca),
.saa(saa),
.f(f),
.j$(j$),
.carry(carry),
.zsum(zsum)
);
assign s0 = f[0];
assign exx = (a[15] & ir[6]) | (a[0] & ~ir[6]);
wire [0:15] at;
at REG_AT(
.clk_sys(clk_sys),
.s0(wx | as2),
.s1(as2),
.c(strob1b),
.sl(eat0),
.f(f),
.at(at)
);
assign at15 = at[15];
assign exy = (at[15] & axy) | (a[0] & ~axy);
wire strobb = as2 & strob2b;
wire stroba = ~as2 & strob1b;
wire ac_clk = w_ac & (stroba | strobb);
wire [0:15] ac;
ac REG_AC(
.clk_sys(clk_sys),
.c(ac_clk),
.w(w),
.ac(ac)
);
wire M8_11 = ac[0] ^ a[0];
wire M8_3 = ~ac[0] ^ a[0];
wire M7_8 = (~a[0] & am1) | (M8_11 & apb) | (M8_3 & amb) | (a[0] & ap1);
assign s_1 = ~M7_8 ^ ~carry;
assign zs = ~s_1 & zsum;
// WZI - wskaźnik zera sumatora
wire wzi_clk = as2 & strob1b;
always @ (posedge clk_sys) begin
if (wzi_clk) wzi <= zs;
end
wire ar_load = w_ar & (stroba | strobb);
wire ar_plus1 = arp1 & stroba;
wire [0:15] ar;
ar REG_AR(
.clk_sys(clk_sys),
.l(ar_load),
.p1(ar_plus1),
.m4(arm4),
.w(w),
.arz(arz),
.ar(ar)
);
wire ic_plus1 = icp1 & strob1b;
wire ic_load = w_ic & (stroba | strobb);
wire [0:15] ic;
ic REG_IC(
.clk_sys(clk_sys),
.cu(ic_plus1),
.l(ic_load),
.r(off),
.w(w),
.ic(ic)
);
wire [0:15] a;
bus_a BUS_A(
.bac(bac),
.bab(bab),
.baa(baa),
.aa(aa),
.ab(ab),
.l(l),
.ir(ir),
.ar(ar),
.ic(ic),
.a(a)
);
always @ (*) begin
case ({ar_ad, ic_ad})
2'b00 : dad = 16'd0;
2'b01 : dad = ic;
2'b10 : dad = ar;
2'b11 : dad = ic | ar; // Unused, but in original design it would be just that
endcase
end
assign zga = (kl[0:15] == {~barnb, dad[1:15]});
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
//Legal Notice: (C)2021 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
`default_nettype none
`timescale 1ns/1ns
module tb_inst_level;
`include "../task/task_disp_branch.v"
`include "../task/task_disp_loadstore.v"
localparam PL_CORE_CYCLE = 20; //It's necessary "Core Clock == Bus Clock". This restriction is removed near future.
localparam PL_BUS_CYCLE = 20; //
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
localparam PL_GCI_SIZE = 32'h0001_0000;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
wire iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire [3:0] oMEMORY_MASK;
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
wire iMEMORY_VALID;
wire oMEMORY_BUSY;
wire [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
mist1032isa TARGET(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(iBUS_CLOCK),
.iDPS_CLOCK(iDPS_CLOCK),
.inRESET(inRESET),
/****************************************
SCI
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(oMEMORY_REQ),
.iMEMORY_LOCK(iMEMORY_LOCK),
.oMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.oMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.oMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.iMEMORY_VALID(iMEMORY_VALID),
.oMEMORY_BUSY(oMEMORY_BUSY),
.iMEMORY_DATA(iMEMORY_DATA),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(oGCI_REQ), //Input
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ), //Output
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
.oDEBUG_PC(oDEBUG_PC),
.oDEBUG0(oDEBUG0),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
$display("Check Start");
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
//GCI Init
#(PL_BUS_CYCLE*32);
while(oGCI_BUSY) #(PL_BUS_CYCLE);
iGCI_REQ = 1'b1;
iGCI_DATA = PL_GCI_SIZE;
#(PL_BUS_CYCLE);
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
#15000000 begin
$stop;
end
end
/******************************************************
Simulation Task
******************************************************/
always@(posedge iCORE_CLOCK)begin
if(inRESET)begin
//task_disp_branch();
task_disp_loadstore();
end
end
/******************************************************
Memory Model
******************************************************/
sim_memory_model #(1, "tb_inst_test.hex") MEMORY_MODEL(
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//Req
.iMEMORY_REQ(oMEMORY_REQ),
.oMEMORY_LOCK(iMEMORY_LOCK),
.iMEMORY_ORDER(oMEMORY_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iMEMORY_MASK(oMEMORY_MASK),
.iMEMORY_RW(oMEMORY_RW), //1:Write | 0:Read
.iMEMORY_ADDR(oMEMORY_ADDR),
//This -> Data RAM
.iMEMORY_DATA(oMEMORY_DATA),
//Data RAM -> This
.oMEMORY_VALID(iMEMORY_VALID),
.iMEMORY_LOCK(oMEMORY_BUSY),
.oMEMORY_DATA(iMEMORY_DATA)
);
/******************************************************
Assertion
******************************************************/
reg assert_check_flag;
reg [31:0] assert_wrong_number;
reg [31:0] assert_wrong_type;
reg [31:0] assert_result;
reg [31:0] assert_expect;
always@(posedge iCORE_CLOCK)begin
if(inRESET && oMEMORY_REQ && !iMEMORY_LOCK && oMEMORY_ORDER == 2'h2 && oMEMORY_RW)begin
//Finish Check
if(oMEMORY_ADDR == 32'h0002_0004)begin
if(!assert_check_flag)begin
$display("[SIM-ERR]Wrong Data.");
$display("[SIM-ERR]Wrong Type : %d", assert_wrong_type);
$display("[SIM-ERR]Index:%d, Expect:%x, Result:%x", assert_wrong_number, assert_expect, assert_result);
$display("[SIM-ERR]Simulation Finished.");
$finish;
end
else begin
$display("[SIM-OK]Simulation Finished.");
$finish;
end
end
//Check Flag
else if(oMEMORY_ADDR == 32'h0002_0000)begin
assert_check_flag = oMEMORY_DATA[24];
end
//Error Number
else if(oMEMORY_ADDR == 32'h0002_000c)begin
assert_wrong_number = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Type
else if(oMEMORY_ADDR == 32'h0002_0008)begin
assert_wrong_type = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Result
else if(oMEMORY_ADDR == 32'h0002_0010)begin
assert_result = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
//Error Expect
else if(oMEMORY_ADDR == 32'h0002_0014)begin
assert_expect = {oMEMORY_DATA[7:0], oMEMORY_DATA[15:8], oMEMORY_DATA[23:16], oMEMORY_DATA[31:24]};
end
end
end
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_BLACKBOX_V
`define SKY130_FD_SC_LS__A41O_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_BLACKBOX_V
|
module top (
fpga_clk_50,
fpga_reset_n,
ledr, // LEDR
hex0, //HEX0
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
emac_mdio,
emac_mdc,
emac_tx_ctl,
emac_tx_clk,
emac_txd,
emac_rx_ctl,
emac_rx_clk,
emac_rxd,
hps_usb1_D0,
hps_usb1_D1,
hps_usb1_D2,
hps_usb1_D3,
hps_usb1_D4,
hps_usb1_D5,
hps_usb1_D6,
hps_usb1_D7,
hps_usb1_CLK,
hps_usb1_STP,
hps_usb1_DIR,
hps_usb1_NXT,
sd_cmd,
sd_clk,
sd_d,
uart_rx,
uart_tx,
led,
i2c_sda,
i2c_scl
);
input wire fpga_clk_50;
input wire fpga_reset_n;
output wire [9:0] ledr;
output wire [3:0] hex0;
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
inout wire emac_mdio;
output wire emac_mdc;
output wire emac_tx_ctl;
output wire emac_tx_clk;
output wire [3:0] emac_txd;
input wire emac_rx_ctl;
input wire emac_rx_clk;
input wire [3:0] emac_rxd;
inout wire hps_usb1_D0;
inout wire hps_usb1_D1;
inout wire hps_usb1_D2;
inout wire hps_usb1_D3;
inout wire hps_usb1_D4;
inout wire hps_usb1_D5;
inout wire hps_usb1_D6;
inout wire hps_usb1_D7;
input wire hps_usb1_CLK;
output wire hps_usb1_STP;
input wire hps_usb1_DIR;
input wire hps_usb1_NXT;
inout wire sd_cmd;
output wire sd_clk;
inout wire [3:0] sd_d;
input wire uart_rx;
output wire uart_tx;
inout wire led;
inout wire i2c_scl;
inout wire i2c_sda;
wire [29:0] fpga_internal_led;
wire kernel_clk;
system the_system (
.reset_50_reset_n (fpga_reset_n),
.clk_50_clk (fpga_clk_50),
.kernel_clk_clk (kernel_clk),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
.peripheral_hps_io_emac1_inst_MDIO (emac_mdio),
.peripheral_hps_io_emac1_inst_MDC (emac_mdc),
.peripheral_hps_io_emac1_inst_TX_CLK (emac_tx_clk),
.peripheral_hps_io_emac1_inst_TX_CTL (emac_tx_ctl),
.peripheral_hps_io_emac1_inst_TXD0 (emac_txd[0]),
.peripheral_hps_io_emac1_inst_TXD1 (emac_txd[1]),
.peripheral_hps_io_emac1_inst_TXD2 (emac_txd[2]),
.peripheral_hps_io_emac1_inst_TXD3 (emac_txd[3]),
.peripheral_hps_io_emac1_inst_RX_CLK (emac_rx_clk),
.peripheral_hps_io_emac1_inst_RX_CTL (emac_rx_ctl),
.peripheral_hps_io_emac1_inst_RXD0 (emac_rxd[0]),
.peripheral_hps_io_emac1_inst_RXD1 (emac_rxd[1]),
.peripheral_hps_io_emac1_inst_RXD2 (emac_rxd[2]),
.peripheral_hps_io_emac1_inst_RXD3 (emac_rxd[3]),
.peripheral_hps_io_usb1_inst_D0 (hps_usb1_D0 ), // .hps_io_usb1_inst_D0
.peripheral_hps_io_usb1_inst_D1 (hps_usb1_D1 ), // .hps_io_usb1_inst_D1
.peripheral_hps_io_usb1_inst_D2 (hps_usb1_D2 ), // .hps_io_usb1_inst_D2
.peripheral_hps_io_usb1_inst_D3 (hps_usb1_D3 ), // .hps_io_usb1_inst_D3
.peripheral_hps_io_usb1_inst_D4 (hps_usb1_D4), // .hps_io_usb1_inst_D4
.peripheral_hps_io_usb1_inst_D5 (hps_usb1_D5 ), // .hps_io_usb1_inst_D5
.peripheral_hps_io_usb1_inst_D6 (hps_usb1_D6 ), // .hps_io_usb1_inst_D6
.peripheral_hps_io_usb1_inst_D7 (hps_usb1_D7 ), // .hps_io_usb1_inst_D7
.peripheral_hps_io_usb1_inst_CLK (hps_usb1_CLK ), // .hps_io_usb1_inst_CLK
.peripheral_hps_io_usb1_inst_STP (hps_usb1_STP ), // .hps_io_usb1_inst_STP
.peripheral_hps_io_usb1_inst_DIR (hps_usb1_DIR), // .hps_io_usb1_inst_DIR
.peripheral_hps_io_usb1_inst_NXT (hps_usb1_NXT ), // .hps_io_usb1_inst_NXT
.peripheral_hps_io_sdio_inst_CMD (sd_cmd),
.peripheral_hps_io_sdio_inst_CLK (sd_clk),
.peripheral_hps_io_sdio_inst_D0 (sd_d[0]),
.peripheral_hps_io_sdio_inst_D1 (sd_d[1]),
.peripheral_hps_io_sdio_inst_D2 (sd_d[2]),
.peripheral_hps_io_sdio_inst_D3 (sd_d[3]),
.peripheral_hps_io_uart0_inst_RX (uart_rx),
.peripheral_hps_io_uart0_inst_TX (uart_tx),
.peripheral_hps_io_gpio_inst_GPIO53 (led),
.acl_iface_led_pio_external_connection_export (ledr[7:0]), //FPGA LED_PIO
.peripheral_hps_io_i2c1_inst_SDA (i2c_sda),
.peripheral_hps_io_i2c1_inst_SCL (i2c_scl)
);
// module for visualizing the kernel clock with 4 LEDs
async_counter_30 AC30 (
.clk (kernel_clk),
.count (fpga_internal_led)
);
// assign fpga_led_output[3:0] = ~fpga_internal_led[29:26];
assign hex0[3:0] = ~fpga_internal_led[29:26];
endmodule
module async_counter_30(clk, count);
input clk;
output [29:0] count;
reg [14:0] count_a;
reg [14:0] count_b;
initial count_a = 15'b0;
initial count_b = 15'b0;
always @(negedge clk)
count_a <= count_a + 1'b1;
always @(negedge count_a[14])
count_b <= count_b + 1'b1;
assign count = {count_b, count_a};
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_2_V
`define SKY130_FD_SC_MS__MAJ3_2_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:16:47 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353;
NAND2X1TS U35 ( .A(n62), .B(n195), .Y(n192) );
INVX2TS U36 ( .A(n52), .Y(n207) );
NAND2X1TS U37 ( .A(n205), .B(n204), .Y(n206) );
NAND2X1TS U38 ( .A(n239), .B(n238), .Y(n240) );
NAND2X1TS U39 ( .A(n245), .B(n244), .Y(n246) );
NAND2X1TS U40 ( .A(n252), .B(n251), .Y(n253) );
AOI21X2TS U41 ( .A0(n258), .A1(n243), .B0(n242), .Y(n247) );
AOI21X2TS U42 ( .A0(n258), .A1(n256), .B0(n249), .Y(n254) );
CMPR32X2TS U43 ( .A(in1[6]), .B(n328), .C(n320), .CO(n318), .S(res[6]) );
NAND2X1TS U44 ( .A(n202), .B(in1[31]), .Y(n203) );
CLKINVX1TS U45 ( .A(n232), .Y(n245) );
NOR2X1TS U46 ( .A(n336), .B(in1[8]), .Y(n349) );
NAND2X4TS U47 ( .A(n59), .B(n184), .Y(n58) );
NAND2X1TS U48 ( .A(n182), .B(in1[28]), .Y(n212) );
INVX4TS U49 ( .A(n164), .Y(n59) );
CLKMX2X2TS U50 ( .A(in2[30]), .B(n190), .S0(add_sub), .Y(n191) );
MX2X1TS U51 ( .A(in2[29]), .B(n187), .S0(add_sub), .Y(n188) );
CMPR32X2TS U52 ( .A(in1[1]), .B(n70), .C(n69), .CO(n300), .S(res[1]) );
CLKMX2X2TS U53 ( .A(in2[5]), .B(n316), .S0(n315), .Y(n323) );
NAND2X2TS U54 ( .A(n158), .B(in1[22]), .Y(n251) );
NAND2X2TS U55 ( .A(n137), .B(in1[19]), .Y(n265) );
CLKMX2X2TS U56 ( .A(in2[27]), .B(n174), .S0(n315), .Y(n180) );
NOR2X4TS U57 ( .A(n137), .B(in1[19]), .Y(n264) );
NAND2BX1TS U58 ( .AN(in2[29]), .B(n189), .Y(n199) );
CLKMX2X4TS U59 ( .A(in2[21]), .B(n151), .S0(n315), .Y(n157) );
NOR2X2TS U60 ( .A(n147), .B(n185), .Y(n176) );
NOR3X4TS U61 ( .A(n147), .B(in2[28]), .C(n185), .Y(n189) );
NOR2X2TS U62 ( .A(n147), .B(n175), .Y(n173) );
NAND2X4TS U63 ( .A(n65), .B(n270), .Y(n128) );
OR2X6TS U64 ( .A(n123), .B(in1[17]), .Y(n65) );
NAND2X1TS U65 ( .A(n172), .B(n171), .Y(n175) );
NOR2X2TS U66 ( .A(n153), .B(n152), .Y(n154) );
NOR2X2TS U67 ( .A(n153), .B(in2[20]), .Y(n150) );
NOR2X4TS U68 ( .A(n147), .B(in2[24]), .Y(n168) );
NAND2X6TS U69 ( .A(n101), .B(in1[13]), .Y(n290) );
NOR2X6TS U70 ( .A(n101), .B(in1[13]), .Y(n289) );
NOR2X2TS U71 ( .A(in2[25]), .B(in2[24]), .Y(n172) );
CLKINVX2TS U72 ( .A(n147), .Y(n165) );
MX2X4TS U73 ( .A(in2[13]), .B(n98), .S0(n302), .Y(n101) );
MXI2X2TS U74 ( .A(n105), .B(n100), .S0(n302), .Y(n102) );
NOR2X2TS U75 ( .A(n14), .B(n13), .Y(n95) );
NAND2X8TS U76 ( .A(n146), .B(n145), .Y(n147) );
NOR2X2TS U77 ( .A(n22), .B(n47), .Y(n14) );
NOR2X2TS U78 ( .A(n22), .B(n7), .Y(n12) );
NAND2X2TS U79 ( .A(n89), .B(in1[11]), .Y(n341) );
OR2X4TS U80 ( .A(n83), .B(in1[9]), .Y(n339) );
OR2X2TS U81 ( .A(in2[21]), .B(in2[20]), .Y(n152) );
NAND2X1TS U82 ( .A(n105), .B(n111), .Y(n112) );
NAND2X6TS U83 ( .A(n99), .B(n107), .Y(n113) );
NOR2X1TS U84 ( .A(in2[19]), .B(in2[18]), .Y(n133) );
INVX2TS U85 ( .A(in2[14]), .Y(n105) );
BUFX4TS U86 ( .A(add_sub), .Y(n302) );
INVX2TS U87 ( .A(n306), .Y(n71) );
INVX8TS U88 ( .A(add_sub), .Y(n88) );
AND2X6TS U89 ( .A(n80), .B(n306), .Y(n81) );
INVX8TS U90 ( .A(in2[2]), .Y(n44) );
NOR2X2TS U91 ( .A(in2[11]), .B(in2[10]), .Y(n91) );
NOR2X1TS U92 ( .A(n71), .B(n79), .Y(n74) );
INVX2TS U93 ( .A(n315), .Y(n47) );
CLKXOR2X2TS U94 ( .A(n168), .B(in2[25]), .Y(n169) );
NOR2X1TS U95 ( .A(n309), .B(in2[6]), .Y(n307) );
NAND2X2TS U96 ( .A(n16), .B(n18), .Y(n15) );
MXI2X2TS U97 ( .A(n136), .B(n135), .S0(add_sub), .Y(n138) );
CLKMX2X2TS U98 ( .A(in2[28]), .B(n177), .S0(add_sub), .Y(n182) );
NAND2X1TS U99 ( .A(n138), .B(in1[20]), .Y(n260) );
INVX2TS U100 ( .A(n237), .Y(n239) );
AOI21X1TS U101 ( .A0(n65), .A1(n35), .B0(n268), .Y(n272) );
ADDHXLTS U102 ( .A(in2[0]), .B(in1[0]), .CO(n69), .S(res[0]) );
NOR2X4TS U103 ( .A(n264), .B(n259), .Y(n140) );
XNOR2X2TS U104 ( .A(n166), .B(in2[26]), .Y(n167) );
NAND2X2TS U105 ( .A(n165), .B(n172), .Y(n166) );
NOR2X4TS U106 ( .A(in2[13]), .B(in2[12]), .Y(n107) );
INVX2TS U107 ( .A(in2[15]), .Y(n111) );
XOR2X1TS U108 ( .A(n241), .B(n240), .Y(res[24]) );
NOR2X2TS U109 ( .A(n10), .B(n204), .Y(n27) );
INVX2TS U110 ( .A(n195), .Y(n196) );
INVX2TS U111 ( .A(n62), .Y(n10) );
NAND2X2TS U112 ( .A(n62), .B(n205), .Y(n198) );
OR2X4TS U113 ( .A(n191), .B(in1[30]), .Y(n62) );
OAI21X2TS U114 ( .A0(n265), .A1(n259), .B0(n260), .Y(n139) );
NOR2X2TS U115 ( .A(n129), .B(in2[18]), .Y(n130) );
NAND2X2TS U116 ( .A(n51), .B(n86), .Y(n50) );
INVX2TS U117 ( .A(n21), .Y(n13) );
INVX12TS U118 ( .A(n88), .Y(n315) );
CLKINVX6TS U119 ( .A(in2[8]), .Y(n42) );
OR2X4TS U120 ( .A(n197), .B(n56), .Y(n53) );
NOR2X4TS U121 ( .A(n210), .B(n211), .Y(n184) );
NOR2X4TS U122 ( .A(n196), .B(n27), .Y(n197) );
NOR2X2TS U123 ( .A(n198), .B(n56), .Y(n55) );
NAND2X4TS U124 ( .A(n216), .B(n64), .Y(n210) );
INVX8TS U125 ( .A(n128), .Y(n37) );
MX2X2TS U126 ( .A(in2[31]), .B(n201), .S0(add_sub), .Y(n202) );
NAND3X6TS U127 ( .A(n17), .B(n294), .C(n15), .Y(n283) );
NOR2X4TS U128 ( .A(n248), .B(n250), .Y(n243) );
NOR2X4TS U129 ( .A(n158), .B(in1[22]), .Y(n250) );
INVX2TS U130 ( .A(n269), .Y(n125) );
NAND2X4TS U131 ( .A(n336), .B(in1[8]), .Y(n350) );
XOR2X1TS U132 ( .A(n314), .B(in2[5]), .Y(n316) );
CLKMX2X2TS U133 ( .A(in2[3]), .B(n299), .S0(n315), .Y(n305) );
OR2X2TS U134 ( .A(n47), .B(in1[12]), .Y(n7) );
XOR2X1TS U135 ( .A(n254), .B(n253), .Y(res[22]) );
INVX6TS U136 ( .A(n31), .Y(n30) );
OAI21X2TS U137 ( .A0(n209), .A1(n211), .B0(n212), .Y(n183) );
AND2X2TS U138 ( .A(n224), .B(n223), .Y(n9) );
NAND2X6TS U139 ( .A(n36), .B(n127), .Y(n34) );
XOR2X1TS U140 ( .A(n293), .B(n292), .Y(res[13]) );
NAND2X6TS U141 ( .A(n37), .B(n117), .Y(n36) );
NAND2X2TS U142 ( .A(n191), .B(in1[30]), .Y(n195) );
AND2X2TS U143 ( .A(n64), .B(n220), .Y(n8) );
XOR2X1TS U144 ( .A(n296), .B(n295), .Y(res[12]) );
INVX2TS U145 ( .A(n250), .Y(n252) );
XOR2X1TS U146 ( .A(n348), .B(n347), .Y(res[10]) );
OR2X4TS U147 ( .A(n180), .B(in1[27]), .Y(n64) );
NAND3X4TS U148 ( .A(n3), .B(n18), .C(n24), .Y(n17) );
NOR2X4TS U149 ( .A(n138), .B(in1[20]), .Y(n259) );
NAND2X4TS U150 ( .A(n19), .B(n341), .Y(n16) );
XOR2X1TS U151 ( .A(n353), .B(n352), .Y(res[8]) );
NAND2X4TS U152 ( .A(n95), .B(in1[12]), .Y(n294) );
OR2X2TS U153 ( .A(n116), .B(in1[16]), .Y(n63) );
NAND2X2TS U154 ( .A(n102), .B(in1[14]), .Y(n285) );
NOR2X2TS U155 ( .A(n118), .B(in2[16]), .Y(n119) );
NAND2X4TS U156 ( .A(n339), .B(n85), .Y(n25) );
NOR2X1TS U157 ( .A(n323), .B(in1[5]), .Y(n326) );
MX2X2TS U158 ( .A(in2[7]), .B(n308), .S0(n315), .Y(n329) );
NOR4X4TS U159 ( .A(n144), .B(n152), .C(in2[23]), .D(in2[22]), .Y(n145) );
INVX8TS U160 ( .A(n208), .Y(n230) );
XOR2X1TS U161 ( .A(n221), .B(n8), .Y(res[27]) );
NAND2X4TS U162 ( .A(n162), .B(n243), .Y(n164) );
NAND2X4TS U163 ( .A(n342), .B(n20), .Y(n19) );
XOR2X4TS U164 ( .A(n51), .B(in2[10]), .Y(n45) );
XOR2X1TS U165 ( .A(n225), .B(n9), .Y(res[26]) );
AOI21X2TS U166 ( .A0(n258), .A1(n236), .B0(n235), .Y(n241) );
INVX6TS U167 ( .A(n231), .Y(n258) );
AOI21X4TS U168 ( .A0(n162), .A1(n242), .B0(n161), .Y(n163) );
OAI21X2TS U169 ( .A0(n244), .A1(n237), .B0(n238), .Y(n161) );
NOR2X4TS U170 ( .A(n94), .B(n90), .Y(n51) );
XOR2X2TS U171 ( .A(n154), .B(in2[22]), .Y(n155) );
NOR2X6TS U172 ( .A(in2[7]), .B(in2[6]), .Y(n80) );
NOR2X4TS U173 ( .A(n102), .B(in1[14]), .Y(n284) );
OAI21X4TS U174 ( .A0(n250), .A1(n255), .B0(n251), .Y(n242) );
NAND2X2TS U175 ( .A(n110), .B(in1[15]), .Y(n280) );
MX2X4TS U176 ( .A(in2[15]), .B(n109), .S0(n302), .Y(n110) );
XOR2X2TS U177 ( .A(n108), .B(in2[15]), .Y(n109) );
NAND2X2TS U178 ( .A(n106), .B(n96), .Y(n97) );
XOR2X1TS U179 ( .A(n272), .B(n271), .Y(res[18]) );
NAND2X6TS U180 ( .A(n277), .B(n63), .Y(n39) );
MXI2X4TS U181 ( .A(n42), .B(n82), .S0(n302), .Y(n336) );
MXI2X4TS U182 ( .A(n171), .B(n167), .S0(n302), .Y(n179) );
XNOR2X1TS U183 ( .A(n150), .B(in2[21]), .Y(n151) );
XNOR2X2TS U184 ( .A(n207), .B(n206), .Y(res[29]) );
XNOR2X4TS U185 ( .A(n193), .B(n192), .Y(res[30]) );
NOR2X4TS U186 ( .A(n124), .B(in1[18]), .Y(n126) );
MXI2X4TS U187 ( .A(n122), .B(n121), .S0(n302), .Y(n124) );
XNOR2X2TS U188 ( .A(n129), .B(in2[18]), .Y(n121) );
NAND2X4TS U189 ( .A(n157), .B(in1[21]), .Y(n255) );
OAI21X4TS U190 ( .A0(n230), .A1(n226), .B0(n227), .Y(n225) );
MXI2X4TS U191 ( .A(n156), .B(n155), .S0(n302), .Y(n158) );
NOR2X4TS U192 ( .A(n222), .B(n226), .Y(n216) );
MXI2X4TS U193 ( .A(n170), .B(n169), .S0(n315), .Y(n178) );
NOR2X2TS U194 ( .A(n232), .B(n237), .Y(n162) );
XNOR2X1TS U195 ( .A(n94), .B(in2[8]), .Y(n82) );
XNOR2X1TS U196 ( .A(add_sub), .B(in2[9]), .Y(n77) );
OR3X1TS U197 ( .A(n306), .B(n88), .C(in2[9]), .Y(n76) );
NOR4BX1TS U198 ( .AN(n80), .B(n79), .C(in2[9]), .D(n72), .Y(n78) );
NAND2X1TS U199 ( .A(n47), .B(in2[11]), .Y(n46) );
INVX2TS U200 ( .A(in2[11]), .Y(n49) );
XNOR2X1TS U201 ( .A(n113), .B(in2[14]), .Y(n100) );
NAND2X4TS U202 ( .A(n87), .B(in1[10]), .Y(n346) );
OR2X4TS U203 ( .A(n89), .B(in1[11]), .Y(n342) );
NOR2X2TS U204 ( .A(n182), .B(in1[28]), .Y(n211) );
INVX2TS U205 ( .A(n220), .Y(n181) );
NAND2X2TS U206 ( .A(n134), .B(n133), .Y(n144) );
NAND3XLTS U207 ( .A(n107), .B(n106), .C(n105), .Y(n108) );
MX2X4TS U208 ( .A(in2[17]), .B(n120), .S0(n315), .Y(n123) );
XNOR2X1TS U209 ( .A(n173), .B(in2[27]), .Y(n174) );
XOR2X1TS U210 ( .A(n199), .B(in2[30]), .Y(n190) );
OAI21X1TS U211 ( .A0(n332), .A1(n331), .B0(n330), .Y(n333) );
INVX2TS U212 ( .A(n346), .Y(n20) );
NOR2X1TS U213 ( .A(n21), .B(in1[12]), .Y(n11) );
NAND2X4TS U214 ( .A(n338), .B(n25), .Y(n24) );
INVX2TS U215 ( .A(n350), .Y(n85) );
INVX2TS U216 ( .A(n283), .Y(n293) );
OAI21X2TS U217 ( .A0(n284), .A1(n290), .B0(n285), .Y(n103) );
NOR2X2TS U218 ( .A(n289), .B(n284), .Y(n104) );
NOR2X4TS U219 ( .A(n110), .B(in1[15]), .Y(n279) );
NAND2X2TS U220 ( .A(n124), .B(in1[18]), .Y(n269) );
INVX2TS U221 ( .A(n126), .Y(n270) );
NAND2X4TS U222 ( .A(n123), .B(in1[17]), .Y(n273) );
NAND2X1TS U223 ( .A(n39), .B(n275), .Y(n35) );
INVX2TS U224 ( .A(n34), .Y(n28) );
NAND2X2TS U225 ( .A(n38), .B(n37), .Y(n29) );
NOR2X4TS U226 ( .A(n179), .B(in1[26]), .Y(n222) );
NAND2X2TS U227 ( .A(n178), .B(in1[25]), .Y(n227) );
NOR2X2TS U228 ( .A(n178), .B(in1[25]), .Y(n226) );
NAND2X2TS U229 ( .A(n179), .B(in1[26]), .Y(n223) );
NAND2X2TS U230 ( .A(n180), .B(in1[27]), .Y(n220) );
INVX2TS U231 ( .A(n217), .Y(n218) );
INVX2TS U232 ( .A(n194), .Y(n205) );
NOR2X2TS U233 ( .A(n188), .B(in1[29]), .Y(n194) );
NAND2X2TS U234 ( .A(n188), .B(in1[29]), .Y(n204) );
OR2X4TS U235 ( .A(in2[9]), .B(in2[8]), .Y(n90) );
NAND3X2TS U236 ( .A(n42), .B(n41), .C(n40), .Y(n72) );
CLKBUFX2TS U237 ( .A(n99), .Y(n106) );
NAND2X2TS U238 ( .A(n134), .B(n146), .Y(n129) );
NAND3X4TS U239 ( .A(n38), .B(n37), .C(n140), .Y(n31) );
NAND2X2TS U240 ( .A(n34), .B(n140), .Y(n33) );
NOR2X2TS U241 ( .A(n329), .B(in1[7]), .Y(n332) );
NAND2X2TS U242 ( .A(n47), .B(n96), .Y(n21) );
NOR2X2TS U243 ( .A(n157), .B(in1[21]), .Y(n248) );
XNOR2X1TS U244 ( .A(n309), .B(in2[6]), .Y(n310) );
INVX2TS U245 ( .A(n248), .Y(n256) );
INVX2TS U246 ( .A(n255), .Y(n249) );
NAND2X2TS U247 ( .A(n159), .B(in1[23]), .Y(n244) );
NOR2X4TS U248 ( .A(n160), .B(in1[24]), .Y(n237) );
NOR2X1TS U249 ( .A(n233), .B(n232), .Y(n236) );
INVX2TS U250 ( .A(n243), .Y(n233) );
NAND2X2TS U251 ( .A(n160), .B(in1[24]), .Y(n238) );
INVX2TS U252 ( .A(n5), .Y(n56) );
NAND2X1TS U253 ( .A(n351), .B(n350), .Y(n352) );
NAND2X1TS U254 ( .A(n339), .B(n338), .Y(n337) );
NAND2X1TS U255 ( .A(n342), .B(n341), .Y(n343) );
OAI21X1TS U256 ( .A0(n348), .A1(n345), .B0(n346), .Y(n344) );
NAND2X1TS U257 ( .A(n18), .B(n294), .Y(n296) );
AOI21X1TS U258 ( .A0(n3), .A1(n24), .B0(n16), .Y(n295) );
NAND2X1TS U259 ( .A(n291), .B(n290), .Y(n292) );
INVX2TS U260 ( .A(n289), .Y(n291) );
NAND2X1TS U261 ( .A(n286), .B(n285), .Y(n287) );
OAI21XLTS U262 ( .A0(n293), .A1(n289), .B0(n290), .Y(n288) );
INVX2TS U263 ( .A(n284), .Y(n286) );
NAND2X1TS U264 ( .A(n281), .B(n280), .Y(n282) );
INVX2TS U265 ( .A(n279), .Y(n281) );
NAND2X1TS U266 ( .A(n63), .B(n275), .Y(n276) );
XNOR2X1TS U267 ( .A(n274), .B(n35), .Y(res[17]) );
NAND2X1TS U268 ( .A(n65), .B(n273), .Y(n274) );
INVX2TS U269 ( .A(n273), .Y(n268) );
XOR2XLTS U270 ( .A(n4), .B(n267), .Y(res[19]) );
NAND2X1TS U271 ( .A(n266), .B(n265), .Y(n267) );
XNOR2X1TS U272 ( .A(n263), .B(n262), .Y(res[20]) );
NAND2X1TS U273 ( .A(n261), .B(n260), .Y(n262) );
OAI21X1TS U274 ( .A0(n4), .A1(n264), .B0(n265), .Y(n263) );
INVX2TS U275 ( .A(n259), .Y(n261) );
XNOR2X1TS U276 ( .A(n258), .B(n257), .Y(res[21]) );
NAND2X1TS U277 ( .A(n256), .B(n255), .Y(n257) );
XOR2X1TS U278 ( .A(n230), .B(n229), .Y(res[25]) );
NAND2X1TS U279 ( .A(n228), .B(n227), .Y(n229) );
INVX2TS U280 ( .A(n226), .Y(n228) );
INVX2TS U281 ( .A(n222), .Y(n224) );
INVX2TS U282 ( .A(n216), .Y(n219) );
XNOR2X1TS U283 ( .A(n215), .B(n214), .Y(res[28]) );
NAND2X1TS U284 ( .A(n213), .B(n212), .Y(n214) );
INVX2TS U285 ( .A(n211), .Y(n213) );
NAND3X2TS U286 ( .A(n54), .B(n203), .C(n53), .Y(res[32]) );
OAI21X1TS U287 ( .A0(n234), .A1(n232), .B0(n244), .Y(n235) );
NOR2X4TS U288 ( .A(n87), .B(in1[10]), .Y(n345) );
MXI2X4TS U289 ( .A(n86), .B(n45), .S0(n302), .Y(n87) );
AOI21X4TS U290 ( .A0(n283), .A1(n104), .B0(n103), .Y(n278) );
AND2X4TS U291 ( .A(n23), .B(n342), .Y(n3) );
NOR2X4TS U292 ( .A(n159), .B(in1[23]), .Y(n232) );
AND2X2TS U293 ( .A(n29), .B(n28), .Y(n4) );
OR2X2TS U294 ( .A(n202), .B(in1[31]), .Y(n5) );
INVX2TS U295 ( .A(n338), .Y(n84) );
NAND2X2TS U296 ( .A(n83), .B(in1[9]), .Y(n338) );
INVX2TS U297 ( .A(n275), .Y(n117) );
NAND2X2TS U298 ( .A(n116), .B(in1[16]), .Y(n275) );
AND2X2TS U299 ( .A(n5), .B(n203), .Y(n6) );
NOR2X4TS U300 ( .A(n12), .B(n11), .Y(n18) );
INVX2TS U301 ( .A(in2[10]), .Y(n86) );
INVX2TS U302 ( .A(n345), .Y(n23) );
XOR2X1TS U303 ( .A(n329), .B(n319), .Y(res[7]) );
MXI2X1TS U304 ( .A(n66), .B(n40), .S0(n88), .Y(n70) );
XNOR2X2TS U305 ( .A(in2[0]), .B(in2[1]), .Y(n66) );
ADDFHX2TS U306 ( .A(in1[4]), .B(n322), .CI(n317), .CO(n321), .S(res[4]) );
XOR2X4TS U307 ( .A(n26), .B(n6), .Y(res[31]) );
INVX4TS U308 ( .A(n92), .Y(n93) );
CLKXOR2X2TS U309 ( .A(n141), .B(in2[23]), .Y(n142) );
OAI21X4TS U310 ( .A0(n52), .A1(n194), .B0(n204), .Y(n193) );
XNOR2X4TS U311 ( .A(n106), .B(in2[12]), .Y(n22) );
OAI21X4TS U312 ( .A0(n52), .A1(n198), .B0(n197), .Y(n26) );
NOR2X8TS U313 ( .A(n60), .B(n57), .Y(n52) );
NOR2X8TS U314 ( .A(n32), .B(n30), .Y(n231) );
NAND2BX4TS U315 ( .AN(n139), .B(n33), .Y(n32) );
INVX8TS U316 ( .A(n39), .Y(n38) );
OAI21X4TS U317 ( .A0(n278), .A1(n279), .B0(n280), .Y(n277) );
INVX12TS U318 ( .A(in2[1]), .Y(n40) );
INVX12TS U319 ( .A(in2[0]), .Y(n41) );
NOR2X8TS U320 ( .A(n297), .B(n79), .Y(n313) );
NAND2X8TS U321 ( .A(n44), .B(n43), .Y(n79) );
INVX12TS U322 ( .A(in2[3]), .Y(n43) );
NAND2X8TS U323 ( .A(n40), .B(n41), .Y(n297) );
OAI21X4TS U324 ( .A0(n231), .A1(n164), .B0(n163), .Y(n208) );
OAI21X4TS U325 ( .A0(n48), .A1(n47), .B0(n46), .Y(n89) );
XOR2X4TS U326 ( .A(n50), .B(n49), .Y(n48) );
NOR2X4TS U327 ( .A(n231), .B(n58), .Y(n57) );
NAND2BX4TS U328 ( .AN(n52), .B(n55), .Y(n54) );
NAND2BX4TS U329 ( .AN(n183), .B(n61), .Y(n60) );
NAND2BX4TS U330 ( .AN(n163), .B(n184), .Y(n61) );
XOR2X1TS U331 ( .A(n247), .B(n246), .Y(res[23]) );
NOR2X8TS U332 ( .A(in2[5]), .B(in2[4]), .Y(n306) );
NAND2BX4TS U333 ( .AN(n144), .B(n146), .Y(n153) );
AOI21X2TS U334 ( .A0(n335), .A1(n334), .B0(n333), .Y(n353) );
NOR2X1TS U335 ( .A(n327), .B(n332), .Y(n334) );
XOR2X4TS U336 ( .A(n97), .B(in2[13]), .Y(n98) );
INVX2TS U337 ( .A(n264), .Y(n266) );
NAND2X1TS U338 ( .A(n270), .B(n269), .Y(n271) );
XNOR2X1TS U339 ( .A(n297), .B(in2[2]), .Y(n68) );
INVX2TS U340 ( .A(in2[2]), .Y(n67) );
MXI2X1TS U341 ( .A(n68), .B(n67), .S0(n88), .Y(n301) );
INVX2TS U342 ( .A(n72), .Y(n73) );
NAND4X1TS U343 ( .A(n74), .B(n80), .C(in2[9]), .D(n73), .Y(n75) );
OAI211X4TS U344 ( .A0(n78), .A1(n77), .B0(n76), .C0(n75), .Y(n83) );
NAND2X8TS U345 ( .A(n313), .B(n81), .Y(n94) );
INVX2TS U346 ( .A(in2[12]), .Y(n96) );
NOR2BX4TS U347 ( .AN(n91), .B(n90), .Y(n92) );
NOR2X8TS U348 ( .A(n94), .B(n93), .Y(n99) );
INVX2TS U349 ( .A(in2[16]), .Y(n115) );
NOR2X8TS U350 ( .A(n113), .B(n112), .Y(n146) );
XOR2X1TS U351 ( .A(n146), .B(in2[16]), .Y(n114) );
MXI2X2TS U352 ( .A(n115), .B(n114), .S0(n302), .Y(n116) );
INVX2TS U353 ( .A(n146), .Y(n118) );
XNOR2X1TS U354 ( .A(n119), .B(in2[17]), .Y(n120) );
INVX2TS U355 ( .A(in2[18]), .Y(n122) );
NOR2X2TS U356 ( .A(in2[17]), .B(in2[16]), .Y(n134) );
AOI2BB1X4TS U357 ( .A0N(n273), .A1N(n126), .B0(n125), .Y(n127) );
INVX2TS U358 ( .A(in2[19]), .Y(n132) );
XOR2X1TS U359 ( .A(n130), .B(in2[19]), .Y(n131) );
MXI2X4TS U360 ( .A(n132), .B(n131), .S0(n315), .Y(n137) );
INVX2TS U361 ( .A(in2[20]), .Y(n136) );
XNOR2X1TS U362 ( .A(n153), .B(in2[20]), .Y(n135) );
INVX2TS U363 ( .A(in2[23]), .Y(n143) );
NOR3X4TS U364 ( .A(n153), .B(in2[22]), .C(n152), .Y(n141) );
MXI2X4TS U365 ( .A(n143), .B(n142), .S0(n315), .Y(n159) );
INVX2TS U366 ( .A(in2[24]), .Y(n149) );
XNOR2X1TS U367 ( .A(n147), .B(in2[24]), .Y(n148) );
MXI2X2TS U368 ( .A(n149), .B(n148), .S0(add_sub), .Y(n160) );
INVX2TS U369 ( .A(in2[22]), .Y(n156) );
INVX2TS U370 ( .A(in2[26]), .Y(n171) );
INVX2TS U371 ( .A(in2[25]), .Y(n170) );
OR2X2TS U372 ( .A(n175), .B(in2[27]), .Y(n185) );
XNOR2X1TS U373 ( .A(n176), .B(in2[28]), .Y(n177) );
OAI21X4TS U374 ( .A0(n227), .A1(n222), .B0(n223), .Y(n217) );
AOI21X4TS U375 ( .A0(n217), .A1(n64), .B0(n181), .Y(n209) );
XNOR2X1TS U376 ( .A(n189), .B(in2[29]), .Y(n187) );
NOR2X2TS U377 ( .A(n199), .B(in2[30]), .Y(n200) );
XNOR2X1TS U378 ( .A(n200), .B(in2[31]), .Y(n201) );
OAI21X4TS U379 ( .A0(n230), .A1(n210), .B0(n209), .Y(n215) );
OAI21X4TS U380 ( .A0(n230), .A1(n219), .B0(n218), .Y(n221) );
INVX2TS U381 ( .A(n242), .Y(n234) );
XNOR2X1TS U382 ( .A(n277), .B(n276), .Y(res[16]) );
XOR2XLTS U383 ( .A(n278), .B(n282), .Y(res[15]) );
XNOR2X1TS U384 ( .A(n288), .B(n287), .Y(res[14]) );
NOR2X1TS U385 ( .A(n297), .B(in2[2]), .Y(n298) );
XNOR2X1TS U386 ( .A(n298), .B(in2[3]), .Y(n299) );
ADDFHX2TS U387 ( .A(n301), .B(in1[2]), .CI(n300), .CO(n304), .S(res[2]) );
INVX2TS U388 ( .A(in2[4]), .Y(n312) );
XNOR2X1TS U389 ( .A(n313), .B(n312), .Y(n303) );
MXI2X2TS U390 ( .A(n312), .B(n303), .S0(n302), .Y(n322) );
CMPR32X2TS U391 ( .A(in1[3]), .B(n305), .C(n304), .CO(n317), .S(res[3]) );
NAND2X1TS U392 ( .A(n313), .B(n306), .Y(n309) );
XNOR2X1TS U393 ( .A(n307), .B(in2[7]), .Y(n308) );
INVX2TS U394 ( .A(in2[6]), .Y(n311) );
MXI2X2TS U395 ( .A(n311), .B(n310), .S0(add_sub), .Y(n328) );
NAND2X1TS U396 ( .A(n313), .B(n312), .Y(n314) );
XOR2X4TS U397 ( .A(in1[7]), .B(n318), .Y(n319) );
CMPR32X2TS U398 ( .A(in1[5]), .B(n323), .C(n321), .CO(n320), .S(res[5]) );
NAND2X1TS U399 ( .A(n322), .B(in1[4]), .Y(n325) );
NAND2X1TS U400 ( .A(n323), .B(in1[5]), .Y(n324) );
OAI21X1TS U401 ( .A0(n326), .A1(n325), .B0(n324), .Y(n335) );
NOR2X1TS U402 ( .A(n328), .B(in1[6]), .Y(n327) );
NAND2X1TS U403 ( .A(n328), .B(in1[6]), .Y(n331) );
NAND2X1TS U404 ( .A(n329), .B(in1[7]), .Y(n330) );
OAI21X4TS U405 ( .A0(n353), .A1(n349), .B0(n350), .Y(n340) );
XNOR2X1TS U406 ( .A(n340), .B(n337), .Y(res[9]) );
AOI21X4TS U407 ( .A0(n340), .A1(n339), .B0(n84), .Y(n348) );
XNOR2X1TS U408 ( .A(n344), .B(n343), .Y(res[11]) );
NAND2X1TS U409 ( .A(n23), .B(n346), .Y(n347) );
INVX2TS U410 ( .A(n349), .Y(n351) );
initial $sdf_annotate("Approx_adder_ACAIIN16Q8_syn.sdf");
endmodule
|
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
(* altera_attribute = "-name MESSAGE_DISABLE 14130", altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" *) module ddr3_s4_amphy_phy_alt_mem_phy (
//Clock and reset inputs:
pll_ref_clk,
global_reset_n,
soft_reset_n,
// Used to indicate PLL loss of lock for system reset management
reset_request_n,
// Clock and reset for the controller interface
ctl_clk,
ctl_reset_n,
// Write data interface
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_wlat,
// Address and command interface:
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
// Read data interface:
ctl_doing_rd,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
//re-calibration request & configuration
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
//Calibration status interface:
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
//Parity signals for registered DIMMs
mem_ac_parity,
mem_err_out_n,
parity_error_n,
//ports to memory device(s):
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_clk,
mem_clk_n,
mem_reset_n,
// Bidirectional Memory interface signals:
mem_dq,
mem_dqs,
mem_dqs_n,
// On Chip Termination: - dynamically updated values.
oct_ctl_rs_value,
oct_ctl_rt_value,
// DLL import/export ports
dqs_offset_delay_ctrl,
dqs_delay_ctrl_import,
dqs_delay_ctrl_export,
dll_reference_clk,
// Auxiliary clocks. Some systems may need these for debugging
// purposes, or for full-rate to half-rate bridge interfaces
aux_half_rate_clk,
aux_full_rate_clk,
aux_scan_clk, // New for 9.0 for PLL/DLL re-config.
aux_scan_clk_reset_n, // New for 9.0 for PLL/DLL re-config.
// Debug interface:- ALTERA USE ONLY
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest,
// PLL reconfig interfaces - new for 9.0
pll_reconfig_enable,
pll_phasecounterselect,
pll_phaseupdown,
pll_phasestep,
pll_phase_done,
// Externalisation of levelled PHY's scan chain controls
hc_scan_enable_access,
hc_scan_enable_dq,
hc_scan_enable_dm,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_ck,
hc_scan_din,
hc_scan_dout,
hc_scan_update
);
// Default parameter values :
parameter FAMILY = "Stratix III";
parameter SPEED_GRADE = "C3";
parameter MEM_IF_MEMTYPE = "DDR3";
parameter DLL_EXPORT_IMPORT = "NONE";
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 9000;
parameter DQS_PHASE_SETTING = 2;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_DQSN_EN = 1;
parameter MEM_IF_ADDR_CMD_PHASE = "PLL";
parameter MEM_IF_RANKS_PER_SLOT = 1; // how ranks are arranged into slot - needed for odt setting in the sequencer
parameter MEM_IF_ADDR_WIDTH = 13;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_OCT_EN = 0;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_MR_0 = 0;
parameter MEM_IF_MR_1 = 0;
parameter MEM_IF_MR_2 = 0;
parameter MEM_IF_MR_3 = 0;
parameter MEM_IF_PRESET_RLAT = 0;
parameter PLL_STEPS_PER_CYCLE = 24;
parameter SCAN_CLK_DIVIDE_BY = 4;
parameter REDUCE_SIM_TIME = 1;
parameter FORCE_HC = 0;
parameter CAPABILITIES = 0;
parameter WRITE_DESKEW_T10 = 0;
parameter WRITE_DESKEW_T9NI = 0;
parameter WRITE_DESKEW_T9I = 0;
parameter WRITE_DESKEW_RANGE = 0;
parameter TINIT_TCK = 40000;
parameter TINIT_RST = 100000;
parameter DBG_A_WIDTH = 13;
parameter MEM_IF_CS_PER_RANK = 1; // duplicates CS, CKE, ODT, sequencer still controls 1 rank, but it is subdivided from controller perspective.
parameter MEM_IF_RDV_PER_CHIP = 0; // multiple chips, and which gives valid data...
parameter GENERATE_ADDITIONAL_DBG_RTL = 0; // Non-Levelling sequencer specific
parameter SEQ_STRING_ID = "seq_name";
parameter LEVELLING = 1;
parameter READ_DESKEW_MODE = "NONE";
parameter WRITE_DESKEW_MODE = "NONE";
parameter PLL_RECONFIG_PORTS_EN = 0;
parameter RANK_HAS_ADDR_SWAP = 0;
parameter INVERT_POSTAMBLE_CLK = "false";
// In full-rate modes, some addr/cmd phases require an inverted phy_clk here to make the transfer
// successfully. If core to addr/cmd clock timing is failing, then it may be that an incorrect
// default for this parameter was selected by the GUI.
// Tests have shown that for addr/cmd phases<270 degrees it should be inverted, otherwise it
// should not but this does vary dependant on frequency and loading, so for middling phases
// from 240 to 270 this parameter may need inverting.
parameter INVERT_ADDR_CMD_TXFR_CLK = "false";
// Params for Registered DIMMs
parameter CHIP_OR_DIMM = "Unbuffered DIMM";
parameter RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
// Localparams :
localparam ENABLE_DDR3_SEQUENCER = "TRUE";
localparam MEM_IF_DQS_CAPTURE_EN = 1;
localparam ADV_LAT_WIDTH = 5;
localparam CAPTURE_MIMIC_PATH = 0;
localparam DDR_MIMIC_PATH_EN = 1;
localparam MIMIC_DEBUG_EN = 0;
localparam NUM_MIMIC_SAMPLE_CYCLES = 6;
localparam NUM_DEBUG_SAMPLES_TO_STORE = 4096;
localparam ASYNCHRONOUS_AVALON_CLOCK = 1;
localparam POSTAMBLE_AWIDTH = 6;
localparam MEM_TCL = "1.5";
localparam POSTAMBLE_INITIAL_LAT = 13;
localparam RDV_INITIAL_LAT = 23;
localparam RDP_INITIAL_LAT = ((DWIDTH_RATIO == 2) && (MEM_IF_MEMTYPE == "DDR2")) ? 4:6;
localparam RESYNC_PIPELINE_DEPTH = 0;
localparam CLOCK_INDEX_WIDTH = 4;
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam USE_DLL_OFFSET = "false";
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH / MEM_IF_CS_PER_RANK;
localparam OCT_RTT_LAUNCH_TIME_DELAY = 0;
localparam OCT_RTT_EXTENSION = 0;
localparam PER_GROUP_HR_RSC = 0;
// I/O Signal definitions :
// Clock and reset I/O :
input wire pll_ref_clk;
input wire global_reset_n;
input wire soft_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// The controller must use this phy_clk to interface to the PHY. It is
// optional as to whether the remainder of the system uses it :
output wire ctl_clk;
output wire ctl_reset_n;
// new AFI I/Os - write data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_wdata_valid;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_wdata;
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO -1 : 0] ctl_dm;
output wire [4 : 0] ctl_wlat;
// new AFI I/Os - addr/cmd i/f:
input wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_addr;
input wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_ba;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_cas_n;
input wire [MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1:0] ctl_cke;
input wire [MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1:0] ctl_cs_n;
input wire [MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1:0] ctl_odt;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_ras_n;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_we_n;
input wire [DWIDTH_RATIO/2 - 1 : 0] ctl_rst_n;
// new AFI I/Os - read data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
output wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_rdata;
output wire [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output wire [4 : 0] ctl_rlat;
// new AFI I/Os - update interface:
input wire ctl_cal_req;
// new AFI I/Os - status interface:
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
// Parity signals for RDIMMs
output wire mem_ac_parity;
input wire mem_err_out_n;
output wire parity_error_n;
// PHY configuration:
input wire [MEM_IF_DQS_WIDTH * MEM_IF_NUM_RANKS - 1 : 0] ctl_cal_byte_lane_sel_n;
//Inputs from DIMM:
//Outputs to DIMM :
output wire [MEM_IF_ADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_NUM_RANKS - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
wire [MEM_IF_DWIDTH - 1 : 0] mem_d;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
output wire [MEM_IF_NUM_RANKS - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_reset_n;
//The mem_clks are outputs, but one is sometimes used for the mimic_path, so
//is looped back in. Therefore defining as an inout ensures no errors in Quartus :
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
//Bidirectional:
inout tri [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs_n;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] oct_ctl_rs_value;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] oct_ctl_rt_value;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_offset_delay_ctrl; // New for 9.0, tie to zero if not required.
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_import;
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_export;
output wire dll_reference_clk;
// Auxillary clocks. These do not have to be connected if the system
// doesn't require them :
output wire aux_half_rate_clk;
output wire aux_full_rate_clk;
// The scan clock is provided as a convenient clock for the user logic which
// drives either the DLL or PLL reprogramming interfaces
output wire aux_scan_clk; // New for 9.0
output wire aux_scan_clk_reset_n; // New for 9.0
// AVALON MM Slave -- debug IF
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH -1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [31 : 0] dbg_wr_data;
output wire [31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
// PLL reconfig interface. Made available primarily for HardCopy customers :
input wire pll_reconfig_enable; // New for 9.0 - tie low if not required.
input wire [3:0] pll_phasecounterselect; // New for 9.0 - tie low if not required.
input wire pll_phaseupdown; // New for 9.0 - tie low if not required.
input wire pll_phasestep; // New for 9.0 - tie low if not required.
output wire pll_phase_done; // New for 9.0
// Size the interface based on DWDTH, as this will always be the largest :
input wire hc_scan_enable_access; // New for 9.1 - tie low if not required.
input wire [MEM_IF_DWIDTH - 1 : 0] hc_scan_enable_dq; // New for 9.1 - tie low if not required.
input wire [MEM_IF_DM_WIDTH - 1 : 0] hc_scan_enable_dm; // New for 9.1 - tie low if not required.
input wire [MEM_IF_DQS_WIDTH - 1 : 0] hc_scan_enable_dqs; // New for 9.1 - tie low if not required.
input wire [MEM_IF_DQS_WIDTH - 1 : 0] hc_scan_enable_dqs_config; // New for 9.1 - tie low if not required.
input wire [MEM_IF_DQS_WIDTH - 1 : 0] hc_scan_din; // New for 9.1 - tie low if not required.
input wire [MEM_IF_DQS_WIDTH - 1 : 0] hc_scan_update; // New for 9.1 - tie low if not required.
output wire [MEM_IF_DWIDTH - 1 : 0] hc_scan_dout; // New for 9.1
input wire hc_scan_ck; // New for 9.1 - tie low if not required.
// Internal signal declarations :
wire aux_clk;
// Clocks :
// full-rate memory clock
wire mem_clk_2x;
// write_clk_2x is a full-rate write clock. It is -90 degress aligned to the
// system clock :
wire write_clk_2x;
wire phy_clk_1x_src;
wire phy_clk_1x;
wire ac_clk_1x;
wire cs_n_clk_1x;
wire postamble_clk_2x;
wire resync_clk_2x;
wire measure_clk_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] resync_clk_1x;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_internal;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl; // Output from clk_reset block
// resets, async assert, de-assert is sync'd to each clock domain
wire reset_mem_clk_2x_n;
wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_rdp_phy_clk_1x_n;
wire reset_phy_clk_1x_n;
wire reset_ac_clk_1x_n;
wire reset_cs_n_clk_1x_n;
wire reset_mimic_2x_n;
wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_resync_clk_1x_n;
wire reset_seq_n;
wire reset_measure_clk_1x_n;
wire reset_resync_clk_2x_n;
// Misc signals :
wire phs_shft_busy;
wire pll_seq_reconfig_busy;
// Postamble signals :
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO /2 - 1 : 0] poa_postamble_en_preset;
// Sequencer signals
wire seq_mmc_start;
wire seq_pll_inc_dec_n;
wire seq_pll_start_reconfig;
wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_dec_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_inc_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_poa_lat_dec_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_poa_lat_inc_1x;
wire seq_poa_protection_override_1x;
wire seq_rdp_reset_req_n;
wire seq_ac_sel;
wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_addr;
wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_ba;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_cas_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_ras_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_we_n;
wire [MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cke;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cs_n;
wire [MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : 0] seq_ac_odt;
wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0 ] seq_wdp_dm;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_dqs_burst;
wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0 ] seq_wdp_wdata;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_wdata_valid;
wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
wire seq_wdp_ovride;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] oct_rsst_sel;
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid;
wire seq_rdata_valid_lat_inc;
wire seq_rdata_valid_lat_dec;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_rdata_valid;
// Scanchain signals
reg [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
reg [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
reg [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
reg [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
reg [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
reg [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
reg [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
reg [MEM_IF_DQS_WIDTH - 1 : 0] scan_ck;
wire [MEM_IF_DWIDTH - 1 : 0] scan_dout;
// set pll clock index of resync and mimic clocks
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
// The clk_reset block provides the sc_clk to the sequencer and DP blocks.
wire sc_clk;
wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// Mimic signals :
wire mmc_seq_done;
wire mmc_seq_value;
wire mimic_data;
wire mux_seq_controller_ready;
wire mux_seq_wdata_req;
// Read datapath signals :
// Connections from the IOE to the read datapath :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
// Write datapath signals :
// wires from the wdp to the dpio :
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata0_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_l_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs3_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs2_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs1_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs0_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_l_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm3_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm2_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm1_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm0_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_h_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_l_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_dqs_add_2t_delay;
wire ctl_add_1t_ac_lat_internal;
wire ctl_add_1t_odt_lat_internal;
wire ctl_add_intermediate_regs_internal;
wire ctl_negedge_en_internal;
// These ports are tied off for DDR,DDR2,DDR3. Registers are used to reduce Quartus warnings :
(* preserve *) reg [DWIDTH_RATIO - 1 : 0] ctl_mem_dqs;
wire [MEM_IF_NUM_RANKS - 1 : 0] int_rank_has_addr_swap;
//SIII declarations :
//Outputs from the dp_io block to the read_dp block :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata0_1x;
reg [DWIDTH_RATIO/2 - 1 : 0] rdv_pipe_ip;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay; // oct_lat
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend; //oct_extend_duration
wire seq_oct_val;
wire seq_mem_clk_disable;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_ac_rst_n;
wire dqs_delay_update_en;
// Offset control output for internal offset control block - usupported :
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offsetctrl_out;
// offsetctrl_out for the DQS delay chains. This will be driven by dqs_offset_delay_ctrl when
// in external DLL mode (DLL_IMPORT_EXPORT == "IMPORT" :
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offsetctrl_internal;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] seq_scan_enable_ck;
wire [MEM_IF_DWIDTH - 1 : 0] seq_scan_enable_dq;
wire [MEM_IF_DM_WIDTH - 1 : 0] seq_scan_enable_dm;
wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_scan_enable_dqs;
wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_scan_enable_dqs_config;
wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_scan_update;
wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_scan_din;
//Generate variable :
genvar dqs_grp_num;
// continual assignments :
// The top level I/O should not have the "Nx" clock domain suffices, so this is
// assigned here. Also note that to avoid delta delay issues both the external and
// internal phy_clks are assigned to a common 'src' clock :
assign ctl_clk = phy_clk_1x_src;
assign phy_clk_1x = phy_clk_1x_src;
assign ctl_reset_n = reset_phy_clk_1x_n;
// Generate auxillary clocks:
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin
assign aux_half_rate_clk = phy_clk_1x;
assign aux_full_rate_clk = aux_clk;
end
// Full-rate mode - NB unsupported for DDR3 :
else
begin
assign aux_half_rate_clk = aux_clk;
assign aux_full_rate_clk = phy_clk_1x;
end
endgenerate
assign dqs_delay_ctrl_export = dqs_delay_ctrl;
assign dll_reference_clk = mem_clk_2x;
// If using an external DLL, DLL_EXPORT_IMPORT shall be set to "IMPORT" and the
// delay code for the DQS delay chains and the phase alignment blocks (if used)
// shall come from the dqs_delay_ctrl_import input instead. This should be connected
// to the "delayctrlout" output of the external DLL
generate
if (DLL_EXPORT_IMPORT == "IMPORT")
assign dqs_delay_ctrl_internal = dqs_delay_ctrl_import;
else
assign dqs_delay_ctrl_internal = dqs_delay_ctrl;
endgenerate
// If DQS offsetting is required, external DLL mode should be used
// (as this is the only supported mode for offsetting), so DLL_EXPORT_IMPORT shall be
// set to "IMPORT" and the offset_delay_ctrl signal for the DQS delay chain shall come
// from the "dqs_offset_delay_ctrl" input. This should be connected in turn to the
// "offset_ctrl_out" output of the dll_offset_ctrl block.
generate
if (DLL_EXPORT_IMPORT == "IMPORT")
assign dlloffset_offsetctrl_internal = dqs_offset_delay_ctrl;
else
assign dlloffset_offsetctrl_internal = dlloffset_offsetctrl_out;
endgenerate
//Scan control muxing :
always @*
begin
if (hc_scan_enable_access == 1'b1)
begin
scan_enable_dq = hc_scan_enable_dq;
scan_enable_dm = hc_scan_enable_dm;
scan_enable_dqs = hc_scan_enable_dqs;
scan_enable_dqs_config = hc_scan_enable_dqs_config;
scan_enable_ck = 1'b0;
scan_update = hc_scan_update;
scan_din = hc_scan_din;
scan_ck = {MEM_IF_DQS_WIDTH{hc_scan_ck}} ;
end
else
begin
scan_enable_dq = seq_scan_enable_dq;
scan_enable_dm = seq_scan_enable_dm;
scan_enable_dqs = seq_scan_enable_dqs;
scan_enable_dqs_config = seq_scan_enable_dqs_config;
scan_enable_ck = seq_scan_enable_ck; // Actually sequencer does not use, but included for completeness.
scan_update = seq_scan_update;
scan_din = seq_scan_din;
scan_ck = sc_clk_dp;
end
end
assign hc_scan_dout = hc_scan_enable_access ? scan_dout : 'h0 ;
// Instance I/O modules :
//
ddr3_s4_amphy_phy_alt_mem_phy_dp_io #(
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_CLK_PS_STR (MEM_IF_CLK_PS_STR),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DM_PINS_EN (MEM_IF_DM_PINS_EN),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.LEVELLING (LEVELLING),
.READ_DESKEW_MODE (READ_DESKEW_MODE),
.WRITE_DESKEW_MODE (WRITE_DESKEW_MODE),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.MEM_IF_OCT_EN (MEM_IF_OCT_EN),
.MEM_IF_POSTAMBLE_EN_WIDTH (8),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DQS_OUT_MODE (DQS_OUT_MODE),
.DQS_PHASE (DQS_PHASE),
.DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.MEM_TCL (MEM_TCL),
.ENABLE_DDR3_SEQUENCER (ENABLE_DDR3_SEQUENCER),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH),
.DQS_DELAY_USES_OFFSET (USE_DLL_OFFSET),
.INVERT_POSTAMBLE_CLK (INVERT_POSTAMBLE_CLK)
) dpio (
.reset_write_clk_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.resync_clk_2x (resync_clk_2x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.resync_clk_1x (resync_clk_1x),
.sc_clk (scan_ck),
.scan_enable_dqs_config (scan_enable_dqs_config),
.scan_enable_dqs (scan_enable_dqs),
.scan_enable_dq (scan_enable_dq),
.scan_enable_dm (scan_enable_dm),
.scan_update (scan_update),
.scan_din (scan_din),
.scan_dout (scan_dout),
.dedicated_dll_delay_ctrl (dqs_delay_ctrl_internal),
.seq_dqs_delay_ctrl (dqs_delay_ctrl_internal),
.dll_offset_delay_ctrl (dlloffset_offsetctrl_internal),
.dqs_update_en (dqs_delay_update_en),
.mem_d (mem_d),
.mem_dm (mem_dm),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqsn (mem_dqs_n),
.dio_rdata3_1x (dio_rdata3_1x),
.dio_rdata2_1x (dio_rdata2_1x),
.dio_rdata1_1x (dio_rdata1_1x),
.dio_rdata0_1x (dio_rdata0_1x),
.poa_postamble_en_preset (poa_postamble_en_preset),
.wdp_wdata3_1x (wdp_wdata3_1x),
.wdp_wdata2_1x (wdp_wdata2_1x),
.wdp_wdata1_1x (wdp_wdata1_1x),
.wdp_wdata0_1x (wdp_wdata0_1x),
.wdp_wdata_oe_h_1x (wdp_wdata_oe_h_1x),
.wdp_wdata_oe_l_1x (wdp_wdata_oe_l_1x),
.wdp_dqs3_1x (wdp_dqs3_1x),
.wdp_dqs2_1x (wdp_dqs2_1x),
.wdp_dqs1_1x (wdp_dqs1_1x),
.wdp_dqs0_1x (wdp_dqs0_1x),
.wdp_dqs_oe_h_1x (wdp_dqs_oe_h_1x),
.wdp_dqs_oe_l_1x (wdp_dqs_oe_l_1x),
.wdp_dm3_1x (wdp_dm3_1x),
.wdp_dm2_1x (wdp_dm2_1x),
.wdp_dm1_1x (wdp_dm1_1x),
.wdp_dm0_1x (wdp_dm0_1x),
.wdp_oct_h_1x (wdp_oct_h_1x),
.wdp_oct_l_1x (wdp_oct_l_1x),
.seriesterminationcontrol (oct_ctl_rs_value),
.parallelterminationcontrol (oct_ctl_rt_value)
);
// Instance the read datapath :
// This needs generating on a per DQS-group basis :
// For example, a 64bit memory with 4 DQ bits per DQS will instance this block 16
// times, each instance catering for 4 DQ bits.
generate
if (DWIDTH_RATIO == 4)
begin: hr_rdp
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS ; dqs_grp_num=dqs_grp_num+1)
begin : rdp_per_group
//
ddr3_s4_amphy_phy_alt_mem_phy_read_dp_group #(
.ADDR_COUNT_WIDTH (4),
.BIDIR_DPINS (1),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.FAMILY (FAMILY),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.RDP_INITIAL_LAT (RDP_INITIAL_LAT),
.RDP_RESYNC_LAT_CTL_EN (0),
.RESYNC_PIPELINE_DEPTH (RESYNC_PIPELINE_DEPTH)
) rdp (
.phy_clk_1x (phy_clk_1x),
.resync_clk_1x (resync_clk_1x[dqs_grp_num]),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n[dqs_grp_num]),
.reset_resync_clk_1x_n (reset_resync_clk_1x_n[dqs_grp_num]),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x[dqs_grp_num]),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x[dqs_grp_num]),
.dio_rdata3_1x (dio_rdata3_1x[(dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1:dqs_grp_num*MEM_IF_DQ_PER_DQS]),
.dio_rdata2_1x (dio_rdata2_1x[(dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1:dqs_grp_num*MEM_IF_DQ_PER_DQS]),
.dio_rdata1_1x (dio_rdata1_1x[(dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1:dqs_grp_num*MEM_IF_DQ_PER_DQS]),
.dio_rdata0_1x (dio_rdata0_1x[(dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1:dqs_grp_num*MEM_IF_DQ_PER_DQS]),
.ctl_mem_rdata ( { ctl_rdata[MEM_IF_DWIDTH * 3 + ((dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1) : MEM_IF_DWIDTH * 3 + (dqs_grp_num*MEM_IF_DQ_PER_DQS) ],
ctl_rdata[MEM_IF_DWIDTH * 2 + ((dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1) : MEM_IF_DWIDTH * 2 + (dqs_grp_num*MEM_IF_DQ_PER_DQS) ],
ctl_rdata[MEM_IF_DWIDTH * 1 + ((dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1) : MEM_IF_DWIDTH * 1 + (dqs_grp_num*MEM_IF_DQ_PER_DQS) ],
ctl_rdata[MEM_IF_DWIDTH * 0 + ((dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1) : MEM_IF_DWIDTH * 0 + (dqs_grp_num*MEM_IF_DQ_PER_DQS) ]
})
);
end
end
else
begin : fr_rdp
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS ; dqs_grp_num=dqs_grp_num+1)
begin : rdp_per_group
//
ddr3_s4_amphy_phy_alt_mem_phy_read_dp_group #(
.ADDR_COUNT_WIDTH (4),
.BIDIR_DPINS (1),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.FAMILY (FAMILY),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.RDP_INITIAL_LAT (RDP_INITIAL_LAT),
.RDP_RESYNC_LAT_CTL_EN (0),
.RESYNC_PIPELINE_DEPTH (RESYNC_PIPELINE_DEPTH)
) rdp (
.phy_clk_1x (phy_clk_1x),
.resync_clk_1x (resync_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n[dqs_grp_num]),
.reset_resync_clk_1x_n (reset_resync_clk_2x_n),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x[dqs_grp_num]),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x[dqs_grp_num]),
.dio_rdata3_1x (),
.dio_rdata2_1x (),
.dio_rdata1_1x (dio_rdata1_1x[(dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1:dqs_grp_num*MEM_IF_DQ_PER_DQS]),
.dio_rdata0_1x (dio_rdata0_1x[(dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1:dqs_grp_num*MEM_IF_DQ_PER_DQS]),
.ctl_mem_rdata ( { ctl_rdata[MEM_IF_DWIDTH * 1 + ((dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1) : MEM_IF_DWIDTH * 1 + (dqs_grp_num*MEM_IF_DQ_PER_DQS) ],
ctl_rdata[MEM_IF_DWIDTH * 0 + ((dqs_grp_num+1)*MEM_IF_DQ_PER_DQS-1) : MEM_IF_DWIDTH * 0 + (dqs_grp_num*MEM_IF_DQ_PER_DQS) ]
})
);
end
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : hr_oct_gen
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS ; dqs_grp_num=dqs_grp_num+1)
begin : park_at_rs_oct_group
//
ddr3_s4_amphy_phy_alt_mem_phy_oct_delay #(
.FAMILY (FAMILY),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) oct (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.oct_lat (seq_oct_oct_delay),
.oct_extend_duration (seq_oct_oct_extend),
.ctl_doing_rd ( { ctl_doing_rd[(dqs_grp_num + (MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS))], ctl_doing_rd[dqs_grp_num]}),
.oct_out ( { oct_rsst_sel[(dqs_grp_num + (MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS))], oct_rsst_sel[dqs_grp_num]})
);
end
end
else
begin : fr_oct_gen
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS ; dqs_grp_num=dqs_grp_num+1)
begin : park_at_rs_oct_group
//
ddr3_s4_amphy_phy_alt_mem_phy_oct_delay #(
.FAMILY (FAMILY),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) oct (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.oct_lat (seq_oct_oct_delay),
.oct_extend_duration (seq_oct_oct_extend),
.ctl_doing_rd (ctl_doing_rd[dqs_grp_num]),
.oct_out (oct_rsst_sel[dqs_grp_num])
);
end
end
endgenerate
// Instance the write datapath :
always @(posedge phy_clk_1x)
begin
if (DWIDTH_RATIO == 4)
ctl_mem_dqs <= 4'b1100;
else
ctl_mem_dqs <= 2'b10;
end
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_wdp_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_write_dp #(
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("HALF"),
.LOCAL_IF_DWIDTH (MEM_IF_DWIDTH * DWIDTH_RATIO),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_BE_WIDTH (MEM_IF_DM_WIDTH * DWIDTH_RATIO),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_OCT_EN (MEM_IF_OCT_EN),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_DM_PINS_EN (MEM_IF_DM_PINS_EN)
) wdp (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.ctl_mem_dqs (ctl_mem_dqs),
.ctl_mem_oct (oct_rsst_sel),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_dqs (seq_wdp_dqs),
.seq_ctl_sel (seq_wdp_ovride),
.seq_oct_val (seq_oct_val),
.seq_dq_dm_add_2t_delay (1'b0),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.wdp_wdata3_1x (wdp_wdata3_1x),
.wdp_wdata2_1x (wdp_wdata2_1x),
.wdp_wdata1_1x (wdp_wdata1_1x),
.wdp_wdata0_1x (wdp_wdata0_1x),
.wdp_wdata_oe_h_1x (wdp_wdata_oe_h_1x),
.wdp_wdata_oe_l_1x (wdp_wdata_oe_l_1x),
.wdp_dqs3_1x (wdp_dqs3_1x),
.wdp_dqs2_1x (wdp_dqs2_1x),
.wdp_dqs1_1x (wdp_dqs1_1x),
.wdp_dqs0_1x (wdp_dqs0_1x),
.wdp_dqs_oe_h_1x (wdp_dqs_oe_h_1x),
.wdp_dqs_oe_l_1x (wdp_dqs_oe_l_1x),
.wdp_dm3_1x (wdp_dm3_1x),
.wdp_dm2_1x (wdp_dm2_1x),
.wdp_dm1_1x (wdp_dm1_1x),
.wdp_dm0_1x (wdp_dm0_1x),
.wdp_oct_h_1x (wdp_oct_h_1x),
.wdp_oct_l_1x (wdp_oct_l_1x)
);
end
else
begin: full_rate_wdp_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_write_dp_fr #(
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("FULL"),
.LOCAL_IF_DWIDTH (MEM_IF_DWIDTH * DWIDTH_RATIO),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_BE_WIDTH (MEM_IF_DM_WIDTH * DWIDTH_RATIO),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_OCT_EN (MEM_IF_OCT_EN),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_DM_PINS_EN (MEM_IF_DM_PINS_EN)
) wdp (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.ctl_mem_dqs (ctl_mem_dqs),
.ctl_mem_oct (oct_rsst_sel),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_dqs (seq_wdp_dqs),
.seq_ctl_sel (seq_wdp_ovride),
.seq_oct_val (seq_oct_val),
.seq_dq_dm_add_2t_delay (1'b0),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.wdp_wdata1_1x (wdp_wdata1_1x),
.wdp_wdata0_1x (wdp_wdata0_1x),
.wdp_wdata_oe_h_1x (wdp_wdata_oe_h_1x),
.wdp_wdata_oe_l_1x (wdp_wdata_oe_l_1x),
.wdp_dqs1_1x (wdp_dqs1_1x),
.wdp_dqs0_1x (wdp_dqs0_1x),
.wdp_dqs_oe_h_1x (wdp_dqs_oe_h_1x),
.wdp_dqs_oe_l_1x (wdp_dqs_oe_l_1x),
.wdp_dm1_1x (wdp_dm1_1x),
.wdp_dm0_1x (wdp_dm0_1x),
.wdp_oct_h_1x (wdp_oct_h_1x),
.wdp_oct_l_1x (wdp_oct_l_1x)
);
end
endgenerate
// Instance the address and command :
generate
if (DWIDTH_RATIO == 4)
begin: half_rate_adc_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd #(
.FAMILY (FAMILY),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK),
.LEVELLING (LEVELLING),
.CHIP_OR_DIMM (CHIP_OR_DIMM)
) adc (
.ac_clk_1x (ac_clk_1x),
.cs_n_clk_1x (cs_n_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_cs_n_clk_1x_n), // cs_n reset is used instead. Basically the same.
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
.ctl_negedge_en (ctl_negedge_en_internal),
.ctl_mem_addr_h (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_addr_l (ctl_addr[MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_ADDR_WIDTH]),
.ctl_mem_ba_h (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.ctl_mem_cas_n_h (ctl_cas_n[0]),
.ctl_mem_cas_n_l (ctl_cas_n[1]),
.ctl_mem_cke_h (ctl_cke[MEM_IF_NUM_RANKS - 1 : 0]),
.ctl_mem_cke_l (ctl_cke[MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : MEM_IF_NUM_RANKS]),
.ctl_mem_cs_n_h (ctl_cs_n[MEM_IF_NUM_RANKS - 1 : 0]),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : MEM_IF_NUM_RANKS]),
.ctl_mem_odt_h (ctl_odt[MEM_IF_NUM_RANKS - 1 : 0]),
.ctl_mem_odt_l (ctl_odt[MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : MEM_IF_NUM_RANKS]),
.ctl_mem_ras_n_h (ctl_ras_n[0]),
.ctl_mem_ras_n_l (ctl_ras_n[1]),
.ctl_mem_we_n_h (ctl_we_n[0]),
.ctl_mem_we_n_l (ctl_we_n[1]),
.ctl_mem_wps_n ({MEM_IF_NUM_RANKS{1'b0}}),
.ctl_mem_rps_n ({MEM_IF_NUM_RANKS{1'b0}}),
.ctl_mem_rst_n_h (ctl_rst_n[0]),
.ctl_mem_rst_n_l (ctl_rst_n[1]),
.seq_addr_h (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_ADDR_WIDTH]),
.seq_ba_h (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.seq_cas_n_h (seq_ac_cas_n[0]),
.seq_cas_n_l (seq_ac_cas_n[1]),
.seq_cke_h (seq_ac_cke[MEM_IF_NUM_RANKS - 1 : 0]),
.seq_cke_l (seq_ac_cke[MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : MEM_IF_NUM_RANKS]),
.seq_cs_n_h (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_odt_h (seq_ac_odt[MEM_IF_NUM_RANKS - 1 : 0]),
.seq_odt_l (seq_ac_odt[MEM_IF_NUM_RANKS * DWIDTH_RATIO/2 - 1 : MEM_IF_NUM_RANKS]),
.seq_ras_n_h (seq_ac_ras_n[0]),
.seq_ras_n_l (seq_ac_ras_n[1]),
.seq_we_n_h (seq_ac_we_n[0]),
.seq_we_n_l (seq_ac_we_n[1]),
.seq_mem_rst_n_h (seq_ac_rst_n[0]),
.seq_mem_rst_n_l (seq_ac_rst_n[1]),
.seq_ac_sel (seq_ac_sel),
.seq_wps_n ({MEM_IF_NUM_RANKS{1'b0}}),
.seq_rps_n ({MEM_IF_NUM_RANKS{1'b0}}),
.mem_ac_parity (mem_ac_parity),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.mem_rst_n (mem_reset_n),
.mem_rps_n (),
.mem_wps_n ()
);
end
else
begin : full_rate_adc_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd #(
.FAMILY (FAMILY),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK),
.LEVELLING (LEVELLING),
.CHIP_OR_DIMM (CHIP_OR_DIMM)
) adc (
.ac_clk_1x (ac_clk_1x),
.cs_n_clk_1x (cs_n_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_cs_n_clk_1x_n), // cs_n reset is used instead. Basically the same.
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
.ctl_negedge_en (ctl_negedge_en_internal),
.ctl_mem_addr_h (),
.ctl_mem_addr_l (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_ba_h (),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_cas_n_h (),
.ctl_mem_cas_n_l (ctl_cas_n[0]),
.ctl_mem_cke_h (),
.ctl_mem_cke_l (ctl_cke[MEM_IF_NUM_RANKS - 1 : 0]),
.ctl_mem_cs_n_h (),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_NUM_RANKS - 1 : 0]),
.ctl_mem_odt_h (),
.ctl_mem_odt_l (ctl_odt[MEM_IF_NUM_RANKS - 1 : 0]),
.ctl_mem_ras_n_h (),
.ctl_mem_ras_n_l (ctl_ras_n[0]),
.ctl_mem_we_n_h (),
.ctl_mem_we_n_l (ctl_we_n[0]),
.ctl_mem_wps_n ({MEM_IF_CS_WIDTH{1'b0}}),
.ctl_mem_rps_n ({MEM_IF_CS_WIDTH{1'b0}}),
.ctl_mem_rst_n_h (),
.ctl_mem_rst_n_l (ctl_rst_n[0]),
.seq_addr_h (),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_ba_h (),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_cas_n_h (),
.seq_cas_n_l (seq_ac_cas_n[0]),
.seq_cke_h (),
.seq_cke_l (seq_ac_cke[MEM_IF_NUM_RANKS - 1 : 0]),
.seq_cs_n_h (),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_h (),
.seq_odt_l (seq_ac_odt[MEM_IF_NUM_RANKS - 1 : 0]),
.seq_ras_n_h (),
.seq_ras_n_l (seq_ac_ras_n[0]),
.seq_we_n_h (),
.seq_we_n_l (seq_ac_we_n[0]),
.seq_mem_rst_n_h (),
.seq_mem_rst_n_l (seq_ac_rst_n[0]),
.seq_ac_sel (seq_ac_sel),
.seq_wps_n ({MEM_IF_NUM_RANKS{1'b0}}),
.seq_rps_n ({MEM_IF_NUM_RANKS{1'b0}}),
.mem_ac_parity (mem_ac_parity),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.mem_rst_n (mem_reset_n),
.mem_rps_n (),
.mem_wps_n ()
);
end
endgenerate
assign int_rank_has_addr_swap = RANK_HAS_ADDR_SWAP[MEM_IF_CS_WIDTH - 1 : 0];
assign pll_resync_clk_index = 5;
assign pll_measure_clk_index = 7;
// instantiate the DDR3 sequencer:
//
ddr3_s4_amphy_phy_alt_mem_phy_seq_wrapper
//
seq_wrapper (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.ctl_cal_success (ctl_cal_success),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_warning (ctl_cal_warning),
.ctl_cal_req (ctl_cal_req),
.int_RANK_HAS_ADDR_SWAP (int_rank_has_addr_swap),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.phs_shft_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.sc_clk_dp (sc_clk_dp),
.scan_enable_dqs_config (seq_scan_enable_dqs_config),
.scan_update (seq_scan_update),
.scan_din (seq_scan_din),
.scan_enable_ck (seq_scan_enable_ck), //NB. mem_clk scan config
.scan_enable_dqs (seq_scan_enable_dqs),
.scan_enable_dq (seq_scan_enable_dq),
.scan_enable_dm (seq_scan_enable_dm),
.hr_rsc_clk (resync_clk_1x[0]),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.ctl_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs_internal (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.ctl_rdata (ctl_rdata),
.int_rdata_valid_1t (seq_rdata_valid),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_val (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_clk (dbg_clk),
.dbg_reset_n (dbg_reset_n),
.dbg_addr (dbg_addr),
.dbg_wr (dbg_wr),
.dbg_rd (dbg_rd),
.dbg_cs (dbg_cs),
.dbg_wr_data (dbg_wr_data),
.dbg_rd_data (dbg_rd_data),
.dbg_waitrequest (dbg_waitrequest)
);
// Instance the postamble. Note that there is one block per DQS group, this is
// because each group generates its own half-rate resync clock and may require
// different postamble treatment :
generate
if (DWIDTH_RATIO == 4)
begin: hr_poa_gen
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS ; dqs_grp_num=dqs_grp_num+1)
begin : poa_group
//
ddr3_s4_amphy_phy_alt_mem_phy_postamble #(
.FAMILY (FAMILY),
.MEM_IF_POSTAMBLE_EN_WIDTH (8),
.POSTAMBLE_AWIDTH (POSTAMBLE_AWIDTH),
.POSTAMBLE_HALFT_EN (0),
.POSTAMBLE_INITIAL_LAT (POSTAMBLE_INITIAL_LAT),
.POSTAMBLE_RESYNC_LAT_CTL_EN (0),
.DWIDTH_RATIO (4)
) poa (
.phy_clk_1x (phy_clk_1x),
.resync_clk_1x (resync_clk_1x[dqs_grp_num]),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n[dqs_grp_num]),
.reset_resync_clk_1x_n (reset_resync_clk_1x_n[dqs_grp_num]),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x[dqs_grp_num]),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x[dqs_grp_num]),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.ctl_doing_rd_beat ({merged_doing_rd[dqs_grp_num + MEM_IF_DQS_WIDTH], merged_doing_rd[dqs_grp_num + 0]}),
.poa_postamble_en_preset (poa_postamble_en_preset[((dqs_grp_num + 1) * (DWIDTH_RATIO/2) - 1) : ((dqs_grp_num)*(DWIDTH_RATIO/2))])
);
end
end
else
begin: fr_poa_gen
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS ; dqs_grp_num=dqs_grp_num+1)
begin : poa_group
//
ddr3_s4_amphy_phy_alt_mem_phy_postamble #(
.FAMILY (FAMILY),
.MEM_IF_POSTAMBLE_EN_WIDTH (8),
.POSTAMBLE_AWIDTH (POSTAMBLE_AWIDTH),
.POSTAMBLE_HALFT_EN (0),
.POSTAMBLE_INITIAL_LAT (POSTAMBLE_INITIAL_LAT),
.POSTAMBLE_RESYNC_LAT_CTL_EN (0),
.DWIDTH_RATIO (2)
) poa (
.phy_clk_1x (phy_clk_1x),
.resync_clk_1x (resync_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n[dqs_grp_num]),
.reset_resync_clk_1x_n (reset_resync_clk_2x_n),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x[dqs_grp_num]),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x[dqs_grp_num]),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.ctl_doing_rd_beat (merged_doing_rd[dqs_grp_num + 0]),
.poa_postamble_en_preset (poa_postamble_en_preset[((dqs_grp_num + 1) * (DWIDTH_RATIO/2) - 1) : ((dqs_grp_num)*(DWIDTH_RATIO/2))])
);
end
end
endgenerate
// Generate the input to the RDV delay.
// Also determine the data for the OCT control & postamble paths (merged_doing_rd)
generate
if (DWIDTH_RATIO == 4)
begin : merging_doing_rd_halfrate
always @*
begin
merged_doing_rd = seq_rdv_doing_rd | (ctl_doing_rd & {(2 * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[ MEM_IF_DQS_WIDTH - 1 : 0];
rdv_pipe_ip[1] = | merged_doing_rd[2 * MEM_IF_DQS_WIDTH - 1 : MEM_IF_DQS_WIDTH];
end
end
else // DWIDTH_RATIO == 2 NOTE THAT THIS IS NOT CURRENTLY SUPPORTED
begin : merging_doing_rd_fullrate
always @*
begin
merged_doing_rd = seq_rdv_doing_rd | (ctl_doing_rd & { MEM_IF_DQS_WIDTH {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[MEM_IF_DQS_WIDTH - 1 : 0];
end
end // else: !if(DWIDTH_RATIO == 4)
endgenerate
// Generate rdata_valid for sequencer and controller
//
ddr3_s4_amphy_phy_alt_mem_phy_rdata_valid #(
.FAMILY (FAMILY),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.RDATA_VALID_AWIDTH (8),
.RDATA_VALID_INITIAL_LAT (RDV_INITIAL_LAT),
.DWIDTH_RATIO (DWIDTH_RATIO)
) rdv_pipe (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n[0]),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_doing_rd (seq_rdv_doing_rd),
.ctl_doing_rd (ctl_doing_rd),
.ctl_cal_success (ctl_cal_success),
.ctl_rdata_valid (ctl_rdata_valid),
.seq_rdata_valid (seq_rdata_valid)
);
//
ddr3_s4_amphy_phy_alt_mem_phy_clk_reset #(
.AC_PHASE ("MEM_CLK"),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.DDR_MIMIC_PATH_EN (DDR_MIMIC_PATH_EN),
.DLL_EXPORT_IMPORT (DLL_EXPORT_IMPORT),
.LOCAL_IF_CLK_PS (4000),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_CLK_PS_STR (MEM_IF_CLK_PS_STR),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.MIF_FILENAME ("PLL.MIF"),
.DWIDTH_RATIO (DWIDTH_RATIO),
.PLL_EXPORT_IMPORT ("NONE"),
.PLL_REF_CLK_PS (4000),
.PLL_TYPE ("ENHANCED"),
.SPEED_GRADE ("C3"),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH),
.DQS_OUT_MODE (DQS_OUT_MODE),
.DQS_PHASE (DQS_PHASE),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.USE_MEM_CLK_FOR_ADDR_CMD_CLK (1),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH),
.USE_DLL_OFFSET (USE_DLL_OFFSET),
.LEVELLING (LEVELLING),
.READ_DESKEW_MODE (READ_DESKEW_MODE),
.WRITE_DESKEW_MODE (WRITE_DESKEW_MODE),
.PLL_RECONFIG_PORTS_EN (PLL_RECONFIG_PORTS_EN)
) clk (
.pll_ref_clk (pll_ref_clk),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.seq_rdp_reset_req_n ({MEM_IF_DQS_WIDTH{seq_rdp_reset_req_n}}),
.seq_qdr_doff_req_n (),
.resync_clk_1x (resync_clk_1x),
.ac_clk_1x (ac_clk_1x),
.measure_clk_1x (measure_clk_1x),
.mem_clk_2x (mem_clk_2x),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.phy_clk_1x (phy_clk_1x_src),
.postamble_clk_2x (postamble_clk_2x),
.resync_clk_2x (resync_clk_2x),
.cs_n_clk_1x (cs_n_clk_1x),
.write_clk_2x (write_clk_2x),
.aux_clk (aux_clk),
.scan_clk (aux_scan_clk),
.aux_scan_clk_reset_n (aux_scan_clk_reset_n), // Connection New for 9.0
.scan_clk_in (scan_ck[0]),
.scan_enable_ck (scan_enable_ck),
.scan_update (scan_update[0]),
.scan_din (scan_din[0]),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.reset_measure_clk_1x_n (reset_measure_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_rdp_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.reset_resync_clk_1x_n (reset_resync_clk_1x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.reset_write_clk_2x_n (),
.reset_cs_n_clk_1x_n (reset_cs_n_clk_1x_n),
.mem_reset_n (),
.mem_doff_n (),
.reset_request_n (reset_request_n),
.dqs_delay_ctrl (dqs_delay_ctrl),
.dqs_delay_ctrl_import (dqs_delay_ctrl_import),
.dqs_delay_update_en (dqs_delay_update_en),
.dlloffset_addnsub (1'b0),
.dlloffset_offset ({DQS_DELAY_CTL_WIDTH{1'b0}}),
.dlloffset_offsetctrl_out (dlloffset_offsetctrl_out),
.phs_shft_busy (phs_shft_busy),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_select (seq_pll_select),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.mimic_data_1x (mimic_data),
.seq_clk_disable (seq_mem_clk_disable),
.ctrl_clk_disable (ctl_mem_clk_disable),
.pll_reconfig_enable (pll_reconfig_enable), // Connection New for 9.0
.pll_phasecounterselect (pll_phasecounterselect), // Connection New for 9.0
.pll_phaseupdown (pll_phaseupdown), // Connection New for 9.0
.pll_phasestep (pll_phasestep), // Connection New for 9.0
.pll_phase_done (pll_phase_done) // Connection New for 9.0
);
// Instance the mimic block :
//
ddr3_s4_amphy_phy_alt_mem_phy_mimic #(
.NUM_MIMIC_SAMPLE_CYCLES (NUM_MIMIC_SAMPLE_CYCLES)
) mmc (
.measure_clk (measure_clk_1x),
.reset_measure_clk_n (reset_measure_clk_1x_n),
.mimic_data_in (mimic_data),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value)
);
// If required, instance the Mimic debug block. If the debug block is used, a top level input
// for mimic_recapture_debug_data should be created.
generate
if (MIMIC_DEBUG_EN == 1)
begin : create_mimic_debug_ram
//
ddr3_s4_amphy_phy_alt_mem_phy_mimic_debug #(
.NUM_DEBUG_SAMPLES_TO_STORE (NUM_DEBUG_SAMPLES_TO_STORE),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE)
) mmc_debug (
.measure_clk (measure_clk_1x),
.reset_measure_clk_n (reset_measure_clk_1x_n),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mimic_recapture_debug_data (1'b0)
);
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_oct_delay ( // inputs
phy_clk_1x,
reset_phy_clk_1x_n,
oct_lat,
oct_extend_duration,
ctl_doing_rd,
// outputs
oct_out
);
parameter FAMILY = "STRATIXIII"; // why needed ??
parameter OCT_LAT_WIDTH = 5; // note hardcoded max lat of 32 mem_clk
parameter DWIDTH_RATIO = 4; // scales output & input widths..
// clocks
input wire phy_clk_1x;
// resets
input wire reset_phy_clk_1x_n;
// control signals from sequencer
input wire [OCT_LAT_WIDTH - 1 : 0] oct_lat;
input wire [OCT_LAT_WIDTH - 1 : 0] oct_extend_duration;
input wire [DWIDTH_RATIO / 2 - 1 : 0] ctl_doing_rd;
// output to IOE for SIII :
output reg [DWIDTH_RATIO / 2 - 1 : 0] oct_out;
localparam DELAY_ARRAY_SIZE = 32;
localparam MAX_EXTENSION = 14;
localparam EXTEND_ARRAY_SIZE = MAX_EXTENSION + (DWIDTH_RATIO / 2);
// internal wires/regs // these should probably be made 2D arrays for readability...
reg [DELAY_ARRAY_SIZE - 1 : 0] delay_array;
reg [EXTEND_ARRAY_SIZE - 1 : 0] extend_array;
reg [(DWIDTH_RATIO / 2) - 1 : 0] extended_value;
wire [(DWIDTH_RATIO / 2) - 1 : 0] pre_extended_value;
reg [EXTEND_ARRAY_SIZE - 1 : 0] pre_extend_array;
reg [MAX_EXTENSION : 0] extend_using_this_bit_mask;
wire [MAX_EXTENSION : 0] dwidth_scaled_pre_extend_array [(DWIDTH_RATIO / 2) - 1 : 0];
integer i;
integer j;
integer k;
integer l;
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n )
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
extend_using_this_bit_mask <= 0;
end
else
begin
for (i = 0; i < MAX_EXTENSION + 1; i = i + 1)
begin
if (i > oct_extend_duration)
extend_using_this_bit_mask[i] <= 1'b0;
else
extend_using_this_bit_mask[i] <= 1'b1;
end
end
end
// pre-extend array is re-ordered to allow this to be more easily visibly to humans.
always @*
begin
pre_extend_array[EXTEND_ARRAY_SIZE - 1 : (DWIDTH_RATIO / 2)] = extend_array[ EXTEND_ARRAY_SIZE - (DWIDTH_RATIO / 2) - 1: 0] ;
for (j=0; j < DWIDTH_RATIO / 2; j = j+1)
begin
pre_extend_array[j] = ctl_doing_rd[ (DWIDTH_RATIO / 2) -1 -j];
end
end
reg [DELAY_ARRAY_SIZE - 1 : 0] delay_array_temp;
// generate registered version
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n )
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
delay_array <= {DELAY_ARRAY_SIZE{1'b0}};
extend_array <= {EXTEND_ARRAY_SIZE{1'b0}};
oct_out <= {(DWIDTH_RATIO/2){1'b0}};
end
else
begin
delay_array_temp = {delay_array[ DELAY_ARRAY_SIZE - (DWIDTH_RATIO / 2) - 1 : 0], extended_value};
extend_array <= pre_extend_array;
delay_array <= delay_array_temp;
if (oct_lat < (DELAY_ARRAY_SIZE - (DWIDTH_RATIO / 2)) )
begin
for (l = 0; l < (DWIDTH_RATIO / 2); l = l + 1)
begin
oct_out[(DWIDTH_RATIO / 2) -1 -l] <= delay_array_temp[oct_lat + l];
end
end
else
oct_out <= 0;
end
end
// generate different array which can be anded to give a per bit result -- this is becasue RHS sweeping based on bits won't work !!
generate
genvar bits;
for (bits = 0; bits < (DWIDTH_RATIO / 2); bits = bits + 1)
begin : generate_arrays
assign dwidth_scaled_pre_extend_array[bits] = pre_extend_array[ MAX_EXTENSION + bits : bits];
assign pre_extended_value[bits] = | (extend_using_this_bit_mask & dwidth_scaled_pre_extend_array[bits]);
end
endgenerate
//for per bit in extended_vale use array (generated above) take result of bitwise and for all bits in vecotr (length of extension) and or result together(real lenght extension to 1 bit)
always @(extended_value or pre_extended_value)
begin
if (extended_value < MAX_EXTENSION +1)
begin
for (k = 0; k < (DWIDTH_RATIO / 2); k = k + 1)
begin
extended_value [k] = pre_extended_value[k];
end
end
else
extended_value = 0;
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_ac (
ac_clk_1x,
phy_clk_1x,
reset_phy_clk_1x_n,
reset_ac_clk_1x_n,
ctl_add_1t_ac_lat,
ctl_add_intermediate_regs,
seq_ac_sel,
ctl_ac_h,
ctl_ac_l,
seq_ac_h,
seq_ac_l,
mem_ac );
parameter POWER_UP_HIGH = 1;
parameter MEM_IF_MEMTYPE = "DDR";
parameter DWIDTH_RATIO = 4;
parameter INVERT_ADDR_CMD_TXFR_CLK = "false";
input wire ac_clk_1x;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
input wire reset_ac_clk_1x_n;
input wire ctl_add_1t_ac_lat;
input wire ctl_add_intermediate_regs;
input wire seq_ac_sel;
input wire ctl_ac_h;
input wire ctl_ac_l;
input wire seq_ac_h;
input wire seq_ac_l;
output wire mem_ac;
reg ac_h_r = POWER_UP_HIGH[0];
reg ac_l_r = POWER_UP_HIGH[0];
reg ac_del_1x = POWER_UP_HIGH[0];
reg ac_h_r_alt = POWER_UP_HIGH[0];
reg ac_l_r_alt = POWER_UP_HIGH[0];
reg ac_del_1x_alt = POWER_UP_HIGH[0];
reg ac_h_ddio_alt_r = POWER_UP_HIGH[0];
reg ac_l_ddio_alt_r = POWER_UP_HIGH[0];
reg ac_l;
reg ac_h;
reg ac_l_ddio;
reg ac_h_ddio;
reg ac_l_ddio_r;
reg ac_l_ddio_alt;
reg ac_h_ddio_alt;
wire reset_1x ;
reg ac_h_ddio_mux_op;
reg ac_l_ddio_datainlo;
reg ctl_ac_l_r = POWER_UP_HIGH[0];
reg ctl_ac_h_r = POWER_UP_HIGH[0];
reg seq_ac_l_r = POWER_UP_HIGH[0];
reg seq_ac_h_r = POWER_UP_HIGH[0];
// Active sense is high on atoms :
wire reset_ac_clk_1x;
assign reset_ac_clk_1x = ~reset_ac_clk_1x_n;
generate
if (MEM_IF_MEMTYPE != "DDR3")
begin : delay_ac
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_ac_l_r <= POWER_UP_HIGH[0];
ctl_ac_h_r <= POWER_UP_HIGH[0];
seq_ac_l_r <= POWER_UP_HIGH[0];
seq_ac_h_r <= POWER_UP_HIGH[0];
end
else
begin
ctl_ac_l_r <= ctl_ac_l;
ctl_ac_h_r <= ctl_ac_h;
seq_ac_l_r <= seq_ac_l;
seq_ac_h_r <= seq_ac_h;
end
end //always
end
else
begin : ac_passthru
always @*
begin
ctl_ac_l_r = ctl_ac_l;
ctl_ac_h_r = ctl_ac_h;
seq_ac_l_r = seq_ac_l;
seq_ac_h_r = seq_ac_h;
end //always
end
endgenerate
// Select between the sequencer inputs and the controller's :
generate
// QDR memory types :
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_ac_mux_gen
always @*
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l = ctl_ac_l;
ac_h = ctl_ac_h;
end
1'b1 :
begin
ac_l = seq_ac_l;
ac_h = seq_ac_h;
end
endcase
end //always
end
else
begin : ddr_ac_mux_gen
if (DWIDTH_RATIO == 4) //HR
begin : hr_mux_gen
// Half Rate DDR memory types require an extra cycle of latency :
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ac_l <= POWER_UP_HIGH[0];
ac_h <= POWER_UP_HIGH[0];
end
else
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l_r;
ac_h <= ctl_ac_h_r;
end
1'b1 :
begin
ac_l <= seq_ac_l_r;
ac_h <= seq_ac_h_r;
end
endcase
end
end //always
end
else // FR
begin : fr_passthru_gen
// Note that "_h" is unused in full-rate and no latency
// is required :
always @*
begin
casez(seq_ac_sel)
1'b0:
begin
ac_l = ctl_ac_l;
end
1'b1:
begin
ac_l = seq_ac_l;
end
endcase
end
end
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : half_rate
// Registering of inputs :
always @(posedge phy_clk_1x)
begin
ac_h_r <= ac_h;
ac_l_r <= ac_l;
ac_del_1x <= ac_l_r;
end
// Create alternative negedge registered versions
always @(negedge phy_clk_1x)
begin
ac_h_r_alt <= ac_h;
ac_l_r_alt <= ac_l;
ac_del_1x_alt <= ac_l_r_alt;
end
// Determine whether to add a cycle latency :
always @*
begin
casez(ctl_add_1t_ac_lat)
1'b0 :
begin
ac_l_ddio = ac_l_r;
ac_h_ddio = ac_h_r;
ac_l_ddio_alt = ac_l_r_alt;
ac_h_ddio_alt = ac_h_r_alt;
end
1'b1 :
begin
ac_l_ddio = ac_h_r;
ac_h_ddio = ac_del_1x;
ac_l_ddio_alt = ac_h_r_alt;
ac_h_ddio_alt = ac_del_1x_alt;
end
// X propagation :
default :
begin
ac_l_ddio = 1'bx;
ac_h_ddio = 1'bx;
ac_l_ddio_alt = 1'bx;
ac_h_ddio_alt = 1'bx;
end
endcase
end
// If using 'alt' signals, transfer to ac_clk in the core :
always @(posedge phy_clk_1x)
begin
ac_l_ddio_alt_r <= ac_l_ddio_alt;
ac_h_ddio_alt_r <= ac_h_ddio_alt;
end
// Nb. Quartus shall either remove the "alt" logic, or it's posedge equivalent
// based upon the setting of ctl_add_intermediate_regs :
always @*
begin
if (ctl_add_intermediate_regs == 1'b0)
begin
ac_h_ddio_mux_op = ac_h_ddio;
ac_l_ddio_datainlo = ac_l_ddio;
end
else
begin
ac_h_ddio_mux_op = ac_h_ddio_alt_r;
ac_l_ddio_datainlo = ac_l_ddio_alt_r;
end
end
if (POWER_UP_HIGH == 1)
begin : ac_power_up_high
stratixiii_ddio_out #(
.async_mode("preset"),
.power_up("high"),
.half_rate_mode("false"),
.use_new_clocking_model("true")
) addr_pin(
.datainlo (ac_l_ddio_datainlo),
.datainhi (ac_h_ddio_mux_op),
.clkhi (ac_clk_1x),
.clklo (ac_clk_1x),
.muxsel (ac_clk_1x),
.ena (1'b1),
.areset (reset_ac_clk_1x),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (mem_ac),
.devclrn (),
.devpor ()
);
end
else
begin : ac_power_up_low
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
) addr_pin (
.datainlo (ac_l_ddio_datainlo),
.datainhi (ac_h_ddio_mux_op),
.clkhi (ac_clk_1x),
.clklo (ac_clk_1x),
.muxsel (ac_clk_1x),
.ena (1'b1),
.areset (reset_ac_clk_1x),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (mem_ac),
.devclrn (),
.devpor ()
);
end
end // Half-rate
// Full-rate
// In full-rate modes, some addr/cmd phases require an inverted phy_clk here to make the transfer
// successfully. If core to addr/cmd clock timing is failing, then it may be that an incorrect
// default for this parameter was selected by the GUI.
// Tests have shown that for addr/cmd phases<270 degrees it should be inverted, otherwise it
// should not but this does vary dependant on frequency and loading, so for middling phases
// from 240 to 270 this parameter may need inverting.
else if (INVERT_ADDR_CMD_TXFR_CLK == "true")
begin : full_rate_inverted_clk
// Inverted PHY transfer clock :
always @(negedge phy_clk_1x)
begin
// Registering of inputs :
// 1t registering - only used if ctl_add_1t_ac_lat is true
ac_l_r <= ac_l;
// Determine whether to add a cycle latency :
// add 1 addr_clock delay if "Add 1T" is set:
if ( ctl_add_intermediate_regs == 1'b1)
ac_l_ddio <= ac_l_r;
else
ac_l_ddio <= ac_l;
end
// Inverted PHY transfer clock :
always @(negedge phy_clk_1x)
begin
ac_l_ddio_r <= ac_l_ddio;
end
if (POWER_UP_HIGH == 1)
begin
stratixiii_ddio_out #(
.async_mode("preset"),
.power_up("high"),
.half_rate_mode("false"),
.use_new_clocking_model("true")
) addr_pin(
.datainhi (ac_l_ddio_r),
.datainlo (ac_l_ddio),
.clkhi (ac_clk_1x),
.clklo (ac_clk_1x),
.muxsel (ac_clk_1x),
.ena (1'b1),
.areset (reset_ac_clk_1x),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (mem_ac),
.devclrn (),
.devpor ()
);
end
else
begin
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
) addr_pin (
.datainhi (ac_l_ddio_r),
.datainlo (ac_l_ddio),
.clkhi (ac_clk_1x),
.clklo (ac_clk_1x),
.muxsel (ac_clk_1x),
.ena (1'b1),
.areset (reset_ac_clk_1x),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (mem_ac),
.devclrn (),
.devpor ()
);
end // else: !if(POWER_UP_HIGH == 1)
end
else // the non-inverted case :
begin : full_rate_non_inverted_clk
// Non-Inverted PHY transfer clock :
always @(posedge phy_clk_1x)
begin
// Registering of inputs :
// 1t registering - only used if ctl_add_1t_ac_lat is true
ac_l_r <= ac_l;
// Determine whether to add a cycle latency :
// add 1 addr_clock delay if "Add 1T" is set:
if ( ctl_add_intermediate_regs == 1'b1)
ac_l_ddio <= ac_l_r;
else
ac_l_ddio <= ac_l;
end
// Non-Inverted PHY transfer clock :
always @(posedge phy_clk_1x)
begin
ac_l_ddio_r <= ac_l_ddio;
end
if (POWER_UP_HIGH == 1)
begin
stratixiii_ddio_out #(
.async_mode("preset"),
.power_up("high"),
.half_rate_mode("false"),
.use_new_clocking_model("true")
) addr_pin(
.datainhi (ac_l_ddio_r),
.datainlo (ac_l_ddio),
.clkhi (ac_clk_1x),
.clklo (ac_clk_1x),
.muxsel (ac_clk_1x),
.ena (1'b1),
.areset (reset_ac_clk_1x),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (mem_ac),
.devclrn (),
.devpor ()
);
end
else
begin
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
) addr_pin (
.datainhi (ac_l_ddio_r),
.datainlo (ac_l_ddio),
.clkhi (ac_clk_1x),
.clklo (ac_clk_1x),
.muxsel (ac_clk_1x),
.ena (1'b1),
.areset (reset_ac_clk_1x),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (mem_ac),
.devclrn (),
.devpor ()
);
end // else: !if(POWER_UP_HIGH == 1)
end // block: full_rate
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_addr_cmd (
ac_clk_1x,
cs_n_clk_1x,
phy_clk_1x,
reset_phy_clk_1x_n,
reset_ac_clk_1x_n,
// Usual Addr/cmd interface from controller :
ctl_add_1t_ac_lat,
ctl_add_1t_odt_lat,
ctl_add_intermediate_regs,
ctl_negedge_en,
ctl_mem_addr_h,
ctl_mem_addr_l,
ctl_mem_ba_h,
ctl_mem_ba_l,
ctl_mem_cas_n_h,
ctl_mem_cas_n_l,
ctl_mem_cke_h,
ctl_mem_cke_l,
ctl_mem_cs_n_h,
ctl_mem_cs_n_l,
ctl_mem_odt_h,
ctl_mem_odt_l,
ctl_mem_ras_n_h,
ctl_mem_ras_n_l,
ctl_mem_we_n_h,
ctl_mem_we_n_l,
// DDR3 Signals
ctl_mem_rst_n_h,
ctl_mem_rst_n_l,
//QDRII signals :
ctl_mem_wps_n,
ctl_mem_rps_n,
// Interface from Sequencer, used for DDR3 calibration
// as the MRS registers need to be controlled :
seq_addr_h,
seq_addr_l,
seq_ba_h,
seq_ba_l,
seq_cas_n_h,
seq_cas_n_l,
seq_cke_h,
seq_cke_l,
seq_cs_n_h,
seq_cs_n_l,
seq_odt_h,
seq_odt_l,
seq_ras_n_h,
seq_ras_n_l,
seq_we_n_h,
seq_we_n_l,
// DDR3 Signals
seq_mem_rst_n_h,
seq_mem_rst_n_l,
seq_ac_sel,
seq_wps_n,
seq_rps_n,
mem_ac_parity,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_odt,
mem_ras_n,
mem_we_n,
mem_rst_n,
mem_rps_n,
mem_wps_n
);
parameter FAMILY = "Stratix III";
parameter MEM_ADDR_CMD_BUS_COUNT = 1;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_NUM_RANKS = 2;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_ROWADDR_WIDTH = 13;
parameter DWIDTH_RATIO = 4;
parameter INVERT_ADDR_CMD_TXFR_CLK = "false";
parameter LEVELLING = 0;
parameter CHIP_OR_DIMM = "Unregistered DIMM";
input wire cs_n_clk_1x;
input wire ac_clk_1x;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
input wire reset_ac_clk_1x_n;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_l;
input wire ctl_add_1t_ac_lat;
input wire ctl_add_1t_odt_lat;
input wire ctl_add_intermediate_regs;
input wire ctl_negedge_en;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_l;
input wire ctl_mem_cas_n_h;
input wire ctl_mem_cas_n_l;
input wire [MEM_IF_NUM_RANKS - 1:0] ctl_mem_cke_h;
input wire [MEM_IF_NUM_RANKS - 1:0] ctl_mem_cke_l;
input wire [MEM_IF_NUM_RANKS - 1:0] ctl_mem_cs_n_h;
input wire [MEM_IF_NUM_RANKS - 1:0] ctl_mem_cs_n_l;
input wire [MEM_IF_NUM_RANKS - 1:0] ctl_mem_odt_h;
input wire [MEM_IF_NUM_RANKS - 1:0] ctl_mem_odt_l;
input wire ctl_mem_ras_n_h;
input wire ctl_mem_ras_n_l;
input wire ctl_mem_we_n_h;
input wire ctl_mem_we_n_l;
input wire ctl_mem_rst_n_h;
input wire ctl_mem_rst_n_l;
// QDRII has seperate read and write addresses that are multiplexed
// onto the ctl_mem_addr output :
input wire [MEM_IF_NUM_RANKS -1:0] ctl_mem_wps_n;
input wire [MEM_IF_NUM_RANKS -1:0] ctl_mem_rps_n;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_l;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_l;
input wire seq_cas_n_h;
input wire seq_cas_n_l;
input wire [MEM_IF_NUM_RANKS - 1:0] seq_cke_h;
input wire [MEM_IF_NUM_RANKS - 1:0] seq_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_l;
input wire [MEM_IF_NUM_RANKS - 1:0] seq_odt_h;
input wire [MEM_IF_NUM_RANKS - 1:0] seq_odt_l;
input wire seq_ras_n_h;
input wire seq_ras_n_l;
input wire seq_we_n_h;
input wire seq_we_n_l;
input wire seq_mem_rst_n_h;
input wire seq_mem_rst_n_l;
input wire seq_ac_sel;
// Sequencer QDR signals :
input wire [MEM_IF_NUM_RANKS -1:0] seq_wps_n;
input wire [MEM_IF_NUM_RANKS -1:0] seq_rps_n;
output wire mem_ac_parity;
output wire [MEM_IF_ROWADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_NUM_RANKS - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
output wire [MEM_IF_NUM_RANKS - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_rst_n;
output wire [MEM_IF_NUM_RANKS - 1 : 0] mem_rps_n;
output wire [MEM_IF_NUM_RANKS - 1 : 0] mem_wps_n;
genvar ia;
genvar ib;
genvar ic;
genvar id;
genvar ie;
// Create the ADDR I/O structure :
generate
// QDR memory types :
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdrii
// The address is multiplexed read/write addresses :
for (ia=0; ia<MEM_IF_ROWADDR_WIDTH; ia=ia+1)
begin : addr
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) addr_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_addr_h[ia]), // NB. Write == High
.ctl_ac_l (ctl_mem_addr_l[ia]),
.seq_ac_h (seq_addr_h[ia]),
.seq_ac_l (seq_addr_l[ia]),
.mem_ac (mem_addr[ia])
);
end
// Create the WPS_N I/O structure:
for (ib=0; ib<MEM_IF_CS_WIDTH; ib=ib+1)
begin : wps_n
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) wps_n_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_wps_n[ib]),
.ctl_ac_l (1'b1),
.seq_ac_h (seq_wps_n[ib]),
.seq_ac_l (1'b1),
.mem_ac (mem_wps_n[ib])
);
end
// Create the RPS_N I/O structure:
for (ic=0; ic<MEM_IF_CS_WIDTH; ic=ic+1)
begin : rps_n
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) rps_n_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (1'b1),
.ctl_ac_l (ctl_mem_rps_n[ic]),
.seq_ac_h (1'b1),
.seq_ac_l (seq_rps_n[ic]),
.mem_ac (mem_rps_n[ic])
);
end
end // QDRII
// DDR memory types :
else
begin : ddr
for (ia=0; ia<MEM_IF_ROWADDR_WIDTH; ia=ia+1)
begin : addr
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) addr_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_addr_h[ia]),
.ctl_ac_l (ctl_mem_addr_l[ia]),
.seq_ac_h (seq_addr_h[ia]),
.seq_ac_l (seq_addr_l[ia]),
.mem_ac (mem_addr[ia])
);
end
// Create the BANK_ADDR I/O structure :
for (ib=0; ib<MEM_IF_BANKADDR_WIDTH; ib=ib+1)
begin : ba
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) ba_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ba_h[ib]),
.ctl_ac_l (ctl_mem_ba_l[ib]),
.seq_ac_h (seq_ba_h[ib]),
.seq_ac_l (seq_ba_l[ib]),
.mem_ac (mem_ba[ib])
);
end
// Create the CAS_N I/O structure :
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) cas_n_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cas_n_h),
.ctl_ac_l (ctl_mem_cas_n_l),
.seq_ac_h (seq_cas_n_h),
.seq_ac_l (seq_cas_n_l),
.mem_ac (mem_cas_n)
);
// Create the CKE I/O structure:
for (ic=0; ic<MEM_IF_NUM_RANKS; ic=ic+1)
begin : cke
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) cke_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cke_h[ic]),
.ctl_ac_l (ctl_mem_cke_l[ic]),
.seq_ac_h (seq_cke_h[ic]),
.seq_ac_l (seq_cke_l[ic]),
.mem_ac (mem_cke[ic])
);
end
// Create the CS_N I/O structure. Note that the 2x clock is different.
// In RDIMMs, single-rank DIMMs has 2 chip selects but only one rank. The high-order bit is only used to configure the
// register but otherwise is unused. Lock any unused CS lines to high.
wire [MEM_IF_CS_WIDTH-1:0] ctl_mem_cs_n_h_padded = {{MEM_IF_CS_WIDTH-MEM_IF_NUM_RANKS{1'b1}}, ctl_mem_cs_n_h};
wire [MEM_IF_CS_WIDTH-1:0] ctl_mem_cs_n_l_padded = {{MEM_IF_CS_WIDTH-MEM_IF_NUM_RANKS{1'b1}}, ctl_mem_cs_n_l};
for (id=0; id<MEM_IF_CS_WIDTH; id=id+1)
begin : cs_n
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) cs_n_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cs_n_h_padded[id]),
.ctl_ac_l (ctl_mem_cs_n_l_padded[id]),
.seq_ac_h (seq_cs_n_h[id]),
.seq_ac_l (seq_cs_n_l[id]),
.mem_ac (mem_cs_n[id])
);
end
// Create the ODT I/O structure for DDR2 and 3 only :
if (MEM_IF_MEMTYPE != "DDR")
begin : gen_odt
for (ie=0; ie<MEM_IF_NUM_RANKS; ie=ie+1)
begin : odt
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
)odt_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_odt_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_odt_h[ie]),
.ctl_ac_l (ctl_mem_odt_l[ie]),
.seq_ac_h (seq_odt_h[ie]),
.seq_ac_l (seq_odt_l[ie]),
.mem_ac (mem_odt[ie])
);
end
end
// Create the RAS_N I/O structure :
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) ras_n_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ras_n_h),
.ctl_ac_l (ctl_mem_ras_n_l),
.seq_ac_h (seq_ras_n_h),
.seq_ac_l (seq_ras_n_l),
.mem_ac (mem_ras_n)
);
// Create the WE_N I/O structure :
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
) we_n_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_we_n_h),
.ctl_ac_l (ctl_mem_we_n_l),
.seq_ac_h (seq_we_n_h),
.seq_ac_l (seq_we_n_l),
.mem_ac (mem_we_n)
);
assign mem_rps_n = {MEM_IF_NUM_RANKS{1'b0}};
assign mem_wps_n = {MEM_IF_NUM_RANKS{1'b0}};
end
endgenerate
generate
if (MEM_IF_MEMTYPE == "DDR3")
begin : ddr3_rst
// generate rst_n for DDR3
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.INVERT_ADDR_CMD_TXFR_CLK (INVERT_ADDR_CMD_TXFR_CLK)
)ddr3_rst_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_rst_n_h),
.ctl_ac_l (ctl_mem_rst_n_l),
.seq_ac_h (seq_mem_rst_n_h),
.seq_ac_l (seq_mem_rst_n_l),
.mem_ac (mem_rst_n)
);
end
else
begin : no_ddr3_rst
assign mem_rst_n = 1'b1;
end
// Generate address/command parity signal
// Delay a bunch of config and select lines by 1 cycle
wire ctl_parity_h = ^({ctl_mem_addr_h, ctl_mem_ba_h, ctl_mem_cas_n_h, ctl_mem_ras_n_h, ctl_mem_we_n_h});
reg ctl_parity_l;
wire seq_parity_h = ^({seq_addr_h, seq_ba_h, seq_cas_n_h, seq_ras_n_h, seq_we_n_h});
reg seq_parity_l;
always @(posedge phy_clk_1x)
begin
ctl_parity_l <= ^({ctl_mem_addr_l, ctl_mem_ba_l, ctl_mem_cas_n_l, ctl_mem_ras_n_l, ctl_mem_we_n_l});
seq_parity_l <= ^({seq_addr_l, seq_ba_l, seq_cas_n_l, seq_ras_n_l, seq_we_n_l});
end
if (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1 && CHIP_OR_DIMM == "Registered DIMM")
begin : ddr3_parity
// generate parity for DDR3
//
ddr3_s4_amphy_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.DWIDTH_RATIO (DWIDTH_RATIO)
)ddr3_parity_struct (
.ac_clk_1x (ac_clk_1x),
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_parity_l),
.ctl_ac_l (ctl_parity_h),
.seq_ac_h (seq_parity_l),
.seq_ac_l (seq_parity_h),
.mem_ac (mem_ac_parity)
);
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_dp_io (
reset_write_clk_2x_n,
phy_clk_1x,
resync_clk_2x,
mem_clk_2x,
write_clk_2x,
resync_clk_1x,
sc_clk,
scan_enable_dqs_config,
scan_enable_dqs,
scan_enable_dq,
scan_enable_dm,
scan_update,
scan_din,
scan_dout,
dedicated_dll_delay_ctrl,
seq_dqs_delay_ctrl,
dll_offset_delay_ctrl,
dqs_update_en,
mem_d,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
dio_rdata3_1x,
dio_rdata2_1x,
dio_rdata1_1x,
dio_rdata0_1x,
poa_postamble_en_preset,
wdp_wdata3_1x,
wdp_wdata2_1x,
wdp_wdata1_1x,
wdp_wdata0_1x,
wdp_wdata_oe_h_1x,
wdp_wdata_oe_l_1x,
wdp_dqs3_1x,
wdp_dqs2_1x,
wdp_dqs1_1x,
wdp_dqs0_1x,
wdp_dqs_oe_h_1x,
wdp_dqs_oe_l_1x,
wdp_dm3_1x,
wdp_dm2_1x,
wdp_dm1_1x,
wdp_dm0_1x,
wdp_oct_h_1x,
wdp_oct_l_1x,
seriesterminationcontrol,
parallelterminationcontrol
) /* synthesis altera_attribute="SUPPRESS_DA_RULE_INTERNAL=C105" */ ;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_CAPTURE_EN = 1;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_MEMTYPE = "DDR";
parameter LEVELLING = 1;
parameter READ_DESKEW_MODE = "NONE";
parameter WRITE_DESKEW_MODE = "NONE";
parameter MEM_IF_DQSN_EN = 1;
parameter MEM_IF_OCT_EN = 0;
parameter MEM_IF_POSTAMBLE_EN_WIDTH = 8;
parameter MEM_IF_ROWADDR_WIDTH = 13;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 9000;
parameter DQS_PHASE_SETTING = 2;
parameter DWIDTH_RATIO = 4;
parameter ENABLE_DDR3_SEQUENCER = "FALSE";
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter MEM_TCL = "1.5";
parameter DQS_DELAY_USES_OFFSET = "false";
parameter INVERT_POSTAMBLE_CLK = "false";
localparam DM_PER_DQS = MEM_IF_DM_WIDTH / (MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS);
// To determine which DQS_CONFIG to connect the DM pins to, this depends upon the number
// of DQ pins per DQS and whether the memory type is DDR or QDR :
localparam DDR_BY8_OR_BY9 = ((MEM_IF_MEMTYPE != "QDRII") && (MEM_IF_DQ_PER_DQS != 4));
localparam QDRII_NORMAL_CQ_CQN_SWAPPING = 1;
localparam NUM_CLKDIVS_PER_GRP = cal_num_clkdivs_per_grp(MEM_IF_DQ_PER_DQS);
// Read.
localparam MEM_IF_CAPT_T1_DESKEW_EN = uses_dekew_delay(MEM_IF_MEMTYPE, LEVELLING, READ_DESKEW_MODE);
// Write.
localparam MEM_IF_WR_T9_DESKEW_EN = uses_delay(MEM_IF_MEMTYPE, LEVELLING);
localparam MEM_IF_WR_T10_DESKEW_EN = 0;
// Strobe.
localparam MEM_IF_STR_T9_DESKEW_EN = uses_delay(MEM_IF_MEMTYPE, LEVELLING);
localparam MEM_IF_STR_T10_DESKEW_EN = uses_dekew_delay(MEM_IF_MEMTYPE, LEVELLING, WRITE_DESKEW_MODE);
// OCT.
localparam MEM_IF_OCT_T9_DESKEW_EN = uses_delay(MEM_IF_MEMTYPE, LEVELLING);
localparam MEM_IF_OCT_T10_DESKEW_EN = 0;
// DQSLB.
localparam MEM_IF_USE_T7 = uses_dekew_delay(MEM_IF_MEMTYPE, LEVELLING, READ_DESKEW_MODE);
localparam MEM_IF_USE_T11 = uses_delay(MEM_IF_MEMTYPE, LEVELLING);
localparam MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL = "false";
localparam DQS_DELAY_CODE_FROM_DLL = "true";
localparam USE_DQS_DELAY_LATCHES = "false";
localparam DQS_USE_PHASECTRL_IN = "false";
localparam OPA_USES_DELAYED_CLK = "true";
localparam SINGLE_LEVELLING_DELAY_CHAIN = "true";
input wire reset_write_clk_2x_n;
input wire phy_clk_1x;
input wire resync_clk_2x;
input wire mem_clk_2x;
input wire write_clk_2x;
// The SIII half-rate resync clock is produced from clock dividers, 1 or 2 per
// DQS group (1 for 4 DQ per DQS, 2 for >4 DQ per DQS). These are output to the
// read_dp block to be used to re-sync the read data :
// NB. 'wire' omitted so that attributes can be applied later :
output [MEM_IF_DQS_WIDTH - 1 : 0] resync_clk_1x;
input wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] sc_clk;
input wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] scan_enable_dqs_config;
input wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] scan_enable_dqs;
input wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
input wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] scan_din;
input wire [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] scan_update;
output reg [MEM_IF_DWIDTH - 1 : 0] scan_dout;
// This goes to the output phase aligns
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
// Modified DLL delay control from the core - only used when MEM_IF_DQS_CAPTURE is true.
// The sequencer shall phase-shift the DQS delay to optimise the capture window.
// This goes to the DQS delay chains/enable
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] seq_dqs_delay_ctrl;
// the below wire is used to connect up the DLL phase offset primaive when connected.
input wire [DQS_DELAY_CTL_WIDTH-1:0] dll_offset_delay_ctrl;
// Used for controlling the DQS delay updates from the core or DLL
input wire dqs_update_en;
output wire [MEM_IF_DWIDTH - 1 : 0] mem_d;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
inout wire [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout wire [MEM_IF_DQS_WIDTH - 1 : 0] mem_dqs;
inout wire [MEM_IF_DQS_WIDTH - 1 : 0] mem_dqsn;
(* preserve *) output wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata3_1x;
(* preserve *) output wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata2_1x;
(* preserve *) output wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata1_1x;
(* preserve *) output wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata0_1x;
input wire [((DWIDTH_RATIO/2 )* MEM_IF_DQS_WIDTH) - 1 : 0] poa_postamble_en_preset;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata3_1x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata2_1x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata1_1x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata0_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_h_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_l_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs3_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs2_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs1_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs0_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_h_1x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_l_1x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm3_1x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm2_1x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm1_1x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm0_1x;
input wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_h_1x;
input wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_l_1x;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] seriesterminationcontrol;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] parallelterminationcontrol;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_n_captured;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_p_captured;
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_n_ams;
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_p_ams;
// Use DQS clock to register DQ read data
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_clk;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] dq_capture_clk;
// Create one divider clock output per clock divider. There shall be "cal_num_clkdivs_per_grp" clock dividers per DQS group :
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] div_clk [0 : NUM_CLKDIVS_PER_GRP - 1] ;
// Each DQS group has it's own DQS enable signal :
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_enable_src;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_enable;
// QDRII uses pseudo-differential DQS/DQSN, therefore the DQSN path needs to be defined :
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] dqsn_enable_src;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] dqsn_enable;
// This must be global, so that the clock dividers can access it :
wire [MEM_IF_DQS_WIDTH - 1 : 0] dividerphasesetting [0 : NUM_CLKDIVS_PER_GRP - 1] ;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] resync_clk_1x ;
wire [MEM_IF_DQS_WIDTH - 1 : 0] resync_clk_array [0 : NUM_CLKDIVS_PER_GRP - 1] ;
wire [MEM_IF_DQS_WIDTH - 1 : 0] resync_clk_array_n [0 : NUM_CLKDIVS_PER_GRP - 1] ;
wire [((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH) - 1 : 0] delayed_poa_postamble_en_preset_sim;
reg [((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH) - 1 : 0] delayed_poa_postamble_en_preset;
wire ddr_div_clk_source;
wire [MEM_IF_DQS_WIDTH - 1 : 0] qdrii_div_clk_source;
wire [MEM_IF_DQS_WIDTH - 1 : 0] i_mem_dqs;
wire [MEM_IF_DQS_WIDTH - 1 : 0] i_mem_dqsn;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0] offset_dqs_delay_code;
wire [NUM_CLKDIVS_PER_GRP * MEM_IF_DQS_WIDTH - 1 : 0] scan_dout_dqs_config;
wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_dout_dqs;
wire [MEM_IF_DWIDTH - 1 : 0] scan_dout_dq;
wire [MEM_IF_DM_WIDTH - 1 : 0] scan_dout_dm;
genvar num_clkdivs;
genvar div_clk_num;
genvar dqs_grp_num;
genvar dm_num;
genvar dq_num;
genvar index;
// Delay postamble enable signal to prevent false failures in RTL simulation
//
generate
for (index=0; index<(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH; index=index+1)
begin : delay_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_delay # (
.WIDTH (1),
.DELAY_PS (MEM_IF_CLK_PS/4)
) postamble_preset_delay(
.s_in (poa_postamble_en_preset[index]),
.s_out (delayed_poa_postamble_en_preset_sim[index])
);
end
endgenerate
always @*
begin
delayed_poa_postamble_en_preset = delayed_poa_postamble_en_preset_sim;
end
// The resync clock is chosen for the read path and postamble RAMs.
generate
for (dqs_grp_num=0; dqs_grp_num < MEM_IF_DQS_WIDTH; dqs_grp_num = dqs_grp_num + 1)
begin : resync_clks_gen
assign resync_clk_1x [dqs_grp_num] = resync_clk_array[0][dqs_grp_num];
end
endgenerate
// Clock dividers :
function integer cal_num_clkdivs_per_grp (input integer dq_per_dqs);
begin
casez (dq_per_dqs)
4 : cal_num_clkdivs_per_grp = 1;
8 : cal_num_clkdivs_per_grp = 2;
9 : cal_num_clkdivs_per_grp = 2;
18 : cal_num_clkdivs_per_grp = 4;
default : cal_num_clkdivs_per_grp = 8;
endcase
end
endfunction
function integer calc_resync_index (input integer dq_num);
begin
if (MEM_IF_DQ_PER_DQS%9 == 0)
begin
casez (dq_num)
0,1,2,3 : calc_resync_index = 0;
4,5,6,7,8 : calc_resync_index = 1;
9,10,11,12 : calc_resync_index = 2;
13,14,15,16,17 : calc_resync_index = 3;
18,19,20,21 : calc_resync_index = 4;
22,23,24,25,26 : calc_resync_index = 5;
27,28,29,30 : calc_resync_index = 6;
default : calc_resync_index = 7;
endcase
end
else
calc_resync_index = dq_num/4;
end
endfunction
function integer uses_delay (input [31:0] mem_type,
input levelling);
begin
if (((mem_type == "DDR3") || (mem_type == "ddr3")) && levelling == 1)
uses_delay = 1;
else
uses_delay = 0;
end
endfunction
function integer uses_dekew_delay (input [31:0] mem_type,
input levelling,
input [31:0] mode);
begin
if (((mem_type == "DDR3") || (mem_type == "ddr3")) && levelling == 1 && ((mode != "NONE") && (mode != "none")))
uses_dekew_delay = 1;
else
uses_dekew_delay = 0;
end
endfunction
generate
if (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1)
begin : ddr_clkdiv_gen
assign ddr_div_clk_source = ~resync_clk_2x;
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DQS_WIDTH ; dqs_grp_num=dqs_grp_num+1)
begin : grp_gen
stratixiii_io_clock_divider # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.use_masterin ("false"),
.invert_phase ("false")
) clk_div_group_master (
.clk (ddr_div_clk_source),
.phaseselect (dividerphasesetting[0][dqs_grp_num]),
.delayctrlin (),
.phasectrlin (),
.masterin (),
.phaseinvertctrl (),
.devclrn (),
.devpor (),
.clkout (resync_clk_array[0][dqs_grp_num]),
.slaveout (div_clk[0][dqs_grp_num])
);
//Generate the necessary number of slaves per dqs group.if we are a group wider than x4
if (MEM_IF_DQ_PER_DQS > 4)
for (num_clkdivs=1; num_clkdivs < MEM_IF_DQ_PER_DQS/4; num_clkdivs = num_clkdivs + 1)
begin : slave_gen
// Drive masterin from the above divider :
stratixiii_io_clock_divider # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.use_masterin ("true"),
.invert_phase ("false")
) clk_div_slave (
.clk (ddr_div_clk_source),
.phaseselect (dividerphasesetting[num_clkdivs][dqs_grp_num]),
.delayctrlin (),
.phasectrlin (),
.masterin (div_clk[num_clkdivs-1][dqs_grp_num]),
.phaseinvertctrl (),
.devclrn (),
.devpor (),
.clkout (resync_clk_array[num_clkdivs][dqs_grp_num]),
.slaveout (div_clk[num_clkdivs][dqs_grp_num])
);
end
end
end
else if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_clkdiv_gen
// QDRII uses the DQS enable signal for the source of the clock dividers :
assign qdrii_div_clk_source = dqsn_enable_src;
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DQS_WIDTH ; dqs_grp_num=dqs_grp_num+1)
begin : grp_gen
stratixiii_io_clock_divider # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.use_masterin ("false"),
.invert_phase ("false")
) clk_div_group_master (
.clk (qdrii_div_clk_source[dqs_grp_num]),
.phaseselect (dividerphasesetting[0][dqs_grp_num]),
.delayctrlin (),
.phasectrlin (),
.masterin (),
.phaseinvertctrl (),
.devclrn (),
.devpor (),
.clkout (resync_clk_array[0][dqs_grp_num]),
.slaveout (div_clk[0][dqs_grp_num])
);
// Create any necessary slaves :
// In lieu of the old "_l" and "_h" system, we now generate indices 0,1,2.. to support wide QDRII groups :
for (num_clkdivs=1; num_clkdivs < NUM_CLKDIVS_PER_GRP; num_clkdivs = num_clkdivs + 1)
begin : slave_gen
// Drive masterin from the above divider :
stratixiii_io_clock_divider # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.use_masterin ("true"),
.invert_phase ("false")
) clk_div_slave (
.clk (qdrii_div_clk_source[dqs_grp_num]),
.phaseselect (dividerphasesetting[num_clkdivs][dqs_grp_num]),
.delayctrlin (),
.phasectrlin (),
.masterin (div_clk[num_clkdivs-1][dqs_grp_num]),
.phaseinvertctrl (),
.devclrn (),
.devpor (),
.clkout (resync_clk_array[num_clkdivs][dqs_grp_num]),
.slaveout (div_clk[num_clkdivs][dqs_grp_num])
);
end
end
end
else
begin : ddr_clkdiv_gen
assign ddr_div_clk_source = ~resync_clk_2x;
// Create first master and first slave (if > x4 group)
stratixiii_io_clock_divider # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.use_masterin ("false"),
.invert_phase ("false")
) clk_div_master(
.clk (ddr_div_clk_source),
.phaseselect (dividerphasesetting[0][0]),
.delayctrlin (),
.phasectrlin (),
.masterin (),
.phaseinvertctrl (),
.devclrn (),
.devpor (),
.clkout (resync_clk_array[0][0]),
.slaveout (div_clk[0][0])
);
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DQS_WIDTH ; dqs_grp_num=dqs_grp_num+1)
begin : grp_gen
// Create any necessary slaves :
// In lieu of the old "_l" and "_h" system, we now generate indices 0,1,2.. to support wide QDRII groups :
// For group 0 we already have element [0][0], as our master, so start incrementing from 1
for (num_clkdivs= (dqs_grp_num==0 ? 1:0); num_clkdivs < MEM_IF_DQ_PER_DQS/4; num_clkdivs = num_clkdivs + 1)
begin : slaves_gen
wire masterin; // Localvar for slave masterin clk feed
// If this is the first slave in the group, drive from slave in previous DQS group :
if (num_clkdivs==0) // NB. Therefore we are not in DQS group 0.
if (MEM_IF_DQ_PER_DQS == 8 || MEM_IF_DQ_PER_DQS == 9)
assign masterin = div_clk[1][dqs_grp_num-1]; // for dq_per_dqs==8
else
assign masterin = div_clk[0][dqs_grp_num-1]; // for dq_per_dqs==4
// Otherwise drive from previous slave (For dq_per_dqs>4 only):
else
assign masterin = div_clk[num_clkdivs-1][dqs_grp_num];
// Drive masterin from the above divider :
stratixiii_io_clock_divider # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.use_masterin ("true"),
.invert_phase ("false")
) clk_div_slave (
.clk (ddr_div_clk_source),
.phaseselect (dividerphasesetting[num_clkdivs][dqs_grp_num]),
.delayctrlin (),
.phasectrlin (),
.masterin (masterin),
.phaseinvertctrl (),
.devclrn (),
.devpor (),
.clkout (resync_clk_array[num_clkdivs][dqs_grp_num]),
.slaveout (div_clk[num_clkdivs][dqs_grp_num])
);
end
end
end
endgenerate
// Now create the DQ, DM and DQS/DQSN I/O paths themselves :
generate
for (dqs_grp_num=0; dqs_grp_num<MEM_IF_DQS_WIDTH ; dqs_grp_num=dqs_grp_num+1)
begin : dqs_group
// Local routing from DQS_CONFIG to DQS logic :
wire [`DQSCONFIG_DQS_BUSOUT_DELAY_SETTING_WIDTH-1 :0] dqsbusoutdelaysetting[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [`DQSCONFIG_DQS_EN_CTRL_PHASE_SETTING_WIDTH-1:0] dqsenablectrlphasesetting[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [`DQSCONFIG_DQS_EN_DELAY_SETTING_WIDTH-1 :0] dqsenabledelaysetting[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [2 :0] dqsinputphasesetting [0 : NUM_CLKDIVS_PER_GRP - 1];
wire [NUM_CLKDIVS_PER_GRP-1:0] enadqsenablephasetransferreg;
wire [NUM_CLKDIVS_PER_GRP-1:0] dqsenablectrlphaseinvert;
wire [NUM_CLKDIVS_PER_GRP-1:0] enaoctcycledelaysetting;
wire [NUM_CLKDIVS_PER_GRP-1:0] enaoutputcycledelaysetting;
wire [NUM_CLKDIVS_PER_GRP-1:0] enaoutputphasetransferreg;
wire [NUM_CLKDIVS_PER_GRP-1:0] enaoctphasetransferreg;
wire [`DQSCONFIG_RESYNC_IP_PHASE_SETTING_WIDTH-1 :0] resyncinputphasesetting [0 : NUM_CLKDIVS_PER_GRP - 1];
wire [NUM_CLKDIVS_PER_GRP-1:0] enainputcycledelaysetting;
wire [NUM_CLKDIVS_PER_GRP-1:0] enainputphasetransferreg;
wire [NUM_CLKDIVS_PER_GRP-1:0] resyncinputphaseinvert;
wire [NUM_CLKDIVS_PER_GRP-1:0] enadataoutbypass;
wire [NUM_CLKDIVS_PER_GRP-1:0] dqoutputphaseinvert;
wire [`DQSCONFIG_DQ_OP_PHASE_SETTING_WIDTH-1 :0] dqoutputphasesetting[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [`DQSCONFIG_DQS_OCT_DELAY_SETTING1_WIDTH-1 :0] octdelaysetting1[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [`DQSCONFIG_DQS_OCT_DELAY_SETTING2_WIDTH-1 :0] octdelaysetting2[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [`DQSCONFIG_DQS_OUTPUT_PHASE_SETTING_WIDTH-1 :0] dqsoutputphasesetting[0 : NUM_CLKDIVS_PER_GRP - 1];
wire [NUM_CLKDIVS_PER_GRP-1:0] dqsoutputphaseinvert;
wire dqs_sneak;
// First generate DQ pins for each DQS group :
for (dq_num=0; dq_num<MEM_IF_DQ_PER_DQS ; dq_num=dq_num+1)
begin : dq
// Note that if MEM_IF_DQ_PER_DQS is 8 or 9, two dqs_config blocks are instanced per DQS group
// and half the DQ pins are fed from one set of dqs_config outputs, and half from the other
//
ddr3_s4_amphy_phy_alt_mem_phy_dq_io # (
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.LEVELLING (LEVELLING),
.MEM_IF_OCT_EN (MEM_IF_OCT_EN),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.ENABLE_DDR3_SEQUENCER (ENABLE_DDR3_SEQUENCER),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH),
.MEM_IF_CAPT_T1_DESKEW_EN (MEM_IF_CAPT_T1_DESKEW_EN),
.MEM_IF_WR_T9_DESKEW_EN (MEM_IF_WR_T9_DESKEW_EN),
.MEM_IF_WR_T10_DESKEW_EN (MEM_IF_WR_T10_DESKEW_EN),
.MEM_IF_OCT_T9_DESKEW_EN (MEM_IF_OCT_T9_DESKEW_EN),
.MEM_IF_OCT_T10_DESKEW_EN (MEM_IF_OCT_T10_DESKEW_EN),
.MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL),
.OPA_USES_DELAYED_CLK (OPA_USES_DELAYED_CLK),
.SINGLE_LEVELLING_DELAY_CHAIN (SINGLE_LEVELLING_DELAY_CHAIN)
) dq_pad (
.phy_clk_1x (phy_clk_1x),
.write_clk_2x (write_clk_2x),
.mem_clk_2x (mem_clk_2x),
.resync_clk_2x (resync_clk_2x),
.resync_clk_1x (resync_clk_array[calc_resync_index(dq_num)][dqs_grp_num]),
.sc_clk (sc_clk[dqs_grp_num]),
.scan_din (scan_din[dqs_grp_num]),
.scan_update (scan_update[dqs_grp_num]),
.scan_enable (scan_enable_dq[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.scan_dout (scan_dout_dq[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.mem_d (mem_d[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.mem_dq (mem_dq[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.dqs_enable (dqs_enable[dqs_grp_num]),
.dqsn_enable (dqsn_enable[dqs_grp_num]),
.dio_rdata3_1x (dio_rdata3_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.dio_rdata2_1x (dio_rdata2_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.dio_rdata1_1x (dio_rdata1_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.dio_rdata0_1x (dio_rdata0_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.wdp_wdata3_1x (wdp_wdata3_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.wdp_wdata2_1x (wdp_wdata2_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.wdp_wdata1_1x (wdp_wdata1_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.wdp_wdata0_1x (wdp_wdata0_1x[dqs_grp_num*MEM_IF_DQ_PER_DQS+dq_num]),
.wdp_wdata_oe_h_1x (wdp_wdata_oe_h_1x[dqs_grp_num]),
.wdp_wdata_oe_l_1x (wdp_wdata_oe_l_1x[dqs_grp_num]),
.wdp_oct_h_1x (wdp_oct_h_1x[dqs_grp_num]),
.wdp_oct_l_1x (wdp_oct_l_1x[dqs_grp_num]),
.dedicated_dll_delay_ctrl (dedicated_dll_delay_ctrl),
.dqoutputphasesetting (dqoutputphasesetting[calc_resync_index(dq_num)]),
.dqoutputphaseinvert (dqoutputphaseinvert[calc_resync_index(dq_num)]),
.enaoutputcycledelaysetting (enaoutputcycledelaysetting[calc_resync_index(dq_num)]),
.enaoutputphasetransferreg (enaoutputphasetransferreg[calc_resync_index(dq_num)]),
.resyncinputphasesetting (resyncinputphasesetting[calc_resync_index(dq_num)]),
.enainputcycledelaysetting (enainputcycledelaysetting[calc_resync_index(dq_num)]),
.enainputphasetransferreg (enainputphasetransferreg[calc_resync_index(dq_num)]),
.resyncinputphaseinvert (resyncinputphaseinvert[calc_resync_index(dq_num)]),
.enadataoutbypass (enadataoutbypass[calc_resync_index(dq_num)]),
.dqsoutputphasesetting (dqsoutputphasesetting[calc_resync_index(dq_num)]),
.dqsoutputphaseinvert (dqsoutputphaseinvert[calc_resync_index(dq_num)]),
.enaoctcycledelaysetting (enaoctcycledelaysetting[calc_resync_index(dq_num)]),
.enaoctphasetransferreg (enaoctphasetransferreg[calc_resync_index(dq_num)]),
.octdelaysetting1 (octdelaysetting1[calc_resync_index(dq_num)]),
.octdelaysetting2 (octdelaysetting2[calc_resync_index(dq_num)]),
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol (parallelterminationcontrol)
);
end
// DM Pin - if required :
if (MEM_IF_DM_PINS_EN)
begin : dm_gen
// First generate DQ pins for each DQS group. For DDR only x8 or x9 groups are supported and
// for these just one DM pin is required. For QDRII there may be more DMs per group :
for (dm_num=0; dm_num<DM_PER_DQS ; dm_num=dm_num+1)
begin : dm_pad_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_dm # (
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.LEVELLING (LEVELLING),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DWIDTH_RATIO (DWIDTH_RATIO),
.ENABLE_DDR3_SEQUENCER (ENABLE_DDR3_SEQUENCER),
.MEM_IF_WR_T9_DESKEW_EN (MEM_IF_WR_T9_DESKEW_EN),
.MEM_IF_WR_T10_DESKEW_EN (MEM_IF_WR_T10_DESKEW_EN),
.MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL),
.OPA_USES_DELAYED_CLK (OPA_USES_DELAYED_CLK),
.SINGLE_LEVELLING_DELAY_CHAIN (SINGLE_LEVELLING_DELAY_CHAIN)
) dm_pad (
.phy_clk_1x (phy_clk_1x),
.write_clk_2x (write_clk_2x),
.sc_clk (sc_clk[dqs_grp_num]),
.scan_din (scan_din[dqs_grp_num]),
.scan_update (scan_update[dqs_grp_num]),
.scan_enable (scan_enable_dm[dqs_grp_num]),
.scan_dout (scan_dout_dm[dqs_grp_num]),
.mem_dm ( mem_dm[dqs_grp_num * DM_PER_DQS + dm_num]),
.wdp_dm3_1x (wdp_dm3_1x[dqs_grp_num * DM_PER_DQS + dm_num]),
.wdp_dm2_1x (wdp_dm2_1x[dqs_grp_num * DM_PER_DQS + dm_num]),
.wdp_dm1_1x (wdp_dm1_1x[dqs_grp_num * DM_PER_DQS + dm_num]),
.wdp_dm0_1x (wdp_dm0_1x[dqs_grp_num * DM_PER_DQS + dm_num]),
.dedicated_dll_delay_ctrl (dedicated_dll_delay_ctrl),
.dqoutputphasesetting (dqoutputphasesetting[dm_num+DDR_BY8_OR_BY9]),
.enaoutputcycledelaysetting (enaoutputcycledelaysetting[dm_num+DDR_BY8_OR_BY9]),
.enaoutputphasetransferreg (enaoutputphasetransferreg[dm_num+DDR_BY8_OR_BY9]),
.dqoutputphaseinvert (dqoutputphaseinvert[dm_num+DDR_BY8_OR_BY9]),
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol (parallelterminationcontrol)
);
end
end
// Instance the DQS enable path once per DQS group :
//
ddr3_s4_amphy_phy_alt_mem_phy_dqs_ip # (
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_CLK_PS_STR (MEM_IF_CLK_PS_STR),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.LEVELLING (LEVELLING),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DQS_PHASE (DQS_PHASE),
.DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.DWIDTH_RATIO (DWIDTH_RATIO),
.ENABLE_DDR3_SEQUENCER (ENABLE_DDR3_SEQUENCER),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH),
.MEM_TCL (MEM_TCL),
.DQS_DELAY_CODE_FROM_DLL (DQS_DELAY_CODE_FROM_DLL),
.DQS_DELAY_USES_OFFSET (DQS_DELAY_USES_OFFSET),
.USE_DQS_DELAY_LATCHES (USE_DQS_DELAY_LATCHES),
.DQS_USE_PHASECTRL_IN (DQS_USE_PHASECTRL_IN),
.MEM_IF_USE_T11 (MEM_IF_USE_T11),
.MEM_IF_USE_T7 (MEM_IF_USE_T7),
.INVERT_POSTAMBLE_CLK (INVERT_POSTAMBLE_CLK)
) dqs_ip (
.poa_postamble_en_preset (delayed_poa_postamble_en_preset[((dqs_grp_num + 1) * (DWIDTH_RATIO/2) - 1) : ((dqs_grp_num)*(DWIDTH_RATIO/2))]),
.resync_clk_1x (resync_clk_array[0][dqs_grp_num]),
.resync_clk_2x (resync_clk_2x),
.dedicated_dll_delay_ctrl (dedicated_dll_delay_ctrl),
.seq_dqs_delay_ctrl (seq_dqs_delay_ctrl),
.dll_offset_delay_ctrl (dll_offset_delay_ctrl),
.dqs_update_en (dqs_update_en),
.dqsinputphasesetting (dqsinputphasesetting[0]),
.dqs_pad (i_mem_dqs[dqs_grp_num]),
.dqsn_pad (i_mem_dqsn[dqs_grp_num]),
.dqs_enable (dqs_enable_src[dqs_grp_num]),
.dqsn_enable (dqsn_enable_src[dqs_grp_num]),
.dqsbusoutdelaysetting (dqsbusoutdelaysetting[0]),
.dqsenablectrlphasesetting (dqsenablectrlphasesetting[0]),
.dqsenabledelaysetting (dqsenabledelaysetting[0]),
.enadqsenablephasetransferreg (enadqsenablephasetransferreg[0]),
.dqsenablectrlphaseinvert (dqsenablectrlphaseinvert[0]),
.enaoutputcycledelaysetting (enaoutputcycledelaysetting[0]),
.enaoutputphasetransferreg (enaoutputphasetransferreg[0]),
.dqsoutputphaseinvert (dqsoutputphaseinvert[0]),
.dqsoutputphasesetting (dqsoutputphasesetting[0])
);
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_swap_cqs_based_on_mem_tcl
//****Possible MEM_TCL latency values
//** Altera recommendation followed: FPGA pin swap of CQ/CQn pins
// MEM_TCL = 2.0
//** Altera recommendation not followed: No FPGA pin swap of CQ/CQn pins
// MEM_TCL = 1.5/2.5
//These effects are only visible on the device pinout!
if ((MEM_TCL === "1.5") || (MEM_TCL === "2.5") || (MEM_TCL === "12.0"))
begin : qdr_normal_cq_cqn
assign i_mem_dqs[dqs_grp_num] = mem_dqs [dqs_grp_num];
assign i_mem_dqsn[dqs_grp_num] = mem_dqsn[dqs_grp_num];
end
else // MEM_TCL === "2.0" || "11.5" || "12.5"
begin : qdr_swapped_cq_cqn
assign i_mem_dqs[dqs_grp_num] = mem_dqsn[dqs_grp_num];
assign i_mem_dqsn[dqs_grp_num] = mem_dqs [dqs_grp_num];
end
assign dqs_enable[dqs_grp_num] = dqs_enable_src[dqs_grp_num];
assign dqsn_enable[dqs_grp_num] = dqsn_enable_src[dqs_grp_num];
end
else
begin : ddr_dqs_enable_gen
assign i_mem_dqs[dqs_grp_num] = mem_dqs [dqs_grp_num];
assign i_mem_dqsn[dqs_grp_num] = mem_dqsn[dqs_grp_num];
assign dqs_enable[dqs_grp_num] = dqs_enable_src[dqs_grp_num];
assign dqsn_enable[dqs_grp_num] = dqsn_enable_src[dqs_grp_num];
end
// NB. Share the scan_din and scan_update per DQS group.
// DQS Output path not required for QDRII :
if (MEM_IF_MEMTYPE != "QDRII")
begin : dqs_op_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_dqs_op # (
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.INVERT_OP_FOR_DQSN (0),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.LEVELLING (LEVELLING),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.MEM_IF_OCT_EN (MEM_IF_OCT_EN),
.DWIDTH_RATIO (DWIDTH_RATIO),
.ENABLE_DDR3_SEQUENCER (ENABLE_DDR3_SEQUENCER),
.MEM_IF_STR_T9_DESKEW_EN (MEM_IF_STR_T9_DESKEW_EN),
.MEM_IF_STR_T10_DESKEW_EN (MEM_IF_STR_T10_DESKEW_EN),
.MEM_IF_OCT_T9_DESKEW_EN (MEM_IF_OCT_T9_DESKEW_EN),
.MEM_IF_OCT_T10_DESKEW_EN (MEM_IF_OCT_T10_DESKEW_EN),
.MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL),
.OPA_USES_DELAYED_CLK (OPA_USES_DELAYED_CLK)
) dqs_op (
.phy_clk_1x (phy_clk_1x),
.write_clk_2x (write_clk_2x),
.mem_clk_2x (mem_clk_2x),
.sc_clk (sc_clk[dqs_grp_num]),
.scan_enable (scan_enable_dqs[dqs_grp_num]),
.scan_update (scan_update[dqs_grp_num]),
.scan_din (scan_din[dqs_grp_num]),
.scan_dout (scan_dout_dqs[dqs_grp_num]),
.wdp_dqs3_1x (wdp_dqs3_1x[dqs_grp_num]),
.wdp_dqs2_1x (wdp_dqs2_1x[dqs_grp_num]),
.wdp_dqs1_1x (wdp_dqs1_1x[dqs_grp_num]),
.wdp_dqs0_1x (wdp_dqs0_1x[dqs_grp_num]),
.wdp_dqs_oe_h_1x (wdp_dqs_oe_h_1x[dqs_grp_num]),
.wdp_dqs_oe_l_1x (wdp_dqs_oe_l_1x[dqs_grp_num]),
.wdp_oct_h_1x (wdp_oct_h_1x[dqs_grp_num]),
.wdp_oct_l_1x (wdp_oct_l_1x[dqs_grp_num]),
.dqs_sneak_in (),
.dqs_sneak_out (dqs_sneak),
.dqs_pad (mem_dqs[dqs_grp_num]),
.dedicated_dll_delay_ctrl (dedicated_dll_delay_ctrl),
.enaoutputcycledelaysetting (enaoutputcycledelaysetting[0]),
.enaoutputphasetransferreg (enaoutputphasetransferreg[0]),
.dqsoutputphaseinvert (dqsoutputphaseinvert[0]),
.dqsoutputphasesetting (dqsoutputphasesetting[0]),
.enaoctcycledelaysetting (enaoctcycledelaysetting[0]),
.enaoctphasetransferreg (enaoctphasetransferreg[0]),
.octdelaysetting1 (octdelaysetting1[0]),
.octdelaysetting2 (octdelaysetting2[0]),
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol (parallelterminationcontrol)
);
// For DDR3 and 2 where a DQSN pin is required, instance the dqs module again,
// but invert the output, and wire in the sneak output from the DQS pin :
if (MEM_IF_MEMTYPE == "DDR3" || (MEM_IF_MEMTYPE == "DDR2" && (MEM_IF_DQSN_EN == 1)) )
begin : dqsn_op_gen
//
ddr3_s4_amphy_phy_alt_mem_phy_dqs_op # (
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.INVERT_OP_FOR_DQSN (1),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.LEVELLING (LEVELLING),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.MEM_IF_OCT_EN (MEM_IF_OCT_EN),
.DWIDTH_RATIO (DWIDTH_RATIO),
.ENABLE_DDR3_SEQUENCER (ENABLE_DDR3_SEQUENCER),
.MEM_IF_STR_T9_DESKEW_EN (MEM_IF_STR_T9_DESKEW_EN),
.MEM_IF_STR_T10_DESKEW_EN (MEM_IF_STR_T10_DESKEW_EN),
.MEM_IF_OCT_T9_DESKEW_EN (MEM_IF_OCT_T9_DESKEW_EN),
.MEM_IF_OCT_T10_DESKEW_EN (MEM_IF_OCT_T10_DESKEW_EN),
.MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL),
.OPA_USES_DELAYED_CLK (OPA_USES_DELAYED_CLK)
) dqsn_op (
.phy_clk_1x (phy_clk_1x),
.write_clk_2x (write_clk_2x),
.mem_clk_2x (mem_clk_2x),
.sc_clk (sc_clk[dqs_grp_num]),
.scan_enable (),
.scan_update (),
.scan_din (),
.scan_dout (),
.wdp_dqs3_1x (wdp_dqs3_1x[dqs_grp_num]),
.wdp_dqs2_1x (wdp_dqs2_1x[dqs_grp_num]),
.wdp_dqs1_1x (wdp_dqs1_1x[dqs_grp_num]),
.wdp_dqs0_1x (wdp_dqs0_1x[dqs_grp_num]),
.wdp_dqs_oe_h_1x (wdp_dqs_oe_h_1x[dqs_grp_num]),
.wdp_dqs_oe_l_1x (wdp_dqs_oe_l_1x[dqs_grp_num]),
.wdp_oct_h_1x (wdp_oct_h_1x[dqs_grp_num]),
.wdp_oct_l_1x (wdp_oct_l_1x[dqs_grp_num]),
.dqs_sneak_in (dqs_sneak),
.dqs_sneak_out (),
.dqs_pad (mem_dqsn[dqs_grp_num]),
.dedicated_dll_delay_ctrl (dedicated_dll_delay_ctrl),
.enaoutputcycledelaysetting (enaoutputcycledelaysetting[0]),
.enaoutputphasetransferreg (enaoutputphasetransferreg[0]),
.dqsoutputphaseinvert (dqsoutputphaseinvert[0]),
.dqsoutputphasesetting (dqsoutputphasesetting[0]),
.enaoctcycledelaysetting (enaoctcycledelaysetting[0]),
.enaoctphasetransferreg (enaoctphasetransferreg[0]),
.octdelaysetting1 (octdelaysetting1[0]),
.octdelaysetting2 (octdelaysetting2[0]),
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol (parallelterminationcontrol)
);
end
end // Not QDRII
// Create any necessary slaves :
// In lieu of the old "_l" and "_h" system, we now generate indices 0,1,2.. to support wide QDRII groups :
for (num_clkdivs=0; num_clkdivs < NUM_CLKDIVS_PER_GRP; num_clkdivs = num_clkdivs + 1)
begin : dqs_config_gen
stratixiii_dqs_config dqs_config(
.datain (scan_din[dqs_grp_num]),
.clk (sc_clk[dqs_grp_num]),
.ena (scan_enable_dqs_config[dqs_grp_num]),
.update (scan_update[dqs_grp_num]),
// synopsys translate_off
.devclrn(), .devpor(),
.dqsbusoutfinedelaysetting(),
.dqsenablefinedelaysetting(),
// synopsys translate_on
.dqsbusoutdelaysetting (dqsbusoutdelaysetting[num_clkdivs]),
.dqsinputphasesetting (dqsinputphasesetting [num_clkdivs]),
.dqsenablectrlphasesetting (dqsenablectrlphasesetting[num_clkdivs]),
.dqsoutputphasesetting (dqsoutputphasesetting[num_clkdivs]),
.dqoutputphasesetting (dqoutputphasesetting[num_clkdivs]),
.resyncinputphasesetting (resyncinputphasesetting[num_clkdivs]),
.dividerphasesetting (dividerphasesetting[num_clkdivs][dqs_grp_num]),
.enaoctcycledelaysetting (enaoctcycledelaysetting[num_clkdivs]),
.enainputcycledelaysetting (enainputcycledelaysetting[num_clkdivs]),
.enaoutputcycledelaysetting (enaoutputcycledelaysetting[num_clkdivs]),
.dqsenabledelaysetting (dqsenabledelaysetting[num_clkdivs]),
.octdelaysetting1 (octdelaysetting1[num_clkdivs]),
.octdelaysetting2 (octdelaysetting2[num_clkdivs]),
.enadataoutbypass (enadataoutbypass[num_clkdivs]),
.enadqsenablephasetransferreg (enadqsenablephasetransferreg[num_clkdivs]),
.enaoctphasetransferreg (enaoctphasetransferreg[num_clkdivs]),
.enaoutputphasetransferreg (enaoutputphasetransferreg[num_clkdivs]),
.enainputphasetransferreg (enainputphasetransferreg[num_clkdivs]),
.resyncinputphaseinvert (resyncinputphaseinvert[num_clkdivs]),
.dqsenablectrlphaseinvert (dqsenablectrlphaseinvert[num_clkdivs]),
.dqoutputphaseinvert (dqoutputphaseinvert[num_clkdivs]),
.dqsoutputphaseinvert (dqsoutputphaseinvert[num_clkdivs]),
.dataout (scan_dout_dqs_config[dqs_grp_num*NUM_CLKDIVS_PER_GRP + num_clkdivs])
);
end
end // DQS group
endgenerate
// Scan data out muxing - this is provided purely for HCx :
generate
if (MEM_IF_DM_PINS_EN)
begin : hcx_scan_dout_mux
always @*
begin
casez({|scan_enable_dqs_config, |scan_enable_dqs, |scan_enable_dq, |scan_enable_dm})
4'b1000 : scan_dout = {{ (MEM_IF_DWIDTH - (NUM_CLKDIVS_PER_GRP * MEM_IF_DQS_WIDTH) ){1'b0}}, scan_dout_dqs_config};
4'b0100 : scan_dout = {{ (MEM_IF_DWIDTH - MEM_IF_DQS_WIDTH){1'b0}}, scan_dout_dqs};
4'b0010 : scan_dout = scan_dout_dq;
default : scan_dout = {{(MEM_IF_DWIDTH - MEM_IF_DM_WIDTH){1'b0}}, scan_dout_dm};
endcase
end
end
else
begin : hcx_scan_dout_mux_no_dm
always @*
begin
casez({|scan_enable_dqs_config, |scan_enable_dqs, |scan_enable_dq})
3'b100 : scan_dout = {{ (MEM_IF_DWIDTH - (NUM_CLKDIVS_PER_GRP * MEM_IF_DQS_WIDTH) ){1'b0}}, scan_dout_dqs_config};
3'b010 : scan_dout = {{ (MEM_IF_DWIDTH - MEM_IF_DQS_WIDTH){1'b0}}, scan_dout_dqs};
default : scan_dout = scan_dout_dq;
endcase
end
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_dq_io (
phy_clk_1x,
write_clk_2x,
mem_clk_2x,
resync_clk_2x,
resync_clk_1x,
sc_clk,
scan_din,
scan_dout,
scan_update,
scan_enable,
mem_d,
mem_dq,
dqs_enable,
dqsn_enable,
dio_rdata3_1x,
dio_rdata2_1x,
dio_rdata1_1x,
dio_rdata0_1x,
wdp_wdata3_1x,
wdp_wdata2_1x,
wdp_wdata1_1x,
wdp_wdata0_1x,
wdp_wdata_oe_h_1x,
wdp_wdata_oe_l_1x,
wdp_oct_h_1x,
wdp_oct_l_1x,
dedicated_dll_delay_ctrl,
dqoutputphasesetting,
dqoutputphaseinvert,
enaoutputcycledelaysetting,
enaoutputphasetransferreg,
resyncinputphasesetting,
enainputcycledelaysetting,
enainputphasetransferreg,
resyncinputphaseinvert,
enadataoutbypass,
dqsoutputphasesetting,
dqsoutputphaseinvert,
enaoctcycledelaysetting,
enaoctphasetransferreg,
octdelaysetting1,
octdelaysetting2,
seriesterminationcontrol,
parallelterminationcontrol
) /* synthesis altera_attribute="SUPPRESS_DA_RULE_INTERNAL=D101" */ ;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_MEMTYPE = "DDR";
parameter LEVELLING = 1;
parameter MEM_IF_OCT_EN = 0;
parameter MEM_IF_DQS_WIDTH = 8;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DWIDTH_RATIO = 4;
parameter ENABLE_DDR3_SEQUENCER = "FALSE";
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter MEM_IF_CAPT_T1_DESKEW_EN = 0;
parameter MEM_IF_WR_T9_DESKEW_EN = 0;
parameter MEM_IF_WR_T10_DESKEW_EN = 0;
parameter MEM_IF_OCT_T9_DESKEW_EN = 0;
parameter MEM_IF_OCT_T10_DESKEW_EN = 0;
parameter MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL = "FALSE";
parameter OPA_USES_DELAYED_CLK = "false";
parameter SINGLE_LEVELLING_DELAY_CHAIN = "true";
input wire phy_clk_1x;
input wire write_clk_2x;
input wire mem_clk_2x;
input wire resync_clk_2x;
input wire resync_clk_1x;
input wire sc_clk;
input wire scan_din;
input wire scan_update;
input wire scan_enable;
output wire scan_dout;
inout wire mem_dq;
output wire mem_d; // For QDRII only
input wire dqs_enable;
input wire dqsn_enable;
output wire dio_rdata3_1x;
output wire dio_rdata2_1x;
output wire dio_rdata1_1x;
output wire dio_rdata0_1x;
input wire wdp_wdata3_1x;
input wire wdp_wdata2_1x;
input wire wdp_wdata1_1x;
input wire wdp_wdata0_1x;
input wire wdp_wdata_oe_h_1x;
input wire wdp_wdata_oe_l_1x;
input wire wdp_oct_h_1x;
input wire wdp_oct_l_1x;
input wire [ DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
input wire [`DQSCONFIG_DQ_OP_PHASE_SETTING_WIDTH-1 :0] dqoutputphasesetting;
input wire dqoutputphaseinvert;
input wire enaoutputcycledelaysetting;
input wire enaoutputphasetransferreg;
input wire [`DQSCONFIG_RESYNC_IP_PHASE_SETTING_WIDTH-1:0] resyncinputphasesetting;
input wire enainputcycledelaysetting;
input wire enainputphasetransferreg;
input wire resyncinputphaseinvert;
input wire enadataoutbypass;
//OCT only :
input wire [`DQSCONFIG_DQS_OUTPUT_PHASE_SETTING_WIDTH-1:0] dqsoutputphasesetting;
input wire dqsoutputphaseinvert;
input wire enaoctcycledelaysetting;
input wire enaoctphasetransferreg;
input wire [`DQSCONFIG_DQS_OCT_DELAY_SETTING1_WIDTH-1 :0] octdelaysetting1;
input wire [`DQSCONFIG_DQS_OCT_DELAY_SETTING2_WIDTH-1 :0] octdelaysetting2;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] seriesterminationcontrol;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] parallelterminationcontrol;
wire [`IOCONFIG_DQ_PAD_TO_IP_REG_DELAY_SETTING_WIDTH-1:0] dq_padtoinputregisterdelaysetting;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING1_WIDTH-1 :0] dq_outputdelaysetting1;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING2_WIDTH-1 :0] dq_outputdelaysetting2;
wire dq_output_ibuf;
wire dq_t1_delay_dataout;
wire dqi_captured_h;
wire dqi_captured_l;
wire dqi_aligned_h;
wire dqi_aligned_l;
wire dqo_l;
wire dqo_h;
wire dqo_aligned;
wire dqo_delayed;
wire dqo_delayed2;
wire dqoe;
wire dqoe_aligned;
wire dqoe_delayed;
wire dqoe_delayed2;
wire dqoct;
wire dqoct_aligned;
wire dqoct_delayed;
wire dqoct_delayed2;
// Write side :
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_dqo_gen
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) dqo_ddio_in_h (
.datainhi (wdp_wdata3_1x),
.datainlo (wdp_wdata2_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqo_h),
.devclrn (),
.devpor ()
);
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) dqo_ddio_in_l (
.datainhi (wdp_wdata1_1x),
.datainlo (wdp_wdata0_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqo_l),
.devclrn (),
.devpor ()
);
end
else
begin : full_rate_dqo_gen
assign dqo_l = wdp_wdata0_1x;
assign dqo_h = wdp_wdata1_1x;
end
endgenerate
// Phase alignment is either via DDIO for DDR/DDR2 or phase alignment atom for DDR3 :
generate
if (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1)
begin : ddr3_dq_opa_gen
// Note : delay_buffer_mode for output_phase_alignment atoms must always
// be tied to "high" :
stratixiii_output_phase_alignment #(
.operation_mode ("ddio_out"),
.use_phasectrlin (ENABLE_DDR3_SEQUENCER),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.phase_setting_for_delayed_clock (2),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.invert_phase ("dynamic"),
.use_primary_clock (SINGLE_LEVELLING_DELAY_CHAIN),
.bypass_input_register ("false")
) dq_opa_inst(
.datain ({dqo_h,dqo_l}),
.clk (write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoutputcycledelaysetting),
.enaphasetransferreg (enaoutputphasetransferreg),
.phaseinvertctrl (dqoutputphaseinvert),
// synopsys translate_off
.delaymode(),
.dutycycledelayctrlin(),
.devclrn(),
.devpor(),
.dffin(),
.dff1t(),
.dffddiodataout(),
// synopsys translate_on
.dataout (dqo_aligned)
);
end
// For DDR, DDR2, DDR3 (non-levelling solution) and QDRII, use a DDIO_OUT atom:
else
begin : ddr_qdr_dq_ddio_out_gen
// DDIO output
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
) dq_ddio_inst (
.datainhi (dqo_h),
.datainlo (dqo_l),
.clkhi (write_clk_2x),
.clklo (write_clk_2x),
.muxsel (write_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk (),
// synopsys translate_on
.dataout (dqo_aligned),
.devclrn (),
.devpor ()
);
end
endgenerate
// Switch to OE side :
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_dqoe_gen
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) dqoe_ddio_in_h(
.datainhi (~wdp_wdata_oe_h_1x),
.datainlo (~wdp_wdata_oe_l_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqoe),
.devclrn (),
.devpor ()
);
end
else
begin : full_rate_dqoe_gen
assign dqoe = ~wdp_wdata_oe_l_1x;
end
endgenerate
// Phase alignment is either via DDIO for DDR/DDR2 or phase alignment atom for DDR3 :
generate
if (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1)
begin :ddr3_opa_gen
// output_phase_alignment of oe
// Note : delay_buffer_mode for output_phase_alignment atoms must always
// be tied to "high" :
stratixiii_output_phase_alignment # (
.operation_mode ("oe"),
.use_phasectrlin (ENABLE_DDR3_SEQUENCER),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.phase_setting_for_delayed_clock (2),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.invert_phase ("dynamic"),
.use_primary_clock (SINGLE_LEVELLING_DELAY_CHAIN),
.bypass_input_register ("false")
) dq_oepa_inst(
.datain ({1'b0,dqoe}),
.clk (write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoutputcycledelaysetting),
.enaphasetransferreg (enaoutputphasetransferreg),
.phaseinvertctrl (dqoutputphaseinvert),
// synopsys translate_off
.delaymode(),
.dutycycledelayctrlin(),
.devclrn(),
.devpor(),
.dffin(),
.dff1t(),
.dffddiodataout(),
// synopsys translate_on
.dataout (dqoe_aligned)
);
end
// For DDR, DDR2, DDR3 (non-levelling solution) and QDRII, use a DFF atom:
else
begin : ddr_dff_gen
// The attribute here ensures the flop is not reduced, and is placed in the I/O :
(* altera_attribute = "-name FAST_OUTPUT_ENABLE_REGISTER ON" *) dff dq_oedff_inst(
.d (dqoe),
.clk (write_clk_2x),
.clrn (1'b1),
.prn (),
.q (dqoe_aligned)
);
end
endgenerate
generate
if (MEM_IF_WR_T9_DESKEW_EN == 1)
begin : gen_T9_dp_deskew
stratixiii_delay_chain dqoe_t9_delay(
.datain (dqoe_aligned),
.delayctrlin (dq_outputdelaysetting1),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqoe_delayed)
);
stratixiii_delay_chain dqo_t9_delay(
.datain (dqo_aligned),
.delayctrlin (dq_outputdelaysetting1),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqo_delayed)
);
end
else
begin : gen_T9_dp_no_deskew
assign dqoe_delayed = dqoe_aligned;
assign dqo_delayed = dqo_aligned;
end
endgenerate
generate
if (MEM_IF_WR_T10_DESKEW_EN == 1)
begin : gen_T10_dp_deskew
stratixiii_delay_chain dqoe_t10_delay(
.datain (dqoe_delayed),
.delayctrlin ({1'b0, dq_outputdelaysetting2}),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqoe_delayed2)
);
stratixiii_delay_chain dqo_t10_delay(
.datain (dqo_delayed),
.delayctrlin ({1'b0, dq_outputdelaysetting2}),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqo_delayed2)
);
end
else
begin : gen_T10_dp_no_deskew
assign dqoe_delayed2 = dqoe_delayed;
assign dqo_delayed2 = dqo_delayed;
end
endgenerate
// Switch to OCT if required :
generate
if (MEM_IF_OCT_EN == 1)
begin : oct_gen
if (DWIDTH_RATIO == 4)
begin : half_rate_dqoct_gen
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) dqoct_ddio_in_h(
.datainhi (wdp_oct_h_1x),
.datainlo (wdp_oct_l_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqoct),
.devclrn (),
.devpor ()
);
end
else
begin : full_rate_dqoct_gen
assign dqoct = wdp_oct_l_1x;
end
// Phase alignment is either via DDIO for DDR/DDR2/DDR3(non-levelling) or phase alignment atom for DDR3 :
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2" || (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 0))
begin : ddio_oe_oct_gen
// DDIO OE output
stratixiii_ddio_oe dqoct_ddio_inst (
.oe (dqoct),
.clk (mem_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
.dataout (dqoct_aligned),
// synopsys translate_off
.dfflo(),
.dffhi(),
// synopsys translate_on
.devclrn (),
.devpor ()
);
end
else
begin : opa_oct_gen
// output_phase_alignment of oct
// Note : delay_buffer_mode for output_phase_alignment atoms must always
// be tied to "high" :
stratixiii_output_phase_alignment # (
.operation_mode ("rtena"),
.use_phasectrlin (ENABLE_DDR3_SEQUENCER),
.phase_setting (2), // to match DQS
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("none"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.phase_setting_for_delayed_clock (2),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.invert_phase ("dynamic"),
.use_primary_clock ("true"),
.bypass_input_register ("false")
) dq_octpa_inst(
.datain ({1'b0,dqoct}),
.clk (write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqsoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoctcycledelaysetting),
.enaphasetransferreg (enaoctphasetransferreg),
.phaseinvertctrl (dqsoutputphaseinvert),
// synopsys translate_off
.devclrn(), .devpor(),
.dffin(), .dff1t(), .dffddiodataout(),
// synopsys translate_on
.dataout (dqoct_aligned)
);
end
if (MEM_IF_OCT_T9_DESKEW_EN == 1)
begin : gen_T9_OCT_deskew
stratixiii_delay_chain dqoct_t9_delay(
.datain (dqoct_aligned),
.delayctrlin (octdelaysetting1),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqoct_delayed)
);
end
else
begin : gen_T9_OCT_no_deskew
assign dqoct_delayed = dqoct_aligned;
end
if (MEM_IF_OCT_T10_DESKEW_EN == 1)
begin : gen_T10_OCT_deskew
stratixiii_delay_chain dqoct_t10_delay(
.datain (dqoct_delayed),
.delayctrlin ({1'b0, octdelaysetting2}),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqoct_delayed2)
);
end
else
begin : gen_T10_OCT_no_deskew
assign dqoct_delayed2 = dqoct_delayed;
end
end // if MEM_IF_OCT_EN
// No OCT :
else
begin : no_oct_gen
assign dqoct_delayed2 = 1'b0;
end
endgenerate
generate
// QDR has unidirectional data :
if (MEM_IF_MEMTYPE == "QDRII")
begin : gen_qdr_obuf
// output buf
stratixiii_io_obuf # (
.bus_hold ( "false"),
.open_drain_output ( "false"),
.shift_series_termination_control (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL)
) dq_obuf_inst(
.i (dqo_delayed2),
.oe (~dqoe_delayed2),
.dynamicterminationcontrol (dqoct_delayed2),
// synopsys translate_off
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol(parallelterminationcontrol),
.obar (),
// synopsys translate_on
.o (mem_d)
);
end
// This is the same for DDR2 and DDR3 modes - bidirectional:
else
begin : gen_ddr_obuf
stratixiii_io_obuf # (
.bus_hold ( "false"),
.open_drain_output ( "false"),
.shift_series_termination_control (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL)
) dq_obuf_inst(
.i (dqo_delayed2),
.oe (~dqoe_delayed2),
.dynamicterminationcontrol (dqoct_delayed2),
// synopsys translate_off
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol(parallelterminationcontrol),
.obar (),
// synopsys translate_on
.devoe (),
.o (mem_dq)
);
assign mem_d = 1'b0;
end
endgenerate
// DQ Read data path
// Note that this is the same for DDR2 and DDR3 modes :
// Input buf
stratixiii_io_ibuf # (
.simulate_z_as("gnd")
) dqi_io_ibuf(
.i (mem_dq),
.ibar (),
// synopsys translate_off
.dynamicterminationcontrol(),
// synopsys translate_on
.o (dq_output_ibuf)
);
generate
if (MEM_IF_CAPT_T1_DESKEW_EN == 1)
begin : gen_dq_input_with_deskeq
stratixiii_delay_chain dqi_t1_delay (
.datain (dq_output_ibuf),
.delayctrlin (dq_padtoinputregisterdelaysetting),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dq_t1_delay_dataout)
);
end
else
begin : gen_dq_input_without_deskew
assign dq_t1_delay_dataout = dq_output_ibuf;
end
endgenerate
generate
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_dq_ddio_in_gen
// Capture DQ read data
stratixiii_ddio_in # (
.async_mode ("clear"),
.power_up ("low"),
.sync_mode ("none"),
.use_clkn ("true")
) dqi_ddio_in (
.datain (dq_t1_delay_dataout),
.clk (dqs_enable),
.clkn (dqsn_enable),
.ena (1'b1),
.areset (1'b0),
.sreset (),
.regoutlo (dqi_captured_l),
.regouthi (dqi_captured_h),
.dfflo (),
.devclrn (),
.devpor ()
);
end
else
begin : ddr_dq_ddio_in_gen
// Capture DQ read data
stratixiii_ddio_in # (
.async_mode ("clear"),
.power_up ("low"),
.sync_mode ("none"),
.use_clkn ("false")
) dqi_ddio_in (
.datain (dq_t1_delay_dataout),
.clk (~dqs_enable),
.clkn (),
.ena (1'b1),
.areset (1'b0),
.sreset (),
.regoutlo (dqi_captured_l),
.regouthi (dqi_captured_h),
.dfflo (),
.devclrn (),
.devpor ()
);
end
endgenerate
// The input phase align atoms on the DQ input path should have "use_phasectrlin"
// set to FALSE and "bypass_output_register" set to TRUE for DDR/DDR2 :
generate
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2" || (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 0))
begin : ddr_ipa_gen
// Resynchronize captured read data
// Note : delay_buffer_mode for input_phase_alignment atoms must always
// be tied to "high" :
stratixiii_input_phase_alignment # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.add_input_cycle_delay ("false"),
.bypass_output_register ("true"),
.add_phase_transfer_reg ("false"),
.invert_phase ("false")
) dqi_ipa_h (
.datain (dqi_captured_h),
.clk (resync_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (resyncinputphasesetting),
.areset (1'b0),
.enainputcycledelay (enainputcycledelaysetting),
.enaphasetransferreg (enainputphasetransferreg),
.phaseinvertctrl (resyncinputphaseinvert),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
.dff1t (),
// synopsys translate_on
.dataout (dqi_aligned_h)
);
// Note : delay_buffer_mode for input_phase_alignment atoms must always
// be tied to "high" :
stratixiii_input_phase_alignment # (
.use_phasectrlin ("false"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.add_input_cycle_delay ("false"),
.bypass_output_register ("true"),
.add_phase_transfer_reg ("false"),
.invert_phase ("false")
) dqi_ipa_l (
.datain (dqi_captured_l),
.clk (resync_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (resyncinputphasesetting),
.areset (1'b0),
.enainputcycledelay (enainputcycledelaysetting),
.enaphasetransferreg (enainputphasetransferreg),
.phaseinvertctrl (resyncinputphaseinvert),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
.dff1t (),
// synopsys translate_on
.dataout (dqi_aligned_l)
);
end
else if (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1)
begin : ddr3_ipa_gen
// Resynchronize captured read data
// Note : delay_buffer_mode for input_phase_alignment atoms must always
// be tied to "high" :
stratixiii_input_phase_alignment # (
.use_phasectrlin ("true"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.add_input_cycle_delay ("dynamic"), //dynamic
.bypass_output_register ("false"),
.add_phase_transfer_reg ("dynamic"),
.invert_phase ("dynamic")
) dqi_ipa_h (
.datain (dqi_captured_h),
.clk (resync_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (resyncinputphasesetting),
.areset (1'b0),
.enainputcycledelay (enainputcycledelaysetting),
.enaphasetransferreg (enainputphasetransferreg),
.phaseinvertctrl (resyncinputphaseinvert),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
.dff1t (),
// synopsys translate_on
.dataout (dqi_aligned_h)
);
// Note : delay_buffer_mode for input_phase_alignment atoms must always
// be tied to "high" :
stratixiii_input_phase_alignment # (
.use_phasectrlin ("true"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.add_input_cycle_delay ("dynamic"), //dynamic
.bypass_output_register ("false"),
.add_phase_transfer_reg ("dynamic"),
.invert_phase ("dynamic")
) dqi_ipa_l (
.datain (dqi_captured_l),
.clk (resync_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (resyncinputphasesetting),
.areset (1'b0),
.enainputcycledelay (enainputcycledelaysetting),
.enaphasetransferreg (enainputphasetransferreg),
.phaseinvertctrl (resyncinputphaseinvert),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
.dff1t (),
// synopsys translate_on
.dataout (dqi_aligned_l)
);
end
else // QDR-II has no input phase alignment :
begin : qdr_no_ipa_gen
assign dqi_aligned_l = dqi_captured_l;
assign dqi_aligned_h = dqi_captured_h;
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_dqi_gen
if ((MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1) && ((ENABLE_DDR3_SEQUENCER === "TRUE") || (ENABLE_DDR3_SEQUENCER === "true")))
begin : gen_hri_with_dataoutbypass
stratixiii_half_rate_input # (
.power_up ("low"),
.async_mode ("none"),
.use_dataoutbypass ("true")
) dqi_hrate(
.datain ({dqi_aligned_h,dqi_aligned_l}),
.directin (dq_output_ibuf),
.clk (resync_clk_1x),
.areset (),
.dataoutbypass (enadataoutbypass),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dataout ({dio_rdata3_1x, dio_rdata2_1x, dio_rdata1_1x, dio_rdata0_1x})
);
end
// For DDR and QDRII dataoutpypass for write levelling is not required :
else
begin : gen_hri_no_dataoutbypass
stratixiii_half_rate_input # (
.power_up ("low"),
.async_mode ("none"),
.use_dataoutbypass ("false")
) dqi_hrate(
.datain ({dqi_aligned_h,dqi_aligned_l}),
.directin (dq_output_ibuf),
.clk (resync_clk_1x),
.areset (),
.dataoutbypass (enadataoutbypass),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dataout ({dio_rdata3_1x, dio_rdata2_1x, dio_rdata1_1x, dio_rdata0_1x})
);
end
end
else
begin : full_rate_dqi_gen
assign dio_rdata0_1x = dqi_aligned_l;
assign dio_rdata1_1x = dqi_aligned_h;
end
endgenerate
generate
// QDR has unidirectional data :
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_io_config_gen
// IO_CONFIG - num_dq 0->16
stratixiii_io_config d_io_config(
.datain (scan_din), // shared per DQS group
.clk (sc_clk),
.ena (scan_enable),
.update (scan_update), // shared per DQS group
// synopsys translate_off
.devclrn(), .devpor(),
.dutycycledelaymode(),
.dutycycledelaysettings(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.padtoinputregisterfinedelaysetting(),
// synopsys translate_on
.padtoinputregisterdelaysetting(),
.outputdelaysetting1 (dq_outputdelaysetting1),
.outputdelaysetting2 (dq_outputdelaysetting2),
.dataout ()
);
// IO_CONFIG - num_dq 0->16
stratixiii_io_config dq_io_config(
.datain (scan_din), // shared per DQS group
.clk (sc_clk),
.ena (scan_enable),
.update (scan_update), // shared per DQS group
// synopsys translate_off
.devclrn(), .devpor(),
.dutycycledelaymode(),
.dutycycledelaysettings(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.padtoinputregisterfinedelaysetting(),
// synopsys translate_on
.padtoinputregisterdelaysetting(dq_padtoinputregisterdelaysetting),
.outputdelaysetting1 (),
.outputdelaysetting2 (),
.dataout ()
);
end
// For DDR memories, where there is only 1 DQ pin per IO channel, use one IO config block :
else
begin : ddr_io_config_gen
// IO_CONFIG - num_dq 0->16
stratixiii_io_config dq_io_config(
.datain (scan_din), // shared per DQS group
.clk (sc_clk),
.ena (scan_enable),
.update (scan_update), // shared per DQS group
// synopsys translate_off
.devclrn(), .devpor(),
.dutycycledelaymode(),
.dutycycledelaysettings(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.padtoinputregisterfinedelaysetting(),
// synopsys translate_on
.padtoinputregisterdelaysetting(dq_padtoinputregisterdelaysetting),
.outputdelaysetting1 (dq_outputdelaysetting1),
.outputdelaysetting2 (dq_outputdelaysetting2),
.dataout (scan_dout)
);
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_clk_reset (
pll_ref_clk,
global_reset_n,
soft_reset_n,
seq_rdp_reset_req_n,
seq_qdr_doff_req_n,
resync_clk_1x,
ac_clk_1x,
measure_clk_1x,
mem_clk_2x,
mem_clk,
mem_clk_n,
phy_clk_1x,
postamble_clk_2x,
resync_clk_2x,
cs_n_clk_1x,
write_clk_2x,
aux_clk,
scan_clk,
aux_scan_clk_reset_n, // Connection New for 9.0
scan_clk_in,
scan_enable_ck,
scan_update,
scan_din,
reset_ac_clk_1x_n,
reset_measure_clk_1x_n,
reset_mem_clk_2x_n,
reset_phy_clk_1x_n,
reset_rdp_phy_clk_1x_n,
reset_resync_clk_1x_n,
reset_resync_clk_2x_n,
reset_write_clk_2x_n,
reset_cs_n_clk_1x_n,
mem_reset_n,
mem_doff_n,
reset_request_n, // new output
dqs_delay_ctrl,
dqs_delay_ctrl_import,
dqs_delay_update_en,
dlloffset_addnsub,
dlloffset_offset,
dlloffset_offsetctrl_out,
phs_shft_busy,
seq_pll_inc_dec_n,
seq_pll_select,
seq_pll_start_reconfig,
mimic_data_1x,
seq_clk_disable,
ctrl_clk_disable,
pll_reconfig_enable, // Connection New for 9.0
pll_phasecounterselect, // Connection New for 9.0
pll_phaseupdown, // Connection New for 9.0
pll_phasestep, // Connection New for 9.0
pll_phase_done // Connection New for 9.0
) /* synthesis altera_attribute=" SUPPRESS_DA_RULE_INTERNAL=\"R101,C104,C106\" ; AUTO_GLOBAL_REGISTER_CONTROLS=\"OFF\" "*/;
// Note the peculiar ranging below is necessary to use a generated CASE statement
// later in the code :
parameter AC_PHASE = "MEM_CLK";
parameter CLOCK_INDEX_WIDTH = 3;
parameter DDR_MIMIC_PATH_EN = 1; // Only applicable for QDRII
parameter DLL_EXPORT_IMPORT = "NONE";
parameter LOCAL_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_MEMTYPE = "DDR";
parameter LEVELLING = 1;
parameter READ_DESKEW_MODE = "NONE";
parameter WRITE_DESKEW_MODE = "NONE";
parameter MEM_IF_DQSN_EN = 1;
parameter MIF_FILENAME = "PLL.MIF";
parameter DWIDTH_RATIO = 4;
parameter PLL_EXPORT_IMPORT = "NONE";
parameter PLL_REF_CLK_PS = 4000;
parameter PLL_TYPE = "ENHANCED";
parameter SPEED_GRADE = "C3";
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 72;
parameter SCAN_CLK_DIVIDE_BY = 2;
parameter USE_MEM_CLK_FOR_ADDR_CMD_CLK = 1;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter USE_DLL_OFFSET = "false";
parameter PLL_RECONFIG_PORTS_EN = 0;
localparam RDP_RESET_PIPE_DEPTH = (MEM_IF_MEMTYPE == "QDRII") ? 1 : 3;
// Clock/reset inputs :
input global_reset_n;
input wire soft_reset_n;
input wire pll_ref_clk;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_reset_req_n;
input wire seq_qdr_doff_req_n;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] resync_clk_1x; //NB. Input!
// Clock/reset outputs :
output ac_clk_1x;
output measure_clk_1x;
output mem_clk_2x;
inout [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
output phy_clk_1x;
output postamble_clk_2x;
output resync_clk_2x;
output cs_n_clk_1x;
output write_clk_2x;
// The Aux clk shall be half-rate for full-rate mode and visa versa :
output aux_clk;
output wire reset_ac_clk_1x_n;
output wire reset_measure_clk_1x_n;
output wire reset_mem_clk_2x_n;
output reg reset_phy_clk_1x_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_rdp_phy_clk_1x_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_resync_clk_1x_n;
output wire reset_resync_clk_2x_n;
output wire reset_write_clk_2x_n;
output wire reset_cs_n_clk_1x_n;
output wire mem_reset_n;
output wire mem_doff_n;
// This is the PLL locked signal :
output wire reset_request_n;
// Misc I/O :
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl;
// For DDR3 only, when using an external DLL we need to import the code for the
// mem_clk output phase align block :
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_import;
output wire dqs_delay_update_en;
// Note - although the DLL offset signals are present here, use of an offset when
// in "internal" DLL mode is unsupported (and would therefore prevent hardcopy migration).
// Customers requiring DLL offsets should use "external" DLL mode, as this is the
// supported flow :
input wire dlloffset_addnsub; // Do not use
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offset; // Do not use
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offsetctrl_out; // Do not use
output wire phs_shft_busy;
input wire seq_pll_inc_dec_n;
input wire [CLOCK_INDEX_WIDTH - 1 : 0 ] seq_pll_select;
input wire seq_pll_start_reconfig;
output wire mimic_data_1x;
// Create the scan clock. This is a divided-down version of the PLL reference clock.
// The scan chain will have an Fmax of around 100MHz, and so initially the scan clock is
// created by a divide-by 4 circuit to allow plenty of margin with the expected reference
// clock frequency of 100MHz. This may be changed via the parameter.
output scan_clk;
output aux_scan_clk_reset_n;
localparam MEM_IF_STR_T9_DESKEW_EN = 0;
localparam MEM_IF_STR_T10_DESKEW_EN = 0;//uses_dekew_delay(MEM_IF_MEMTYPE, LEVELLING, WRITE_DESKEW_MODE);
input wire scan_clk_in;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_din;
input wire scan_update;
input wire seq_clk_disable;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctrl_clk_disable;
// PLL reconfig interface. Made available primarily for HardCopy customers :
input wire pll_reconfig_enable; // New for 9.0 - tie low if not required.
input wire [3:0] pll_phasecounterselect; // New for 9.0 - tie low if not required.
input wire pll_phaseupdown; // New for 9.0 - tie low if not required.
input wire pll_phasestep; // New for 9.0 - tie low if not required.
output wire pll_phase_done; // New for 9.0
wire global_reset_n;
(* keep, altera_attribute = "-name global_signal off" *) reg scan_clk = 1'b0;
(* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire mem_clk_2x;
(* keep, altera_attribute = "-name global_signal global_clock" *) wire phy_clk_1x;
wire aux_clk;
wire postamble_clk_2x;
(* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire resync_clk_2x;
(* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire write_clk_2x;
wire cs_n_clk_1x;
(* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire ac_clk_1x;
(* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire measure_clk_1x;
(* keep, altera_attribute = "-name global_signal off" *) wire phy_internal_reset_n;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
reg [2:0] divider = 3'h0;
(*preserve*) reg seq_pll_start_reconfig_ams;
(*preserve*) reg seq_pll_start_reconfig_r;
(*preserve*) reg seq_pll_start_reconfig_2r;
(*preserve*) reg seq_pll_start_reconfig_3r;
reg pll_new_dir;
reg [CLOCK_INDEX_WIDTH - 1 : 0 ] pll_new_phase;
wire pll_phase_auto_calibrate_pulse;
(*preserve*) reg pll_reprogram_request;
wire pll_locked_src;
reg pll_locked;
(*preserve*) reg pll_reprogram_request_pulse; // 1 scan clk cycle long
(*preserve*) reg pll_reprogram_request_pulse_r;
(*preserve*) reg pll_reprogram_request_pulse_2r;
wire pll_reprogram_request_long_pulse; // 3 scan clk cycles long
(*preserve*) reg reset_master_ams;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_pdiff_in;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_buf_in;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n_buf_in;
reg phs_shft_busy_siii;
(*preserve*) reg [2:0] seq_pll_start_reconfig_ccd_pipe;
(*preserve*) reg seq_pll_inc_dec_ccd;
(*preserve*) reg [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select_ccd ;
(*preserve*) reg global_pre_clear;
wire global_or_soft_reset_n;
(*preserve*) reg clk_div_reset_ams_n = 1'b0;
(*preserve*) reg clk_div_reset_ams_n_r = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n_r = 1'b0;
wire clk_divider_reset_n;
wire qdr_doff_req_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] rdp_reset_req_n;
wire pll_reset;
wire fb_clk;
wire pll_reconfig_reset_n;
wire master_reset_resync_clk_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_resync_clk_1x_pre_clear;
wire dll_offset_delay_ctrl_clk;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0] dll_offset_delay_code;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_pdiff_in_delayed1;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_pdiff_in_delayed2;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING1_WIDTH-1:0] outputdelaysetting1[MEM_IF_CLK_PAIR_COUNT - 1 : 0];
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING2_WIDTH-1:0] outputdelaysetting2[MEM_IF_CLK_PAIR_COUNT - 1 : 0];
// Hc-x requires access to the PLL phase stepping inputs, therefore they are multiplexed :
reg [3:0] muxed_pll_phasecounterselect;
reg muxed_pll_phasestep;
reg muxed_pll_phaseupdown;
wire pll_reconfig_enable_internal;
genvar dqs_group;
function integer uses_dekew_delay (input [31:0] mem_type,
input levelling,
input [31:0] mode);
begin
if (((mem_type == "DDR3") || (mem_type == "ddr3")) && levelling == 1 && ((mode != "NONE") && (mode != "none")))
uses_dekew_delay = 1;
else
uses_dekew_delay = 0;
end
endfunction
// Output the PLL locked signal to be used as a reset_request_n - IE. reset when the PLL loses
// lock :
assign reset_request_n = pll_locked;
// Reset the scanclk clock divider if we either have a global_reset or the PLL loses lock
assign pll_reconfig_reset_n = global_reset_n && pll_locked;
// Delayed and re-synchronised to scan clk, reset output for external PLL reconfiguration users :
assign aux_scan_clk_reset_n = pll_reconfig_reset_ams_n_r;
// Clock divider circuit reset generation.
always @(posedge phy_clk_1x or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
clk_div_reset_ams_n <= 1'b0;
clk_div_reset_ams_n_r <= 1'b0;
end
else
begin
clk_div_reset_ams_n <= 1'b1;
clk_div_reset_ams_n_r <= clk_div_reset_ams_n;
end
end
// PLL reconfig and synchronisation circuit reset generation.
always @(posedge scan_clk or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
pll_reconfig_reset_ams_n <= 1'b0;
pll_reconfig_reset_ams_n_r <= 1'b0;
end
else
begin
pll_reconfig_reset_ams_n <= 1'b1;
pll_reconfig_reset_ams_n_r <= pll_reconfig_reset_ams_n;
end
end
// Create the scan clock. Used for PLL reconfiguring in this block.
// Clock divider reset is the direct output of the AMS flops :
assign clk_divider_reset_n = clk_div_reset_ams_n_r;
generate
if (SCAN_CLK_DIVIDE_BY == 1)
begin : no_scan_clk_divider
always @(phy_clk_1x)
begin
scan_clk = phy_clk_1x;
end
end
else
begin : gen_scan_clk
always @(posedge phy_clk_1x or negedge clk_divider_reset_n)
begin
if (clk_divider_reset_n == 1'b0)
begin
scan_clk <= 1'b0;
divider <= 3'h0;
end
else
begin
// This method of clock division does not require "divider" to be used
// as an intermediate clock:
if (divider == (SCAN_CLK_DIVIDE_BY / 2 - 1))
begin
scan_clk <= ~scan_clk; // Toggle
divider <= 3'h0;
end
else
begin
scan_clk <= scan_clk; // Do not toggle
divider <= divider + 3'h1;
end
end
end
end
endgenerate
// NB. This lookup_sii table shall be different for CIII/SIII
function [3:0] lookup_siii;
input [CLOCK_INDEX_WIDTH-1:0] seq_num;
begin
casez (seq_num)
4'b0000 : lookup_siii = 4'b0010; // Legal code
4'b0001 : lookup_siii = 4'b0011; // Legal code
4'b0010 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b0011 : lookup_siii = 4'b0101; // Legal code
4'b0100 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b0101 : lookup_siii = 4'b0110; // Legal code
4'b0110 : lookup_siii = 4'b1000; // Legal code
4'b0111 : lookup_siii = 4'b0111; // Legal code
4'b1000 : lookup_siii = 4'b0100; // Legal code
4'b1001 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b1010 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b1011 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b1100 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b1101 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b1110 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
4'b1111 : lookup_siii = 4'b1111; // illegal - return code 4'b1111
default : lookup_siii = 4'bxxxx; // X propagation
endcase
end
endfunction
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_pll_inc_dec_ccd <= 1'b0;
seq_pll_select_ccd <= {CLOCK_INDEX_WIDTH{1'b0}};
seq_pll_start_reconfig_ccd_pipe <= 3'b000;
end
// Generate 'ccd' Cross Clock Domain signals :
else
begin
seq_pll_start_reconfig_ccd_pipe <= {seq_pll_start_reconfig_ccd_pipe[1:0], seq_pll_start_reconfig};
if (seq_pll_start_reconfig == 1'b1 && seq_pll_start_reconfig_ccd_pipe[0] == 1'b0)
begin
seq_pll_inc_dec_ccd <= seq_pll_inc_dec_n;
seq_pll_select_ccd <= seq_pll_select;
end
end
end
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
seq_pll_start_reconfig_ams <= 1'b0;
seq_pll_start_reconfig_r <= 1'b0;
seq_pll_start_reconfig_2r <= 1'b0;
seq_pll_start_reconfig_3r <= 1'b0;
pll_reprogram_request_pulse <= 1'b0;
pll_reprogram_request_pulse_r <= 1'b0;
pll_reprogram_request_pulse_2r <= 1'b0;
pll_reprogram_request <= 1'b0;
end
else
begin
seq_pll_start_reconfig_ams <= seq_pll_start_reconfig_ccd_pipe[2];
seq_pll_start_reconfig_r <= seq_pll_start_reconfig_ams;
seq_pll_start_reconfig_2r <= seq_pll_start_reconfig_r;
seq_pll_start_reconfig_3r <= seq_pll_start_reconfig_2r;
pll_reprogram_request_pulse <= pll_phase_auto_calibrate_pulse;
pll_reprogram_request_pulse_r <= pll_reprogram_request_pulse;
pll_reprogram_request_pulse_2r <= pll_reprogram_request_pulse_r;
pll_reprogram_request <= pll_reprogram_request_long_pulse;
end
end
// Rising-edge detect to generate a single phase shift step
assign pll_phase_auto_calibrate_pulse = ~seq_pll_start_reconfig_3r && seq_pll_start_reconfig_2r;
// extend the phase shift request pulse to be 3 scan clk cycles long.
assign pll_reprogram_request_long_pulse = pll_reprogram_request_pulse || pll_reprogram_request_pulse_r || pll_reprogram_request_pulse_2r;
// Register the Phase step settings
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
pll_new_dir <= 1'b0;
pll_new_phase <= 'h0;
end
else
begin
if (pll_phase_auto_calibrate_pulse)
begin
pll_new_dir <= seq_pll_inc_dec_ccd;
pll_new_phase <= seq_pll_select_ccd;
end
end
end
// generate the busy signal - just the inverse of the done o/p from the pll, and stretched ,
//as the initial pulse might not be long enough to be catched by the sequencer
//the same circuitry in the ciii clock and reset block
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
phs_shft_busy_siii <= 1'b0;
else
phs_shft_busy_siii <= pll_reprogram_request || ~pll_phase_done;
end
assign phs_shft_busy = phs_shft_busy_siii;
// Gate the soft reset input (from SOPC builder for example) with the PLL
// locked signal :
assign global_or_soft_reset_n = soft_reset_n && global_reset_n;
// Create the PHY internal reset signal :
assign phy_internal_reset_n = pll_locked && global_or_soft_reset_n;
// The PLL resets only on a global reset :
assign pll_reset = !global_reset_n;
// If PLL reconfig ports are present, create the reconfig mux :
generate
// Half-rate mode :
if (PLL_RECONFIG_PORTS_EN == 1)
assign pll_reconfig_enable_internal = pll_reconfig_enable;
else
assign pll_reconfig_enable_internal = 1'b0;
endgenerate
always @*
begin
if (pll_reconfig_enable_internal == 1'b0)
begin
muxed_pll_phasecounterselect = lookup_siii(pll_new_phase);
muxed_pll_phasestep = pll_reprogram_request;
muxed_pll_phaseupdown = pll_new_dir;
end
else
begin
muxed_pll_phasecounterselect = pll_phasecounterselect;
muxed_pll_phasestep = pll_phasestep;
muxed_pll_phaseupdown = pll_phaseupdown;
end
end
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin : half_rate
//
ddr3_s4_amphy_phy_alt_mem_phy_pll pll (
.inclk0 (pll_ref_clk),
.areset (pll_reset),
.c0 (phy_clk_1x), // hR
.c1 (mem_clk_2x), // FR
.c2 (aux_clk), // FR
.c3 (write_clk_2x), // FR
.c4 (resync_clk_2x), // FR
.c5 (measure_clk_1x), // hR
.c6 (ac_clk_1x), // hR
.phasecounterselect (muxed_pll_phasecounterselect),
.phasestep (muxed_pll_phasestep),
.phaseupdown (muxed_pll_phaseupdown),
.scanclk (scan_clk),
.locked (pll_locked_src),
.phasedone (pll_phase_done)
);
end
// Full-rate mode :
else
begin : full_rate
//
ddr3_s4_amphy_phy_alt_mem_phy_pll pll (
.inclk0 (pll_ref_clk),
.areset (pll_reset),
.c0 (aux_clk), // hR
.c1 (mem_clk_2x), // FR
.c2 (phy_clk_1x), // FR
.c3 (write_clk_2x), // FR
.c4 (resync_clk_2x), // FR
.c5 (measure_clk_1x), // hR
.c6 (ac_clk_1x), // hR
.phasecounterselect (muxed_pll_phasecounterselect),
.phasestep (muxed_pll_phasestep),
.phaseupdown (muxed_pll_phaseupdown),
.scanclk (scan_clk),
.locked (pll_locked_src),
.phasedone (pll_phase_done)
);
end
endgenerate
//synopsys translate_off
reg [19:0] pll_locked_chain = 20'h0;
always @(posedge pll_ref_clk)
begin
pll_locked_chain <= {pll_locked_chain[18:0],pll_locked_src};
end
//synopsys translate_on
always @*
begin
pll_locked = pll_locked_src;
//synopsys translate_off
pll_locked = pll_locked_chain[19];
//synopsys translate_on
end
assign cs_n_clk_1x = ac_clk_1x;
// The postamble clock is the inverse of the resync clock
assign postamble_clk_2x = ~resync_clk_2x;
generate
genvar clk_pair;
for (clk_pair = 0 ; clk_pair < MEM_IF_CLK_PAIR_COUNT; clk_pair = clk_pair + 1)
begin : DDR_CLK_OUT
// For DDR/DDR2 use DDIO :
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2" || MEM_IF_MEMTYPE == "QDRII" || (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 0))
begin : ddio_memclk_gen
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
) mem_clk_ddio (
.datainlo (1'b0),
.datainhi (~seq_clk_disable && ~ctrl_clk_disable[clk_pair]),
.clkhi (mem_clk_2x),
.clklo (mem_clk_2x),
.muxsel (mem_clk_2x),
.clk (),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
.dataout (mem_clk_pdiff_in[clk_pair]),
.dfflo (),
.dffhi (),
.devpor (),
.devclrn ()
);
end
// For DDR3 use a phase align atom :
else
begin : phase_align_memclk_gen
wire ck_h;
wire ck_l;
wire ck_n_h;
wire ck_n_l;
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) mem_clk_hr_ddio_h(
.datainhi (~seq_clk_disable && ~ctrl_clk_disable[clk_pair]),
.datainlo (~seq_clk_disable && ~ctrl_clk_disable[clk_pair]),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (ck_h),
.devclrn(),
.devpor()
);
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) mem_clk_hr_ddio_l(
.datainhi (1'b0),
.datainlo (1'b0),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (ck_l),
.devclrn(),
.devpor()
);
// Note : delay_buffer_mode for output_phase_alignment atoms must always
// be tied to "high" :
stratixiii_output_phase_alignment # (
.operation_mode ("ddio_out"),
.use_phasectrlin ("false"),
.phase_setting (2),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.sync_mode ("none"),
.add_output_cycle_delay ("false"),
.use_delayed_clock ("false"),
.phase_setting_for_delayed_clock (2),
.add_phase_transfer_reg ("true"),
.use_phasectrl_clock ("false"),
.invert_phase ("false"),
.use_primary_clock ("true"),
.bypass_input_register ("false")
) mem_clk_opa (
.datain ({ck_h, ck_l}),
.clk (write_clk_2x),
.delayctrlin ((DLL_EXPORT_IMPORT == "IMPORT") ? dqs_delay_ctrl_import : dqs_delay_ctrl),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.phaseinvertctrl (),
.enaphasetransferreg (),
.enaoutputcycledelay (),
.phasectrlin (),
// synopsys translate_off
.devclrn(), .devpor(),
.dffin(), .dff1t(), .dffddiodataout(),
// synopsys translate_on
.dataout (mem_clk_pdiff_in[clk_pair])
);
end
if (MEM_IF_STR_T9_DESKEW_EN == 1)
begin : gen_T9
stratixiii_delay_chain o_pa_dc1(
.datain (mem_clk_pdiff_in[clk_pair]),
.delayctrlin (outputdelaysetting1[clk_pair]),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (mem_clk_pdiff_in_delayed1[clk_pair])
);
end
else
begin : gen_no_T9
assign mem_clk_pdiff_in_delayed1[clk_pair] = mem_clk_pdiff_in[clk_pair];
end
if (MEM_IF_STR_T10_DESKEW_EN == 1)
begin : gen_T10_dqs_deskew
stratixiii_delay_chain o_pa_dc2(
.datain (mem_clk_pdiff_in_delayed1[clk_pair]),
.delayctrlin ({1'b0, outputdelaysetting2[clk_pair]}),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (mem_clk_pdiff_in_delayed2[clk_pair])
);
end
else
begin : gen_no_T10
assign mem_clk_pdiff_in_delayed2[clk_pair] = mem_clk_pdiff_in_delayed1[clk_pair];
end
// Pseudo-diff used to ensure fanout of 1 from OPA/DDIO_OUT atoms :
stratixiii_pseudo_diff_out mem_clk_pdiff (
.i (mem_clk_pdiff_in_delayed2[clk_pair]),
.o ( mem_clk_buf_in[clk_pair]),
.obar (mem_clk_n_buf_in[clk_pair])
);
// The same output buf is for both DDR2 and 3 :
stratixiii_io_obuf # (
.bus_hold("false"),
.open_drain_output("false"),
.shift_series_termination_control("false")
) mem_clk_obuf (
.i (mem_clk_buf_in[clk_pair]),
.oe (1'b1),
.dynamicterminationcontrol (1'b0),
// synopsys translate_off
.seriesterminationcontrol(),
.parallelterminationcontrol(),
.obar(),
// synopsys translate_on
.o(mem_clk[clk_pair]),
.devoe()
);
// The same output buf is used
stratixiii_io_obuf # (
.bus_hold("false"),
.open_drain_output("false"),
.shift_series_termination_control("false")
) mem_clk_n_obuf (
.i (mem_clk_n_buf_in[clk_pair]),
.oe (1'b1),
.dynamicterminationcontrol (1'b0),
// synopsys translate_off
.seriesterminationcontrol(),
.parallelterminationcontrol(),
.obar(),
// synopsys translate_on
.o(mem_clk_n[clk_pair]),
.devoe()
);
// IO CONFIG.
stratixiii_io_config io_config(
.datain(scan_din[clk_pair]),
.clk(scan_clk_in),
.ena(scan_enable_ck[clk_pair]),
.update(scan_update),
// synopsys translate_off
.devclrn(), .devpor(),
.dutycycledelaymode(),
.dutycycledelaysettings(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.padtoinputregisterfinedelaysetting(),
// synopsys translate_on
.padtoinputregisterdelaysetting(),
.outputdelaysetting1(outputdelaysetting1[clk_pair]),
.outputdelaysetting2(outputdelaysetting2[clk_pair]),
.dataout()
);
end //for
endgenerate
// Mimic path - connect an input buffer to the pad. Choose mem_clk[0] as
// this shall always be implemented :
generate
// Mimic clock generation should be differential or single-ended dependant upon DQS usage :
if (MEM_IF_MEMTYPE == "QDRII" || MEM_IF_MEMTYPE == "DDR" || (MEM_IF_MEMTYPE == "DDR2" && (MEM_IF_DQSN_EN == 0)) )
begin : gen_mimic_se_ibuf
stratixiii_io_ibuf fb_clk_ibuf(
.i (mem_clk[0]),
// synopsys translate_off
.ibar(),
.dynamicterminationcontrol(),
// synopsys translate_on
.o (fb_clk)
);
end
// For DDR3 and DDR2 with DQSN, use a differential I/O :
else
begin : gen_mimic_diff_ibuf
stratixiii_io_ibuf fb_clk_ibuf(
.i (mem_clk[0]),
.ibar (mem_clk_n[0]),
// synopsys translate_off
.dynamicterminationcontrol(),
// synopsys translate_on
.o (fb_clk)
);
end
endgenerate
// DDR2 Mimic Path Generation - in effect this is just a register :
stratixiii_ddio_in ddio_mimic(
.datain (fb_clk),
.clk (measure_clk_1x),
.clkn (),
// synopsys translate_off
.devclrn(),
.devpor(),
// synopsys translate_on
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
.regoutlo (),
.regouthi (mimic_data_1x),
.dfflo ()
);
generate
if (DLL_EXPORT_IMPORT != "IMPORT")
begin
// Note : delay_buffer_mode for the dll atoms may be either 'high' or 'low', so it is
// correct to propagate the DLL_DELAY_BUFFER_MODE parameter here :
stratixiii_dll # (
.input_frequency (MEM_IF_CLK_PS_STR),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.delay_chain_length (DLL_DELAY_CHAIN_LENGTH),
.delayctrlout_mode ("normal"),
.jitter_reduction ("true"),
.sim_valid_lock (1280),
.sim_low_buffer_intrinsic_delay (350),
.sim_high_buffer_intrinsic_delay (175),
.sim_buffer_delay_increment (10),
.static_delay_ctrl (0),
.lpm_type ("stratixiii_dll")
) dll(
.clk (mem_clk_2x),
.aload (~pll_locked),
.delayctrlout (dqs_delay_ctrl),
.upndnout (),
.dqsupdate (dqs_delay_update_en),
.offsetdelayctrlclkout (dll_offset_delay_ctrl_clk),
.offsetdelayctrlout (dll_offset_delay_code),
.devpor (),
.devclrn (),
.upndninclkena (),
.upndnin ()
);
end
endgenerate
generate
if (USE_DLL_OFFSET =="true" || USE_DLL_OFFSET == "TRUE")
stratixiii_dll_offset_ctrl # (
.use_offset (USE_DLL_OFFSET),
.static_offset ("0"),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE)
) dll_phs_offset (
.clk (dll_offset_delay_ctrl_clk),
.aload (~pll_locked),
.offsetdelayctrlin (dll_offset_delay_code),
.offset (dlloffset_offset),
.addnsub (dlloffset_addnsub),
.devclrn (),
.devpor (),
.offsettestout (),
.offsetctrlout (dlloffset_offsetctrl_out)
);
else
assign dlloffset_offsetctrl_out = 6'b000000;
endgenerate
// Master reset generation :
always @(posedge phy_clk_1x or negedge phy_internal_reset_n)
begin
if (phy_internal_reset_n == 1'b0)
begin
reset_master_ams <= 1'b0;
global_pre_clear <= 1'b0;
end
else
begin
reset_master_ams <= 1'b1;
global_pre_clear <= reset_master_ams;
end
end
// phy_clk reset generation :
always @(posedge phy_clk_1x or negedge global_pre_clear)
begin
if (global_pre_clear == 1'b0)
begin
reset_phy_clk_1x_n <= 1'b0;
end
else
begin
reset_phy_clk_1x_n <= global_pre_clear;
end
end
generate
for (dqs_group = 0 ; dqs_group < MEM_IF_DQS_WIDTH; dqs_group = dqs_group + 1)
begin : RESET_RDP_BUS
assign rdp_reset_req_n[dqs_group] = seq_rdp_reset_req_n[dqs_group] && global_pre_clear ;
// phy_clk reset generation for read datapaths :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (RDP_RESET_PIPE_DEPTH) ) reset_rdp_phy_clk_pipe(
.clock (phy_clk_1x),
.pre_clear (rdp_reset_req_n[dqs_group]),
.reset_out (reset_rdp_phy_clk_1x_n[dqs_group])
);
end
endgenerate
// NB. phy_clk reset is generated above.
// Instantiate the reset pipes. The 4 reset signals below are family invariant
// whilst the other resets are generated on a per-family basis :
// mem_clk reset generation :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) mem_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (mem_reset_n)
);
// mem_clk_2x reset generation - required for SIII DDR/DDR2 support :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) mem_clk_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_mem_clk_2x_n)
);
// write_clk_2x reset generation :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) write_clk_pipe(
.clock (write_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_write_clk_2x_n)
);
// ac_clk_1x reset generation :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) ac_clk_pipe_1x(
.clock (ac_clk_1x),
.pre_clear (global_pre_clear),
.reset_out (reset_ac_clk_1x_n)
);
// cs_clk_2x reset generation :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) cs_n_clk_pipe_1x(
.clock (cs_n_clk_1x),
.pre_clear (global_pre_clear),
.reset_out (reset_cs_n_clk_1x_n)
);
// measure_clk_1x reset generation :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) measure_clk_pipe(
.clock (measure_clk_1x),
.pre_clear (global_pre_clear),
.reset_out (reset_measure_clk_1x_n)
);
// resync_clk_2x reset generation :
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (RDP_RESET_PIPE_DEPTH) ) resync_clk_2x_pipe(
.clock (resync_clk_2x),
.pre_clear (rdp_reset_req_n[0]),
.reset_out (reset_resync_clk_2x_n)
);
generate
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_doff_pipe_gen
assign qdr_doff_req_n = seq_qdr_doff_req_n && global_pre_clear ;
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) qdr_doff_pipe(
.clock (mem_clk_2x),
.pre_clear (qdr_doff_req_n),
.reset_out (mem_doff_n)
);
end
else
begin
assign mem_doff_n = 1'b0;
end
endgenerate
generate
for (dqs_group = 0 ; dqs_group < 1; dqs_group = dqs_group + 1)
begin : reset_resync_clk_pipe
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) resync_clk_pipe_1x(
.clock (resync_clk_1x[0]),
.pre_clear (rdp_reset_req_n[0]),
.reset_out (master_reset_resync_clk_1x)
);
end
endgenerate
// QDRII requires individual control of each DQS group reset, whilst DDR3 requires all groups to be synchronised to reset[0] :
assign reset_resync_clk_1x_pre_clear = (MEM_IF_MEMTYPE == "QDRII") ? rdp_reset_req_n : {MEM_IF_DQS_WIDTH{master_reset_resync_clk_1x}} ;
// resync_clk_1x reset generation. Note that the pre_clear is connected to the
// local read data path reset request signal, as these shall be reset when the
// sequencer requests :
generate
for (dqs_group = 0 ; dqs_group < MEM_IF_DQS_WIDTH; dqs_group = dqs_group + 1)
begin : slave_reset_resync_clk_pipe
//
ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) slave_resync_clk_pipe_1x(
.clock (resync_clk_1x[dqs_group]), // Choose one resync_clk from which to generate reset
.pre_clear (reset_resync_clk_1x_pre_clear[dqs_group]),
.reset_out (reset_resync_clk_1x_n[dqs_group])
);
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_postamble ( // inputs
phy_clk_1x,
resync_clk_1x,
reset_phy_clk_1x_n,
reset_resync_clk_1x_n,
seq_poa_lat_inc_1x,
seq_poa_lat_dec_1x,
seq_poa_protection_override_1x,
// for 2T / 2N addr/CMD drive both of these with the same value.
// (DWIDTH_RATIO/2 - 1 downto 0) (LSB represents first when changes ionto full-rate!
ctl_doing_rd_beat,
// outputs (DWIDTH_RATIO/2 - 1 downto 0)
poa_postamble_en_preset
);
parameter FAMILY = "STRATIXIII";
parameter POSTAMBLE_INITIAL_LAT = 13; //13 for SIII, 16 for SII/CIII
parameter POSTAMBLE_RESYNC_LAT_CTL_EN = 0; // 0 means false, 1 means true
parameter POSTAMBLE_AWIDTH = 6;
parameter POSTAMBLE_HALFT_EN = 0; // 0 means false, 1 means true
parameter MEM_IF_POSTAMBLE_EN_WIDTH = 8;
parameter DWIDTH_RATIO = 4;
// clocks
input wire phy_clk_1x;
input wire resync_clk_1x;
// resets
input wire reset_phy_clk_1x_n;
input wire reset_resync_clk_1x_n;
// control signals from sequencer
input wire seq_poa_lat_inc_1x;
input wire seq_poa_lat_dec_1x;
input wire seq_poa_protection_override_1x;
input wire [DWIDTH_RATIO/2 - 1 : 0] ctl_doing_rd_beat ;
// output to IOE for SIII :
output wire [DWIDTH_RATIO/2 - 1 : 0] poa_postamble_en_preset;
// internal wires/regs
reg [POSTAMBLE_AWIDTH - 1 : 0] rd_addr;
reg [POSTAMBLE_AWIDTH - 1 : 0] wr_addr;
reg [POSTAMBLE_AWIDTH - 1 : 0] next_wr_addr;
reg [DWIDTH_RATIO/2 - 1 : 0] wr_data;
wire wr_en;
reg sync_seq_poa_lat_inc_1x;
reg sync_seq_poa_lat_dec_1x;
reg seq_poa_lat_inc_1x_1t;
reg seq_poa_lat_dec_1x_1t;
// only for halfrate. --- also for Quarter_rate......
reg ctl_doing_rd_beat2_1x_r1;
wire [DWIDTH_RATIO/2 - 1 : 0] postamble_en;
reg bit_order_1x;
reg ams_inc;
reg ams_dec;
// loop variables
genvar i;
////////////////////////////////////////////////////////////////////////////////
// Generate Statements to synchronise controls if necessary
////////////////////////////////////////////////////////////////////////////////
generate
//begin
if (POSTAMBLE_RESYNC_LAT_CTL_EN == 0)
begin : sync_lat_controls
always @* // combinational logic sensitivity
begin
sync_seq_poa_lat_inc_1x = seq_poa_lat_inc_1x;
sync_seq_poa_lat_dec_1x = seq_poa_lat_dec_1x;
end
end
else
begin : resynch_lat_controls
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
sync_seq_poa_lat_inc_1x <= 1'b0;
sync_seq_poa_lat_dec_1x <= 1'b0;
ams_inc <= 1'b0;
ams_dec <= 1'b0;
end
else
begin
sync_seq_poa_lat_inc_1x <= ams_inc;
sync_seq_poa_lat_dec_1x <= ams_dec;
ams_inc <= seq_poa_lat_inc_1x;
ams_dec <= seq_poa_lat_dec_1x;
end
end
end
//end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// write address controller
////////////////////////////////////////////////////////////////////////////////
// override_postamble_protection is overide onto write data.
// otherwise use bit_order_1x to choose how word is written into RAM.
generate // based on DWIDTH RATIO...
//begin
if (DWIDTH_RATIO == 4) // Half Rate
begin : halfrate_wdata_gen
always @* // combinational logic sensitivity
begin
if (seq_poa_protection_override_1x == 1'b1)
begin
wr_data = `POA_OVERRIDE_VAL;
end
else if (bit_order_1x == 1'b0)
begin
wr_data = {ctl_doing_rd_beat[1], ctl_doing_rd_beat[0]};
end
else
begin
wr_data = {ctl_doing_rd_beat[0], ctl_doing_rd_beat2_1x_r1};
end
end
end
else // Full-rate
begin : fullrate_wdata_gen
always @* // combinational logic sensitivity
begin
if (seq_poa_protection_override_1x == 1'b1)
begin
wr_data = `POA_OVERRIDE_VAL_FULL_RATE;
end
else
begin
wr_data = ctl_doing_rd_beat;
end
end
end
//end
endgenerate
always @*
begin
next_wr_addr = wr_addr + 1'b1;
if (sync_seq_poa_lat_dec_1x == 1'b1 && seq_poa_lat_dec_1x_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr = wr_addr;
end
end
else if (sync_seq_poa_lat_inc_1x == 1'b1 && seq_poa_lat_inc_1x_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr = wr_addr + 2'h2;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr <= POSTAMBLE_INITIAL_LAT[POSTAMBLE_AWIDTH - 1 : 0];
end
else
begin
wr_addr <= next_wr_addr;
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_doing_rd_beat2_1x_r1 <= 1'b0;
seq_poa_lat_inc_1x_1t <= 1'b0;
seq_poa_lat_dec_1x_1t <= 1'b0;
bit_order_1x <= 1'b1; // 1'b0
end
else
begin
ctl_doing_rd_beat2_1x_r1 <= ctl_doing_rd_beat[DWIDTH_RATIO/2 - 1];
seq_poa_lat_inc_1x_1t <= sync_seq_poa_lat_inc_1x;
seq_poa_lat_dec_1x_1t <= sync_seq_poa_lat_dec_1x;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (sync_seq_poa_lat_dec_1x == 1'b1 && seq_poa_lat_dec_1x_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (sync_seq_poa_lat_inc_1x == 1'b1 && seq_poa_lat_inc_1x_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
///////////////////////////////////////////////////////////////////////////////////
// Instantiate the postamble dpram
///////////////////////////////////////////////////////////////////////////////////
assign wr_en = 1'b1; // tied high
// For StratixIII, the read and write sides are the same width :
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**POSTAMBLE_AWIDTH),
.numwords_b (2**POSTAMBLE_AWIDTH),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.ram_block_type ("MLAB"),
.widthad_a (POSTAMBLE_AWIDTH),
.widthad_b (POSTAMBLE_AWIDTH),
.width_a (DWIDTH_RATIO/2),
.width_b (DWIDTH_RATIO/2),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (wr_en),
.clock0 (phy_clk_1x),
.clock1 (resync_clk_1x),
.address_a (wr_addr),
.address_b (rd_addr),
.data_a (wr_data),
.q_b (postamble_en),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_b ({DWIDTH_RATIO/2{1'b1}}),
.q_a (),
.rden_b (1'b1),
.wren_b (1'b0),
.eccstatus (),
.clocken3 (),
.clocken2 (),
.rden_a ()
);
///////////////////////////////////////////////////////////////////////////////////
// read address generator : just a free running counter.
///////////////////////////////////////////////////////////////////////////////////
always @(posedge resync_clk_1x or negedge reset_resync_clk_1x_n)
begin
if (reset_resync_clk_1x_n == 1'b0)
begin
rd_addr <= {POSTAMBLE_AWIDTH{1'b0}};
end
else
begin
rd_addr <= rd_addr + 1'b1; //inc address, can wrap
end
end
assign poa_postamble_en_preset = postamble_en;
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_read_dp_group ( phy_clk_1x,
resync_clk_1x,
reset_phy_clk_1x_n,
reset_resync_clk_1x_n,
seq_rdp_dec_read_lat_1x,
seq_rdp_inc_read_lat_1x,
dio_rdata3_1x,
dio_rdata2_1x,
dio_rdata1_1x,
dio_rdata0_1x,
ctl_mem_rdata
);
parameter ADDR_COUNT_WIDTH = 4;
parameter BIDIR_DPINS = 1; // 0 for QDR only.
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_CLK_PS = 4000;
parameter FAMILY = "STRATIXII";
parameter MEM_IF_DQ_PER_DQS = 8;
parameter RDP_INITIAL_LAT = 6;
parameter RDP_RESYNC_LAT_CTL_EN = 0;
parameter RESYNC_PIPELINE_DEPTH = 1; // No pipelining in the FD spec.
input wire phy_clk_1x;
input wire resync_clk_1x;
input wire reset_phy_clk_1x_n;
input wire reset_resync_clk_1x_n;
input wire seq_rdp_dec_read_lat_1x;
input wire seq_rdp_inc_read_lat_1x;
input wire [MEM_IF_DQ_PER_DQS-1 : 0] dio_rdata0_1x;
input wire [MEM_IF_DQ_PER_DQS-1 : 0] dio_rdata1_1x;
input wire [MEM_IF_DQ_PER_DQS-1 : 0] dio_rdata2_1x;
input wire [MEM_IF_DQ_PER_DQS-1 : 0] dio_rdata3_1x;
output wire [DWIDTH_RATIO*MEM_IF_DQ_PER_DQS-1 : 0] ctl_mem_rdata;
// concatonated read data :
wire [(DWIDTH_RATIO*MEM_IF_DQ_PER_DQS)-1 : 0] dio_rdata;
reg [ADDR_COUNT_WIDTH - 1 : 0] rd_ram_rd_addr;
reg [ADDR_COUNT_WIDTH - 1 : 0] rd_ram_wr_addr;
reg inc_read_lat_sync_r;
reg dec_read_lat_sync_r;
// Optional AMS registers :
reg inc_read_lat_ams ;
reg inc_read_lat_sync;
reg dec_read_lat_ams ;
reg dec_read_lat_sync;
wire rd_addr_stall;
wire rd_addr_double_inc;
////////////////////////////////////////////////////////////////////////////////
// Write Address block
////////////////////////////////////////////////////////////////////////////////
always@ (posedge resync_clk_1x or negedge reset_resync_clk_1x_n)
begin
if (reset_resync_clk_1x_n == 0)
begin
rd_ram_wr_addr <= RDP_INITIAL_LAT[ADDR_COUNT_WIDTH - 1 : 0];
end
else
begin
rd_ram_wr_addr <= rd_ram_wr_addr + 1'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
// Pipeline registers
////////////////////////////////////////////////////////////////////////////////
// Concatenate the input read data :
generate
if (DWIDTH_RATIO ==4)
begin
assign dio_rdata = {dio_rdata3_1x, dio_rdata2_1x, dio_rdata1_1x, dio_rdata0_1x};
end
else
begin
assign dio_rdata = {dio_rdata1_1x, dio_rdata0_1x};
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Instantiate the read_dp dpram
////////////////////////////////////////////////////////////////////////////////
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**ADDR_COUNT_WIDTH),
.numwords_b (2**ADDR_COUNT_WIDTH),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.ram_block_type ("MLAB"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH),
.width_a (DWIDTH_RATIO*MEM_IF_DQ_PER_DQS),
.width_b (DWIDTH_RATIO*MEM_IF_DQ_PER_DQS),
.width_byteena_a (1)
)
ram (
.wren_a (1'b1),
.clock0 (resync_clk_1x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (dio_rdata),
.q_b (ctl_mem_rdata),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_b ({(DWIDTH_RATIO*MEM_IF_DQ_PER_DQS){1'b1}}),
.q_a (),
.rden_b (1'b1),
.wren_b (1'b0),
.eccstatus (),
.clocken3 (),
.clocken2 (),
.rden_a ()
);
////////////////////////////////////////////////////////////////////////////////
// Read Address block
////////////////////////////////////////////////////////////////////////////////
// Optional Anti-metastability flops :
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin : rd_addr_ams
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_ams <= 1'b0;
inc_read_lat_sync <= 1'b0;
inc_read_lat_sync_r <= 1'b0;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= 1'b0;
dec_read_lat_sync <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// Synchronise rd_lat_inc_1x :
inc_read_lat_ams <= seq_rdp_inc_read_lat_1x;
inc_read_lat_sync <= inc_read_lat_ams;
inc_read_lat_sync_r <= inc_read_lat_sync;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= seq_rdp_dec_read_lat_1x;
dec_read_lat_sync <= dec_read_lat_ams;
dec_read_lat_sync_r <= dec_read_lat_sync;
end
end // always
// No anti-metastability protection required :
else
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_sync_r <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// No need to re-synchronise, just register for edge detect :
inc_read_lat_sync_r <= seq_rdp_inc_read_lat_1x;
dec_read_lat_sync_r <= seq_rdp_dec_read_lat_1x;
end
end
endgenerate
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
begin : lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && inc_read_lat_sync;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && dec_read_lat_sync );
// 'stall' logic :
// assign rd_addr_stall = !( !dec_read_lat_sync_r && dec_read_lat_sync );
assign rd_addr_stall = !inc_read_lat_sync_r && inc_read_lat_sync;
end
else
begin : no_lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
// 'stall' logic :
//assign rd_addr_stall = !( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
assign rd_addr_stall = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
end
endgenerate
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 0)
begin
rd_ram_rd_addr <= { ADDR_COUNT_WIDTH {1'b0} };
end
else
begin
// RAM read address :
if (rd_addr_stall == 1'b0)
begin
rd_ram_rd_addr <= rd_ram_rd_addr + 1'b1 + rd_addr_double_inc;
end
end
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
`default_nettype none
//
module ddr3_s4_amphy_phy_alt_mem_phy_rdata_valid ( // inputs
phy_clk_1x,
reset_phy_clk_1x_n,
seq_rdata_valid_lat_dec,
seq_rdata_valid_lat_inc,
seq_doing_rd,
ctl_doing_rd,
ctl_cal_success,
// outputs
ctl_rdata_valid,
seq_rdata_valid
);
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_DQS_WIDTH = 8;
parameter RDATA_VALID_AWIDTH = 5;
parameter RDATA_VALID_INITIAL_LAT = 16;
parameter DWIDTH_RATIO = 2;
localparam MAX_RDATA_VALID_DELAY = 2 ** RDATA_VALID_AWIDTH;
localparam RDV_DELAY_SHR_LEN = MAX_RDATA_VALID_DELAY*(DWIDTH_RATIO/2);
// clocks
input wire phy_clk_1x;
// resets
input wire reset_phy_clk_1x_n;
// control signals from sequencer
input wire seq_rdata_valid_lat_dec;
input wire seq_rdata_valid_lat_inc;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] seq_doing_rd;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
input wire ctl_cal_success;
// output to IOE
output reg [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output reg [DWIDTH_RATIO / 2 -1 : 0] seq_rdata_valid;
// Internal Signals / Variables
reg [RDATA_VALID_AWIDTH - 1 : 0] rd_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] wr_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] next_wr_addr;
reg [DWIDTH_RATIO/2 - 1 : 0] wr_data;
wire [DWIDTH_RATIO / 2 -1 : 0] int_rdata_valid;
reg [DWIDTH_RATIO/2 - 1 : 0] rdv_pipe_ip;
reg rdv_pipe_ip_beat2_r;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
reg seq_rdata_valid_lat_dec_1t;
reg seq_rdata_valid_lat_inc_1t;
reg bit_order_1x;
// Generate the input to the RDV delay.
// Also determine the data for the OCT control & postamble paths (merged_doing_rd)
generate
if (DWIDTH_RATIO == 4)
begin : merging_doing_rd_halfrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & {(2 * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[ MEM_IF_DQS_WIDTH - 1 : 0];
rdv_pipe_ip[1] = | merged_doing_rd[2 * MEM_IF_DQS_WIDTH - 1 : MEM_IF_DQS_WIDTH];
end
end
else // DWIDTH_RATIO == 2
begin : merging_doing_rd_fullrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & { MEM_IF_DQS_WIDTH {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[MEM_IF_DQS_WIDTH - 1 : 0];
end
end // else: !if(DWIDTH_RATIO == 4)
endgenerate
// Register inc/dec rdata_valid signals and generate bit_order_1x
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_rdata_valid_lat_dec_1t <= 1'b0;
seq_rdata_valid_lat_inc_1t <= 1'b0;
bit_order_1x <= 1'b1;
end
else
begin
rdv_pipe_ip_beat2_r <= rdv_pipe_ip[DWIDTH_RATIO/2 - 1];
seq_rdata_valid_lat_dec_1t <= seq_rdata_valid_lat_dec;
seq_rdata_valid_lat_inc_1t <= seq_rdata_valid_lat_inc;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
// write data
generate // based on DWIDTH RATIO
if (DWIDTH_RATIO == 4) // Half Rate
begin : halfrate_wdata_gen
always @* // combinational logic sensitivity
begin
if (bit_order_1x == 1'b0)
begin
wr_data = {rdv_pipe_ip[1], rdv_pipe_ip[0]};
end
else
begin
wr_data = {rdv_pipe_ip[0], rdv_pipe_ip_beat2_r};
end
end
end
else // Full-rate
begin : fullrate_wdata_gen
always @* // combinational logic sensitivity
begin
wr_data = rdv_pipe_ip;
end
end
endgenerate
// write address
always @*
begin
next_wr_addr = wr_addr + 1'b1;
if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr = wr_addr;
end
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr = wr_addr + 2'h2;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr <= RDATA_VALID_INITIAL_LAT[RDATA_VALID_AWIDTH - 1 : 0];
end
else
begin
wr_addr <= next_wr_addr;
end
end
// read address generator : just a free running counter.
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
rd_addr <= {RDATA_VALID_AWIDTH{1'b0}};
end
else
begin
rd_addr <= rd_addr + 1'b1; //inc address, can wrap
end
end
// altsyncram instance
altsyncram #(.
address_aclr_b ("NONE"),
.address_reg_b ("CLOCK0"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**RDATA_VALID_AWIDTH),
.numwords_b (2**RDATA_VALID_AWIDTH),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK0"),
.power_up_uninitialized ("FALSE"),
.widthad_a (RDATA_VALID_AWIDTH),
.widthad_b (RDATA_VALID_AWIDTH),
.width_a (DWIDTH_RATIO/2),
.width_b (DWIDTH_RATIO/2),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (phy_clk_1x),
.address_a (wr_addr),
.address_b (rd_addr),
.data_a (wr_data),
.q_b (int_rdata_valid),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH_RATIO/2){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
// Generate read data valid enable signals for controller and seqencer
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
seq_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
end
else
begin
// shift the shift register by DWIDTH_RATIO locations
// rdv_delay_index plus (DWIDTH_RATIO/2)-1 bits counting down
ctl_rdata_valid <= int_rdata_valid & {(DWIDTH_RATIO/2){ctl_cal_success}};
seq_rdata_valid <= int_rdata_valid;
end
end
endmodule
`default_nettype wire
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_write_dp(
// clocks
phy_clk_1x,
// active-low reset, sync'd to clock domain
reset_phy_clk_1x_n,
// control i/f inputs
ctl_mem_be,
ctl_mem_dqs_burst,
ctl_mem_wdata,
ctl_mem_wdata_valid,
ctl_mem_dqs,
// from OCT path...
ctl_mem_oct,
// seq i/f inputs :
seq_be,
seq_dqs_burst,
seq_wdata,
seq_wdata_valid,
seq_dqs,
seq_ctl_sel,
seq_oct_val,
seq_dq_dm_add_2t_delay,
seq_dqs_add_2t_delay,
// outputs to IOEs
wdp_wdata3_1x,
wdp_wdata2_1x,
wdp_wdata1_1x,
wdp_wdata0_1x,
wdp_wdata_oe_h_1x,
wdp_wdata_oe_l_1x,
wdp_dqs3_1x,
wdp_dqs2_1x,
wdp_dqs1_1x,
wdp_dqs0_1x,
wdp_dqs_oe_h_1x,
wdp_dqs_oe_l_1x,
wdp_dm3_1x,
wdp_dm2_1x,
wdp_dm1_1x,
wdp_dm0_1x,
wdp_oct_h_1x,
wdp_oct_l_1x
);
// Notes on parameters :
//
// BIDIR_DPINS is only required to support QDR-type memory, which has seperate DQ and D
// data buses. The value is ignored pending QDR support.
//
// LOCAL_IF_DRATE should not be required, as SIII will always be half-rate.
//
// MEM_IF_DQS_WIDTH should always be MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS
//
// MEM_IF_DM_WIDTH should always be equal to MEM_IF_DQS_WIDTH
//
// GENERATE_WRITE_DQS is only required to support QDR-type memory, which does not
// require write DQS logic
//
parameter BIDIR_DPINS = 1;
parameter LOCAL_IF_DRATE = "HALF";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_BE_WIDTH = 32;
parameter MEM_IF_OCT_EN = 0;
parameter GENERATE_WRITE_DQS = 1;
parameter MEM_IF_DWIDTH = 64;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_MEMTYPE = "QDRII";
// Notes on I/O :
//
// ctl_mem_be is the inverse of the "DM" value.
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
// control i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] ctl_mem_be;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] ctl_mem_wdata;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_wdata_valid;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_oct;
input wire [3 : 0] ctl_mem_dqs;
// seq i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] seq_be;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] seq_wdata;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_wdata_valid;
input wire seq_oct_val;
input wire [3 : 0] seq_dqs;
input wire seq_ctl_sel;
input wire seq_dq_dm_add_2t_delay;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
// outputs to the IOEs
(* preserve *) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata3_1x;
(* preserve *) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata2_1x;
(* preserve *) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata1_1x;
(* preserve *) output reg [MEM_IF_DWIDTH - 1 : 0] wdp_wdata0_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_h_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_l_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs3_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs2_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs1_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs0_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_h_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_l_1x;
// These shall be NWS/BWS for QDRII :
(* preserve *) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm3_1x;
(* preserve *) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm2_1x;
(* preserve *) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm1_1x;
(* preserve *) output reg [MEM_IF_DM_WIDTH -1 : 0] wdp_dm0_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_h_1x;
(* preserve *) output reg [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_l_1x;
// internal reg declarations
// Note that at this point, the 'be' signal shall potentially have been
// doubled in width if in 4 DQ_PER_DQS mode :
(* preserve *) reg [3 : 0] mem_dqs_r;
(* preserve *) reg [LOCAL_IF_DWIDTH - 1 : 0] mem_wdata_r;
(* preserve *) reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] mem_be_r;
(* preserve *) reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 - 1 : 0] mem_dqs_burst_r;
(* preserve *) reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 - 1 : 0] mem_wdata_valid_r;
(* preserve *) reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 - 1 : 0] mem_oct_r;
// MUX outputs....
reg [DWIDTH_RATIO - 1 : 0] mem_dqs ;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_dqs_burst ;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_wdata_valid;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] mem_oct;
reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] mem_be ;
reg [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] mem_wdata ;
reg tie_low = 1'b0;
always @*
begin
// Select controller or sequencer according to the select signal :
//for QDRII, no register is needed here
if (seq_ctl_sel)
begin
mem_dqs_burst = seq_dqs_burst;
mem_dqs = seq_dqs;
mem_be = seq_be;
mem_wdata = seq_wdata;
mem_wdata_valid = seq_wdata_valid;
mem_oct = {(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2){seq_oct_val}};
end
else
begin
mem_dqs_burst = ctl_mem_dqs_burst;
mem_dqs = ctl_mem_dqs;
mem_be = ctl_mem_be;
mem_wdata = ctl_mem_wdata;
mem_wdata_valid = ctl_mem_wdata_valid;
mem_oct = ctl_mem_oct;
end
end
// Additional registeriong for clk delay switching in.
always @(posedge phy_clk_1x)
begin
mem_dqs_r <= mem_dqs;
mem_wdata_valid_r <= mem_wdata_valid;
mem_dqs_burst_r <= mem_dqs_burst;
mem_wdata_r <= mem_wdata;
mem_oct_r <= mem_oct;
mem_be_r <= mem_be;
end
generate
genvar ia;
for (ia=0; ia<MEM_IF_DWIDTH; ia=ia+1)
begin : gen_dq
always @(posedge phy_clk_1x)
begin
if (seq_dq_dm_add_2t_delay)
begin
wdp_wdata3_1x[ia] <= mem_wdata_r[ia+MEM_IF_DWIDTH*2];
wdp_wdata2_1x[ia] <= mem_wdata_r[ia+MEM_IF_DWIDTH*0];
wdp_wdata1_1x[ia] <= mem_wdata_r[ia+MEM_IF_DWIDTH*3];
wdp_wdata0_1x[ia] <= mem_wdata_r[ia+MEM_IF_DWIDTH*1];
end
else
begin
wdp_wdata3_1x[ia] <= mem_wdata[ia+MEM_IF_DWIDTH*2];
wdp_wdata2_1x[ia] <= mem_wdata[ia+MEM_IF_DWIDTH*0];
wdp_wdata1_1x[ia] <= mem_wdata[ia+MEM_IF_DWIDTH*3];
wdp_wdata0_1x[ia] <= mem_wdata[ia+MEM_IF_DWIDTH*1];
end
end //posedge clk
end // block: gen_dqs
endgenerate
// OEs
generate
genvar ib;
for (ib=0; ib<MEM_IF_DQS_WIDTH; ib=ib+1)
begin : gen_dqoe
always @(posedge phy_clk_1x)
begin
if (seq_dq_dm_add_2t_delay)
begin
wdp_wdata_oe_l_1x[ib] <= mem_wdata_valid_r[ib];
wdp_wdata_oe_h_1x[ib] <= mem_wdata_valid_r[ib+ MEM_IF_DQS_WIDTH];
end
else
begin
wdp_wdata_oe_l_1x[ib] <= mem_wdata_valid[ib ];
wdp_wdata_oe_h_1x[ib] <= mem_wdata_valid[ib+ MEM_IF_DQS_WIDTH];
end
end //posedge clk
end // block: gen_dqoe
endgenerate
generate
genvar ic;
for (ic=0; ic<MEM_IF_DQS_WIDTH; ic=ic+1)
begin : gen_dqs
always @(posedge phy_clk_1x)
begin
if (seq_dqs_add_2t_delay[ic])
begin
wdp_dqs3_1x[ic] <= mem_dqs_r[3] ^ ~mem_dqs_burst_r[ic + MEM_IF_DQS_WIDTH];
wdp_dqs2_1x[ic] <= mem_dqs_r[2] ^ ~mem_dqs_burst_r[ic];
wdp_dqs1_1x[ic] <= mem_dqs_r[1] ^ ~mem_dqs_burst_r[ic + MEM_IF_DQS_WIDTH];
wdp_dqs0_1x[ic] <= mem_dqs_r[0] ^ ~mem_dqs_burst_r[ic];
wdp_dqs_oe_l_1x[ic] <= mem_dqs_burst_r[ic];
wdp_dqs_oe_h_1x[ic] <= mem_dqs_burst_r[ic + MEM_IF_DQS_WIDTH];
end
else
begin
wdp_dqs3_1x[ic] <= mem_dqs[3] ^ ~mem_dqs_burst[ic + MEM_IF_DQS_WIDTH];
wdp_dqs2_1x[ic] <= mem_dqs[2] ^ ~mem_dqs_burst[ic];
wdp_dqs1_1x[ic] <= mem_dqs[1] ^ ~mem_dqs_burst[ic + MEM_IF_DQS_WIDTH];
wdp_dqs0_1x[ic] <= mem_dqs[0] ^ ~mem_dqs_burst[ic];
wdp_dqs_oe_l_1x[ic] <= mem_dqs_burst[ic];
wdp_dqs_oe_h_1x[ic] <= mem_dqs_burst[ic + MEM_IF_DQS_WIDTH];
end
end
if (MEM_IF_OCT_EN == 1)
begin
always @(posedge phy_clk_1x)
begin
if (seq_dqs_add_2t_delay[ic])
begin
wdp_oct_l_1x[ic] <= mem_oct_r[ic];
wdp_oct_h_1x[ic] <= mem_oct_r[ic + MEM_IF_DQS_WIDTH];
end
else
begin
wdp_oct_l_1x[ic] <= mem_oct[ic];
wdp_oct_h_1x[ic] <= mem_oct[ic + MEM_IF_DQS_WIDTH];
end
end //posedge clk
end // OCT_EN
else // Tie-off if OCT not enabled :
begin
always @(tie_low)
begin
wdp_oct_h_1x[ic] = tie_low;
wdp_oct_l_1x[ic] = tie_low;
end
end
end // block: gen_dqs
endgenerate
// Conditional generation of DM logic, based on generic
generate
genvar ie;
if (MEM_IF_DM_PINS_EN == 1'b1)
begin : dm_logic
for (ie=0; ie<MEM_IF_DM_WIDTH; ie=ie+1)
begin : gen_dm
always @(posedge phy_clk_1x)
begin
if (seq_dq_dm_add_2t_delay)
begin
wdp_dm3_1x[ie] <= mem_be_r[ie+MEM_IF_DM_WIDTH*2];
wdp_dm2_1x[ie] <= mem_be_r[ie+MEM_IF_DM_WIDTH*0];
wdp_dm1_1x[ie] <= mem_be_r[ie+MEM_IF_DM_WIDTH*3];
wdp_dm0_1x[ie] <= mem_be_r[ie+MEM_IF_DM_WIDTH*1];
end
else
begin
wdp_dm3_1x[ie] <= mem_be[ie+MEM_IF_DM_WIDTH*2];
wdp_dm2_1x[ie] <= mem_be[ie+MEM_IF_DM_WIDTH*0];
wdp_dm1_1x[ie] <= mem_be[ie+MEM_IF_DM_WIDTH*3];
wdp_dm0_1x[ie] <= mem_be[ie+MEM_IF_DM_WIDTH*1];
end
end //posedge clk
end // block: gen_dm
end // block: dm_logic_enabled
endgenerate
endmodule // alt_mem_phy_write_dp_sii
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_dqs_op (
phy_clk_1x,
write_clk_2x,
mem_clk_2x,
sc_clk,
scan_enable,
scan_update,
scan_din,
scan_dout,
wdp_dqs3_1x,
wdp_dqs2_1x,
wdp_dqs1_1x,
wdp_dqs0_1x,
wdp_dqs_oe_h_1x,
wdp_dqs_oe_l_1x,
wdp_oct_h_1x,
wdp_oct_l_1x,
dqs_sneak_in,
dqs_sneak_out,
dqs_pad,
dedicated_dll_delay_ctrl,
enaoutputcycledelaysetting,
enaoutputphasetransferreg,
dqsoutputphaseinvert,
dqsoutputphasesetting,
enaoctcycledelaysetting,
enaoctphasetransferreg,
octdelaysetting1,
octdelaysetting2,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter INVERT_OP_FOR_DQSN = 0;
parameter MEM_IF_MEMTYPE = "DDR";
parameter LEVELLING = 1;
parameter MEM_IF_DQSN_EN = 1;
parameter MEM_IF_OCT_EN = 0;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_STR_T9_DESKEW_EN = 0;
parameter MEM_IF_STR_T10_DESKEW_EN = 0;
parameter MEM_IF_OCT_T9_DESKEW_EN = 0;
parameter MEM_IF_OCT_T10_DESKEW_EN = 0;
parameter MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL = "false";
parameter ENABLE_DDR3_SEQUENCER = "FALSE";
parameter OPA_USES_DELAYED_CLK = "false";
input wire phy_clk_1x;
input wire write_clk_2x;
input wire mem_clk_2x;
input wire sc_clk;
input wire scan_enable;
input wire scan_update;
input wire scan_din;
output wire scan_dout;
input wire wdp_dqs3_1x;
input wire wdp_dqs2_1x;
input wire wdp_dqs1_1x;
input wire wdp_dqs0_1x;
input wire wdp_dqs_oe_h_1x;
input wire wdp_dqs_oe_l_1x;
//OCT
input wire wdp_oct_h_1x;
input wire wdp_oct_l_1x;
// If this block is being instanced as a DQSN output path, then instead of using
// DDIO/Output phase align atoms, a sneak path is used, which is an inverted version
// of the DQS output path. The parameter INVERT_OP_FOR_DQSN is used to determine what to do.
input wire dqs_sneak_in;
// If this block is a DQS output path, then we need to tap-off the output path and
// output as the sneak path for the DQSN path to use :
output wire dqs_sneak_out;
inout wire dqs_pad;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
// NB. These are outputs from the DQS CONFIG block :
input wire enaoutputcycledelaysetting;
input wire enaoutputphasetransferreg;
input wire dqsoutputphaseinvert;
input wire [`DQSCONFIG_DQS_OUTPUT_PHASE_SETTING_WIDTH-1:0] dqsoutputphasesetting;
//OCT only :
input wire enaoctcycledelaysetting;
input wire enaoctphasetransferreg;
input wire [`DQSCONFIG_DQS_OCT_DELAY_SETTING1_WIDTH-1 :0] octdelaysetting1;
input wire [`DQSCONFIG_DQS_OCT_DELAY_SETTING2_WIDTH-1 :0] octdelaysetting2;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] seriesterminationcontrol;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] parallelterminationcontrol;
// Internal wires :
wire dqs_oe;
wire dqs_oe_aligned;
reg dqs_oe_aligned_reg;
wire dqs_oe_aligned_delayed;
wire dqs_oe_aligned_delayed2;
wire dqs_oct;
wire dqs_oct_aligned;
wire dqs_oct_aligned_delayed;
wire dqs_oct_aligned_delayed2;
wire dqs_l;
wire dqs_h;
wire dqs_aligned;
wire dqs_aligned_delayed;
wire dqs_aligned_delayed2;
wire dqs_pdiff_out;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING1_WIDTH-1:0] outputdelaysetting1;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING2_WIDTH-1:0] outputdelaysetting2;
generate
if (INVERT_OP_FOR_DQSN == 0)
begin : dqs_ddio_out_gen
if (DWIDTH_RATIO == 4)
begin : dqs_ddio_out_half_rate_gen
// Output path. Instance this if a DQS path only :
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) o_ddio_h(
.datainhi (wdp_dqs3_1x),
.datainlo (wdp_dqs2_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqs_h),
.devpor (),
.devclrn ()
);
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) o_ddio_l(
.datainhi (wdp_dqs1_1x),
.datainlo (wdp_dqs0_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqs_l),
.devpor (),
.devclrn ()
);
end
else
begin : dqs_ddio_out_full_rate_gen
assign dqs_l = wdp_dqs0_1x;
assign dqs_h = wdp_dqs1_1x;
end
// Phase alignment is either via DDIO for DDR/DDR2 or phase alignment atom for DDR3 :
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2" || (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 0))
begin : ddr_ddio_phase_align_gen
// DDIO output
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
)dqs_ddio_inst(
.datainhi (dqs_h),
.datainlo (dqs_l),
.clkhi (mem_clk_2x),
.clklo (mem_clk_2x),
.muxsel (mem_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqs_aligned),
.devpor (),
.devclrn ()
);
end
else
begin : ddr3_opa_phase_align_gen
// Output_phase_alignment of output
// Note : delay_buffer_mode for output_phase_alignment atoms must always be tied to "high" :
stratixiii_output_phase_alignment # (
.operation_mode ("ddio_out"),
.use_phasectrlin (ENABLE_DDR3_SEQUENCER),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.use_primary_clock ("true"),
.invert_phase ("dynamic"),
//.phase_setting_for_delayed_clock (2),
.phase_setting (2)
) o_phase_align (
.datain ({dqs_h,dqs_l}),
.clk (write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqsoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoctcycledelaysetting),
.enaphasetransferreg (enaoctphasetransferreg),
.phaseinvertctrl (dqsoutputphaseinvert),
// synopsys translate_off
.delaymode(),
.dutycycledelayctrlin(),
.devclrn(),
.devpor(),
.dffin(),
.dff1t(),
.dffddiodataout(),
// synopsys translate_on
.dataout (dqs_aligned)
);
end
// If DQSN is to be used, instance the pseudo-diff atom :
if (MEM_IF_DQSN_EN == 1)
begin : pseudo_diff_gen
// DQS, so assign the sneak-out path :
stratixiii_pseudo_diff_out o_pdiff (
.i (dqs_aligned_delayed2),
.o (dqs_pdiff_out),
.obar (dqs_sneak_out)
);
end
// Otherwise, output from the delay chain :
else
begin : no_pseudo_diff_gen
assign dqs_pdiff_out = dqs_aligned_delayed2;
assign dqs_sneak_out = 1'b0;
end
end // DQSN or not
else // If DQSN, use the sneak path :
begin : dqsn_sneak_path_gen
// No need to invert sneak path as the pseudo_diff in DQS should have done this :
assign dqs_pdiff_out = dqs_sneak_in;
assign dqs_sneak_out = 1'b0;
end
endgenerate
// DQS OE path :
// The OE path is always instanced, regardless of whether this is a DQS or DQSN path.
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_oe_ddio_gen
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) oe_ddio (
.datainhi (~wdp_dqs_oe_h_1x),
.datainlo (~wdp_dqs_oe_l_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqs_oe),
.devpor (),
.devclrn ()
);
end
else
begin : full_rate_oe_ddio_gen
assign dqs_oe = ~wdp_dqs_oe_l_1x;
end
endgenerate
// Phase alignment is either via DDIO for DDR/DDR2 or phase alignment atom for DDR3 :
generate
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2")
begin : ddr_ddio_oe_phase_align_gen
// DDR/DDR2 DDIO_OE
stratixiii_ddio_oe oe_phase_align (
.oe (dqs_oe),
.clk (mem_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (),
// synopsys translate_off
.dfflo (),
.dffhi (),
.devpor (),
.devclrn (),
// synopsys translate_on
.dataout (dqs_oe_aligned)
);
end
else
begin : ddr3_dqs_oe
if (LEVELLING == 0)
begin : ddr3_ddio_oe_phase_align_gen
// synopsys translate_off
initial
dqs_oe_aligned_reg = 0;
// synopsys translate_on
always @ (posedge mem_clk_2x)
dqs_oe_aligned_reg <= dqs_oe;
assign dqs_oe_aligned = dqs_oe_aligned_reg;
end
else
begin : ddr3_opa_phase_align_gen
// Output_phase_alignment of oe
// Note : delay_buffer_mode for output_phase_alignment atoms must always be tied to "high" :
stratixiii_output_phase_alignment # (
.operation_mode ("oe"),
.use_phasectrlin (ENABLE_DDR3_SEQUENCER),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.use_primary_clock ("true"),
.invert_phase ("dynamic"),
//.phase_setting_for_delayed_clock (2),
.phase_setting (2)
) oe_phase_align (
.datain ({1'b0,dqs_oe}),
.clk (LEVELLING == 0 ? mem_clk_2x : write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqsoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoctcycledelaysetting),
.enaphasetransferreg (enaoctphasetransferreg),
.phaseinvertctrl (dqsoutputphaseinvert),
// synopsys translate_off
.delaymode(),
.dutycycledelayctrlin(),
.devclrn(),
.devpor(),
.dffin(),
.dff1t(),
.dffddiodataout(),
// synopsys translate_on
.dataout (dqs_oe_aligned)
);
end
end
endgenerate
generate
if (MEM_IF_STR_T9_DESKEW_EN == 1)
begin : gen_T9_dqs_deskew
stratixiii_delay_chain o_pa_dc1(
.datain (dqs_aligned),
.delayctrlin (outputdelaysetting1),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqs_aligned_delayed)
);
// oe delay_chain_1
stratixiii_delay_chain oe1_opa_dc1(
.datain (dqs_oe_aligned),
.delayctrlin (outputdelaysetting1),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqs_oe_aligned_delayed)
);
end
else
begin : gen_T9_dqs_no_deskew
assign dqs_aligned_delayed = dqs_aligned;
assign dqs_oe_aligned_delayed = dqs_oe_aligned;
end
endgenerate
generate
if (MEM_IF_STR_T10_DESKEW_EN == 1)
begin : gen_T10_dqs_deskew
// output delay_chain_2
stratixiii_delay_chain o_pa_dc2(
.datain (dqs_aligned_delayed),
.delayctrlin ({1'b0, outputdelaysetting2}),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqs_aligned_delayed2)
);
// oe delay_chain_2
stratixiii_delay_chain oe1_opa_dc2(
.datain (dqs_oe_aligned_delayed),
.delayctrlin ({1'b0, outputdelaysetting2}),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqs_oe_aligned_delayed2)
);
end
else
begin : gen_T10_dqs_no_deskew
assign dqs_aligned_delayed2 = dqs_aligned_delayed;
assign dqs_oe_aligned_delayed2 = dqs_oe_aligned_delayed;
end
endgenerate
// DQS OCT path :
// The OCT path is always instanced, regardless of whether this is a DQS or DQSN path.
generate
if (MEM_IF_OCT_EN == 1)
begin : oct_ddio_gen
if (DWIDTH_RATIO == 4)
begin : dqs_oct_half_rate_gen
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) oct_ddio (
.datainhi (wdp_oct_h_1x),
.datainlo (wdp_oct_l_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqs_oct),
.devpor (),
.devclrn ()
);
end
else
begin : dqs_oct_full_rate_gen
assign dqs_oct = wdp_oct_l_1x;
end
// Phase alignment is either via DDIO for DDR/DDR2 or phase alignment atom for DDR3 :
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2" || (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 0))
begin : ddr_ddio_oe_phase_align_gen
// DDR/DDR2 DDIO_OE
stratixiii_ddio_oe oct_phase_align (
.oe (dqs_oct),
.clk (mem_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (),
// synopsys translate_off
.dfflo (),
.dffhi (),
.devpor (),
.devclrn (),
// synopsys translate_on
.dataout (dqs_oct_aligned)
);
end
else
begin : ddr3_opa_phase_align_gen
// Output_phase_alignment of oct
// Note : delay_buffer_mode for output_phase_alignment atoms must always be tied to "high" :
stratixiii_output_phase_alignment # (
.operation_mode ("rtena"),//("extended_rtena"),
.use_phasectrlin (ENABLE_DDR3_SEQUENCER),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("none"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.use_primary_clock ("true"),
.invert_phase ("dynamic"),
//.phase_setting_for_delayed_clock (2),
.phase_setting (2)
) oct_phase_align(
.datain ({1'b0,dqs_oct}),
.clk (write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqsoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoctcycledelaysetting),
.enaphasetransferreg (enaoctphasetransferreg),
.phaseinvertctrl (dqsoutputphaseinvert),
// synopsys translate_off
.delaymode(),
.dutycycledelayctrlin(),
.devclrn(),
.devpor(),
.dffin(),
.dff1t(),
.dffddiodataout(),
// synopsys translate_on
.dataout (dqs_oct_aligned)
);
end
if (MEM_IF_OCT_T9_DESKEW_EN == 1)
begin : gen_T9_OCT_deskew
stratixiii_delay_chain dqoct_t9_delay(
.datain (dqs_oct_aligned),
.delayctrlin (octdelaysetting1),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqs_oct_aligned_delayed)
);
end
else
begin : gen_T9_OCT_no_deskew
assign dqs_oct_aligned_delayed = dqs_oct_aligned;
end
if (MEM_IF_OCT_T10_DESKEW_EN == 1)
begin : gen_T10_OCT_deskew
stratixiii_delay_chain dqoct_t10_delay(
.datain (dqs_oct_aligned_delayed),
.delayctrlin ({1'b0, octdelaysetting2}),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqs_oct_aligned_delayed2)
);
end
else
begin : gen_T10_OCT_no_deskew
assign dqs_oct_aligned_delayed2 = dqs_oct_aligned_delayed;
end
end // if MEM_IF_OCT_EN
// No OCT :
else
begin : no_oct_gen
assign dqs_oct_aligned_delayed2 = 1'b0;
end
endgenerate
// output buf for DQS
stratixiii_io_obuf # (
.bus_hold ("false"),
.open_drain_output ("false"),
.shift_series_termination_control (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL)
) obuf(
.i (dqs_pdiff_out),
.oe (~dqs_oe_aligned_delayed2),
.dynamicterminationcontrol (dqs_oct_aligned_delayed2),
// synopsys translate_off
.seriesterminationcontrol (seriesterminationcontrol),
.parallelterminationcontrol(parallelterminationcontrol),
.obar(),
// synopsys translate_on
.o(dqs_pad),
.devoe()
);
// IO_CONFIG
stratixiii_io_config io_config(
.datain(scan_din),
.clk(sc_clk),
.ena(scan_enable),
.update(scan_update),
// synopsys translate_off
.devclrn(), .devpor(),
.dutycycledelaymode(),
.dutycycledelaysettings(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.padtoinputregisterfinedelaysetting(),
// synopsys translate_on
.padtoinputregisterdelaysetting(),
.outputdelaysetting1(outputdelaysetting1),
.outputdelaysetting2(outputdelaysetting2),
.dataout(scan_dout)
);
endmodule
//
`timescale 1 ps / 1 ps
//
module ddr3_s4_amphy_phy_alt_mem_phy_delay (
s_in,
s_out
);
//parameters
parameter WIDTH = 1;
parameter DELAY_PS = 10;
//ports
input wire [WIDTH - 1 : 0] s_in;
output reg [WIDTH - 1 : 0] s_out;
// synopsys translate_off
wire [WIDTH - 1 : 0] delayed_s_in;
//model the transport delay
assign #(DELAY_PS) delayed_s_in = s_in;
// synopsys translate_on
always @*
begin
s_out = s_in;
// synopsys translate_off
s_out = delayed_s_in;
// synopsys translate_on
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_dqs_ip (
poa_postamble_en_preset,
resync_clk_1x,
resync_clk_2x,
dedicated_dll_delay_ctrl,
seq_dqs_delay_ctrl,
dll_offset_delay_ctrl,
dqs_update_en,
dqsinputphasesetting,
dqs_pad,
dqsn_pad,
dqs_enable,
dqsn_enable,
dqsbusoutdelaysetting,
dqsenablectrlphasesetting,
dqsenabledelaysetting,
enadqsenablephasetransferreg,
dqsenablectrlphaseinvert,
enaoutputcycledelaysetting,
enaoutputphasetransferreg,
dqsoutputphaseinvert,
dqsoutputphasesetting
) /* synthesis altera_attribute="SUPPRESS_DA_RULE_INTERNAL=\"A103,R101\"" */ ;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_MEMTYPE = "DDR";
parameter LEVELLING = 1;
parameter MEM_IF_DQSN_EN = 1;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DQS_PHASE = 9000;
parameter DQS_PHASE_SETTING = 2;
parameter DWIDTH_RATIO = 4;
parameter ENABLE_DDR3_SEQUENCER = "FALSE";
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter MEM_TCL = "1.5";
parameter DQS_DELAY_CODE_FROM_DLL = "FALSE";
parameter DQS_DELAY_USES_OFFSET = "false";
parameter USE_DQS_DELAY_LATCHES = "false";
parameter DQS_USE_PHASECTRL_IN = "false";
parameter MEM_IF_USE_T11 = 0;
parameter MEM_IF_USE_T7 = 0;
parameter INVERT_POSTAMBLE_CLK = "false";
localparam DQS_BUS_INSERTION_DELAY = 250;
localparam ADD_PHASE_TRANSFER_REG_SETTING = (INVERT_POSTAMBLE_CLK == "false" || INVERT_POSTAMBLE_CLK == "FALSE") ? "true" : "false";
input wire [DWIDTH_RATIO/2 -1 : 0] poa_postamble_en_preset;
// Half-rate resync clock from clock dividers :
input wire resync_clk_1x;
input wire resync_clk_2x;
// The DLL delay control is used for the DQS Enable Control :
input wire [DQS_DELAY_CTL_WIDTH-1:0] dedicated_dll_delay_ctrl;
// The sequencer can supply a unique 6bit delay control code to each DQS group or this can come straight from the DLL.
input wire [DQS_DELAY_CTL_WIDTH-1:0] seq_dqs_delay_ctrl;
input wire [DQS_DELAY_CTL_WIDTH-1:0] dll_offset_delay_ctrl;
input wire dqs_update_en;
input wire [2 : 0] dqsinputphasesetting;
inout wire dqs_pad;
inout wire dqsn_pad;
// NB. 'wire' omitted so that attributes can be applied later.
// DQS enable used for DDR/2/3 memories, as these either have true differential
// DQS/DQSN pins (producing one active high DQS enable) or (for DDR) just a DQS
// signal is used :
output dqs_enable;
// For QDRII devices, DQS and DQSN are pseudo-differential and as the active-low
// version of DQS is required to clock incoming DQ data, this is directly propagated :
output dqsn_enable;
// NB. These are outputs from the DQS CONFIG block :
input wire [`DQSCONFIG_DQS_OUTPUT_PHASE_SETTING_WIDTH-1: 0] dqsoutputphasesetting;
input wire [`DQSCONFIG_DQS_BUSOUT_DELAY_SETTING_WIDTH-1 :0] dqsbusoutdelaysetting;
input wire [`DQSCONFIG_DQS_EN_CTRL_PHASE_SETTING_WIDTH-1:0] dqsenablectrlphasesetting;
input wire [`DQSCONFIG_DQS_EN_DELAY_SETTING_WIDTH-1 :0] dqsenabledelaysetting;
input wire enadqsenablephasetransferreg;
input wire dqsenablectrlphaseinvert;
input wire enaoutputcycledelaysetting;
input wire enaoutputphasetransferreg;
input wire dqsoutputphaseinvert;
(* altera_attribute = "-name global_signal off" *) wire dqs_buffered;
(* altera_attribute = "-name global_signal off" *) wire dqs_delayed;
(* altera_attribute = "-name global_signal off" *) wire dqs_delayed2;
(* altera_attribute = "-name global_signal off" *) wire dqsn_buffered;
(* altera_attribute = "-name global_signal off" *) wire dqsn_delayed;
(* altera_attribute = "-name global_signal off" *) wire dqsn_delayed2;
wire dqs_enable_ddio_output;
wire dqs_enable_ctrl_op;
wire dqs_enable_ctrl_op_delayed;
wire [DQS_DELAY_CTL_WIDTH-1:0] chosen_dqs_delay_delayctrlin;
wire dqsn_enable;
(* altera_attribute = "-name global_signal off" *) reg dqs_enable;
(* altera_attribute = "-name global_signal off" *) wire dqs_enable_op;
(* altera_attribute = "-name global_signal off" *) wire dqsn_enable_op;
wire dqs_enable_sim;
function integer min (input integer a, b);
begin
if (a < b)
min = a;
else
min = b;
end
endfunction
//
ddr3_s4_amphy_phy_alt_mem_phy_delay # (
.WIDTH (1),
.DELAY_PS (DQS_BUS_INSERTION_DELAY)
) dqs_enable_delay(
.s_in (dqs_enable_op),
.s_out (dqs_enable_sim)
);
always @*
begin
dqs_enable = dqs_enable_sim;
end
generate
if (MEM_IF_MEMTYPE == "QDRII")
begin : gen_dqsn_enable_delay
assign #DQS_BUS_INSERTION_DELAY dqsn_enable = dqsn_enable_op;
end
else
begin : tie_off_dqsn_enable
// Set dqsn_enable to zero. The '?' is used simply to reduce warnings about dqsn_enable_op not being read :
assign dqsn_enable = dqsn_enable_op ? 1'b0 : 1'b0;
end
endgenerate
generate
// For DDR, or DDR2 where DQSN is disabled, it is important to leave the DQSN
// pad unconnected, as otherwise this path remains in the netlist even
// though there is no intent to use DQSN, and it is unused as an output :
if (MEM_IF_MEMTYPE == "DDR" || (MEM_IF_MEMTYPE == "DDR2" && (MEM_IF_DQSN_EN == 0)) )
begin : ddr_no_dqsn_ibuf_gen
// Input buf
stratixiii_io_ibuf dqs_inpt_io_ibuf(
.i (dqs_pad),
.ibar (),
// synopsys translate_off
.dynamicterminationcontrol(),
// synopsys translate_on
.o (dqs_buffered)
);
assign dqsn_pad = 1'b0;
end
// QDRII has both DQS and DQSN, but only pseudo-differential. Both are used for DQ
// capture in the DDIO atom :
else if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_ibuf_gen
// Input buf
stratixiii_io_ibuf dqs_inpt_io_ibuf(
.i (dqs_pad),
.ibar (),
// synopsys translate_off
.dynamicterminationcontrol(),
// synopsys translate_on
.o (dqs_buffered)
);
// Input buf
stratixiii_io_ibuf dqsn_inpt_io_ibuf(
.i (dqsn_pad),
.ibar (),
// synopsys translate_off
.dynamicterminationcontrol(),
// synopsys translate_on
.o (dqsn_buffered)
);
end
// DDR2 (with DQSN enabled) and DDR3 have true differential DQS inputs :
else
begin : ddr3_2_with_dqsn_ibuf_gen
// Input buf
stratixiii_io_ibuf dqs_inpt_io_ibuf(
.i (dqs_pad),
.ibar (dqsn_pad),
// synopsys translate_off
.dynamicterminationcontrol(),
// synopsys translate_on
.o (dqs_buffered)
);
end
endgenerate
// DQS delay.
generate
if (DQS_DELAY_CODE_FROM_DLL == "FALSE" || DQS_DELAY_CODE_FROM_DLL == "false" )
assign chosen_dqs_delay_delayctrlin = seq_dqs_delay_ctrl;
else
assign chosen_dqs_delay_delayctrlin = dedicated_dll_delay_ctrl;
endgenerate
// The delay control for each DQS group comes from the modified delay control
// from the sequencer. Note that it is correct that DLL_DELAY_BUFFER_MODE should
// be propagated to delay_buffer_mode here.
generate
if (MEM_IF_MEMTYPE == "QDRII")
begin : gen_qdrii_dqs_delay_chain
if (DQS_DELAY_USES_OFFSET =="true" || DQS_DELAY_USES_OFFSET == "TRUE")
begin : gen_dqs_delay_chain_with_offset
stratixiii_dqs_delay_chain # (
.dqs_input_frequency (MEM_IF_CLK_PS_STR),
.use_phasectrlin (DQS_USE_PHASECTRL_IN),
.phase_setting (DQS_PHASE_SETTING),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.dqs_phase_shift (DQS_PHASE),
.dqs_offsetctrl_enable (DQS_DELAY_USES_OFFSET),
.dqs_ctrl_latches_enable (USE_DQS_DELAY_LATCHES)
) delay_chain(
.dqsin (dqs_buffered),
.delayctrlin (chosen_dqs_delay_delayctrlin),
.offsetctrlin (dll_offset_delay_ctrl),
.dqsupdateen (dqs_update_en),
.phasectrlin (dqsinputphasesetting),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dqsbusout (dqs_enable_op)
);
end
else
begin: gen_dqs_delay_chain_no_offset
stratixiii_dqs_delay_chain # (
.dqs_input_frequency (MEM_IF_CLK_PS_STR),
.use_phasectrlin (DQS_USE_PHASECTRL_IN),
.phase_setting (DQS_PHASE_SETTING),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.dqs_phase_shift (DQS_PHASE),
.dqs_offsetctrl_enable (DQS_DELAY_USES_OFFSET),
.dqs_ctrl_latches_enable (USE_DQS_DELAY_LATCHES)
) delay_chain(
.dqsin (dqs_buffered),
.delayctrlin (chosen_dqs_delay_delayctrlin),
.offsetctrlin (), //(dll_offset_delay_ctrl),
.dqsupdateen (dqs_update_en),
.phasectrlin (dqsinputphasesetting),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dqsbusout (dqs_enable_op)
);
end
end
else
begin : gen_ddr_dqs_delay_chain
if (DQS_DELAY_USES_OFFSET == "true" || DQS_DELAY_USES_OFFSET == "TRUE")
begin : gen_dqs_delay_chain_with_offset
stratixiii_dqs_delay_chain # (
.dqs_input_frequency (MEM_IF_CLK_PS_STR),
.use_phasectrlin (DQS_USE_PHASECTRL_IN),
.phase_setting (DQS_PHASE_SETTING),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.dqs_phase_shift (DQS_PHASE),
.dqs_offsetctrl_enable ("true"),
.dqs_ctrl_latches_enable (USE_DQS_DELAY_LATCHES)
) delay_chain(
.dqsin (dqs_buffered),
.delayctrlin (chosen_dqs_delay_delayctrlin),
.offsetctrlin (dll_offset_delay_ctrl),
.dqsupdateen (dqs_update_en),
.phasectrlin (dqsinputphasesetting),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dqsbusout (dqs_delayed)
);
end
else
begin: gen_dqs_delay_chain_no_offset
stratixiii_dqs_delay_chain # (
.dqs_input_frequency (MEM_IF_CLK_PS_STR),
.use_phasectrlin (DQS_USE_PHASECTRL_IN),
.phase_setting (DQS_PHASE_SETTING),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.dqs_phase_shift (DQS_PHASE),
.dqs_offsetctrl_enable ("false"),
.dqs_ctrl_latches_enable (USE_DQS_DELAY_LATCHES)
) delay_chain(
.dqsin (dqs_buffered),
.delayctrlin (chosen_dqs_delay_delayctrlin),
.offsetctrlin (), //(dll_offset_delay_ctrl),
.dqsupdateen (dqs_update_en),
.phasectrlin (dqsinputphasesetting),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dqsbusout (dqs_delayed)
);
end
end
endgenerate
generate
if (MEM_IF_USE_T7 == 1)
begin : gen_dynamic_dqs_T7_delay_chain_gen
// Delayed DQS delay chain - t7
stratixiii_delay_chain dqs_t7_delay
(
.datain (dqs_delayed),
.delayctrlin (dqsbusoutdelaysetting),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqs_delayed2)
);
end
else
begin : gen_ddr_no_dqs_T7_delay_chain
assign dqs_delayed2 = dqs_delayed;
end
endgenerate
generate
if (MEM_IF_MEMTYPE == "QDRII")
begin : qdr_dqsn_delay_chain_gen
if (DQS_DELAY_USES_OFFSET == "true" || DQS_DELAY_USES_OFFSET == "TRUE")
begin
stratixiii_dqs_delay_chain # (
.dqs_input_frequency (MEM_IF_CLK_PS_STR),
.use_phasectrlin (DQS_USE_PHASECTRL_IN),
.phase_setting (DQS_PHASE_SETTING),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.dqs_phase_shift (DQS_PHASE),
.dqs_offsetctrl_enable ("true"),
.dqs_ctrl_latches_enable (USE_DQS_DELAY_LATCHES)
) dqsn_delay_chain(
.dqsin (dqsn_buffered),
.delayctrlin (chosen_dqs_delay_delayctrlin),
.offsetctrlin (dll_offset_delay_ctrl),
.dqsupdateen (dqs_update_en),
.phasectrlin (dqsinputphasesetting),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dqsbusout (dqsn_enable_op)
);
end
else
begin
stratixiii_dqs_delay_chain # (
.dqs_input_frequency (MEM_IF_CLK_PS_STR),
.use_phasectrlin (DQS_USE_PHASECTRL_IN),
.phase_setting (DQS_PHASE_SETTING),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.dqs_phase_shift (DQS_PHASE),
.dqs_offsetctrl_enable ("false"),
.dqs_ctrl_latches_enable (USE_DQS_DELAY_LATCHES)
) dqsn_delay_chain(
.dqsin (dqsn_buffered),
.delayctrlin (chosen_dqs_delay_delayctrlin),
.offsetctrlin (), //(dll_offset_delay_ctrl),
.dqsupdateen (dqs_update_en),
.phasectrlin (dqsinputphasesetting),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
// synopsys translate_on
.dqsbusout (dqsn_enable_op)
);
end
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_dqs_enable_gen
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) ddio(
.datainhi (poa_postamble_en_preset[1]),
.datainlo (poa_postamble_en_preset[0]),
.clkhi (resync_clk_1x),
.clklo (resync_clk_1x),
.muxsel (resync_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.devclrn(),
.devpor(),
.clk(),
// synopsys translate_on
.dataout (dqs_enable_ddio_output)
);
end
else
begin
assign dqs_enable_ddio_output = poa_postamble_en_preset[0];
end
endgenerate
generate
if (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 1)
begin : ddr3_dqs_enable_ctrl_gen
// DQS Enable Control
stratixiii_dqs_enable_ctrl # (
.use_phasectrlin ("true"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.level_dqs_enable ("true"),
.delay_dqs_enable_by_half_cycle ("true"),
.add_phase_transfer_reg ("dynamic"),
.invert_phase ("dynamic")
) dqs_enable_ctrl (
.dqsenablein (dqs_enable_ddio_output),
.clk (resync_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqsenablectrlphasesetting),
.enaphasetransferreg (enadqsenablephasetransferreg),
.phaseinvertctrl (dqsenablectrlphaseinvert),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
.dffextenddqsenable (),
// synopsys translate_on
.dqsenableout (dqs_enable_ctrl_op)
);
// DQS enable delay chain
if (MEM_IF_USE_T11 == 1)
begin : ddr3_using_t11_delay
stratixiii_delay_chain dqs_enable_ctrl_dc1
(
.datain (dqs_enable_ctrl_op),
.delayctrlin ({1'b0,dqsenabledelaysetting}),
// synopsys translate_off
.finedelayctrlin(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqs_enable_ctrl_op_delayed)
);
end
else
begin : ddr3_not_using_t11_delay
assign dqs_enable_ctrl_op_delayed = dqs_enable_ctrl_op;
end
// DQS Enable
stratixiii_dqs_enable dqs_enable_atom(
.dqsin (dqs_delayed2),
.dqsenable (dqs_enable_ctrl_op_delayed),
// synopsys translate_off
.devclrn (),
.devpor (),
// synopsys translate_on
.dqsbusout (dqs_enable_op)
);
// Tie-off unused DQSN enable for DDR :
assign dqsn_enable_op = 1'b0;
end
else if (MEM_IF_MEMTYPE == "DDR2" || MEM_IF_MEMTYPE == "DDR" || (MEM_IF_MEMTYPE == "DDR3" && LEVELLING == 0))
begin : ddr_dqs_enable_ctrl_gen
// DQS Enable Control
stratixiii_dqs_enable_ctrl # (
.use_phasectrlin ("false"),
.phase_setting (0), //zero tap used
.delay_buffer_mode ("high"), // n/a due to zero tap
.level_dqs_enable ("true"),
.delay_dqs_enable_by_half_cycle ("true"),
.add_phase_transfer_reg (ADD_PHASE_TRANSFER_REG_SETTING),
.invert_phase (INVERT_POSTAMBLE_CLK)
) dqs_enable_ctrl (
.dqsenablein (dqs_enable_ddio_output),
.clk (resync_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqsenablectrlphasesetting),
.enaphasetransferreg (enadqsenablephasetransferreg),
.phaseinvertctrl (dqsenablectrlphaseinvert),
// synopsys translate_off
.devclrn (),
.devpor (),
.dffin (),
.dffextenddqsenable (),
// synopsys translate_on
.dqsenableout (dqs_enable_ctrl_op)
);
// DQS enable delay chain If used could be inserted here
assign dqs_enable_ctrl_op_delayed = dqs_enable_ctrl_op;
// DQS Enable
stratixiii_dqs_enable dqs_enable_atom(
.dqsin (dqs_delayed2),
.dqsenable (dqs_enable_ctrl_op_delayed),
// synopsys translate_off
.devclrn (),
.devpor (),
// synopsys translate_on
.dqsbusout (dqs_enable_op)
);
// Tie-off unused DQSN enable for DDR :
assign dqsn_enable_op = 1'b0;
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_dm (
phy_clk_1x,
write_clk_2x,
sc_clk,
scan_din,
scan_update,
scan_enable,
scan_dout,
mem_dm,
wdp_dm3_1x,
wdp_dm2_1x,
wdp_dm1_1x,
wdp_dm0_1x,
dedicated_dll_delay_ctrl,
dqoutputphasesetting,
enaoutputcycledelaysetting,
enaoutputphasetransferreg,
dqoutputphaseinvert,
seriesterminationcontrol,
parallelterminationcontrol
);
parameter MEM_IF_MEMTYPE = "DDR";
parameter LEVELLING = 1;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter ENABLE_DDR3_SEQUENCER = "FALSE";
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_WR_T9_DESKEW_EN = 0;
parameter MEM_IF_WR_T10_DESKEW_EN = 0;
parameter MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL = "FALSE";
parameter OPA_USES_DELAYED_CLK = "false";
parameter SINGLE_LEVELLING_DELAY_CHAIN = "true";
input wire phy_clk_1x;
input wire write_clk_2x;
input wire sc_clk;
input wire scan_din;
input wire scan_update;
input wire scan_enable;
output wire scan_dout;
inout wire mem_dm;
input wire wdp_dm3_1x;
input wire wdp_dm2_1x;
input wire wdp_dm1_1x;
input wire wdp_dm0_1x;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
input wire [`DQSCONFIG_DQ_OP_PHASE_SETTING_WIDTH-1 :0] dqoutputphasesetting;
input wire enaoutputcycledelaysetting;
input wire enaoutputphasetransferreg;
input wire dqoutputphaseinvert;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] seriesterminationcontrol;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] parallelterminationcontrol;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING1_WIDTH-1 :0] dq_outputdelaysetting1;
wire [`IOCONFIG_DQ_OUTPUT_DELAY_SETTING2_WIDTH-1 :0] dq_outputdelaysetting2;
// Internal wires :
wire dqm_l;
wire dqm_h;
wire dqm_aligned;
wire dqm_delayed;
wire dqm_delayed2;
// Write side :
// NB. These atoms should be exactly the same as the DQ write path :
generate
if (DWIDTH_RATIO == 4)
begin : half_rate
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) dqm_ddio_in_h (
.datainhi (wdp_dm3_1x),
.datainlo (wdp_dm2_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqm_h),
.devclrn(),
.devpor()
);
stratixiii_ddio_out # (
.half_rate_mode("true"),
.use_new_clocking_model("true")
) dqm_ddio_in_l(
.datainhi (wdp_dm1_1x),
.datainlo (wdp_dm0_1x),
.clkhi (phy_clk_1x),
.clklo (phy_clk_1x),
.muxsel (phy_clk_1x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.dfflo(),
.dffhi(),
.clk(),
// synopsys translate_on
.dataout (dqm_l),
.devclrn(),
.devpor()
);
end
else
begin : full_rate
assign dqm_l = wdp_dm0_1x;
assign dqm_h = wdp_dm1_1x;
end
endgenerate
// Phase alignment is either via DDIO for DDR/DDR2 or phase alignment atom for DDR3 :
generate
if (MEM_IF_MEMTYPE == "DDR" || MEM_IF_MEMTYPE == "DDR2" || MEM_IF_MEMTYPE == "QDRII" || (MEM_IF_MEMTYPE == "DDR3" & LEVELLING == 0))
begin : ddr_qdr_dm_ddio_gen
// DDIO output
stratixiii_ddio_out # (
.half_rate_mode("false"),
.use_new_clocking_model("true")
) dm_ddio_inst (
.datainhi (dqm_h),
.datainlo (dqm_l),
.clkhi (write_clk_2x),
.clklo (write_clk_2x),
.muxsel (write_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
// synopsys translate_off
.clk (),
.dfflo(),
.dffhi(),
.devclrn(),
.devpor(),
// synopsys translate_on
.dataout (dqm_aligned)
);
end
else
begin : ddr3_dm_opa_gen
// Note : delay_buffer_mode for output_phase_alignment atoms must always
// be tied to "high" :
stratixiii_output_phase_alignment #(
.operation_mode ("ddio_out"),
.use_phasectrlin ("true"),
.phase_setting (0),
.delay_buffer_mode ("high"),
.power_up ("low"),
.async_mode ("clear"),
.sync_mode ("none"),
.add_output_cycle_delay ("dynamic"),
.use_delayed_clock (OPA_USES_DELAYED_CLK),
.phase_setting_for_delayed_clock (2),
.add_phase_transfer_reg ("dynamic"),
.use_phasectrl_clock ("true"),
.invert_phase ("dynamic"),
.use_primary_clock (SINGLE_LEVELLING_DELAY_CHAIN),
.bypass_input_register ("false")
) dm_opa_inst(
.datain ({dqm_h,dqm_l}),
.clk (write_clk_2x),
.delayctrlin (dedicated_dll_delay_ctrl),
.phasectrlin (dqoutputphasesetting),
.areset (1'b0),
.sreset (1'b0),
.clkena (1'b1),
.enaoutputcycledelay (enaoutputcycledelaysetting),
.enaphasetransferreg (enaoutputphasetransferreg),
.phaseinvertctrl (dqoutputphaseinvert),
// synopsys translate_off
.devclrn(), .devpor(),
.dffin(), .dff1t(), .dffddiodataout(),
// synopsys translate_on
.dataout (dqm_aligned)
);
end
endgenerate
generate
if (MEM_IF_WR_T9_DESKEW_EN == 1)
begin : gen_T9_dp_deskew
stratixiii_delay_chain dqm_t9_delay(
.datain (dqm_aligned),
.delayctrlin (dq_outputdelaysetting1),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqm_delayed)
);
end
else
begin : gen_T9_dp_no_deskew
assign dqm_delayed = dqm_aligned;
end
endgenerate
generate
if (MEM_IF_WR_T10_DESKEW_EN == 1)
begin : gen_T10_dp_deskew
stratixiii_delay_chain dqm_t10_delay(
.datain (dqm_delayed),
.delayctrlin ({1'b0, dq_outputdelaysetting2}),
// synopsys translate_off
.devclrn(), .devpor(),
// synopsys translate_on
.dataout (dqm_delayed2)
);
end
else
begin : gen_T10_dp_no_deskew
assign dqm_delayed2 = dqm_delayed;
end
endgenerate
// output buf
stratixiii_io_obuf # (
.bus_hold ( "false"),
.open_drain_output ( "false"),
.shift_series_termination_control (MEM_IF_SHIFT_SERIES_TERMINATION_CONTROL)
) dq_obuf_inst(
.i (dqm_delayed2),
.oe (1'b1),
.dynamicterminationcontrol (1'b0),
// synopsys translate_off
.seriesterminationcontrol(seriesterminationcontrol),
.parallelterminationcontrol(parallelterminationcontrol),
.obar(),
// synopsys translate_on
.o(mem_dm),
.devoe ()
);
// IO_CONFIG - num_dq 0->16
stratixiii_io_config dq_io_config(
.datain(scan_din), // shared per DQS group
.clk(sc_clk),
.ena(scan_enable),
.update(scan_update), // shared per DQS group
// synopsys translate_off
.devclrn(), .devpor(),
.dutycycledelaymode(),
.dutycycledelaysettings(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.padtoinputregisterfinedelaysetting(),
// synopsys translate_on
.padtoinputregisterdelaysetting(),
.outputdelaysetting1(dq_outputdelaysetting1),
.outputdelaysetting2(dq_outputdelaysetting2),
.dataout(scan_dout)
);
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_mux (
phy_clk_1x,
reset_phy_clk_1x_n,
// MUX Outputs to controller :
ctl_address,
ctl_read_req,
ctl_wdata,
ctl_write_req,
ctl_size,
ctl_be,
ctl_refresh_req,
ctl_burstbegin,
// Controller inputs to the MUX :
ctl_ready,
ctl_wdata_req,
ctl_rdata,
ctl_rdata_valid,
ctl_refresh_ack,
ctl_init_done,
// MUX Select line :
ctl_usr_mode_rdy,
// MUX inputs from local interface :
local_address,
local_read_req,
local_wdata,
local_write_req,
local_size,
local_be,
local_refresh_req,
local_burstbegin,
// MUX outputs to sequencer :
mux_seq_controller_ready,
mux_seq_wdata_req,
// MUX inputs from sequencer :
seq_mux_address,
seq_mux_read_req,
seq_mux_wdata,
seq_mux_write_req,
seq_mux_size,
seq_mux_be,
seq_mux_refresh_req,
seq_mux_burstbegin,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
local_autopch_req,
local_powerdn_req,
local_self_rfsh_req,
local_powerdn_ack,
local_self_rfsh_ack,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
ctl_autopch_req,
ctl_powerdn_req,
ctl_self_rfsh_req,
ctl_powerdn_ack,
ctl_self_rfsh_ack,
// Also MUX some signals from the controller to the local interface :
local_ready,
local_wdata_req,
local_init_done,
local_rdata,
local_rdata_valid,
local_refresh_ack
);
parameter LOCAL_IF_AWIDTH = 26;
parameter LOCAL_IF_DWIDTH = 256;
parameter LOCAL_BURST_LEN_BITS = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DWIDTH = 64;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
// MUX Select line :
input wire ctl_usr_mode_rdy;
// MUX inputs from local interface :
input wire [LOCAL_IF_AWIDTH - 1 : 0] local_address;
input wire local_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] local_wdata;
input wire local_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] local_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] local_be;
input wire local_refresh_req;
input wire local_burstbegin;
// MUX inputs from sequencer :
input wire [LOCAL_IF_AWIDTH - 1 : 0] seq_mux_address;
input wire seq_mux_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] seq_mux_wdata;
input wire seq_mux_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] seq_mux_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1:0] seq_mux_be;
input wire seq_mux_refresh_req;
input wire seq_mux_burstbegin;
// MUX Outputs to controller :
output reg [LOCAL_IF_AWIDTH - 1 : 0] ctl_address;
output reg ctl_read_req;
output reg [LOCAL_IF_DWIDTH - 1 : 0] ctl_wdata;
output reg ctl_write_req;
output reg [LOCAL_BURST_LEN_BITS - 1 : 0] ctl_size;
output reg [(LOCAL_IF_DWIDTH/8) - 1:0] ctl_be;
output reg ctl_refresh_req;
output reg ctl_burstbegin;
// The "ready" input from the controller shall be passed to either the
// local interface if in user mode, or the sequencer :
input wire ctl_ready;
output reg local_ready;
output reg mux_seq_controller_ready;
// The controller's "wdata req" output is similarly passed to either
// the local interface if in user mode, or the sequencer :
input wire ctl_wdata_req;
output reg local_wdata_req;
output reg mux_seq_wdata_req;
input wire ctl_init_done;
output reg local_init_done;
input wire [LOCAL_IF_DWIDTH - 1 : 0] ctl_rdata;
output reg [LOCAL_IF_DWIDTH - 1 : 0] local_rdata;
input wire ctl_rdata_valid;
output reg local_rdata_valid;
input wire ctl_refresh_ack;
output reg local_refresh_ack;
//-> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
input wire local_autopch_req;
input wire local_powerdn_req;
input wire local_self_rfsh_req;
output reg local_powerdn_ack;
output reg local_self_rfsh_ack;
// --> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
output reg ctl_autopch_req;
output reg ctl_powerdn_req;
output reg ctl_self_rfsh_req;
input wire ctl_powerdn_ack;
input wire ctl_self_rfsh_ack;
wire local_burstbegin_held;
reg burstbegin_hold;
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
burstbegin_hold <= 1'b0;
else
begin
if (local_ready == 1'b0 && (local_write_req == 1'b1 || local_read_req == 1'b1) && local_burstbegin == 1'b1)
burstbegin_hold <= 1'b1;
else if (local_ready == 1'b1 && (local_write_req == 1'b1 || local_read_req == 1'b1))
burstbegin_hold <= 1'b0;
end
end
// Gate the local burstbegin signal with the held version :
assign local_burstbegin_held = burstbegin_hold || local_burstbegin;
always @*
begin
if (ctl_usr_mode_rdy == 1'b1)
begin
// Pass local interface signals to the controller if ready :
ctl_address = local_address;
ctl_read_req = local_read_req;
ctl_wdata = local_wdata;
ctl_write_req = local_write_req;
ctl_size = local_size;
ctl_be = local_be;
ctl_refresh_req = local_refresh_req;
ctl_burstbegin = local_burstbegin_held;
// If in user mode, pass on the controller's ready
// and wdata request signals to the local interface :
local_ready = ctl_ready;
local_wdata_req = ctl_wdata_req;
local_init_done = ctl_init_done;
local_rdata = ctl_rdata;
local_rdata_valid = ctl_rdata_valid;
local_refresh_ack = ctl_refresh_ack;
// Whilst indicate to the sequencer that the controller is busy :
mux_seq_controller_ready = 1'b0;
mux_seq_wdata_req = 1'b0;
// Autopch_req & Local_power_req changes
ctl_autopch_req = local_autopch_req;
ctl_powerdn_req = local_powerdn_req;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = ctl_powerdn_ack;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
else
begin
// Pass local interface signals to the sequencer if not in user mode :
// NB. The controller will have more address bits than the sequencer, so
// these are zero padded :
ctl_address = seq_mux_address;
ctl_read_req = seq_mux_read_req;
ctl_wdata = seq_mux_wdata;
ctl_write_req = seq_mux_write_req;
ctl_size = seq_mux_size; // NB. Should be tied-off when the mux is instanced
ctl_be = seq_mux_be; // NB. Should be tied-off when the mux is instanced
ctl_refresh_req = local_refresh_req; // NB. Should be tied-off when the mux is instanced
ctl_burstbegin = seq_mux_burstbegin; // NB. Should be tied-off when the mux is instanced
// Indicate to the local IF that the controller is busy :
local_ready = 1'b0;
local_wdata_req = 1'b0;
local_init_done = 1'b0;
local_rdata = {LOCAL_IF_DWIDTH{1'b0}};
local_rdata_valid = 1'b0;
local_refresh_ack = ctl_refresh_ack;
// If not in user mode, pass on the controller's ready
// and wdata request signals to the sequencer :
mux_seq_controller_ready = ctl_ready;
mux_seq_wdata_req = ctl_wdata_req;
// Autopch_req & Local_power_req changes
ctl_autopch_req = 1'b0;
ctl_powerdn_req = 1'b0;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = 1'b0;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
end
endmodule
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
/* -----------------------------------------------------------------------------
// module description
---------------------------------------------------------------------------- */
//
module ddr3_s4_amphy_phy_alt_mem_phy_mimic(
//Inputs
//Clocks
measure_clk, // full rate clock from PLL
mimic_data_in, // Input against which the VT variations
// are tracked (e.g. memory clock)
// Active low reset
reset_measure_clk_n,
//Indicates that the mimic calibration sequence can start
seq_mmc_start, // from sequencer
//Outputs
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
input wire measure_clk;
input wire mimic_data_in;
input wire reset_measure_clk_n;
input wire seq_mmc_start;
output wire mmc_seq_done;
output wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
// Parameters
parameter NUM_MIMIC_SAMPLE_CYCLES = 6;
parameter SHIFT_REG_COUNTER_WIDTH = clogb2(NUM_MIMIC_SAMPLE_CYCLES);
reg [`MIMIC_FSM_WIDTH-1:0] mimic_state;
reg [2:0] seq_mmc_start_metastable;
wire start_edge_detected;
(* altera_attribute=" -name fast_input_register OFF"*) reg [1:0] mimic_data_in_metastable;
wire mimic_data_in_sample;
wire shift_reg_data_out_all_ones;
reg mimic_done_out;
reg mimic_value_captured;
reg [SHIFT_REG_COUNTER_WIDTH : 0] shift_reg_counter;
reg shift_reg_enable;
wire shift_reg_data_in;
reg shift_reg_s_clr;
wire shift_reg_a_clr;
reg [NUM_MIMIC_SAMPLE_CYCLES -1 : 0] shift_reg_data_out;
// shift register which contains the sampled data
always @(posedge measure_clk or posedge shift_reg_a_clr)
begin
if (shift_reg_a_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else
begin
if (shift_reg_s_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else if (shift_reg_enable == 1'b1)
begin
shift_reg_data_out <= {(shift_reg_data_out[NUM_MIMIC_SAMPLE_CYCLES -2 : 0]), shift_reg_data_in};
end
end
end
// Metastable-harden mimic_start :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
seq_mmc_start_metastable <= 0;
end
else
begin
seq_mmc_start_metastable[0] <= seq_mmc_start;
seq_mmc_start_metastable[1] <= seq_mmc_start_metastable[0];
seq_mmc_start_metastable[2] <= seq_mmc_start_metastable[1];
end
end
assign start_edge_detected = seq_mmc_start_metastable[1]
&& !seq_mmc_start_metastable[2];
// Metastable-harden mimic_data_in :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_data_in_metastable <= 0;
end
//some mimic paths configurations have another flop inside the wysiwyg ioe
else
begin
mimic_data_in_metastable[0] <= mimic_data_in;
mimic_data_in_metastable[1] <= mimic_data_in_metastable[0];
end
end
assign mimic_data_in_sample = mimic_data_in_metastable[1];
// Main FSM :
always @(posedge measure_clk or negedge reset_measure_clk_n )
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_state <= `MIMIC_IDLE;
mimic_done_out <= 1'b0;
mimic_value_captured <= 1'b0;
shift_reg_counter <= 0;
shift_reg_enable <= 1'b0;
shift_reg_s_clr <= 1'b0;
end
else
begin
case (mimic_state)
`MIMIC_IDLE : begin
shift_reg_counter <= 0;
mimic_done_out <= 1'b0;
shift_reg_s_clr <= 1'b1;
shift_reg_enable <= 1'b1;
if (start_edge_detected == 1'b1)
begin
mimic_state <= `MIMIC_SAMPLE;
shift_reg_counter <= shift_reg_counter + 1'b1;
shift_reg_s_clr <= 1'b0;
end
else
begin
mimic_state <= `MIMIC_IDLE;
end
end // case: MIMIC_IDLE
`MIMIC_SAMPLE : begin
shift_reg_counter <= shift_reg_counter + 1'b1;
if (shift_reg_counter == NUM_MIMIC_SAMPLE_CYCLES + 1)
begin
mimic_done_out <= 1'b1;
mimic_value_captured <= shift_reg_data_out_all_ones; //captured only here
shift_reg_enable <= 1'b0;
shift_reg_counter <= shift_reg_counter;
mimic_state <= `MIMIC_SEND;
end
end // case: MIMIC_SAMPLE
`MIMIC_SEND : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND1;
/* mimic_value_captured will not change during MIMIC_SEND
it will change next time mimic_done_out is asserted
mimic_done_out will be reset during MIMIC_IDLE
the purpose of the current state is to add one clock cycle
mimic_done_out will be active for 2 measure_clk clock cycles, i.e
the pulses duration will be just one sequencer clock cycle
(which is half rate) */
end // case: MIMIC_SEND
// MIMIC_SEND1 and MIMIC_SEND2 extend the mimic_done_out signal by another 2 measure_clk_2x cycles
// so it is a total of 4 measure clocks long (ie 2 half-rate clock cycles long in total)
`MIMIC_SEND1 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND2;
end
`MIMIC_SEND2 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_IDLE;
end
default : begin
mimic_state <= `MIMIC_IDLE;
end
endcase
end
end
assign shift_reg_data_out_all_ones = (( & shift_reg_data_out) == 1'b1) ? 1'b1
: 1'b0;
// Shift Register assignments
assign shift_reg_data_in = mimic_data_in_sample;
assign shift_reg_a_clr = !reset_measure_clk_n;
// Output assignments
assign mmc_seq_done = mimic_done_out;
assign mmc_seq_value = mimic_value_captured;
endmodule
`default_nettype wire
//
/* -----------------------------------------------------------------------------
// module description
----------------------------------------------------------------------------- */
//
module ddr3_s4_amphy_phy_alt_mem_phy_mimic_debug(
// Inputs
// Clocks
measure_clk, // full rate clock from PLL
// Active low reset
reset_measure_clk_n,
mimic_recapture_debug_data, // from user board button
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
// Parameters
parameter NUM_DEBUG_SAMPLES_TO_STORE = 4096; // can range from 4096 to 524288
parameter PLL_STEPS_PER_CYCLE = 24; // can range from 16 to 48
input wire measure_clk;
input wire reset_measure_clk_n;
input wire mimic_recapture_debug_data;
input wire mmc_seq_done;
input wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
parameter RAM_WR_ADDRESS_WIDTH = clogb2(NUM_DEBUG_SAMPLES_TO_STORE - 1); // can range from 12 to 19
reg s_clr_ram_wr_address_count;
reg [(clogb2(PLL_STEPS_PER_CYCLE)-1) : 0] mimic_sample_count;
reg [RAM_WR_ADDRESS_WIDTH-1 : 0 ] ram_write_address;
wire ram_wr_enable;
wire [0:0] debug_ram_data;
reg clear_ram_wr_enable;
reg [1:0] mimic_recapture_debug_data_metastable;
wire mimic_done_in_dbg; // for internal use, just 1 measure_clk cycles long
reg mmc_seq_done_r;
// generate mimic_done_in_debug : a single clock wide pulse based on the rising edge of mmc_seq_done:
always @ (posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0) // asynchronous reset (active low)
begin
mmc_seq_done_r <= 1'b0;
end
else
begin
mmc_seq_done_r <= mmc_seq_done;
end
end
assign mimic_done_in_dbg = mmc_seq_done && !mmc_seq_done_r;
assign ram_wr_enable = mimic_done_in_dbg && !clear_ram_wr_enable;
assign debug_ram_data[0] = mmc_seq_value;
altsyncram #(
.clock_enable_input_a ( "BYPASS"),
.clock_enable_output_a ( "BYPASS"),
.intended_device_family ( "Stratix II"),
.lpm_hint ( "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MRAM"),
.lpm_type ( "altsyncram"),
.maximum_depth ( 4096),
.numwords_a ( 4096),
.operation_mode ( "SINGLE_PORT"),
.outdata_aclr_a ( "NONE"),
.outdata_reg_a ( "UNREGISTERED"),
.power_up_uninitialized ( "FALSE"),
.widthad_a ( 12),
.width_a ( 1),
.width_byteena_a ( 1)
)
altsyncram_component (
.wren_a ( ram_wr_enable),
.clock0 ( measure_clk),
.address_a ( ram_write_address),
.data_a ( debug_ram_data),
.q_a ( )
);
// Metastability_mimic_recapture_debug_data :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_recapture_debug_data_metastable <= 2'b0;
end
else
begin
mimic_recapture_debug_data_metastable[0] <= mimic_recapture_debug_data;
mimic_recapture_debug_data_metastable[1] <= mimic_recapture_debug_data_metastable[0];
end
end
//mimic_sample_counter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_sample_count <= 0; // (others => '0');
end
else
begin
if (mimic_done_in_dbg == 1'b1)
begin
mimic_sample_count <= mimic_sample_count + 1'b1;
if (mimic_sample_count == PLL_STEPS_PER_CYCLE-1)
begin
mimic_sample_count <= 0; //(others => '0');
end
end
end
end
//RAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b0;
end
else
begin
if (s_clr_ram_wr_address_count == 1'b1) // then --Active high synchronous reset
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b0;
if (mimic_done_in_dbg == 1'b1)
begin
if (ram_write_address != NUM_DEBUG_SAMPLES_TO_STORE-1)
begin
ram_write_address <= ram_write_address + 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b1;
end
end
end
end
end
//ClearRAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
else
begin
if (mimic_recapture_debug_data_metastable[1] == 1'b1)
begin
s_clr_ram_wr_address_count <= 1'b1;
end
else if (mimic_sample_count == 0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
end
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_s4_amphy_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or negedge pre_clear)
begin
if (pre_clear == 1'b0)
begin
ams_pipe <= 0;
end
else
begin
for (i=0; i< PIPE_DEPTH; i = i + 1)
begin
if (i==0)
ams_pipe[i] <= 1'b1;
else
ams_pipe[i] <= ams_pipe[i-1];
end
end // if-else
end // always
// end
assign reset_out = ams_pipe[PIPE_DEPTH-1];
endmodule
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.0 Build 157 04/27/2011
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive STRATIX_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive STRATIX_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive STRATIX_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module stratix_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
STRATIX_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** stratix_mux21
module stratix_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** stratix_mux41
module stratix_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** stratix_and1
module stratix_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** stratix_and16
module stratix_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** stratix_bmux21
module stratix_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** stratix_b17mux21
module stratix_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** stratix_nmux21
module stratix_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** stratix_b5mux21
module stratix_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_asynch_lcell
//
// Description : Verilog simulation model for asynchronous LUT based
// module in Stratix Lcell.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_asynch_lcell (
dataa,
datab,
datac,
datad,
cin,
cin0,
cin1,
inverta,
qfbkin,
regin,
combout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad ;
input cin;
input cin0;
input cin1;
input inverta;
input qfbkin;
// OUTPUT PORTS
output combout;
output cout;
output cout0;
output cout1;
output regin;
// INTERNAL VARIABLES
reg icout;
reg icout0;
reg icout1;
reg data;
reg lut_data;
reg inverta_dataa;
reg [15:0] bin_mask;
integer iop_mode;
reg [1:0] isum_lutc_input;
reg icin_used;
reg icin0_used;
reg icin1_used;
wire qfbk_mode;
// INPUT BUFFERS
wire idataa;
wire idatab;
wire idatac;
wire idatad;
wire icin;
wire icin0;
wire icin1;
wire iinverta;
buf (idataa, dataa);
buf (idatab, datab);
buf (idatac, datac);
buf (idatad, datad);
buf (icin, cin);
buf (icin0, cin0);
buf (icin1, cin1);
buf (iinverta, inverta);
assign qfbk_mode = (sum_lutc_input == "qfbk") ? 1'b1 : 1'b0;
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(cin0 => combout) = (0, 0) ;
(cin1 => combout) = (0, 0) ;
(inverta => combout) = (0, 0) ;
if (qfbk_mode == 1'b1)
(qfbkin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
(cin0 => cout) = (0, 0) ;
(cin1 => cout) = (0, 0) ;
(inverta => cout) = (0, 0);
(dataa => cout0) = (0, 0);
(datab => cout0) = (0, 0);
(cin0 => cout0) = (0, 0) ;
(inverta => cout0) = (0, 0);
(dataa => cout1) = (0, 0);
(datab => cout1) = (0, 0);
(cin1 => cout1) = (0, 0) ;
(inverta => cout1) = (0, 0);
(dataa => regin) = (0, 0) ;
(datab => regin) = (0, 0) ;
(datac => regin) = (0, 0) ;
(datad => regin) = (0, 0) ;
(cin => regin) = (0, 0) ;
(cin0 => regin) = (0, 0) ;
(cin1 => regin) = (0, 0) ;
(inverta => regin) = (0, 0) ;
if (qfbk_mode == 1'b1)
(qfbkin => regin) = (0, 0) ;
endspecify
function [16:1] str_to_bin ;
input [8*4:1] s;
reg [8*4:1] reg_s;
reg [4:1] digit [8:1];
reg [8:1] tmp;
integer m;
integer ivalue ;
begin
ivalue = 0;
reg_s = s;
for (m=1; m<=4; m= m+1 )
begin
tmp = reg_s[32:25];
digit[m] = tmp & 8'b00001111;
reg_s = reg_s << 8;
if (tmp[7] == 'b1)
digit[m] = digit[m] + 9;
end
str_to_bin = {digit[1], digit[2], digit[3], digit[4]};
end
endfunction
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
bin_mask = str_to_bin(lut_mask);
if (operation_mode == "normal")
iop_mode = 0; // normal mode
else if (operation_mode == "arithmetic")
iop_mode = 1; // arithmetic mode
else
begin
$display ("Error: Invalid operation_mode specified\n");
$display ("Time: %0t Instance: %m", $time);
iop_mode = 2;
end
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else if (sum_lutc_input == "qfbk")
isum_lutc_input = 2;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 3;
end
if (cin_used == "true")
icin_used = 1;
else if (cin_used == "false")
icin_used = 0;
if (cin0_used == "true")
icin0_used = 1;
else if (cin0_used == "false")
icin0_used = 0;
if (cin1_used == "true")
icin1_used = 1;
else if (cin1_used == "false")
icin1_used = 0;
end
always @(idatad or idatac or idatab or idataa or icin or
icin0 or icin1 or iinverta or qfbkin)
begin
if (iinverta === 'b1) //invert dataa
inverta_dataa = !idataa;
else
inverta_dataa = idataa;
if (iop_mode == 0) // normal mode
begin
if (isum_lutc_input == 0) // datac
begin
data = lut4(bin_mask, inverta_dataa, idatab,
idatac, idatad);
end
else if (isum_lutc_input == 1) // cin
begin
if (icin0_used == 1 || icin1_used == 1)
begin
if (icin_used == 1)
data = (icin === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
idatad);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
idatad);
end
else
data = lut4(bin_mask, inverta_dataa, idatab,
icin, idatad);
end
else if(isum_lutc_input == 2) // qfbk
begin
data = lut4(bin_mask, inverta_dataa, idatab,
qfbkin, idatad);
end
end
else if (iop_mode == 1) // arithmetic mode
begin
// sum LUT
if (isum_lutc_input == 0) // datac
begin
data = lut4(bin_mask, inverta_dataa, idatab,
idatac, 'b1);
end
else if (isum_lutc_input == 1) // cin
begin
if (icin0_used == 1 || icin1_used == 1)
begin
if (icin_used == 1)
data = (icin === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
'b1);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
'b1);
end
else if (icin_used == 1)
data = lut4(bin_mask, inverta_dataa, idatab,
icin, 'b1);
else // cin is not used, inverta is used as cin
data = lut4(bin_mask, inverta_dataa, idatab,
iinverta, 'b1);
end
else if(isum_lutc_input == 2) // qfbk
begin
data = lut4(bin_mask, inverta_dataa, idatab,
qfbkin, 'b1);
end
// carry LUT
icout0 = lut4(bin_mask, inverta_dataa, idatab, icin0, 'b0);
icout1 = lut4(bin_mask, inverta_dataa, idatab, icin1, 'b0);
if (icin_used == 1)
begin
if (icin0_used == 1 || icin1_used == 1)
icout = (icin === 'b0) ? icout0 : icout1;
else
icout = lut4(bin_mask, inverta_dataa, idatab,
icin, 'b0);
end
else // inverta is used in place of cin
begin
if (icin0_used == 1 || icin1_used == 1)
icout = (iinverta === 'b0) ? icout0 : icout1;
else
icout = lut4(bin_mask, inverta_dataa, idatab,
iinverta, 'b0);
end
end
end
and (combout, data, 1'b1) ;
and (cout, icout, 1'b1) ;
and (cout0, icout0, 1'b1) ;
and (cout1, icout1, 1'b1) ;
and (regin, data, 1'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lcell_register
//
// Description : Verilog simulation model for register with control
// signals module in Stratix Lcell.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lcell_register (
clk,
aclr,
aload,
sclr,
sload,
ena,
datain,
datac,
regcascin,
devclrn,
devpor,
regout,
qfbkout
);
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter power_up = "low";
parameter x_on_violation = "on";
// INPUT PORTS
input clk;
input ena;
input aclr;
input aload;
input sclr;
input sload;
input datain;
input datac;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output regout;
output qfbkout;
// INTERNAL VARIABLES
reg iregout;
wire reset;
wire nosload;
reg regcascin_viol;
reg datain_viol, datac_viol;
reg sclr_viol, sload_viol;
reg ena_viol, clk_per_viol;
reg violation;
reg clk_last_value;
reg ipower_up;
reg icascade_mode;
reg isynch_mode;
reg ix_on_violation;
// INPUT BUFFERS
wire clk_in;
wire iaclr;
wire iaload;
wire isclr;
wire isload;
wire iena;
wire idatac;
wire iregcascin;
wire idatain;
buf (clk_in, clk);
buf (iaclr, aclr);
buf (iaload, aload);
buf (isclr, sclr);
buf (isload, sload);
buf (iena, ena);
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
assign reset = devpor && devclrn && (!iaclr) && (iena);
assign nosload = reset && (!isload);
specify
$setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
$setuphold (posedge clk &&& nosload, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: iregout)) = (0, 0) ;
(datac => regout) = (0, 0) ;
(posedge clk => (qfbkout +: iregout)) = 0 ;
(posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
(posedge aload => (qfbkout +: iregout)) = (0, 0) ;
(datac => qfbkout) = (0, 0) ;
endspecify
initial
begin
violation = 0;
clk_last_value = 'b0;
if (power_up == "low")
begin
iregout <= 'b0;
ipower_up = 0;
end
else if (power_up == "high")
begin
iregout <= 'b1;
ipower_up = 1;
end
if (register_cascade_mode == "on")
icascade_mode = 1;
else
icascade_mode = 0;
if (synch_mode == "on" )
isynch_mode = 1;
else
isynch_mode = 0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol
or sload_viol or ena_viol or clk_per_viol)
begin
if (ix_on_violation == 1)
violation = 1;
end
always @ (clk_in or idatac or iaclr or posedge iaload
or devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout <= 'bx;
end
else
begin
if (devpor == 'b0)
begin
if (ipower_up == 0) // "low"
iregout <= 'b0;
else if (ipower_up == 1) // "high"
iregout <= 'b1;
end
else if (devclrn == 'b0)
iregout <= 'b0;
else if (iaclr === 'b1)
iregout <= 'b0 ;
else if (iaload === 'b1)
iregout <= idatac;
else if (iena === 'b1 && clk_in === 'b1 &&
clk_last_value === 'b0)
begin
if (isynch_mode == 1)
begin
if (isclr === 'b1)
iregout <= 'b0 ;
else if (isload === 'b1)
iregout <= idatac;
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
end
clk_last_value = clk_in;
end
and (regout, iregout, 1'b1);
and (qfbkout, iregout, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lcell
//
// Description : Verilog simulation model for Stratix Lcell, including
// the following sub module(s):
// 1. stratix_asynch_lcell
// 2. stratix_lcell_register
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lcell (
clk,
dataa,
datab,
datac,
datad,
aclr,
aload,
sclr,
sload,
ena,
cin,
cin0,
cin1,
inverta,
regcascin,
devclrn,
devpor,
combout,
regout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "reg_and_comb";
parameter lpm_type = "stratix_lcell";
parameter x_on_violation = "on";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad;
input clk;
input aclr;
input aload;
input sclr;
input sload;
input ena;
input cin;
input cin0;
input cin1;
input inverta;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output combout;
output regout;
output cout;
output cout0;
output cout1;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES
wire dffin, qfbkin;
stratix_asynch_lcell lecomb (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.cin(cin),
.cin0(cin0),
.cin1(cin1),
.inverta(inverta),
.qfbkin(qfbkin),
.regin(dffin),
.combout(combout),
.cout(cout),
.cout0(cout0),
.cout1(cout1)
);
defparam lecomb.operation_mode = operation_mode;
defparam lecomb.sum_lutc_input = sum_lutc_input;
defparam lecomb.cin_used = cin_used;
defparam lecomb.cin0_used = cin0_used;
defparam lecomb.cin1_used = cin1_used;
defparam lecomb.lut_mask = lut_mask;
stratix_lcell_register lereg (
.clk(clk),
.aclr(aclr),
.aload(aload),
.sclr(sclr),
.sload(sload),
.ena(ena),
.datain(dffin),
.datac(datac),
.regcascin(regcascin),
.devclrn(devclrn),
.devpor(devpor),
.regout(regout),
.qfbkout(qfbkin)
);
defparam lereg.synch_mode = synch_mode;
defparam lereg.register_cascade_mode = register_cascade_mode;
defparam lereg.power_up = power_up;
defparam lereg.x_on_violation = x_on_violation;
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_asynch_io
//
// Description : Verilog simulation model for asynchronous
// module in Stratix IO.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_asynch_io
(
datain,
oe,
regin,
ddioregin,
padio,
delayctrlin,
combout,
regout,
ddioregout,
dqsundelayedout
);
// INPUT PORTS
input datain;
input oe;
input regin;
input ddioregin;
input delayctrlin;
// OUTPUT PORTS
output combout;
output regout;
output ddioregout;
output dqsundelayedout;
// INPUT/OUTPUT PORTS
inout padio;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter phase_shift = "0";
parameter input_frequency = "10000 ps";
// INTERNAL VARIABLES
reg prev_value;
reg tmp_padio, tmp_combout;
reg buf_control;
reg combout_tmp;
reg [1:0] iop_mode;
integer dqs_delay;
// INPUT BUFFERS
wire datain_in;
wire oe_in;
wire delayctrlin_ipd;
buf(datain_in, datain);
buf(oe_in, oe);
buf (delayctrlin_ipd, delayctrlin);
tri padio_tmp;
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
specify
(padio => combout) = (0,0);
(padio => dqsundelayedout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(ddioregin => ddioregout) = (0, 0);
(regin => regout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
dqs_delay = (str2int(phase_shift) * str2int(input_frequency))/360;
if (operation_mode == "input")
iop_mode = 0;
else if (operation_mode == "output")
iop_mode = 1;
else if (operation_mode == "bidir")
iop_mode = 2;
else
begin
$display ("Error: Invalid operation_mode specified\n");
$display ("Time: %0t Instance: %m", $time);
iop_mode = 3;
end
end
always @(delayctrlin_ipd)
begin
if (delayctrlin_ipd == 1'b1)
dqs_delay = (str2int(phase_shift) * str2int(input_frequency))/360;
else if (delayctrlin_ipd == 1'b0)
dqs_delay = 0;
else
begin
$display($time, " Warning: Illegal value detected on 'delayctrlin' input.");
$display ("Time: %0t Instance: %m", $time);
dqs_delay = 0;
end
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if ( operation_mode == "input")
begin
if (padio == 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if (iop_mode == 1 || iop_mode == 2) // output or bidir
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in == 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if (iop_mode == 2) // bidir
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (iop_mode == 2) // bidir
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end
if (iop_mode == 1) // output
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if (iop_mode == 0) // input
begin
tmp_combout = padio;
end
else if (iop_mode == 1 || iop_mode == 2) // output or bidir
begin
if (iop_mode == 2) // bidir
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in == 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in stratix io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
combout_tmp <= #(dqs_delay) tmp_combout;
end
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, combout_tmp, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
and (ddioregout, ddioregin, 1'b1);
and (dqsundelayedout, tmp_combout, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_io_register
//
// Description : Verilog simulation model for register with control
// signals module in Stratix IO.
//
///////////////////////////////////////////////////////////////////////
module stratix_io_register
(
clk,
datain,
ena,
sreset,
areset,
devclrn,
devpor,
regout
);
parameter async_reset = "none";
parameter sync_reset = "none";
parameter power_up = "low";
// INPUT PORTS
input clk;
input ena;
input datain;
input areset;
input sreset;
input devclrn;
input devpor;
// OUTPUT PORTS
output regout;
// INTERNAL VARIABLES
reg iregout;
wire reset, is_areset_clear, is_areset_preset;
reg datain_viol;
reg sreset_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
// INPUT BUFFERS
wire clk_in;
wire idatain;
wire iareset;
wire isreset;
wire iena;
buf (clk_in, clk);
buf (idatain, datain);
buf (iareset, areset);
buf (isreset, sreset);
buf (iena, ena);
assign reset = devpor && devclrn
&& !(iareset && async_reset != "none") && (iena);
assign is_areset_clear = (async_reset == "clear")?1'b1:1'b0;
assign is_areset_preset = (async_reset == "preset")?1'b1:1'b0;
specify
$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sreset, 0, 0, sreset_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
if (is_areset_clear == 1'b1)
(posedge areset => (regout +: 1'b0)) = (0,0);
if ( is_areset_preset == 1'b1)
(posedge areset => (regout +: 1'b1)) = (0,0);
endspecify
initial
begin
violation = 0;
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
always @ (datain_viol or sreset_viol or ena_viol)
begin
violation = 1;
end
always @ (clk_in or posedge iareset or negedge devclrn or
negedge devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout = 'bx;
end
else if (devpor == 'b0)
begin
if (power_up == "low")
iregout = 'b0;
else if (power_up == "high")
iregout = 'b1;
end
else if (devclrn == 'b0)
iregout = 'b0;
else if (async_reset == "clear" && iareset == 'b1)
iregout = 'b0 ;
else if (async_reset == "preset" && iareset == 'b1 )
iregout = 'b1;
else if (iena == 'b1 && clk_in == 'b1 && clk_last_value == 'b0)
begin
if (sync_reset == "clear" && isreset == 'b1)
iregout = 'b0 ;
else if (sync_reset == "preset" && isreset == 'b1)
iregout = 'b1;
else
iregout = idatain ;
end
clk_last_value = clk_in;
end
and (regout, iregout, 'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lcell_register
//
// Description : Verilog simulation model for register with control
// signals module in Stratix Lcell.
//
///////////////////////////////////////////////////////////////////////
module stratix_io
(
datain,
ddiodatain,
oe,
outclk,
outclkena,
inclk,
inclkena,
areset,
sreset,
delayctrlin,
devclrn,
devpor,
devoe,
padio,
combout,
regout,
ddioregout,
dqsundelayedout
);
parameter operation_mode = "input";
parameter ddio_mode = "none";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_sync_reset = "none";
parameter output_power_up = "low";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_sync_reset = "none";
parameter oe_power_up = "low";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_sync_reset = "none";
parameter input_power_up = "low";
parameter extend_oe_disable = "false";
parameter sim_dll_phase_shift = "0";
parameter sim_dqs_input_frequency = "10000 ps";
parameter lpm_type = "stratix_io";
// INPUT/OUTPUT PORTS
inout padio;
// INPUT PORTS
input datain;
input ddiodatain;
input oe;
input outclk;
input outclkena;
input inclk;
input inclkena;
input areset;
input sreset;
input delayctrlin;
input devclrn;
input devpor;
input devoe;
// OUTPUT PORTS
output combout;
output regout;
output ddioregout;
output dqsundelayedout;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
// INTERNAL VARIABLES
wire oe_reg_out, oe_pulse_reg_out;
wire in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out;
wire out_reg_out, out_ddio_reg_out;
wire out_clk_ena, oe_clk_ena;
wire tmp_datain;
wire ddio_data;
wire oe_out;
wire outclk_delayed;
assign out_clk_ena = (tie_off_output_clock_enable == "false") ? outclkena : 1'b1;
assign oe_clk_ena = (tie_off_oe_clock_enable == "false") ? outclkena : 1'b1;
//input register
stratix_io_register in_reg
(
.regout(in_reg_out),
.clk(inclk),
.ena(inclkena),
.datain(padio),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam in_reg.async_reset = input_async_reset;
defparam in_reg.sync_reset = input_sync_reset;
defparam in_reg.power_up = input_power_up;
// in_ddio0_reg
stratix_io_register in_ddio0_reg
(
.regout(in_ddio0_reg_out),
.clk(!inclk),
.ena (inclkena),
.datain(padio),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam in_ddio0_reg.async_reset = input_async_reset;
defparam in_ddio0_reg.sync_reset = input_sync_reset;
defparam in_ddio0_reg.power_up = input_power_up;
// in_ddio1_reg
// this register has no sync_reset
stratix_io_register in_ddio1_reg
(
.regout(in_ddio1_reg_out),
.clk(inclk),
.ena(inclkena),
.datain(in_ddio0_reg_out),
.areset(areset),
.sreset(1'b0),
.devpor(devpor),
.devclrn(devclrn)
);
defparam in_ddio1_reg.async_reset = input_async_reset;
defparam in_ddio1_reg.sync_reset = "none";
defparam in_ddio1_reg.power_up = input_power_up;
// out_reg
stratix_io_register out_reg
(
.regout(out_reg_out),
.clk(outclk),
.ena(out_clk_ena),
.datain(datain),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam out_reg.async_reset = output_async_reset;
defparam out_reg.sync_reset = output_sync_reset;
defparam out_reg.power_up = output_power_up;
// out ddio reg
stratix_io_register out_ddio_reg
(
.regout(out_ddio_reg_out),
.clk(outclk),
.ena(out_clk_ena),
.datain(ddiodatain),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam out_ddio_reg.async_reset = output_async_reset;
defparam out_ddio_reg.sync_reset = output_sync_reset;
defparam out_ddio_reg.power_up = output_power_up;
// oe reg
stratix_io_register oe_reg
(
.regout (oe_reg_out),
.clk(outclk),
.ena(oe_clk_ena),
.datain(oe),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam oe_reg.async_reset = oe_async_reset;
defparam oe_reg.sync_reset = oe_sync_reset;
defparam oe_reg.power_up = oe_power_up;
// oe_pulse reg
stratix_io_register oe_pulse_reg
(
.regout(oe_pulse_reg_out),
.clk(!outclk),
.ena(oe_clk_ena),
.datain(oe_reg_out),
.areset(areset),
.sreset(sreset),
.devpor(devpor),
.devclrn(devclrn)
);
defparam oe_pulse_reg.async_reset = oe_async_reset;
defparam oe_pulse_reg.sync_reset = oe_sync_reset;
defparam oe_pulse_reg.power_up = oe_power_up;
assign oe_out = (oe_register_mode == "register") ?
(extend_oe_disable == "true" ? oe_pulse_reg_out
&& oe_reg_out : oe_reg_out) : oe;
stratix_and1 sel_delaybuf
(
.Y(outclk_delayed),
.IN1(outclk)
);
stratix_mux21 ddio_data_mux
(
.MO (ddio_data),
.A (out_ddio_reg_out),
.B (out_reg_out),
.S (outclk_delayed)
);
assign tmp_datain = (ddio_mode == "output" || ddio_mode == "bidir") ?
ddio_data : ((operation_mode == "output" ||
operation_mode == "bidir") ?
((output_register_mode == "register")
? out_reg_out : datain) : 'b0);
// timing info in case output and/or input are not registered.
stratix_asynch_io inst1
(
.datain(tmp_datain),
.oe(oe_out),
.regin(in_reg_out),
.ddioregin(in_ddio1_reg_out),
.padio(padio),
.delayctrlin(delayctrlin),
.combout(combout),
.regout(regout),
.ddioregout(ddioregout),
.dqsundelayedout(dqsundelayedout)
);
defparam inst1.operation_mode = operation_mode;
defparam inst1.bus_hold = bus_hold;
defparam inst1.open_drain_output = open_drain_output;
defparam inst1.phase_shift = sim_dll_phase_shift;
defparam inst1.input_frequency = sim_dqs_input_frequency;
endmodule // stratix_io
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_REGISTER
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_register
(
data,
clk,
aclr,
if_aclr,
ena,
async,
dataout
);
parameter data_width = 72;
parameter power_up = 1'b0;
input [71:0] data;
input clk;
input aclr;
input ena;
input async;
input if_aclr;
output [71:0] dataout;
wire [71:0] data_ipd;
wire clk_ipd;
wire aclr_ipd;
wire ena_ipd;
wire reset;
wire [71:0] dataout_tbuf;
wire [71:0] dataout_tmp;
reg [71:0] dataout_reg;
reg [71:0] dataout_reg_c;
reg viol_notifier; // USED FOR DELAY
assign dataout_tbuf = dataout_tmp;
assign reset = (!aclr_ipd) && (ena_ipd);
buf data_buf0(data_ipd[0], data[0]);
buf data_buf1(data_ipd[1], data[1]);
buf data_buf2(data_ipd[2], data[2]);
buf data_buf3(data_ipd[3], data[3]);
buf data_buf4(data_ipd[4], data[4]);
buf data_buf5(data_ipd[5], data[5]);
buf data_buf6(data_ipd[6], data[6]);
buf data_buf7(data_ipd[7], data[7]);
buf data_buf8(data_ipd[8], data[8]);
buf data_buf9(data_ipd[9], data[9]);
buf data_buf10(data_ipd[10], data[10]);
buf data_buf11(data_ipd[11], data[11]);
buf data_buf12(data_ipd[12], data[12]);
buf data_buf13(data_ipd[13], data[13]);
buf data_buf14(data_ipd[14], data[14]);
buf data_buf15(data_ipd[15], data[15]);
buf data_buf16(data_ipd[16], data[16]);
buf data_buf17(data_ipd[17], data[17]);
buf data_buf18(data_ipd[18], data[18]);
buf data_buf19(data_ipd[19], data[19]);
buf data_buf20(data_ipd[20], data[20]);
buf data_buf21(data_ipd[21], data[21]);
buf data_buf22(data_ipd[22], data[22]);
buf data_buf23(data_ipd[23], data[23]);
buf data_buf24(data_ipd[24], data[24]);
buf data_buf25(data_ipd[25], data[25]);
buf data_buf26(data_ipd[26], data[26]);
buf data_buf27(data_ipd[27], data[27]);
buf data_buf28(data_ipd[28], data[28]);
buf data_buf29(data_ipd[29], data[29]);
buf data_buf30(data_ipd[30], data[30]);
buf data_buf31(data_ipd[31], data[31]);
buf data_buf32(data_ipd[32], data[32]);
buf data_buf33(data_ipd[33], data[33]);
buf data_buf34(data_ipd[34], data[34]);
buf data_buf35(data_ipd[35], data[35]);
buf data_buf36(data_ipd[36], data[36]);
buf data_buf37(data_ipd[37], data[37]);
buf data_buf38(data_ipd[38], data[38]);
buf data_buf39(data_ipd[39], data[39]);
buf data_buf40(data_ipd[40], data[40]);
buf data_buf41(data_ipd[41], data[41]);
buf data_buf42(data_ipd[42], data[42]);
buf data_buf43(data_ipd[43], data[43]);
buf data_buf44(data_ipd[44], data[44]);
buf data_buf45(data_ipd[45], data[45]);
buf data_buf46(data_ipd[46], data[46]);
buf data_buf47(data_ipd[47], data[47]);
buf data_buf48(data_ipd[48], data[48]);
buf data_buf49(data_ipd[49], data[49]);
buf data_buf50(data_ipd[50], data[50]);
buf data_buf51(data_ipd[51], data[51]);
buf data_buf52(data_ipd[52], data[52]);
buf data_buf53(data_ipd[53], data[53]);
buf data_buf54(data_ipd[54], data[54]);
buf data_buf55(data_ipd[55], data[55]);
buf data_buf56(data_ipd[56], data[56]);
buf data_buf57(data_ipd[57], data[57]);
buf data_buf58(data_ipd[58], data[58]);
buf data_buf59(data_ipd[59], data[59]);
buf data_buf60(data_ipd[60], data[60]);
buf data_buf61(data_ipd[61], data[61]);
buf data_buf62(data_ipd[62], data[62]);
buf data_buf63(data_ipd[63], data[63]);
buf data_buf64(data_ipd[64], data[64]);
buf data_buf65(data_ipd[65], data[65]);
buf data_buf66(data_ipd[66], data[66]);
buf data_buf67(data_ipd[67], data[67]);
buf data_buf68(data_ipd[68], data[68]);
buf data_buf69(data_ipd[69], data[69]);
buf data_buf70(data_ipd[70], data[70]);
buf data_buf71(data_ipd[71], data[71]);
buf dataout_buf0(dataout[0], dataout_tbuf[0]);
buf dataout_buf1(dataout[1], dataout_tbuf[1]);
buf dataout_buf2(dataout[2], dataout_tbuf[2]);
buf dataout_buf3(dataout[3], dataout_tbuf[3]);
buf dataout_buf4(dataout[4], dataout_tbuf[4]);
buf dataout_buf5(dataout[5], dataout_tbuf[5]);
buf dataout_buf6(dataout[6], dataout_tbuf[6]);
buf dataout_buf7(dataout[7], dataout_tbuf[7]);
buf dataout_buf8(dataout[8], dataout_tbuf[8]);
buf dataout_buf9(dataout[9], dataout_tbuf[9]);
buf dataout_buf10(dataout[10], dataout_tbuf[10]);
buf dataout_buf11(dataout[11], dataout_tbuf[11]);
buf dataout_buf12(dataout[12], dataout_tbuf[12]);
buf dataout_buf13(dataout[13], dataout_tbuf[13]);
buf dataout_buf14(dataout[14], dataout_tbuf[14]);
buf dataout_buf15(dataout[15], dataout_tbuf[15]);
buf dataout_buf16(dataout[16], dataout_tbuf[16]);
buf dataout_buf17(dataout[17], dataout_tbuf[17]);
buf dataout_buf18(dataout[18], dataout_tbuf[18]);
buf dataout_buf19(dataout[19], dataout_tbuf[19]);
buf dataout_buf20(dataout[20], dataout_tbuf[20]);
buf dataout_buf21(dataout[21], dataout_tbuf[21]);
buf dataout_buf22(dataout[22], dataout_tbuf[22]);
buf dataout_buf23(dataout[23], dataout_tbuf[23]);
buf dataout_buf24(dataout[24], dataout_tbuf[24]);
buf dataout_buf25(dataout[25], dataout_tbuf[25]);
buf dataout_buf26(dataout[26], dataout_tbuf[26]);
buf dataout_buf27(dataout[27], dataout_tbuf[27]);
buf dataout_buf28(dataout[28], dataout_tbuf[28]);
buf dataout_buf29(dataout[29], dataout_tbuf[29]);
buf dataout_buf30(dataout[30], dataout_tbuf[30]);
buf dataout_buf31(dataout[31], dataout_tbuf[31]);
buf dataout_buf32(dataout[32], dataout_tbuf[32]);
buf dataout_buf33(dataout[33], dataout_tbuf[33]);
buf dataout_buf34(dataout[34], dataout_tbuf[34]);
buf dataout_buf35(dataout[35], dataout_tbuf[35]);
buf dataout_buf36(dataout[36], dataout_tbuf[36]);
buf dataout_buf37(dataout[37], dataout_tbuf[37]);
buf dataout_buf38(dataout[38], dataout_tbuf[38]);
buf dataout_buf39(dataout[39], dataout_tbuf[39]);
buf dataout_buf40(dataout[40], dataout_tbuf[40]);
buf dataout_buf41(dataout[41], dataout_tbuf[41]);
buf dataout_buf42(dataout[42], dataout_tbuf[42]);
buf dataout_buf43(dataout[43], dataout_tbuf[43]);
buf dataout_buf44(dataout[44], dataout_tbuf[44]);
buf dataout_buf45(dataout[45], dataout_tbuf[45]);
buf dataout_buf46(dataout[46], dataout_tbuf[46]);
buf dataout_buf47(dataout[47], dataout_tbuf[47]);
buf dataout_buf48(dataout[48], dataout_tbuf[48]);
buf dataout_buf49(dataout[49], dataout_tbuf[49]);
buf dataout_buf50(dataout[50], dataout_tbuf[50]);
buf dataout_buf51(dataout[51], dataout_tbuf[51]);
buf dataout_buf52(dataout[52], dataout_tbuf[52]);
buf dataout_buf53(dataout[53], dataout_tbuf[53]);
buf dataout_buf54(dataout[54], dataout_tbuf[54]);
buf dataout_buf55(dataout[55], dataout_tbuf[55]);
buf dataout_buf56(dataout[56], dataout_tbuf[56]);
buf dataout_buf57(dataout[57], dataout_tbuf[57]);
buf dataout_buf58(dataout[58], dataout_tbuf[58]);
buf dataout_buf59(dataout[59], dataout_tbuf[59]);
buf dataout_buf60(dataout[60], dataout_tbuf[60]);
buf dataout_buf61(dataout[61], dataout_tbuf[61]);
buf dataout_buf62(dataout[62], dataout_tbuf[62]);
buf dataout_buf63(dataout[63], dataout_tbuf[63]);
buf dataout_buf64(dataout[64], dataout_tbuf[64]);
buf dataout_buf65(dataout[65], dataout_tbuf[65]);
buf dataout_buf66(dataout[66], dataout_tbuf[66]);
buf dataout_buf67(dataout[67], dataout_tbuf[67]);
buf dataout_buf68(dataout[68], dataout_tbuf[68]);
buf dataout_buf69(dataout[69], dataout_tbuf[69]);
buf dataout_buf70(dataout[70], dataout_tbuf[70]);
buf dataout_buf71(dataout[71], dataout_tbuf[71]);
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
initial
begin
if(power_up)
begin
dataout_reg <= ~(71'b0);
dataout_reg_c <= ~(71'b0);
end
else
begin
dataout_reg <= 'b0;
dataout_reg_c <= 'b0;
end
end
specify
specparam TSU = 0; // Set up time
specparam TH = 0; // Hold time
specparam TCO = 0; // Clock to Output time
specparam TCLR = 0; // Clear time
specparam TCLR_MIN_PW = 0;// Minimum pulse width of clear
specparam TPRE = 0; // Preset time
specparam TPRE_MIN_PW = 0;// Minimum pulse width of preset
specparam TCLK_MIN_PW = 0;// Minimum pulse width of clock
specparam TCE_MIN_PW = 0; // Minimum pulse width of clock enable
specparam TCLKL = 0; // Minimum clock low time
specparam TCLKH = 0; // Minimum clock high time
$setup (data, posedge clk &&& reset, 0, viol_notifier);
$hold (posedge clk &&& reset, data, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, ena, 0, viol_notifier );
(posedge aclr => (dataout +: 'b0)) = (0,0);
(posedge clk => (dataout +: dataout_tmp)) = (0,0);
endspecify
// ACLR
always @(posedge clk_ipd or posedge aclr_ipd)
begin
if (aclr_ipd == 1'b1)
dataout_reg_c <= 'b0;
else if (ena_ipd == 1'b1)
dataout_reg_c <= data_ipd;
else
dataout_reg_c <= dataout_reg_c;
end
// !ACLR
always @(posedge clk_ipd)
begin
if (ena_ipd == 1'b1)
dataout_reg <= data_ipd;
else
dataout_reg <= dataout_reg;
end
assign dataout_tmp = (async ? data_ipd : (if_aclr ? dataout_reg_c : dataout_reg));
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_MULT_INTERNAL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_mult_internal
(
dataa,
datab,
signa,
signb,
scanouta,
scanoutb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = 36;
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
output [dataa_width-1:0] scanouta;
output [datab_width-1:0] scanoutb;
output [35:0] dataout;
wire [35:0] dataout_s;
wire neg;
wire [35:0] dataout_tmp;
wire [dataa_width-1:0] abs_a;
wire [datab_width-1:0] abs_b;
wire [17:0] dataa_tmp;
wire [17:0] datab_tmp;
wire [17:0] scanouta_tmp;
wire [17:0] scanoutb_tmp;
wire [(dataa_width+datab_width)-1:0] abs_output;
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(dataa => scanouta) = (0, 0);
(datab => scanoutb) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
buf dataa_buf [dataa_width-1:0] (dataa_tmp[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_tmp[datab_width-1:0], datab);
assign neg = ((dataa_tmp[dataa_width-1] && signa) ^ (datab_tmp[datab_width-1] && signb));
assign abs_a = (signa && dataa_tmp[dataa_width-1]) ? (~dataa_tmp[dataa_width-1:0] + 1) : dataa_tmp[dataa_width-1:0];
assign abs_b = (signb && datab_tmp[datab_width-1]) ? (~datab_tmp[datab_width-1:0] + 1) : datab_tmp[datab_width-1:0];
assign scanouta_tmp = dataa_tmp;
assign scanoutb_tmp = datab_tmp;
assign abs_output = abs_a * abs_b;
assign dataout_tmp = neg ? (~abs_output + 1) : abs_output;
buf scanouta_buf [dataa_width-1:0] (scanouta, scanouta_tmp[dataa_width-1:0]);
buf scanoutb_buf [datab_width-1:0] (scanoutb, scanoutb_tmp[datab_width-1:0]);
buf dataout_buf0(dataout[0], dataout_tmp[0]);
buf dataout_buf1(dataout[1], dataout_tmp[1]);
buf dataout_buf2(dataout[2], dataout_tmp[2]);
buf dataout_buf3(dataout[3], dataout_tmp[3]);
buf dataout_buf4(dataout[4], dataout_tmp[4]);
buf dataout_buf5(dataout[5], dataout_tmp[5]);
buf dataout_buf6(dataout[6], dataout_tmp[6]);
buf dataout_buf7(dataout[7], dataout_tmp[7]);
buf dataout_buf8(dataout[8], dataout_tmp[8]);
buf dataout_buf9(dataout[9], dataout_tmp[9]);
buf dataout_buf10(dataout[10], dataout_tmp[10]);
buf dataout_buf11(dataout[11], dataout_tmp[11]);
buf dataout_buf12(dataout[12], dataout_tmp[12]);
buf dataout_buf13(dataout[13], dataout_tmp[13]);
buf dataout_buf14(dataout[14], dataout_tmp[14]);
buf dataout_buf15(dataout[15], dataout_tmp[15]);
buf dataout_buf16(dataout[16], dataout_tmp[16]);
buf dataout_buf17(dataout[17], dataout_tmp[17]);
buf dataout_buf18(dataout[18], dataout_tmp[18]);
buf dataout_buf19(dataout[19], dataout_tmp[19]);
buf dataout_buf20(dataout[20], dataout_tmp[20]);
buf dataout_buf21(dataout[21], dataout_tmp[21]);
buf dataout_buf22(dataout[22], dataout_tmp[22]);
buf dataout_buf23(dataout[23], dataout_tmp[23]);
buf dataout_buf24(dataout[24], dataout_tmp[24]);
buf dataout_buf25(dataout[25], dataout_tmp[25]);
buf dataout_buf26(dataout[26], dataout_tmp[26]);
buf dataout_buf27(dataout[27], dataout_tmp[27]);
buf dataout_buf28(dataout[28], dataout_tmp[28]);
buf dataout_buf29(dataout[29], dataout_tmp[29]);
buf dataout_buf30(dataout[30], dataout_tmp[30]);
buf dataout_buf31(dataout[31], dataout_tmp[31]);
buf dataout_buf32(dataout[32], dataout_tmp[32]);
buf dataout_buf33(dataout[33], dataout_tmp[33]);
buf dataout_buf34(dataout[34], dataout_tmp[34]);
buf dataout_buf35(dataout[35], dataout_tmp[35]);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_MULT
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
scanouta,
scanoutb,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter output_clock = "none";
parameter dataa_clear = "none";
parameter datab_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter output_clear = "none";
parameter signa_internally_grounded = "false";
parameter signb_internally_grounded = "false";
parameter lpm_hint = "true";
parameter lpm_type = "stratix_mac_mult";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = dataa_width + datab_width;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
output [dataa_width-1:0] scanouta;
output [datab_width-1:0] scanoutb;
tri1 devclrn;
tri1 devpor;
wire [35:0] mult_output;
wire [71:0] signa_out;
wire [71:0] signb_out;
wire [71:0] dataout_tmp;
wire [71:0] scanouta_tmp;
wire [71:0] scanoutb_tmp;
assign dataout = dataout_tmp[35:0];
stratix_mac_register dataa_mac_reg
(
.data ({{(72-dataa_width){1'b0}},dataa}),
.clk (clk[select_the(dataa_clock)]),
.aclr (aclr[select_the(dataa_clear)] || ~devclrn || ~devpor),
.if_aclr ((dataa_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(dataa_clock)]),
.dataout (scanouta_tmp),
.async ((dataa_clock == "none") ? 1'b1 : 1'b0 )
);
defparam dataa_mac_reg.data_width = dataa_width;
defparam dataa_mac_reg.power_up = 1'b0;
stratix_mac_register datab_mac_reg
(
.data ({{(72-datab_width){1'b0}},datab}),
.clk (clk[select_the(datab_clock)]),
.aclr (aclr[select_the(datab_clear)] || ~devclrn || ~devpor),
.if_aclr ((datab_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(datab_clock)]),
.dataout (scanoutb_tmp),
.async ((datab_clock == "none") ? 1'b1 : 1'b0 )
);
defparam datab_mac_reg.data_width = datab_width;
defparam datab_mac_reg.power_up = 1'b0;
stratix_mac_register signa_mac_reg
(
.data ({{(71){1'b0}},signa}),
.clk (clk[select_the(signa_clock)]),
.aclr (aclr[select_the(signa_clear)] || ~devclrn || ~devpor),
.if_aclr ((signa_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(signa_clock)]),
.dataout (signa_out),
.async ((signa_clock == "none") ? 1'b1 : 1'b0 )
);
defparam signa_mac_reg.data_width = 1;
defparam signa_mac_reg.power_up = 1'b0;
stratix_mac_register signb_mac_reg
(
.data ({{(71){1'b0}},signb}),
.clk (clk[select_the(signb_clock)]),
.aclr (aclr[select_the(signb_clear)] || ~devclrn || ~devpor),
.if_aclr ((signb_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(signb_clock)]),
.dataout (signb_out),
.async ((signb_clock == "none") ? 1'b1 : 1'b0 )
);
defparam signb_mac_reg.data_width = 1;
defparam signb_mac_reg.power_up = 1'b0;
stratix_mac_mult_internal mac_multiply
(
.dataa (scanouta_tmp[dataa_width-1:0]),
.datab (scanoutb_tmp[datab_width-1:0]),
.signa ((signa_internally_grounded == "false") ? signa_out[0] : 1'b0),
.signb ((signb_internally_grounded == "false") ? signb_out[0] : 1'b0),
.scanouta(scanouta),
.scanoutb(scanoutb),
.dataout(mult_output)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = (dataa_width+datab_width);
stratix_mac_register dataout_mac_reg
(
.data ({{(36){1'b0}},mult_output}),
.clk (clk[select_the(output_clock)]),
.aclr (aclr[select_the(output_clear)] || ~devclrn || ~devpor),
.if_aclr ((output_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(output_clock)]),
.dataout (dataout_tmp),
.async ((output_clock == "none") ? 1'b1 : 1'b0 )
);
defparam dataout_mac_reg.data_width = (dataa_width+datab_width);
defparam dataout_mac_reg.power_up = 1'b0;
//////////////////////////////////////////////////////////////////////////////
//
// SELECT_THE
//
//////////////////////////////////////////////////////////////////////////////
function integer select_the;
input [8*4:1] string_name;
begin
if (string_name == "0")
select_the = 0;
else if (string_name == "1")
select_the = 1;
else if (string_name == "2")
select_the = 2;
else if (string_name == "3")
select_the = 3;
else if (string_name == "none")
select_the = 0;
end
endfunction
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_OUT_INTERNAL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_out_internal (dataa, datab, datac, datad, signx, signy,
addnsub0, addnsub1, zeroacc, dataout_global,
dataout, accoverflow);
`define ADD 1'b1
`define SUB 1'b0
parameter operation_mode = "output_only";
parameter dataa_width = 36;
parameter datab_width = 36;
parameter datac_width = 36;
parameter datad_width = 36;
parameter dataout_width = 72;
input [36:0] dataa;
input [36:0] datab;
input [36:0] datac;
input [36:0] datad;
input signx;
input signy;
input addnsub0;
input addnsub1;
input zeroacc;
input [71:0] dataout_global;
output [71:0] dataout;
output accoverflow;
reg [72:0] dataout_tmp;
reg accoverflow_tmp;
reg [72:0] last_dataout;
reg [71:0] dataa_u;
reg [71:0] datab_u;
reg [71:0] datab_s;
reg [71:0] datac_u;
reg [71:0] datac_s;
reg [71:0] datad_u;
reg [71:0] datad_s;
reg [72:0] data_tmp;
wire [71:0] dataout_tbuf;
wire accoverflow_tbuf;
specify
(dataa *> dataout) = (0,0);
(datab *> dataout) = (0,0);
(datac *> dataout) = (0,0);
(datad *> dataout) = (0,0);
(signx *> dataout) = (0,0);
(signy *> dataout) = (0,0);
(addnsub0 *> dataout) = (0,0);
(addnsub1 *> dataout) = (0,0);
(zeroacc *> dataout) = (0,0);
(dataa *> accoverflow) = (0,0);
(signx *> accoverflow) = (0,0);
(signy *> accoverflow) = (0,0);
(addnsub0 *> accoverflow) = (0,0);
(addnsub1 *> accoverflow) = (0,0);
(zeroacc *> accoverflow) = (0,0);
endspecify
buf dataout_buf0(dataout[0], dataout_tbuf[0]);
buf dataout_buf1(dataout[1], dataout_tbuf[1]);
buf dataout_buf2(dataout[2], dataout_tbuf[2]);
buf dataout_buf3(dataout[3], dataout_tbuf[3]);
buf dataout_buf4(dataout[4], dataout_tbuf[4]);
buf dataout_buf5(dataout[5], dataout_tbuf[5]);
buf dataout_buf6(dataout[6], dataout_tbuf[6]);
buf dataout_buf7(dataout[7], dataout_tbuf[7]);
buf dataout_buf8(dataout[8], dataout_tbuf[8]);
buf dataout_buf9(dataout[9], dataout_tbuf[9]);
buf dataout_buf10(dataout[10], dataout_tbuf[10]);
buf dataout_buf11(dataout[11], dataout_tbuf[11]);
buf dataout_buf12(dataout[12], dataout_tbuf[12]);
buf dataout_buf13(dataout[13], dataout_tbuf[13]);
buf dataout_buf14(dataout[14], dataout_tbuf[14]);
buf dataout_buf15(dataout[15], dataout_tbuf[15]);
buf dataout_buf16(dataout[16], dataout_tbuf[16]);
buf dataout_buf17(dataout[17], dataout_tbuf[17]);
buf dataout_buf18(dataout[18], dataout_tbuf[18]);
buf dataout_buf19(dataout[19], dataout_tbuf[19]);
buf dataout_buf20(dataout[20], dataout_tbuf[20]);
buf dataout_buf21(dataout[21], dataout_tbuf[21]);
buf dataout_buf22(dataout[22], dataout_tbuf[22]);
buf dataout_buf23(dataout[23], dataout_tbuf[23]);
buf dataout_buf24(dataout[24], dataout_tbuf[24]);
buf dataout_buf25(dataout[25], dataout_tbuf[25]);
buf dataout_buf26(dataout[26], dataout_tbuf[26]);
buf dataout_buf27(dataout[27], dataout_tbuf[27]);
buf dataout_buf28(dataout[28], dataout_tbuf[28]);
buf dataout_buf29(dataout[29], dataout_tbuf[29]);
buf dataout_buf30(dataout[30], dataout_tbuf[30]);
buf dataout_buf31(dataout[31], dataout_tbuf[31]);
buf dataout_buf32(dataout[32], dataout_tbuf[32]);
buf dataout_buf33(dataout[33], dataout_tbuf[33]);
buf dataout_buf34(dataout[34], dataout_tbuf[34]);
buf dataout_buf35(dataout[35], dataout_tbuf[35]);
buf dataout_buf36(dataout[36], dataout_tbuf[36]);
buf dataout_buf37(dataout[37], dataout_tbuf[37]);
buf dataout_buf38(dataout[38], dataout_tbuf[38]);
buf dataout_buf39(dataout[39], dataout_tbuf[39]);
buf dataout_buf40(dataout[40], dataout_tbuf[40]);
buf dataout_buf41(dataout[41], dataout_tbuf[41]);
buf dataout_buf42(dataout[42], dataout_tbuf[42]);
buf dataout_buf43(dataout[43], dataout_tbuf[43]);
buf dataout_buf44(dataout[44], dataout_tbuf[44]);
buf dataout_buf45(dataout[45], dataout_tbuf[45]);
buf dataout_buf46(dataout[46], dataout_tbuf[46]);
buf dataout_buf47(dataout[47], dataout_tbuf[47]);
buf dataout_buf48(dataout[48], dataout_tbuf[48]);
buf dataout_buf49(dataout[49], dataout_tbuf[49]);
buf dataout_buf50(dataout[50], dataout_tbuf[50]);
buf dataout_buf51(dataout[51], dataout_tbuf[51]);
buf dataout_buf52(dataout[52], dataout_tbuf[52]);
buf dataout_buf53(dataout[53], dataout_tbuf[53]);
buf dataout_buf54(dataout[54], dataout_tbuf[54]);
buf dataout_buf55(dataout[55], dataout_tbuf[55]);
buf dataout_buf56(dataout[56], dataout_tbuf[56]);
buf dataout_buf57(dataout[57], dataout_tbuf[57]);
buf dataout_buf58(dataout[58], dataout_tbuf[58]);
buf dataout_buf59(dataout[59], dataout_tbuf[59]);
buf dataout_buf60(dataout[60], dataout_tbuf[60]);
buf dataout_buf61(dataout[61], dataout_tbuf[61]);
buf dataout_buf62(dataout[62], dataout_tbuf[62]);
buf dataout_buf63(dataout[63], dataout_tbuf[63]);
buf dataout_buf64(dataout[64], dataout_tbuf[64]);
buf dataout_buf65(dataout[65], dataout_tbuf[65]);
buf dataout_buf66(dataout[66], dataout_tbuf[66]);
buf dataout_buf67(dataout[67], dataout_tbuf[67]);
buf dataout_buf68(dataout[68], dataout_tbuf[68]);
buf dataout_buf69(dataout[69], dataout_tbuf[69]);
buf dataout_buf70(dataout[70], dataout_tbuf[70]);
buf dataout_buf71(dataout[71], dataout_tbuf[71]);
buf accoverflow_buf(accoverflow, accoverflow_tbuf);
assign dataout_tbuf[71:0] = dataout_tmp[71:0];
assign accoverflow_tbuf = accoverflow_tmp;
always @(dataa or datab or datac or datad or dataout_global
or signx or signy or addnsub0 or addnsub1
or zeroacc or operation_mode)
begin
case (operation_mode)
"output_only": // dataout_tmp = dataa
begin
dataout_tmp = dataa;
end
"accumulator": // dataout_tmp += dataa
begin
if (signx || signy) begin
data_tmp = {{73 - dataa_width{dataa[dataa_width-1]}},
dataa[dataa_width-1:0]};
last_dataout = {{73-dataout_width{dataout_global[dataout_width-1]}},
dataout_global[dataout_width-1:0]};
end else begin
data_tmp = {{73 - dataa_width{1'b0}},
dataa[dataa_width-1:0]};
last_dataout = {{73-dataout_width{1'b0}},
dataout_global[dataout_width-1:0]};
end
if (zeroacc) begin
if (`ADD == addnsub0)
dataout_tmp[dataout_width:0] = data_tmp;
else
dataout_tmp[dataout_width:0] = - data_tmp;
end else begin
if (`ADD == addnsub0)
dataout_tmp[dataout_width:0] = last_dataout + data_tmp;
else
dataout_tmp[dataout_width:0] = last_dataout - data_tmp;
end
if (signx || signy)
accoverflow_tmp = dataout_tmp[dataout_width] ^ dataout_tmp[dataout_width-1];
else
accoverflow_tmp = dataout_tmp[dataout_width];
end
"one_level_adder": // dataout_tmp = dataa +/- datab
begin
if(addnsub0)
dataout_tmp[dataout_width-1:0] =
add_or_sub(signx || signy, dataa[35:0], signx || signy, datab[35:0], addnsub0);
else
dataout_tmp[dataout_width-1:0] =
add_or_sub(signx || signy , dataa[35:0], signx || signy, datab[35:0], 1'b0);
end
"two_level_adder": // dataout_tmp = (dataa +/- datab) + (datac +/- datad)
// DEFAULT TO ADD (say if the addnsub0,1 signal is set to GROUND)
begin // dataout_width = dataa_width + 2;
dataout_tmp[dataout_width-1:0] =
add_or_sub(signx || signy, dataa[35:0], signx || signy, datab[35:0], addnsub0) +
add_or_sub(signx || signy, datac[35:0], signx || signy, datad[35:0], addnsub1);
end
"36_bit_multiply":
begin
dataa_u = dataa[35:0];
datab_u = datab[35:0];
datab_s = {{(72-36){datab[35]}}, datab[35:0]};
datac_u = datac[35:0];
datac_s = {{(72-36){datac[35]}}, datac[35:0]};
datad_u = datad[35:0];
datad_s = {{(72-36){datad[35]}}, datad[35:0]};
if(signx == 1'b0 && signy == 1'b0)
begin
dataout_tmp = (datab_u << 36) + (datac_u << 18) +
(datad_u << 18) + dataa_u;
end // if (signx == 1'b0 && signy == 1'b0)
else if(signx == 1'b0 && signy == 1'b1)
begin
dataout_tmp = (datab_s << 36) + (datac_u << 18) +
(datad_s << 18) + dataa_u;
end // if (signx == 1'b0 && signy == 1'b1)
else if(signx == 1'b1 && signy == 1'b0)
begin
dataout_tmp = (datab_s << 36) + (datac_s << 18) +
(datad_u << 18) + dataa_u;
end // if (signx == 1'b1 && signy == 1'b0)
else if(signx == 1'b1 && signy == 1'b1)
begin
dataout_tmp = (datab_s << 36) + (datac_s << 18) +
(datad_s << 18) + dataa_u;
end // if (signx == 1'b1 && signy == 1'b1)
end
default :
begin
$display ("INFO: Default operation not specified\n");
$display ("Time: %0t Instance: %m", $time);
end
endcase
end
//////////////////////////////////////////////////////////////////////////////
//
// ADD_OR_SUB
//
//////////////////////////////////////////////////////////////////////////////
function [52:0] add_or_sub;
input sign_a;
input [dataa_width-1:0] data_a;
input sign_b;
input [datab_width-1:0] data_b;
input operation;
reg sa;
reg sb;
reg [dataa_width-1:0] abs_a;
reg [datab_width-1:0] abs_b;
begin
sa = ( sign_a && data_a[dataa_width-1] );
sb = ( sign_b && data_b[datab_width-1] );
abs_a = ( sign_a && data_a[dataa_width-1] ) ? (~data_a + 1) : data_a;
abs_b = ( sign_b && data_b[datab_width-1] ) ? (~data_b + 1) : data_b;
if (operation == `ADD)
begin
add_or_sub = (sa ? -abs_a : abs_a) + (sb ? -abs_b : abs_b);
end
else if (operation == `SUB)
begin
add_or_sub = (sa ? -abs_a : abs_a) - (sb ? -abs_b : abs_b);
end
else
begin
$display ("INFO: Default operation not specified\n");
$display ("Time: %0t Instance: %m", $time);
end
end
endfunction // add_or_sub
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// STRATIX_MAC_OUT
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_mac_out
(
dataa,
datab,
datac,
datad,
zeroacc,
addnsub0,
addnsub1,
signa,
signb,
clk,
aclr,
ena,
dataout,
accoverflow,
devclrn,
devpor
);
parameter operation_mode = "output_only";
parameter dataa_width = 1;
parameter datab_width = 1;
parameter datac_width = 1;
parameter datad_width = 1;
parameter addnsub0_clock = "none";
parameter addnsub1_clock = "none";
parameter zeroacc_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter output_clock = "none";
parameter addnsub0_clear = "none";
parameter addnsub1_clear = "none";
parameter zeroacc_clear = "none";
parameter signa_clear = "none";
parameter signb_clear = "none";
parameter output_clear = "none";
parameter addnsub0_pipeline_clock = "none";
parameter addnsub1_pipeline_clock = "none";
parameter zeroacc_pipeline_clock = "none";
parameter signa_pipeline_clock = "none";
parameter signb_pipeline_clock = "none";
parameter addnsub0_pipeline_clear = "none";
parameter addnsub1_pipeline_clear = "none";
parameter zeroacc_pipeline_clear = "none";
parameter signa_pipeline_clear = "none";
parameter signb_pipeline_clear = "none";
parameter lpm_hint = "true";
parameter lpm_type = "stratix_mac_out";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter dataout_width = (dataa_width > datab_width ? dataa_width : datab_width)
+ (datac_width > datad_width ? datac_width : datad_width);
parameter overflow_programmable_invert = 1'b0;
parameter data_out_programmable_invert = 72'b0;
// SIMULATION_ONLY_PARAMETERS_END
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input [datac_width-1:0] datac;
input [datad_width-1:0] datad;
input zeroacc;
input addnsub0;
input addnsub1;
input signa;
input signb;
input [3:0] clk;
input [3:0] aclr;
input [3:0] ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
output accoverflow;
tri1 devclrn;
tri1 devpor;
wire [71:0] signa_pipe;
wire [71:0] signb_pipe;
wire [71:0] signa_out;
wire [71:0] signb_out;
wire [71:0] addnsub0_pipe;
wire [71:0] addnsub1_pipe;
wire [71:0] addnsub0_out;
wire [71:0] addnsub1_out;
wire [71:0] zeroacc_pipe;
wire [71:0] zeroacc_out;
wire [71:0] dataout_wire;
wire accoverflow_wire;
wire [71:0] dataout_tmp;
wire [71:0] accoverflow_tmp;
stratix_mac_register signa_mac_reg
(
.data ({{(71){1'b0}},signa}),
.clk (clk[select_the(signa_clock)]),
.aclr (aclr[select_the(signa_clear)] || ~devclrn || ~devpor),
.if_aclr ((signa_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(signa_clock)]),
.dataout (signa_pipe),
.async ((signa_clock == "none") ? 1'b1 : 1'b0 )
);
defparam signa_mac_reg.data_width = 1;
defparam signa_mac_reg.power_up = 1'b0;
stratix_mac_register signb_mac_reg
(
.data ({{(71){1'b0}},signb}),
.clk (clk[select_the(signb_clock)]),
.aclr (aclr[select_the(signb_clear)] || ~devclrn || ~devpor),
.if_aclr ((signb_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(signb_clock)]),
.dataout (signb_pipe),
.async ((signb_clock == "none") ? 1'b1 : 1'b0 )
);
defparam signb_mac_reg.data_width = 1;
defparam signb_mac_reg.power_up = 1'b0;
stratix_mac_register zeroacc_mac_reg
(
.data ({{(71){1'b0}},zeroacc}),
.clk (clk[select_the(zeroacc_clock)]),
.aclr (aclr[select_the(zeroacc_clear)] || ~devclrn || ~devpor),
.if_aclr ((zeroacc_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(zeroacc_clock)]),
.dataout (zeroacc_pipe),
.async ((zeroacc_clock == "none") ? 1'b1 : 1'b0 )
);
defparam zeroacc_mac_reg.data_width = 1;
defparam zeroacc_mac_reg.power_up = 1'b0;
stratix_mac_register addnsub0_mac_reg
(
.data ({{(71){1'b0}},addnsub0}),
.clk (clk[select_the(addnsub0_clock)]),
.aclr (aclr[select_the(addnsub0_clear)] || ~devclrn || ~devpor),
.if_aclr ((addnsub0_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(addnsub0_clock)]),
.dataout (addnsub0_pipe),
.async ((addnsub0_clock == "none") ? 1'b1 : 1'b0 )
);
defparam addnsub0_mac_reg.data_width = 1;
defparam addnsub0_mac_reg.power_up = 1'b0;
stratix_mac_register addnsub1_mac_reg
(
.data ({{(71){1'b0}},addnsub1}),
.clk (clk[select_the(addnsub1_clock)]),
.aclr (aclr[select_the(addnsub1_clear)] || ~devclrn || ~devpor),
.if_aclr ((addnsub1_clear != "none") ? 1'b1 : 1'b0),
.ena (ena[select_the(addnsub1_clock)]),
.dataout (addnsub1_pipe),
.async ((addnsub1_clock == "none") ? 1'b1 : 1'b0 )
);
defparam addnsub1_mac_reg.data_width = 1;
defparam addnsub1_mac_reg.power_up = 1'b0;
stratix_mac_register signa_mac_pipeline_reg
(
.data (signa_pipe),
.clk (clk[select_the(signa_pipeline_clock)]),
.aclr (aclr[select_the(signa_pipeline_clear)] || ~devclrn || ~devpor),
.if_aclr ((signa_pipeline_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(signa_pipeline_clock)]),
.dataout (signa_out),
.async ((signa_pipeline_clock == "none") ? 1'b1 : 1'b0 )
);
defparam signa_mac_pipeline_reg.data_width = 1;
defparam signa_mac_pipeline_reg.power_up = 1'b0;
stratix_mac_register signb_mac_pipeline_reg
(
.data (signb_pipe),
.clk (clk[select_the(signb_pipeline_clock)]),
.aclr (aclr[select_the(signb_pipeline_clear)] || ~devclrn || ~devpor),
.if_aclr ((signb_pipeline_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(signb_pipeline_clock)]),
.dataout (signb_out),
.async ((signb_pipeline_clock == "none") ? 1'b1 : 1'b0 )
);
defparam signb_mac_pipeline_reg.data_width = 1;
defparam signb_mac_pipeline_reg.power_up = 1'b0;
stratix_mac_register zeroacc_mac_pipeline_reg
(
.data (zeroacc_pipe),
.clk (clk[select_the(zeroacc_pipeline_clock)]),
.aclr (aclr[select_the(zeroacc_pipeline_clear)] || ~devclrn || ~devpor),
.if_aclr ((zeroacc_pipeline_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(zeroacc_pipeline_clock)]),
.dataout (zeroacc_out),
.async ((zeroacc_pipeline_clock == "none") ? 1'b1 : 1'b0 )
);
defparam zeroacc_mac_pipeline_reg.data_width = 1;
defparam zeroacc_mac_pipeline_reg.power_up = 1'b0;
stratix_mac_register addnsub0_mac_pipeline_reg
(
.data (addnsub0_pipe),
.clk (clk[select_the(addnsub0_pipeline_clock)]),
.aclr (aclr[select_the(addnsub0_pipeline_clear)] || ~devclrn || ~devpor),
.if_aclr ((addnsub0_pipeline_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(addnsub0_pipeline_clock)]),
.dataout (addnsub0_out),
.async ((addnsub0_pipeline_clock == "none") ? 1'b1 : 1'b0 )
);
defparam addnsub0_mac_pipeline_reg.data_width = 1;
defparam addnsub0_mac_pipeline_reg.power_up = 1'b0;
stratix_mac_register addnsub1_mac_pipeline_reg
(
.data (addnsub1_pipe),
.clk (clk[select_the(addnsub1_pipeline_clock)]),
.aclr (aclr[select_the(addnsub1_pipeline_clear)] || ~devclrn || ~devpor),
.if_aclr ((addnsub1_pipeline_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(addnsub1_pipeline_clock)]),
.dataout (addnsub1_out),
.async ((addnsub1_pipeline_clock == "none") ? 1'b1 : 1'b0 )
);
defparam addnsub1_mac_pipeline_reg.data_width = 1;
defparam addnsub1_mac_pipeline_reg.power_up = 1'b0;
stratix_mac_out_internal mac_adder
(
.dataa ({{37-dataa_width{1'bz}},dataa}),
.datab ({{37-datab_width{1'bz}},datab}),
.datac ({{37-datac_width{1'bz}},datac}),
.datad ({{37-datad_width{1'bz}},datad}),
.signx (signa_out[0]),
.signy (signb_out[0]),
.addnsub0 (addnsub0_out[0]),
.addnsub1 (addnsub1_out[0]),
.zeroacc (zeroacc_out[0]),
.dataout_global (dataout_tmp[71:0]),
.dataout (dataout_wire[71:0]),
.accoverflow (accoverflow_wire)
);
defparam mac_adder.dataa_width = dataa_width;
defparam mac_adder.datab_width = datab_width;
defparam mac_adder.datac_width = datac_width;
defparam mac_adder.datad_width = datad_width;
defparam mac_adder.dataout_width = dataout_width;
defparam mac_adder.operation_mode = operation_mode;
stratix_mac_register dataout_out_reg
(
.data (dataout_wire),
.clk (clk[select_the(output_clock)]),
.aclr (aclr[select_the(output_clear)] || ~devclrn || ~devpor),
.if_aclr ((output_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(output_clock)]),
.dataout (dataout_tmp),
.async ((output_clock == "none") ? 1'b1 : 1'b0 )
);
defparam dataout_out_reg.data_width = dataout_width;
defparam dataout_out_reg.power_up = 1'b0;
stratix_mac_register accoverflow_out_reg
(
.data ({{(71){1'b0}},accoverflow_wire}),
.clk (clk[select_the(output_clock)]),
.aclr (aclr[select_the(output_clear)] || ~devclrn || ~devpor),
.if_aclr ((output_clear != "none") ? 1'b1 : 1'b0 ),
.ena (ena[select_the(output_clock)]),
.dataout (accoverflow_tmp),
.async ((output_clock == "none") ? 1'b1 : 1'b0 )
);
defparam accoverflow_out_reg.data_width = 1;
defparam accoverflow_out_reg.power_up = 1'b0;
assign dataout = dataout_tmp ^ data_out_programmable_invert;
assign accoverflow = accoverflow_tmp[0] ^ overflow_programmable_invert;
//////////////////////////////////////////////////////////////////////////////
//
// SELECT_THE
//
//////////////////////////////////////////////////////////////////////////////
function integer select_the;
input [8*4:1] string_name;
begin
if (string_name == "0")
select_the = 0;
else if (string_name == "1")
select_the = 1;
else if (string_name == "2")
select_the = 2;
else if (string_name == "3")
select_the = 3;
else if (string_name == "none")
select_the = 0;
end
endfunction
endmodule
//--------------------------------------------------------------------------
// Module Name : stratix_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratix_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : stratix_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratix_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : stratix_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module stratix_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_read_enable_write_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "stratix_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbrewe_int;
assign portbrewe_int = portbrewe;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a, active_b;
wire active_a_in, active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
if ((power_up_uninitialized == "false") && ~ram_type)
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0_int;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0_int : clr1_int);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0_int;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0_int : clr1_int);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0_int;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0_int : clr1_int);
assign active_a_in = ena0_int;
assign active_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? ena0_int : ena1_int;
// Store clock enable value for SEAB/MEAB
// port A active
stratix_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
stratix_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
stratix_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
stratix_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
stratix_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
stratix_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
stratix_ram_register rewe_b_register (
.d(portbrewe_int),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
stratix_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
stratix_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
stratix_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
stratix_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
stratix_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
stratix_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),
.cycle()
);
stratix_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),
.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime)
read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
stratix_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
stratix_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ? ena0_int : ena1_int;
stratix_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ? ena0_int : ena1_int;
stratix_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // stratix_ram_block
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lvds_tx_parallel_register
//
// Description : Parallel register used in the Transmitter module
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lvds_tx_parallel_register (clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_enable (enable_ipd,enable);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
$setuphold(posedge clk, datain, 0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or devpor or devclrn)
begin
if ((devpor === 1'b0) || (devclrn === 1'b0))
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value !== clk_ipd))
begin
if (enable_ipd === 1)
begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end //always
assign dataout_opd = dataout_tmp;
endmodule //stratix_lvds_tx_register
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lvds_tx_out_block
//
// Description : Negative edge triggered register on the TX output
// side. It also optionally generates an clock output,
// which could be identical or inverted of the input
// clock.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lvds_tx_out_block (clk,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
// INPUT PORTS
input datain;
input clk;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
reg dataout_tmp;
reg clk_last_value;
wire bypass_mode;
wire invert_mode;
wire falling_clk_out;
// INPUT BUFFERS
wire clk_in;
wire datain_in;
buf (clk_in, clk);
buf (datain_in, datain);
assign falling_clk_out = (use_falling_clock_edge == "true")?1'b1:1'b0;
assign bypass_mode = (bypass_serializer == "true")?1'b1:1'b0;
assign invert_mode = (invert_clock == "true")?1'b1:1'b0;
specify
(datain => dataout) = (0, 0);
if (bypass_mode == 1'b1)
(clk => dataout) = (0, 0);
if (bypass_mode == 1'b0 && falling_clk_out == 1'b1)
(negedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 0;
end
always @(clk_in or datain_in or devclrn or devpor)
begin
if ((devpor === 'b0) || (devclrn === 'b0))
begin
dataout_tmp <= 0;
end
else
begin
if (bypass_serializer == "false")
begin
if (use_falling_clock_edge == "false")
dataout_tmp <= datain_in;
else if ((clk_in === 1'b0) && (clk_last_value !== clk_in))
dataout_tmp <= datain_in;
end //bypass is off
else //generate clk_out
dataout_tmp <= (invert_clock == "false") ? clk_in : !clk_in;
end //devpor
clk_last_value <= clk_in;
end // always
and (dataout, dataout_tmp, 1'b1);
endmodule //stratix_lvds_tx_out_block
////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lvds_transmitter
//
// Description : Timing simulation model for Stratix LVDS Transmitter,
// including the following sub module(s):
// 1. DFFE
// 2. stratix_lvds_tx_parallel_register
// 3. stratix_lvds_tx_out_block
//
////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lvds_transmitter (clk0,
enable0,
datain,
dataout,
devclrn,
devpor
);
parameter bypass_serializer = "false";
parameter invert_clock = "false";
parameter use_falling_clock_edge = "false";
parameter lpm_type = "stratix_lvds_transmitter";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter channel_width = 4;
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk0;
input enable0;
input devclrn;
input devpor;
// OUTPUT PORTS
output dataout;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES
reg shift_out;
reg clk0_last_value;
wire [channel_width - 1:0] input_data;
reg [channel_width - 1:0] shift_data;
wire txload0;
wire txload1;
wire txload2;
wire bypass_mode;
reg [channel_width - 1:0] datain_dly;
reg [channel_width - 1:0] datain_dly2;
reg tmp_bit;
// INPUT BUFFERS
wire clk0_in;
buf (clk0_in, clk0);
initial
begin
clk0_last_value = 1'b0;
shift_out = 1'b0;
shift_data = {channel_width{1'b0}};
end
stratix_dffe txload0_reg (.D(enable0),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(clk0_in),
.Q(txload0));
stratix_dffe txload1_reg (.D(txload0),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(clk0_in),
.Q(txload1));
stratix_dffe txload2_reg (.D(txload1),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk0_in),
.Q(txload2));
stratix_lvds_tx_out_block output_module (.clk(clk0_in),
.datain(shift_out),
.dataout(dataout),
.devclrn(devclrn),
.devpor(devpor));
defparam output_module.bypass_serializer = bypass_serializer;
defparam output_module.invert_clock = invert_clock;
defparam output_module.use_falling_clock_edge = use_falling_clock_edge;
stratix_lvds_tx_parallel_register input_reg (.clk(txload0),
.enable(1'b1),
.datain(datain_dly2),
.dataout(input_data),
.devclrn(devclrn),
.devpor(devpor));
defparam input_reg.channel_width = channel_width;
always @(datain)
begin
datain_dly <= datain;
end
always @(datain_dly)
begin
datain_dly2 <= datain_dly;
end
always @(clk0_in or devclrn or devpor)
begin
if ((devpor == 'b0) || (devclrn == 'b0))
begin
shift_out <= 1'b0;
shift_data <= {channel_width{1'b0}};
end
else
begin
if (bypass_serializer == "false")
begin
if ((clk0_in === 1'b1) && (clk0_last_value !== clk0_in))
begin
if (txload2 === 1'b1)
begin
shift_out <= input_data[channel_width - 1];
{tmp_bit, shift_data} <= {input_data, input_data[0]};
end
else
begin
shift_out <= shift_data[channel_width - 1];
{tmp_bit, shift_data} <= {shift_data, shift_data[0]};
end
end
end //bypass is off
end //devpor
clk0_last_value <= clk0_in;
end // always
endmodule // stratix_lvds_transmitter
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lvds_rx_parallel_register
//
// Description : Parallel register used in the Receiver module
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lvds_rx_parallel_register (clk,
enable,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
// INPUT PORTS
input [channel_width - 1:0] datain;
input clk;
input enable;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
// INTERNAL VARIABLES
reg clk_last_value;
reg [channel_width - 1:0] dataout_tmp;
wire clk_ipd;
wire enable_ipd;
wire [channel_width - 1:0] datain_ipd;
buf buf_clk (clk_ipd,clk);
buf buf_enable (enable_ipd,enable);
buf buf_datain [channel_width - 1:0] (datain_ipd,datain);
wire [channel_width - 1:0] dataout_opd;
buf buf_dataout [channel_width - 1:0] (dataout,dataout_opd);
specify
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
endspecify
initial
begin
clk_last_value = 0;
dataout_tmp = 'b0;
end
always @(clk_ipd or devpor or devclrn)
begin
if ((devpor === 'b0) || (devclrn === 'b0))
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1) && (clk_last_value !== clk_ipd))
begin
if (enable_ipd === 1)
begin
dataout_tmp <= datain_ipd;
end
end
end
clk_last_value <= clk_ipd;
end //always
assign dataout_opd = dataout_tmp;
endmodule //stratix_lvds_rx_register
///////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_lvds_receiver
//
// Description : Verilog simulation model for Stratix LVDS Receiver
// including the following sub module(s):
// 1. DFFE
// 2. stratix_lvds_rx_parallel_register
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_lvds_receiver (clk0,
enable0,
enable1,
datain,
dataout,
devclrn,
devpor
);
parameter channel_width = 4;
parameter use_enable1 = "false";
parameter lpm_type = "stratix_lvds_receiver";
// INPUT PORTS
input datain;
input clk0;
input enable0;
input enable1;
input devclrn;
input devpor;
// OUTPUT PORTS
output [channel_width - 1:0] dataout;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES
reg clk0_last_value;
reg [channel_width - 1:0] shift_data;
wire [channel_width - 1:0] load_data;
wire rxload0;
wire rxload1;
wire rxload2;
wire txload_in;
wire txload_out;
wire clk0_in;
wire datain_in;
reg rxload2_dly;
reg tmp_bit;
initial
begin
clk0_last_value = 0;
shift_data = {channel_width{1'b0}};
end
stratix_and1 clkdelaybuffer (.Y(clk0_in),
.IN1(clk0));
stratix_and1 dataindelaybuffer (.Y(datain_in),
.IN1(datain));
stratix_dffe rxload0_reg (.D(enable0),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(clk0_in),
.Q(rxload0));
stratix_dffe rxload1_reg (.D(rxload0),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(clk0_in),
.Q(rxload1));
stratix_dffe rxload2_reg (.D(rxload1),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk0_in),
.Q(rxload2));
assign txload_in = (use_enable1 == "true") ? enable1 : enable0;
stratix_dffe txload_reg (.D(txload_in),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(clk0_in),
.Q(txload_out));
stratix_lvds_rx_parallel_register load_reg (.clk(!clk0_in),
.enable(rxload2_dly),
.datain(shift_data),
.dataout(load_data),
.devclrn(devclrn),
.devpor(devpor));
defparam load_reg.channel_width = channel_width;
stratix_lvds_rx_parallel_register output_reg (.clk(txload_out),
.enable(1'b1),
.datain(load_data),
.dataout(dataout),
.devclrn(devclrn),
.devpor(devpor));
defparam output_reg.channel_width = channel_width;
always @(rxload2)
begin
rxload2_dly <= rxload2;
end
always @(clk0_in or devpor or devclrn)
begin
if ((devpor === 'b0) || (devclrn === 'b0))
shift_data <= {channel_width{1'b0}};
else
begin
if ((clk0_in === 0) && (clk0_last_value !== clk0_in))
{tmp_bit, shift_data} <= {shift_data, datain_in};
end //devpor
clk0_last_value <= clk0_in;
end //always
endmodule //stratix_lvds_receiver
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the Stratix PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module stratix_m_cntr (clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // stratix_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the Stratix PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module stratix_n_cntr (clk,
reset,
cout,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg clk_last_valid_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'bx)
begin
$display("Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.");
$display("Time: %0t Instance: %m", $time);
end
else if ((clk === 1'b1) && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk))
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
if (clk !== 1'bx)
clk_last_valid_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // stratix_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the L0, L1, G0, G1, G2, G3, E0,
// E1, E2 and E3 output counters of the Stratix PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module stratix_scale_cntr (clk,
reset,
cout,
high,
low,
initial_value,
mode,
time_delay,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] time_delay;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
reg [31:0] high_reg;
reg [31:0] low_reg;
reg high_cnt_xfer_done;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 0;
high_cnt_xfer_done = 0;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
high_reg = high;
low_reg = low;
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 0;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == "off")
tmp_cout = 0;
else if (mode == "bypass")
tmp_cout = clk;
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
output_shift_count = output_shift_count + 1;
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == "even" && (count == (high_reg*2) + 1))
begin
tmp_cout = 0;
if (high_cnt_xfer_done === 1'b1)
begin
low_reg = low;
high_cnt_xfer_done = 0;
end
end
else if (mode == "odd" && (count == (high_reg*2)))
begin
tmp_cout = 0;
if (high_cnt_xfer_done === 1'b1)
begin
low_reg = low;
high_cnt_xfer_done = 0;
end
end
else if (count == (high_reg + low_reg)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
if (high_reg != high)
begin
high_reg = high;
high_cnt_xfer_done = 1;
end
end
end
end
clk_last_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // stratix_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module stratix_pll_reg (q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (posedge clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk == 1) & (ena == 1'b1))
q <= d;
end
endmodule // stratix_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_pll
//
// Description : Timing simulation model for the Stratix StratixGX PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module stratix_pll (inclk,
fbin,
ena,
clkswitch,
areset,
pfdena,
clkena,
extclkena,
scanclk,
scanaclr,
scandata,
clk,
extclk,
clkbad,
activeclock,
locked,
clkloss,
scandataout,
// lvds mode specific ports
comparator,
enable0,
enable1);
parameter operation_mode = "normal";
parameter qualify_conf_done = "off";
parameter compensate_clock = "clk0";
parameter pll_type = "auto";
parameter scan_chain = "long";
parameter lpm_type = "stratix_pll";
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = 0;
parameter clk0_time_delay = 0;
parameter clk0_duty_cycle = 50;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = 0;
parameter clk1_time_delay = 0;
parameter clk1_duty_cycle = 50;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = 0;
parameter clk2_time_delay = 0;
parameter clk2_duty_cycle = 50;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = 0;
parameter clk3_time_delay = 0;
parameter clk3_duty_cycle = 50;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = 0;
parameter clk4_time_delay = 0;
parameter clk4_duty_cycle = 50;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = 0;
parameter clk5_time_delay = 0;
parameter clk5_duty_cycle = 50;
parameter extclk0_multiply_by = 1;
parameter extclk0_divide_by = 1;
parameter extclk0_phase_shift = 0;
parameter extclk0_time_delay = 0;
parameter extclk0_duty_cycle = 50;
parameter extclk1_multiply_by = 1;
parameter extclk1_divide_by = 1;
parameter extclk1_phase_shift = 0;
parameter extclk1_time_delay = 0;
parameter extclk1_duty_cycle = 50;
parameter extclk2_multiply_by = 1;
parameter extclk2_divide_by = 1;
parameter extclk2_phase_shift = 0;
parameter extclk2_time_delay = 0;
parameter extclk2_duty_cycle = 50;
parameter extclk3_multiply_by = 1;
parameter extclk3_divide_by = 1;
parameter extclk3_phase_shift = 0;
parameter extclk3_time_delay = 0;
parameter extclk3_duty_cycle = 50;
parameter primary_clock = "inclk0";
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter valid_lock_multiplier = 5;
parameter invalid_lock_multiplier = 5;
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter feedback_source = "extclk0";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter spread_frequency = 0;
parameter common_rx_tx = "off";
parameter rx_outclock_resource = "auto";
parameter use_vco_bypass = "false";
parameter use_dc_coupling = "false";
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter l0_high = 1;
parameter l0_low = 1;
parameter l0_initial = 1;
parameter l0_mode = "bypass";
parameter l0_ph = 0;
parameter l0_time_delay = 0;
parameter l1_high = 1;
parameter l1_low = 1;
parameter l1_initial = 1;
parameter l1_mode = "bypass";
parameter l1_ph = 0;
parameter l1_time_delay = 0;
parameter g0_high = 1;
parameter g0_low = 1;
parameter g0_initial = 1;
parameter g0_mode = "bypass";
parameter g0_ph = 0;
parameter g0_time_delay = 0;
parameter g1_high = 1;
parameter g1_low = 1;
parameter g1_initial = 1;
parameter g1_mode = "bypass";
parameter g1_ph = 0;
parameter g1_time_delay = 0;
parameter g2_high = 1;
parameter g2_low = 1;
parameter g2_initial = 1;
parameter g2_mode = "bypass";
parameter g2_ph = 0;
parameter g2_time_delay = 0;
parameter g3_high = 1;
parameter g3_low = 1;
parameter g3_initial = 1;
parameter g3_mode = "bypass";
parameter g3_ph = 0;
parameter g3_time_delay = 0;
parameter e0_high = 1;
parameter e0_low = 1;
parameter e0_initial = 1;
parameter e0_mode = "bypass";
parameter e0_ph = 0;
parameter e0_time_delay = 0;
parameter e1_high = 1;
parameter e1_low = 1;
parameter e1_initial = 1;
parameter e1_mode = "bypass";
parameter e1_ph = 0;
parameter e1_time_delay = 0;
parameter e2_high = 1;
parameter e2_low = 1;
parameter e2_initial = 1;
parameter e2_mode = "bypass";
parameter e2_ph = 0;
parameter e2_time_delay = 0;
parameter e3_high = 1;
parameter e3_low = 1;
parameter e3_initial = 1;
parameter e3_mode = "bypass";
parameter e3_ph = 0;
parameter e3_time_delay = 0;
parameter m_ph = 0;
parameter m_time_delay = 0;
parameter n_time_delay = 0;
parameter extclk0_counter = "e0";
parameter extclk1_counter = "e1";
parameter extclk2_counter = "e2";
parameter extclk3_counter = "e3";
parameter clk0_counter = "g0";
parameter clk1_counter = "g1";
parameter clk2_counter = "g2";
parameter clk3_counter = "g3";
parameter clk4_counter = "l0";
parameter clk5_counter = "l1";
// LVDS mode parameters
parameter enable0_counter = "l0";
parameter enable1_counter = "l0";
parameter charge_pump_current = 0;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 1;
parameter pll_compensation_delay = 0;
parameter simulation_type = "timing";
parameter source_is_pll = "off";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter family_name = "Stratix";
parameter skip_vco = "off";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter extclk0_use_even_counter_mode = "off";
parameter extclk1_use_even_counter_mode = "off";
parameter extclk2_use_even_counter_mode = "off";
parameter extclk3_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
parameter extclk0_use_even_counter_value = "off";
parameter extclk1_use_even_counter_value = "off";
parameter extclk2_use_even_counter_value = "off";
parameter extclk3_use_even_counter_value = "off";
// SIMULATION_ONLY_PARAMETERS_END
parameter scan_chain_mif_file = "";
// INPUT PORTS
input [1:0] inclk;
input fbin;
input ena;
input clkswitch;
input areset;
input pfdena;
input [5:0] clkena;
input [3:0] extclkena;
input scanclk;
input scanaclr;
input scandata;
// lvds specific input ports
input comparator;
// OUTPUT PORTS
output [5:0] clk;
output [3:0] extclk;
output [1:0] clkbad;
output activeclock;
output locked;
output clkloss;
output scandataout;
// lvds specific output ports
output enable0;
output enable1;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire clkena0_ipd;
wire clkena1_ipd;
wire clkena2_ipd;
wire clkena3_ipd;
wire clkena4_ipd;
wire clkena5_ipd;
wire extclkena0_ipd;
wire extclkena1_ipd;
wire extclkena2_ipd;
wire extclkena3_ipd;
wire scanclk_ipd;
wire scanaclr_ipd;
wire scandata_ipd;
wire comparator_ipd;
wire clkswitch_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, fbin);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (clkena0_ipd, clkena[0]);
buf (clkena1_ipd, clkena[1]);
buf (clkena2_ipd, clkena[2]);
buf (clkena3_ipd, clkena[3]);
buf (clkena4_ipd, clkena[4]);
buf (clkena5_ipd, clkena[5]);
buf (extclkena0_ipd, extclkena[0]);
buf (extclkena1_ipd, extclkena[1]);
buf (extclkena2_ipd, extclkena[2]);
buf (extclkena3_ipd, extclkena[3]);
buf (scanclk_ipd, scanclk);
buf (scanaclr_ipd, scanaclr);
buf (scandata_ipd, scandata);
buf (comparator_ipd, comparator);
buf (clkswitch_ipd, clkswitch);
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer primary_clock_frequency;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer l0_count;
integer l1_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer loop_time_delay;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
integer pull_back_ext_cntr;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time scanaclr_rising_time;
time scanaclr_falling_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg l0_got_first_rising_edge;
reg l1_got_first_rising_edge;
reg vco_l0_last_value;
reg vco_l1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val;
reg [31:0] m_val_tmp;
reg [31:0] m2_val;
reg [31:0] n_val;
reg [31:0] n_val_tmp;
reg [31:0] n2_val;
reg [31:0] m_time_delay_val;
reg [31:0] n_time_delay_val;
reg [31:0] m_delay;
reg [8*6:1] m_mode_val;
reg [8*6:1] m2_mode_val;
reg [8*6:1] n_mode_val;
reg [8*6:1] n2_mode_val;
reg [31:0] l0_high_val;
reg [31:0] l0_low_val;
reg [31:0] l0_initial_val;
reg [31:0] l0_time_delay_val;
reg [8*6:1] l0_mode_val;
reg [31:0] l1_high_val;
reg [31:0] l1_low_val;
reg [31:0] l1_initial_val;
reg [31:0] l1_time_delay_val;
reg [8*6:1] l1_mode_val;
reg [31:0] g0_high_val;
reg [31:0] g0_low_val;
reg [31:0] g0_initial_val;
reg [31:0] g0_time_delay_val;
reg [8*6:1] g0_mode_val;
reg [31:0] g1_high_val;
reg [31:0] g1_low_val;
reg [31:0] g1_initial_val;
reg [31:0] g1_time_delay_val;
reg [8*6:1] g1_mode_val;
reg [31:0] g2_high_val;
reg [31:0] g2_low_val;
reg [31:0] g2_initial_val;
reg [31:0] g2_time_delay_val;
reg [8*6:1] g2_mode_val;
reg [31:0] g3_high_val;
reg [31:0] g3_low_val;
reg [31:0] g3_initial_val;
reg [31:0] g3_time_delay_val;
reg [8*6:1] g3_mode_val;
reg [31:0] e0_high_val;
reg [31:0] e0_low_val;
reg [31:0] e0_initial_val;
reg [31:0] e0_time_delay_val;
reg [8*6:1] e0_mode_val;
reg [31:0] e1_high_val;
reg [31:0] e1_low_val;
reg [31:0] e1_initial_val;
reg [31:0] e1_time_delay_val;
reg [8*6:1] e1_mode_val;
reg [31:0] e2_high_val;
reg [31:0] e2_low_val;
reg [31:0] e2_initial_val;
reg [31:0] e2_time_delay_val;
reg [8*6:1] e2_mode_val;
reg [31:0] e3_high_val;
reg [31:0] e3_low_val;
reg [31:0] e3_initial_val;
reg [31:0] e3_time_delay_val;
reg [8*6:1] e3_mode_val;
reg scanclk_last_value;
reg scanaclr_last_value;
reg transfer;
reg transfer_enable;
reg [288:0] scan_data;
reg schedule_vco;
reg schedule_offset;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
wire inclk_l0;
wire inclk_l1;
wire inclk_m;
wire clk0_tmp;
wire clk1_tmp;
wire clk2_tmp;
wire clk3_tmp;
wire clk4_tmp;
wire clk5_tmp;
wire extclk0_tmp;
wire extclk1_tmp;
wire extclk2_tmp;
wire extclk3_tmp;
wire nce_l0;
wire nce_l1;
wire nce_temp;
reg vco_l0;
reg vco_l1;
wire clk0;
wire clk1;
wire clk2;
wire clk3;
wire clk4;
wire clk5;
wire extclk0;
wire extclk1;
wire extclk2;
wire extclk3;
wire ena0;
wire ena1;
wire ena2;
wire ena3;
wire ena4;
wire ena5;
wire extena0;
wire extena1;
wire extena2;
wire extena3;
wire refclk;
wire fbclk;
wire l0_clk;
wire l1_clk;
wire g0_clk;
wire g1_clk;
wire g2_clk;
wire g3_clk;
wire e0_clk;
wire e1_clk;
wire e2_clk;
wire e3_clk;
wire dffa_out;
wire dffb_out;
wire dffc_out;
wire dffd_out;
wire lvds_dffb_clk;
wire lvds_dffc_clk;
wire lvds_dffd_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg l0_tmp;
reg l1_tmp;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [31:0] ext_fbk_cntr_delay;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
wire inclk_e0;
wire inclk_e1;
wire inclk_e2;
wire inclk_e3;
wire [31:0] cntr_e0_initial;
wire [31:0] cntr_e1_initial;
wire [31:0] cntr_e2_initial;
wire [31:0] cntr_e3_initial;
wire [31:0] cntr_e0_delay;
wire [31:0] cntr_e1_delay;
wire [31:0] cntr_e2_delay;
wire [31:0] cntr_e3_delay;
reg [31:0] ext_fbk_delay;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
// reg [8*6:1] current_clock;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
reg active_clk_was_switched;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
reg scandataout_tmp;
reg scandataout_trigger;
integer quiet_time;
reg pll_in_quiet_period;
time start_quiet_time;
reg quiet_period_violation;
reg reconfig_err;
reg scanclr_violation;
reg scanclr_clk_violation;
reg got_first_scanclk_after_scanclr_inactive_edge;
reg error;
reg no_warn;
// LOCAL_PARAMETERS_BEGIN
parameter EGPP_SCAN_CHAIN = 289;
parameter GPP_SCAN_CHAIN = 193;
parameter TRST = 5000;
parameter TRSTCLK = 5000;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_extclk0_mult_by;
integer i_extclk0_div_by;
integer i_extclk1_mult_by;
integer i_extclk1_div_by;
integer i_extclk2_mult_by;
integer i_extclk2_div_by;
integer i_extclk3_mult_by;
integer i_extclk3_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_l0_high;
integer i_l1_high;
integer i_g0_high;
integer i_g1_high;
integer i_g2_high;
integer i_g3_high;
integer i_e0_high;
integer i_e1_high;
integer i_e2_high;
integer i_e3_high;
integer i_l0_low;
integer i_l1_low;
integer i_g0_low;
integer i_g1_low;
integer i_g2_low;
integer i_g3_low;
integer i_e0_low;
integer i_e1_low;
integer i_e2_low;
integer i_e3_low;
integer i_l0_initial;
integer i_l1_initial;
integer i_g0_initial;
integer i_g1_initial;
integer i_g2_initial;
integer i_g3_initial;
integer i_e0_initial;
integer i_e1_initial;
integer i_e2_initial;
integer i_e3_initial;
reg [8*6:1] i_l0_mode;
reg [8*6:1] i_l1_mode;
reg [8*6:1] i_g0_mode;
reg [8*6:1] i_g1_mode;
reg [8*6:1] i_g2_mode;
reg [8*6:1] i_g3_mode;
reg [8*6:1] i_e0_mode;
reg [8*6:1] i_e1_mode;
reg [8*6:1] i_e2_mode;
reg [8*6:1] i_e3_mode;
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_l0_ph;
integer i_l1_ph;
integer i_g0_ph;
integer i_g1_ph;
integer i_g2_ph;
integer i_g3_ph;
integer i_e0_ph;
integer i_e1_ph;
integer i_e2_ph;
integer i_e3_ph;
integer i_m_ph;
integer m_ph_val;
integer i_l0_time_delay;
integer i_l1_time_delay;
integer i_g0_time_delay;
integer i_g1_time_delay;
integer i_g2_time_delay;
integer i_g3_time_delay;
integer i_e0_time_delay;
integer i_e1_time_delay;
integer i_e2_time_delay;
integer i_e3_time_delay;
integer i_m_time_delay;
integer i_n_time_delay;
integer i_extclk3_counter;
integer i_extclk2_counter;
integer i_extclk1_counter;
integer i_extclk0_counter;
integer i_clk5_counter;
integer i_clk4_counter;
integer i_clk3_counter;
integer i_clk2_counter;
integer i_clk1_counter;
integer i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
reg pll_is_in_reset;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_enable0_counter;
reg [8*`WORD_LENGTH:1] l_enable1_counter;
integer current_clock;
reg is_fast_pll;
reg op_mode;
reg init;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input L0, L0_mode, L1, L1_mode, G0, G0_mode, G1, G1_mode, G2, G2_mode, G3, G3_mode, E0, E0_mode, E1, E1_mode, E2, E2_mode, E3, E3_mode, scan_chain, refclk, m_mod;
integer L0, L1, G0, G1, G2, G3, E0, E1, E2, E3;
reg [8*6:1] L0_mode, L1_mode, G0_mode, G1_mode, G2_mode, G3_mode, E0_mode, E1_mode, E2_mode, E3_mode;
reg [8*5:1] scan_chain;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (L0_mode != "bypass" && L0_mode != " off")
max_modulus = L0;
if (L1 > max_modulus && L1_mode != "bypass" && L1_mode != " off")
max_modulus = L1;
if (G0 > max_modulus && G0_mode != "bypass" && G0_mode != " off")
max_modulus = G0;
if (G1 > max_modulus && G1_mode != "bypass" && G1_mode != " off")
max_modulus = G1;
if (G2 > max_modulus && G2_mode != "bypass" && G2_mode != " off")
max_modulus = G2;
if (G3 > max_modulus && G3_mode != "bypass" && G3_mode != " off")
max_modulus = G3;
if (scan_chain == "long")
begin
if (E0 > max_modulus && E0_mode != "bypass" && E0_mode != " off")
max_modulus = E0;
if (E1 > max_modulus && E1_mode != "bypass" && E1_mode != " off")
max_modulus = E1;
if (E2 > max_modulus && E2_mode != "bypass" && E2_mode != " off")
max_modulus = E2;
if (E3 > max_modulus && E3_mode != "bypass" && E3_mode != " off")
max_modulus = E3;
end
slowest_clk = ((refclk/m_mod) * max_modulus *2);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9,3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = "even";
else
R = "odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
if (counter_low == 0)
counter_low = 1;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the actual time delay for each PLL counter
function integer counter_time_delay;
input clk_time_delay, m_time_delay, n_time_delay;
integer clk_time_delay, m_time_delay, n_time_delay;
begin
counter_time_delay = clk_time_delay + m_time_delay - n_time_delay;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for stratix lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_scan_chain = alpha_tolower(scan_chain);
l_primary_clock = alpha_tolower(primary_clock);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_enable0_counter = alpha_tolower(enable0_counter);
l_enable1_counter = alpha_tolower(enable1_counter);
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
// convert user parameters to advanced
i_n = 1;
if (l_pll_type == "lvds")
i_m = clk0_multiply_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
i_m_time_delay = maxnegabs (str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay = mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (l_pll_type == "lvds")
i_g0_high = counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high = counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_g1_high = counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high = counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high = counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (l_pll_type == "lvds")
begin
i_l0_high = i_g0_high;
i_l1_high = i_g0_high;
end
else
begin
i_l0_high = counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high = counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end
i_e0_high = counter_high(output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high = counter_high(output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high = counter_high(output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high = counter_high(output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (l_pll_type == "lvds")
i_g0_low = counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low = counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_g1_low = counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low = counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low = counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (l_pll_type == "lvds")
begin
i_l0_low = i_g0_low;
i_l1_low = i_g0_low;
end
else
begin
i_l0_low = counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low = counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end
i_e0_low = counter_low(output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low = counter_low(output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low = counter_low(output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low = counter_low(output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
if (l_pll_type == "lvds")
i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
else
i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_g1_initial = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_g2_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_g3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
begin
i_l0_initial = i_g0_initial;
i_l1_initial = i_g0_initial;
end
else
begin
i_l0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_l1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
end
i_e0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs)), i_m, i_n);
i_e1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs)), i_m, i_n);
i_e2_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs)), i_m, i_n);
i_e3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_mode = counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_g1_mode = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (l_pll_type == "lvds")
begin
i_l0_mode = "bypass";
i_l1_mode = "bypass";
end
else
begin
i_l0_mode = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end
i_e0_mode = counter_mode(extclk0_duty_cycle,output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode = counter_mode(extclk1_duty_cycle,output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode = counter_mode(extclk2_duty_cycle,output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode = counter_mode(extclk3_duty_cycle,output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
else
i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_g1_ph = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_g2_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_g3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
begin
i_l0_ph = i_g0_ph;
i_l1_ph = i_g0_ph;
end
else
begin
i_l0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_l1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
end
i_e0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs)), i_m, i_n);
i_e1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs)), i_m, i_n);
i_e2_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs)), i_m, i_n);
i_e3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_time_delay = counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay,
i_n_time_delay);
else
i_g0_time_delay = counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g1_time_delay = counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g2_time_delay = counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g3_time_delay = counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay,
i_n_time_delay);
if (l_pll_type == "lvds")
begin
i_l0_time_delay = i_g0_time_delay;
i_l1_time_delay = i_g0_time_delay;
end
else
begin
i_l0_time_delay = counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay,
i_n_time_delay);
i_l1_time_delay = counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay,
i_n_time_delay);
end
i_e0_time_delay = counter_time_delay ( str2int( extclk0_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e1_time_delay = counter_time_delay ( str2int( extclk1_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e2_time_delay = counter_time_delay ( str2int( extclk2_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e3_time_delay = counter_time_delay ( str2int( extclk3_time_delay),
i_m_time_delay,
i_n_time_delay);
i_extclk3_counter = "e3" ;
i_extclk2_counter = "e2" ;
i_extclk1_counter = "e1" ;
i_extclk0_counter = "e0" ;
i_clk5_counter = "l1" ;
i_clk4_counter = "l0" ;
i_clk3_counter = "g3" ;
i_clk2_counter = "g2" ;
i_clk1_counter = "g1" ;
if (l_pll_type == "lvds")
begin
l_enable0_counter = "l0";
l_enable1_counter = "l1";
i_clk0_counter = "l0" ;
end
else
i_clk0_counter = "g0" ;
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (l_feedback_source == "extclk0")
begin
if (i_e0_mode == "bypass")
output_count = 1;
else
output_count = i_e0_high + i_e0_low;
end
else if (l_feedback_source == "extclk1")
begin
if (i_e1_mode == "bypass")
output_count = 1;
else
output_count = i_e1_high + i_e1_low;
end
else if (l_feedback_source == "extclk2")
begin
if (i_e2_mode == "bypass")
output_count = 1;
else
output_count = i_e2_high + i_e2_low;
end
else if (l_feedback_source == "extclk3")
begin
if (i_e3_mode == "bypass")
output_count = 1;
else
output_count = i_e3_high + i_e3_low;
end
else // default to e0
begin
if (i_e0_mode == "bypass")
output_count = 1;
else
output_count = i_e0_high + i_e0_low;
end
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_l0_high = l0_high;
i_l1_high = l1_high;
i_g0_high = g0_high;
i_g1_high = g1_high;
i_g2_high = g2_high;
i_g3_high = g3_high;
i_e0_high = e0_high;
i_e1_high = e1_high;
i_e2_high = e2_high;
i_e3_high = e3_high;
i_l0_low = l0_low;
i_l1_low = l1_low;
i_g0_low = g0_low;
i_g1_low = g1_low;
i_g2_low = g2_low;
i_g3_low = g3_low;
i_e0_low = e0_low;
i_e1_low = e1_low;
i_e2_low = e2_low;
i_e3_low = e3_low;
i_l0_initial = l0_initial;
i_l1_initial = l1_initial;
i_g0_initial = g0_initial;
i_g1_initial = g1_initial;
i_g2_initial = g2_initial;
i_g3_initial = g3_initial;
i_e0_initial = e0_initial;
i_e1_initial = e1_initial;
i_e2_initial = e2_initial;
i_e3_initial = e3_initial;
i_l0_mode = alpha_tolower(l0_mode);
i_l1_mode = alpha_tolower(l1_mode);
i_g0_mode = alpha_tolower(g0_mode);
i_g1_mode = alpha_tolower(g1_mode);
i_g2_mode = alpha_tolower(g2_mode);
i_g3_mode = alpha_tolower(g3_mode);
i_e0_mode = alpha_tolower(e0_mode);
i_e1_mode = alpha_tolower(e1_mode);
i_e2_mode = alpha_tolower(e2_mode);
i_e3_mode = alpha_tolower(e3_mode);
i_l0_ph = l0_ph;
i_l1_ph = l1_ph;
i_g0_ph = g0_ph;
i_g1_ph = g1_ph;
i_g2_ph = g2_ph;
i_g3_ph = g3_ph;
i_e0_ph = e0_ph;
i_e1_ph = e1_ph;
i_e2_ph = e2_ph;
i_e3_ph = e3_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
i_l0_time_delay = l0_time_delay;
i_l1_time_delay = l1_time_delay;
i_g0_time_delay = g0_time_delay;
i_g1_time_delay = g1_time_delay;
i_g2_time_delay = g2_time_delay;
i_g3_time_delay = g3_time_delay;
i_e0_time_delay = e0_time_delay;
i_e1_time_delay = e1_time_delay;
i_e2_time_delay = e2_time_delay;
i_e3_time_delay = e3_time_delay;
i_m_time_delay = m_time_delay;
i_n_time_delay = n_time_delay;
i_extclk3_counter = alpha_tolower(extclk3_counter);
i_extclk2_counter = alpha_tolower(extclk2_counter);
i_extclk1_counter = alpha_tolower(extclk1_counter);
i_extclk0_counter = alpha_tolower(extclk0_counter);
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end // user to advanced conversion
// set the scan_chain length
if (l_scan_chain == "long")
scan_chain_length = EGPP_SCAN_CHAIN;
else if (l_scan_chain == "short")
scan_chain_length = GPP_SCAN_CHAIN;
if (l_primary_clock == "inclk0")
begin
refclk_period = inclk0_input_frequency * i_n;
primary_clock_frequency = inclk0_input_frequency;
end
else if (l_primary_clock == "inclk1")
begin
refclk_period = inclk1_input_frequency * i_n;
primary_clock_frequency = inclk1_input_frequency;
end
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
schedule_offset = 1;
vco_out[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
l0_got_first_rising_edge = 0;
l1_got_first_rising_edge = 0;
vco_l0_last_value = 0;
l0_count = 1;
l1_count = 1;
l0_tmp = 0;
l1_tmp = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_l0 = 0;
vco_l1 = 0;
total_pull_back = 0;
pull_back_M = 0;
pull_back_ext_cntr = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandataout_tmp = 0;
scandataout_trigger = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val = i_m;
m_time_delay_val = i_m_time_delay;
n_val = i_n;
n_time_delay_val = i_n_time_delay;
m_ph_val = i_m_ph;
m2_val = m2;
n2_val = n2;
if (m_val == 1)
m_mode_val = "bypass";
if (m2_val == 1)
m2_mode_val = "bypass";
if (n_val == 1)
n_mode_val = "bypass";
if (n2_val == 1)
n2_mode_val = "bypass";
if (skip_vco == "on")
begin
m_val = 1;
m_initial_val = 1;
m_time_delay_val = 0;
m_ph_val = 0;
end
l0_high_val = i_l0_high;
l0_low_val = i_l0_low;
l0_initial_val = i_l0_initial;
l0_mode_val = i_l0_mode;
l0_time_delay_val = i_l0_time_delay;
l1_high_val = i_l1_high;
l1_low_val = i_l1_low;
l1_initial_val = i_l1_initial;
l1_mode_val = i_l1_mode;
l1_time_delay_val = i_l1_time_delay;
g0_high_val = i_g0_high;
g0_low_val = i_g0_low;
g0_initial_val = i_g0_initial;
g0_mode_val = i_g0_mode;
g0_time_delay_val = i_g0_time_delay;
g1_high_val = i_g1_high;
g1_low_val = i_g1_low;
g1_initial_val = i_g1_initial;
g1_mode_val = i_g1_mode;
g1_time_delay_val = i_g1_time_delay;
g2_high_val = i_g2_high;
g2_low_val = i_g2_low;
g2_initial_val = i_g2_initial;
g2_mode_val = i_g2_mode;
g2_time_delay_val = i_g2_time_delay;
g3_high_val = i_g3_high;
g3_low_val = i_g3_low;
g3_initial_val = i_g3_initial;
g3_mode_val = i_g3_mode;
g3_time_delay_val = i_g3_time_delay;
e0_high_val = i_e0_high;
e0_low_val = i_e0_low;
e0_initial_val = i_e0_initial;
e0_mode_val = i_e0_mode;
e0_time_delay_val = i_e0_time_delay;
e1_high_val = i_e1_high;
e1_low_val = i_e1_low;
e1_initial_val = i_e1_initial;
e1_mode_val = i_e1_mode;
e1_time_delay_val = i_e1_time_delay;
e2_high_val = i_e2_high;
e2_low_val = i_e2_low;
e2_initial_val = i_e2_initial;
e2_mode_val = i_e2_mode;
e2_time_delay_val = i_e2_time_delay;
e3_high_val = i_e3_high;
e3_low_val = i_e3_low;
e3_initial_val = i_e3_initial;
e3_mode_val = i_e3_mode;
e3_time_delay_val = i_e3_time_delay;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
// current_clock = l_primary_clock;
if (l_primary_clock == "inclk0")
current_clock = 0;
else
current_clock = 1;
if (l_primary_clock == "inclk0")
active_clock = 0;
else
active_clock = 1;
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
active_clk_was_switched = 0;
// initialize quiet_time
quiet_time = slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
l_scan_chain,
refclk_period, m_val);
pll_in_quiet_period = 0;
start_quiet_time = 0;
quiet_period_violation = 0;
reconfig_err = 0;
scanclr_violation = 0;
scanclr_clk_violation = 0;
got_first_scanclk_after_scanclr_inactive_edge = 0;
error = 0;
scanaclr_rising_time = 0;
scanaclr_falling_time = 0;
// VCO feedback loop settings for external feedback mode
// first find which ext counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
if (l_feedback_source == "extclk0")
begin
if (i_extclk0_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk0_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk0_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk0_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk1")
begin
if (i_extclk1_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk1_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk1_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk1_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk2")
begin
if (i_extclk2_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk2_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk2_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk2_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk3")
begin
if (i_extclk3_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk3_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk3_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk3_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
// now save this counter's parameters
if (ext_fbk_cntr == "e0")
begin
ext_fbk_cntr_high = e0_high_val;
ext_fbk_cntr_low = e0_low_val;
ext_fbk_cntr_ph = i_e0_ph;
ext_fbk_cntr_initial = i_e0_initial;
ext_fbk_cntr_delay = e0_time_delay_val;
ext_fbk_cntr_mode = e0_mode_val;
end
else if (ext_fbk_cntr == "e1")
begin
ext_fbk_cntr_high = e1_high_val;
ext_fbk_cntr_low = e1_low_val;
ext_fbk_cntr_ph = i_e1_ph;
ext_fbk_cntr_initial = i_e1_initial;
ext_fbk_cntr_delay = e1_time_delay_val;
ext_fbk_cntr_mode = e1_mode_val;
end
else if (ext_fbk_cntr == "e2")
begin
ext_fbk_cntr_high = e2_high_val;
ext_fbk_cntr_low = e2_low_val;
ext_fbk_cntr_ph = i_e2_ph;
ext_fbk_cntr_initial = i_e2_initial;
ext_fbk_cntr_delay = e2_time_delay_val;
ext_fbk_cntr_mode = e2_mode_val;
end
else if (ext_fbk_cntr == "e3")
begin
ext_fbk_cntr_high = e3_high_val;
ext_fbk_cntr_low = e3_low_val;
ext_fbk_cntr_ph = i_e3_ph;
ext_fbk_cntr_initial = i_e3_initial;
ext_fbk_cntr_delay = e3_time_delay_val;
ext_fbk_cntr_mode = e3_mode_val;
end
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
end
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
else
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 0;
m_val_tmp = m_val;
n_val_tmp = n_val;
pll_is_in_reset = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
end
assign inclk_m = l_operation_mode == "external_feedback" ? (l_feedback_source == "extclk0" ? extclk0_tmp :
l_feedback_source == "extclk1" ? extclk1_tmp :
l_feedback_source == "extclk2" ? extclk2_tmp :
l_feedback_source == "extclk3" ? extclk3_tmp : 1'b0) :
vco_out[m_ph_val];
stratix_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val),
.time_delay(m_delay));
always @(clkswitch_ipd)
begin
if (clkswitch_ipd == 1'b1)
external_switch = 1;
clkloss_tmp <= clkswitch_ipd;
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock !== 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock !== 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
if (current_clock == 0)
current_clk_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
if (current_clock == 1)
current_clk_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock
if (((l_primary_clock == "inclk0") && (clk0_is_bad == 1'b1)) || ((l_primary_clock == "inclk1") && (clk1_is_bad == 1'b1)))
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching
if ((inclk0_ipd !== inclk0_last_value) && (current_clock == 0))
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && (current_clock == 1))
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && (l_enable_switch_over_counter == "on") && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
begin
current_clock = 1;
end
else
begin
current_clock = 0;
end
active_clock = ~active_clock;
active_clk_was_switched = 1;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
and (clkloss, clkloss_tmp, 1'b1);
stratix_n_cntr n1 ( .clk(inclk_n),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val),
.time_delay(n_time_delay_val));
stratix_scale_cntr l0 ( .clk(vco_out[i_l0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(l0_clk),
.high(l0_high_val),
.low(l0_low_val),
.initial_value(l0_initial_val),
.mode(l0_mode_val),
.time_delay(l0_time_delay_val),
.ph_tap(i_l0_ph));
stratix_scale_cntr l1 ( .clk(vco_out[i_l1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(l1_clk),
.high(l1_high_val),
.low(l1_low_val),
.initial_value(l1_initial_val),
.mode(l1_mode_val),
.time_delay(l1_time_delay_val),
.ph_tap(i_l1_ph));
stratix_scale_cntr g0 ( .clk(vco_out[i_g0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g0_clk),
.high(g0_high_val),
.low(g0_low_val),
.initial_value(g0_initial_val),
.mode(g0_mode_val),
.time_delay(g0_time_delay_val),
.ph_tap(i_g0_ph));
stratix_pll_reg lvds_dffa ( .d(comparator_ipd),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(g0_clk),
.q(dffa_out));
stratix_pll_reg lvds_dffb ( .d(dffa_out),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(lvds_dffb_clk),
.q(dffb_out));
assign lvds_dffb_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
stratix_pll_reg lvds_dffc ( .d(dffb_out),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(lvds_dffc_clk),
.q(dffc_out));
assign lvds_dffc_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
assign nce_temp = ~dffc_out && dffb_out;
stratix_pll_reg lvds_dffd ( .d(nce_temp),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(~lvds_dffd_clk),
.q(dffd_out));
assign lvds_dffd_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
assign nce_l0 = (l_enable0_counter == "l0") ? dffd_out : 1'b0;
assign nce_l1 = (l_enable0_counter == "l1") ? dffd_out : 1'b0;
stratix_scale_cntr g1 ( .clk(vco_out[i_g1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g1_clk),
.high(g1_high_val),
.low(g1_low_val),
.initial_value(g1_initial_val),
.mode(g1_mode_val),
.time_delay(g1_time_delay_val),
.ph_tap(i_g1_ph));
stratix_scale_cntr g2 ( .clk(vco_out[i_g2_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g2_clk),
.high(g2_high_val),
.low(g2_low_val),
.initial_value(g2_initial_val),
.mode(g2_mode_val),
.time_delay(g2_time_delay_val),
.ph_tap(i_g2_ph));
stratix_scale_cntr g3 ( .clk(vco_out[i_g3_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g3_clk),
.high(g3_high_val),
.low(g3_low_val),
.initial_value(g3_initial_val),
.mode(g3_mode_val),
.time_delay(g3_time_delay_val),
.ph_tap(i_g3_ph));
assign cntr_e0_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? 1 : e0_initial_val;
assign cntr_e0_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? ext_fbk_delay : e0_time_delay_val;
stratix_scale_cntr e0 ( .clk(vco_out[i_e0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e0_clk),
.high(e0_high_val),
.low(e0_low_val),
.initial_value(cntr_e0_initial),
.mode(e0_mode_val),
.time_delay(cntr_e0_delay),
.ph_tap(i_e0_ph));
assign cntr_e1_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? 1 : e1_initial_val;
assign cntr_e1_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? ext_fbk_delay : e1_time_delay_val;
stratix_scale_cntr e1 ( .clk(vco_out[i_e1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e1_clk),
.high(e1_high_val),
.low(e1_low_val),
.initial_value(cntr_e1_initial),
.mode(e1_mode_val),
.time_delay(cntr_e1_delay),
.ph_tap(i_e1_ph));
assign cntr_e2_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? 1 : e2_initial_val;
assign cntr_e2_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? ext_fbk_delay : e2_time_delay_val;
stratix_scale_cntr e2 ( .clk(vco_out[i_e2_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e2_clk),
.high(e2_high_val),
.low(e2_low_val),
.initial_value(cntr_e2_initial),
.mode(e2_mode_val),
.time_delay(cntr_e2_delay),
.ph_tap(i_e2_ph));
assign cntr_e3_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? 1 : e3_initial_val;
assign cntr_e3_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? ext_fbk_delay : e3_time_delay_val;
stratix_scale_cntr e3 ( .clk(vco_out[i_e3_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e3_clk),
.high(e3_high_val),
.low(e3_low_val),
.initial_value(cntr_e3_initial),
.mode(e3_mode_val),
.time_delay(cntr_e3_delay),
.ph_tap(i_e3_ph));
always @((vco_out[i_l0_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)
begin
if ((areset_ipd == 1'b1) || (ena_ipd == 1'b0) || (stop_vco == 1'b1))
begin
l0_count = 1;
l0_got_first_rising_edge = 0;
end
else begin
if (nce_l0 == 1'b0)
begin
if (l0_got_first_rising_edge == 1'b0)
begin
if (vco_out[i_l0_ph] == 1'b1 && vco_out[i_l0_ph] != vco_l0_last_value)
l0_got_first_rising_edge = 1;
end
else if (vco_out[i_l0_ph] != vco_l0_last_value)
begin
l0_count = l0_count + 1;
if (l0_count == (l0_high_val + l0_low_val) * 2)
l0_count = 1;
end
end
if (vco_out[i_l0_ph] == 1'b0 && vco_out[i_l0_ph] != vco_l0_last_value)
begin
if (l0_count == 1)
begin
l0_tmp = 1;
l0_got_first_rising_edge = 0;
end
else l0_tmp = 0;
end
end
vco_l0_last_value = vco_out[i_l0_ph];
end
always @((vco_out[i_l1_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)
begin
if (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1)
begin
l1_count = 1;
l1_got_first_rising_edge = 0;
end
else begin
if (nce_l1 == 1'b0)
begin
if (l1_got_first_rising_edge == 1'b0)
begin
if (vco_out[i_l1_ph] == 1'b1 && vco_out[i_l1_ph] != vco_l1_last_value)
l1_got_first_rising_edge = 1;
end
else if (vco_out[i_l1_ph] != vco_l1_last_value)
begin
l1_count = l1_count + 1;
if (l1_count == (l1_high_val + l1_low_val) * 2)
l1_count = 1;
end
end
if (vco_out[i_l1_ph] == 1'b0 && vco_out[i_l1_ph] != vco_l1_last_value)
begin
if (l1_count == 1)
begin
l1_tmp = 1;
l1_got_first_rising_edge = 0;
end
else l1_tmp = 0;
end
end
vco_l1_last_value = vco_out[i_l1_ph];
end
assign enable0_tmp = (l_enable0_counter == "l0") ? l0_tmp : l1_tmp;
assign enable1_tmp = (l_enable1_counter == "l0") ? l0_tmp : l1_tmp;
always @ (inclk_n or ena_ipd or areset_ipd)
begin
if (areset_ipd == 'b1)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
if (ena_ipd == 'b1)
begin
gate_count = gate_count + 1;
if (gate_count == gate_lock_counter)
gate_out = 1;
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @ (scanclk_ipd or scanaclr_ipd)
begin
if (scanaclr_ipd === 1'b1 && scanaclr_last_value === 1'b0)
scanaclr_rising_time = $time;
else if (scanaclr_ipd === 1'b0 && scanaclr_last_value === 1'b1)
begin
scanaclr_falling_time = $time;
// check for scanaclr active pulse width
if ($time - scanaclr_rising_time < TRST)
begin
scanclr_violation = 1;
$display ("Warning : Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_rising_time);
$display ("Time: %0t Instance: %m", $time);
end
else begin
scanclr_violation = 0;
for (i = 0; i <= scan_chain_length; i = i + 1)
scan_data[i] = 0;
end
got_first_scanclk_after_scanclr_inactive_edge = 0;
end
else if ((scanclk_ipd === 'b1 && scanclk_last_value !== scanclk_ipd) && (got_first_scanclk_after_scanclr_inactive_edge === 1'b0) && ($time - scanaclr_falling_time < TRSTCLK))
begin
scanclr_clk_violation = 1;
$display ("Warning : Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_falling_time);
$display ("Time: %0t Instance: %m", $time);
got_first_scanclk_after_scanclr_inactive_edge = 1;
end
else if (scanclk_ipd == 'b1 && scanclk_last_value != scanclk_ipd && scanaclr_ipd === 1'b0)
begin
if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
begin
$display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
$display ("Time: %0t Instance: %m", $time);
quiet_period_violation = 1;
end
else begin
pll_in_quiet_period = 0;
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] = scandata_ipd;
end
if (got_first_scanclk_after_scanclr_inactive_edge === 1'b0)
begin
got_first_scanclk_after_scanclr_inactive_edge = 1;
scanclr_clk_violation = 0;
end
end
else if (scanclk_ipd === 1'b0 && scanclk_last_value !== scanclk_ipd && scanaclr_ipd === 1'b0)
begin
if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
begin
$display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
$display ("Time: %0t Instance: %m", $time);
quiet_period_violation = 1;
end
else if (scan_data[scan_chain_length-1] == 1'b1)
begin
pll_in_quiet_period = 1;
quiet_period_violation = 0;
reconfig_err = 0;
start_quiet_time = $time;
// initiate transfer
scandataout_tmp <= 1'b1;
quiet_time = slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
l_scan_chain,
refclk_period, m_val);
scandataout_trigger <= #(quiet_time) ~scandataout_trigger;
transfer <= 1;
end
end
scanclk_last_value = scanclk_ipd;
scanaclr_last_value = scanaclr_ipd;
end
always @(scandataout_trigger)
begin
if (areset_ipd === 1'b0)
scandataout_tmp <= 1'b0;
end
always @(posedge transfer)
begin
if (transfer == 1'b1)
begin
$display("NOTE : Reconfiguring PLL");
$display ("Time: %0t Instance: %m", $time);
if (l_scan_chain == "long")
begin
// cntr e3
error = 0;
if (scan_data[273] == 1'b1)
begin
e3_mode_val = "bypass";
if (scan_data[283] == 1'b1)
begin
e3_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[283] == 1'b1)
e3_mode_val = "odd";
else
e3_mode_val = "even";
// before reading delay bits, clear e3_time_delay_val
e3_time_delay_val = 32'b0;
e3_time_delay_val = scan_data[287:284];
e3_time_delay_val = e3_time_delay_val * 250;
if (e3_time_delay_val > 3000)
e3_time_delay_val = 3000;
e3_high_val[8:0] <= scan_data[272:264];
e3_low_val[8:0] <= scan_data[282:274];
if (scan_data[272:264] == 9'b000000000)
e3_high_val[9:0] <= 10'b1000000000;
else
e3_high_val[9] <= 1'b0;
if (scan_data[282:274] == 9'b000000000)
e3_low_val[9:0] <= 10'b1000000000;
else
e3_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e3")
begin
ext_fbk_cntr_high = e3_high_val;
ext_fbk_cntr_low = e3_low_val;
ext_fbk_cntr_delay = e3_time_delay_val;
ext_fbk_cntr_mode = e3_mode_val;
end
// cntr e2
if (scan_data[249] == 1'b1)
begin
e2_mode_val = "bypass";
if (scan_data[259] == 1'b1)
begin
e2_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[259] == 1'b1)
e2_mode_val = "odd";
else
e2_mode_val = "even";
e2_time_delay_val = 32'b0;
e2_time_delay_val = scan_data[263:260];
e2_time_delay_val = e2_time_delay_val * 250;
if (e2_time_delay_val > 3000)
e2_time_delay_val = 3000;
e2_high_val[8:0] <= scan_data[248:240];
e2_low_val[8:0] <= scan_data[258:250];
if (scan_data[248:240] == 9'b000000000)
e2_high_val[9:0] <= 10'b1000000000;
else
e2_high_val[9] <= 1'b0;
if (scan_data[258:250] == 9'b000000000)
e2_low_val[9:0] <= 10'b1000000000;
else
e2_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e2")
begin
ext_fbk_cntr_high = e2_high_val;
ext_fbk_cntr_low = e2_low_val;
ext_fbk_cntr_delay = e2_time_delay_val;
ext_fbk_cntr_mode = e2_mode_val;
end
// cntr e1
if (scan_data[225] == 1'b1)
begin
e1_mode_val = "bypass";
if (scan_data[235] == 1'b1)
begin
e1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[235] == 1'b1)
e1_mode_val = "odd";
else
e1_mode_val = "even";
e1_time_delay_val = 32'b0;
e1_time_delay_val = scan_data[239:236];
e1_time_delay_val = e1_time_delay_val * 250;
if (e1_time_delay_val > 3000)
e1_time_delay_val = 3000;
e1_high_val[8:0] <= scan_data[224:216];
e1_low_val[8:0] <= scan_data[234:226];
if (scan_data[224:216] == 9'b000000000)
e1_high_val[9:0] <= 10'b1000000000;
else
e1_high_val[9] <= 1'b0;
if (scan_data[234:226] == 9'b000000000)
e1_low_val[9:0] <= 10'b1000000000;
else
e1_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e1")
begin
ext_fbk_cntr_high = e1_high_val;
ext_fbk_cntr_low = e1_low_val;
ext_fbk_cntr_delay = e1_time_delay_val;
ext_fbk_cntr_mode = e1_mode_val;
end
// cntr e0
if (scan_data[201] == 1'b1)
begin
e0_mode_val = "bypass";
if (scan_data[211] == 1'b1)
begin
e0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[211] == 1'b1)
e0_mode_val = "odd";
else
e0_mode_val = "even";
e0_time_delay_val = 32'b0;
e0_time_delay_val = scan_data[215:212];
e0_time_delay_val = e0_time_delay_val * 250;
if (e0_time_delay_val > 3000)
e0_time_delay_val = 3000;
e0_high_val[8:0] <= scan_data[200:192];
e0_low_val[8:0] <= scan_data[210:202];
if (scan_data[200:192] == 9'b000000000)
e0_high_val[9:0] <= 10'b1000000000;
else
e0_high_val[9] <= 1'b0;
if (scan_data[210:202] == 9'b000000000)
e0_low_val[9:0] <= 10'b1000000000;
else
e0_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e0")
begin
ext_fbk_cntr_high = e0_high_val;
ext_fbk_cntr_low = e0_low_val;
ext_fbk_cntr_delay = e0_time_delay_val;
ext_fbk_cntr_mode = e0_mode_val;
end
end
// cntr l1
if (scan_data[177] == 1'b1)
begin
l1_mode_val = "bypass";
if (scan_data[187] == 1'b1)
begin
l1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[187] == 1'b1)
l1_mode_val = "odd";
else
l1_mode_val = "even";
l1_time_delay_val = 32'b0;
l1_time_delay_val = scan_data[191:188];
l1_time_delay_val = l1_time_delay_val * 250;
if (l1_time_delay_val > 3000)
l1_time_delay_val = 3000;
l1_high_val[8:0] <= scan_data[176:168];
l1_low_val[8:0] <= scan_data[186:178];
if (scan_data[176:168] == 9'b000000000)
l1_high_val[9:0] <= 10'b1000000000;
else
l1_high_val[9] <= 1'b0;
if (scan_data[186:178] == 9'b000000000)
l1_low_val[9:0] <= 10'b1000000000;
else
l1_low_val[9] <= 1'b0;
// cntr l0
if (scan_data[153] == 1'b1)
begin
l0_mode_val = "bypass";
if (scan_data[163] == 1'b1)
begin
l0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[163] == 1'b1)
l0_mode_val = "odd";
else
l0_mode_val = "even";
l0_time_delay_val = 32'b0;
l0_time_delay_val = scan_data[167:164];
l0_time_delay_val = l0_time_delay_val * 250;
if (l0_time_delay_val > 3000)
l0_time_delay_val = 3000;
l0_high_val[8:0] <= scan_data[152:144];
l0_low_val[8:0] <= scan_data[162:154];
if (scan_data[152:144] == 9'b000000000)
l0_high_val[9:0] <= 10'b1000000000;
else
l0_high_val[9] <= 1'b0;
if (scan_data[162:154] == 9'b000000000)
l0_low_val[9:0] <= 10'b1000000000;
else
l0_low_val[9] <= 1'b0;
// cntr g3
if (scan_data[129] == 1'b1)
begin
g3_mode_val = "bypass";
if (scan_data[139] == 1'b1)
begin
g3_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[139] == 1'b1)
g3_mode_val = "odd";
else
g3_mode_val = "even";
g3_time_delay_val = 32'b0;
g3_time_delay_val = scan_data[143:140];
g3_time_delay_val = g3_time_delay_val * 250;
if (g3_time_delay_val > 3000)
g3_time_delay_val = 3000;
g3_high_val[8:0] <= scan_data[128:120];
g3_low_val[8:0] <= scan_data[138:130];
if (scan_data[128:120] == 9'b000000000)
g3_high_val[9:0] <= 10'b1000000000;
else
g3_high_val[9] <= 1'b0;
if (scan_data[138:130] == 9'b000000000)
g3_low_val[9:0] <= 10'b1000000000;
else
g3_low_val[9] <= 1'b0;
// cntr g2
if (scan_data[105] == 1'b1)
begin
g2_mode_val = "bypass";
if (scan_data[115] == 1'b1)
begin
g2_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[115] == 1'b1)
g2_mode_val = "odd";
else
g2_mode_val = "even";
g2_time_delay_val = 32'b0;
g2_time_delay_val = scan_data[119:116];
g2_time_delay_val = g2_time_delay_val * 250;
if (g2_time_delay_val > 3000)
g2_time_delay_val = 3000;
g2_high_val[8:0] <= scan_data[104:96];
g2_low_val[8:0] <= scan_data[114:106];
if (scan_data[104:96] == 9'b000000000)
g2_high_val[9:0] <= 10'b1000000000;
else
g2_high_val[9] <= 1'b0;
if (scan_data[114:106] == 9'b000000000)
g2_low_val[9:0] <= 10'b1000000000;
else
g2_low_val[9] <= 1'b0;
// cntr g1
if (scan_data[81] == 1'b1)
begin
g1_mode_val = "bypass";
if (scan_data[91] == 1'b1)
begin
g1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[91] == 1'b1)
g1_mode_val = "odd";
else
g1_mode_val = "even";
g1_time_delay_val = 32'b0;
g1_time_delay_val = scan_data[95:92];
g1_time_delay_val = g1_time_delay_val * 250;
if (g1_time_delay_val > 3000)
g1_time_delay_val = 3000;
g1_high_val[8:0] <= scan_data[80:72];
g1_low_val[8:0] <= scan_data[90:82];
if (scan_data[80:72] == 9'b000000000)
g1_high_val[9:0] <= 10'b1000000000;
else
g1_high_val[9] <= 1'b0;
if (scan_data[90:82] == 9'b000000000)
g1_low_val[9:0] <= 10'b1000000000;
else
g1_low_val[9] <= 1'b0;
// cntr g0
if (scan_data[57] == 1'b1)
begin
g0_mode_val = "bypass";
if (scan_data[67] == 1'b1)
begin
g0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[67] == 1'b1)
g0_mode_val = "odd";
else
g0_mode_val = "even";
g0_time_delay_val = 32'b0;
g0_time_delay_val = scan_data[71:68];
g0_time_delay_val = g0_time_delay_val * 250;
if (g0_time_delay_val > 3000)
g0_time_delay_val = 3000;
g0_high_val[8:0] <= scan_data[56:48];
g0_low_val[8:0] <= scan_data[66:58];
if (scan_data[56:48] == 9'b000000000)
g0_high_val[9:0] <= 10'b1000000000;
else
g0_high_val[9] <= 1'b0;
if (scan_data[66:58] == 9'b000000000)
g0_low_val[9:0] <= 10'b1000000000;
else
g0_low_val[9] <= 1'b0;
// cntr M
error = 0;
m_val_tmp = 0;
m_val_tmp[8:0] = scan_data[32:24];
if (scan_data[33] !== 1'b1)
begin
if (m_val_tmp[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for M counter. Instead, the M counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (m_val_tmp[8:0] == 9'b000000000)
m_val_tmp[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val === "bypass")
$display ("Warning : M counter switched from BYPASS mode to enabled (M modulus = %d). PLL may lose lock.", m_val_tmp[9:0]);
else
$display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
m_mode_val = "";
end
end
else if (scan_data[33] == 1'b1)
begin
if (scan_data[24] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter M in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (m_mode_val !== "bypass")
$display ("Warning : M counter switched from enabled to BYPASS mode. PLL may lose lock.");
m_val_tmp[9:0] = 10'b0000000001;
m_mode_val = "bypass";
$display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (skip_vco == "on")
m_val_tmp[9:0] = 10'b0000000001;
// cntr M2
if (ss > 0)
begin
error = 0;
m2_val[8:0] = scan_data[42:34];
if (scan_data[43] !== 1'b1)
begin
if (m2_val[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for M2 counter. Instead, the M2 counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (m2_val[8:0] == 9'b000000000)
m2_val[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (m2_mode_val === "bypass")
begin
$display ("Warning : M2 counter switched from BYPASS mode to enabled (M2 modulus = %d). Pll may lose lock.", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" M2 modulus = %d ", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
m2_mode_val = "";
end
end
else if (scan_data[43] == 1'b1)
begin
if (scan_data[34] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter M2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (m2_mode_val !== "bypass")
begin
$display ("Warning : M2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
end
m2_val[9:0] = 10'b0000000001;
m2_mode_val = "bypass";
$display(" M2 modulus = %d ", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (m_mode_val != m2_mode_val)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M1/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
m_time_delay_val = 32'b0;
m_time_delay_val = scan_data[47:44];
m_time_delay_val = m_time_delay_val * 250;
if (m_time_delay_val > 3000)
m_time_delay_val = 3000;
if (skip_vco == "on")
m_time_delay_val = 32'b0;
$display(" M time delay = %0d", m_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
// cntr N
error = 0;
n_val_tmp[8:0] = scan_data[8:0];
n_val_tmp[9] = 1'b0;
if (scan_data[9] !== 1'b1)
begin
if (n_val_tmp[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for N counter. Instead, the N counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (n_val_tmp[8:0] == 9'b000000000)
n_val_tmp[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val === "bypass")
begin
$display ("Warning : N counter switched from BYPASS mode to enabled (N modulus = %d). PLL may lose lock.", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" N modulus = %d ", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
n_mode_val = "";
end
end
else if (scan_data[9] == 1'b1) // bypass
begin
if (scan_data[0] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter N in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (n_mode_val !== "bypass")
begin
$display ("Warning : N counter switched from enabled to BYPASS mode. PLL may lose lock.");
$display ("Time: %0t Instance: %m", $time);
end
n_val_tmp[9:0] = 10'b0000000001;
n_mode_val = "bypass";
$display(" N modulus = %d ", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
// cntr N2
if (ss > 0)
begin
error = 0;
n2_val[8:0] = scan_data[18:10];
if (scan_data[19] !== 1'b1)
begin
if (n2_val[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for N2 counter. Instead, the N2 counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (n2_val[8:0] == 9'b000000000)
n2_val = 10'b1000000000;
if (error == 1'b0)
begin
if (n2_mode_val === "bypass")
begin
$display ("Warning : N2 counter switched from BYPASS mode to enabled (N2 modulus = %d). PLL may lose lock.", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" N2 modulus = %d ", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
n2_mode_val = "";
end
end
else if (scan_data[19] == 1'b1) // bypass
begin
if (scan_data[10] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter N2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (n2_mode_val !== "bypass")
begin
$display ("Warning : N2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
$display ("Time: %0t Instance: %m", $time);
end
n2_val[9:0] = 10'b0000000001;
n2_mode_val = "bypass";
$display(" N2 modulus = %d ", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (n_mode_val != n2_mode_val)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N1/N2 counters. Either both should be BYASSED or both NON-BYPASSED.");
$display ("Time: %0t Instance: %m", $time);
end
end // ss > 0
n_time_delay_val = 32'b0;
n_time_delay_val = scan_data[23:20];
n_time_delay_val = n_time_delay_val * 250;
if (n_time_delay_val > 3000)
n_time_delay_val = 3000;
$display(" N time delay = %0d", n_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
transfer <= 0;
// clear the scan_chain
for (i = 0; i <= scan_chain_length; i = i + 1)
scan_data[i] = 0;
end
end
always @(negedge transfer)
begin
if (l_scan_chain == "long")
begin
$display(" E3 high = %d, E3 low = %d, E3 mode = %s, E3 time delay = %0d", e3_high_val[9:0], e3_low_val[9:0], e3_mode_val, e3_time_delay_val);
$display(" E2 high = %d, E2 low = %d, E2 mode = %s, E2 time delay = %0d", e2_high_val[9:0], e2_low_val[9:0], e2_mode_val, e2_time_delay_val);
$display(" E1 high = %d, E1 low = %d, E1 mode = %s, E1 time delay = %0d", e1_high_val[9:0], e1_low_val[9:0], e1_mode_val, e1_time_delay_val);
$display(" E0 high = %d, E0 low = %d, E0 mode = %s, E0 time delay = %0d", e0_high_val[9:0], e0_low_val[9:0], e0_mode_val, e0_time_delay_val);
end
$display(" L1 high = %d, L1 low = %d, L1 mode = %s, L1 time delay = %0d", l1_high_val[9:0], l1_low_val[9:0], l1_mode_val, l1_time_delay_val);
$display(" L0 high = %d, L0 low = %d, L0 mode = %s, L0 time delay = %0d", l0_high_val[9:0], l0_low_val[9:0], l0_mode_val, l0_time_delay_val);
$display(" G3 high = %d, G3 low = %d, G3 mode = %s, G3 time delay = %0d", g3_high_val[9:0], g3_low_val[9:0], g3_mode_val, g3_time_delay_val);
$display(" G2 high = %d, G2 low = %d, G2 mode = %s, G2 time delay = %0d", g2_high_val[9:0], g2_low_val[9:0], g2_mode_val, g2_time_delay_val);
$display(" G1 high = %d, G1 low = %d, G1 mode = %s, G1 time delay = %0d", g1_high_val[9:0], g1_low_val[9:0], g1_mode_val, g1_time_delay_val);
$display(" G0 high = %d, G0 low = %d, G0 mode = %s, G0 time delay = %0d", g0_high_val[9:0], g0_low_val[9:0], g0_mode_val, g0_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
end
always @(schedule_vco or areset_ipd or ena_ipd)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd == 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// if areset is deasserted
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1)
begin
// deassert scandataout now and allow reconfig to complete if
// areset was high during reconfig
if (scandataout_tmp === 1'b1)
scandataout_tmp <= #(quiet_time) 1'b0;
end
// if ena was deasserted
if (ena_ipd == 1'b0 && ena_ipd_last_value !== ena_ipd)
begin
$display (" Note : %s PLL was disabled", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1))
begin
if (areset_ipd === 1'b1)
pll_is_in_reset = 1;
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
schedule_offset = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset enable0 and enable1 counter parameters
// l0_count = 1;
// l1_count = 1;
// l0_got_first_rising_edge = 0;
// l1_got_first_rising_edge = 0;
end else if (ena_ipd === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
end
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val;
loop_initial = i_m_initial - 1;
loop_ph = i_m_ph;
loop_time_delay = m_time_delay_val;
if (l_operation_mode == "external_feedback")
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * (ext_fbk_cntr_modulus));
loop_time_delay = m_time_delay_val + ext_fbk_cntr_delay;
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (l_operation_mode == "external_feedback")
begin
pull_back_ext_cntr = ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier) + fbk_phase;
while (pull_back_ext_cntr > refclk_period)
pull_back_ext_cntr = pull_back_ext_cntr - refclk_period;
pull_back_M = m_time_delay_val + (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_ext_cntr = 0;
pull_back_M = initial_delay + m_time_delay_val + fbk_phase;
end
total_pull_back = pull_back_M + pull_back_ext_cntr;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
if (l_operation_mode == "external_feedback")
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
ext_fbk_delay = pull_back_ext_cntr - fbk_phase;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// add offset
if (schedule_offset == 1'b1)
begin
sched_time = sched_time + offset;
schedule_offset = 0;
end
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
// this may no longer be required
if (sched_time > 0)
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_ipd;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk)
begin
refclk_last_value = refclk;
end
always @(negedge fbclk)
begin
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
n_val <= n_val_tmp;
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ( (vco_max != 0 && vco_min != 0) && (skip_vco == "off") && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
first_schedule = 1;
schedule_offset = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
m_val <= m_val_tmp;
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked == 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
$display ("Note : %s PLL lost lock due to loss of input clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
// if (abs(refclk_period - fbclk_period) > 2)
// begin
// new_m_times_vco_period = refclk_period;
// end
// else if (abs(fbclk_time - refclk_time) <= 2 || (refclk_period - abs(fbclk_time - refclk_time) <= 2))
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
if (l_pll_type == "fast")
locked_tmp = 0;
end
// increment lock counter only if the second part of the above
// time check is NOT true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
first_schedule = 1;
schedule_offset = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
if (abs(fbclk_time - refclk_time) > 1.5 * refclk_period)
begin
// input clock may have stopped : do nothing
end
else begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (quiet_period_violation == 1'b1 || reconfig_err == 1'b1 || scanclr_violation == 1'b1 || scanclr_clk_violation == 1'b1)
begin
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk0_tmp = i_clk0_counter == "l0" ? l0_clk : i_clk0_counter == "l1" ? l1_clk : i_clk0_counter == "g0" ? g0_clk : i_clk0_counter == "g1" ? g1_clk : i_clk0_counter == "g2" ? g2_clk : i_clk0_counter == "g3" ? g3_clk : 1'b0;
assign clk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk0_tmp : 1'bx;
stratix_dffe ena0_reg ( .D(clkena0_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk0_tmp),
.Q(ena0));
assign clk1_tmp = i_clk1_counter == "l0" ? l0_clk : i_clk1_counter == "l1" ? l1_clk : i_clk1_counter == "g0" ? g0_clk : i_clk1_counter == "g1" ? g1_clk : i_clk1_counter == "g2" ? g2_clk : i_clk1_counter == "g3" ? g3_clk : 1'b0;
assign clk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk1_tmp : 1'bx;
stratix_dffe ena1_reg ( .D(clkena1_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk1_tmp),
.Q(ena1));
assign clk2_tmp = i_clk2_counter == "l0" ? l0_clk : i_clk2_counter == "l1" ? l1_clk : i_clk2_counter == "g0" ? g0_clk : i_clk2_counter == "g1" ? g1_clk : i_clk2_counter == "g2" ? g2_clk : i_clk2_counter == "g3" ? g3_clk : 1'b0;
assign clk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk2_tmp : 1'bx;
stratix_dffe ena2_reg ( .D(clkena2_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk2_tmp),
.Q(ena2));
assign clk3_tmp = i_clk3_counter == "l0" ? l0_clk : i_clk3_counter == "l1" ? l1_clk : i_clk3_counter == "g0" ? g0_clk : i_clk3_counter == "g1" ? g1_clk : i_clk3_counter == "g2" ? g2_clk : i_clk3_counter == "g3" ? g3_clk : 1'b0;
assign clk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk3_tmp : 1'bx;
stratix_dffe ena3_reg ( .D(clkena3_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk3_tmp),
.Q(ena3));
assign clk4_tmp = i_clk4_counter == "l0" ? l0_clk : i_clk4_counter == "l1" ? l1_clk : i_clk4_counter == "g0" ? g0_clk : i_clk4_counter == "g1" ? g1_clk : i_clk4_counter == "g2" ? g2_clk : i_clk4_counter == "g3" ? g3_clk : 1'b0;
assign clk4 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk4_tmp : 1'bx;
stratix_dffe ena4_reg ( .D(clkena4_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk4_tmp),
.Q(ena4));
assign clk5_tmp = i_clk5_counter == "l0" ? l0_clk : i_clk5_counter == "l1" ? l1_clk : i_clk5_counter == "g0" ? g0_clk : i_clk5_counter == "g1" ? g1_clk : i_clk5_counter == "g2" ? g2_clk : i_clk5_counter == "g3" ? g3_clk : 1'b0;
assign clk5 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk5_tmp : 1'bx;
stratix_dffe ena5_reg ( .D(clkena5_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk5_tmp),
.Q(ena5));
assign extclk0_tmp = i_extclk0_counter == "e0" ? e0_clk : i_extclk0_counter == "e1" ? e1_clk : i_extclk0_counter == "e2" ? e2_clk : i_extclk0_counter == "e3" ? e3_clk : i_extclk0_counter == "g0" ? g0_clk : 1'b0;
assign extclk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk0_tmp : 1'bx;
stratix_dffe extena0_reg ( .D(extclkena0_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk0_tmp),
.Q(extena0));
assign extclk1_tmp = i_extclk1_counter == "e0" ? e0_clk : i_extclk1_counter == "e1" ? e1_clk : i_extclk1_counter == "e2" ? e2_clk : i_extclk1_counter == "e3" ? e3_clk : i_extclk1_counter == "g0" ? g0_clk : 1'b0;
assign extclk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk1_tmp : 1'bx;
stratix_dffe extena1_reg ( .D(extclkena1_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk1_tmp),
.Q(extena1));
assign extclk2_tmp = i_extclk2_counter == "e0" ? e0_clk : i_extclk2_counter == "e1" ? e1_clk : i_extclk2_counter == "e2" ? e2_clk : i_extclk2_counter == "e3" ? e3_clk : i_extclk2_counter == "g0" ? g0_clk : 1'b0;
assign extclk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk2_tmp : 1'bx;
stratix_dffe extena2_reg ( .D(extclkena2_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk2_tmp),
.Q(extena2));
assign extclk3_tmp = i_extclk3_counter == "e0" ? e0_clk : i_extclk3_counter == "e1" ? e1_clk : i_extclk3_counter == "e2" ? e2_clk : i_extclk3_counter == "e3" ? e3_clk : i_extclk3_counter == "g0" ? g0_clk : 1'b0;
assign extclk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk3_tmp : 1'bx;
stratix_dffe extena3_reg ( .D(extclkena3_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk3_tmp),
.Q(extena3));
assign enable_0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable0_tmp : 1'bx;
assign enable_1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable1_tmp : 1'bx;
// ACCELERATE OUTPUTS
and (clk[0], ena0, clk0);
and (clk[1], ena1, clk1);
and (clk[2], ena2, clk2);
and (clk[3], ena3, clk3);
and (clk[4], ena4, clk4);
and (clk[5], ena5, clk5);
and (extclk[0], extena0, extclk0);
and (extclk[1], extena1, extclk1);
and (extclk[2], extena2, extclk2);
and (extclk[3], extena3, extclk3);
and (enable0, 1'b1, enable_0);
and (enable1, 1'b1, enable_1);
and (scandataout, 1'b1, scandataout_tmp);
endmodule // stratix_pll
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : stratix_dll
//
// Description : Simulation model for the Stratix DLL.
//
// Outputs : Delayctrlout output (active high) indicates when the
// DLL locks to the incoming clock
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module stratix_dll (clk,
delayctrlout
);
// GLOBAL PARAMETERS
parameter input_frequency = "10000 ps";
parameter phase_shift = "0";
parameter sim_valid_lock = 1;
parameter sim_invalid_lock = 5;
parameter lpm_type = "stratix_dll";
// INPUT PORTS
input clk;
// OUTPUT PORTS
output delayctrlout;
// INTERNAL NETS AND VARIABLES
reg clk_ipd_last_value;
reg got_first_rising_edge;
reg got_first_falling_edge;
reg dll_is_locked;
reg start_clk_detect;
reg start_clk_detect_last_value;
reg violation;
reg duty_cycle_warn;
reg input_freq_warn;
time clk_ipd_last_rising_edge;
time clk_ipd_last_falling_edge;
integer clk_per_tolerance;
integer duty_cycle;
integer clk_detect_count;
integer half_cycles_to_lock;
integer half_cycles_to_keep_lock;
integer input_period;
// BUFFER INPUTS
wire clk_ipd;
buf (clk_ipd, clk);
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
initial
begin
clk_ipd_last_value = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
clk_ipd_last_rising_edge = 0;
clk_ipd_last_falling_edge = 0;
input_period = str2int(input_frequency);
duty_cycle = input_period/2;
clk_per_tolerance = input_period * 0.1;
// if sim_valid_lock == 0, DLL starts out locked.
if (sim_valid_lock == 0)
dll_is_locked = 1;
else
dll_is_locked = 0;
clk_detect_count = 0;
start_clk_detect = 0;
start_clk_detect_last_value = 0;
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
violation = 0;
duty_cycle_warn = 1;
input_freq_warn = 1;
end
always @(clk_ipd)
begin
if (clk_ipd == 1'b1 && clk_ipd != clk_ipd_last_value)
begin
// rising edge
if (got_first_rising_edge == 1'b0)
begin
got_first_rising_edge = 1;
half_cycles_to_lock = half_cycles_to_lock + 1;
if (sim_valid_lock > 0 && half_cycles_to_lock >= sim_valid_lock && violation == 1'b0)
begin
dll_is_locked <= 1;
$display(" Note : DLL locked to incoming clock.");
$display("Time: %0t Instance: %m", $time);
end
// start the internal clock that will monitor
// the input clock
start_clk_detect <= 1;
end
else
begin
// reset clock event counter
clk_detect_count = 0;
// check for clk_period violation
if ( (($time - clk_ipd_last_rising_edge) < (input_period - clk_per_tolerance)) || (($time - clk_ipd_last_rising_edge) > (input_period + clk_per_tolerance)) )
begin
violation = 1;
if (input_freq_warn === 1'b1)
begin
$display(" Warning : Input frequency violation");
$display("Time: %0t Instance: %m", $time);
input_freq_warn = 0;
end
end
else if ( (($time - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) || (($time - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) )
begin
// duty cycle violation
violation = 1;
if (duty_cycle_warn === 1'b1)
begin
$display(" Warning : Duty Cycle violation");
$display("Time: %0t Instance: %m", $time);
duty_cycle_warn = 0;
end
end
else
violation = 0;
if (violation)
begin
if (dll_is_locked)
begin
half_cycles_to_keep_lock = half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock)
begin
dll_is_locked <= 0;
$display(" Warning : DLL lost lock due to input frequency/Duty cycle violation.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
end
end
else
half_cycles_to_lock = 0;
end
else begin
if (dll_is_locked == 1'b0)
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock)
begin
dll_is_locked <= 1;
$display(" Note : DLL locked to incoming clock.");
$display("Time: %0t Instance: %m", $time);
end
end
else
half_cycles_to_keep_lock = 0;
end
end
clk_ipd_last_rising_edge = $time;
end
else if (clk_ipd == 1'b0 && clk_ipd != clk_ipd_last_value)
begin
// falling edge
// reset clock event counter
clk_detect_count = 0;
got_first_falling_edge = 1;
if (got_first_rising_edge == 1'b1)
begin
// check for duty cycle violation
if ( (($time - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) || (($time - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) )
begin
violation = 1;
if (duty_cycle_warn === 1'b1)
begin
$display(" Warning : Duty Cycle violation");
$display("Time: %0t Instance: %m", $time);
duty_cycle_warn = 0;
end
end
else
violation = 0;
if (dll_is_locked)
begin
if (violation)
begin
half_cycles_to_keep_lock = half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock)
begin
dll_is_locked <= 0;
$display(" Warning : DLL lost lock due to input frequency/Duty cycle violation.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
end
end
else
half_cycles_to_keep_lock = 0;
end
else
begin
if (violation)
begin
// reset_lock_counter
half_cycles_to_lock = 0;
end
else
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
end
end
end
else
begin
// first clk edge is falling edge, do nothing
end
clk_ipd_last_falling_edge = $time;
end
else
begin
// illegal value
if (dll_is_locked && (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1))
begin
dll_is_locked <= 0;
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
$display(" Error : Illegal value detected on input clock. DLL will lose lock.");
$display("Time: %0t Instance: %m", $time);
end
else if (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1)
begin
// clock started up, then went to 'X'
// this is to weed out the 'X' at start of simulation
$display(" Error : Illegal value detected on input clock.");
$display("Time: %0t Instance: %m", $time);
// reset lock counter
half_cycles_to_lock = 0;
end
end
clk_ipd_last_value = clk_ipd;
end
// ********************************************************************
// The following block generates the internal clock that is used to
// track loss of input clock. A counter counts events on this internal
// clock, and is reset to 0 on event on input clock. If input clock
// flatlines, the counter will exceed the limit and DLL will lose lock.
// Events on internal clock are scheduled at the max. allowable input
// clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
// ********************************************************************
always @(start_clk_detect)
begin
if (start_clk_detect != start_clk_detect_last_value)
begin
// increment clock event counter
clk_detect_count = clk_detect_count + 1;
if (dll_is_locked)
begin
if (clk_detect_count > sim_invalid_lock)
begin
dll_is_locked = 0;
$display(" Warning : DLL lost lock due to loss of input clock.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
clk_detect_count = 0;
start_clk_detect <= #(input_period/2) 1'b0;
end
else
start_clk_detect <= #(input_period/2 + clk_per_tolerance/2) ~start_clk_detect;
end
else if (clk_detect_count > 10)
begin
$display(" Warning : No input clock. DLL will not lock.");
$display("Time: %0t Instance: %m", $time);
clk_detect_count = 0;
end
else
start_clk_detect <= #(input_period/2 + clk_per_tolerance/2) ~start_clk_detect;
end
// save this event value
start_clk_detect_last_value = start_clk_detect;
end
// ACCELERATE OUTPUTS
and (delayctrlout, 1'b1, dll_is_locked);
endmodule
//--------------------------------------------------------------------
//
// Module Name : stratix_jtag
//
// Description : Stratix JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratix_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "stratix_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : stratix_crcblock
//
// Description : Stratix CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratix_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "stratix_crcblock";
endmodule
//---------------------------------------------------------------------
//
// Module Name : stratix_rublock
//
// Description : Stratix RUBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module stratix_rublock
(
clk,
shiftnld,
captnupdt,
regin,
rsttimer,
rconfig,
regout,
pgmout
);
parameter operation_mode = "remote";
parameter sim_init_config = "factory";
parameter sim_init_watchdog_value = 0;
parameter sim_init_page_select = 0;
parameter sim_init_status = 0;
parameter lpm_type = "stratix_rublock";
input clk;
input shiftnld;
input captnupdt;
input regin;
input rsttimer;
input rconfig;
output regout;
output [2:0] pgmout;
reg [16:0] update_reg;
reg [4:0] status_reg;
reg [21:0] shift_reg;
reg [2:0] pgmout_update;
integer i;
// initialize registers
initial
begin
if (operation_mode == "local")
// PGM[] output
pgmout_update = 1;
else
// PGM[] output
pgmout_update = 0;
// Shift reg
shift_reg = 0;
// Status reg
status_reg = sim_init_status;
// wd_timeout field
update_reg[16:5] = sim_init_watchdog_value;
// wd enable field
if (sim_init_watchdog_value > 0)
update_reg[4] = 1;
else
update_reg[4] = 0;
// PGM[] field
update_reg[3:1] = sim_init_page_select;
// AnF bit
if (sim_init_config == "factory")
update_reg[0] = 0;
else
update_reg[0] = 1;
$display("Info: Remote Update Block: Initial configuration:");
$display ("Time: %0t Instance: %m", $time);
$display(" -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to %s", status_reg[0] ? "True" : "False");
$display(" -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False");
$display(" -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False");
$display(" -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False");
$display(" -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False");
$display(" -> Field Configuration Mode is set to %s", update_reg[0] ? "Application" : "Factory");
$display(" -> Field PGM[] Page Select is set to %d", update_reg[3:1]);
$display(" -> Field User Watchdog is set to %s", update_reg[4] ? "Enabled" : "Disabled");
$display(" -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5]);
end
// regout is inverted output of shift-reg bit 0
assign regout = !shift_reg[0];
// pgmout is set when reconfig is asserted
assign pgmout = pgmout_update;
always @(clk)
begin
if (clk == 1)
begin
if (shiftnld == 1)
begin
// register shifting
for (i=0; i<=20; i=i+1)
begin
shift_reg[i] <= shift_reg[i+1];
end
shift_reg[21] <= regin;
end
else if (shiftnld == 0)
begin
// register loading
if (captnupdt == 1)
begin
// capture data into shift register
shift_reg <= {update_reg, status_reg};
end
else if (captnupdt == 0)
begin
// update data from shift into Update Register
if (operation_mode == "remote" && sim_init_config == "factory")
begin
// every bit in Update Reg gets updated
update_reg[16:0] <= shift_reg[21:5];
$display("Info: Remote Update Block: Update Register updated at time %d ps", $time);
$display ("Time: %0t Instance: %m", $time);
$display(" -> Field Configuration Mode is set to %s", shift_reg[5] ? "Application" : "Factory");
$display(" -> Field PGM[] Page Select is set to %d", shift_reg[8:6]);
$display(" -> Field User Watchdog is set to %s", (shift_reg[9] == 1) ? "Enabled" : (shift_reg[9] == 0) ? "Disabled" : "x");
$display(" -> Field User Watchdog Timeout Value is set to %d", shift_reg[21:10]);
end
else
begin
// trying to do update in Application mode
$display("Warning: Remote Update Block: Attempted update of Update Register at time %d ps when Configuration is set to Application", $time);
$display ("Time: %0t Instance: %m", $time);
end
end
else
begin
// invalid captnupdt
// destroys update and shift regs
shift_reg <= 'bx;
if (sim_init_config == "factory")
begin
update_reg[16:1] <= 'bx;
end
end
end
else
begin
// invalid shiftnld: destroys update and shift regs
shift_reg <= 'bx;
if (sim_init_config == "factory")
begin
update_reg[16:1] <= 'bx;
end
end
end
else if (clk != 0)
begin
// invalid clk: destroys registers
shift_reg <= 'bx;
if (sim_init_config == "factory")
begin
update_reg[16:1] <= 'bx;
end
end
end
always @(rconfig)
begin
if (rconfig == 1)
begin
// start reconfiguration
$display("Info: Remote Update Block: Reconfiguration initiated at time %d ps", $time);
$display ("Time: %0t Instance: %m", $time);
$display(" -> Field Configuration Mode is set to %s", update_reg[0] ? "Application" : "Factory");
$display(" -> Field PGM[] Page Select is set to %d", update_reg[3:1]);
$display(" -> Field User Watchdog is set to %s", (update_reg[4] == 1) ? "Enabled" : (update_reg[4] == 0) ? "Disabled" : "x");
$display(" -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5]);
if (operation_mode == "remote")
begin
// set pgm[] to page as set in Update Register
pgmout_update <= update_reg[3:1];
end
else if (operation_mode == "local")
begin
// set pgm[] to page as 001
pgmout_update <= 'b001;
end
else
begin
// invalid rconfig: destroys pgmout
pgmout_update <= 'bx;
end
end
else if (rconfig != 0)
begin
// invalid rconfig: destroys pgmout
pgmout_update <= 'bx;
end
end
endmodule
//------------------------------------------------------------------
//
// Module Name : stratix_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module stratix_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // stratix_routing_wire
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*###########################################################################
# Function: Generates clocks for eLink module:
# CCLK_N/P - Epiphany Core Clock, Differential, must be connected
# directly to IO pins.
#
# lclk_p - Parallel data clock, at bit rate / 8
#
# lclk_s - Serial DDR data clock, at bit rate / 2
#
# lclk_out - DDR "Clock" clock, to generate LCLK output
# At bit rate / 2, 90deg shifted from lclk_s
#
# Inputs:
# ecfg_cclk_en - Enable the CCLK output
# ecfg_cclk_div - CCLK divider
# ecfg_cclk_pllcfg - PLL configuration (not implemented)
#
# Notes: Uses Xilinx macros throughout
#
############################################################################
*/
`timescale 1ns/1ps
module eclock (/*AUTOARG*/
// Outputs
CCLK_P, CCLK_N, lclk_s, lclk_out, lclk_p,
// Inputs
clkin, reset, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg
);
// Parameters must be set as follows:
// PFD input frequency = 1/CLKIN1_PERIOD / DIVCLK_DIVIDE (10-450MHz)
// VCO frequency = PFD input frequency * CLKFBOUT_MULT (800-1600MHz)
// Output frequency = VCO frequency / CLKOUTn_DIVIDE
parameter CLKIN_PERIOD = 10.000; // ns -> 100MHz
parameter CLKIN_DIVIDE = 1;
parameter VCO_MULT = 12; // VCO = 1200MHz
parameter CCLK_DIVIDE = 2; // CCLK = 600MHz (at /1 setting)
parameter LCLK_DIVIDE = 4; // LCLK = 300MHz (600MB/s eLink, 75MW/s parallel)
parameter FEATURE_CCLK_DIV = 1'b1;
parameter IOSTD_ELINK = "LVDS_25";
// input clock & reset
input clkin;
input reset;
// From configuration register
input ecfg_cclk_en; //cclk enable
input [3:0] ecfg_cclk_div; //cclk divider setting
input [3:0] ecfg_cclk_pllcfg; //pll configuration TODO: ??
output CCLK_P, CCLK_N;
output lclk_s;
output lclk_out;
output lclk_p;
// Wires
wire cclk_src;
wire cclk_base;
wire cclk_p_src;
wire cclk_p;
wire cclk;
wire lclk_s_src;
wire lclk_out_src;
wire lclk_p_src;
wire clkfb;
// PLL Primitive
PLLE2_BASE
#(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(VCO_MULT), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(CLKIN_PERIOD),// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(CCLK_DIVIDE),
.CLKOUT1_DIVIDE(LCLK_DIVIDE),
.CLKOUT2_DIVIDE(LCLK_DIVIDE),
.CLKOUT3_DIVIDE(LCLK_DIVIDE * 4),
.CLKOUT4_DIVIDE(CCLK_DIVIDE * 4),
.CLKOUT5_DIVIDE(128),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(90.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(CLKIN_DIVIDE),// Master division value, (1-56)
.REF_JITTER1(0.01), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) eclk_pll
(
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(cclk_src), // 1-bit output: CLKOUT0
.CLKOUT1(lclk_s_src), // 1-bit output: CLKOUT1
.CLKOUT2(lclk_out_src), // 1-bit output: CLKOUT2
.CLKOUT3(lclk_p_src), // 1-bit output: CLKOUT3
.CLKOUT4(cclk_p_src), // 1-bit output: CLKOUT4
.CLKOUT5(), // 1-bit output: CLKOUT5
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(clkfb), // 1-bit output: Feedback clock
.LOCKED(), // 1-bit output: LOCK
.CLKIN1(clkin), // 1-bit input: Input clock
// Control Ports: 1-bit (each) inpu: PLL control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(1'b0), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(clkfb) // 1-bit input: Feedback clock
);
// Output buffering
BUFG cclk_buf
(.O (cclk_base),
.I (cclk_src));
BUFG cclk_p_buf
(.O (cclk_p),
.I (cclk_p_src));
BUFG lclk_s_buf
(.O (lclk_s),
.I (lclk_s_src));
BUFG lclk_out_buf
(.O (lclk_out),
.I (lclk_out_src));
BUFG lclk_p_buf
(.O (lclk_p),
.I (lclk_p_src));
generate
if( FEATURE_CCLK_DIV ) begin : gen_cclk_div
// Create adjustable (but fast) CCLK
wire rxi_cclk_out;
reg [8:1] cclk_pattern;
reg [3:0] clk_div_sync;
reg enb_sync;
always @ (posedge cclk_p) begin // Might need x-clock TIG here
clk_div_sync <= ecfg_cclk_div;
enb_sync <= ecfg_cclk_en;
if(enb_sync)
case(clk_div_sync)
4'h0: cclk_pattern <= 8'd0; // Clock OFF
4'h7: cclk_pattern <= 8'b10101010; // Divide by 1
4'h6: cclk_pattern <= 8'b11001100; // Divide by 2
4'h5: cclk_pattern <= 8'b11110000; // Divide by 4
default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8
endcase
else
cclk_pattern <= 8'b00000000;
end // always @ (posedge lclk_p)
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_inst
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(cclk), // 1-bit output: Data path output
.SHIFTOUT1(), // SHIFTOUTn: 1-bit (each): Data output expansion
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(cclk_base), // 1-bit input: High speed clock
.CLKDIV(cclk_p), // 1-bit input: Divided clock
.D1(cclk_pattern[1]), // D1 - D8: Parallel data inputs (1-bit each)
.D2(cclk_pattern[2]),
.D3(cclk_pattern[3]),
.D4(cclk_pattern[4]),
.D5(cclk_pattern[5]),
.D6(cclk_pattern[6]),
.D7(cclk_pattern[7]),
.D8(cclk_pattern[8]),
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(reset), // 1-bit input: Reset
.SHIFTIN1(1'b0), // SHIFTINn: Data input expansion (1-bit each)
.SHIFTIN2(1'b0),
.T1(1'b0), // T1 - T4: Parallel 3-state inputs
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
end else begin : gen_fixed_cclk // Non-dividable CCLK
reg enb_sync;
always @ (posedge cclk_p)
enb_sync <= ecfg_cclk_en;
// The following does not result in timing failures,
// but doesn't seem glitch-safe
assign cclk = cclk_base & enb_sync;
end
endgenerate
// xilinx OBUFDS instantiation
//
OBUFDS
#(.IOSTANDARD (IOSTD_ELINK))
obufds_cclk_inst
(.O (CCLK_P),
.OB (CCLK_N),
.I (cclk));
endmodule // eclock
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
// Innediate assert
labeled_imas: assert #0 (1);
assert final (1);
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Tue May 26 11:16:08 2015
//Host : WK49-Ubuntu running 64-bit Ubuntu 14.04.2 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDC_scl_i,
DDC_scl_o,
DDC_scl_t,
DDC_sda_i,
DDC_sda_o,
DDC_sda_t,
clk,
hdmi_clk_n,
hdmi_clk_p,
hdmi_d_n,
hdmi_d_p,
hdmi_hpd,
hdmi_out_en,
vga_b,
vga_g,
vga_hs,
vga_r,
vga_vs);
input DDC_scl_i;
output DDC_scl_o;
output DDC_scl_t;
input DDC_sda_i;
output DDC_sda_o;
output DDC_sda_t;
input clk;
input hdmi_clk_n;
input hdmi_clk_p;
input [2:0]hdmi_d_n;
input [2:0]hdmi_d_p;
output [0:0]hdmi_hpd;
output [0:0]hdmi_out_en;
output [4:0]vga_b;
output [5:0]vga_g;
output vga_hs;
output [4:0]vga_r;
output vga_vs;
wire GND_2;
wire TMDS_Clk_n_1;
wire TMDS_Clk_p_1;
wire [2:0]TMDS_Data_n_1;
wire [2:0]TMDS_Data_p_1;
wire clk_1;
wire clk_wiz_0_clk_out1;
wire dvi2rgb_0_DDC_SCL_I;
wire dvi2rgb_0_DDC_SCL_O;
wire dvi2rgb_0_DDC_SCL_T;
wire dvi2rgb_0_DDC_SDA_I;
wire dvi2rgb_0_DDC_SDA_O;
wire dvi2rgb_0_DDC_SDA_T;
wire dvi2rgb_0_PixelClk;
wire dvi2rgb_0_RGB_ACTIVE_VIDEO;
wire [23:0]dvi2rgb_0_RGB_DATA;
wire dvi2rgb_0_RGB_HSYNC;
wire dvi2rgb_0_RGB_VSYNC;
wire [4:0]rgb2vga_0_vga_pBlue;
wire [5:0]rgb2vga_0_vga_pGreen;
wire rgb2vga_0_vga_pHSync;
wire [4:0]rgb2vga_0_vga_pRed;
wire rgb2vga_0_vga_pVSync;
wire [0:0]xlconstant_0_dout;
wire [0:0]xlconstant_1_dout;
assign DDC_scl_o = dvi2rgb_0_DDC_SCL_O;
assign DDC_scl_t = dvi2rgb_0_DDC_SCL_T;
assign DDC_sda_o = dvi2rgb_0_DDC_SDA_O;
assign DDC_sda_t = dvi2rgb_0_DDC_SDA_T;
assign TMDS_Clk_n_1 = hdmi_clk_n;
assign TMDS_Clk_p_1 = hdmi_clk_p;
assign TMDS_Data_n_1 = hdmi_d_n[2:0];
assign TMDS_Data_p_1 = hdmi_d_p[2:0];
assign clk_1 = clk;
assign dvi2rgb_0_DDC_SCL_I = DDC_scl_i;
assign dvi2rgb_0_DDC_SDA_I = DDC_sda_i;
assign hdmi_hpd[0] = xlconstant_1_dout;
assign hdmi_out_en[0] = xlconstant_0_dout;
assign vga_b[4:0] = rgb2vga_0_vga_pBlue;
assign vga_g[5:0] = rgb2vga_0_vga_pGreen;
assign vga_hs = rgb2vga_0_vga_pHSync;
assign vga_r[4:0] = rgb2vga_0_vga_pRed;
assign vga_vs = rgb2vga_0_vga_pVSync;
design_1_xlconstant_0_1 GND
(.dout(xlconstant_0_dout));
GND GND_1
(.G(GND_2));
design_1_xlconstant_1_0 VDD
(.dout(xlconstant_1_dout));
design_1_clk_wiz_0_0 clk_wiz_0
(.clk_in1(clk_1),
.clk_out1(clk_wiz_0_clk_out1),
.reset(GND_2));
design_1_dvi2rgb_0_0 dvi2rgb_0
(.DDC_SCL_I(dvi2rgb_0_DDC_SCL_I),
.DDC_SCL_O(dvi2rgb_0_DDC_SCL_O),
.DDC_SCL_T(dvi2rgb_0_DDC_SCL_T),
.DDC_SDA_I(dvi2rgb_0_DDC_SDA_I),
.DDC_SDA_O(dvi2rgb_0_DDC_SDA_O),
.DDC_SDA_T(dvi2rgb_0_DDC_SDA_T),
.PixelClk(dvi2rgb_0_PixelClk),
.RefClk(clk_wiz_0_clk_out1),
.TMDS_Clk_n(TMDS_Clk_n_1),
.TMDS_Clk_p(TMDS_Clk_p_1),
.TMDS_Data_n(TMDS_Data_n_1),
.TMDS_Data_p(TMDS_Data_p_1),
.aRst(GND_2),
.pRst(GND_2),
.vid_pData(dvi2rgb_0_RGB_DATA),
.vid_pHSync(dvi2rgb_0_RGB_HSYNC),
.vid_pVDE(dvi2rgb_0_RGB_ACTIVE_VIDEO),
.vid_pVSync(dvi2rgb_0_RGB_VSYNC));
design_1_rgb2vga_0_0 rgb2vga_0
(.PixelClk(dvi2rgb_0_PixelClk),
.rgb_pData(dvi2rgb_0_RGB_DATA),
.rgb_pHSync(dvi2rgb_0_RGB_HSYNC),
.rgb_pVDE(dvi2rgb_0_RGB_ACTIVE_VIDEO),
.rgb_pVSync(dvi2rgb_0_RGB_VSYNC),
.vga_pBlue(rgb2vga_0_vga_pBlue),
.vga_pGreen(rgb2vga_0_vga_pGreen),
.vga_pHSync(rgb2vga_0_vga_pHSync),
.vga_pRed(rgb2vga_0_vga_pRed),
.vga_pVSync(rgb2vga_0_vga_pVSync));
endmodule
|
module ghrd_10as066n2_pr_region_controller_0 (
input wire avl_csr_read, // avl_csr.read
input wire avl_csr_write, // .write
input wire [1:0] avl_csr_address, // .address
input wire [31:0] avl_csr_writedata, // .writedata
output wire [31:0] avl_csr_readdata, // .readdata
output wire bridge_freeze0_freeze, // bridge_freeze0.freeze
input wire bridge_freeze0_illegal_request, // .illegal_request
output wire bridge_freeze1_freeze, // bridge_freeze1.freeze
input wire bridge_freeze1_illegal_request, // .illegal_request
input wire clock_clk, // clock.clk
output wire pr_handshake_start_req, // pr_handshake.start_req
input wire pr_handshake_start_ack, // .start_ack
output wire pr_handshake_stop_req, // .stop_req
input wire pr_handshake_stop_ack, // .stop_ack
input wire reset_reset, // reset.reset
output wire reset_source_reset // reset_source.reset
);
endmodule
|
// ECP5 Blackbox cells
// FIXME: Create sim models
(* blackbox *)
module MULT18X18D(
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
input CLK0, CLK1, CLK2, CLK3,
input CE0, CE1, CE2, CE3,
input RST0, RST1, RST2, RST3,
input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
output SIGNEDP
);
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
parameter REG_INPUTB_CLK = "NONE";
parameter REG_INPUTB_CE = "CE0";
parameter REG_INPUTB_RST = "RST0";
parameter REG_INPUTC_CLK = "NONE";
parameter REG_PIPELINE_CLK = "NONE";
parameter REG_PIPELINE_CE = "CE0";
parameter REG_PIPELINE_RST = "RST0";
parameter REG_OUTPUT_CLK = "NONE";
parameter [127:0] CLK0_DIV = "ENABLED";
parameter [127:0] CLK1_DIV = "ENABLED";
parameter [127:0] CLK2_DIV = "ENABLED";
parameter [127:0] CLK3_DIV = "ENABLED";
parameter [127:0] GSR = "ENABLED";
parameter [127:0] SOURCEB_MODE = "B_SHIFT";
parameter [127:0] RESETMODE = "SYNC";
endmodule
(* blackbox *)
module ALU54B(
input CLK0, CLK1, CLK2, CLK3,
input CE0, CE1, CE2, CE3,
input RST0, RST1, RST2, RST3,
input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
output EQZ, EQZM, EQOM, EQPAT, EQPATB,
output OVER, UNDER, OVERUNDER,
output SIGNEDR
);
parameter REG_INPUTC0_CLK = "NONE";
parameter REG_INPUTC1_CLK = "NONE";
parameter REG_OPCODEOP0_0_CLK = "NONE";
parameter REG_OPCODEOP0_0_CE = "CE0";
parameter REG_OPCODEOP0_0_RST = "RST0";
parameter REG_OPCODEOP1_0_CLK = "NONE";
parameter REG_OPCODEOP0_1_CLK = "NONE";
parameter REG_OPCODEOP0_1_CE = "CE0";
parameter REG_OPCODEOP0_1_RST = "RST0";
parameter REG_OPCODEIN_0_CLK = "NONE";
parameter REG_OPCODEIN_0_CE = "CE0";
parameter REG_OPCODEIN_0_RST = "RST0";
parameter REG_OPCODEIN_1_CLK = "NONE";
parameter REG_OPCODEIN_1_CE = "CE0";
parameter REG_OPCODEIN_1_RST = "RST0";
parameter REG_OUTPUT0_CLK = "NONE";
parameter REG_OUTPUT1_CLK = "NONE";
parameter REG_FLAG_CLK = "NONE";
parameter [127:0] MCPAT_SOURCE = "STATIC";
parameter [127:0] MASKPAT_SOURCE = "STATIC";
parameter MASK01 = "0x00000000000000";
parameter [127:0] CLK0_DIV = "ENABLED";
parameter [127:0] CLK1_DIV = "ENABLED";
parameter [127:0] CLK2_DIV = "ENABLED";
parameter [127:0] CLK3_DIV = "ENABLED";
parameter MCPAT = "0x00000000000000";
parameter MASKPAT = "0x00000000000000";
parameter RNDPAT = "0x00000000000000";
parameter [127:0] GSR = "ENABLED";
parameter [127:0] RESETMODE = "SYNC";
parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
parameter LEGACY = "DISABLED";
endmodule
(* blackbox *)
module EHXPLLL (
input CLKI, CLKFB,
input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
input STDBY, PLLWAKESYNC,
input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
output CLKOP, CLKOS, CLKOS2, CLKOS3,
output LOCK, INTLOCK,
output REFCLK, CLKINTFB
);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
parameter CLKOS_DIV = 8;
parameter CLKOS2_DIV = 8;
parameter CLKOS3_DIV = 8;
parameter CLKOP_ENABLE = "ENABLED";
parameter CLKOS_ENABLE = "DISABLED";
parameter CLKOS2_ENABLE = "DISABLED";
parameter CLKOS3_ENABLE = "DISABLED";
parameter CLKOP_CPHASE = 0;
parameter CLKOS_CPHASE = 0;
parameter CLKOS2_CPHASE = 0;
parameter CLKOS3_CPHASE = 0;
parameter CLKOP_FPHASE = 0;
parameter CLKOS_FPHASE = 0;
parameter CLKOS2_FPHASE = 0;
parameter CLKOS3_FPHASE = 0;
parameter FEEDBK_PATH = "CLKOP";
parameter CLKOP_TRIM_POL = "RISING";
parameter CLKOP_TRIM_DELAY = 0;
parameter CLKOS_TRIM_POL = "RISING";
parameter CLKOS_TRIM_DELAY = 0;
parameter OUTDIVIDER_MUXA = "DIVA";
parameter OUTDIVIDER_MUXB = "DIVB";
parameter OUTDIVIDER_MUXC = "DIVC";
parameter OUTDIVIDER_MUXD = "DIVD";
parameter PLL_LOCK_MODE = 0;
parameter PLL_LOCK_DELAY = 200;
parameter STDBY_ENABLE = "DISABLED";
parameter REFIN_RESET = "DISABLED";
parameter SYNC_ENABLE = "DISABLED";
parameter INT_LOCK_STICKY = "ENABLED";
parameter DPHASE_SOURCE = "DISABLED";
parameter PLLRST_ENA = "DISABLED";
parameter INTFB_WAKE = "DISABLED";
endmodule
(* blackbox *)
module DTR(
input STARTPULSE,
output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
);
endmodule
(* blackbox *)
module OSCG(
output OSC
);
parameter DIV = 128;
endmodule
(* blackbox *) (* keep *)
module USRMCLK(
input USRMCLKI, USRMCLKTS,
output USRMCLKO
);
endmodule
(* blackbox *) (* keep *)
module JTAGG(
input TCK, TMS, TDI, JTDO2, JTDO1,
output TDO, JTDI, JTCK, JRTI2, JRTI1,
output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
);
parameter ER1 = "ENABLED";
parameter ER2 = "ENABLED";
endmodule
(* blackbox *)
module DELAYF(
input A, LOADN, MOVE, DIRECTION,
output Z, CFLAG
);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
endmodule
(* blackbox *)
module DELAYG(
input A,
output Z
);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
endmodule
(* blackbox *)
module IDDRX1F(
input D, SCLK, RST,
output Q0, Q1
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module IDDRX2F(
input D, SCLK, ECLK, RST,
output Q0, Q1, Q2, Q3
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module IDDR71B(
input D, SCLK, ECLK, RST, ALIGNWD,
output Q0, Q1, Q2, Q3, Q4, Q5, Q6
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module IDDRX2DQA(
input D, DQSR90, ECLK, SCLK, RST,
input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
output Q0, Q1, Q2, Q3, QWL
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX1F(
input SCLK, RST, D0, D1,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX2F(
input SCLK, ECLK, RST, D0, D1, D2, D3,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDR71B(
input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module OSHX2A(
input D0, D1, RST, ECLK, SCLK,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX2DQA(
input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module ODDRX2DQSB(
input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
output Q
);
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module TSHX2DQA(
input T0, T1, SCLK, ECLK, DQSW270, RST,
output Q
);
parameter GSR = "ENABLED";
parameter REGSET = "SET";
endmodule
(* blackbox *)
module TSHX2DQSA(
input T0, T1, SCLK, ECLK, DQSW, RST,
output Q
);
parameter GSR = "ENABLED";
parameter REGSET = "SET";
endmodule
(* blackbox *)
module DQSBUFM(
input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
input ECLK, SCLK,
input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0,
input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
output DQSR90, DQSW, DQSW270,
output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
);
parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
parameter DQS_LI_DEL_VAL = 0;
parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
parameter DQS_LO_DEL_VAL = 0;
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module DDRDLLA(
input CLK, RST, UDDCNTLN, FREEZE,
output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
);
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
endmodule
(* blackbox *)
module CLKDIVF(
input CLKI, RST, ALIGNWD,
output CDIVX
);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
endmodule
(* blackbox *)
module ECLKSYNCB(
input ECLKI, STOP,
output ECLKO
);
endmodule
(* blackbox *)
module ECLKBRIDGECS(
input CLK0, CLK1, SEL,
output ECSOUT
);
endmodule
(* blackbox *)
module DCCA(
input CLKI, CE,
output CLKO
);
endmodule
(* blackbox *) (* keep *)
module DCUA(
input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
input D_REFCLKI,
output D_FFS_PLOL
);
parameter CH0_AUTO_CALIB_EN = "0b0";
parameter CH0_AUTO_FACQ_EN = "0b0";
parameter CH0_BAND_THRESHOLD = "0b000000";
parameter CH0_CALIB_CK_MODE = "0b0";
parameter CH0_CC_MATCH_1 = "0b0000000000";
parameter CH0_CC_MATCH_2 = "0b0000000000";
parameter CH0_CC_MATCH_3 = "0b0000000000";
parameter CH0_CC_MATCH_4 = "0b0000000000";
parameter CH0_CDR_CNT4SEL = "0b00";
parameter CH0_CDR_CNT8SEL = "0b00";
parameter CH0_CTC_BYPASS = "0b0";
parameter CH0_DCOATDCFG = "0b00";
parameter CH0_DCOATDDLY = "0b00";
parameter CH0_DCOBYPSATD = "0b0";
parameter CH0_DCOCALDIV = "0b000";
parameter CH0_DCOCTLGI = "0b000";
parameter CH0_DCODISBDAVOID = "0b0";
parameter CH0_DCOFLTDAC = "0b00";
parameter CH0_DCOFTNRG = "0b000";
parameter CH0_DCOIOSTUNE = "0b000";
parameter CH0_DCOITUNE = "0b00";
parameter CH0_DCOITUNE4LSB = "0b000";
parameter CH0_DCOIUPDNX2 = "0b0";
parameter CH0_DCONUOFLSB = "0b000";
parameter CH0_DCOSCALEI = "0b00";
parameter CH0_DCOSTARTVAL = "0b000";
parameter CH0_DCOSTEP = "0b00";
parameter CH0_DEC_BYPASS = "0b0";
parameter CH0_ENABLE_CG_ALIGN = "0b0";
parameter CH0_ENC_BYPASS = "0b0";
parameter CH0_FF_RX_F_CLK_DIS = "0b0";
parameter CH0_FF_RX_H_CLK_EN = "0b0";
parameter CH0_FF_TX_F_CLK_DIS = "0b0";
parameter CH0_FF_TX_H_CLK_EN = "0b0";
parameter CH0_GE_AN_ENABLE = "0b0";
parameter CH0_INVERT_RX = "0b0";
parameter CH0_INVERT_TX = "0b0";
parameter CH0_LDR_CORE2TX_SEL = "0b0";
parameter CH0_LDR_RX2CORE_SEL = "0b0";
parameter CH0_LEQ_OFFSET_SEL = "0b0";
parameter CH0_LEQ_OFFSET_TRIM = "0b000";
parameter CH0_LSM_DISABLE = "0b0";
parameter CH0_MATCH_2_ENABLE = "0b0";
parameter CH0_MATCH_4_ENABLE = "0b0";
parameter CH0_MIN_IPG_CNT = "0b00";
parameter CH0_PCIE_EI_EN = "0b0";
parameter CH0_PCIE_MODE = "0b0";
parameter CH0_PCS_DET_TIME_SEL = "0b00";
parameter CH0_PDEN_SEL = "0b0";
parameter CH0_PRBS_ENABLE = "0b0";
parameter CH0_PRBS_LOCK = "0b0";
parameter CH0_PRBS_SELECTION = "0b0";
parameter CH0_RATE_MODE_RX = "0b0";
parameter CH0_RATE_MODE_TX = "0b0";
parameter CH0_RCV_DCC_EN = "0b0";
parameter CH0_REG_BAND_OFFSET = "0b0000";
parameter CH0_REG_BAND_SEL = "0b000000";
parameter CH0_REG_IDAC_EN = "0b0";
parameter CH0_REG_IDAC_SEL = "0b0000000000";
parameter CH0_REQ_EN = "0b0";
parameter CH0_REQ_LVL_SET = "0b00";
parameter CH0_RIO_MODE = "0b0";
parameter CH0_RLOS_SEL = "0b0";
parameter CH0_RPWDNB = "0b0";
parameter CH0_RTERM_RX = "0b00000";
parameter CH0_RTERM_TX = "0b00000";
parameter CH0_RXIN_CM = "0b00";
parameter CH0_RXTERM_CM = "0b00";
parameter CH0_RX_DCO_CK_DIV = "0b000";
parameter CH0_RX_DIV11_SEL = "0b0";
parameter CH0_RX_GEAR_BYPASS = "0b0";
parameter CH0_RX_GEAR_MODE = "0b0";
parameter CH0_RX_LOS_CEQ = "0b00";
parameter CH0_RX_LOS_EN = "0b0";
parameter CH0_RX_LOS_HYST_EN = "0b0";
parameter CH0_RX_LOS_LVL = "0b000";
parameter CH0_RX_RATE_SEL = "0b0000";
parameter CH0_RX_SB_BYPASS = "0b0";
parameter CH0_SB_BYPASS = "0b0";
parameter CH0_SEL_SD_RX_CLK = "0b0";
parameter CH0_TDRV_DAT_SEL = "0b00";
parameter CH0_TDRV_POST_EN = "0b0";
parameter CH0_TDRV_PRE_EN = "0b0";
parameter CH0_TDRV_SLICE0_CUR = "0b000";
parameter CH0_TDRV_SLICE0_SEL = "0b00";
parameter CH0_TDRV_SLICE1_CUR = "0b000";
parameter CH0_TDRV_SLICE1_SEL = "0b00";
parameter CH0_TDRV_SLICE2_CUR = "0b00";
parameter CH0_TDRV_SLICE2_SEL = "0b00";
parameter CH0_TDRV_SLICE3_CUR = "0b00";
parameter CH0_TDRV_SLICE3_SEL = "0b00";
parameter CH0_TDRV_SLICE4_CUR = "0b00";
parameter CH0_TDRV_SLICE4_SEL = "0b00";
parameter CH0_TDRV_SLICE5_CUR = "0b00";
parameter CH0_TDRV_SLICE5_SEL = "0b00";
parameter CH0_TPWDNB = "0b0";
parameter CH0_TX_CM_SEL = "0b00";
parameter CH0_TX_DIV11_SEL = "0b0";
parameter CH0_TX_GEAR_BYPASS = "0b0";
parameter CH0_TX_GEAR_MODE = "0b0";
parameter CH0_TX_POST_SIGN = "0b0";
parameter CH0_TX_PRE_SIGN = "0b0";
parameter CH0_UC_MODE = "0b0";
parameter CH0_UDF_COMMA_A = "0b0000000000";
parameter CH0_UDF_COMMA_B = "0b0000000000";
parameter CH0_UDF_COMMA_MASK = "0b0000000000";
parameter CH0_WA_BYPASS = "0b0";
parameter CH0_WA_MODE = "0b0";
parameter CH1_AUTO_CALIB_EN = "0b0";
parameter CH1_AUTO_FACQ_EN = "0b0";
parameter CH1_BAND_THRESHOLD = "0b000000";
parameter CH1_CALIB_CK_MODE = "0b0";
parameter CH1_CC_MATCH_1 = "0b0000000000";
parameter CH1_CC_MATCH_2 = "0b0000000000";
parameter CH1_CC_MATCH_3 = "0b0000000000";
parameter CH1_CC_MATCH_4 = "0b0000000000";
parameter CH1_CDR_CNT4SEL = "0b00";
parameter CH1_CDR_CNT8SEL = "0b00";
parameter CH1_CTC_BYPASS = "0b0";
parameter CH1_DCOATDCFG = "0b00";
parameter CH1_DCOATDDLY = "0b00";
parameter CH1_DCOBYPSATD = "0b0";
parameter CH1_DCOCALDIV = "0b000";
parameter CH1_DCOCTLGI = "0b000";
parameter CH1_DCODISBDAVOID = "0b0";
parameter CH1_DCOFLTDAC = "0b00";
parameter CH1_DCOFTNRG = "0b000";
parameter CH1_DCOIOSTUNE = "0b000";
parameter CH1_DCOITUNE = "0b00";
parameter CH1_DCOITUNE4LSB = "0b000";
parameter CH1_DCOIUPDNX2 = "0b0";
parameter CH1_DCONUOFLSB = "0b000";
parameter CH1_DCOSCALEI = "0b00";
parameter CH1_DCOSTARTVAL = "0b000";
parameter CH1_DCOSTEP = "0b00";
parameter CH1_DEC_BYPASS = "0b0";
parameter CH1_ENABLE_CG_ALIGN = "0b0";
parameter CH1_ENC_BYPASS = "0b0";
parameter CH1_FF_RX_F_CLK_DIS = "0b0";
parameter CH1_FF_RX_H_CLK_EN = "0b0";
parameter CH1_FF_TX_F_CLK_DIS = "0b0";
parameter CH1_FF_TX_H_CLK_EN = "0b0";
parameter CH1_GE_AN_ENABLE = "0b0";
parameter CH1_INVERT_RX = "0b0";
parameter CH1_INVERT_TX = "0b0";
parameter CH1_LDR_CORE2TX_SEL = "0b0";
parameter CH1_LDR_RX2CORE_SEL = "0b0";
parameter CH1_LEQ_OFFSET_SEL = "0b0";
parameter CH1_LEQ_OFFSET_TRIM = "0b000";
parameter CH1_LSM_DISABLE = "0b0";
parameter CH1_MATCH_2_ENABLE = "0b0";
parameter CH1_MATCH_4_ENABLE = "0b0";
parameter CH1_MIN_IPG_CNT = "0b00";
parameter CH1_PCIE_EI_EN = "0b0";
parameter CH1_PCIE_MODE = "0b0";
parameter CH1_PCS_DET_TIME_SEL = "0b00";
parameter CH1_PDEN_SEL = "0b0";
parameter CH1_PRBS_ENABLE = "0b0";
parameter CH1_PRBS_LOCK = "0b0";
parameter CH1_PRBS_SELECTION = "0b0";
parameter CH1_RATE_MODE_RX = "0b0";
parameter CH1_RATE_MODE_TX = "0b0";
parameter CH1_RCV_DCC_EN = "0b0";
parameter CH1_REG_BAND_OFFSET = "0b0000";
parameter CH1_REG_BAND_SEL = "0b000000";
parameter CH1_REG_IDAC_EN = "0b0";
parameter CH1_REG_IDAC_SEL = "0b0000000000";
parameter CH1_REQ_EN = "0b0";
parameter CH1_REQ_LVL_SET = "0b00";
parameter CH1_RIO_MODE = "0b0";
parameter CH1_RLOS_SEL = "0b0";
parameter CH1_RPWDNB = "0b0";
parameter CH1_RTERM_RX = "0b00000";
parameter CH1_RTERM_TX = "0b00000";
parameter CH1_RXIN_CM = "0b00";
parameter CH1_RXTERM_CM = "0b00";
parameter CH1_RX_DCO_CK_DIV = "0b000";
parameter CH1_RX_DIV11_SEL = "0b0";
parameter CH1_RX_GEAR_BYPASS = "0b0";
parameter CH1_RX_GEAR_MODE = "0b0";
parameter CH1_RX_LOS_CEQ = "0b00";
parameter CH1_RX_LOS_EN = "0b0";
parameter CH1_RX_LOS_HYST_EN = "0b0";
parameter CH1_RX_LOS_LVL = "0b000";
parameter CH1_RX_RATE_SEL = "0b0000";
parameter CH1_RX_SB_BYPASS = "0b0";
parameter CH1_SB_BYPASS = "0b0";
parameter CH1_SEL_SD_RX_CLK = "0b0";
parameter CH1_TDRV_DAT_SEL = "0b00";
parameter CH1_TDRV_POST_EN = "0b0";
parameter CH1_TDRV_PRE_EN = "0b0";
parameter CH1_TDRV_SLICE0_CUR = "0b000";
parameter CH1_TDRV_SLICE0_SEL = "0b00";
parameter CH1_TDRV_SLICE1_CUR = "0b000";
parameter CH1_TDRV_SLICE1_SEL = "0b00";
parameter CH1_TDRV_SLICE2_CUR = "0b00";
parameter CH1_TDRV_SLICE2_SEL = "0b00";
parameter CH1_TDRV_SLICE3_CUR = "0b00";
parameter CH1_TDRV_SLICE3_SEL = "0b00";
parameter CH1_TDRV_SLICE4_CUR = "0b00";
parameter CH1_TDRV_SLICE4_SEL = "0b00";
parameter CH1_TDRV_SLICE5_CUR = "0b00";
parameter CH1_TDRV_SLICE5_SEL = "0b00";
parameter CH1_TPWDNB = "0b0";
parameter CH1_TX_CM_SEL = "0b00";
parameter CH1_TX_DIV11_SEL = "0b0";
parameter CH1_TX_GEAR_BYPASS = "0b0";
parameter CH1_TX_GEAR_MODE = "0b0";
parameter CH1_TX_POST_SIGN = "0b0";
parameter CH1_TX_PRE_SIGN = "0b0";
parameter CH1_UC_MODE = "0b0";
parameter CH1_UDF_COMMA_A = "0b0000000000";
parameter CH1_UDF_COMMA_B = "0b0000000000";
parameter CH1_UDF_COMMA_MASK = "0b0000000000";
parameter CH1_WA_BYPASS = "0b0";
parameter CH1_WA_MODE = "0b0";
parameter D_BITCLK_FROM_ND_EN = "0b0";
parameter D_BITCLK_LOCAL_EN = "0b0";
parameter D_BITCLK_ND_EN = "0b0";
parameter D_BUS8BIT_SEL = "0b0";
parameter D_CDR_LOL_SET = "0b00";
parameter D_CMUSETBIASI = "0b00";
parameter D_CMUSETI4CPP = "0b0000";
parameter D_CMUSETI4CPZ = "0b0000";
parameter D_CMUSETI4VCO = "0b00";
parameter D_CMUSETICP4P = "0b00";
parameter D_CMUSETICP4Z = "0b000";
parameter D_CMUSETINITVCT = "0b00";
parameter D_CMUSETISCL4VCO = "0b000";
parameter D_CMUSETP1GM = "0b000";
parameter D_CMUSETP2AGM = "0b000";
parameter D_CMUSETZGM = "0b000";
parameter D_DCO_CALIB_TIME_SEL = "0b00";
parameter D_HIGH_MARK = "0b0000";
parameter D_IB_PWDNB = "0b0";
parameter D_ISETLOS = "0b00000000";
parameter D_LOW_MARK = "0b0000";
parameter D_MACROPDB = "0b0";
parameter D_PD_ISET = "0b00";
parameter D_PLL_LOL_SET = "0b00";
parameter D_REFCK_MODE = "0b000";
parameter D_REQ_ISET = "0b000";
parameter D_RG_EN = "0b0";
parameter D_RG_SET = "0b00";
parameter D_SETICONST_AUX = "0b00";
parameter D_SETICONST_CH = "0b00";
parameter D_SETIRPOLY_AUX = "0b00";
parameter D_SETIRPOLY_CH = "0b00";
parameter D_SETPLLRC = "0b000000";
parameter D_SYNC_LOCAL_EN = "0b0";
parameter D_SYNC_ND_EN = "0b0";
parameter D_TXPLL_PWDNB = "0b0";
parameter D_TX_VCO_CK_DIV = "0b000";
parameter D_XGE_MODE = "0b0";
// These parameters don't do anything but are
// needed for compatibility with Diamond
parameter D_TX_MAX_RATE = "2.5";
parameter D_RX_MAX_RATE = "2.5";
parameter CH0_TXAMPLITUDE = "0d1300";
parameter CH1_TXAMPLITUDE = "0d1300";
parameter CH0_PROTOCOL = "8B10B";
parameter CH1_PROTOCOL = "8B10B";
parameter CH0_CDR_MAX_RATE = "2.5";
parameter CH1_CDR_MAX_RATE = "2.5";
parameter CH0_TXDEPRE = "DISABLED";
parameter CH1_TXDEPRE = "DISABLED";
parameter CH0_TXDEPOST = "DISABLED";
parameter CH1_TXDEPOST = "DISABLED";
endmodule
(* blackbox *)
module EXTREFB (
input REFCLKP, REFCLKN,
output REFCLKO
);
parameter REFCK_PWDNB = "0b0";
parameter REFCK_RTERM = "0b0";
parameter REFCK_DCBIAS_EN = "0b0";
endmodule
(* blackbox *)
module PCSCLKDIV (
input CLKI, RST, SEL2, SEL1, SEL0,
output CDIV1, CDIVX
);
parameter GSR = "DISABLED";
endmodule
// Note: this module is not marked keep as we want it swept away in synth (sim use only)
(* blackbox *)
module PUR (
input PUR
);
parameter RST_PULSE = 1;
endmodule
(* blackbox, keep *)
module GSR (
input GSR
);
endmodule
(* blackbox, keep *)
module SGSR (
input GSR, CLK
);
endmodule
(* blackbox *)
module PDPW16KD (
input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18,
input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
input BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0,
input ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18,
output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
);
parameter DATA_WIDTH_W = 36;
parameter DATA_WIDTH_R = 36;
parameter GSR = "ENABLED";
parameter REGMODE = "NOREG";
parameter RESETMODE = "SYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter CSDECODE_W = "0b000";
parameter CSDECODE_R = "0b000";
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_DATA = "STATIC";
parameter CLKWMUX = "CLKW";
parameter CLKRMUX = "CLKR";
endmodule
|
module mlvds_tx
(input c, input [4:0] mcb_addr,
output [2:0] mlvds_de, output [2:0] mlvds_di,
input [7:0] txd, input txdv, output tx_active,
input rx_active);
// for now, this assumes that we do not accept incoming packets while the
// previous outgoing one was being transmitted. revisit if that ever matters.
wire txdv_d1;
d1 txdv_d1_r(.c(c), .d(txdv), .q(txdv_d1));
wire txe = ~txdv & txdv_d1;
// ensure we have waited a bit after the RX packet completion before we TX
wire [7:0] rx_inactive_count;
localparam RX_INACTIVE_TIME = 8'h80;
r #(8) rx_inactive_count_r
(.c(c), .rst(rx_active), .en(rx_inactive_count != RX_INACTIVE_TIME),
.d(rx_inactive_count + 1'b1), .q(rx_inactive_count));
wire rx_released = rx_inactive_count == RX_INACTIVE_TIME;
localparam ST_IDLE = 4'd0;
localparam ST_WAIT_FOR_CLEAR = 4'd1;
localparam ST_WARMUP = 4'd2;
localparam ST_PREAMBLE = 4'd3;
localparam ST_LEN_HI = 4'd4;
localparam ST_LEN_LO = 4'd5;
localparam ST_ADDR = 4'd6;
localparam ST_FORMAT = 4'd7;
localparam ST_FRAME = 4'd8;
localparam ST_CRC_HI = 4'd9;
localparam ST_CRC_LO = 4'd10;
localparam ST_COOLDOWN = 4'd11;
localparam SW = 4, CW = 6;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [7:0] state_cnt;
r #(8) state_cnt_r(.c(c), .rst(next_state != state), .en(1'b1),
.d(state_cnt + 1'b1), .q(state_cnt));
wire fifo_rst = 1'b0;
wire [7:0] fifo_d, fifo_q;
wire fifo_dv = txdv & state == ST_IDLE;
wire fifo_rd;
wire fifo_empty;
wire [8:0] fifo_cnt;
fifo_512x8 fifo
(.c(c), .rst(fifo_rst), .d(txd), .dv(fifo_dv),
.q(fifo_q), .read(fifo_rd), .count(fifo_cnt), .empty(fifo_empty));
always @* begin
case (state)
ST_IDLE:
if (txe) ctrl = { ST_WAIT_FOR_CLEAR, 6'b000000 };
else ctrl = { ST_IDLE , 6'b000000 };
ST_WAIT_FOR_CLEAR:
if (rx_released) ctrl = { ST_WARMUP , 6'b000001 };
else ctrl = { ST_WAIT_FOR_CLEAR, 6'b000000 };
ST_WARMUP:
if (state_cnt == 8'h7f) ctrl = { ST_PREAMBLE , 6'b000001 };
else ctrl = { ST_WARMUP , 6'b000001 };
ST_PREAMBLE:
if (state_cnt == 8'hf) ctrl = { ST_LEN_HI , 6'b000011 };
else ctrl = { ST_PREAMBLE , 6'b000011 };
ST_LEN_HI:
if (state_cnt == 8'hf) ctrl = { ST_LEN_LO , 6'b010001 };
else ctrl = { ST_LEN_HI , 6'b010001 };
ST_LEN_LO:
if (state_cnt == 8'hf) ctrl = { ST_ADDR , 6'b010101 };
else ctrl = { ST_LEN_LO , 6'b010101 };
ST_ADDR:
if (state_cnt == 8'hf) ctrl = { ST_FRAME , 6'b010111 };
else ctrl = { ST_ADDR , 6'b010111 };
ST_FRAME:
if (state_cnt[3:0] == 4'hf & fifo_empty)
ctrl = { ST_CRC_HI , 6'b011011 };
else ctrl = { ST_FRAME , 6'b011011 };
ST_CRC_HI:
if (state_cnt == 8'hf) ctrl = { ST_CRC_LO , 6'b001101 };
else ctrl = { ST_CRC_HI , 6'b001101 };
ST_CRC_LO:
if (state_cnt == 8'hf) ctrl = { ST_COOLDOWN , 6'b001111 };
else ctrl = { ST_CRC_LO , 6'b001111 };
ST_COOLDOWN:
if (state_cnt == 8'hf) ctrl = { ST_IDLE , 6'b000001 };
else ctrl = { ST_COOLDOWN , 6'b000001 };
default: ctrl = { ST_IDLE , 6'b000000 };
endcase
end
wire [2:0] tx_byte_mux_sel = ctrl[3:1];
wire [15:0] crc;
wire [7:0] tx_byte;
gmux #(.DWIDTH(8), .SELWIDTH(3)) tx_byte_mux
(.d({crc[7:0], crc[15:8], fifo_q, 8'h0,
{3'b0, mcb_addr}, fifo_cnt[7:0]+2'h1, 8'h16, 8'h0}),
.sel(tx_byte_mux_sel),
.z(tx_byte));
wire crc_dv = ctrl[4] & state_cnt[3:0] == 4'h0; //[0];
crc_ccitt crc_ccitt_inst
(.clk(c), .rst(state == ST_IDLE), .d(tx_byte),
.dv(crc_dv), .crc(crc));
`ifdef SIM
reg [3:0] tx_squawk_nibble;
reg tx_squawk_active;
wire [3:0] tx_nibble = tx_squawk_active ? tx_squawk_nibble : (state_cnt[3] ? tx_byte[3:0] : tx_byte[7:4]);
`else
wire [3:0] tx_nibble = state_cnt[3] ? tx_byte[3:0] : tx_byte[7:4];
`endif
// generate the outgoing data clock from the state clock
wire mlvds_di_clk_out = (state_cnt[2:0] == 3'h2) |
(state_cnt[2:0] == 3'h3) |
(state_cnt[2:0] == 3'h4) |
(state_cnt[2:0] == 3'h5);
wire [1:0] mlvds_di_d_out = state_cnt[2] ? tx_nibble[1:0] : tx_nibble[3:2];
r #(3) mlvds_out_r
(.c(c), .rst(1'b0), .en(1'b1),
.d({mlvds_di_d_out, mlvds_di_clk_out}), .q(mlvds_di));
assign fifo_rd = state == ST_FRAME & state_cnt[3:0] == 4'he;
/*
// need to delay the outbound negative-edge bits for one cycle
wire [3:0] tx_nibble_d1;
d1 #(4) tx_nibble_d1_r(.c(c), .d(tx_nibble), .q(tx_nibble_d1));
wire [3:0] tx_nibble_dout = { tx_nibble[3:2], tx_nibble_d1[1:0] };
*/
wire mlvds_de_d1;
d1 mlvds_de_d1_r
(.c(c), .d(ctrl[0]), .q(mlvds_de_d1));
assign mlvds_de = {3{mlvds_de_d1}};
assign tx_active = ctrl[0];
/*
SB_IO #(.PIN_TYPE(6'b110001)) mlvds_tx_ddr_d [1:0]
(.PACKAGE_PIN(mlvds_di[2:1]),
.OUTPUT_CLK(clk_50),
.CLOCK_ENABLE(1'b1), .OUTPUT_ENABLE(1'b1),
.INPUT_CLK(1'b0), .LATCH_INPUT_VALUE(1'b0),
.D_OUT_0(tx_nibble_dout[3:2]),
.D_OUT_1(tx_nibble_dout[1:0]));
SB_IO #(.PIN_TYPE(6'b110001)) mlvds_tx_ddr_c
(.PACKAGE_PIN(mlvds_di[0]),
.OUTPUT_CLK(clk_50_90),
.CLOCK_ENABLE(1'b1), .OUTPUT_ENABLE(1'b1),
.INPUT_CLK(1'b0), .LATCH_INPUT_VALUE(1'b0),
.D_OUT_0(1'b1),
.D_OUT_1(1'b0));
*/
`ifdef SIM
integer squawk_delay, seed;
initial begin
seed = 0;
tx_squawk_active = 1'b0;
/*
forever begin
squawk_delay = $dist_uniform(seed, 1000, 2000);
#squawk_delay;
tx_squawk_nibble = $dist_uniform(seed, 0, 3);
tx_squawk_active = 1'b1;
#50;
tx_squawk_active = 1'b0;
end
*/
//$display($time, " waiting %d ns...", delay);
end
`endif
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// this is an unholy mess. it must be utterly rewritten at some point.
//////////////////////////////////////////////////////////////////////
/*
`ifdef SIM
reg mlvds_pll_reset;
initial begin
mlvds_pll_reset = 0;
#1000 mlvds_pll_reset = 1;
$display("%g releasing simulated MLVDS PLL reset", $time);
end
`else
wire mlvds_pll_reset = 1'b1;
`endif
///////////////// MLVDS PLL
wire mlvds_pll_clk, mlvds_pll_clk_90, mlvds_pll_lock;
mlvds_pll mlvds_pll_inst
(.REFCLK(mlvds_ro[0]), .RESET(mlvds_pll_reset), .LOCK(mlvds_pll_lock),
.PLLOUTGLOBALA(mlvds_pll_clk), .PLLOUTGLOBALB(mlvds_pll_clk_90));
*/
/*
wire mlvds_clk, mlvds_clk_90;
//`ifdef SIM
// add delays to simulate what the real on-chip routing does
// assign #2.25 mlvds_clk = mlvds_pll_clk;
// assign #2.25 mlvds_clk_90 = mlvds_pll_clk_90;
//`else
assign mlvds_clk = mlvds_pll_clk;
assign mlvds_clk_90 = mlvds_pll_clk_90;
//`endif
wire c = mlvds_clk; // save typing
wire [1:0] mlvds_ro_dibit;
sync #(.W(2), .S(3)) ddr_data_sync
(.in({mlvds_ro_posedge[1], mlvds_ro_negedge[1]}),
.out(mlvds_ro_dibit), .clk(c));
wire mlvds_ro_cs;
sync #(.S(3)) ddr_cs_sync
(.in(mlvds_ro_posedge[0]), .out(mlvds_ro_cs), .clk(c));
wire mlvds_ro_cs_d1; // need this d1 to catch the last rx word
r mlvds_ro_cs_d1_r(.c(c), .rst(1'b0), .en(1'b1),
.d(mlvds_ro_cs), .q(mlvds_ro_cs_d1));
wire mlvds_ro_cs_posedge = mlvds_ro_cs & ~mlvds_ro_cs_d1;
wire [2:0] dibit_cnt;
wire dibit_cnt_rst;
r #(3) dibit_cnt_r(.c(c), .rst(dibit_cnt_rst), .en(1'b1),
.d(dibit_cnt+1'b1), .q(dibit_cnt));
wire [7:0] rxd;
r #(8) rxd_r
(.c(c), .rst(1'b0), .en(1'b1),
.d({rxd[5:0], mlvds_ro_dibit}), .q(rxd));
wire rxdv = dibit_cnt[1:0] == 2'b11 & mlvds_ro_cs_d1;
localparam ST_IDLE = 4'd0;
localparam ST_RX_LEN_HI = 4'd1;
localparam ST_RX_LEN_LO = 4'd2;
localparam ST_RX_FRAME = 4'd3;
localparam ST_RX_CSUM_HI = 4'd4;
localparam ST_RX_CSUM_LO = 4'd5;
localparam ST_RX_CHECK_PKT = 4'd6;
localparam ST_TX_
localparam ST_FRAME = 4'd2;
localparam ST_CHECK_PKT = 4'd3;
localparam ST_DRAIN_BUF = 4'd4;
localparam ST_CRC_LO = 4'd5; // save the low CRC byte after rxdv falls
localparam ST_ATX_TXWARM = 4'd6; // warm up the transmitter
localparam ST_ATX_PRE = 4'd7; // async tx preamble
localparam ST_ATX_DRAIN = 4'd8; // async tx frame format
localparam ST_ATX_TXCOOL = 4'd9; // async tx leave transmitter on one more byte
localparam SW = 4, CW = 6;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire idle = state == ST_IDLE; // save typing...
wire addr_match;
r addr_match_r
(.c(c), .rst(idle), .d(1'b1), .q(addr_match),
.en(state == ST_ADDR &
rxdv &
((rxd[3:0] == mcb_addr) | (rxd[3:0] == 4'hf)))); // unicast or broadcast
wire reject_pkt;
wire rxfifo_almost_empty;
always @* begin
case (state)
ST_IDLE:
if (rxdv & rxd == 8'h57) ctrl = { ST_ADDR , 6'b000000 };
else if (|atxfifo_count) ctrl = { ST_ATX_TXWARM , 6'b001010 };
else ctrl = { ST_IDLE , 6'b000000 };
ST_ADDR:
if (rxdv) ctrl = { ST_FRAME , 6'b000000 };
else ctrl = { ST_ADDR , 6'b000000 };
ST_FRAME:
if (~mlvds_ro_cs) ctrl = { ST_CHECK_PKT , 6'b000000 };
else ctrl = { ST_FRAME , 6'b000000 };
ST_CHECK_PKT:
if (reject_pkt) ctrl = { ST_IDLE , 6'b000000 };
else ctrl = { ST_DRAIN_BUF , 6'b000001 };
ST_DRAIN_BUF:
if (fifo_almost_empty) ctrl = { ST_CRC_LO , 6'b000001 };
else ctrl = { ST_DRAIN_BUF , 6'b000001 };
ST_CRC_LO: ctrl = { ST_IDLE , 6'b000000 };
ST_ATX_TXWARM:
if (dibit_cnt[1:0] == 2'b10) ctrl = { ST_ATX_PRE , 6'b101110 };
else ctrl = { ST_ATX_TXWARM , 6'b001100 };
ST_ATX_PRE:
if (dibit_cnt[1:0] == 2'b11) ctrl = { ST_ATX_DRAIN , 6'b011100 };
else ctrl = { ST_ATX_PRE , 6'b001100 };
ST_ATX_DRAIN:
if (dibit_cnt[1:0] == 2'b11)
if (atxfifo_count == 9'b1) ctrl = { ST_ATX_TXCOOL , 6'b111110 };
else ctrl = { ST_ATX_DRAIN , 6'b011100 };
else ctrl = { ST_ATX_DRAIN , 6'b001100 };
ST_ATX_TXCOOL:
if (dibit_cnt[2:0] == 3'd7) ctrl = { ST_IDLE , 6'b000100 };
else ctrl = { ST_ATX_TXCOOL , 6'b001100 };
default: ctrl = { ST_IDLE , 6'b000000 };
endcase
end
wire rxfifo_read = ctrl[0];
assign dibit_cnt_rst = ((state == ST_IDLE) & mlvds_ro_cs_posedge) | ctrl[1];
//wire mlvds_di_d;
//assign mlvds_di[2] = ((state == ST_ATX_PRE) | (state == ST_ATX_DRAIN)) ?
// mlvds_di_d : 2'b0;
assign mlvds_de[2:1] = {ctrl[2], ctrl[2]};
// initialize the CRC calculator to start having already received a 0 (format)
wire [15:0] calc_crc;
crc_ccitt crc_ccitt_inst
(.clk(c), .rst(idle), .d(rxd), .dv(rxdv & ~idle), .crc(calc_crc));
wire [15:0] calc_crc_d1;
r #(16) calc_crc_d1_r
(.c(c), .rst(1'b0), .en(rxdv), .d(calc_crc), .q(calc_crc_d1));
wire [7:0] rxd_d1;
r #(8) rxd_d1_r(.c(c), .rst(1'b0), .en(rxdv), .d(rxd), .q(rxd_d1));
wire crc_match = state == ST_FRAME & { rxd_d1, rxd } == calc_crc_d1;
wire crc_match_d1;
r crc_match_d1_r(.c(c), .rst(1'b0), .en(1'b1), .d(crc_match), .q(crc_match_d1));
assign reject_pkt = ~addr_match | ~crc_match_d1;
wire [8:0] rxfifo_count;
fifo_512x8 rxfifo
(.c(c), .r(idle), .d(rxd), .dv(rxdv & state == ST_FRAME),
.q(mlvds_rxd), .read(rxfifo_read), .count(rxfifo_count));
assign mlvds_rxdv = state == ST_DRAIN_BUF;
assign fifo_almost_empty = rxfifo_count == 9'd2;
////////////////////////////////////////////////////////////////////////
// TX stuff
// atxfifo = async tx fifo
wire [8:0] atxfifo_count;
wire [7:0] atxfifo_q;
wire atxfifo_read = ctrl[4];
wire atxfifo_rst = 1'b0;
fifo_512x8 atxfifo
(.c(c), .r(atxfifo_rst), .d(async_txd), .dv(async_txdv),
.q(atxfifo_q), .read(atxfifo_read), .count(atxfifo_count));
wire [3:0] tx_octet_mux_state = (state - 4'd6);
wire [7:0] next_tx_octet;
gmux #(.DWIDTH(8), .SELWIDTH(2)) tx_octet_mux
(.d({8'h0, atxfifo_q, atxfifo_q, 8'h57}),
.sel(state >= ST_ATX_TXWARM ? tx_octet_mux_state[1:0] : 2'b11),
.z(next_tx_octet));
wire [9:0] tx_shift;
r #(10) tx_shift_r
(.c(mlvds_clk), .rst(1'b0), .en(1'b1),
.d(((dibit_cnt[1:0] == 2'b11) | ctrl[5]) ?
{tx_shift[7:6], next_tx_octet} :
{tx_shift[7:0], 2'b0}),
.q(tx_shift));
wire etx_p = state == ST_ATX_TXCOOL & dibit_cnt >= 3'd4;
wire etx_n = state == ST_ATX_TXCOOL & dibit_cnt >= 3'd5;
SB_IO #(.PIN_TYPE(6'b110001)) mlvds_tx_ddr [1:0]
(.PACKAGE_PIN(mlvds_di[2:1]),
.OUTPUT_CLK(mlvds_clk),
.CLOCK_ENABLE(1'b1), .OUTPUT_ENABLE(1'b1),
.INPUT_CLK(1'b0), .LATCH_INPUT_VALUE(1'b0),
.D_OUT_0({tx_shift[7], ctrl[3] & ~etx_p}),
.D_OUT_1({tx_shift[8], ctrl[2] & ~etx_n}));
*/
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:41 EST 2016
//
// Method conflict info:
// Method: output_arbs_0_select
// Conflict-free: output_arbs_0_select,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_0_next
//
// Method: output_arbs_0_next
// Conflict-free: output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_0_select
// Conflicts: output_arbs_0_next
//
// Method: output_arbs_1_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_1_next
//
// Method: output_arbs_1_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_1_select
// Conflicts: output_arbs_1_next
//
// Method: output_arbs_2_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_2_next
//
// Method: output_arbs_2_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_2_select
// Conflicts: output_arbs_2_next
//
// Method: output_arbs_3_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced before: output_arbs_3_next
//
// Method: output_arbs_3_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_4_select,
// output_arbs_4_next
// Sequenced after: output_arbs_3_select
// Conflicts: output_arbs_3_next
//
// Method: output_arbs_4_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select
// Sequenced before: output_arbs_4_next
//
// Method: output_arbs_4_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next
// Sequenced after: output_arbs_4_select
// Conflicts: output_arbs_4_next
//
//
// Ports:
// Name I/O size props
// output_arbs_0_select O 5
// output_arbs_1_select O 5
// output_arbs_2_select O 5
// output_arbs_3_select O 5
// output_arbs_4_select O 5
// CLK I 1 clock
// RST_N I 1 reset
// output_arbs_0_select_requests I 5
// output_arbs_1_select_requests I 5
// output_arbs_2_select_requests I 5
// output_arbs_3_select_requests I 5
// output_arbs_4_select_requests I 5
// EN_output_arbs_0_next I 1
// EN_output_arbs_1_next I 1
// EN_output_arbs_2_next I 1
// EN_output_arbs_3_next I 1
// EN_output_arbs_4_next I 1
//
// Combinational paths from inputs to outputs:
// output_arbs_0_select_requests -> output_arbs_0_select
// output_arbs_1_select_requests -> output_arbs_1_select
// output_arbs_2_select_requests -> output_arbs_2_select
// output_arbs_3_select_requests -> output_arbs_3_select
// output_arbs_4_select_requests -> output_arbs_4_select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterOutputArbitersRoundRobin(CLK,
RST_N,
output_arbs_0_select_requests,
output_arbs_0_select,
EN_output_arbs_0_next,
output_arbs_1_select_requests,
output_arbs_1_select,
EN_output_arbs_1_next,
output_arbs_2_select_requests,
output_arbs_2_select,
EN_output_arbs_2_next,
output_arbs_3_select_requests,
output_arbs_3_select,
EN_output_arbs_3_next,
output_arbs_4_select_requests,
output_arbs_4_select,
EN_output_arbs_4_next);
input CLK;
input RST_N;
// value method output_arbs_0_select
input [4 : 0] output_arbs_0_select_requests;
output [4 : 0] output_arbs_0_select;
// action method output_arbs_0_next
input EN_output_arbs_0_next;
// value method output_arbs_1_select
input [4 : 0] output_arbs_1_select_requests;
output [4 : 0] output_arbs_1_select;
// action method output_arbs_1_next
input EN_output_arbs_1_next;
// value method output_arbs_2_select
input [4 : 0] output_arbs_2_select_requests;
output [4 : 0] output_arbs_2_select;
// action method output_arbs_2_next
input EN_output_arbs_2_next;
// value method output_arbs_3_select
input [4 : 0] output_arbs_3_select_requests;
output [4 : 0] output_arbs_3_select;
// action method output_arbs_3_next
input EN_output_arbs_3_next;
// value method output_arbs_4_select
input [4 : 0] output_arbs_4_select_requests;
output [4 : 0] output_arbs_4_select;
// action method output_arbs_4_next
input EN_output_arbs_4_next;
// signals for module outputs
wire [4 : 0] output_arbs_0_select,
output_arbs_1_select,
output_arbs_2_select,
output_arbs_3_select,
output_arbs_4_select;
// register oas_0_token
reg [4 : 0] oas_0_token;
wire [4 : 0] oas_0_token$D_IN;
wire oas_0_token$EN;
// register oas_1_token
reg [4 : 0] oas_1_token;
wire [4 : 0] oas_1_token$D_IN;
wire oas_1_token$EN;
// register oas_2_token
reg [4 : 0] oas_2_token;
wire [4 : 0] oas_2_token$D_IN;
wire oas_2_token$EN;
// register oas_3_token
reg [4 : 0] oas_3_token;
wire [4 : 0] oas_3_token$D_IN;
wire oas_3_token$EN;
// register oas_4_token
reg [4 : 0] oas_4_token;
wire [4 : 0] oas_4_token$D_IN;
wire oas_4_token$EN;
// remaining internal signals
wire [1 : 0] ab__h12572,
ab__h12587,
ab__h12602,
ab__h12617,
ab__h12632,
ab__h14013,
ab__h14460,
ab__h14853,
ab__h15197,
ab__h15492,
ab__h19612,
ab__h19627,
ab__h19642,
ab__h19657,
ab__h19672,
ab__h21053,
ab__h21500,
ab__h21893,
ab__h22237,
ab__h22532,
ab__h26652,
ab__h26667,
ab__h26682,
ab__h26697,
ab__h26712,
ab__h28093,
ab__h28540,
ab__h28933,
ab__h29277,
ab__h29572,
ab__h33692,
ab__h33707,
ab__h33722,
ab__h33737,
ab__h33752,
ab__h35133,
ab__h35580,
ab__h35973,
ab__h36317,
ab__h36612,
ab__h5532,
ab__h5547,
ab__h5562,
ab__h5577,
ab__h5592,
ab__h6973,
ab__h7420,
ab__h7813,
ab__h8157,
ab__h8452;
wire NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328,
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276,
NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267,
NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278,
NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206,
NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208,
NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346,
NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337,
ab_BIT_0___h13184,
ab_BIT_0___h13291,
ab_BIT_0___h13398,
ab_BIT_0___h13505,
ab_BIT_0___h14084,
ab_BIT_0___h14220,
ab_BIT_0___h14613,
ab_BIT_0___h14957,
ab_BIT_0___h15252,
ab_BIT_0___h20224,
ab_BIT_0___h20331,
ab_BIT_0___h20438,
ab_BIT_0___h20545,
ab_BIT_0___h21124,
ab_BIT_0___h21260,
ab_BIT_0___h21653,
ab_BIT_0___h21997,
ab_BIT_0___h22292,
ab_BIT_0___h27264,
ab_BIT_0___h27371,
ab_BIT_0___h27478,
ab_BIT_0___h27585,
ab_BIT_0___h28164,
ab_BIT_0___h28300,
ab_BIT_0___h28693,
ab_BIT_0___h29037,
ab_BIT_0___h29332,
ab_BIT_0___h34304,
ab_BIT_0___h34411,
ab_BIT_0___h34518,
ab_BIT_0___h34625,
ab_BIT_0___h35204,
ab_BIT_0___h35340,
ab_BIT_0___h35733,
ab_BIT_0___h36077,
ab_BIT_0___h36372,
ab_BIT_0___h6144,
ab_BIT_0___h6251,
ab_BIT_0___h6358,
ab_BIT_0___h6465,
ab_BIT_0___h7044,
ab_BIT_0___h7180,
ab_BIT_0___h7573,
ab_BIT_0___h7917,
ab_BIT_0___h8212,
oas_0_token_BIT_0___h6142,
oas_0_token_BIT_1___h6249,
oas_0_token_BIT_2___h6356,
oas_0_token_BIT_3___h6463,
oas_0_token_BIT_4___h6570,
oas_1_token_BIT_0___h13182,
oas_1_token_BIT_1___h13289,
oas_1_token_BIT_2___h13396,
oas_1_token_BIT_3___h13503,
oas_1_token_BIT_4___h13610,
oas_2_token_BIT_0___h20222,
oas_2_token_BIT_1___h20329,
oas_2_token_BIT_2___h20436,
oas_2_token_BIT_3___h20543,
oas_2_token_BIT_4___h20650,
oas_3_token_BIT_0___h27262,
oas_3_token_BIT_1___h27369,
oas_3_token_BIT_2___h27476,
oas_3_token_BIT_3___h27583,
oas_3_token_BIT_4___h27690,
oas_4_token_BIT_0___h34302,
oas_4_token_BIT_1___h34409,
oas_4_token_BIT_2___h34516,
oas_4_token_BIT_3___h34623,
oas_4_token_BIT_4___h34730;
// value method output_arbs_0_select
assign output_arbs_0_select =
{ ab__h5532[1] || ab__h6973[1],
!ab__h5532[1] && !ab__h6973[1] &&
(ab__h5547[1] || ab__h7420[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h5532[1] && !ab__h6973[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// value method output_arbs_1_select
assign output_arbs_1_select =
{ ab__h12572[1] || ab__h14013[1],
!ab__h12572[1] && !ab__h14013[1] &&
(ab__h12587[1] || ab__h14460[1]),
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118,
!ab__h12572[1] && !ab__h14013[1] &&
NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138 } ;
// value method output_arbs_2_select
assign output_arbs_2_select =
{ ab__h19612[1] || ab__h21053[1],
!ab__h19612[1] && !ab__h21053[1] &&
(ab__h19627[1] || ab__h21500[1]),
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188,
!ab__h19612[1] && !ab__h21053[1] &&
NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208 } ;
// value method output_arbs_3_select
assign output_arbs_3_select =
{ ab__h26652[1] || ab__h28093[1],
!ab__h26652[1] && !ab__h28093[1] &&
(ab__h26667[1] || ab__h28540[1]),
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258,
!ab__h26652[1] && !ab__h28093[1] &&
NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278 } ;
// value method output_arbs_4_select
assign output_arbs_4_select =
{ ab__h33692[1] || ab__h35133[1],
!ab__h33692[1] && !ab__h35133[1] &&
(ab__h33707[1] || ab__h35580[1]),
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328,
!ab__h33692[1] && !ab__h35133[1] &&
NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337,
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348 } ;
// register oas_0_token
assign oas_0_token$D_IN = { oas_0_token[0], oas_0_token[4:1] } ;
assign oas_0_token$EN = EN_output_arbs_0_next ;
// register oas_1_token
assign oas_1_token$D_IN = { oas_1_token[0], oas_1_token[4:1] } ;
assign oas_1_token$EN = EN_output_arbs_1_next ;
// register oas_2_token
assign oas_2_token$D_IN = { oas_2_token[0], oas_2_token[4:1] } ;
assign oas_2_token$EN = EN_output_arbs_2_next ;
// register oas_3_token
assign oas_3_token$D_IN = { oas_3_token[0], oas_3_token[4:1] } ;
assign oas_3_token$EN = EN_output_arbs_3_next ;
// register oas_4_token
assign oas_4_token$D_IN = { oas_4_token[0], oas_4_token[4:1] } ;
assign oas_4_token$EN = EN_output_arbs_4_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_45(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_0_select_requests[0]),
.gen_grant_carry_p(oas_0_token_BIT_0___h6142),
.gen_grant_carry(ab__h5592));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h6144),
.gen_grant_carry_r(output_arbs_0_select_requests[1]),
.gen_grant_carry_p(oas_0_token_BIT_1___h6249),
.gen_grant_carry(ab__h5577));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h6251),
.gen_grant_carry_r(output_arbs_0_select_requests[2]),
.gen_grant_carry_p(oas_0_token_BIT_2___h6356),
.gen_grant_carry(ab__h5562));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h6358),
.gen_grant_carry_r(output_arbs_0_select_requests[3]),
.gen_grant_carry_p(oas_0_token_BIT_3___h6463),
.gen_grant_carry(ab__h5547));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h6465),
.gen_grant_carry_r(output_arbs_0_select_requests[4]),
.gen_grant_carry_p(oas_0_token_BIT_4___h6570),
.gen_grant_carry(ab__h5532));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h7044),
.gen_grant_carry_r(output_arbs_0_select_requests[0]),
.gen_grant_carry_p(oas_0_token_BIT_0___h6142),
.gen_grant_carry(ab__h8452));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h8212),
.gen_grant_carry_r(output_arbs_0_select_requests[1]),
.gen_grant_carry_p(oas_0_token_BIT_1___h6249),
.gen_grant_carry(ab__h8157));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h7917),
.gen_grant_carry_r(output_arbs_0_select_requests[2]),
.gen_grant_carry_p(oas_0_token_BIT_2___h6356),
.gen_grant_carry(ab__h7813));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h7573),
.gen_grant_carry_r(output_arbs_0_select_requests[3]),
.gen_grant_carry_p(oas_0_token_BIT_3___h6463),
.gen_grant_carry(ab__h7420));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h7180),
.gen_grant_carry_r(output_arbs_0_select_requests[4]),
.gen_grant_carry_p(oas_0_token_BIT_4___h6570),
.gen_grant_carry(ab__h6973));
module_gen_grant_carry instance_gen_grant_carry_46(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_1_select_requests[0]),
.gen_grant_carry_p(oas_1_token_BIT_0___h13182),
.gen_grant_carry(ab__h12632));
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(ab_BIT_0___h13184),
.gen_grant_carry_r(output_arbs_1_select_requests[1]),
.gen_grant_carry_p(oas_1_token_BIT_1___h13289),
.gen_grant_carry(ab__h12617));
module_gen_grant_carry instance_gen_grant_carry_10(.gen_grant_carry_c(ab_BIT_0___h13291),
.gen_grant_carry_r(output_arbs_1_select_requests[2]),
.gen_grant_carry_p(oas_1_token_BIT_2___h13396),
.gen_grant_carry(ab__h12602));
module_gen_grant_carry instance_gen_grant_carry_11(.gen_grant_carry_c(ab_BIT_0___h13398),
.gen_grant_carry_r(output_arbs_1_select_requests[3]),
.gen_grant_carry_p(oas_1_token_BIT_3___h13503),
.gen_grant_carry(ab__h12587));
module_gen_grant_carry instance_gen_grant_carry_12(.gen_grant_carry_c(ab_BIT_0___h13505),
.gen_grant_carry_r(output_arbs_1_select_requests[4]),
.gen_grant_carry_p(oas_1_token_BIT_4___h13610),
.gen_grant_carry(ab__h12572));
module_gen_grant_carry instance_gen_grant_carry_13(.gen_grant_carry_c(ab_BIT_0___h14084),
.gen_grant_carry_r(output_arbs_1_select_requests[0]),
.gen_grant_carry_p(oas_1_token_BIT_0___h13182),
.gen_grant_carry(ab__h15492));
module_gen_grant_carry instance_gen_grant_carry_14(.gen_grant_carry_c(ab_BIT_0___h15252),
.gen_grant_carry_r(output_arbs_1_select_requests[1]),
.gen_grant_carry_p(oas_1_token_BIT_1___h13289),
.gen_grant_carry(ab__h15197));
module_gen_grant_carry instance_gen_grant_carry_15(.gen_grant_carry_c(ab_BIT_0___h14957),
.gen_grant_carry_r(output_arbs_1_select_requests[2]),
.gen_grant_carry_p(oas_1_token_BIT_2___h13396),
.gen_grant_carry(ab__h14853));
module_gen_grant_carry instance_gen_grant_carry_16(.gen_grant_carry_c(ab_BIT_0___h14613),
.gen_grant_carry_r(output_arbs_1_select_requests[3]),
.gen_grant_carry_p(oas_1_token_BIT_3___h13503),
.gen_grant_carry(ab__h14460));
module_gen_grant_carry instance_gen_grant_carry_17(.gen_grant_carry_c(ab_BIT_0___h14220),
.gen_grant_carry_r(output_arbs_1_select_requests[4]),
.gen_grant_carry_p(oas_1_token_BIT_4___h13610),
.gen_grant_carry(ab__h14013));
module_gen_grant_carry instance_gen_grant_carry_47(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_2_select_requests[0]),
.gen_grant_carry_p(oas_2_token_BIT_0___h20222),
.gen_grant_carry(ab__h19672));
module_gen_grant_carry instance_gen_grant_carry_18(.gen_grant_carry_c(ab_BIT_0___h20224),
.gen_grant_carry_r(output_arbs_2_select_requests[1]),
.gen_grant_carry_p(oas_2_token_BIT_1___h20329),
.gen_grant_carry(ab__h19657));
module_gen_grant_carry instance_gen_grant_carry_19(.gen_grant_carry_c(ab_BIT_0___h20331),
.gen_grant_carry_r(output_arbs_2_select_requests[2]),
.gen_grant_carry_p(oas_2_token_BIT_2___h20436),
.gen_grant_carry(ab__h19642));
module_gen_grant_carry instance_gen_grant_carry_20(.gen_grant_carry_c(ab_BIT_0___h20438),
.gen_grant_carry_r(output_arbs_2_select_requests[3]),
.gen_grant_carry_p(oas_2_token_BIT_3___h20543),
.gen_grant_carry(ab__h19627));
module_gen_grant_carry instance_gen_grant_carry_21(.gen_grant_carry_c(ab_BIT_0___h20545),
.gen_grant_carry_r(output_arbs_2_select_requests[4]),
.gen_grant_carry_p(oas_2_token_BIT_4___h20650),
.gen_grant_carry(ab__h19612));
module_gen_grant_carry instance_gen_grant_carry_22(.gen_grant_carry_c(ab_BIT_0___h21124),
.gen_grant_carry_r(output_arbs_2_select_requests[0]),
.gen_grant_carry_p(oas_2_token_BIT_0___h20222),
.gen_grant_carry(ab__h22532));
module_gen_grant_carry instance_gen_grant_carry_23(.gen_grant_carry_c(ab_BIT_0___h22292),
.gen_grant_carry_r(output_arbs_2_select_requests[1]),
.gen_grant_carry_p(oas_2_token_BIT_1___h20329),
.gen_grant_carry(ab__h22237));
module_gen_grant_carry instance_gen_grant_carry_24(.gen_grant_carry_c(ab_BIT_0___h21997),
.gen_grant_carry_r(output_arbs_2_select_requests[2]),
.gen_grant_carry_p(oas_2_token_BIT_2___h20436),
.gen_grant_carry(ab__h21893));
module_gen_grant_carry instance_gen_grant_carry_25(.gen_grant_carry_c(ab_BIT_0___h21653),
.gen_grant_carry_r(output_arbs_2_select_requests[3]),
.gen_grant_carry_p(oas_2_token_BIT_3___h20543),
.gen_grant_carry(ab__h21500));
module_gen_grant_carry instance_gen_grant_carry_26(.gen_grant_carry_c(ab_BIT_0___h21260),
.gen_grant_carry_r(output_arbs_2_select_requests[4]),
.gen_grant_carry_p(oas_2_token_BIT_4___h20650),
.gen_grant_carry(ab__h21053));
module_gen_grant_carry instance_gen_grant_carry_48(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_3_select_requests[0]),
.gen_grant_carry_p(oas_3_token_BIT_0___h27262),
.gen_grant_carry(ab__h26712));
module_gen_grant_carry instance_gen_grant_carry_27(.gen_grant_carry_c(ab_BIT_0___h27264),
.gen_grant_carry_r(output_arbs_3_select_requests[1]),
.gen_grant_carry_p(oas_3_token_BIT_1___h27369),
.gen_grant_carry(ab__h26697));
module_gen_grant_carry instance_gen_grant_carry_28(.gen_grant_carry_c(ab_BIT_0___h27371),
.gen_grant_carry_r(output_arbs_3_select_requests[2]),
.gen_grant_carry_p(oas_3_token_BIT_2___h27476),
.gen_grant_carry(ab__h26682));
module_gen_grant_carry instance_gen_grant_carry_29(.gen_grant_carry_c(ab_BIT_0___h27478),
.gen_grant_carry_r(output_arbs_3_select_requests[3]),
.gen_grant_carry_p(oas_3_token_BIT_3___h27583),
.gen_grant_carry(ab__h26667));
module_gen_grant_carry instance_gen_grant_carry_30(.gen_grant_carry_c(ab_BIT_0___h27585),
.gen_grant_carry_r(output_arbs_3_select_requests[4]),
.gen_grant_carry_p(oas_3_token_BIT_4___h27690),
.gen_grant_carry(ab__h26652));
module_gen_grant_carry instance_gen_grant_carry_31(.gen_grant_carry_c(ab_BIT_0___h28164),
.gen_grant_carry_r(output_arbs_3_select_requests[0]),
.gen_grant_carry_p(oas_3_token_BIT_0___h27262),
.gen_grant_carry(ab__h29572));
module_gen_grant_carry instance_gen_grant_carry_32(.gen_grant_carry_c(ab_BIT_0___h29332),
.gen_grant_carry_r(output_arbs_3_select_requests[1]),
.gen_grant_carry_p(oas_3_token_BIT_1___h27369),
.gen_grant_carry(ab__h29277));
module_gen_grant_carry instance_gen_grant_carry_33(.gen_grant_carry_c(ab_BIT_0___h29037),
.gen_grant_carry_r(output_arbs_3_select_requests[2]),
.gen_grant_carry_p(oas_3_token_BIT_2___h27476),
.gen_grant_carry(ab__h28933));
module_gen_grant_carry instance_gen_grant_carry_34(.gen_grant_carry_c(ab_BIT_0___h28693),
.gen_grant_carry_r(output_arbs_3_select_requests[3]),
.gen_grant_carry_p(oas_3_token_BIT_3___h27583),
.gen_grant_carry(ab__h28540));
module_gen_grant_carry instance_gen_grant_carry_35(.gen_grant_carry_c(ab_BIT_0___h28300),
.gen_grant_carry_r(output_arbs_3_select_requests[4]),
.gen_grant_carry_p(oas_3_token_BIT_4___h27690),
.gen_grant_carry(ab__h28093));
module_gen_grant_carry instance_gen_grant_carry_49(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(output_arbs_4_select_requests[0]),
.gen_grant_carry_p(oas_4_token_BIT_0___h34302),
.gen_grant_carry(ab__h33752));
module_gen_grant_carry instance_gen_grant_carry_36(.gen_grant_carry_c(ab_BIT_0___h34304),
.gen_grant_carry_r(output_arbs_4_select_requests[1]),
.gen_grant_carry_p(oas_4_token_BIT_1___h34409),
.gen_grant_carry(ab__h33737));
module_gen_grant_carry instance_gen_grant_carry_37(.gen_grant_carry_c(ab_BIT_0___h34411),
.gen_grant_carry_r(output_arbs_4_select_requests[2]),
.gen_grant_carry_p(oas_4_token_BIT_2___h34516),
.gen_grant_carry(ab__h33722));
module_gen_grant_carry instance_gen_grant_carry_38(.gen_grant_carry_c(ab_BIT_0___h34518),
.gen_grant_carry_r(output_arbs_4_select_requests[3]),
.gen_grant_carry_p(oas_4_token_BIT_3___h34623),
.gen_grant_carry(ab__h33707));
module_gen_grant_carry instance_gen_grant_carry_39(.gen_grant_carry_c(ab_BIT_0___h34625),
.gen_grant_carry_r(output_arbs_4_select_requests[4]),
.gen_grant_carry_p(oas_4_token_BIT_4___h34730),
.gen_grant_carry(ab__h33692));
module_gen_grant_carry instance_gen_grant_carry_40(.gen_grant_carry_c(ab_BIT_0___h35204),
.gen_grant_carry_r(output_arbs_4_select_requests[0]),
.gen_grant_carry_p(oas_4_token_BIT_0___h34302),
.gen_grant_carry(ab__h36612));
module_gen_grant_carry instance_gen_grant_carry_41(.gen_grant_carry_c(ab_BIT_0___h36372),
.gen_grant_carry_r(output_arbs_4_select_requests[1]),
.gen_grant_carry_p(oas_4_token_BIT_1___h34409),
.gen_grant_carry(ab__h36317));
module_gen_grant_carry instance_gen_grant_carry_42(.gen_grant_carry_c(ab_BIT_0___h36077),
.gen_grant_carry_r(output_arbs_4_select_requests[2]),
.gen_grant_carry_p(oas_4_token_BIT_2___h34516),
.gen_grant_carry(ab__h35973));
module_gen_grant_carry instance_gen_grant_carry_43(.gen_grant_carry_c(ab_BIT_0___h35733),
.gen_grant_carry_r(output_arbs_4_select_requests[3]),
.gen_grant_carry_p(oas_4_token_BIT_3___h34623),
.gen_grant_carry(ab__h35580));
module_gen_grant_carry instance_gen_grant_carry_44(.gen_grant_carry_c(ab_BIT_0___h35340),
.gen_grant_carry_r(output_arbs_4_select_requests[4]),
.gen_grant_carry_p(oas_4_token_BIT_4___h34730),
.gen_grant_carry(ab__h35133));
assign NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328 =
!ab__h33692[1] && !ab__h35133[1] && !ab__h33707[1] &&
!ab__h35580[1] &&
(ab__h33722[1] || ab__h35973[1]) ;
assign NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348 =
!ab__h33692[1] && !ab__h35133[1] && !ab__h33707[1] &&
!ab__h35580[1] &&
NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346 ;
assign NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118 =
!ab__h12572[1] && !ab__h14013[1] && !ab__h12587[1] &&
!ab__h14460[1] &&
(ab__h12602[1] || ab__h14853[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138 =
!ab__h12572[1] && !ab__h14013[1] && !ab__h12587[1] &&
!ab__h14460[1] &&
NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136 ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h5532[1] && !ab__h6973[1] && !ab__h5547[1] &&
!ab__h7420[1] &&
(ab__h5562[1] || ab__h7813[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h5532[1] && !ab__h6973[1] && !ab__h5547[1] &&
!ab__h7420[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276 =
!ab__h26682[1] && !ab__h28933[1] && !ab__h26697[1] &&
!ab__h29277[1] &&
(ab__h26712[1] || ab__h29572[1]) ;
assign NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267 =
!ab__h26667[1] && !ab__h28540[1] && !ab__h26682[1] &&
!ab__h28933[1] &&
(ab__h26697[1] || ab__h29277[1]) ;
assign NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136 =
!ab__h12602[1] && !ab__h14853[1] && !ab__h12617[1] &&
!ab__h15197[1] &&
(ab__h12632[1] || ab__h15492[1]) ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h5562[1] && !ab__h7813[1] && !ab__h5577[1] &&
!ab__h8157[1] &&
(ab__h5592[1] || ab__h8452[1]) ;
assign NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258 =
!ab__h26652[1] && !ab__h28093[1] && !ab__h26667[1] &&
!ab__h28540[1] &&
(ab__h26682[1] || ab__h28933[1]) ;
assign NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278 =
!ab__h26652[1] && !ab__h28093[1] && !ab__h26667[1] &&
!ab__h28540[1] &&
NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276 ;
assign NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206 =
!ab__h19642[1] && !ab__h21893[1] && !ab__h19657[1] &&
!ab__h22237[1] &&
(ab__h19672[1] || ab__h22532[1]) ;
assign NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197 =
!ab__h19627[1] && !ab__h21500[1] && !ab__h19642[1] &&
!ab__h21893[1] &&
(ab__h19657[1] || ab__h22237[1]) ;
assign NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188 =
!ab__h19612[1] && !ab__h21053[1] && !ab__h19627[1] &&
!ab__h21500[1] &&
(ab__h19642[1] || ab__h21893[1]) ;
assign NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208 =
!ab__h19612[1] && !ab__h21053[1] && !ab__h19627[1] &&
!ab__h21500[1] &&
NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206 ;
assign NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127 =
!ab__h12587[1] && !ab__h14460[1] && !ab__h12602[1] &&
!ab__h14853[1] &&
(ab__h12617[1] || ab__h15197[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h5547[1] && !ab__h7420[1] && !ab__h5562[1] &&
!ab__h7813[1] &&
(ab__h5577[1] || ab__h8157[1]) ;
assign NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346 =
!ab__h33722[1] && !ab__h35973[1] && !ab__h33737[1] &&
!ab__h36317[1] &&
(ab__h33752[1] || ab__h36612[1]) ;
assign NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337 =
!ab__h33707[1] && !ab__h35580[1] && !ab__h33722[1] &&
!ab__h35973[1] &&
(ab__h33737[1] || ab__h36317[1]) ;
assign ab_BIT_0___h13184 = ab__h12632[0] ;
assign ab_BIT_0___h13291 = ab__h12617[0] ;
assign ab_BIT_0___h13398 = ab__h12602[0] ;
assign ab_BIT_0___h13505 = ab__h12587[0] ;
assign ab_BIT_0___h14084 = ab__h12572[0] ;
assign ab_BIT_0___h14220 = ab__h14460[0] ;
assign ab_BIT_0___h14613 = ab__h14853[0] ;
assign ab_BIT_0___h14957 = ab__h15197[0] ;
assign ab_BIT_0___h15252 = ab__h15492[0] ;
assign ab_BIT_0___h20224 = ab__h19672[0] ;
assign ab_BIT_0___h20331 = ab__h19657[0] ;
assign ab_BIT_0___h20438 = ab__h19642[0] ;
assign ab_BIT_0___h20545 = ab__h19627[0] ;
assign ab_BIT_0___h21124 = ab__h19612[0] ;
assign ab_BIT_0___h21260 = ab__h21500[0] ;
assign ab_BIT_0___h21653 = ab__h21893[0] ;
assign ab_BIT_0___h21997 = ab__h22237[0] ;
assign ab_BIT_0___h22292 = ab__h22532[0] ;
assign ab_BIT_0___h27264 = ab__h26712[0] ;
assign ab_BIT_0___h27371 = ab__h26697[0] ;
assign ab_BIT_0___h27478 = ab__h26682[0] ;
assign ab_BIT_0___h27585 = ab__h26667[0] ;
assign ab_BIT_0___h28164 = ab__h26652[0] ;
assign ab_BIT_0___h28300 = ab__h28540[0] ;
assign ab_BIT_0___h28693 = ab__h28933[0] ;
assign ab_BIT_0___h29037 = ab__h29277[0] ;
assign ab_BIT_0___h29332 = ab__h29572[0] ;
assign ab_BIT_0___h34304 = ab__h33752[0] ;
assign ab_BIT_0___h34411 = ab__h33737[0] ;
assign ab_BIT_0___h34518 = ab__h33722[0] ;
assign ab_BIT_0___h34625 = ab__h33707[0] ;
assign ab_BIT_0___h35204 = ab__h33692[0] ;
assign ab_BIT_0___h35340 = ab__h35580[0] ;
assign ab_BIT_0___h35733 = ab__h35973[0] ;
assign ab_BIT_0___h36077 = ab__h36317[0] ;
assign ab_BIT_0___h36372 = ab__h36612[0] ;
assign ab_BIT_0___h6144 = ab__h5592[0] ;
assign ab_BIT_0___h6251 = ab__h5577[0] ;
assign ab_BIT_0___h6358 = ab__h5562[0] ;
assign ab_BIT_0___h6465 = ab__h5547[0] ;
assign ab_BIT_0___h7044 = ab__h5532[0] ;
assign ab_BIT_0___h7180 = ab__h7420[0] ;
assign ab_BIT_0___h7573 = ab__h7813[0] ;
assign ab_BIT_0___h7917 = ab__h8157[0] ;
assign ab_BIT_0___h8212 = ab__h8452[0] ;
assign oas_0_token_BIT_0___h6142 = oas_0_token[0] ;
assign oas_0_token_BIT_1___h6249 = oas_0_token[1] ;
assign oas_0_token_BIT_2___h6356 = oas_0_token[2] ;
assign oas_0_token_BIT_3___h6463 = oas_0_token[3] ;
assign oas_0_token_BIT_4___h6570 = oas_0_token[4] ;
assign oas_1_token_BIT_0___h13182 = oas_1_token[0] ;
assign oas_1_token_BIT_1___h13289 = oas_1_token[1] ;
assign oas_1_token_BIT_2___h13396 = oas_1_token[2] ;
assign oas_1_token_BIT_3___h13503 = oas_1_token[3] ;
assign oas_1_token_BIT_4___h13610 = oas_1_token[4] ;
assign oas_2_token_BIT_0___h20222 = oas_2_token[0] ;
assign oas_2_token_BIT_1___h20329 = oas_2_token[1] ;
assign oas_2_token_BIT_2___h20436 = oas_2_token[2] ;
assign oas_2_token_BIT_3___h20543 = oas_2_token[3] ;
assign oas_2_token_BIT_4___h20650 = oas_2_token[4] ;
assign oas_3_token_BIT_0___h27262 = oas_3_token[0] ;
assign oas_3_token_BIT_1___h27369 = oas_3_token[1] ;
assign oas_3_token_BIT_2___h27476 = oas_3_token[2] ;
assign oas_3_token_BIT_3___h27583 = oas_3_token[3] ;
assign oas_3_token_BIT_4___h27690 = oas_3_token[4] ;
assign oas_4_token_BIT_0___h34302 = oas_4_token[0] ;
assign oas_4_token_BIT_1___h34409 = oas_4_token[1] ;
assign oas_4_token_BIT_2___h34516 = oas_4_token[2] ;
assign oas_4_token_BIT_3___h34623 = oas_4_token[3] ;
assign oas_4_token_BIT_4___h34730 = oas_4_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
oas_0_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
oas_1_token <= `BSV_ASSIGNMENT_DELAY 5'd2;
oas_2_token <= `BSV_ASSIGNMENT_DELAY 5'd4;
oas_3_token <= `BSV_ASSIGNMENT_DELAY 5'd8;
oas_4_token <= `BSV_ASSIGNMENT_DELAY 5'd16;
end
else
begin
if (oas_0_token$EN)
oas_0_token <= `BSV_ASSIGNMENT_DELAY oas_0_token$D_IN;
if (oas_1_token$EN)
oas_1_token <= `BSV_ASSIGNMENT_DELAY oas_1_token$D_IN;
if (oas_2_token$EN)
oas_2_token <= `BSV_ASSIGNMENT_DELAY oas_2_token$D_IN;
if (oas_3_token$EN)
oas_3_token <= `BSV_ASSIGNMENT_DELAY oas_3_token$D_IN;
if (oas_4_token$EN)
oas_4_token <= `BSV_ASSIGNMENT_DELAY oas_4_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
oas_0_token = 5'h0A;
oas_1_token = 5'h0A;
oas_2_token = 5'h0A;
oas_3_token = 5'h0A;
oas_4_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkRouterOutputArbitersRoundRobin
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module sd(
input CLK_I,
input RST_I,
output reg CYC_O,
output reg [31:0] DAT_O,
output reg STB_O,
output reg WE_O,
output [31:2] ADR_O,
output [3:0] SEL_O,
input [31:0] DAT_I,
input ACK_I,
input ERR_I,
input RTY_I,
// TAG_TYPE: TGC_O
output SGL_O,
output BLK_O,
output RMW_O,
// TAG_TYPE: TGA_O
output [2:0] CTI_O,
output [1:0] BTE_O,
//slave
output [31:0] slave_DAT_O,
input [31:0] slave_DAT_I,
output reg ACK_O,
output ERR_O,
output RTY_O,
input CYC_I,
input [3:2] ADR_I,
input STB_I,
input WE_I,
input [3:0] SEL_I,
//sd bus 1-bit interface
output reg sd_clk_o = 1'b0,
inout sd_cmd_io,
inout sd_dat_io,
output [5:0] debug_leds
);
/***********************************************************************************************************************
* Wishbone interface
**********************************************************************************************************************/
assign debug_leds = { (RST_I == 1'b1), (error_count == 16'd65535), control_state };
//---------------------------------------------------- wishbone master
assign SGL_O = 1'b1;
assign BLK_O = 1'b0;
assign RMW_O = 1'b0;
assign SEL_O = 4'b1111;
assign BTE_O = 2'b00;
assign CTI_O = 3'b000;
assign ADR_O = wb_address[31:2] + { 23'b0, part_counter };
reg bus_error;
reg data_read = 1'b0;
reg data_write = 1'b0;
reg [31:0] data_part_contents;
//STB_O,CYC_O,WE_O,DAT_O,
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
DAT_O <= 32'd0;
bus_error <= 1'b0;
data_read <= 1'b0;
data_write <= 1'b0;
data_part_contents <= 32'd0;
end
else if(data_state == S_DATA_READ_READY_PART && data_read == 1'b0) begin
if(ACK_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
data_read <= 1'b1;
end
else if(RTY_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
end
else if(ERR_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
data_read <= 1'b1;
bus_error <= 1'b1;
end
else begin
STB_O <= 1'b1;
CYC_O <= 1'b1;
WE_O <= 1'b1;
DAT_O <= data_part;
end
end
else if(data_state == S_DATA_WRITE_READY_PART && data_write == 1'b0) begin
if(ACK_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
data_part_contents <= DAT_I;
data_write <= 1'b1;
end
else if(RTY_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
end
else if(ERR_I == 1'b1) begin
STB_O <= 1'b0;
CYC_O <= 1'b0;
WE_O <= 1'b0;
data_write <= 1'b1;
bus_error <= 1'b1;
end
else begin
STB_O <= 1'b1;
CYC_O <= 1'b1;
WE_O <= 1'b0;
end
end
else if(data_state != S_DATA_READ_READY_PART && data_state != S_DATA_WRITE_READY_PART) begin
if(status == STATUS_ERROR) begin
bus_error <= 1'b0;
end
data_read <= 1'b0;
data_write <= 1'b0;
end
end
//---------------------------------------------------- wishbone slave
assign ERR_O = 1'b0;
assign RTY_O = 1'b0;
assign slave_DAT_O = {29'd0, status[2:0]};
//write only
reg [31:0] wb_address;
reg [31:0] sd_address;
reg [31:0] sd_block_count;
reg [1:0] control;
reg [3:0] last_control_state;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
wb_address <= 32'd0;
sd_address <= 32'd0;
sd_block_count <= 32'd0;
control <= 2'd0;
ACK_O <= 1'b0;
last_control_state <= 4'd0;
end
else begin
last_control_state <= control_state;
if( (last_control_state == S_CTRL_CMD17_READ || last_control_state == S_CTRL_CMD24_WRITE) &&
control_state == S_CTRL_PRE_IDLE
) begin
sd_block_count <= sd_block_count - 32'd1;
sd_address <= sd_address + 32'd1;
wb_address <= wb_address + 32'd512;
ACK_O <= 1'b0;
end
else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1) begin
ACK_O <= 1'b1;
if(ADR_I[3:2] == 2'b00) begin
wb_address[31:24] <= (SEL_I[3] == 1'b1) ? slave_DAT_I[31:24] : wb_address[31:24];
wb_address[23:16] <= (SEL_I[2] == 1'b1) ? slave_DAT_I[23:16] : wb_address[23:16];
wb_address[15:8] <= (SEL_I[1] == 1'b1) ? slave_DAT_I[15:8] : wb_address[15:8];
wb_address[7:0] <= (SEL_I[0] == 1'b1) ? slave_DAT_I[7:0] : wb_address[7:0];
end
else if(ADR_I[3:2] == 2'b01) begin
sd_address[31:24] <= (SEL_I[3] == 1'b1) ? slave_DAT_I[31:24] : sd_address[31:24];
sd_address[23:16] <= (SEL_I[2] == 1'b1) ? slave_DAT_I[23:16] : sd_address[23:16];
sd_address[15:8] <= (SEL_I[1] == 1'b1) ? slave_DAT_I[15:8] : sd_address[15:8];
sd_address[7:0] <= (SEL_I[0] == 1'b1) ? slave_DAT_I[7:0] : sd_address[7:0];
end
else if(ADR_I[3:2] == 2'b10) begin
sd_block_count[31:24] <= (SEL_I[3] == 1'b1) ? slave_DAT_I[31:24] : sd_block_count[31:24];
sd_block_count[23:16] <= (SEL_I[2] == 1'b1) ? slave_DAT_I[23:16] : sd_block_count[23:16];
sd_block_count[15:8] <= (SEL_I[1] == 1'b1) ? slave_DAT_I[15:8] : sd_block_count[15:8];
sd_block_count[7:0] <= (SEL_I[0] == 1'b1) ? slave_DAT_I[7:0] : sd_block_count[7:0];
end
else if(ADR_I[3:2] == 2'b11) begin
control[1:0] <= (SEL_I[0] == 1'b1) ? slave_DAT_I[1:0] : control[1:0];
end
end
else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0 && ADR_I[3:2] == 2'b00) begin
ACK_O <= 1'b1;
end
else begin
ACK_O <= 1'b0;
end
end
end
/***********************************************************************************************************************
* Control state machine
**********************************************************************************************************************/
reg [3:0] control_state;
reg [15:0] error_count;
reg [2:0] status;
reg [37:0] cmd_send_contents;
reg start_cmd = 1'b0;
reg start_read = 1'b0;
reg start_write = 1'b0;
`define CRC7_REVERSE crc7[0],crc7[1],crc7[2],crc7[3],crc7[4],crc7[5],crc7[6]
parameter [3:0]
S_CTRL_INIT = 4'd0,
S_CTRL_CMD0 = 4'd1,
S_CTRL_CMD8 = 4'd2,
S_CTRL_CMD55 = 4'd3,
S_CTRL_ACMD41 = 4'd4,
S_CTRL_CMD2 = 4'd5,
S_CTRL_CMD3 = 4'd6,
S_CTRL_CMD7 = 4'd7,
S_CTRL_PRE_IDLE = 4'd8,
S_CTRL_IDLE = 4'd9,
S_CTRL_CMD17_READ = 4'd10,
S_CTRL_CMD24_WRITE = 4'd11;
parameter [2:0]
STATUS_INIT = 3'd0,
STATUS_INIT_ERROR = 3'd1,
STATUS_IDLE = 3'd2,
STATUS_READ = 3'd3,
STATUS_WRITE = 3'd4,
STATUS_ERROR = 3'd4;
parameter [1:0]
CONTROL_IDLE = 2'd0,
CONTROL_REINIT = 2'd1,
CONTROL_READ = 2'd2,
CONTROL_WRITE = 2'd3;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
control_state <= S_CTRL_INIT;
status <= STATUS_INIT;
cmd_send_contents <= 38'd0;
start_cmd <= 1'b0;
start_read <= 1'b0;
start_write <= 1'b0;
error_count <= 16'd0;
end
else if(control_state == S_CTRL_INIT && error_count == 16'd65535) begin
status <= STATUS_INIT_ERROR;
if(control == CONTROL_REINIT) begin
error_count <= 16'd0;
control_state <= S_CTRL_INIT;
end
end
else if(control_state == S_CTRL_INIT) begin
status <= STATUS_INIT;
start_cmd <= 1'b1;
if(cmd_state == S_CMD_IDLE) begin
//CMD0, no arguments
cmd_send_contents <= { 6'd0, 32'd0 };
control_state <= S_CTRL_CMD0;
end
end
else if(control_state == S_CTRL_CMD0) begin
if(cmd_state == S_CMD_REPLY_ERROR) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD8, supply voltage, check pattern
cmd_send_contents <= { 6'd8, 20'd0, 4'b0001, 8'b10101010 };
control_state <= S_CTRL_CMD8;
end
else start_cmd <= 1'b0;
end
else if(control_state == S_CTRL_CMD8) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE && cmd_reply != { 1'b0, 1'b0, 6'd8, 20'd0, 4'b0001, 8'b10101010, `CRC7_REVERSE, 1'b1 })
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE) begin
start_cmd <= 1'b1;
//CMD55, RCA
cmd_send_contents <= { 6'd55, 16'd0, 16'd0};
control_state <= S_CTRL_CMD55;
end
end
else if(control_state == S_CTRL_CMD55) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd55 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b1 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//ACMD41,
cmd_send_contents <= { 6'd41, //command index
1'b0, //reserved bit
1'b1, //host capacity support HCS(OCR[30])
6'b0, //reserved bits
24'b0001_0000_0000_0000_0000_0000 //VDD voltage window OCR[23:0]
};
control_state <= S_CTRL_ACMD41;
end
end
else if(control_state == S_CTRL_ACMD41) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE && (cmd_reply[47:40] != { 1'b0, 1'b0, 6'b111111 } ||
cmd_reply[39:38] != 2'b11 || cmd_reply[7:0] != {7'b1111111, 1'b1 })
)
) begin
if(error_count == 16'd65535) begin
control_state <= S_CTRL_INIT;
end
else begin
error_count <= error_count + 16'd1;
start_cmd <= 1'b1;
//CMD55, RCA
cmd_send_contents <= { 6'd55, 16'd0, 16'd0};
control_state <= S_CTRL_CMD55;
end
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD2, no arguments
cmd_send_contents <= { 6'd2, 32'd0 };
control_state <= S_CTRL_CMD2;
end
end
else if(control_state == S_CTRL_CMD2) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE && cmd_reply[0] != 1'b1)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD3, no arguments
cmd_send_contents <= { 6'd3, 32'd0 };
control_state <= S_CTRL_CMD3;
end
end
else if(control_state == S_CTRL_CMD3) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd3 } ||
/*23:8= 23,22,19,12:0 from card status*/
cmd_reply[23:21] != 3'b0 || cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 ||
cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b1;
//CMD7, no arguments
cmd_send_contents <= { 6'd7, //command index
cmd_reply[39:24], //RCA
16'd0 //stuff bits
};
control_state <= S_CTRL_CMD7;
end
end
else if(control_state == S_CTRL_CMD7) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd7 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_INIT;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0) begin
start_cmd <= 1'b0;
error_count <= 16'd0;
control_state <= S_CTRL_IDLE;
end
end
else if(control_state == S_CTRL_PRE_IDLE) begin
control_state <= S_CTRL_IDLE;
if(bus_error == 1'b1) error_count <= 16'd65535;
end
else if(control_state == S_CTRL_IDLE && error_count == 16'd65535) begin
status <= STATUS_ERROR;
if(control == CONTROL_IDLE) begin
control_state <= S_CTRL_IDLE;
error_count <= 16'd0;
end
else if(control == CONTROL_REINIT) begin
control_state <= S_CTRL_INIT;
error_count <= 16'd0;
end
end
else if(control_state == S_CTRL_IDLE) begin
if(control == CONTROL_READ && sd_block_count != 32'd0) begin
status <= STATUS_READ;
start_cmd <= 1'b1;
start_read <= 1'b1;
//CMD17, sector address
cmd_send_contents <= { 6'd17, //command index
sd_address[31:0] //sector address
};
control_state <= S_CTRL_CMD17_READ;
end
else if(control == CONTROL_WRITE && sd_block_count != 32'd0) begin
status <= STATUS_WRITE;
start_cmd <= 1'b1;
start_write <= 1'b1;
//CMD24, sector address
cmd_send_contents <= { 6'd24, //command index
sd_address[31:0] //sector address
};
control_state <= S_CTRL_CMD24_WRITE;
end
else begin
status <= STATUS_IDLE;
end
end
else if(control_state == S_CTRL_CMD17_READ) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd17 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_read == 1'b1) begin
start_read <= 1'b0;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_read == 1'b0 && data_state == S_DATA_READ_ERROR) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_read == 1'b0 && data_state == S_DATA_IDLE) begin
error_count <= 16'd0;
control_state <= S_CTRL_PRE_IDLE;
end
end
else if(control_state == S_CTRL_CMD24_WRITE) begin
if(start_cmd == 1'b1) begin
start_cmd <= 1'b0;
end
else if(cmd_state == S_CMD_REPLY_ERROR ||
(cmd_state == S_CMD_IDLE &&
(cmd_reply[47:40] != { 1'b0, 1'b0, 6'd24 } || cmd_reply[39:27] != 13'b0 || cmd_reply[24:21] != 4'b0 ||
cmd_reply[13] != 1'b0 || cmd_reply[11] != 1'b0 || cmd_reply[7:0] != { `CRC7_REVERSE, 1'b1 }
)
)
) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_write == 1'b1) begin
start_write <= 1'b0;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_write == 1'b0 && data_state == S_DATA_WRITE_ERROR) begin
error_count <= error_count + 16'd1;
control_state <= S_CTRL_IDLE;
end
else if(cmd_state == S_CMD_IDLE && start_cmd == 1'b0 && start_write == 1'b0 && data_state == S_DATA_IDLE) begin
error_count <= 16'd0;
control_state <= S_CTRL_PRE_IDLE;
end
end
end
/***********************************************************************************************************************
* SD interface
**********************************************************************************************************************/
reg sd_cmd_o = 1'b1;
reg sd_dat_o = 1'b1;
assign sd_cmd_io = (sd_cmd_enable == 1'b1) ? sd_cmd_o : 1'bZ;
assign sd_dat_io = (sd_data_enable == 1'b1) ? sd_dat_o : 1'bZ;
//CID register not interpreted: CRC7 not checked, always accepted
//---------------------------------------------------- SD data
reg sd_data_enable;
reg [3:0] data_state;
reg [15:0] data_counter;
reg [6:0] part_counter;
reg [15:0] crc16;
reg [31:0] data_part;
reg clk_data_ena;
reg clk_master_ena = 1'b1;
parameter [3:0]
S_DATA_IDLE = 4'd0,
S_DATA_READ_START_BIT = 4'd1,
S_DATA_READ_CONTENTS = 4'd2,
S_DATA_READ_READY_PART = 4'd3,
S_DATA_READ_READY_PART_CONTINUE = 4'd4,
S_DATA_READ_CRC16_END_BIT = 4'd5,
S_DATA_READ_ERROR = 4'd6,
S_DATA_WRITE_START_BIT = 4'd7,
S_DATA_WRITE_READY_PART = 4'd8,
S_DATA_WRITE_CONTENTS = 4'd9,
S_DATA_WRITE_CRC16_END_BIT = 4'd10,
S_DATA_WRITE_CRC_STATUS_START = 4'd11,
S_DATA_WRITE_CRC_STATUS_CONTENTS_END_BIT = 4'd12,
S_DATA_WRITE_BUSY_START = 4'd13,
S_DATA_WRITE_BUSY_WAIT = 4'd14,
S_DATA_WRITE_ERROR = 4'd15;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
sd_data_enable <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 16'd0;
part_counter <= 7'd0;
crc16 <= 16'd0;
data_part <= 32'd0;
clk_data_ena <= 1'b0;
clk_master_ena <= 1'b1;
sd_dat_o <= 1'b1;
end
else if(clk_counter == 2'd0) begin
if(data_state == S_DATA_IDLE) begin
if(start_read == 1'b1) begin
crc16 <= 16'd0;
data_state <= S_DATA_READ_START_BIT;
end
else if(start_write == 1'b1 && start_cmd == 1'b0 && cmd_state == S_CMD_IDLE) begin
crc16 <= 16'd0;
clk_data_ena <= 1'b1;
data_state <= S_DATA_WRITE_START_BIT;
end
end
//wait for response and data simultaneously (data read)
else if(data_state == S_DATA_READ_START_BIT) begin
clk_data_ena <= 1'b1;
if(sd_dat_io == 1'b0) begin
crc16 <= { sd_dat_io ^ crc16[0], crc16[15:12], sd_dat_io ^ crc16[11] ^ crc16[0], crc16[10:5],
sd_dat_io ^ crc16[4] ^ crc16[0], crc16[3:1] };
data_state <= S_DATA_READ_CONTENTS;
data_counter <= 16'd0;
end
else if(data_counter == 16'd65535) begin
crc16 <= 16'd0;
data_state <= S_DATA_READ_ERROR;
data_counter <= 16'd0;
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_READ_CONTENTS) begin
crc16 <= { sd_dat_io ^ crc16[0], crc16[15:12], sd_dat_io ^ crc16[11] ^ crc16[0],
crc16[10:5], sd_dat_io ^ crc16[4] ^ crc16[0], crc16[3:1] };
data_part <= { data_part[30:0], sd_dat_io };
if(data_counter == 16'd30) begin
clk_master_ena <= 1'b0;
data_counter <= data_counter + 16'd1;
end
else if(data_counter == 16'd31) begin
data_state <= S_DATA_READ_READY_PART;
data_counter <= 16'd0;
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_READ_READY_PART) begin
if(data_read == 1'b1) begin
clk_master_ena <= 1'b1;
data_state <= S_DATA_READ_READY_PART_CONTINUE;
end
end
else if(data_state == S_DATA_READ_READY_PART_CONTINUE) begin
if(part_counter == 7'd127) begin
data_state <= S_DATA_READ_CRC16_END_BIT;
part_counter <= 7'd0;
end
else begin
data_state <= S_DATA_READ_CONTENTS;
part_counter <= part_counter + 7'd1;
end
end
else if(data_state == S_DATA_READ_CRC16_END_BIT) begin
data_part <= { sd_dat_io, data_part[31:1] };
if(data_counter == 16'd16) begin
if(data_part[31:16] != crc16[15:0] || sd_dat_io != 1'b1) begin
data_state <= S_DATA_READ_ERROR;
data_counter <= 16'd0;
end
else begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 16'd0;
end
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_READ_ERROR) begin
if(start_read == 1'b1 || start_write == 1'b1) begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 16'd0;
end
end
//send data on data line, wait for crc status, wait for busy on data line (data write)
else if(data_state == S_DATA_WRITE_START_BIT) begin
sd_dat_o <= 1'b0;
crc16 <= { 1'b0 ^ crc16[0], crc16[15:12], 1'b0 ^ crc16[11] ^ crc16[0], crc16[10:5],
1'b0 ^ crc16[4] ^ crc16[0], crc16[3:1] };
sd_data_enable <= 1'b1;
clk_data_ena <= 1'b0;
data_counter <= 16'd0;
data_state <= S_DATA_WRITE_READY_PART;
end
else if(data_state == S_DATA_WRITE_READY_PART) begin
if(data_write == 1'b1) begin
data_state <= S_DATA_WRITE_CONTENTS;
data_part <= data_part_contents;
end
end
else if(data_state == S_DATA_WRITE_CONTENTS) begin
sd_dat_o <= data_part[31];
crc16 <= { data_part[31] ^ crc16[0], crc16[15:12], data_part[31] ^ crc16[11] ^ crc16[0], crc16[10:5],
data_part[31] ^ crc16[4] ^ crc16[0], crc16[3:1] };
data_part <= { data_part[30:0], 1'b0 };
if(data_counter == 16'd31) begin
data_counter <= 16'd0;
if(part_counter == 7'd127) begin
part_counter <= 7'd0;
data_state <= S_DATA_WRITE_CRC16_END_BIT;
end
else begin
part_counter <= part_counter + 7'd1;
data_state <= S_DATA_WRITE_READY_PART;
end
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_WRITE_CRC16_END_BIT) begin
sd_dat_o <= crc16[0];
if(data_counter == 16'd17) begin
crc16 <= 16'd0;
data_state <= S_DATA_WRITE_CRC_STATUS_START;
end
else begin
crc16 <= { 1'b1, crc16[15:1] };
data_counter <= data_counter + 16'd1;
end
end
else if(data_state == S_DATA_WRITE_CRC_STATUS_START) begin
sd_data_enable <= 1'b0;
if(sd_dat_io == 1'b0) begin
data_state <= S_DATA_WRITE_CRC_STATUS_CONTENTS_END_BIT;
data_counter <= 16'b0;
end
else if(data_counter == 16'd65535) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 16'b0;
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_WRITE_CRC_STATUS_CONTENTS_END_BIT) begin
data_part <= { data_part[30:0], sd_dat_io };
if(data_counter == 16'd3) begin
data_state <= S_DATA_WRITE_BUSY_START;
data_counter <= 16'b0;
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_WRITE_BUSY_START) begin
if(sd_dat_io == 1'b0) begin
data_state <= S_DATA_WRITE_BUSY_WAIT;
data_counter <= 16'b0;
end
else if(data_counter == 16'd65535) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 16'b0;
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_WRITE_BUSY_WAIT) begin
if(sd_dat_io == 1'b1 && data_part[3:0] != 4'b0010) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 16'd0;
end
else if(sd_dat_io == 1'b1) begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 16'd0;
end
else if(data_counter == 16'd65535) begin
data_state <= S_DATA_WRITE_ERROR;
data_counter <= 16'd0;
end
else data_counter <= data_counter + 16'd1;
end
else if(data_state == S_DATA_WRITE_ERROR) begin
if(start_read == 1'b1 || start_write == 1'b1) begin
clk_data_ena <= 1'b0;
data_state <= S_DATA_IDLE;
data_counter <= 16'd0;
end
end
end
end
//---------------------------------------------------- SD command
reg sd_cmd_enable;
reg [37:0] cmd_send;
reg [47:0] cmd_reply;
reg [7:0] cmd_state;
reg [7:0] cmd_counter;
reg [6:0] crc7;
reg clk_cmd_ena;
parameter [7:0]
S_CMD_IDLE = 8'd0,
S_CMD_SEND_START_ONES = 8'd1,
S_CMD_SEND_START_BIT = 8'd2,
S_CMD_SEND_START_HOST = 8'd3,
S_CMD_SEND_CONTENTS = 8'd4,
S_CMD_SEND_CRC7 = 8'd5,
S_CMD_SEND_END_BIT = 8'd6,
S_CMD_SEND_END_ONES = 8'd7,
S_CMD_REPLY_START_BIT = 8'd8,
S_CMD_REPLY_CONTENTS = 8'd9,
S_CMD_REPLY_CRC7_END_BIT = 8'd10,
S_CMD_REPLY_FINISH_ONES = 8'd11,
S_CMD_REPLY_ERROR = 8'd12;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
sd_cmd_enable <= 1'b0;
cmd_send <= 38'd0;
cmd_reply <= 48'd0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
crc7 <= 7'd0;
clk_cmd_ena <= 1'b0;
sd_cmd_o <= 1'b1;
end
else if(cmd_state == S_CMD_IDLE) begin
if(start_cmd == 1'b1) begin
cmd_state <= S_CMD_SEND_START_ONES;
end
end
else if(clk_counter == 2'd0 && clk_master_ena == 1'b1) begin
//send command
if(cmd_state == S_CMD_SEND_START_ONES) begin
sd_cmd_enable <= 1'b1;
sd_cmd_o <= 1'b1;
clk_cmd_ena <= 1'b1;
crc7 <= 7'd0;
if(cmd_counter == 8'd7) begin
cmd_state <= S_CMD_SEND_START_BIT;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_SEND_START_BIT) begin
sd_cmd_o <= 1'b0;
crc7 <= { 1'b0 ^ crc7[0], crc7[6:5], 1'b0 ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_state <= S_CMD_SEND_START_HOST;
end
else if(cmd_state == S_CMD_SEND_START_HOST) begin
sd_cmd_o <= 1'b1;
crc7 <= { 1'b1 ^ crc7[0], crc7[6:5], 1'b1 ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_send <= cmd_send_contents;
cmd_state <= S_CMD_SEND_CONTENTS;
end
else if(cmd_state == S_CMD_SEND_CONTENTS) begin
sd_cmd_o <= cmd_send[37];
crc7 <= { cmd_send[37] ^ crc7[0], crc7[6:5], cmd_send[37] ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_send <= { cmd_send[36:0], 1'b0 };
if(cmd_counter == 8'd37) begin
cmd_state <= S_CMD_SEND_CRC7;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_SEND_CRC7) begin
sd_cmd_o <= crc7[0];
crc7 <= { 1'b0, crc7[6:1] };
if(cmd_counter == 8'd6) begin
cmd_state <= S_CMD_SEND_END_BIT;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_SEND_END_BIT) begin
sd_cmd_o <= 1'b1;
// if CMD0: send ones
if(control_state == S_CTRL_CMD0) begin
cmd_state <= S_CMD_SEND_END_ONES;
end
else begin
crc7 <= 7'd0;
cmd_state <= S_CMD_REPLY_START_BIT;
end
end
else if(cmd_state == S_CMD_SEND_END_ONES) begin
sd_cmd_enable <= 1'b0;
sd_cmd_o <= 1'b1;
if(cmd_counter == 8'd7) begin
clk_cmd_ena <= 1'b0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
//wait for response: 48-bits with CRC7
//wait for response: 48-bits without CRC7
//wait for response: 136-bits (CMD2/R2)
//wait for response and busy on data line simultaneously: (CMD7/R1b)
else if(cmd_state == S_CMD_REPLY_START_BIT) begin
sd_cmd_enable <= 1'b0;
if(sd_cmd_io == 1'b0) begin
crc7 <= { sd_cmd_io ^ crc7[0], crc7[6:5], sd_cmd_io ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_reply <= { cmd_reply[46:0], sd_cmd_io };
cmd_state <= S_CMD_REPLY_CONTENTS;
cmd_counter <= 8'd0;
end
else if(cmd_counter == 8'd255) begin
crc7 <= 7'd0;
cmd_state <= S_CMD_REPLY_ERROR;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_REPLY_CONTENTS) begin
crc7 <= { sd_cmd_io ^ crc7[0], crc7[6:5], sd_cmd_io ^ crc7[4] ^ crc7[0], crc7[3:1] };
cmd_reply <= { cmd_reply[46:0], sd_cmd_io };
if( (control_state != S_CTRL_CMD2 && cmd_counter == 8'd38) ||
(control_state == S_CTRL_CMD2 && cmd_counter == 8'd134)
) begin
cmd_state <= S_CMD_REPLY_CRC7_END_BIT;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_REPLY_CRC7_END_BIT) begin
cmd_reply <= { cmd_reply[46:0], sd_cmd_io };
if(cmd_counter == 8'd7) begin
cmd_state <= S_CMD_REPLY_FINISH_ONES;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
//at least 2 clock cycles required for data write
else if(cmd_state == S_CMD_REPLY_FINISH_ONES) begin
//check is sd_dat_io busy for CMD7
if(cmd_counter >= 8'd7 && (control_state != S_CTRL_CMD7 || sd_dat_io == 1'b1)) begin
clk_cmd_ena <= 1'b0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
end
else if(cmd_counter == 8'd255) begin
cmd_state <= S_CMD_REPLY_ERROR;
cmd_counter <= 8'd0;
end
else cmd_counter <= cmd_counter + 8'd1;
end
else if(cmd_state == S_CMD_REPLY_ERROR) begin
if(start_cmd == 1'b1) begin
clk_cmd_ena <= 1'b0;
cmd_state <= S_CMD_IDLE;
cmd_counter <= 8'd0;
end
end
end
end
//---------------------------------------------------- SD clock
reg [1:0] clk_counter;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
sd_clk_o <= 1'b0;
clk_counter <= 2'd0;
end
else if(clk_counter == 2'd0) begin
sd_clk_o <= 1'd0;
if(clk_master_ena == 1'b1 && (clk_cmd_ena == 1'b1 || clk_data_ena == 1'b1)) begin
clk_counter <= clk_counter + 2'd1;
end
end
else if(clk_counter == 2'd1) begin
sd_clk_o <= 1'b1;
clk_counter <= clk_counter + 2'd1;
end
else if(clk_counter == 2'd2) begin //was 5
sd_clk_o <= 1'b0;
clk_counter <= clk_counter + 2'd1;
end
else clk_counter <= clk_counter + 2'd1;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:10 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_1_0/system_vga_gaussian_blur_1_0_sim_netlist.v
// Design : system_vga_gaussian_blur_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_gaussian_blur_1_0,vga_gaussian_blur,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_gaussian_blur,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_gaussian_blur_1_0
(clk_25,
hsync_in,
vsync_in,
rgb_in,
hsync_out,
vsync_out,
rgb_blur,
rgb_pass);
input clk_25;
input hsync_in;
input vsync_in;
input [23:0]rgb_in;
output hsync_out;
output vsync_out;
output [23:0]rgb_blur;
output [23:0]rgb_pass;
wire \<const0> ;
wire \A[0]__14_n_0 ;
wire \A[0]__15_srl29_n_0 ;
wire \A[0]__16_n_0 ;
wire \A[0]__18_n_0 ;
wire \A[0]__24_n_0 ;
wire \A[0]__25_srl29_n_0 ;
wire \A[0]__26_n_0 ;
wire \A[0]__28_n_0 ;
wire \A[0]__4_n_0 ;
wire \A[0]__5_srl29_n_0 ;
wire \A[0]__6_n_0 ;
wire \A[0]__8_n_0 ;
wire \A[1]__14_n_0 ;
wire \A[1]__15_srl29_n_0 ;
wire \A[1]__16_n_0 ;
wire \A[1]__18_n_0 ;
wire \A[1]__24_n_0 ;
wire \A[1]__25_srl29_n_0 ;
wire \A[1]__26_n_0 ;
wire \A[1]__28_n_0 ;
wire \A[1]__4_n_0 ;
wire \A[1]__5_srl29_n_0 ;
wire \A[1]__6_n_0 ;
wire \A[1]__8_n_0 ;
wire \A[2]__14_n_0 ;
wire \A[2]__15_srl29_n_0 ;
wire \A[2]__16_n_0 ;
wire \A[2]__18_n_0 ;
wire \A[2]__24_n_0 ;
wire \A[2]__25_srl29_n_0 ;
wire \A[2]__26_n_0 ;
wire \A[2]__28_n_0 ;
wire \A[2]__4_n_0 ;
wire \A[2]__5_srl29_n_0 ;
wire \A[2]__6_n_0 ;
wire \A[2]__8_n_0 ;
wire \A[3]__14_n_0 ;
wire \A[3]__15_srl29_n_0 ;
wire \A[3]__16_n_0 ;
wire \A[3]__18_n_0 ;
wire \A[3]__24_n_0 ;
wire \A[3]__25_srl29_n_0 ;
wire \A[3]__26_n_0 ;
wire \A[3]__28_n_0 ;
wire \A[3]__4_n_0 ;
wire \A[3]__5_srl29_n_0 ;
wire \A[3]__6_n_0 ;
wire \A[3]__8_n_0 ;
wire \A[4]__14_n_0 ;
wire \A[4]__15_srl29_n_0 ;
wire \A[4]__16_n_0 ;
wire \A[4]__18_n_0 ;
wire \A[4]__24_n_0 ;
wire \A[4]__25_srl29_n_0 ;
wire \A[4]__26_n_0 ;
wire \A[4]__28_n_0 ;
wire \A[4]__4_n_0 ;
wire \A[4]__5_srl29_n_0 ;
wire \A[4]__6_n_0 ;
wire \A[4]__8_n_0 ;
wire \A[5]__14_n_0 ;
wire \A[5]__15_srl29_n_0 ;
wire \A[5]__16_n_0 ;
wire \A[5]__18_n_0 ;
wire \A[5]__24_n_0 ;
wire \A[5]__25_srl29_n_0 ;
wire \A[5]__26_n_0 ;
wire \A[5]__28_n_0 ;
wire \A[5]__4_n_0 ;
wire \A[5]__5_srl29_n_0 ;
wire \A[5]__6_n_0 ;
wire \A[5]__8_n_0 ;
wire \A[6]__14_n_0 ;
wire \A[6]__15_srl29_n_0 ;
wire \A[6]__16_n_0 ;
wire \A[6]__18_n_0 ;
wire \A[6]__24_n_0 ;
wire \A[6]__25_srl29_n_0 ;
wire \A[6]__26_n_0 ;
wire \A[6]__28_n_0 ;
wire \A[6]__4_n_0 ;
wire \A[6]__5_srl29_n_0 ;
wire \A[6]__6_n_0 ;
wire \A[6]__8_n_0 ;
wire \A[7]__14_n_0 ;
wire \A[7]__15_srl29_n_0 ;
wire \A[7]__16_n_0 ;
wire \A[7]__18_n_0 ;
wire \A[7]__24_n_0 ;
wire \A[7]__25_srl29_n_0 ;
wire \A[7]__26_n_0 ;
wire \A[7]__28_n_0 ;
wire \A[7]__4_n_0 ;
wire \A[7]__5_srl29_n_0 ;
wire \A[7]__6_n_0 ;
wire \A[7]__8_n_0 ;
wire [7:0]B;
wire \B[0]__1_n_0 ;
wire \B[0]__3_n_0 ;
wire \B[0]__4_n_0 ;
wire \B[0]__5_n_0 ;
wire \B[0]__7_n_0 ;
wire \B[0]__8_n_0 ;
wire \B[0]__9_n_0 ;
wire \B[1]__0_n_0 ;
wire \B[1]__10_n_0 ;
wire \B[1]__2_n_0 ;
wire \B[1]__4_n_0 ;
wire \B[1]__5_n_0 ;
wire \B[1]__6_n_0 ;
wire \B[1]__8_n_0 ;
wire \B[1]__9_n_0 ;
wire \B[2]__0_n_0 ;
wire \B[2]__10_n_0 ;
wire \B[2]__2_n_0 ;
wire \B[2]__4_n_0 ;
wire \B[2]__5_n_0 ;
wire \B[2]__6_n_0 ;
wire \B[2]__8_n_0 ;
wire \B[2]__9_n_0 ;
wire \B[3]__0_n_0 ;
wire \B[3]__10_n_0 ;
wire \B[3]__2_n_0 ;
wire \B[3]__4_n_0 ;
wire \B[3]__5_n_0 ;
wire \B[3]__6_n_0 ;
wire \B[3]__8_n_0 ;
wire \B[3]__9_n_0 ;
wire \B[4]__0_n_0 ;
wire \B[4]__10_n_0 ;
wire \B[4]__2_n_0 ;
wire \B[4]__4_n_0 ;
wire \B[4]__5_n_0 ;
wire \B[4]__6_n_0 ;
wire \B[4]__8_n_0 ;
wire \B[4]__9_n_0 ;
wire \B[5]__0_n_0 ;
wire \B[5]__10_n_0 ;
wire \B[5]__2_n_0 ;
wire \B[5]__4_n_0 ;
wire \B[5]__5_n_0 ;
wire \B[5]__6_n_0 ;
wire \B[5]__8_n_0 ;
wire \B[5]__9_n_0 ;
wire \B[6]__0_n_0 ;
wire \B[6]__10_n_0 ;
wire \B[6]__2_n_0 ;
wire \B[6]__4_n_0 ;
wire \B[6]__5_n_0 ;
wire \B[6]__6_n_0 ;
wire \B[6]__8_n_0 ;
wire \B[6]__9_n_0 ;
wire \B[7]__0_n_0 ;
wire \B[7]__10_n_0 ;
wire \B[7]__2_n_0 ;
wire \B[7]__4_n_0 ;
wire \B[7]__5_n_0 ;
wire \B[7]__6_n_0 ;
wire \B[7]__8_n_0 ;
wire \B[7]__9_n_0 ;
wire \B_n_0_[0] ;
wire [7:0]C;
wire \C[0]__0_n_0 ;
wire \C[0]__1_n_0 ;
wire \C[0]__2_n_0 ;
wire \C[0]__3_n_0 ;
wire \C[0]__4_n_0 ;
wire \C[1]__0_n_0 ;
wire \C[1]__1_n_0 ;
wire \C[1]__2_n_0 ;
wire \C[1]__3_n_0 ;
wire \C[1]__4_n_0 ;
wire \C[2]__0_n_0 ;
wire \C[2]__1_n_0 ;
wire \C[2]__2_n_0 ;
wire \C[2]__3_n_0 ;
wire \C[2]__4_n_0 ;
wire \C[3]__0_n_0 ;
wire \C[3]__1_n_0 ;
wire \C[3]__2_n_0 ;
wire \C[3]__3_n_0 ;
wire \C[3]__4_n_0 ;
wire \C[4]__0_n_0 ;
wire \C[4]__1_n_0 ;
wire \C[4]__2_n_0 ;
wire \C[4]__3_n_0 ;
wire \C[4]__4_n_0 ;
wire \C[5]__0_n_0 ;
wire \C[5]__1_n_0 ;
wire \C[5]__2_n_0 ;
wire \C[5]__3_n_0 ;
wire \C[5]__4_n_0 ;
wire \C[6]__0_n_0 ;
wire \C[6]__1_n_0 ;
wire \C[6]__2_n_0 ;
wire \C[6]__3_n_0 ;
wire \C[6]__4_n_0 ;
wire \C[7]__0_n_0 ;
wire \C[7]__1_n_0 ;
wire \C[7]__2_n_0 ;
wire \C[7]__3_n_0 ;
wire \C[7]__4_n_0 ;
wire U0_n_1;
wire U0_n_10;
wire U0_n_11;
wire U0_n_12;
wire U0_n_13;
wire U0_n_14;
wire U0_n_15;
wire U0_n_16;
wire U0_n_17;
wire U0_n_18;
wire U0_n_19;
wire U0_n_2;
wire U0_n_20;
wire U0_n_21;
wire U0_n_22;
wire U0_n_23;
wire U0_n_24;
wire U0_n_25;
wire U0_n_26;
wire U0_n_27;
wire U0_n_28;
wire U0_n_29;
wire U0_n_3;
wire U0_n_30;
wire U0_n_31;
wire U0_n_32;
wire U0_n_33;
wire U0_n_34;
wire U0_n_35;
wire U0_n_36;
wire U0_n_37;
wire U0_n_38;
wire U0_n_39;
wire U0_n_4;
wire U0_n_40;
wire U0_n_41;
wire U0_n_42;
wire U0_n_43;
wire U0_n_44;
wire U0_n_45;
wire U0_n_46;
wire U0_n_47;
wire U0_n_48;
wire U0_n_5;
wire U0_n_6;
wire U0_n_7;
wire U0_n_8;
wire U0_n_9;
wire active;
wire clk_25;
wire hsync_in;
wire [23:0]rgb_blur;
wire [23:0]rgb_in;
wire [23:0]rgb_pass;
wire vsync_in;
wire \NLW_A[0]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[0]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[0]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[1]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[1]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[1]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[2]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[2]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[2]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[3]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[3]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[3]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[4]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[4]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[4]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[5]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[5]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[5]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[6]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[6]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[6]__5_srl29_Q31_UNCONNECTED ;
wire \NLW_A[7]__15_srl29_Q31_UNCONNECTED ;
wire \NLW_A[7]__25_srl29_Q31_UNCONNECTED ;
wire \NLW_A[7]__5_srl29_Q31_UNCONNECTED ;
assign hsync_out = \<const0> ;
assign vsync_out = \<const0> ;
FDRE \A[0]__14
(.C(clk_25),
.CE(active),
.D(\A[0]__16_n_0 ),
.Q(\A[0]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[0]__15_srl29 " *)
SRLC32E \A[0]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_33),
.Q(\A[0]__15_srl29_n_0 ),
.Q31(\NLW_A[0]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[0]__16
(.C(clk_25),
.CE(active),
.D(\A[0]__15_srl29_n_0 ),
.Q(\A[0]__16_n_0 ),
.R(1'b0));
FDRE \A[0]__18
(.C(clk_25),
.CE(active),
.D(\C[0]__1_n_0 ),
.Q(\A[0]__18_n_0 ),
.R(1'b0));
FDRE \A[0]__24
(.C(clk_25),
.CE(active),
.D(\A[0]__26_n_0 ),
.Q(\A[0]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[0]__25_srl29 " *)
SRLC32E \A[0]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_41),
.Q(\A[0]__25_srl29_n_0 ),
.Q31(\NLW_A[0]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[0]__26
(.C(clk_25),
.CE(active),
.D(\A[0]__25_srl29_n_0 ),
.Q(\A[0]__26_n_0 ),
.R(1'b0));
FDRE \A[0]__28
(.C(clk_25),
.CE(active),
.D(\C[0]__3_n_0 ),
.Q(\A[0]__28_n_0 ),
.R(1'b0));
FDRE \A[0]__4
(.C(clk_25),
.CE(active),
.D(\A[0]__6_n_0 ),
.Q(\A[0]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[0]__5_srl29 " *)
SRLC32E \A[0]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_25),
.Q(\A[0]__5_srl29_n_0 ),
.Q31(\NLW_A[0]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[0]__6
(.C(clk_25),
.CE(active),
.D(\A[0]__5_srl29_n_0 ),
.Q(\A[0]__6_n_0 ),
.R(1'b0));
FDRE \A[0]__8
(.C(clk_25),
.CE(active),
.D(C[0]),
.Q(\A[0]__8_n_0 ),
.R(1'b0));
FDRE \A[1]__14
(.C(clk_25),
.CE(active),
.D(\A[1]__16_n_0 ),
.Q(\A[1]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[1]__15_srl29 " *)
SRLC32E \A[1]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_34),
.Q(\A[1]__15_srl29_n_0 ),
.Q31(\NLW_A[1]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[1]__16
(.C(clk_25),
.CE(active),
.D(\A[1]__15_srl29_n_0 ),
.Q(\A[1]__16_n_0 ),
.R(1'b0));
FDRE \A[1]__18
(.C(clk_25),
.CE(active),
.D(\C[1]__1_n_0 ),
.Q(\A[1]__18_n_0 ),
.R(1'b0));
FDRE \A[1]__24
(.C(clk_25),
.CE(active),
.D(\A[1]__26_n_0 ),
.Q(\A[1]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[1]__25_srl29 " *)
SRLC32E \A[1]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_42),
.Q(\A[1]__25_srl29_n_0 ),
.Q31(\NLW_A[1]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[1]__26
(.C(clk_25),
.CE(active),
.D(\A[1]__25_srl29_n_0 ),
.Q(\A[1]__26_n_0 ),
.R(1'b0));
FDRE \A[1]__28
(.C(clk_25),
.CE(active),
.D(\C[1]__3_n_0 ),
.Q(\A[1]__28_n_0 ),
.R(1'b0));
FDRE \A[1]__4
(.C(clk_25),
.CE(active),
.D(\A[1]__6_n_0 ),
.Q(\A[1]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[1]__5_srl29 " *)
SRLC32E \A[1]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_26),
.Q(\A[1]__5_srl29_n_0 ),
.Q31(\NLW_A[1]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[1]__6
(.C(clk_25),
.CE(active),
.D(\A[1]__5_srl29_n_0 ),
.Q(\A[1]__6_n_0 ),
.R(1'b0));
FDRE \A[1]__8
(.C(clk_25),
.CE(active),
.D(C[1]),
.Q(\A[1]__8_n_0 ),
.R(1'b0));
FDRE \A[2]__14
(.C(clk_25),
.CE(active),
.D(\A[2]__16_n_0 ),
.Q(\A[2]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[2]__15_srl29 " *)
SRLC32E \A[2]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_35),
.Q(\A[2]__15_srl29_n_0 ),
.Q31(\NLW_A[2]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[2]__16
(.C(clk_25),
.CE(active),
.D(\A[2]__15_srl29_n_0 ),
.Q(\A[2]__16_n_0 ),
.R(1'b0));
FDRE \A[2]__18
(.C(clk_25),
.CE(active),
.D(\C[2]__1_n_0 ),
.Q(\A[2]__18_n_0 ),
.R(1'b0));
FDRE \A[2]__24
(.C(clk_25),
.CE(active),
.D(\A[2]__26_n_0 ),
.Q(\A[2]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[2]__25_srl29 " *)
SRLC32E \A[2]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_43),
.Q(\A[2]__25_srl29_n_0 ),
.Q31(\NLW_A[2]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[2]__26
(.C(clk_25),
.CE(active),
.D(\A[2]__25_srl29_n_0 ),
.Q(\A[2]__26_n_0 ),
.R(1'b0));
FDRE \A[2]__28
(.C(clk_25),
.CE(active),
.D(\C[2]__3_n_0 ),
.Q(\A[2]__28_n_0 ),
.R(1'b0));
FDRE \A[2]__4
(.C(clk_25),
.CE(active),
.D(\A[2]__6_n_0 ),
.Q(\A[2]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[2]__5_srl29 " *)
SRLC32E \A[2]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_27),
.Q(\A[2]__5_srl29_n_0 ),
.Q31(\NLW_A[2]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[2]__6
(.C(clk_25),
.CE(active),
.D(\A[2]__5_srl29_n_0 ),
.Q(\A[2]__6_n_0 ),
.R(1'b0));
FDRE \A[2]__8
(.C(clk_25),
.CE(active),
.D(C[2]),
.Q(\A[2]__8_n_0 ),
.R(1'b0));
FDRE \A[3]__14
(.C(clk_25),
.CE(active),
.D(\A[3]__16_n_0 ),
.Q(\A[3]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[3]__15_srl29 " *)
SRLC32E \A[3]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_36),
.Q(\A[3]__15_srl29_n_0 ),
.Q31(\NLW_A[3]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[3]__16
(.C(clk_25),
.CE(active),
.D(\A[3]__15_srl29_n_0 ),
.Q(\A[3]__16_n_0 ),
.R(1'b0));
FDRE \A[3]__18
(.C(clk_25),
.CE(active),
.D(\C[3]__1_n_0 ),
.Q(\A[3]__18_n_0 ),
.R(1'b0));
FDRE \A[3]__24
(.C(clk_25),
.CE(active),
.D(\A[3]__26_n_0 ),
.Q(\A[3]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[3]__25_srl29 " *)
SRLC32E \A[3]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_44),
.Q(\A[3]__25_srl29_n_0 ),
.Q31(\NLW_A[3]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[3]__26
(.C(clk_25),
.CE(active),
.D(\A[3]__25_srl29_n_0 ),
.Q(\A[3]__26_n_0 ),
.R(1'b0));
FDRE \A[3]__28
(.C(clk_25),
.CE(active),
.D(\C[3]__3_n_0 ),
.Q(\A[3]__28_n_0 ),
.R(1'b0));
FDRE \A[3]__4
(.C(clk_25),
.CE(active),
.D(\A[3]__6_n_0 ),
.Q(\A[3]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[3]__5_srl29 " *)
SRLC32E \A[3]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_28),
.Q(\A[3]__5_srl29_n_0 ),
.Q31(\NLW_A[3]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[3]__6
(.C(clk_25),
.CE(active),
.D(\A[3]__5_srl29_n_0 ),
.Q(\A[3]__6_n_0 ),
.R(1'b0));
FDRE \A[3]__8
(.C(clk_25),
.CE(active),
.D(C[3]),
.Q(\A[3]__8_n_0 ),
.R(1'b0));
FDRE \A[4]__14
(.C(clk_25),
.CE(active),
.D(\A[4]__16_n_0 ),
.Q(\A[4]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[4]__15_srl29 " *)
SRLC32E \A[4]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_37),
.Q(\A[4]__15_srl29_n_0 ),
.Q31(\NLW_A[4]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[4]__16
(.C(clk_25),
.CE(active),
.D(\A[4]__15_srl29_n_0 ),
.Q(\A[4]__16_n_0 ),
.R(1'b0));
FDRE \A[4]__18
(.C(clk_25),
.CE(active),
.D(\C[4]__1_n_0 ),
.Q(\A[4]__18_n_0 ),
.R(1'b0));
FDRE \A[4]__24
(.C(clk_25),
.CE(active),
.D(\A[4]__26_n_0 ),
.Q(\A[4]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[4]__25_srl29 " *)
SRLC32E \A[4]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_45),
.Q(\A[4]__25_srl29_n_0 ),
.Q31(\NLW_A[4]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[4]__26
(.C(clk_25),
.CE(active),
.D(\A[4]__25_srl29_n_0 ),
.Q(\A[4]__26_n_0 ),
.R(1'b0));
FDRE \A[4]__28
(.C(clk_25),
.CE(active),
.D(\C[4]__3_n_0 ),
.Q(\A[4]__28_n_0 ),
.R(1'b0));
FDRE \A[4]__4
(.C(clk_25),
.CE(active),
.D(\A[4]__6_n_0 ),
.Q(\A[4]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[4]__5_srl29 " *)
SRLC32E \A[4]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_29),
.Q(\A[4]__5_srl29_n_0 ),
.Q31(\NLW_A[4]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[4]__6
(.C(clk_25),
.CE(active),
.D(\A[4]__5_srl29_n_0 ),
.Q(\A[4]__6_n_0 ),
.R(1'b0));
FDRE \A[4]__8
(.C(clk_25),
.CE(active),
.D(C[4]),
.Q(\A[4]__8_n_0 ),
.R(1'b0));
FDRE \A[5]__14
(.C(clk_25),
.CE(active),
.D(\A[5]__16_n_0 ),
.Q(\A[5]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[5]__15_srl29 " *)
SRLC32E \A[5]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_38),
.Q(\A[5]__15_srl29_n_0 ),
.Q31(\NLW_A[5]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[5]__16
(.C(clk_25),
.CE(active),
.D(\A[5]__15_srl29_n_0 ),
.Q(\A[5]__16_n_0 ),
.R(1'b0));
FDRE \A[5]__18
(.C(clk_25),
.CE(active),
.D(\C[5]__1_n_0 ),
.Q(\A[5]__18_n_0 ),
.R(1'b0));
FDRE \A[5]__24
(.C(clk_25),
.CE(active),
.D(\A[5]__26_n_0 ),
.Q(\A[5]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[5]__25_srl29 " *)
SRLC32E \A[5]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_46),
.Q(\A[5]__25_srl29_n_0 ),
.Q31(\NLW_A[5]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[5]__26
(.C(clk_25),
.CE(active),
.D(\A[5]__25_srl29_n_0 ),
.Q(\A[5]__26_n_0 ),
.R(1'b0));
FDRE \A[5]__28
(.C(clk_25),
.CE(active),
.D(\C[5]__3_n_0 ),
.Q(\A[5]__28_n_0 ),
.R(1'b0));
FDRE \A[5]__4
(.C(clk_25),
.CE(active),
.D(\A[5]__6_n_0 ),
.Q(\A[5]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[5]__5_srl29 " *)
SRLC32E \A[5]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_30),
.Q(\A[5]__5_srl29_n_0 ),
.Q31(\NLW_A[5]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[5]__6
(.C(clk_25),
.CE(active),
.D(\A[5]__5_srl29_n_0 ),
.Q(\A[5]__6_n_0 ),
.R(1'b0));
FDRE \A[5]__8
(.C(clk_25),
.CE(active),
.D(C[5]),
.Q(\A[5]__8_n_0 ),
.R(1'b0));
FDRE \A[6]__14
(.C(clk_25),
.CE(active),
.D(\A[6]__16_n_0 ),
.Q(\A[6]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[6]__15_srl29 " *)
SRLC32E \A[6]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_39),
.Q(\A[6]__15_srl29_n_0 ),
.Q31(\NLW_A[6]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[6]__16
(.C(clk_25),
.CE(active),
.D(\A[6]__15_srl29_n_0 ),
.Q(\A[6]__16_n_0 ),
.R(1'b0));
FDRE \A[6]__18
(.C(clk_25),
.CE(active),
.D(\C[6]__1_n_0 ),
.Q(\A[6]__18_n_0 ),
.R(1'b0));
FDRE \A[6]__24
(.C(clk_25),
.CE(active),
.D(\A[6]__26_n_0 ),
.Q(\A[6]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[6]__25_srl29 " *)
SRLC32E \A[6]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_47),
.Q(\A[6]__25_srl29_n_0 ),
.Q31(\NLW_A[6]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[6]__26
(.C(clk_25),
.CE(active),
.D(\A[6]__25_srl29_n_0 ),
.Q(\A[6]__26_n_0 ),
.R(1'b0));
FDRE \A[6]__28
(.C(clk_25),
.CE(active),
.D(\C[6]__3_n_0 ),
.Q(\A[6]__28_n_0 ),
.R(1'b0));
FDRE \A[6]__4
(.C(clk_25),
.CE(active),
.D(\A[6]__6_n_0 ),
.Q(\A[6]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[6]__5_srl29 " *)
SRLC32E \A[6]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_31),
.Q(\A[6]__5_srl29_n_0 ),
.Q31(\NLW_A[6]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[6]__6
(.C(clk_25),
.CE(active),
.D(\A[6]__5_srl29_n_0 ),
.Q(\A[6]__6_n_0 ),
.R(1'b0));
FDRE \A[6]__8
(.C(clk_25),
.CE(active),
.D(C[6]),
.Q(\A[6]__8_n_0 ),
.R(1'b0));
FDRE \A[7]__14
(.C(clk_25),
.CE(active),
.D(\A[7]__16_n_0 ),
.Q(\A[7]__14_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[7]__15_srl29 " *)
SRLC32E \A[7]__15_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_40),
.Q(\A[7]__15_srl29_n_0 ),
.Q31(\NLW_A[7]__15_srl29_Q31_UNCONNECTED ));
FDRE \A[7]__16
(.C(clk_25),
.CE(active),
.D(\A[7]__15_srl29_n_0 ),
.Q(\A[7]__16_n_0 ),
.R(1'b0));
FDRE \A[7]__18
(.C(clk_25),
.CE(active),
.D(\C[7]__1_n_0 ),
.Q(\A[7]__18_n_0 ),
.R(1'b0));
FDRE \A[7]__24
(.C(clk_25),
.CE(active),
.D(\A[7]__26_n_0 ),
.Q(\A[7]__24_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[7]__25_srl29 " *)
SRLC32E \A[7]__25_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_48),
.Q(\A[7]__25_srl29_n_0 ),
.Q31(\NLW_A[7]__25_srl29_Q31_UNCONNECTED ));
FDRE \A[7]__26
(.C(clk_25),
.CE(active),
.D(\A[7]__25_srl29_n_0 ),
.Q(\A[7]__26_n_0 ),
.R(1'b0));
FDRE \A[7]__28
(.C(clk_25),
.CE(active),
.D(\C[7]__3_n_0 ),
.Q(\A[7]__28_n_0 ),
.R(1'b0));
FDRE \A[7]__4
(.C(clk_25),
.CE(active),
.D(\A[7]__6_n_0 ),
.Q(\A[7]__4_n_0 ),
.R(1'b0));
(* srl_bus_name = "\A " *)
(* srl_name = "\A[7]__5_srl29 " *)
SRLC32E \A[7]__5_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(U0_n_32),
.Q(\A[7]__5_srl29_n_0 ),
.Q31(\NLW_A[7]__5_srl29_Q31_UNCONNECTED ));
FDRE \A[7]__6
(.C(clk_25),
.CE(active),
.D(\A[7]__5_srl29_n_0 ),
.Q(\A[7]__6_n_0 ),
.R(1'b0));
FDRE \A[7]__8
(.C(clk_25),
.CE(active),
.D(C[7]),
.Q(\A[7]__8_n_0 ),
.R(1'b0));
FDRE \B[0]
(.C(clk_25),
.CE(active),
.D(\A[0]__8_n_0 ),
.Q(\B_n_0_[0] ),
.R(1'b0));
FDRE \B[0]__0
(.C(clk_25),
.CE(active),
.D(\C[0]__0_n_0 ),
.Q(B[0]),
.R(1'b0));
FDRE \B[0]__1
(.C(clk_25),
.CE(active),
.D(B[0]),
.Q(\B[0]__1_n_0 ),
.R(1'b0));
FDRE \B[0]__3
(.C(clk_25),
.CE(active),
.D(\A[0]__18_n_0 ),
.Q(\B[0]__3_n_0 ),
.R(1'b0));
FDRE \B[0]__4
(.C(clk_25),
.CE(active),
.D(\C[0]__2_n_0 ),
.Q(\B[0]__4_n_0 ),
.R(1'b0));
FDRE \B[0]__5
(.C(clk_25),
.CE(active),
.D(\B[0]__4_n_0 ),
.Q(\B[0]__5_n_0 ),
.R(1'b0));
FDRE \B[0]__7
(.C(clk_25),
.CE(active),
.D(\A[0]__28_n_0 ),
.Q(\B[0]__7_n_0 ),
.R(1'b0));
FDRE \B[0]__8
(.C(clk_25),
.CE(active),
.D(\C[0]__4_n_0 ),
.Q(\B[0]__8_n_0 ),
.R(1'b0));
FDRE \B[0]__9
(.C(clk_25),
.CE(active),
.D(\B[0]__8_n_0 ),
.Q(\B[0]__9_n_0 ),
.R(1'b0));
FDRE \B[1]__0
(.C(clk_25),
.CE(active),
.D(\A[1]__8_n_0 ),
.Q(\B[1]__0_n_0 ),
.R(1'b0));
FDRE \B[1]__1
(.C(clk_25),
.CE(active),
.D(\C[1]__0_n_0 ),
.Q(B[1]),
.R(1'b0));
FDRE \B[1]__10
(.C(clk_25),
.CE(active),
.D(\B[1]__9_n_0 ),
.Q(\B[1]__10_n_0 ),
.R(1'b0));
FDRE \B[1]__2
(.C(clk_25),
.CE(active),
.D(B[1]),
.Q(\B[1]__2_n_0 ),
.R(1'b0));
FDRE \B[1]__4
(.C(clk_25),
.CE(active),
.D(\A[1]__18_n_0 ),
.Q(\B[1]__4_n_0 ),
.R(1'b0));
FDRE \B[1]__5
(.C(clk_25),
.CE(active),
.D(\C[1]__2_n_0 ),
.Q(\B[1]__5_n_0 ),
.R(1'b0));
FDRE \B[1]__6
(.C(clk_25),
.CE(active),
.D(\B[1]__5_n_0 ),
.Q(\B[1]__6_n_0 ),
.R(1'b0));
FDRE \B[1]__8
(.C(clk_25),
.CE(active),
.D(\A[1]__28_n_0 ),
.Q(\B[1]__8_n_0 ),
.R(1'b0));
FDRE \B[1]__9
(.C(clk_25),
.CE(active),
.D(\C[1]__4_n_0 ),
.Q(\B[1]__9_n_0 ),
.R(1'b0));
FDRE \B[2]__0
(.C(clk_25),
.CE(active),
.D(\A[2]__8_n_0 ),
.Q(\B[2]__0_n_0 ),
.R(1'b0));
FDRE \B[2]__1
(.C(clk_25),
.CE(active),
.D(\C[2]__0_n_0 ),
.Q(B[2]),
.R(1'b0));
FDRE \B[2]__10
(.C(clk_25),
.CE(active),
.D(\B[2]__9_n_0 ),
.Q(\B[2]__10_n_0 ),
.R(1'b0));
FDRE \B[2]__2
(.C(clk_25),
.CE(active),
.D(B[2]),
.Q(\B[2]__2_n_0 ),
.R(1'b0));
FDRE \B[2]__4
(.C(clk_25),
.CE(active),
.D(\A[2]__18_n_0 ),
.Q(\B[2]__4_n_0 ),
.R(1'b0));
FDRE \B[2]__5
(.C(clk_25),
.CE(active),
.D(\C[2]__2_n_0 ),
.Q(\B[2]__5_n_0 ),
.R(1'b0));
FDRE \B[2]__6
(.C(clk_25),
.CE(active),
.D(\B[2]__5_n_0 ),
.Q(\B[2]__6_n_0 ),
.R(1'b0));
FDRE \B[2]__8
(.C(clk_25),
.CE(active),
.D(\A[2]__28_n_0 ),
.Q(\B[2]__8_n_0 ),
.R(1'b0));
FDRE \B[2]__9
(.C(clk_25),
.CE(active),
.D(\C[2]__4_n_0 ),
.Q(\B[2]__9_n_0 ),
.R(1'b0));
FDRE \B[3]__0
(.C(clk_25),
.CE(active),
.D(\A[3]__8_n_0 ),
.Q(\B[3]__0_n_0 ),
.R(1'b0));
FDRE \B[3]__1
(.C(clk_25),
.CE(active),
.D(\C[3]__0_n_0 ),
.Q(B[3]),
.R(1'b0));
FDRE \B[3]__10
(.C(clk_25),
.CE(active),
.D(\B[3]__9_n_0 ),
.Q(\B[3]__10_n_0 ),
.R(1'b0));
FDRE \B[3]__2
(.C(clk_25),
.CE(active),
.D(B[3]),
.Q(\B[3]__2_n_0 ),
.R(1'b0));
FDRE \B[3]__4
(.C(clk_25),
.CE(active),
.D(\A[3]__18_n_0 ),
.Q(\B[3]__4_n_0 ),
.R(1'b0));
FDRE \B[3]__5
(.C(clk_25),
.CE(active),
.D(\C[3]__2_n_0 ),
.Q(\B[3]__5_n_0 ),
.R(1'b0));
FDRE \B[3]__6
(.C(clk_25),
.CE(active),
.D(\B[3]__5_n_0 ),
.Q(\B[3]__6_n_0 ),
.R(1'b0));
FDRE \B[3]__8
(.C(clk_25),
.CE(active),
.D(\A[3]__28_n_0 ),
.Q(\B[3]__8_n_0 ),
.R(1'b0));
FDRE \B[3]__9
(.C(clk_25),
.CE(active),
.D(\C[3]__4_n_0 ),
.Q(\B[3]__9_n_0 ),
.R(1'b0));
FDRE \B[4]__0
(.C(clk_25),
.CE(active),
.D(\A[4]__8_n_0 ),
.Q(\B[4]__0_n_0 ),
.R(1'b0));
FDRE \B[4]__1
(.C(clk_25),
.CE(active),
.D(\C[4]__0_n_0 ),
.Q(B[4]),
.R(1'b0));
FDRE \B[4]__10
(.C(clk_25),
.CE(active),
.D(\B[4]__9_n_0 ),
.Q(\B[4]__10_n_0 ),
.R(1'b0));
FDRE \B[4]__2
(.C(clk_25),
.CE(active),
.D(B[4]),
.Q(\B[4]__2_n_0 ),
.R(1'b0));
FDRE \B[4]__4
(.C(clk_25),
.CE(active),
.D(\A[4]__18_n_0 ),
.Q(\B[4]__4_n_0 ),
.R(1'b0));
FDRE \B[4]__5
(.C(clk_25),
.CE(active),
.D(\C[4]__2_n_0 ),
.Q(\B[4]__5_n_0 ),
.R(1'b0));
FDRE \B[4]__6
(.C(clk_25),
.CE(active),
.D(\B[4]__5_n_0 ),
.Q(\B[4]__6_n_0 ),
.R(1'b0));
FDRE \B[4]__8
(.C(clk_25),
.CE(active),
.D(\A[4]__28_n_0 ),
.Q(\B[4]__8_n_0 ),
.R(1'b0));
FDRE \B[4]__9
(.C(clk_25),
.CE(active),
.D(\C[4]__4_n_0 ),
.Q(\B[4]__9_n_0 ),
.R(1'b0));
FDRE \B[5]__0
(.C(clk_25),
.CE(active),
.D(\A[5]__8_n_0 ),
.Q(\B[5]__0_n_0 ),
.R(1'b0));
FDRE \B[5]__1
(.C(clk_25),
.CE(active),
.D(\C[5]__0_n_0 ),
.Q(B[5]),
.R(1'b0));
FDRE \B[5]__10
(.C(clk_25),
.CE(active),
.D(\B[5]__9_n_0 ),
.Q(\B[5]__10_n_0 ),
.R(1'b0));
FDRE \B[5]__2
(.C(clk_25),
.CE(active),
.D(B[5]),
.Q(\B[5]__2_n_0 ),
.R(1'b0));
FDRE \B[5]__4
(.C(clk_25),
.CE(active),
.D(\A[5]__18_n_0 ),
.Q(\B[5]__4_n_0 ),
.R(1'b0));
FDRE \B[5]__5
(.C(clk_25),
.CE(active),
.D(\C[5]__2_n_0 ),
.Q(\B[5]__5_n_0 ),
.R(1'b0));
FDRE \B[5]__6
(.C(clk_25),
.CE(active),
.D(\B[5]__5_n_0 ),
.Q(\B[5]__6_n_0 ),
.R(1'b0));
FDRE \B[5]__8
(.C(clk_25),
.CE(active),
.D(\A[5]__28_n_0 ),
.Q(\B[5]__8_n_0 ),
.R(1'b0));
FDRE \B[5]__9
(.C(clk_25),
.CE(active),
.D(\C[5]__4_n_0 ),
.Q(\B[5]__9_n_0 ),
.R(1'b0));
FDRE \B[6]__0
(.C(clk_25),
.CE(active),
.D(\A[6]__8_n_0 ),
.Q(\B[6]__0_n_0 ),
.R(1'b0));
FDRE \B[6]__1
(.C(clk_25),
.CE(active),
.D(\C[6]__0_n_0 ),
.Q(B[6]),
.R(1'b0));
FDRE \B[6]__10
(.C(clk_25),
.CE(active),
.D(\B[6]__9_n_0 ),
.Q(\B[6]__10_n_0 ),
.R(1'b0));
FDRE \B[6]__2
(.C(clk_25),
.CE(active),
.D(B[6]),
.Q(\B[6]__2_n_0 ),
.R(1'b0));
FDRE \B[6]__4
(.C(clk_25),
.CE(active),
.D(\A[6]__18_n_0 ),
.Q(\B[6]__4_n_0 ),
.R(1'b0));
FDRE \B[6]__5
(.C(clk_25),
.CE(active),
.D(\C[6]__2_n_0 ),
.Q(\B[6]__5_n_0 ),
.R(1'b0));
FDRE \B[6]__6
(.C(clk_25),
.CE(active),
.D(\B[6]__5_n_0 ),
.Q(\B[6]__6_n_0 ),
.R(1'b0));
FDRE \B[6]__8
(.C(clk_25),
.CE(active),
.D(\A[6]__28_n_0 ),
.Q(\B[6]__8_n_0 ),
.R(1'b0));
FDRE \B[6]__9
(.C(clk_25),
.CE(active),
.D(\C[6]__4_n_0 ),
.Q(\B[6]__9_n_0 ),
.R(1'b0));
FDRE \B[7]__0
(.C(clk_25),
.CE(active),
.D(\A[7]__8_n_0 ),
.Q(\B[7]__0_n_0 ),
.R(1'b0));
FDRE \B[7]__1
(.C(clk_25),
.CE(active),
.D(\C[7]__0_n_0 ),
.Q(B[7]),
.R(1'b0));
FDRE \B[7]__10
(.C(clk_25),
.CE(active),
.D(\B[7]__9_n_0 ),
.Q(\B[7]__10_n_0 ),
.R(1'b0));
FDRE \B[7]__2
(.C(clk_25),
.CE(active),
.D(B[7]),
.Q(\B[7]__2_n_0 ),
.R(1'b0));
FDRE \B[7]__4
(.C(clk_25),
.CE(active),
.D(\A[7]__18_n_0 ),
.Q(\B[7]__4_n_0 ),
.R(1'b0));
FDRE \B[7]__5
(.C(clk_25),
.CE(active),
.D(\C[7]__2_n_0 ),
.Q(\B[7]__5_n_0 ),
.R(1'b0));
FDRE \B[7]__6
(.C(clk_25),
.CE(active),
.D(\B[7]__5_n_0 ),
.Q(\B[7]__6_n_0 ),
.R(1'b0));
FDRE \B[7]__8
(.C(clk_25),
.CE(active),
.D(\A[7]__28_n_0 ),
.Q(\B[7]__8_n_0 ),
.R(1'b0));
FDRE \B[7]__9
(.C(clk_25),
.CE(active),
.D(\C[7]__4_n_0 ),
.Q(\B[7]__9_n_0 ),
.R(1'b0));
FDRE \C[0]
(.C(clk_25),
.CE(active),
.D(rgb_in[0]),
.Q(C[0]),
.R(1'b0));
FDRE \C[0]__0
(.C(clk_25),
.CE(active),
.D(U0_n_1),
.Q(\C[0]__0_n_0 ),
.R(1'b0));
FDRE \C[0]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[8]),
.Q(\C[0]__1_n_0 ),
.R(1'b0));
FDRE \C[0]__2
(.C(clk_25),
.CE(active),
.D(U0_n_9),
.Q(\C[0]__2_n_0 ),
.R(1'b0));
FDRE \C[0]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[16]),
.Q(\C[0]__3_n_0 ),
.R(1'b0));
FDRE \C[0]__4
(.C(clk_25),
.CE(active),
.D(U0_n_17),
.Q(\C[0]__4_n_0 ),
.R(1'b0));
FDRE \C[1]
(.C(clk_25),
.CE(active),
.D(rgb_in[1]),
.Q(C[1]),
.R(1'b0));
FDRE \C[1]__0
(.C(clk_25),
.CE(active),
.D(U0_n_2),
.Q(\C[1]__0_n_0 ),
.R(1'b0));
FDRE \C[1]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[9]),
.Q(\C[1]__1_n_0 ),
.R(1'b0));
FDRE \C[1]__2
(.C(clk_25),
.CE(active),
.D(U0_n_10),
.Q(\C[1]__2_n_0 ),
.R(1'b0));
FDRE \C[1]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[17]),
.Q(\C[1]__3_n_0 ),
.R(1'b0));
FDRE \C[1]__4
(.C(clk_25),
.CE(active),
.D(U0_n_18),
.Q(\C[1]__4_n_0 ),
.R(1'b0));
FDRE \C[2]
(.C(clk_25),
.CE(active),
.D(rgb_in[2]),
.Q(C[2]),
.R(1'b0));
FDRE \C[2]__0
(.C(clk_25),
.CE(active),
.D(U0_n_3),
.Q(\C[2]__0_n_0 ),
.R(1'b0));
FDRE \C[2]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[10]),
.Q(\C[2]__1_n_0 ),
.R(1'b0));
FDRE \C[2]__2
(.C(clk_25),
.CE(active),
.D(U0_n_11),
.Q(\C[2]__2_n_0 ),
.R(1'b0));
FDRE \C[2]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[18]),
.Q(\C[2]__3_n_0 ),
.R(1'b0));
FDRE \C[2]__4
(.C(clk_25),
.CE(active),
.D(U0_n_19),
.Q(\C[2]__4_n_0 ),
.R(1'b0));
FDRE \C[3]
(.C(clk_25),
.CE(active),
.D(rgb_in[3]),
.Q(C[3]),
.R(1'b0));
FDRE \C[3]__0
(.C(clk_25),
.CE(active),
.D(U0_n_4),
.Q(\C[3]__0_n_0 ),
.R(1'b0));
FDRE \C[3]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[11]),
.Q(\C[3]__1_n_0 ),
.R(1'b0));
FDRE \C[3]__2
(.C(clk_25),
.CE(active),
.D(U0_n_12),
.Q(\C[3]__2_n_0 ),
.R(1'b0));
FDRE \C[3]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[19]),
.Q(\C[3]__3_n_0 ),
.R(1'b0));
FDRE \C[3]__4
(.C(clk_25),
.CE(active),
.D(U0_n_20),
.Q(\C[3]__4_n_0 ),
.R(1'b0));
FDRE \C[4]
(.C(clk_25),
.CE(active),
.D(rgb_in[4]),
.Q(C[4]),
.R(1'b0));
FDRE \C[4]__0
(.C(clk_25),
.CE(active),
.D(U0_n_5),
.Q(\C[4]__0_n_0 ),
.R(1'b0));
FDRE \C[4]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[12]),
.Q(\C[4]__1_n_0 ),
.R(1'b0));
FDRE \C[4]__2
(.C(clk_25),
.CE(active),
.D(U0_n_13),
.Q(\C[4]__2_n_0 ),
.R(1'b0));
FDRE \C[4]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[20]),
.Q(\C[4]__3_n_0 ),
.R(1'b0));
FDRE \C[4]__4
(.C(clk_25),
.CE(active),
.D(U0_n_21),
.Q(\C[4]__4_n_0 ),
.R(1'b0));
FDRE \C[5]
(.C(clk_25),
.CE(active),
.D(rgb_in[5]),
.Q(C[5]),
.R(1'b0));
FDRE \C[5]__0
(.C(clk_25),
.CE(active),
.D(U0_n_6),
.Q(\C[5]__0_n_0 ),
.R(1'b0));
FDRE \C[5]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[13]),
.Q(\C[5]__1_n_0 ),
.R(1'b0));
FDRE \C[5]__2
(.C(clk_25),
.CE(active),
.D(U0_n_14),
.Q(\C[5]__2_n_0 ),
.R(1'b0));
FDRE \C[5]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[21]),
.Q(\C[5]__3_n_0 ),
.R(1'b0));
FDRE \C[5]__4
(.C(clk_25),
.CE(active),
.D(U0_n_22),
.Q(\C[5]__4_n_0 ),
.R(1'b0));
FDRE \C[6]
(.C(clk_25),
.CE(active),
.D(rgb_in[6]),
.Q(C[6]),
.R(1'b0));
FDRE \C[6]__0
(.C(clk_25),
.CE(active),
.D(U0_n_7),
.Q(\C[6]__0_n_0 ),
.R(1'b0));
FDRE \C[6]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[14]),
.Q(\C[6]__1_n_0 ),
.R(1'b0));
FDRE \C[6]__2
(.C(clk_25),
.CE(active),
.D(U0_n_15),
.Q(\C[6]__2_n_0 ),
.R(1'b0));
FDRE \C[6]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[22]),
.Q(\C[6]__3_n_0 ),
.R(1'b0));
FDRE \C[6]__4
(.C(clk_25),
.CE(active),
.D(U0_n_23),
.Q(\C[6]__4_n_0 ),
.R(1'b0));
FDRE \C[7]
(.C(clk_25),
.CE(active),
.D(rgb_in[7]),
.Q(C[7]),
.R(1'b0));
FDRE \C[7]__0
(.C(clk_25),
.CE(active),
.D(U0_n_8),
.Q(\C[7]__0_n_0 ),
.R(1'b0));
FDRE \C[7]__1
(.C(clk_25),
.CE(active),
.D(rgb_in[15]),
.Q(\C[7]__1_n_0 ),
.R(1'b0));
FDRE \C[7]__2
(.C(clk_25),
.CE(active),
.D(U0_n_16),
.Q(\C[7]__2_n_0 ),
.R(1'b0));
FDRE \C[7]__3
(.C(clk_25),
.CE(active),
.D(rgb_in[23]),
.Q(\C[7]__3_n_0 ),
.R(1'b0));
FDRE \C[7]__4
(.C(clk_25),
.CE(active),
.D(U0_n_24),
.Q(\C[7]__4_n_0 ),
.R(1'b0));
GND GND
(.G(\<const0> ));
system_vga_gaussian_blur_1_0_vga_gaussian_blur U0
(.\A[0]__16 (U0_n_33),
.\A[0]__26 (U0_n_41),
.\A[0]__6 (U0_n_25),
.\A[1]__16 (U0_n_34),
.\A[1]__26 (U0_n_42),
.\A[1]__6 (U0_n_26),
.\A[2]__16 (U0_n_35),
.\A[2]__26 (U0_n_43),
.\A[2]__6 (U0_n_27),
.\A[3]__16 (U0_n_36),
.\A[3]__26 (U0_n_44),
.\A[3]__6 (U0_n_28),
.\A[4]__16 (U0_n_37),
.\A[4]__26 (U0_n_45),
.\A[4]__6 (U0_n_29),
.\A[5]__16 (U0_n_38),
.\A[5]__26 (U0_n_46),
.\A[5]__6 (U0_n_30),
.\A[6]__16 (U0_n_39),
.\A[6]__26 (U0_n_47),
.\A[6]__6 (U0_n_31),
.\A[7]__16 (U0_n_40),
.\A[7]__26 (U0_n_48),
.\A[7]__6 (U0_n_32),
.\B[0] (\B_n_0_[0] ),
.\B[0]__3 (\B[0]__3_n_0 ),
.\B[0]__7 (\B[0]__7_n_0 ),
.\B[1]__0 (\B[1]__0_n_0 ),
.\B[1]__4 (\B[1]__4_n_0 ),
.\B[1]__8 (\B[1]__8_n_0 ),
.\B[2]__0 (\B[2]__0_n_0 ),
.\B[2]__4 (\B[2]__4_n_0 ),
.\B[2]__8 (\B[2]__8_n_0 ),
.\B[3]__0 (\B[3]__0_n_0 ),
.\B[3]__4 (\B[3]__4_n_0 ),
.\B[3]__8 (\B[3]__8_n_0 ),
.\B[4]__0 (\B[4]__0_n_0 ),
.\B[4]__4 (\B[4]__4_n_0 ),
.\B[4]__8 (\B[4]__8_n_0 ),
.\B[5]__0 (\B[5]__0_n_0 ),
.\B[5]__4 (\B[5]__4_n_0 ),
.\B[5]__8 (\B[5]__8_n_0 ),
.\B[6]__0 (\B[6]__0_n_0 ),
.\B[6]__4 (\B[6]__4_n_0 ),
.\B[6]__8 (\B[6]__8_n_0 ),
.\B[7]__0 (\B[7]__0_n_0 ),
.\B[7]__1 (B),
.\B[7]__10 ({\B[7]__10_n_0 ,\B[6]__10_n_0 ,\B[5]__10_n_0 ,\B[4]__10_n_0 ,\B[3]__10_n_0 ,\B[2]__10_n_0 ,\B[1]__10_n_0 ,\B[0]__9_n_0 }),
.\B[7]__4 (\B[7]__4_n_0 ),
.\B[7]__5 ({\B[7]__5_n_0 ,\B[6]__5_n_0 ,\B[5]__5_n_0 ,\B[4]__5_n_0 ,\B[3]__5_n_0 ,\B[2]__5_n_0 ,\B[1]__5_n_0 ,\B[0]__4_n_0 }),
.\B[7]__6 ({\B[7]__6_n_0 ,\B[6]__6_n_0 ,\B[5]__6_n_0 ,\B[4]__6_n_0 ,\B[3]__6_n_0 ,\B[2]__6_n_0 ,\B[1]__6_n_0 ,\B[0]__5_n_0 }),
.\B[7]__8 (\B[7]__8_n_0 ),
.\B[7]__9 ({\B[7]__9_n_0 ,\B[6]__9_n_0 ,\B[5]__9_n_0 ,\B[4]__9_n_0 ,\B[3]__9_n_0 ,\B[2]__9_n_0 ,\B[1]__9_n_0 ,\B[0]__8_n_0 }),
.\C[0]__0 (U0_n_1),
.\C[0]__0_0 (\C[0]__0_n_0 ),
.\C[0]__1 (\C[0]__1_n_0 ),
.\C[0]__2 (U0_n_9),
.\C[0]__2_0 (\C[0]__2_n_0 ),
.\C[0]__3 (\C[0]__3_n_0 ),
.\C[0]__4 (U0_n_17),
.\C[0]__4_0 (\C[0]__4_n_0 ),
.\C[1]__0 (U0_n_2),
.\C[1]__0_0 (\C[1]__0_n_0 ),
.\C[1]__1 (\C[1]__1_n_0 ),
.\C[1]__2 (U0_n_10),
.\C[1]__2_0 (\C[1]__2_n_0 ),
.\C[1]__3 (\C[1]__3_n_0 ),
.\C[1]__4 (U0_n_18),
.\C[1]__4_0 (\C[1]__4_n_0 ),
.\C[2]__0 (U0_n_3),
.\C[2]__0_0 (\C[2]__0_n_0 ),
.\C[2]__1 (\C[2]__1_n_0 ),
.\C[2]__2 (U0_n_11),
.\C[2]__2_0 (\C[2]__2_n_0 ),
.\C[2]__3 (\C[2]__3_n_0 ),
.\C[2]__4 (U0_n_19),
.\C[2]__4_0 (\C[2]__4_n_0 ),
.\C[3]__0 (U0_n_4),
.\C[3]__0_0 (\C[3]__0_n_0 ),
.\C[3]__1 (\C[3]__1_n_0 ),
.\C[3]__2 (U0_n_12),
.\C[3]__2_0 (\C[3]__2_n_0 ),
.\C[3]__3 (\C[3]__3_n_0 ),
.\C[3]__4 (U0_n_20),
.\C[3]__4_0 (\C[3]__4_n_0 ),
.\C[4]__0 (U0_n_5),
.\C[4]__0_0 (\C[4]__0_n_0 ),
.\C[4]__1 (\C[4]__1_n_0 ),
.\C[4]__2 (U0_n_13),
.\C[4]__2_0 (\C[4]__2_n_0 ),
.\C[4]__3 (\C[4]__3_n_0 ),
.\C[4]__4 (U0_n_21),
.\C[4]__4_0 (\C[4]__4_n_0 ),
.\C[5]__0 (U0_n_6),
.\C[5]__0_0 (\C[5]__0_n_0 ),
.\C[5]__1 (\C[5]__1_n_0 ),
.\C[5]__2 (U0_n_14),
.\C[5]__2_0 (\C[5]__2_n_0 ),
.\C[5]__3 (\C[5]__3_n_0 ),
.\C[5]__4 (U0_n_22),
.\C[5]__4_0 (\C[5]__4_n_0 ),
.\C[6]__0 (U0_n_7),
.\C[6]__0_0 (\C[6]__0_n_0 ),
.\C[6]__1 (\C[6]__1_n_0 ),
.\C[6]__2 (U0_n_15),
.\C[6]__2_0 (\C[6]__2_n_0 ),
.\C[6]__3 (\C[6]__3_n_0 ),
.\C[6]__4 (U0_n_23),
.\C[6]__4_0 (\C[6]__4_n_0 ),
.\C[7] (C),
.\C[7]__0 (U0_n_8),
.\C[7]__0_0 (\C[7]__0_n_0 ),
.\C[7]__1 (\C[7]__1_n_0 ),
.\C[7]__2 (U0_n_16),
.\C[7]__2_0 (\C[7]__2_n_0 ),
.\C[7]__3 (\C[7]__3_n_0 ),
.\C[7]__4 (U0_n_24),
.\C[7]__4_0 (\C[7]__4_n_0 ),
.D({\A[7]__24_n_0 ,\A[6]__24_n_0 ,\A[5]__24_n_0 ,\A[4]__24_n_0 ,\A[3]__24_n_0 ,\A[2]__24_n_0 ,\A[1]__24_n_0 ,\A[0]__24_n_0 ,\A[7]__14_n_0 ,\A[6]__14_n_0 ,\A[5]__14_n_0 ,\A[4]__14_n_0 ,\A[3]__14_n_0 ,\A[2]__14_n_0 ,\A[1]__14_n_0 ,\A[0]__14_n_0 ,\A[7]__4_n_0 ,\A[6]__4_n_0 ,\A[5]__4_n_0 ,\A[4]__4_n_0 ,\A[3]__4_n_0 ,\A[2]__4_n_0 ,\A[1]__4_n_0 ,\A[0]__4_n_0 }),
.I12({\A[7]__26_n_0 ,\A[6]__26_n_0 ,\A[5]__26_n_0 ,\A[4]__26_n_0 ,\A[3]__26_n_0 ,\A[2]__26_n_0 ,\A[1]__26_n_0 ,\A[0]__26_n_0 }),
.I13({\A[7]__28_n_0 ,\A[6]__28_n_0 ,\A[5]__28_n_0 ,\A[4]__28_n_0 ,\A[3]__28_n_0 ,\A[2]__28_n_0 ,\A[1]__28_n_0 ,\A[0]__28_n_0 }),
.I6({\A[7]__16_n_0 ,\A[6]__16_n_0 ,\A[5]__16_n_0 ,\A[4]__16_n_0 ,\A[3]__16_n_0 ,\A[2]__16_n_0 ,\A[1]__16_n_0 ,\A[0]__16_n_0 }),
.I7({\A[7]__18_n_0 ,\A[6]__18_n_0 ,\A[5]__18_n_0 ,\A[4]__18_n_0 ,\A[3]__18_n_0 ,\A[2]__18_n_0 ,\A[1]__18_n_0 ,\A[0]__18_n_0 }),
.Q({\B[7]__2_n_0 ,\B[6]__2_n_0 ,\B[5]__2_n_0 ,\B[4]__2_n_0 ,\B[3]__2_n_0 ,\B[2]__2_n_0 ,\B[1]__2_n_0 ,\B[0]__1_n_0 }),
.active(active),
.clk_25(clk_25),
.hsync_in(hsync_in),
.rgb_blur(rgb_blur),
.rgb_blur11({\A[7]__8_n_0 ,\A[6]__8_n_0 ,\A[5]__8_n_0 ,\A[4]__8_n_0 ,\A[3]__8_n_0 ,\A[2]__8_n_0 ,\A[1]__8_n_0 ,\A[0]__8_n_0 }),
.rgb_blur9({\A[7]__6_n_0 ,\A[6]__6_n_0 ,\A[5]__6_n_0 ,\A[4]__6_n_0 ,\A[3]__6_n_0 ,\A[2]__6_n_0 ,\A[1]__6_n_0 ,\A[0]__6_n_0 }),
.rgb_pass(rgb_pass),
.vsync_in(vsync_in));
endmodule
(* ORIG_REF_NAME = "vga_gaussian_blur" *)
module system_vga_gaussian_blur_1_0_vga_gaussian_blur
(active,
\C[0]__0 ,
\C[1]__0 ,
\C[2]__0 ,
\C[3]__0 ,
\C[4]__0 ,
\C[5]__0 ,
\C[6]__0 ,
\C[7]__0 ,
\C[0]__2 ,
\C[1]__2 ,
\C[2]__2 ,
\C[3]__2 ,
\C[4]__2 ,
\C[5]__2 ,
\C[6]__2 ,
\C[7]__2 ,
\C[0]__4 ,
\C[1]__4 ,
\C[2]__4 ,
\C[3]__4 ,
\C[4]__4 ,
\C[5]__4 ,
\C[6]__4 ,
\C[7]__4 ,
\A[0]__6 ,
\A[1]__6 ,
\A[2]__6 ,
\A[3]__6 ,
\A[4]__6 ,
\A[5]__6 ,
\A[6]__6 ,
\A[7]__6 ,
\A[0]__16 ,
\A[1]__16 ,
\A[2]__16 ,
\A[3]__16 ,
\A[4]__16 ,
\A[5]__16 ,
\A[6]__16 ,
\A[7]__16 ,
\A[0]__26 ,
\A[1]__26 ,
\A[2]__26 ,
\A[3]__26 ,
\A[4]__26 ,
\A[5]__26 ,
\A[6]__26 ,
\A[7]__26 ,
rgb_blur,
rgb_pass,
D,
clk_25,
\B[0] ,
\B[1]__0 ,
\B[2]__0 ,
\B[3]__0 ,
\B[4]__0 ,
\B[5]__0 ,
\B[6]__0 ,
\B[7]__0 ,
\B[0]__3 ,
\B[1]__4 ,
\B[2]__4 ,
\B[3]__4 ,
\B[4]__4 ,
\B[5]__4 ,
\B[6]__4 ,
\B[7]__4 ,
\B[0]__7 ,
\B[1]__8 ,
\B[2]__8 ,
\B[3]__8 ,
\B[4]__8 ,
\B[5]__8 ,
\B[6]__8 ,
\B[7]__8 ,
vsync_in,
hsync_in,
rgb_blur9,
rgb_blur11,
I6,
I7,
I12,
I13,
\B[7]__1 ,
Q,
\C[7] ,
\C[7]__0_0 ,
\B[7]__5 ,
\B[7]__6 ,
\C[7]__1 ,
\C[7]__2_0 ,
\B[7]__9 ,
\B[7]__10 ,
\C[7]__3 ,
\C[7]__4_0 ,
\C[0]__0_0 ,
\C[1]__0_0 ,
\C[2]__0_0 ,
\C[3]__0_0 ,
\C[4]__0_0 ,
\C[5]__0_0 ,
\C[6]__0_0 ,
\C[0]__1 ,
\C[1]__1 ,
\C[2]__1 ,
\C[3]__1 ,
\C[4]__1 ,
\C[5]__1 ,
\C[6]__1 ,
\C[0]__2_0 ,
\C[1]__2_0 ,
\C[2]__2_0 ,
\C[3]__2_0 ,
\C[4]__2_0 ,
\C[5]__2_0 ,
\C[6]__2_0 ,
\C[0]__3 ,
\C[1]__3 ,
\C[2]__3 ,
\C[3]__3 ,
\C[4]__3 ,
\C[5]__3 ,
\C[6]__3 ,
\C[0]__4_0 ,
\C[1]__4_0 ,
\C[2]__4_0 ,
\C[3]__4_0 ,
\C[4]__4_0 ,
\C[5]__4_0 ,
\C[6]__4_0 );
output active;
output \C[0]__0 ;
output \C[1]__0 ;
output \C[2]__0 ;
output \C[3]__0 ;
output \C[4]__0 ;
output \C[5]__0 ;
output \C[6]__0 ;
output \C[7]__0 ;
output \C[0]__2 ;
output \C[1]__2 ;
output \C[2]__2 ;
output \C[3]__2 ;
output \C[4]__2 ;
output \C[5]__2 ;
output \C[6]__2 ;
output \C[7]__2 ;
output \C[0]__4 ;
output \C[1]__4 ;
output \C[2]__4 ;
output \C[3]__4 ;
output \C[4]__4 ;
output \C[5]__4 ;
output \C[6]__4 ;
output \C[7]__4 ;
output \A[0]__6 ;
output \A[1]__6 ;
output \A[2]__6 ;
output \A[3]__6 ;
output \A[4]__6 ;
output \A[5]__6 ;
output \A[6]__6 ;
output \A[7]__6 ;
output \A[0]__16 ;
output \A[1]__16 ;
output \A[2]__16 ;
output \A[3]__16 ;
output \A[4]__16 ;
output \A[5]__16 ;
output \A[6]__16 ;
output \A[7]__16 ;
output \A[0]__26 ;
output \A[1]__26 ;
output \A[2]__26 ;
output \A[3]__26 ;
output \A[4]__26 ;
output \A[5]__26 ;
output \A[6]__26 ;
output \A[7]__26 ;
output [23:0]rgb_blur;
output [23:0]rgb_pass;
input [23:0]D;
input clk_25;
input \B[0] ;
input \B[1]__0 ;
input \B[2]__0 ;
input \B[3]__0 ;
input \B[4]__0 ;
input \B[5]__0 ;
input \B[6]__0 ;
input \B[7]__0 ;
input \B[0]__3 ;
input \B[1]__4 ;
input \B[2]__4 ;
input \B[3]__4 ;
input \B[4]__4 ;
input \B[5]__4 ;
input \B[6]__4 ;
input \B[7]__4 ;
input \B[0]__7 ;
input \B[1]__8 ;
input \B[2]__8 ;
input \B[3]__8 ;
input \B[4]__8 ;
input \B[5]__8 ;
input \B[6]__8 ;
input \B[7]__8 ;
input vsync_in;
input hsync_in;
input [7:0]rgb_blur9;
input [7:0]rgb_blur11;
input [7:0]I6;
input [7:0]I7;
input [7:0]I12;
input [7:0]I13;
input [7:0]\B[7]__1 ;
input [7:0]Q;
input [7:0]\C[7] ;
input \C[7]__0_0 ;
input [7:0]\B[7]__5 ;
input [7:0]\B[7]__6 ;
input \C[7]__1 ;
input \C[7]__2_0 ;
input [7:0]\B[7]__9 ;
input [7:0]\B[7]__10 ;
input \C[7]__3 ;
input \C[7]__4_0 ;
input \C[0]__0_0 ;
input \C[1]__0_0 ;
input \C[2]__0_0 ;
input \C[3]__0_0 ;
input \C[4]__0_0 ;
input \C[5]__0_0 ;
input \C[6]__0_0 ;
input \C[0]__1 ;
input \C[1]__1 ;
input \C[2]__1 ;
input \C[3]__1 ;
input \C[4]__1 ;
input \C[5]__1 ;
input \C[6]__1 ;
input \C[0]__2_0 ;
input \C[1]__2_0 ;
input \C[2]__2_0 ;
input \C[3]__2_0 ;
input \C[4]__2_0 ;
input \C[5]__2_0 ;
input \C[6]__2_0 ;
input \C[0]__3 ;
input \C[1]__3 ;
input \C[2]__3 ;
input \C[3]__3 ;
input \C[4]__3 ;
input \C[5]__3 ;
input \C[6]__3 ;
input \C[0]__4_0 ;
input \C[1]__4_0 ;
input \C[2]__4_0 ;
input \C[3]__4_0 ;
input \C[4]__4_0 ;
input \C[5]__4_0 ;
input \C[6]__4_0 ;
wire \A[0]__16 ;
wire \A[0]__26 ;
wire \A[0]__6 ;
wire \A[1]__16 ;
wire \A[1]__26 ;
wire \A[1]__6 ;
wire \A[2]__16 ;
wire \A[2]__26 ;
wire \A[2]__6 ;
wire \A[3]__16 ;
wire \A[3]__26 ;
wire \A[3]__6 ;
wire \A[4]__16 ;
wire \A[4]__26 ;
wire \A[4]__6 ;
wire \A[5]__16 ;
wire \A[5]__26 ;
wire \A[5]__6 ;
wire \A[6]__16 ;
wire \A[6]__26 ;
wire \A[6]__6 ;
wire \A[7]__16 ;
wire \A[7]__26 ;
wire \A[7]__6 ;
wire \B[0] ;
wire \B[0]__3 ;
wire \B[0]__7 ;
wire \B[1]__0 ;
wire \B[1]__4 ;
wire \B[1]__8 ;
wire \B[2]__0 ;
wire \B[2]__4 ;
wire \B[2]__8 ;
wire \B[3]__0 ;
wire \B[3]__4 ;
wire \B[3]__8 ;
wire \B[4]__0 ;
wire \B[4]__4 ;
wire \B[4]__8 ;
wire \B[5]__0 ;
wire \B[5]__4 ;
wire \B[5]__8 ;
wire \B[6]__0 ;
wire \B[6]__4 ;
wire \B[6]__8 ;
wire \B[7]__0 ;
wire [7:0]\B[7]__1 ;
wire [7:0]\B[7]__10 ;
wire \B[7]__4 ;
wire [7:0]\B[7]__5 ;
wire [7:0]\B[7]__6 ;
wire \B[7]__8 ;
wire [7:0]\B[7]__9 ;
wire [11:1]C;
wire \C[0]__0 ;
wire \C[0]__0_0 ;
wire \C[0]__1 ;
wire \C[0]__2 ;
wire \C[0]__2_0 ;
wire \C[0]__3 ;
wire \C[0]__4 ;
wire \C[0]__4_0 ;
wire \C[1]__0 ;
wire \C[1]__0_0 ;
wire \C[1]__1 ;
wire \C[1]__2 ;
wire \C[1]__2_0 ;
wire \C[1]__3 ;
wire \C[1]__4 ;
wire \C[1]__4_0 ;
wire \C[2]__0 ;
wire \C[2]__0_0 ;
wire \C[2]__1 ;
wire \C[2]__2 ;
wire \C[2]__2_0 ;
wire \C[2]__3 ;
wire \C[2]__4 ;
wire \C[2]__4_0 ;
wire \C[3]__0 ;
wire \C[3]__0_0 ;
wire \C[3]__1 ;
wire \C[3]__2 ;
wire \C[3]__2_0 ;
wire \C[3]__3 ;
wire \C[3]__4 ;
wire \C[3]__4_0 ;
wire \C[4]__0 ;
wire \C[4]__0_0 ;
wire \C[4]__1 ;
wire \C[4]__2 ;
wire \C[4]__2_0 ;
wire \C[4]__3 ;
wire \C[4]__4 ;
wire \C[4]__4_0 ;
wire \C[5]__0 ;
wire \C[5]__0_0 ;
wire \C[5]__1 ;
wire \C[5]__2 ;
wire \C[5]__2_0 ;
wire \C[5]__3 ;
wire \C[5]__4 ;
wire \C[5]__4_0 ;
wire \C[6]__0 ;
wire \C[6]__0_0 ;
wire \C[6]__1 ;
wire \C[6]__2 ;
wire \C[6]__2_0 ;
wire \C[6]__3 ;
wire \C[6]__4 ;
wire \C[6]__4_0 ;
wire [7:0]\C[7] ;
wire \C[7]__0 ;
wire \C[7]__0_0 ;
wire \C[7]__1 ;
wire \C[7]__2 ;
wire \C[7]__2_0 ;
wire \C[7]__3 ;
wire \C[7]__4 ;
wire \C[7]__4_0 ;
wire [11:1]C__0;
wire [11:1]C__1;
wire [23:0]D;
wire [7:0]I12;
wire [7:0]I13;
wire [7:0]I6;
wire [7:0]I7;
wire [31:0]PCIN;
wire [7:0]Q;
wire active;
wire clk_25;
wire hsync_in;
wire i___0_carry__0_i_1__0_n_0;
wire i___0_carry__0_i_1__1_n_0;
wire i___0_carry__0_i_1__2_n_0;
wire i___0_carry__0_i_1__3_n_0;
wire i___0_carry__0_i_1__4_n_0;
wire i___0_carry__0_i_1_n_0;
wire i___0_carry__0_i_2__0_n_0;
wire i___0_carry__0_i_2__1_n_0;
wire i___0_carry__0_i_2__2_n_0;
wire i___0_carry__0_i_2__3_n_0;
wire i___0_carry__0_i_2__4_n_0;
wire i___0_carry__0_i_2_n_0;
wire i___0_carry__0_i_3__0_n_0;
wire i___0_carry__0_i_3__1_n_0;
wire i___0_carry__0_i_3__2_n_0;
wire i___0_carry__0_i_3__3_n_0;
wire i___0_carry__0_i_3__4_n_0;
wire i___0_carry__0_i_3_n_0;
wire i___0_carry__0_i_4__0_n_0;
wire i___0_carry__0_i_4__1_n_0;
wire i___0_carry__0_i_4__2_n_0;
wire i___0_carry__0_i_4__3_n_0;
wire i___0_carry__0_i_4__4_n_0;
wire i___0_carry__0_i_4_n_0;
wire i___0_carry__0_i_5__0_n_0;
wire i___0_carry__0_i_5__1_n_0;
wire i___0_carry__0_i_5__2_n_0;
wire i___0_carry__0_i_5__3_n_0;
wire i___0_carry__0_i_5__4_n_0;
wire i___0_carry__0_i_5_n_0;
wire i___0_carry__0_i_6__0_n_0;
wire i___0_carry__0_i_6__1_n_0;
wire i___0_carry__0_i_6__2_n_0;
wire i___0_carry__0_i_6__3_n_0;
wire i___0_carry__0_i_6__4_n_0;
wire i___0_carry__0_i_6_n_0;
wire i___0_carry__0_i_7__0_n_0;
wire i___0_carry__0_i_7__1_n_0;
wire i___0_carry__0_i_7__2_n_0;
wire i___0_carry__0_i_7__3_n_0;
wire i___0_carry__0_i_7__4_n_0;
wire i___0_carry__0_i_7_n_0;
wire i___0_carry__0_i_8__0_n_0;
wire i___0_carry__0_i_8__1_n_0;
wire i___0_carry__0_i_8__2_n_0;
wire i___0_carry__0_i_8__3_n_0;
wire i___0_carry__0_i_8__4_n_0;
wire i___0_carry__0_i_8_n_0;
wire i___0_carry__1_i_1__0_n_0;
wire i___0_carry__1_i_1__1_n_0;
wire i___0_carry__1_i_1__2_n_0;
wire i___0_carry__1_i_1__3_n_0;
wire i___0_carry__1_i_1__4_n_0;
wire i___0_carry__1_i_1_n_0;
wire i___0_carry__1_i_2__0_n_0;
wire i___0_carry__1_i_2__1_n_0;
wire i___0_carry__1_i_2__2_n_0;
wire i___0_carry__1_i_2__3_n_0;
wire i___0_carry__1_i_2__4_n_0;
wire i___0_carry__1_i_2_n_0;
wire i___0_carry__1_i_3__0_n_0;
wire i___0_carry__1_i_3__1_n_0;
wire i___0_carry__1_i_3__2_n_0;
wire i___0_carry__1_i_3__3_n_0;
wire i___0_carry__1_i_3__4_n_0;
wire i___0_carry__1_i_3_n_0;
wire i___0_carry__1_i_4__0_n_0;
wire i___0_carry__1_i_4__1_n_0;
wire i___0_carry__1_i_4__2_n_0;
wire i___0_carry__1_i_4__3_n_0;
wire i___0_carry__1_i_4__4_n_0;
wire i___0_carry__1_i_4_n_0;
wire i___0_carry__2_i_1__0_n_0;
wire i___0_carry__2_i_1__1_n_0;
wire i___0_carry__2_i_1__2_n_0;
wire i___0_carry__2_i_1__3_n_0;
wire i___0_carry__2_i_1__4_n_0;
wire i___0_carry__2_i_1_n_0;
wire i___0_carry__2_i_2__0_n_0;
wire i___0_carry__2_i_2__1_n_0;
wire i___0_carry__2_i_2__2_n_0;
wire i___0_carry__2_i_2__3_n_0;
wire i___0_carry__2_i_2__4_n_0;
wire i___0_carry__2_i_2_n_0;
wire i___0_carry__2_i_3__0_n_0;
wire i___0_carry__2_i_3__1_n_0;
wire i___0_carry__2_i_3_n_0;
wire i___0_carry__2_i_4__0_n_0;
wire i___0_carry__2_i_4__1_n_0;
wire i___0_carry__2_i_4_n_0;
wire i___0_carry__3_i_1__0_n_0;
wire i___0_carry__3_i_1__1_n_0;
wire i___0_carry__3_i_1_n_0;
wire i___0_carry__3_i_2__0_n_0;
wire i___0_carry__3_i_2__1_n_0;
wire i___0_carry__3_i_2_n_0;
wire i___0_carry__3_i_3__0_n_0;
wire i___0_carry__3_i_3__1_n_0;
wire i___0_carry__3_i_3_n_0;
wire i___0_carry__3_i_4__0_n_0;
wire i___0_carry__3_i_4__1_n_0;
wire i___0_carry__3_i_4_n_0;
wire i___0_carry__4_i_1__0_n_0;
wire i___0_carry__4_i_1__1_n_0;
wire i___0_carry__4_i_1_n_0;
wire i___0_carry__4_i_2__0_n_0;
wire i___0_carry__4_i_2__1_n_0;
wire i___0_carry__4_i_2_n_0;
wire i___0_carry__4_i_3__0_n_0;
wire i___0_carry__4_i_3__1_n_0;
wire i___0_carry__4_i_3_n_0;
wire i___0_carry__4_i_4__0_n_0;
wire i___0_carry__4_i_4__1_n_0;
wire i___0_carry__4_i_4_n_0;
wire i___0_carry__5_i_1__0_n_0;
wire i___0_carry__5_i_1__1_n_0;
wire i___0_carry__5_i_1_n_0;
wire i___0_carry__5_i_2__0_n_0;
wire i___0_carry__5_i_2__1_n_0;
wire i___0_carry__5_i_2_n_0;
wire i___0_carry__5_i_3__0_n_0;
wire i___0_carry__5_i_3__1_n_0;
wire i___0_carry__5_i_3_n_0;
wire i___0_carry__5_i_4__0_n_0;
wire i___0_carry__5_i_4__1_n_0;
wire i___0_carry__5_i_4_n_0;
wire i___0_carry__6_i_1__0_n_0;
wire i___0_carry__6_i_1__1_n_0;
wire i___0_carry__6_i_1_n_0;
wire i___0_carry__6_i_2__0_n_0;
wire i___0_carry__6_i_2__1_n_0;
wire i___0_carry__6_i_2_n_0;
wire i___0_carry__6_i_3__0_n_0;
wire i___0_carry__6_i_3__1_n_0;
wire i___0_carry__6_i_3_n_0;
wire i___0_carry__6_i_4__0_n_0;
wire i___0_carry__6_i_4__1_n_0;
wire i___0_carry__6_i_4_n_0;
wire i___0_carry_i_1__0_n_0;
wire i___0_carry_i_1__1_n_0;
wire i___0_carry_i_1__2_n_0;
wire i___0_carry_i_1__3_n_0;
wire i___0_carry_i_1__4_n_0;
wire i___0_carry_i_1_n_0;
wire i___0_carry_i_2__0_n_0;
wire i___0_carry_i_2__1_n_0;
wire i___0_carry_i_2__2_n_0;
wire i___0_carry_i_2__3_n_0;
wire i___0_carry_i_2__4_n_0;
wire i___0_carry_i_2_n_0;
wire i___0_carry_i_3__0_n_0;
wire i___0_carry_i_3__1_n_0;
wire i___0_carry_i_3__2_n_0;
wire i___0_carry_i_3__3_n_0;
wire i___0_carry_i_3__4_n_0;
wire i___0_carry_i_3_n_0;
wire i___0_carry_i_4__0_n_0;
wire i___0_carry_i_4__1_n_0;
wire i___0_carry_i_4__2_n_0;
wire i___0_carry_i_4__3_n_0;
wire i___0_carry_i_4__4_n_0;
wire i___0_carry_i_4_n_0;
wire i___0_carry_i_5__0_n_0;
wire i___0_carry_i_5__1_n_0;
wire i___0_carry_i_5__2_n_0;
wire i___0_carry_i_5__3_n_0;
wire i___0_carry_i_5__4_n_0;
wire i___0_carry_i_5_n_0;
wire i___0_carry_i_6__0_n_0;
wire i___0_carry_i_6__1_n_0;
wire i___0_carry_i_6__2_n_0;
wire i___0_carry_i_6__3_n_0;
wire i___0_carry_i_6__4_n_0;
wire i___0_carry_i_6_n_0;
wire i___0_carry_i_7__0_n_0;
wire i___0_carry_i_7__1_n_0;
wire i___0_carry_i_7__2_n_0;
wire i___0_carry_i_7__3_n_0;
wire i___0_carry_i_7__4_n_0;
wire i___0_carry_i_7_n_0;
wire i___24_carry__0_i_1__0_n_0;
wire i___24_carry__0_i_1_n_0;
wire i___24_carry__0_i_2__0_n_0;
wire i___24_carry__0_i_2_n_0;
wire i___24_carry__0_i_3__0_n_0;
wire i___24_carry__0_i_3_n_0;
wire i___24_carry__0_i_4__0_n_0;
wire i___24_carry__0_i_4_n_0;
wire i___24_carry__1_i_1__0_n_0;
wire i___24_carry__1_i_1_n_0;
wire i___24_carry_i_1__0_n_0;
wire i___24_carry_i_1_n_0;
wire i___24_carry_i_2__0_n_0;
wire i___24_carry_i_2_n_0;
wire i___24_carry_i_3__0_n_0;
wire i___24_carry_i_3_n_0;
wire i___24_carry_i_4__0_n_0;
wire i___24_carry_i_4_n_0;
wire i___50_carry__0_i_1__0_n_0;
wire i___50_carry__0_i_1_n_0;
wire i___50_carry__0_i_2__0_n_0;
wire i___50_carry__0_i_2_n_0;
wire i___50_carry__0_i_3__0_n_0;
wire i___50_carry__0_i_3_n_0;
wire i___50_carry__0_i_4__0_n_0;
wire i___50_carry__0_i_4_n_0;
wire i___50_carry__1_i_1__0_n_0;
wire i___50_carry__1_i_1_n_0;
wire i___50_carry__1_i_2__0_n_0;
wire i___50_carry__1_i_2_n_0;
wire i___50_carry__1_i_3__0_n_0;
wire i___50_carry__1_i_3_n_0;
wire i___50_carry__1_i_4__0_n_0;
wire i___50_carry__1_i_4_n_0;
wire i___50_carry__1_i_5__0_n_0;
wire i___50_carry__1_i_5_n_0;
wire i___50_carry_i_1__0_n_0;
wire i___50_carry_i_1_n_0;
wire i___50_carry_i_2__0_n_0;
wire i___50_carry_i_2_n_0;
wire i___50_carry_i_3__0_n_0;
wire i___50_carry_i_3_n_0;
wire i___82_carry__0_i_1__0_n_0;
wire i___82_carry__0_i_1_n_0;
wire i___82_carry__0_i_2__0_n_0;
wire i___82_carry__0_i_2_n_0;
wire i___82_carry__0_i_3__0_n_0;
wire i___82_carry__0_i_3_n_0;
wire i___82_carry__0_i_4__0_n_0;
wire i___82_carry__0_i_4_n_0;
wire i___82_carry__1_i_1__0_n_0;
wire i___82_carry__1_i_1_n_0;
wire i___82_carry__1_i_2__0_n_0;
wire i___82_carry__1_i_2_n_0;
wire i___82_carry__1_i_3__0_n_0;
wire i___82_carry__1_i_3_n_0;
wire i___82_carry__1_i_4__0_n_0;
wire i___82_carry__1_i_4_n_0;
wire i___82_carry__1_i_5__0_n_0;
wire i___82_carry__1_i_5_n_0;
wire i___82_carry__2_i_1__0_n_0;
wire i___82_carry__2_i_1_n_0;
wire i___82_carry__2_i_2__0_n_3;
wire i___82_carry__2_i_2_n_3;
wire i___82_carry_i_1__0_n_0;
wire i___82_carry_i_1_n_0;
wire i___82_carry_i_2__0_n_0;
wire i___82_carry_i_2_n_0;
wire i___82_carry_i_3__0_n_0;
wire i___82_carry_i_3_n_0;
wire i__carry__0_i_1__0_n_0;
wire i__carry__0_i_1__1_n_0;
wire i__carry__0_i_1__2_n_0;
wire i__carry__0_i_1_n_0;
wire i__carry__0_i_2__0_n_0;
wire i__carry__0_i_2__1_n_0;
wire i__carry__0_i_2__2_n_0;
wire i__carry__0_i_2_n_0;
wire i__carry__0_i_3__0_n_0;
wire i__carry__0_i_3__1_n_0;
wire i__carry__0_i_3__2_n_0;
wire i__carry__0_i_3_n_0;
wire i__carry__0_i_4__0_n_0;
wire i__carry__0_i_4__1_n_0;
wire i__carry__0_i_4__2_n_0;
wire i__carry__0_i_4_n_0;
wire i__carry__0_i_5__0_n_0;
wire i__carry__0_i_5_n_0;
wire i__carry__0_i_6__0_n_0;
wire i__carry__0_i_6_n_0;
wire i__carry__0_i_7__0_n_0;
wire i__carry__0_i_7_n_0;
wire i__carry__0_i_8__0_n_0;
wire i__carry__0_i_8_n_0;
wire i__carry__1_i_1__0_n_0;
wire i__carry__1_i_1__1_n_0;
wire i__carry__1_i_1__2_n_0;
wire i__carry__1_i_1_n_0;
wire i__carry__1_i_2__0_n_0;
wire i__carry__1_i_2_n_0;
wire i__carry__1_i_3__0_n_0;
wire i__carry__1_i_3_n_0;
wire i__carry__1_i_4__0_n_0;
wire i__carry__1_i_4_n_0;
wire i__carry__1_i_5__0_n_0;
wire i__carry__1_i_5_n_0;
wire i__carry__1_i_6__0_n_0;
wire i__carry__1_i_6_n_0;
wire i__carry__1_i_7__0_n_0;
wire i__carry__1_i_7_n_0;
wire i__carry__1_i_8__0_n_0;
wire i__carry__1_i_8_n_0;
wire i__carry__2_i_1__0_n_0;
wire i__carry__2_i_1_n_0;
wire i__carry__2_i_2__0_n_0;
wire i__carry__2_i_2_n_0;
wire i__carry__2_i_3__0_n_0;
wire i__carry__2_i_3_n_0;
wire i__carry__2_i_4__0_n_0;
wire i__carry__2_i_4_n_0;
wire i__carry__2_i_5__0_n_0;
wire i__carry__2_i_5_n_0;
wire i__carry__2_i_6__0_n_0;
wire i__carry__2_i_6_n_0;
wire i__carry__2_i_7__0_n_0;
wire i__carry__2_i_7_n_0;
wire i__carry__2_i_8__0_n_0;
wire i__carry__2_i_8_n_0;
wire i__carry_i_1__0_n_0;
wire i__carry_i_1__1_n_0;
wire i__carry_i_1__2_n_0;
wire i__carry_i_1_n_0;
wire i__carry_i_2__0_n_0;
wire i__carry_i_2__1_n_0;
wire i__carry_i_2__2_n_0;
wire i__carry_i_2_n_0;
wire i__carry_i_3__0_n_0;
wire i__carry_i_3__1_n_0;
wire i__carry_i_3__2_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4__0_n_0;
wire i__carry_i_4_n_0;
wire i__carry_i_5__0_n_0;
wire i__carry_i_5_n_0;
wire i__carry_i_6__0_n_0;
wire i__carry_i_6_n_0;
wire i__carry_i_7__0_n_0;
wire i__carry_i_7_n_0;
wire i__carry_i_8__0_n_0;
wire i__carry_i_8_n_0;
wire [11:0]p_0_in;
wire [23:0]p_7_out;
wire [23:0]rgb_blur;
wire [7:0]rgb_blur11;
wire [31:0]rgb_blur3;
wire rgb_blur3__24_carry__0_i_1_n_0;
wire rgb_blur3__24_carry__0_i_2_n_0;
wire rgb_blur3__24_carry__0_i_3_n_0;
wire rgb_blur3__24_carry__0_i_4_n_0;
wire rgb_blur3__24_carry__0_n_0;
wire rgb_blur3__24_carry__0_n_1;
wire rgb_blur3__24_carry__0_n_2;
wire rgb_blur3__24_carry__0_n_3;
wire rgb_blur3__24_carry__0_n_4;
wire rgb_blur3__24_carry__0_n_5;
wire rgb_blur3__24_carry__0_n_6;
wire rgb_blur3__24_carry__0_n_7;
wire rgb_blur3__24_carry__1_i_1_n_0;
wire rgb_blur3__24_carry__1_n_2;
wire rgb_blur3__24_carry__1_n_7;
wire rgb_blur3__24_carry_i_1_n_0;
wire rgb_blur3__24_carry_i_2_n_0;
wire rgb_blur3__24_carry_i_3_n_0;
wire rgb_blur3__24_carry_i_4_n_0;
wire rgb_blur3__24_carry_n_0;
wire rgb_blur3__24_carry_n_1;
wire rgb_blur3__24_carry_n_2;
wire rgb_blur3__24_carry_n_3;
wire rgb_blur3__24_carry_n_4;
wire rgb_blur3__24_carry_n_5;
wire rgb_blur3__24_carry_n_6;
wire rgb_blur3__24_carry_n_7;
wire rgb_blur3__50_carry__0_i_1_n_0;
wire rgb_blur3__50_carry__0_i_2_n_0;
wire rgb_blur3__50_carry__0_i_3_n_0;
wire rgb_blur3__50_carry__0_i_4_n_0;
wire rgb_blur3__50_carry__0_n_0;
wire rgb_blur3__50_carry__0_n_1;
wire rgb_blur3__50_carry__0_n_2;
wire rgb_blur3__50_carry__0_n_3;
wire rgb_blur3__50_carry__1_i_1_n_0;
wire rgb_blur3__50_carry__1_i_2_n_0;
wire rgb_blur3__50_carry__1_i_3_n_0;
wire rgb_blur3__50_carry__1_i_4_n_0;
wire rgb_blur3__50_carry__1_i_5_n_0;
wire rgb_blur3__50_carry__1_n_0;
wire rgb_blur3__50_carry__1_n_1;
wire rgb_blur3__50_carry__1_n_2;
wire rgb_blur3__50_carry__1_n_3;
wire rgb_blur3__50_carry_i_1_n_0;
wire rgb_blur3__50_carry_i_2_n_0;
wire rgb_blur3__50_carry_i_3_n_0;
wire rgb_blur3__50_carry_n_0;
wire rgb_blur3__50_carry_n_1;
wire rgb_blur3__50_carry_n_2;
wire rgb_blur3__50_carry_n_3;
wire rgb_blur3__82_carry__0_i_1_n_0;
wire rgb_blur3__82_carry__0_i_2_n_0;
wire rgb_blur3__82_carry__0_i_3_n_0;
wire rgb_blur3__82_carry__0_i_4_n_0;
wire rgb_blur3__82_carry__0_n_0;
wire rgb_blur3__82_carry__0_n_1;
wire rgb_blur3__82_carry__0_n_2;
wire rgb_blur3__82_carry__0_n_3;
wire rgb_blur3__82_carry__0_n_4;
wire rgb_blur3__82_carry__0_n_5;
wire rgb_blur3__82_carry__0_n_6;
wire rgb_blur3__82_carry__0_n_7;
wire rgb_blur3__82_carry__1_i_1_n_0;
wire rgb_blur3__82_carry__1_i_2_n_0;
wire rgb_blur3__82_carry__1_i_3_n_0;
wire rgb_blur3__82_carry__1_i_4_n_0;
wire rgb_blur3__82_carry__1_i_5_n_0;
wire rgb_blur3__82_carry__1_n_0;
wire rgb_blur3__82_carry__1_n_1;
wire rgb_blur3__82_carry__1_n_2;
wire rgb_blur3__82_carry__1_n_3;
wire rgb_blur3__82_carry__1_n_4;
wire rgb_blur3__82_carry__1_n_5;
wire rgb_blur3__82_carry__1_n_6;
wire rgb_blur3__82_carry__1_n_7;
wire rgb_blur3__82_carry__2_i_1_n_0;
wire rgb_blur3__82_carry__2_i_2_n_3;
wire rgb_blur3__82_carry__2_n_2;
wire rgb_blur3__82_carry__2_n_7;
wire rgb_blur3__82_carry_i_1_n_0;
wire rgb_blur3__82_carry_i_2_n_0;
wire rgb_blur3__82_carry_i_3_n_0;
wire rgb_blur3__82_carry_n_0;
wire rgb_blur3__82_carry_n_1;
wire rgb_blur3__82_carry_n_2;
wire rgb_blur3__82_carry_n_3;
wire rgb_blur3__82_carry_n_4;
wire rgb_blur3__82_carry_n_5;
wire rgb_blur3__82_carry_n_6;
wire rgb_blur3_carry__0_i_1_n_0;
wire rgb_blur3_carry__0_i_2_n_0;
wire rgb_blur3_carry__0_i_3_n_0;
wire rgb_blur3_carry__0_i_4_n_0;
wire rgb_blur3_carry__0_n_0;
wire rgb_blur3_carry__0_n_1;
wire rgb_blur3_carry__0_n_2;
wire rgb_blur3_carry__0_n_3;
wire rgb_blur3_carry__0_n_4;
wire rgb_blur3_carry__0_n_5;
wire rgb_blur3_carry__0_n_6;
wire rgb_blur3_carry__0_n_7;
wire rgb_blur3_carry__1_i_1_n_0;
wire rgb_blur3_carry__1_n_2;
wire rgb_blur3_carry__1_n_7;
wire rgb_blur3_carry_i_1_n_0;
wire rgb_blur3_carry_i_2_n_0;
wire rgb_blur3_carry_i_3_n_0;
wire rgb_blur3_carry_n_0;
wire rgb_blur3_carry_n_1;
wire rgb_blur3_carry_n_2;
wire rgb_blur3_carry_n_3;
wire rgb_blur3_carry_n_4;
wire rgb_blur3_carry_n_5;
wire rgb_blur3_carry_n_6;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_0 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_1 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_2 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_3 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_4 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_5 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_6 ;
wire \rgb_blur3_inferred__0/i___0_carry__0_n_7 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_0 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_1 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_2 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_3 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_4 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_5 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_6 ;
wire \rgb_blur3_inferred__0/i___0_carry__1_n_7 ;
wire \rgb_blur3_inferred__0/i___0_carry__2_n_2 ;
wire \rgb_blur3_inferred__0/i___0_carry__2_n_3 ;
wire \rgb_blur3_inferred__0/i___0_carry__2_n_5 ;
wire \rgb_blur3_inferred__0/i___0_carry__2_n_6 ;
wire \rgb_blur3_inferred__0/i___0_carry__2_n_7 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_0 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_1 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_2 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_3 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_4 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_5 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_6 ;
wire \rgb_blur3_inferred__0/i___0_carry_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__0_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__1_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__2_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__3_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__4_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__5_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry__6_n_7 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_0 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_1 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_2 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_3 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_4 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_5 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_6 ;
wire \rgb_blur3_inferred__1/i___0_carry_n_7 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_0 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_1 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_2 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_3 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_4 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_5 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_6 ;
wire \rgb_blur3_inferred__2/i___24_carry__0_n_7 ;
wire \rgb_blur3_inferred__2/i___24_carry__1_n_2 ;
wire \rgb_blur3_inferred__2/i___24_carry__1_n_7 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_0 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_1 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_2 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_3 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_4 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_5 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_6 ;
wire \rgb_blur3_inferred__2/i___24_carry_n_7 ;
wire \rgb_blur3_inferred__2/i___50_carry__0_n_0 ;
wire \rgb_blur3_inferred__2/i___50_carry__0_n_1 ;
wire \rgb_blur3_inferred__2/i___50_carry__0_n_2 ;
wire \rgb_blur3_inferred__2/i___50_carry__0_n_3 ;
wire \rgb_blur3_inferred__2/i___50_carry__1_n_0 ;
wire \rgb_blur3_inferred__2/i___50_carry__1_n_1 ;
wire \rgb_blur3_inferred__2/i___50_carry__1_n_2 ;
wire \rgb_blur3_inferred__2/i___50_carry__1_n_3 ;
wire \rgb_blur3_inferred__2/i___50_carry_n_0 ;
wire \rgb_blur3_inferred__2/i___50_carry_n_1 ;
wire \rgb_blur3_inferred__2/i___50_carry_n_2 ;
wire \rgb_blur3_inferred__2/i___50_carry_n_3 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_0 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_1 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_2 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_3 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_4 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_5 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_6 ;
wire \rgb_blur3_inferred__2/i___82_carry__0_n_7 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_0 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_1 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_2 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_3 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_4 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_5 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_6 ;
wire \rgb_blur3_inferred__2/i___82_carry__1_n_7 ;
wire \rgb_blur3_inferred__2/i___82_carry__2_n_2 ;
wire \rgb_blur3_inferred__2/i___82_carry__2_n_7 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_0 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_1 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_2 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_3 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_4 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_5 ;
wire \rgb_blur3_inferred__2/i___82_carry_n_6 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_0 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_1 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_2 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_3 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_4 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_5 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_6 ;
wire \rgb_blur3_inferred__2/i__carry__0_n_7 ;
wire \rgb_blur3_inferred__2/i__carry__1_n_2 ;
wire \rgb_blur3_inferred__2/i__carry__1_n_7 ;
wire \rgb_blur3_inferred__2/i__carry_n_0 ;
wire \rgb_blur3_inferred__2/i__carry_n_1 ;
wire \rgb_blur3_inferred__2/i__carry_n_2 ;
wire \rgb_blur3_inferred__2/i__carry_n_3 ;
wire \rgb_blur3_inferred__2/i__carry_n_4 ;
wire \rgb_blur3_inferred__2/i__carry_n_5 ;
wire \rgb_blur3_inferred__2/i__carry_n_6 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_0 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_1 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_2 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_3 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_4 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_5 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_6 ;
wire \rgb_blur3_inferred__3/i___0_carry__0_n_7 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_0 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_1 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_2 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_3 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_4 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_5 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_6 ;
wire \rgb_blur3_inferred__3/i___0_carry__1_n_7 ;
wire \rgb_blur3_inferred__3/i___0_carry__2_n_2 ;
wire \rgb_blur3_inferred__3/i___0_carry__2_n_3 ;
wire \rgb_blur3_inferred__3/i___0_carry__2_n_5 ;
wire \rgb_blur3_inferred__3/i___0_carry__2_n_6 ;
wire \rgb_blur3_inferred__3/i___0_carry__2_n_7 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_0 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_1 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_2 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_3 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_4 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_5 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_6 ;
wire \rgb_blur3_inferred__3/i___0_carry_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__0_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__1_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__2_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__3_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__4_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__5_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry__6_n_7 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_0 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_1 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_2 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_3 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_4 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_5 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_6 ;
wire \rgb_blur3_inferred__4/i___0_carry_n_7 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_0 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_1 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_2 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_3 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_4 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_5 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_6 ;
wire \rgb_blur3_inferred__5/i___24_carry__0_n_7 ;
wire \rgb_blur3_inferred__5/i___24_carry__1_n_2 ;
wire \rgb_blur3_inferred__5/i___24_carry__1_n_7 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_0 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_1 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_2 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_3 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_4 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_5 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_6 ;
wire \rgb_blur3_inferred__5/i___24_carry_n_7 ;
wire \rgb_blur3_inferred__5/i___50_carry__0_n_0 ;
wire \rgb_blur3_inferred__5/i___50_carry__0_n_1 ;
wire \rgb_blur3_inferred__5/i___50_carry__0_n_2 ;
wire \rgb_blur3_inferred__5/i___50_carry__0_n_3 ;
wire \rgb_blur3_inferred__5/i___50_carry__1_n_0 ;
wire \rgb_blur3_inferred__5/i___50_carry__1_n_1 ;
wire \rgb_blur3_inferred__5/i___50_carry__1_n_2 ;
wire \rgb_blur3_inferred__5/i___50_carry__1_n_3 ;
wire \rgb_blur3_inferred__5/i___50_carry_n_0 ;
wire \rgb_blur3_inferred__5/i___50_carry_n_1 ;
wire \rgb_blur3_inferred__5/i___50_carry_n_2 ;
wire \rgb_blur3_inferred__5/i___50_carry_n_3 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_0 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_1 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_2 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_3 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_4 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_5 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_6 ;
wire \rgb_blur3_inferred__5/i___82_carry__0_n_7 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_0 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_1 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_2 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_3 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_4 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_5 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_6 ;
wire \rgb_blur3_inferred__5/i___82_carry__1_n_7 ;
wire \rgb_blur3_inferred__5/i___82_carry__2_n_2 ;
wire \rgb_blur3_inferred__5/i___82_carry__2_n_7 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_0 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_1 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_2 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_3 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_4 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_5 ;
wire \rgb_blur3_inferred__5/i___82_carry_n_6 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_0 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_1 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_2 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_3 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_4 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_5 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_6 ;
wire \rgb_blur3_inferred__5/i__carry__0_n_7 ;
wire \rgb_blur3_inferred__5/i__carry__1_n_2 ;
wire \rgb_blur3_inferred__5/i__carry__1_n_7 ;
wire \rgb_blur3_inferred__5/i__carry_n_0 ;
wire \rgb_blur3_inferred__5/i__carry_n_1 ;
wire \rgb_blur3_inferred__5/i__carry_n_2 ;
wire \rgb_blur3_inferred__5/i__carry_n_3 ;
wire \rgb_blur3_inferred__5/i__carry_n_4 ;
wire \rgb_blur3_inferred__5/i__carry_n_5 ;
wire \rgb_blur3_inferred__5/i__carry_n_6 ;
wire \rgb_blur3_inferred__6/i___0_carry__0_n_0 ;
wire \rgb_blur3_inferred__6/i___0_carry__0_n_1 ;
wire \rgb_blur3_inferred__6/i___0_carry__0_n_2 ;
wire \rgb_blur3_inferred__6/i___0_carry__0_n_3 ;
wire \rgb_blur3_inferred__6/i___0_carry__1_n_0 ;
wire \rgb_blur3_inferred__6/i___0_carry__1_n_1 ;
wire \rgb_blur3_inferred__6/i___0_carry__1_n_2 ;
wire \rgb_blur3_inferred__6/i___0_carry__1_n_3 ;
wire \rgb_blur3_inferred__6/i___0_carry__2_n_2 ;
wire \rgb_blur3_inferred__6/i___0_carry__2_n_3 ;
wire \rgb_blur3_inferred__6/i___0_carry_n_0 ;
wire \rgb_blur3_inferred__6/i___0_carry_n_1 ;
wire \rgb_blur3_inferred__6/i___0_carry_n_2 ;
wire \rgb_blur3_inferred__6/i___0_carry_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__0_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry__0_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__0_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__0_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__1_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry__1_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__1_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__1_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__2_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry__2_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__2_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__2_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__3_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry__3_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__3_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__3_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__4_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry__4_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__4_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__4_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__5_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry__5_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__5_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__5_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry__6_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry__6_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry__6_n_3 ;
wire \rgb_blur3_inferred__7/i___0_carry_n_0 ;
wire \rgb_blur3_inferred__7/i___0_carry_n_1 ;
wire \rgb_blur3_inferred__7/i___0_carry_n_2 ;
wire \rgb_blur3_inferred__7/i___0_carry_n_3 ;
wire rgb_blur4;
wire rgb_blur4_carry__0_i_1_n_0;
wire rgb_blur4_carry__0_i_2_n_0;
wire rgb_blur4_carry__0_i_3_n_0;
wire rgb_blur4_carry__0_i_4_n_0;
wire rgb_blur4_carry__0_i_5_n_0;
wire rgb_blur4_carry__0_i_6_n_0;
wire rgb_blur4_carry__0_i_7_n_0;
wire rgb_blur4_carry__0_i_8_n_0;
wire rgb_blur4_carry__0_n_0;
wire rgb_blur4_carry__0_n_1;
wire rgb_blur4_carry__0_n_2;
wire rgb_blur4_carry__0_n_3;
wire rgb_blur4_carry__1_i_1_n_0;
wire rgb_blur4_carry__1_i_2_n_0;
wire rgb_blur4_carry__1_i_3_n_0;
wire rgb_blur4_carry__1_i_4_n_0;
wire rgb_blur4_carry__1_i_5_n_0;
wire rgb_blur4_carry__1_i_6_n_0;
wire rgb_blur4_carry__1_i_7_n_0;
wire rgb_blur4_carry__1_i_8_n_0;
wire rgb_blur4_carry__1_n_0;
wire rgb_blur4_carry__1_n_1;
wire rgb_blur4_carry__1_n_2;
wire rgb_blur4_carry__1_n_3;
wire rgb_blur4_carry__2_i_1_n_0;
wire rgb_blur4_carry__2_i_2_n_0;
wire rgb_blur4_carry__2_i_3_n_0;
wire rgb_blur4_carry__2_i_4_n_0;
wire rgb_blur4_carry__2_i_5_n_0;
wire rgb_blur4_carry__2_i_6_n_0;
wire rgb_blur4_carry__2_i_7_n_0;
wire rgb_blur4_carry__2_i_8_n_0;
wire rgb_blur4_carry__2_n_0;
wire rgb_blur4_carry__2_n_1;
wire rgb_blur4_carry__2_n_2;
wire rgb_blur4_carry__2_n_3;
wire rgb_blur4_carry_i_1_n_0;
wire rgb_blur4_carry_i_2_n_0;
wire rgb_blur4_carry_i_3_n_0;
wire rgb_blur4_carry_i_4_n_0;
wire rgb_blur4_carry_i_5_n_0;
wire rgb_blur4_carry_i_6_n_0;
wire rgb_blur4_carry_i_7_n_0;
wire rgb_blur4_carry_i_8_n_0;
wire rgb_blur4_carry_n_0;
wire rgb_blur4_carry_n_1;
wire rgb_blur4_carry_n_2;
wire rgb_blur4_carry_n_3;
wire \rgb_blur4_inferred__0/i__carry__0_n_0 ;
wire \rgb_blur4_inferred__0/i__carry__0_n_1 ;
wire \rgb_blur4_inferred__0/i__carry__0_n_2 ;
wire \rgb_blur4_inferred__0/i__carry__0_n_3 ;
wire \rgb_blur4_inferred__0/i__carry__1_n_0 ;
wire \rgb_blur4_inferred__0/i__carry__1_n_1 ;
wire \rgb_blur4_inferred__0/i__carry__1_n_2 ;
wire \rgb_blur4_inferred__0/i__carry__1_n_3 ;
wire \rgb_blur4_inferred__0/i__carry__2_n_0 ;
wire \rgb_blur4_inferred__0/i__carry__2_n_1 ;
wire \rgb_blur4_inferred__0/i__carry__2_n_2 ;
wire \rgb_blur4_inferred__0/i__carry__2_n_3 ;
wire \rgb_blur4_inferred__0/i__carry_n_0 ;
wire \rgb_blur4_inferred__0/i__carry_n_1 ;
wire \rgb_blur4_inferred__0/i__carry_n_2 ;
wire \rgb_blur4_inferred__0/i__carry_n_3 ;
wire \rgb_blur4_inferred__1/i__carry__0_n_0 ;
wire \rgb_blur4_inferred__1/i__carry__0_n_1 ;
wire \rgb_blur4_inferred__1/i__carry__0_n_2 ;
wire \rgb_blur4_inferred__1/i__carry__0_n_3 ;
wire \rgb_blur4_inferred__1/i__carry__1_n_0 ;
wire \rgb_blur4_inferred__1/i__carry__1_n_1 ;
wire \rgb_blur4_inferred__1/i__carry__1_n_2 ;
wire \rgb_blur4_inferred__1/i__carry__1_n_3 ;
wire \rgb_blur4_inferred__1/i__carry__2_n_1 ;
wire \rgb_blur4_inferred__1/i__carry__2_n_2 ;
wire \rgb_blur4_inferred__1/i__carry__2_n_3 ;
wire \rgb_blur4_inferred__1/i__carry_n_0 ;
wire \rgb_blur4_inferred__1/i__carry_n_1 ;
wire \rgb_blur4_inferred__1/i__carry_n_2 ;
wire \rgb_blur4_inferred__1/i__carry_n_3 ;
wire [7:0]rgb_blur9;
wire \rgb_blur[10]_i_2_n_0 ;
wire \rgb_blur[10]_i_3_n_0 ;
wire \rgb_blur[11]_i_2_n_0 ;
wire \rgb_blur[12]_i_2_n_0 ;
wire \rgb_blur[12]_i_3_n_0 ;
wire \rgb_blur[12]_i_5_n_0 ;
wire \rgb_blur[12]_i_6_n_0 ;
wire \rgb_blur[12]_i_7_n_0 ;
wire \rgb_blur[12]_i_8_n_0 ;
wire \rgb_blur[13]_i_2_n_0 ;
wire \rgb_blur[14]_i_2_n_0 ;
wire \rgb_blur[15]_i_2_n_0 ;
wire \rgb_blur[15]_i_4_n_0 ;
wire \rgb_blur[15]_i_5_n_0 ;
wire \rgb_blur[15]_i_6_n_0 ;
wire \rgb_blur[15]_i_7_n_0 ;
wire \rgb_blur[18]_i_2_n_0 ;
wire \rgb_blur[18]_i_3_n_0 ;
wire \rgb_blur[19]_i_2_n_0 ;
wire \rgb_blur[1]_i_3_n_0 ;
wire \rgb_blur[1]_i_4_n_0 ;
wire \rgb_blur[1]_i_5_n_0 ;
wire \rgb_blur[1]_i_6_n_0 ;
wire \rgb_blur[1]_i_7_n_0 ;
wire \rgb_blur[20]_i_2_n_0 ;
wire \rgb_blur[20]_i_3_n_0 ;
wire \rgb_blur[21]_i_2_n_0 ;
wire \rgb_blur[22]_i_2_n_0 ;
wire \rgb_blur[23]_i_1_n_0 ;
wire \rgb_blur[23]_i_3_n_0 ;
wire \rgb_blur[23]_i_5_n_0 ;
wire \rgb_blur[2]_i_2_n_0 ;
wire \rgb_blur[2]_i_3_n_0 ;
wire \rgb_blur[3]_i_2_n_0 ;
wire \rgb_blur[4]_i_2_n_0 ;
wire \rgb_blur[4]_i_3_n_0 ;
wire \rgb_blur[4]_i_5_n_0 ;
wire \rgb_blur[4]_i_6_n_0 ;
wire \rgb_blur[4]_i_7_n_0 ;
wire \rgb_blur[4]_i_8_n_0 ;
wire \rgb_blur[5]_i_2_n_0 ;
wire \rgb_blur[6]_i_2_n_0 ;
wire \rgb_blur[7]_i_2_n_0 ;
wire \rgb_blur[7]_i_4_n_0 ;
wire \rgb_blur[7]_i_5_n_0 ;
wire \rgb_blur[7]_i_6_n_0 ;
wire \rgb_blur[7]_i_7_n_0 ;
wire \rgb_blur[9]_i_3_n_0 ;
wire \rgb_blur[9]_i_4_n_0 ;
wire \rgb_blur[9]_i_5_n_0 ;
wire \rgb_blur[9]_i_6_n_0 ;
wire \rgb_blur[9]_i_7_n_0 ;
wire \rgb_blur_reg[12]_i_4_n_0 ;
wire \rgb_blur_reg[12]_i_4_n_1 ;
wire \rgb_blur_reg[12]_i_4_n_2 ;
wire \rgb_blur_reg[12]_i_4_n_3 ;
wire \rgb_blur_reg[12]_i_4_n_4 ;
wire \rgb_blur_reg[12]_i_4_n_5 ;
wire \rgb_blur_reg[12]_i_4_n_6 ;
wire \rgb_blur_reg[12]_i_4_n_7 ;
wire \rgb_blur_reg[15]_i_3_n_2 ;
wire \rgb_blur_reg[15]_i_3_n_3 ;
wire \rgb_blur_reg[15]_i_3_n_5 ;
wire \rgb_blur_reg[15]_i_3_n_6 ;
wire \rgb_blur_reg[15]_i_3_n_7 ;
wire \rgb_blur_reg[17]_i_2_n_0 ;
wire \rgb_blur_reg[17]_i_2_n_1 ;
wire \rgb_blur_reg[17]_i_2_n_2 ;
wire \rgb_blur_reg[17]_i_2_n_3 ;
wire \rgb_blur_reg[17]_i_2_n_4 ;
wire \rgb_blur_reg[1]_i_2_n_0 ;
wire \rgb_blur_reg[1]_i_2_n_1 ;
wire \rgb_blur_reg[1]_i_2_n_2 ;
wire \rgb_blur_reg[1]_i_2_n_3 ;
wire \rgb_blur_reg[1]_i_2_n_4 ;
wire \rgb_blur_reg[20]_i_4_n_0 ;
wire \rgb_blur_reg[20]_i_4_n_1 ;
wire \rgb_blur_reg[20]_i_4_n_2 ;
wire \rgb_blur_reg[20]_i_4_n_3 ;
wire \rgb_blur_reg[20]_i_4_n_4 ;
wire \rgb_blur_reg[20]_i_4_n_5 ;
wire \rgb_blur_reg[20]_i_4_n_6 ;
wire \rgb_blur_reg[20]_i_4_n_7 ;
wire \rgb_blur_reg[23]_i_4_n_2 ;
wire \rgb_blur_reg[23]_i_4_n_3 ;
wire \rgb_blur_reg[23]_i_4_n_5 ;
wire \rgb_blur_reg[23]_i_4_n_6 ;
wire \rgb_blur_reg[23]_i_4_n_7 ;
wire \rgb_blur_reg[4]_i_4_n_0 ;
wire \rgb_blur_reg[4]_i_4_n_1 ;
wire \rgb_blur_reg[4]_i_4_n_2 ;
wire \rgb_blur_reg[4]_i_4_n_3 ;
wire \rgb_blur_reg[4]_i_4_n_4 ;
wire \rgb_blur_reg[4]_i_4_n_5 ;
wire \rgb_blur_reg[4]_i_4_n_6 ;
wire \rgb_blur_reg[4]_i_4_n_7 ;
wire \rgb_blur_reg[7]_i_3_n_2 ;
wire \rgb_blur_reg[7]_i_3_n_3 ;
wire \rgb_blur_reg[7]_i_3_n_5 ;
wire \rgb_blur_reg[7]_i_3_n_6 ;
wire \rgb_blur_reg[7]_i_3_n_7 ;
wire \rgb_blur_reg[9]_i_2_n_0 ;
wire \rgb_blur_reg[9]_i_2_n_1 ;
wire \rgb_blur_reg[9]_i_2_n_2 ;
wire \rgb_blur_reg[9]_i_2_n_3 ;
wire \rgb_blur_reg[9]_i_2_n_4 ;
wire \rgb_buffer_reg[1026][0]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][10]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][11]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][12]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][13]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][14]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][15]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][16]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][17]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][18]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][19]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][1]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][20]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][21]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][22]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][23]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][2]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][3]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][4]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][5]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][6]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][7]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][8]_srl32_n_0 ;
wire \rgb_buffer_reg[1026][9]_srl32_n_0 ;
wire \rgb_buffer_reg[1058][0]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][10]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][11]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][12]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][13]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][14]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][15]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][16]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][17]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][18]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][19]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][1]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][20]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][21]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][22]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][23]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][2]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][3]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][4]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][5]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][6]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][7]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][8]_srl32_n_1 ;
wire \rgb_buffer_reg[1058][9]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][0]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][10]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][11]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][12]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][13]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][14]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][15]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][16]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][17]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][18]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][19]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][1]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][20]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][21]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][22]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][23]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][2]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][3]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][4]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][5]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][6]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][7]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][8]_srl32_n_1 ;
wire \rgb_buffer_reg[1090][9]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][0]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][10]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][11]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][12]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][13]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][14]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][15]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][16]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][17]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][18]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][19]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][1]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][20]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][21]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][22]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][23]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][2]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][3]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][4]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][5]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][6]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][7]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][8]_srl32_n_1 ;
wire \rgb_buffer_reg[1122][9]_srl32_n_1 ;
wire \rgb_buffer_reg[1154][0]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][10]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][11]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][12]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][13]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][14]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][15]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][16]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][17]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][18]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][19]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][1]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][20]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][21]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][22]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][23]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][2]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][3]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][4]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][5]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][6]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][7]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][8]_srl32_n_0 ;
wire \rgb_buffer_reg[1154][9]_srl32_n_0 ;
wire \rgb_buffer_reg[1186][0]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][10]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][11]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][12]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][13]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][14]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][15]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][16]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][17]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][18]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][19]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][1]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][20]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][21]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][22]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][23]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][2]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][3]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][4]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][5]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][6]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][7]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][8]_srl32_n_1 ;
wire \rgb_buffer_reg[1186][9]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][0]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][10]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][11]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][12]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][13]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][14]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][15]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][16]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][17]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][18]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][19]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][1]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][20]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][21]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][22]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][23]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][2]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][3]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][4]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][5]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][6]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][7]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][8]_srl32_n_1 ;
wire \rgb_buffer_reg[1218][9]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][0]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][10]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][11]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][12]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][13]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][14]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][15]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][16]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][17]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][18]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][19]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][1]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][20]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][21]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][22]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][23]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][2]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][3]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][4]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][5]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][6]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][7]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][8]_srl32_n_1 ;
wire \rgb_buffer_reg[1250][9]_srl32_n_1 ;
wire \rgb_buffer_reg[130][0]_srl32_n_0 ;
wire \rgb_buffer_reg[130][10]_srl32_n_0 ;
wire \rgb_buffer_reg[130][11]_srl32_n_0 ;
wire \rgb_buffer_reg[130][12]_srl32_n_0 ;
wire \rgb_buffer_reg[130][13]_srl32_n_0 ;
wire \rgb_buffer_reg[130][14]_srl32_n_0 ;
wire \rgb_buffer_reg[130][15]_srl32_n_0 ;
wire \rgb_buffer_reg[130][16]_srl32_n_0 ;
wire \rgb_buffer_reg[130][17]_srl32_n_0 ;
wire \rgb_buffer_reg[130][18]_srl32_n_0 ;
wire \rgb_buffer_reg[130][19]_srl32_n_0 ;
wire \rgb_buffer_reg[130][1]_srl32_n_0 ;
wire \rgb_buffer_reg[130][20]_srl32_n_0 ;
wire \rgb_buffer_reg[130][21]_srl32_n_0 ;
wire \rgb_buffer_reg[130][22]_srl32_n_0 ;
wire \rgb_buffer_reg[130][23]_srl32_n_0 ;
wire \rgb_buffer_reg[130][2]_srl32_n_0 ;
wire \rgb_buffer_reg[130][3]_srl32_n_0 ;
wire \rgb_buffer_reg[130][4]_srl32_n_0 ;
wire \rgb_buffer_reg[130][5]_srl32_n_0 ;
wire \rgb_buffer_reg[130][6]_srl32_n_0 ;
wire \rgb_buffer_reg[130][7]_srl32_n_0 ;
wire \rgb_buffer_reg[130][8]_srl32_n_0 ;
wire \rgb_buffer_reg[130][9]_srl32_n_0 ;
wire \rgb_buffer_reg[162][0]_srl32_n_1 ;
wire \rgb_buffer_reg[162][10]_srl32_n_1 ;
wire \rgb_buffer_reg[162][11]_srl32_n_1 ;
wire \rgb_buffer_reg[162][12]_srl32_n_1 ;
wire \rgb_buffer_reg[162][13]_srl32_n_1 ;
wire \rgb_buffer_reg[162][14]_srl32_n_1 ;
wire \rgb_buffer_reg[162][15]_srl32_n_1 ;
wire \rgb_buffer_reg[162][16]_srl32_n_1 ;
wire \rgb_buffer_reg[162][17]_srl32_n_1 ;
wire \rgb_buffer_reg[162][18]_srl32_n_1 ;
wire \rgb_buffer_reg[162][19]_srl32_n_1 ;
wire \rgb_buffer_reg[162][1]_srl32_n_1 ;
wire \rgb_buffer_reg[162][20]_srl32_n_1 ;
wire \rgb_buffer_reg[162][21]_srl32_n_1 ;
wire \rgb_buffer_reg[162][22]_srl32_n_1 ;
wire \rgb_buffer_reg[162][23]_srl32_n_1 ;
wire \rgb_buffer_reg[162][2]_srl32_n_1 ;
wire \rgb_buffer_reg[162][3]_srl32_n_1 ;
wire \rgb_buffer_reg[162][4]_srl32_n_1 ;
wire \rgb_buffer_reg[162][5]_srl32_n_1 ;
wire \rgb_buffer_reg[162][6]_srl32_n_1 ;
wire \rgb_buffer_reg[162][7]_srl32_n_1 ;
wire \rgb_buffer_reg[162][8]_srl32_n_1 ;
wire \rgb_buffer_reg[162][9]_srl32_n_1 ;
wire \rgb_buffer_reg[194][0]_srl32_n_1 ;
wire \rgb_buffer_reg[194][10]_srl32_n_1 ;
wire \rgb_buffer_reg[194][11]_srl32_n_1 ;
wire \rgb_buffer_reg[194][12]_srl32_n_1 ;
wire \rgb_buffer_reg[194][13]_srl32_n_1 ;
wire \rgb_buffer_reg[194][14]_srl32_n_1 ;
wire \rgb_buffer_reg[194][15]_srl32_n_1 ;
wire \rgb_buffer_reg[194][16]_srl32_n_1 ;
wire \rgb_buffer_reg[194][17]_srl32_n_1 ;
wire \rgb_buffer_reg[194][18]_srl32_n_1 ;
wire \rgb_buffer_reg[194][19]_srl32_n_1 ;
wire \rgb_buffer_reg[194][1]_srl32_n_1 ;
wire \rgb_buffer_reg[194][20]_srl32_n_1 ;
wire \rgb_buffer_reg[194][21]_srl32_n_1 ;
wire \rgb_buffer_reg[194][22]_srl32_n_1 ;
wire \rgb_buffer_reg[194][23]_srl32_n_1 ;
wire \rgb_buffer_reg[194][2]_srl32_n_1 ;
wire \rgb_buffer_reg[194][3]_srl32_n_1 ;
wire \rgb_buffer_reg[194][4]_srl32_n_1 ;
wire \rgb_buffer_reg[194][5]_srl32_n_1 ;
wire \rgb_buffer_reg[194][6]_srl32_n_1 ;
wire \rgb_buffer_reg[194][7]_srl32_n_1 ;
wire \rgb_buffer_reg[194][8]_srl32_n_1 ;
wire \rgb_buffer_reg[194][9]_srl32_n_1 ;
wire \rgb_buffer_reg[226][0]_srl32_n_1 ;
wire \rgb_buffer_reg[226][10]_srl32_n_1 ;
wire \rgb_buffer_reg[226][11]_srl32_n_1 ;
wire \rgb_buffer_reg[226][12]_srl32_n_1 ;
wire \rgb_buffer_reg[226][13]_srl32_n_1 ;
wire \rgb_buffer_reg[226][14]_srl32_n_1 ;
wire \rgb_buffer_reg[226][15]_srl32_n_1 ;
wire \rgb_buffer_reg[226][16]_srl32_n_1 ;
wire \rgb_buffer_reg[226][17]_srl32_n_1 ;
wire \rgb_buffer_reg[226][18]_srl32_n_1 ;
wire \rgb_buffer_reg[226][19]_srl32_n_1 ;
wire \rgb_buffer_reg[226][1]_srl32_n_1 ;
wire \rgb_buffer_reg[226][20]_srl32_n_1 ;
wire \rgb_buffer_reg[226][21]_srl32_n_1 ;
wire \rgb_buffer_reg[226][22]_srl32_n_1 ;
wire \rgb_buffer_reg[226][23]_srl32_n_1 ;
wire \rgb_buffer_reg[226][2]_srl32_n_1 ;
wire \rgb_buffer_reg[226][3]_srl32_n_1 ;
wire \rgb_buffer_reg[226][4]_srl32_n_1 ;
wire \rgb_buffer_reg[226][5]_srl32_n_1 ;
wire \rgb_buffer_reg[226][6]_srl32_n_1 ;
wire \rgb_buffer_reg[226][7]_srl32_n_1 ;
wire \rgb_buffer_reg[226][8]_srl32_n_1 ;
wire \rgb_buffer_reg[226][9]_srl32_n_1 ;
wire \rgb_buffer_reg[258][0]_srl32_n_0 ;
wire \rgb_buffer_reg[258][10]_srl32_n_0 ;
wire \rgb_buffer_reg[258][11]_srl32_n_0 ;
wire \rgb_buffer_reg[258][12]_srl32_n_0 ;
wire \rgb_buffer_reg[258][13]_srl32_n_0 ;
wire \rgb_buffer_reg[258][14]_srl32_n_0 ;
wire \rgb_buffer_reg[258][15]_srl32_n_0 ;
wire \rgb_buffer_reg[258][16]_srl32_n_0 ;
wire \rgb_buffer_reg[258][17]_srl32_n_0 ;
wire \rgb_buffer_reg[258][18]_srl32_n_0 ;
wire \rgb_buffer_reg[258][19]_srl32_n_0 ;
wire \rgb_buffer_reg[258][1]_srl32_n_0 ;
wire \rgb_buffer_reg[258][20]_srl32_n_0 ;
wire \rgb_buffer_reg[258][21]_srl32_n_0 ;
wire \rgb_buffer_reg[258][22]_srl32_n_0 ;
wire \rgb_buffer_reg[258][23]_srl32_n_0 ;
wire \rgb_buffer_reg[258][2]_srl32_n_0 ;
wire \rgb_buffer_reg[258][3]_srl32_n_0 ;
wire \rgb_buffer_reg[258][4]_srl32_n_0 ;
wire \rgb_buffer_reg[258][5]_srl32_n_0 ;
wire \rgb_buffer_reg[258][6]_srl32_n_0 ;
wire \rgb_buffer_reg[258][7]_srl32_n_0 ;
wire \rgb_buffer_reg[258][8]_srl32_n_0 ;
wire \rgb_buffer_reg[258][9]_srl32_n_0 ;
wire \rgb_buffer_reg[290][0]_srl32_n_1 ;
wire \rgb_buffer_reg[290][10]_srl32_n_1 ;
wire \rgb_buffer_reg[290][11]_srl32_n_1 ;
wire \rgb_buffer_reg[290][12]_srl32_n_1 ;
wire \rgb_buffer_reg[290][13]_srl32_n_1 ;
wire \rgb_buffer_reg[290][14]_srl32_n_1 ;
wire \rgb_buffer_reg[290][15]_srl32_n_1 ;
wire \rgb_buffer_reg[290][16]_srl32_n_1 ;
wire \rgb_buffer_reg[290][17]_srl32_n_1 ;
wire \rgb_buffer_reg[290][18]_srl32_n_1 ;
wire \rgb_buffer_reg[290][19]_srl32_n_1 ;
wire \rgb_buffer_reg[290][1]_srl32_n_1 ;
wire \rgb_buffer_reg[290][20]_srl32_n_1 ;
wire \rgb_buffer_reg[290][21]_srl32_n_1 ;
wire \rgb_buffer_reg[290][22]_srl32_n_1 ;
wire \rgb_buffer_reg[290][23]_srl32_n_1 ;
wire \rgb_buffer_reg[290][2]_srl32_n_1 ;
wire \rgb_buffer_reg[290][3]_srl32_n_1 ;
wire \rgb_buffer_reg[290][4]_srl32_n_1 ;
wire \rgb_buffer_reg[290][5]_srl32_n_1 ;
wire \rgb_buffer_reg[290][6]_srl32_n_1 ;
wire \rgb_buffer_reg[290][7]_srl32_n_1 ;
wire \rgb_buffer_reg[290][8]_srl32_n_1 ;
wire \rgb_buffer_reg[290][9]_srl32_n_1 ;
wire \rgb_buffer_reg[322][0]_srl32_n_1 ;
wire \rgb_buffer_reg[322][10]_srl32_n_1 ;
wire \rgb_buffer_reg[322][11]_srl32_n_1 ;
wire \rgb_buffer_reg[322][12]_srl32_n_1 ;
wire \rgb_buffer_reg[322][13]_srl32_n_1 ;
wire \rgb_buffer_reg[322][14]_srl32_n_1 ;
wire \rgb_buffer_reg[322][15]_srl32_n_1 ;
wire \rgb_buffer_reg[322][16]_srl32_n_1 ;
wire \rgb_buffer_reg[322][17]_srl32_n_1 ;
wire \rgb_buffer_reg[322][18]_srl32_n_1 ;
wire \rgb_buffer_reg[322][19]_srl32_n_1 ;
wire \rgb_buffer_reg[322][1]_srl32_n_1 ;
wire \rgb_buffer_reg[322][20]_srl32_n_1 ;
wire \rgb_buffer_reg[322][21]_srl32_n_1 ;
wire \rgb_buffer_reg[322][22]_srl32_n_1 ;
wire \rgb_buffer_reg[322][23]_srl32_n_1 ;
wire \rgb_buffer_reg[322][2]_srl32_n_1 ;
wire \rgb_buffer_reg[322][3]_srl32_n_1 ;
wire \rgb_buffer_reg[322][4]_srl32_n_1 ;
wire \rgb_buffer_reg[322][5]_srl32_n_1 ;
wire \rgb_buffer_reg[322][6]_srl32_n_1 ;
wire \rgb_buffer_reg[322][7]_srl32_n_1 ;
wire \rgb_buffer_reg[322][8]_srl32_n_1 ;
wire \rgb_buffer_reg[322][9]_srl32_n_1 ;
wire \rgb_buffer_reg[34][0]_srl32_n_1 ;
wire \rgb_buffer_reg[34][10]_srl32_n_1 ;
wire \rgb_buffer_reg[34][11]_srl32_n_1 ;
wire \rgb_buffer_reg[34][12]_srl32_n_1 ;
wire \rgb_buffer_reg[34][13]_srl32_n_1 ;
wire \rgb_buffer_reg[34][14]_srl32_n_1 ;
wire \rgb_buffer_reg[34][15]_srl32_n_1 ;
wire \rgb_buffer_reg[34][16]_srl32_n_1 ;
wire \rgb_buffer_reg[34][17]_srl32_n_1 ;
wire \rgb_buffer_reg[34][18]_srl32_n_1 ;
wire \rgb_buffer_reg[34][19]_srl32_n_1 ;
wire \rgb_buffer_reg[34][1]_srl32_n_1 ;
wire \rgb_buffer_reg[34][20]_srl32_n_1 ;
wire \rgb_buffer_reg[34][21]_srl32_n_1 ;
wire \rgb_buffer_reg[34][22]_srl32_n_1 ;
wire \rgb_buffer_reg[34][23]_srl32_n_1 ;
wire \rgb_buffer_reg[34][2]_srl32_n_1 ;
wire \rgb_buffer_reg[34][3]_srl32_n_1 ;
wire \rgb_buffer_reg[34][4]_srl32_n_1 ;
wire \rgb_buffer_reg[34][5]_srl32_n_1 ;
wire \rgb_buffer_reg[34][6]_srl32_n_1 ;
wire \rgb_buffer_reg[34][7]_srl32_n_1 ;
wire \rgb_buffer_reg[34][8]_srl32_n_1 ;
wire \rgb_buffer_reg[34][9]_srl32_n_1 ;
wire \rgb_buffer_reg[354][0]_srl32_n_1 ;
wire \rgb_buffer_reg[354][10]_srl32_n_1 ;
wire \rgb_buffer_reg[354][11]_srl32_n_1 ;
wire \rgb_buffer_reg[354][12]_srl32_n_1 ;
wire \rgb_buffer_reg[354][13]_srl32_n_1 ;
wire \rgb_buffer_reg[354][14]_srl32_n_1 ;
wire \rgb_buffer_reg[354][15]_srl32_n_1 ;
wire \rgb_buffer_reg[354][16]_srl32_n_1 ;
wire \rgb_buffer_reg[354][17]_srl32_n_1 ;
wire \rgb_buffer_reg[354][18]_srl32_n_1 ;
wire \rgb_buffer_reg[354][19]_srl32_n_1 ;
wire \rgb_buffer_reg[354][1]_srl32_n_1 ;
wire \rgb_buffer_reg[354][20]_srl32_n_1 ;
wire \rgb_buffer_reg[354][21]_srl32_n_1 ;
wire \rgb_buffer_reg[354][22]_srl32_n_1 ;
wire \rgb_buffer_reg[354][23]_srl32_n_1 ;
wire \rgb_buffer_reg[354][2]_srl32_n_1 ;
wire \rgb_buffer_reg[354][3]_srl32_n_1 ;
wire \rgb_buffer_reg[354][4]_srl32_n_1 ;
wire \rgb_buffer_reg[354][5]_srl32_n_1 ;
wire \rgb_buffer_reg[354][6]_srl32_n_1 ;
wire \rgb_buffer_reg[354][7]_srl32_n_1 ;
wire \rgb_buffer_reg[354][8]_srl32_n_1 ;
wire \rgb_buffer_reg[354][9]_srl32_n_1 ;
wire \rgb_buffer_reg[386][0]_srl32_n_0 ;
wire \rgb_buffer_reg[386][10]_srl32_n_0 ;
wire \rgb_buffer_reg[386][11]_srl32_n_0 ;
wire \rgb_buffer_reg[386][12]_srl32_n_0 ;
wire \rgb_buffer_reg[386][13]_srl32_n_0 ;
wire \rgb_buffer_reg[386][14]_srl32_n_0 ;
wire \rgb_buffer_reg[386][15]_srl32_n_0 ;
wire \rgb_buffer_reg[386][16]_srl32_n_0 ;
wire \rgb_buffer_reg[386][17]_srl32_n_0 ;
wire \rgb_buffer_reg[386][18]_srl32_n_0 ;
wire \rgb_buffer_reg[386][19]_srl32_n_0 ;
wire \rgb_buffer_reg[386][1]_srl32_n_0 ;
wire \rgb_buffer_reg[386][20]_srl32_n_0 ;
wire \rgb_buffer_reg[386][21]_srl32_n_0 ;
wire \rgb_buffer_reg[386][22]_srl32_n_0 ;
wire \rgb_buffer_reg[386][23]_srl32_n_0 ;
wire \rgb_buffer_reg[386][2]_srl32_n_0 ;
wire \rgb_buffer_reg[386][3]_srl32_n_0 ;
wire \rgb_buffer_reg[386][4]_srl32_n_0 ;
wire \rgb_buffer_reg[386][5]_srl32_n_0 ;
wire \rgb_buffer_reg[386][6]_srl32_n_0 ;
wire \rgb_buffer_reg[386][7]_srl32_n_0 ;
wire \rgb_buffer_reg[386][8]_srl32_n_0 ;
wire \rgb_buffer_reg[386][9]_srl32_n_0 ;
wire \rgb_buffer_reg[418][0]_srl32_n_1 ;
wire \rgb_buffer_reg[418][10]_srl32_n_1 ;
wire \rgb_buffer_reg[418][11]_srl32_n_1 ;
wire \rgb_buffer_reg[418][12]_srl32_n_1 ;
wire \rgb_buffer_reg[418][13]_srl32_n_1 ;
wire \rgb_buffer_reg[418][14]_srl32_n_1 ;
wire \rgb_buffer_reg[418][15]_srl32_n_1 ;
wire \rgb_buffer_reg[418][16]_srl32_n_1 ;
wire \rgb_buffer_reg[418][17]_srl32_n_1 ;
wire \rgb_buffer_reg[418][18]_srl32_n_1 ;
wire \rgb_buffer_reg[418][19]_srl32_n_1 ;
wire \rgb_buffer_reg[418][1]_srl32_n_1 ;
wire \rgb_buffer_reg[418][20]_srl32_n_1 ;
wire \rgb_buffer_reg[418][21]_srl32_n_1 ;
wire \rgb_buffer_reg[418][22]_srl32_n_1 ;
wire \rgb_buffer_reg[418][23]_srl32_n_1 ;
wire \rgb_buffer_reg[418][2]_srl32_n_1 ;
wire \rgb_buffer_reg[418][3]_srl32_n_1 ;
wire \rgb_buffer_reg[418][4]_srl32_n_1 ;
wire \rgb_buffer_reg[418][5]_srl32_n_1 ;
wire \rgb_buffer_reg[418][6]_srl32_n_1 ;
wire \rgb_buffer_reg[418][7]_srl32_n_1 ;
wire \rgb_buffer_reg[418][8]_srl32_n_1 ;
wire \rgb_buffer_reg[418][9]_srl32_n_1 ;
wire \rgb_buffer_reg[450][0]_srl32_n_1 ;
wire \rgb_buffer_reg[450][10]_srl32_n_1 ;
wire \rgb_buffer_reg[450][11]_srl32_n_1 ;
wire \rgb_buffer_reg[450][12]_srl32_n_1 ;
wire \rgb_buffer_reg[450][13]_srl32_n_1 ;
wire \rgb_buffer_reg[450][14]_srl32_n_1 ;
wire \rgb_buffer_reg[450][15]_srl32_n_1 ;
wire \rgb_buffer_reg[450][16]_srl32_n_1 ;
wire \rgb_buffer_reg[450][17]_srl32_n_1 ;
wire \rgb_buffer_reg[450][18]_srl32_n_1 ;
wire \rgb_buffer_reg[450][19]_srl32_n_1 ;
wire \rgb_buffer_reg[450][1]_srl32_n_1 ;
wire \rgb_buffer_reg[450][20]_srl32_n_1 ;
wire \rgb_buffer_reg[450][21]_srl32_n_1 ;
wire \rgb_buffer_reg[450][22]_srl32_n_1 ;
wire \rgb_buffer_reg[450][23]_srl32_n_1 ;
wire \rgb_buffer_reg[450][2]_srl32_n_1 ;
wire \rgb_buffer_reg[450][3]_srl32_n_1 ;
wire \rgb_buffer_reg[450][4]_srl32_n_1 ;
wire \rgb_buffer_reg[450][5]_srl32_n_1 ;
wire \rgb_buffer_reg[450][6]_srl32_n_1 ;
wire \rgb_buffer_reg[450][7]_srl32_n_1 ;
wire \rgb_buffer_reg[450][8]_srl32_n_1 ;
wire \rgb_buffer_reg[450][9]_srl32_n_1 ;
wire \rgb_buffer_reg[482][0]_srl32_n_1 ;
wire \rgb_buffer_reg[482][10]_srl32_n_1 ;
wire \rgb_buffer_reg[482][11]_srl32_n_1 ;
wire \rgb_buffer_reg[482][12]_srl32_n_1 ;
wire \rgb_buffer_reg[482][13]_srl32_n_1 ;
wire \rgb_buffer_reg[482][14]_srl32_n_1 ;
wire \rgb_buffer_reg[482][15]_srl32_n_1 ;
wire \rgb_buffer_reg[482][16]_srl32_n_1 ;
wire \rgb_buffer_reg[482][17]_srl32_n_1 ;
wire \rgb_buffer_reg[482][18]_srl32_n_1 ;
wire \rgb_buffer_reg[482][19]_srl32_n_1 ;
wire \rgb_buffer_reg[482][1]_srl32_n_1 ;
wire \rgb_buffer_reg[482][20]_srl32_n_1 ;
wire \rgb_buffer_reg[482][21]_srl32_n_1 ;
wire \rgb_buffer_reg[482][22]_srl32_n_1 ;
wire \rgb_buffer_reg[482][23]_srl32_n_1 ;
wire \rgb_buffer_reg[482][2]_srl32_n_1 ;
wire \rgb_buffer_reg[482][3]_srl32_n_1 ;
wire \rgb_buffer_reg[482][4]_srl32_n_1 ;
wire \rgb_buffer_reg[482][5]_srl32_n_1 ;
wire \rgb_buffer_reg[482][6]_srl32_n_1 ;
wire \rgb_buffer_reg[482][7]_srl32_n_1 ;
wire \rgb_buffer_reg[482][8]_srl32_n_1 ;
wire \rgb_buffer_reg[482][9]_srl32_n_1 ;
wire \rgb_buffer_reg[514][0]_srl32_n_0 ;
wire \rgb_buffer_reg[514][10]_srl32_n_0 ;
wire \rgb_buffer_reg[514][11]_srl32_n_0 ;
wire \rgb_buffer_reg[514][12]_srl32_n_0 ;
wire \rgb_buffer_reg[514][13]_srl32_n_0 ;
wire \rgb_buffer_reg[514][14]_srl32_n_0 ;
wire \rgb_buffer_reg[514][15]_srl32_n_0 ;
wire \rgb_buffer_reg[514][16]_srl32_n_0 ;
wire \rgb_buffer_reg[514][17]_srl32_n_0 ;
wire \rgb_buffer_reg[514][18]_srl32_n_0 ;
wire \rgb_buffer_reg[514][19]_srl32_n_0 ;
wire \rgb_buffer_reg[514][1]_srl32_n_0 ;
wire \rgb_buffer_reg[514][20]_srl32_n_0 ;
wire \rgb_buffer_reg[514][21]_srl32_n_0 ;
wire \rgb_buffer_reg[514][22]_srl32_n_0 ;
wire \rgb_buffer_reg[514][23]_srl32_n_0 ;
wire \rgb_buffer_reg[514][2]_srl32_n_0 ;
wire \rgb_buffer_reg[514][3]_srl32_n_0 ;
wire \rgb_buffer_reg[514][4]_srl32_n_0 ;
wire \rgb_buffer_reg[514][5]_srl32_n_0 ;
wire \rgb_buffer_reg[514][6]_srl32_n_0 ;
wire \rgb_buffer_reg[514][7]_srl32_n_0 ;
wire \rgb_buffer_reg[514][8]_srl32_n_0 ;
wire \rgb_buffer_reg[514][9]_srl32_n_0 ;
wire \rgb_buffer_reg[546][0]_srl32_n_1 ;
wire \rgb_buffer_reg[546][10]_srl32_n_1 ;
wire \rgb_buffer_reg[546][11]_srl32_n_1 ;
wire \rgb_buffer_reg[546][12]_srl32_n_1 ;
wire \rgb_buffer_reg[546][13]_srl32_n_1 ;
wire \rgb_buffer_reg[546][14]_srl32_n_1 ;
wire \rgb_buffer_reg[546][15]_srl32_n_1 ;
wire \rgb_buffer_reg[546][16]_srl32_n_1 ;
wire \rgb_buffer_reg[546][17]_srl32_n_1 ;
wire \rgb_buffer_reg[546][18]_srl32_n_1 ;
wire \rgb_buffer_reg[546][19]_srl32_n_1 ;
wire \rgb_buffer_reg[546][1]_srl32_n_1 ;
wire \rgb_buffer_reg[546][20]_srl32_n_1 ;
wire \rgb_buffer_reg[546][21]_srl32_n_1 ;
wire \rgb_buffer_reg[546][22]_srl32_n_1 ;
wire \rgb_buffer_reg[546][23]_srl32_n_1 ;
wire \rgb_buffer_reg[546][2]_srl32_n_1 ;
wire \rgb_buffer_reg[546][3]_srl32_n_1 ;
wire \rgb_buffer_reg[546][4]_srl32_n_1 ;
wire \rgb_buffer_reg[546][5]_srl32_n_1 ;
wire \rgb_buffer_reg[546][6]_srl32_n_1 ;
wire \rgb_buffer_reg[546][7]_srl32_n_1 ;
wire \rgb_buffer_reg[546][8]_srl32_n_1 ;
wire \rgb_buffer_reg[546][9]_srl32_n_1 ;
wire \rgb_buffer_reg[578][0]_srl32_n_1 ;
wire \rgb_buffer_reg[578][10]_srl32_n_1 ;
wire \rgb_buffer_reg[578][11]_srl32_n_1 ;
wire \rgb_buffer_reg[578][12]_srl32_n_1 ;
wire \rgb_buffer_reg[578][13]_srl32_n_1 ;
wire \rgb_buffer_reg[578][14]_srl32_n_1 ;
wire \rgb_buffer_reg[578][15]_srl32_n_1 ;
wire \rgb_buffer_reg[578][16]_srl32_n_1 ;
wire \rgb_buffer_reg[578][17]_srl32_n_1 ;
wire \rgb_buffer_reg[578][18]_srl32_n_1 ;
wire \rgb_buffer_reg[578][19]_srl32_n_1 ;
wire \rgb_buffer_reg[578][1]_srl32_n_1 ;
wire \rgb_buffer_reg[578][20]_srl32_n_1 ;
wire \rgb_buffer_reg[578][21]_srl32_n_1 ;
wire \rgb_buffer_reg[578][22]_srl32_n_1 ;
wire \rgb_buffer_reg[578][23]_srl32_n_1 ;
wire \rgb_buffer_reg[578][2]_srl32_n_1 ;
wire \rgb_buffer_reg[578][3]_srl32_n_1 ;
wire \rgb_buffer_reg[578][4]_srl32_n_1 ;
wire \rgb_buffer_reg[578][5]_srl32_n_1 ;
wire \rgb_buffer_reg[578][6]_srl32_n_1 ;
wire \rgb_buffer_reg[578][7]_srl32_n_1 ;
wire \rgb_buffer_reg[578][8]_srl32_n_1 ;
wire \rgb_buffer_reg[578][9]_srl32_n_1 ;
wire [23:0]\rgb_buffer_reg[642] ;
wire \rgb_buffer_reg[66][0]_srl32_n_1 ;
wire \rgb_buffer_reg[66][10]_srl32_n_1 ;
wire \rgb_buffer_reg[66][11]_srl32_n_1 ;
wire \rgb_buffer_reg[66][12]_srl32_n_1 ;
wire \rgb_buffer_reg[66][13]_srl32_n_1 ;
wire \rgb_buffer_reg[66][14]_srl32_n_1 ;
wire \rgb_buffer_reg[66][15]_srl32_n_1 ;
wire \rgb_buffer_reg[66][16]_srl32_n_1 ;
wire \rgb_buffer_reg[66][17]_srl32_n_1 ;
wire \rgb_buffer_reg[66][18]_srl32_n_1 ;
wire \rgb_buffer_reg[66][19]_srl32_n_1 ;
wire \rgb_buffer_reg[66][1]_srl32_n_1 ;
wire \rgb_buffer_reg[66][20]_srl32_n_1 ;
wire \rgb_buffer_reg[66][21]_srl32_n_1 ;
wire \rgb_buffer_reg[66][22]_srl32_n_1 ;
wire \rgb_buffer_reg[66][23]_srl32_n_1 ;
wire \rgb_buffer_reg[66][2]_srl32_n_1 ;
wire \rgb_buffer_reg[66][3]_srl32_n_1 ;
wire \rgb_buffer_reg[66][4]_srl32_n_1 ;
wire \rgb_buffer_reg[66][5]_srl32_n_1 ;
wire \rgb_buffer_reg[66][6]_srl32_n_1 ;
wire \rgb_buffer_reg[66][7]_srl32_n_1 ;
wire \rgb_buffer_reg[66][8]_srl32_n_1 ;
wire \rgb_buffer_reg[66][9]_srl32_n_1 ;
wire \rgb_buffer_reg[674][0]_srl32_n_1 ;
wire \rgb_buffer_reg[674][10]_srl32_n_1 ;
wire \rgb_buffer_reg[674][11]_srl32_n_1 ;
wire \rgb_buffer_reg[674][12]_srl32_n_1 ;
wire \rgb_buffer_reg[674][13]_srl32_n_1 ;
wire \rgb_buffer_reg[674][14]_srl32_n_1 ;
wire \rgb_buffer_reg[674][15]_srl32_n_1 ;
wire \rgb_buffer_reg[674][16]_srl32_n_1 ;
wire \rgb_buffer_reg[674][17]_srl32_n_1 ;
wire \rgb_buffer_reg[674][18]_srl32_n_1 ;
wire \rgb_buffer_reg[674][19]_srl32_n_1 ;
wire \rgb_buffer_reg[674][1]_srl32_n_1 ;
wire \rgb_buffer_reg[674][20]_srl32_n_1 ;
wire \rgb_buffer_reg[674][21]_srl32_n_1 ;
wire \rgb_buffer_reg[674][22]_srl32_n_1 ;
wire \rgb_buffer_reg[674][23]_srl32_n_1 ;
wire \rgb_buffer_reg[674][2]_srl32_n_1 ;
wire \rgb_buffer_reg[674][3]_srl32_n_1 ;
wire \rgb_buffer_reg[674][4]_srl32_n_1 ;
wire \rgb_buffer_reg[674][5]_srl32_n_1 ;
wire \rgb_buffer_reg[674][6]_srl32_n_1 ;
wire \rgb_buffer_reg[674][7]_srl32_n_1 ;
wire \rgb_buffer_reg[674][8]_srl32_n_1 ;
wire \rgb_buffer_reg[674][9]_srl32_n_1 ;
wire \rgb_buffer_reg[706][0]_srl32_n_1 ;
wire \rgb_buffer_reg[706][10]_srl32_n_1 ;
wire \rgb_buffer_reg[706][11]_srl32_n_1 ;
wire \rgb_buffer_reg[706][12]_srl32_n_1 ;
wire \rgb_buffer_reg[706][13]_srl32_n_1 ;
wire \rgb_buffer_reg[706][14]_srl32_n_1 ;
wire \rgb_buffer_reg[706][15]_srl32_n_1 ;
wire \rgb_buffer_reg[706][16]_srl32_n_1 ;
wire \rgb_buffer_reg[706][17]_srl32_n_1 ;
wire \rgb_buffer_reg[706][18]_srl32_n_1 ;
wire \rgb_buffer_reg[706][19]_srl32_n_1 ;
wire \rgb_buffer_reg[706][1]_srl32_n_1 ;
wire \rgb_buffer_reg[706][20]_srl32_n_1 ;
wire \rgb_buffer_reg[706][21]_srl32_n_1 ;
wire \rgb_buffer_reg[706][22]_srl32_n_1 ;
wire \rgb_buffer_reg[706][23]_srl32_n_1 ;
wire \rgb_buffer_reg[706][2]_srl32_n_1 ;
wire \rgb_buffer_reg[706][3]_srl32_n_1 ;
wire \rgb_buffer_reg[706][4]_srl32_n_1 ;
wire \rgb_buffer_reg[706][5]_srl32_n_1 ;
wire \rgb_buffer_reg[706][6]_srl32_n_1 ;
wire \rgb_buffer_reg[706][7]_srl32_n_1 ;
wire \rgb_buffer_reg[706][8]_srl32_n_1 ;
wire \rgb_buffer_reg[706][9]_srl32_n_1 ;
wire \rgb_buffer_reg[738][0]_srl32_n_1 ;
wire \rgb_buffer_reg[738][10]_srl32_n_1 ;
wire \rgb_buffer_reg[738][11]_srl32_n_1 ;
wire \rgb_buffer_reg[738][12]_srl32_n_1 ;
wire \rgb_buffer_reg[738][13]_srl32_n_1 ;
wire \rgb_buffer_reg[738][14]_srl32_n_1 ;
wire \rgb_buffer_reg[738][15]_srl32_n_1 ;
wire \rgb_buffer_reg[738][16]_srl32_n_1 ;
wire \rgb_buffer_reg[738][17]_srl32_n_1 ;
wire \rgb_buffer_reg[738][18]_srl32_n_1 ;
wire \rgb_buffer_reg[738][19]_srl32_n_1 ;
wire \rgb_buffer_reg[738][1]_srl32_n_1 ;
wire \rgb_buffer_reg[738][20]_srl32_n_1 ;
wire \rgb_buffer_reg[738][21]_srl32_n_1 ;
wire \rgb_buffer_reg[738][22]_srl32_n_1 ;
wire \rgb_buffer_reg[738][23]_srl32_n_1 ;
wire \rgb_buffer_reg[738][2]_srl32_n_1 ;
wire \rgb_buffer_reg[738][3]_srl32_n_1 ;
wire \rgb_buffer_reg[738][4]_srl32_n_1 ;
wire \rgb_buffer_reg[738][5]_srl32_n_1 ;
wire \rgb_buffer_reg[738][6]_srl32_n_1 ;
wire \rgb_buffer_reg[738][7]_srl32_n_1 ;
wire \rgb_buffer_reg[738][8]_srl32_n_1 ;
wire \rgb_buffer_reg[738][9]_srl32_n_1 ;
wire \rgb_buffer_reg[770][0]_srl32_n_0 ;
wire \rgb_buffer_reg[770][10]_srl32_n_0 ;
wire \rgb_buffer_reg[770][11]_srl32_n_0 ;
wire \rgb_buffer_reg[770][12]_srl32_n_0 ;
wire \rgb_buffer_reg[770][13]_srl32_n_0 ;
wire \rgb_buffer_reg[770][14]_srl32_n_0 ;
wire \rgb_buffer_reg[770][15]_srl32_n_0 ;
wire \rgb_buffer_reg[770][16]_srl32_n_0 ;
wire \rgb_buffer_reg[770][17]_srl32_n_0 ;
wire \rgb_buffer_reg[770][18]_srl32_n_0 ;
wire \rgb_buffer_reg[770][19]_srl32_n_0 ;
wire \rgb_buffer_reg[770][1]_srl32_n_0 ;
wire \rgb_buffer_reg[770][20]_srl32_n_0 ;
wire \rgb_buffer_reg[770][21]_srl32_n_0 ;
wire \rgb_buffer_reg[770][22]_srl32_n_0 ;
wire \rgb_buffer_reg[770][23]_srl32_n_0 ;
wire \rgb_buffer_reg[770][2]_srl32_n_0 ;
wire \rgb_buffer_reg[770][3]_srl32_n_0 ;
wire \rgb_buffer_reg[770][4]_srl32_n_0 ;
wire \rgb_buffer_reg[770][5]_srl32_n_0 ;
wire \rgb_buffer_reg[770][6]_srl32_n_0 ;
wire \rgb_buffer_reg[770][7]_srl32_n_0 ;
wire \rgb_buffer_reg[770][8]_srl32_n_0 ;
wire \rgb_buffer_reg[770][9]_srl32_n_0 ;
wire \rgb_buffer_reg[802][0]_srl32_n_1 ;
wire \rgb_buffer_reg[802][10]_srl32_n_1 ;
wire \rgb_buffer_reg[802][11]_srl32_n_1 ;
wire \rgb_buffer_reg[802][12]_srl32_n_1 ;
wire \rgb_buffer_reg[802][13]_srl32_n_1 ;
wire \rgb_buffer_reg[802][14]_srl32_n_1 ;
wire \rgb_buffer_reg[802][15]_srl32_n_1 ;
wire \rgb_buffer_reg[802][16]_srl32_n_1 ;
wire \rgb_buffer_reg[802][17]_srl32_n_1 ;
wire \rgb_buffer_reg[802][18]_srl32_n_1 ;
wire \rgb_buffer_reg[802][19]_srl32_n_1 ;
wire \rgb_buffer_reg[802][1]_srl32_n_1 ;
wire \rgb_buffer_reg[802][20]_srl32_n_1 ;
wire \rgb_buffer_reg[802][21]_srl32_n_1 ;
wire \rgb_buffer_reg[802][22]_srl32_n_1 ;
wire \rgb_buffer_reg[802][23]_srl32_n_1 ;
wire \rgb_buffer_reg[802][2]_srl32_n_1 ;
wire \rgb_buffer_reg[802][3]_srl32_n_1 ;
wire \rgb_buffer_reg[802][4]_srl32_n_1 ;
wire \rgb_buffer_reg[802][5]_srl32_n_1 ;
wire \rgb_buffer_reg[802][6]_srl32_n_1 ;
wire \rgb_buffer_reg[802][7]_srl32_n_1 ;
wire \rgb_buffer_reg[802][8]_srl32_n_1 ;
wire \rgb_buffer_reg[802][9]_srl32_n_1 ;
wire \rgb_buffer_reg[834][0]_srl32_n_1 ;
wire \rgb_buffer_reg[834][10]_srl32_n_1 ;
wire \rgb_buffer_reg[834][11]_srl32_n_1 ;
wire \rgb_buffer_reg[834][12]_srl32_n_1 ;
wire \rgb_buffer_reg[834][13]_srl32_n_1 ;
wire \rgb_buffer_reg[834][14]_srl32_n_1 ;
wire \rgb_buffer_reg[834][15]_srl32_n_1 ;
wire \rgb_buffer_reg[834][16]_srl32_n_1 ;
wire \rgb_buffer_reg[834][17]_srl32_n_1 ;
wire \rgb_buffer_reg[834][18]_srl32_n_1 ;
wire \rgb_buffer_reg[834][19]_srl32_n_1 ;
wire \rgb_buffer_reg[834][1]_srl32_n_1 ;
wire \rgb_buffer_reg[834][20]_srl32_n_1 ;
wire \rgb_buffer_reg[834][21]_srl32_n_1 ;
wire \rgb_buffer_reg[834][22]_srl32_n_1 ;
wire \rgb_buffer_reg[834][23]_srl32_n_1 ;
wire \rgb_buffer_reg[834][2]_srl32_n_1 ;
wire \rgb_buffer_reg[834][3]_srl32_n_1 ;
wire \rgb_buffer_reg[834][4]_srl32_n_1 ;
wire \rgb_buffer_reg[834][5]_srl32_n_1 ;
wire \rgb_buffer_reg[834][6]_srl32_n_1 ;
wire \rgb_buffer_reg[834][7]_srl32_n_1 ;
wire \rgb_buffer_reg[834][8]_srl32_n_1 ;
wire \rgb_buffer_reg[834][9]_srl32_n_1 ;
wire \rgb_buffer_reg[866][0]_srl32_n_1 ;
wire \rgb_buffer_reg[866][10]_srl32_n_1 ;
wire \rgb_buffer_reg[866][11]_srl32_n_1 ;
wire \rgb_buffer_reg[866][12]_srl32_n_1 ;
wire \rgb_buffer_reg[866][13]_srl32_n_1 ;
wire \rgb_buffer_reg[866][14]_srl32_n_1 ;
wire \rgb_buffer_reg[866][15]_srl32_n_1 ;
wire \rgb_buffer_reg[866][16]_srl32_n_1 ;
wire \rgb_buffer_reg[866][17]_srl32_n_1 ;
wire \rgb_buffer_reg[866][18]_srl32_n_1 ;
wire \rgb_buffer_reg[866][19]_srl32_n_1 ;
wire \rgb_buffer_reg[866][1]_srl32_n_1 ;
wire \rgb_buffer_reg[866][20]_srl32_n_1 ;
wire \rgb_buffer_reg[866][21]_srl32_n_1 ;
wire \rgb_buffer_reg[866][22]_srl32_n_1 ;
wire \rgb_buffer_reg[866][23]_srl32_n_1 ;
wire \rgb_buffer_reg[866][2]_srl32_n_1 ;
wire \rgb_buffer_reg[866][3]_srl32_n_1 ;
wire \rgb_buffer_reg[866][4]_srl32_n_1 ;
wire \rgb_buffer_reg[866][5]_srl32_n_1 ;
wire \rgb_buffer_reg[866][6]_srl32_n_1 ;
wire \rgb_buffer_reg[866][7]_srl32_n_1 ;
wire \rgb_buffer_reg[866][8]_srl32_n_1 ;
wire \rgb_buffer_reg[866][9]_srl32_n_1 ;
wire \rgb_buffer_reg[898][0]_srl32_n_0 ;
wire \rgb_buffer_reg[898][10]_srl32_n_0 ;
wire \rgb_buffer_reg[898][11]_srl32_n_0 ;
wire \rgb_buffer_reg[898][12]_srl32_n_0 ;
wire \rgb_buffer_reg[898][13]_srl32_n_0 ;
wire \rgb_buffer_reg[898][14]_srl32_n_0 ;
wire \rgb_buffer_reg[898][15]_srl32_n_0 ;
wire \rgb_buffer_reg[898][16]_srl32_n_0 ;
wire \rgb_buffer_reg[898][17]_srl32_n_0 ;
wire \rgb_buffer_reg[898][18]_srl32_n_0 ;
wire \rgb_buffer_reg[898][19]_srl32_n_0 ;
wire \rgb_buffer_reg[898][1]_srl32_n_0 ;
wire \rgb_buffer_reg[898][20]_srl32_n_0 ;
wire \rgb_buffer_reg[898][21]_srl32_n_0 ;
wire \rgb_buffer_reg[898][22]_srl32_n_0 ;
wire \rgb_buffer_reg[898][23]_srl32_n_0 ;
wire \rgb_buffer_reg[898][2]_srl32_n_0 ;
wire \rgb_buffer_reg[898][3]_srl32_n_0 ;
wire \rgb_buffer_reg[898][4]_srl32_n_0 ;
wire \rgb_buffer_reg[898][5]_srl32_n_0 ;
wire \rgb_buffer_reg[898][6]_srl32_n_0 ;
wire \rgb_buffer_reg[898][7]_srl32_n_0 ;
wire \rgb_buffer_reg[898][8]_srl32_n_0 ;
wire \rgb_buffer_reg[898][9]_srl32_n_0 ;
wire \rgb_buffer_reg[930][0]_srl32_n_1 ;
wire \rgb_buffer_reg[930][10]_srl32_n_1 ;
wire \rgb_buffer_reg[930][11]_srl32_n_1 ;
wire \rgb_buffer_reg[930][12]_srl32_n_1 ;
wire \rgb_buffer_reg[930][13]_srl32_n_1 ;
wire \rgb_buffer_reg[930][14]_srl32_n_1 ;
wire \rgb_buffer_reg[930][15]_srl32_n_1 ;
wire \rgb_buffer_reg[930][16]_srl32_n_1 ;
wire \rgb_buffer_reg[930][17]_srl32_n_1 ;
wire \rgb_buffer_reg[930][18]_srl32_n_1 ;
wire \rgb_buffer_reg[930][19]_srl32_n_1 ;
wire \rgb_buffer_reg[930][1]_srl32_n_1 ;
wire \rgb_buffer_reg[930][20]_srl32_n_1 ;
wire \rgb_buffer_reg[930][21]_srl32_n_1 ;
wire \rgb_buffer_reg[930][22]_srl32_n_1 ;
wire \rgb_buffer_reg[930][23]_srl32_n_1 ;
wire \rgb_buffer_reg[930][2]_srl32_n_1 ;
wire \rgb_buffer_reg[930][3]_srl32_n_1 ;
wire \rgb_buffer_reg[930][4]_srl32_n_1 ;
wire \rgb_buffer_reg[930][5]_srl32_n_1 ;
wire \rgb_buffer_reg[930][6]_srl32_n_1 ;
wire \rgb_buffer_reg[930][7]_srl32_n_1 ;
wire \rgb_buffer_reg[930][8]_srl32_n_1 ;
wire \rgb_buffer_reg[930][9]_srl32_n_1 ;
wire \rgb_buffer_reg[962][0]_srl32_n_1 ;
wire \rgb_buffer_reg[962][10]_srl32_n_1 ;
wire \rgb_buffer_reg[962][11]_srl32_n_1 ;
wire \rgb_buffer_reg[962][12]_srl32_n_1 ;
wire \rgb_buffer_reg[962][13]_srl32_n_1 ;
wire \rgb_buffer_reg[962][14]_srl32_n_1 ;
wire \rgb_buffer_reg[962][15]_srl32_n_1 ;
wire \rgb_buffer_reg[962][16]_srl32_n_1 ;
wire \rgb_buffer_reg[962][17]_srl32_n_1 ;
wire \rgb_buffer_reg[962][18]_srl32_n_1 ;
wire \rgb_buffer_reg[962][19]_srl32_n_1 ;
wire \rgb_buffer_reg[962][1]_srl32_n_1 ;
wire \rgb_buffer_reg[962][20]_srl32_n_1 ;
wire \rgb_buffer_reg[962][21]_srl32_n_1 ;
wire \rgb_buffer_reg[962][22]_srl32_n_1 ;
wire \rgb_buffer_reg[962][23]_srl32_n_1 ;
wire \rgb_buffer_reg[962][2]_srl32_n_1 ;
wire \rgb_buffer_reg[962][3]_srl32_n_1 ;
wire \rgb_buffer_reg[962][4]_srl32_n_1 ;
wire \rgb_buffer_reg[962][5]_srl32_n_1 ;
wire \rgb_buffer_reg[962][6]_srl32_n_1 ;
wire \rgb_buffer_reg[962][7]_srl32_n_1 ;
wire \rgb_buffer_reg[962][8]_srl32_n_1 ;
wire \rgb_buffer_reg[962][9]_srl32_n_1 ;
wire \rgb_buffer_reg[98][0]_srl32_n_1 ;
wire \rgb_buffer_reg[98][10]_srl32_n_1 ;
wire \rgb_buffer_reg[98][11]_srl32_n_1 ;
wire \rgb_buffer_reg[98][12]_srl32_n_1 ;
wire \rgb_buffer_reg[98][13]_srl32_n_1 ;
wire \rgb_buffer_reg[98][14]_srl32_n_1 ;
wire \rgb_buffer_reg[98][15]_srl32_n_1 ;
wire \rgb_buffer_reg[98][16]_srl32_n_1 ;
wire \rgb_buffer_reg[98][17]_srl32_n_1 ;
wire \rgb_buffer_reg[98][18]_srl32_n_1 ;
wire \rgb_buffer_reg[98][19]_srl32_n_1 ;
wire \rgb_buffer_reg[98][1]_srl32_n_1 ;
wire \rgb_buffer_reg[98][20]_srl32_n_1 ;
wire \rgb_buffer_reg[98][21]_srl32_n_1 ;
wire \rgb_buffer_reg[98][22]_srl32_n_1 ;
wire \rgb_buffer_reg[98][23]_srl32_n_1 ;
wire \rgb_buffer_reg[98][2]_srl32_n_1 ;
wire \rgb_buffer_reg[98][3]_srl32_n_1 ;
wire \rgb_buffer_reg[98][4]_srl32_n_1 ;
wire \rgb_buffer_reg[98][5]_srl32_n_1 ;
wire \rgb_buffer_reg[98][6]_srl32_n_1 ;
wire \rgb_buffer_reg[98][7]_srl32_n_1 ;
wire \rgb_buffer_reg[98][8]_srl32_n_1 ;
wire \rgb_buffer_reg[98][9]_srl32_n_1 ;
wire \rgb_buffer_reg[994][0]_srl32_n_1 ;
wire \rgb_buffer_reg[994][10]_srl32_n_1 ;
wire \rgb_buffer_reg[994][11]_srl32_n_1 ;
wire \rgb_buffer_reg[994][12]_srl32_n_1 ;
wire \rgb_buffer_reg[994][13]_srl32_n_1 ;
wire \rgb_buffer_reg[994][14]_srl32_n_1 ;
wire \rgb_buffer_reg[994][15]_srl32_n_1 ;
wire \rgb_buffer_reg[994][16]_srl32_n_1 ;
wire \rgb_buffer_reg[994][17]_srl32_n_1 ;
wire \rgb_buffer_reg[994][18]_srl32_n_1 ;
wire \rgb_buffer_reg[994][19]_srl32_n_1 ;
wire \rgb_buffer_reg[994][1]_srl32_n_1 ;
wire \rgb_buffer_reg[994][20]_srl32_n_1 ;
wire \rgb_buffer_reg[994][21]_srl32_n_1 ;
wire \rgb_buffer_reg[994][22]_srl32_n_1 ;
wire \rgb_buffer_reg[994][23]_srl32_n_1 ;
wire \rgb_buffer_reg[994][2]_srl32_n_1 ;
wire \rgb_buffer_reg[994][3]_srl32_n_1 ;
wire \rgb_buffer_reg[994][4]_srl32_n_1 ;
wire \rgb_buffer_reg[994][5]_srl32_n_1 ;
wire \rgb_buffer_reg[994][6]_srl32_n_1 ;
wire \rgb_buffer_reg[994][7]_srl32_n_1 ;
wire \rgb_buffer_reg[994][8]_srl32_n_1 ;
wire \rgb_buffer_reg[994][9]_srl32_n_1 ;
wire [23:0]rgb_pass;
wire vsync_in;
wire [3:1]NLW_i___82_carry__2_i_2_CO_UNCONNECTED;
wire [3:0]NLW_i___82_carry__2_i_2_O_UNCONNECTED;
wire [3:1]NLW_i___82_carry__2_i_2__0_CO_UNCONNECTED;
wire [3:0]NLW_i___82_carry__2_i_2__0_O_UNCONNECTED;
wire [3:0]NLW_rgb_blur3__24_carry__1_CO_UNCONNECTED;
wire [3:1]NLW_rgb_blur3__24_carry__1_O_UNCONNECTED;
wire [0:0]NLW_rgb_blur3__50_carry_O_UNCONNECTED;
wire [0:0]NLW_rgb_blur3__82_carry_O_UNCONNECTED;
wire [3:0]NLW_rgb_blur3__82_carry__2_CO_UNCONNECTED;
wire [3:1]NLW_rgb_blur3__82_carry__2_O_UNCONNECTED;
wire [3:1]NLW_rgb_blur3__82_carry__2_i_2_CO_UNCONNECTED;
wire [3:0]NLW_rgb_blur3__82_carry__2_i_2_O_UNCONNECTED;
wire [0:0]NLW_rgb_blur3_carry_O_UNCONNECTED;
wire [3:0]NLW_rgb_blur3_carry__1_CO_UNCONNECTED;
wire [3:1]NLW_rgb_blur3_carry__1_O_UNCONNECTED;
wire [3:2]\NLW_rgb_blur3_inferred__0/i___0_carry__2_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur3_inferred__0/i___0_carry__2_O_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur3_inferred__1/i___0_carry__6_CO_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur3_inferred__2/i___24_carry__1_CO_UNCONNECTED ;
wire [3:1]\NLW_rgb_blur3_inferred__2/i___24_carry__1_O_UNCONNECTED ;
wire [0:0]\NLW_rgb_blur3_inferred__2/i___50_carry_O_UNCONNECTED ;
wire [0:0]\NLW_rgb_blur3_inferred__2/i___82_carry_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur3_inferred__2/i___82_carry__2_CO_UNCONNECTED ;
wire [3:1]\NLW_rgb_blur3_inferred__2/i___82_carry__2_O_UNCONNECTED ;
wire [0:0]\NLW_rgb_blur3_inferred__2/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur3_inferred__2/i__carry__1_CO_UNCONNECTED ;
wire [3:1]\NLW_rgb_blur3_inferred__2/i__carry__1_O_UNCONNECTED ;
wire [3:2]\NLW_rgb_blur3_inferred__3/i___0_carry__2_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur3_inferred__3/i___0_carry__2_O_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur3_inferred__4/i___0_carry__6_CO_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur3_inferred__5/i___24_carry__1_CO_UNCONNECTED ;
wire [3:1]\NLW_rgb_blur3_inferred__5/i___24_carry__1_O_UNCONNECTED ;
wire [0:0]\NLW_rgb_blur3_inferred__5/i___50_carry_O_UNCONNECTED ;
wire [0:0]\NLW_rgb_blur3_inferred__5/i___82_carry_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur3_inferred__5/i___82_carry__2_CO_UNCONNECTED ;
wire [3:1]\NLW_rgb_blur3_inferred__5/i___82_carry__2_O_UNCONNECTED ;
wire [0:0]\NLW_rgb_blur3_inferred__5/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur3_inferred__5/i__carry__1_CO_UNCONNECTED ;
wire [3:1]\NLW_rgb_blur3_inferred__5/i__carry__1_O_UNCONNECTED ;
wire [3:2]\NLW_rgb_blur3_inferred__6/i___0_carry__2_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur3_inferred__6/i___0_carry__2_O_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur3_inferred__7/i___0_carry__6_CO_UNCONNECTED ;
wire [3:0]NLW_rgb_blur4_carry_O_UNCONNECTED;
wire [3:0]NLW_rgb_blur4_carry__0_O_UNCONNECTED;
wire [3:0]NLW_rgb_blur4_carry__1_O_UNCONNECTED;
wire [3:0]NLW_rgb_blur4_carry__2_O_UNCONNECTED;
wire [3:0]\NLW_rgb_blur4_inferred__0/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__0/i__carry__0_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__0/i__carry__1_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__0/i__carry__2_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__1/i__carry_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__1/i__carry__0_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__1/i__carry__1_O_UNCONNECTED ;
wire [3:0]\NLW_rgb_blur4_inferred__1/i__carry__2_O_UNCONNECTED ;
wire [3:2]\NLW_rgb_blur_reg[15]_i_3_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur_reg[15]_i_3_O_UNCONNECTED ;
wire [2:0]\NLW_rgb_blur_reg[17]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_rgb_blur_reg[1]_i_2_O_UNCONNECTED ;
wire [3:2]\NLW_rgb_blur_reg[23]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur_reg[23]_i_4_O_UNCONNECTED ;
wire [3:2]\NLW_rgb_blur_reg[7]_i_3_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_blur_reg[7]_i_3_O_UNCONNECTED ;
wire [2:0]\NLW_rgb_blur_reg[9]_i_2_O_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1026][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1058][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1090][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1122][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1154][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1186][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1218][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1250][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][0]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][10]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][11]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][12]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][13]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][14]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][15]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][16]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][17]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][18]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][19]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][1]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][20]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][21]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][22]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][23]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][2]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][3]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][4]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][5]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][6]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][7]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][8]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[1279][9]_srl29_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[130][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[162][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[194][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[226][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[258][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[290][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[322][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[34][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[354][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[386][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[418][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[450][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[482][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[514][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[546][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[578][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[610][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[66][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[674][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[706][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[738][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[770][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[802][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[834][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[866][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[898][9]_srl32_Q31_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[930][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[962][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[98][9]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][0]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][10]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][11]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][12]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][13]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][14]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][15]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][16]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][17]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][18]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][19]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][1]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][20]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][21]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][22]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][23]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][2]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][3]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][4]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][5]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][6]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][7]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][8]_srl32_Q_UNCONNECTED ;
wire \NLW_rgb_buffer_reg[994][9]_srl32_Q_UNCONNECTED ;
LUT2 #(
.INIT(4'h1))
\B[7]__2_i_1
(.I0(hsync_in),
.I1(vsync_in),
.O(active));
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_1
(.I0(\C[7] [6]),
.I1(rgb_blur3__82_carry__0_n_5),
.I2(Q[6]),
.O(i___0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_1__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__0_n_5 ),
.I1(\B[6]__0 ),
.I2(\C[6]__0_0 ),
.O(i___0_carry__0_i_1__0_n_0));
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_1__1
(.I0(\B[7]__6 [6]),
.I1(\C[6]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry__0_n_5 ),
.O(i___0_carry__0_i_1__1_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_1__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__0_n_5 ),
.I1(\B[6]__4 ),
.I2(\C[6]__2_0 ),
.O(i___0_carry__0_i_1__2_n_0));
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_1__3
(.I0(\B[7]__10 [6]),
.I1(\C[6]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry__0_n_5 ),
.O(i___0_carry__0_i_1__3_n_0));
(* HLUTNM = "lutpair38" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_1__4
(.I0(\C[6]__4_0 ),
.I1(PCIN[6]),
.I2(\B[6]__8 ),
.O(i___0_carry__0_i_1__4_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_2
(.I0(Q[5]),
.I1(\C[7] [5]),
.I2(rgb_blur3__82_carry__0_n_6),
.O(i___0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_2__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__0_n_6 ),
.I1(\B[5]__0 ),
.I2(\C[5]__0_0 ),
.O(i___0_carry__0_i_2__0_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_2__1
(.I0(\B[7]__6 [5]),
.I1(\C[5]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry__0_n_6 ),
.O(i___0_carry__0_i_2__1_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_2__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__0_n_6 ),
.I1(\B[5]__4 ),
.I2(\C[5]__2_0 ),
.O(i___0_carry__0_i_2__2_n_0));
(* HLUTNM = "lutpair31" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_2__3
(.I0(\B[7]__10 [5]),
.I1(\C[5]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry__0_n_6 ),
.O(i___0_carry__0_i_2__3_n_0));
(* HLUTNM = "lutpair37" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_2__4
(.I0(\C[5]__4_0 ),
.I1(PCIN[5]),
.I2(\B[5]__8 ),
.O(i___0_carry__0_i_2__4_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_3
(.I0(Q[4]),
.I1(\C[7] [4]),
.I2(rgb_blur3__82_carry__0_n_7),
.O(i___0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_3__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__0_n_7 ),
.I1(\B[4]__0 ),
.I2(\C[4]__0_0 ),
.O(i___0_carry__0_i_3__0_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_3__1
(.I0(\B[7]__6 [4]),
.I1(\C[4]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry__0_n_7 ),
.O(i___0_carry__0_i_3__1_n_0));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_3__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__0_n_7 ),
.I1(\B[4]__4 ),
.I2(\C[4]__2_0 ),
.O(i___0_carry__0_i_3__2_n_0));
(* HLUTNM = "lutpair30" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_3__3
(.I0(\B[7]__10 [4]),
.I1(\C[4]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry__0_n_7 ),
.O(i___0_carry__0_i_3__3_n_0));
(* HLUTNM = "lutpair36" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_3__4
(.I0(\C[4]__4_0 ),
.I1(PCIN[4]),
.I2(\B[4]__8 ),
.O(i___0_carry__0_i_3__4_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_4
(.I0(Q[3]),
.I1(\C[7] [3]),
.I2(rgb_blur3__82_carry_n_4),
.O(i___0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_4__0
(.I0(\rgb_blur3_inferred__0/i___0_carry_n_4 ),
.I1(\B[3]__0 ),
.I2(\C[3]__0_0 ),
.O(i___0_carry__0_i_4__0_n_0));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_4__1
(.I0(\B[7]__6 [3]),
.I1(\C[3]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry_n_4 ),
.O(i___0_carry__0_i_4__1_n_0));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_4__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_4 ),
.I1(\B[3]__4 ),
.I2(\C[3]__2_0 ),
.O(i___0_carry__0_i_4__2_n_0));
(* HLUTNM = "lutpair29" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_4__3
(.I0(\B[7]__10 [3]),
.I1(\C[3]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry_n_4 ),
.O(i___0_carry__0_i_4__3_n_0));
(* HLUTNM = "lutpair35" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry__0_i_4__4
(.I0(\C[3]__4_0 ),
.I1(PCIN[3]),
.I2(\B[3]__8 ),
.O(i___0_carry__0_i_4__4_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_5
(.I0(i___0_carry__0_i_1_n_0),
.I1(rgb_blur3__82_carry__0_n_4),
.I2(Q[7]),
.I3(\C[7] [7]),
.O(i___0_carry__0_i_5_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_5__0
(.I0(i___0_carry__0_i_1__0_n_0),
.I1(\rgb_blur3_inferred__0/i___0_carry__0_n_4 ),
.I2(\B[7]__0 ),
.I3(\C[7]__0_0 ),
.O(i___0_carry__0_i_5__0_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_5__1
(.I0(i___0_carry__0_i_1__1_n_0),
.I1(\rgb_blur3_inferred__2/i___82_carry__0_n_4 ),
.I2(\B[7]__6 [7]),
.I3(\C[7]__1 ),
.O(i___0_carry__0_i_5__1_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_5__2
(.I0(i___0_carry__0_i_1__2_n_0),
.I1(\rgb_blur3_inferred__3/i___0_carry__0_n_4 ),
.I2(\B[7]__4 ),
.I3(\C[7]__2_0 ),
.O(i___0_carry__0_i_5__2_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_5__3
(.I0(i___0_carry__0_i_1__3_n_0),
.I1(\rgb_blur3_inferred__5/i___82_carry__0_n_4 ),
.I2(\B[7]__10 [7]),
.I3(\C[7]__3 ),
.O(i___0_carry__0_i_5__3_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_5__4
(.I0(i___0_carry__0_i_1__4_n_0),
.I1(PCIN[7]),
.I2(\B[7]__8 ),
.I3(\C[7]__4_0 ),
.O(i___0_carry__0_i_5__4_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_6
(.I0(\C[7] [6]),
.I1(rgb_blur3__82_carry__0_n_5),
.I2(Q[6]),
.I3(i___0_carry__0_i_2_n_0),
.O(i___0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_6__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__0_n_5 ),
.I1(\B[6]__0 ),
.I2(\C[6]__0_0 ),
.I3(i___0_carry__0_i_2__0_n_0),
.O(i___0_carry__0_i_6__0_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_6__1
(.I0(\B[7]__6 [6]),
.I1(\C[6]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry__0_n_5 ),
.I3(i___0_carry__0_i_2__1_n_0),
.O(i___0_carry__0_i_6__1_n_0));
(* HLUTNM = "lutpair25" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_6__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__0_n_5 ),
.I1(\B[6]__4 ),
.I2(\C[6]__2_0 ),
.I3(i___0_carry__0_i_2__2_n_0),
.O(i___0_carry__0_i_6__2_n_0));
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_6__3
(.I0(\B[7]__10 [6]),
.I1(\C[6]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry__0_n_5 ),
.I3(i___0_carry__0_i_2__3_n_0),
.O(i___0_carry__0_i_6__3_n_0));
(* HLUTNM = "lutpair38" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_6__4
(.I0(\C[6]__4_0 ),
.I1(PCIN[6]),
.I2(\B[6]__8 ),
.I3(i___0_carry__0_i_2__4_n_0),
.O(i___0_carry__0_i_6__4_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_7
(.I0(Q[5]),
.I1(\C[7] [5]),
.I2(rgb_blur3__82_carry__0_n_6),
.I3(i___0_carry__0_i_3_n_0),
.O(i___0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_7__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__0_n_6 ),
.I1(\B[5]__0 ),
.I2(\C[5]__0_0 ),
.I3(i___0_carry__0_i_3__0_n_0),
.O(i___0_carry__0_i_7__0_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_7__1
(.I0(\B[7]__6 [5]),
.I1(\C[5]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry__0_n_6 ),
.I3(i___0_carry__0_i_3__1_n_0),
.O(i___0_carry__0_i_7__1_n_0));
(* HLUTNM = "lutpair24" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_7__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__0_n_6 ),
.I1(\B[5]__4 ),
.I2(\C[5]__2_0 ),
.I3(i___0_carry__0_i_3__2_n_0),
.O(i___0_carry__0_i_7__2_n_0));
(* HLUTNM = "lutpair31" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_7__3
(.I0(\B[7]__10 [5]),
.I1(\C[5]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry__0_n_6 ),
.I3(i___0_carry__0_i_3__3_n_0),
.O(i___0_carry__0_i_7__3_n_0));
(* HLUTNM = "lutpair37" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_7__4
(.I0(\C[5]__4_0 ),
.I1(PCIN[5]),
.I2(\B[5]__8 ),
.I3(i___0_carry__0_i_3__4_n_0),
.O(i___0_carry__0_i_7__4_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_8
(.I0(Q[4]),
.I1(\C[7] [4]),
.I2(rgb_blur3__82_carry__0_n_7),
.I3(i___0_carry__0_i_4_n_0),
.O(i___0_carry__0_i_8_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_8__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__0_n_7 ),
.I1(\B[4]__0 ),
.I2(\C[4]__0_0 ),
.I3(i___0_carry__0_i_4__0_n_0),
.O(i___0_carry__0_i_8__0_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_8__1
(.I0(\B[7]__6 [4]),
.I1(\C[4]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry__0_n_7 ),
.I3(i___0_carry__0_i_4__1_n_0),
.O(i___0_carry__0_i_8__1_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_8__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__0_n_7 ),
.I1(\B[4]__4 ),
.I2(\C[4]__2_0 ),
.I3(i___0_carry__0_i_4__2_n_0),
.O(i___0_carry__0_i_8__2_n_0));
(* HLUTNM = "lutpair30" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_8__3
(.I0(\B[7]__10 [4]),
.I1(\C[4]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry__0_n_7 ),
.I3(i___0_carry__0_i_4__3_n_0),
.O(i___0_carry__0_i_8__3_n_0));
(* HLUTNM = "lutpair36" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry__0_i_8__4
(.I0(\C[4]__4_0 ),
.I1(PCIN[4]),
.I2(\B[4]__8 ),
.I3(i___0_carry__0_i_4__4_n_0),
.O(i___0_carry__0_i_8__4_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__1_i_1
(.I0(rgb_blur3__82_carry__1_n_5),
.I1(rgb_blur3__82_carry__1_n_4),
.O(i___0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__1_i_1__0
(.I0(\rgb_blur3_inferred__2/i___82_carry__1_n_5 ),
.I1(\rgb_blur3_inferred__2/i___82_carry__1_n_4 ),
.O(i___0_carry__1_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__1_i_1__1
(.I0(\rgb_blur3_inferred__5/i___82_carry__1_n_5 ),
.I1(\rgb_blur3_inferred__5/i___82_carry__1_n_4 ),
.O(i___0_carry__1_i_1__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_1__2
(.I0(\rgb_blur3_inferred__0/i___0_carry__1_n_4 ),
.O(i___0_carry__1_i_1__2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_1__3
(.I0(\rgb_blur3_inferred__3/i___0_carry__1_n_4 ),
.O(i___0_carry__1_i_1__3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_1__4
(.I0(PCIN[11]),
.O(i___0_carry__1_i_1__4_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__1_i_2
(.I0(rgb_blur3__82_carry__1_n_6),
.I1(rgb_blur3__82_carry__1_n_5),
.O(i___0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__1_i_2__0
(.I0(\rgb_blur3_inferred__2/i___82_carry__1_n_6 ),
.I1(\rgb_blur3_inferred__2/i___82_carry__1_n_5 ),
.O(i___0_carry__1_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__1_i_2__1
(.I0(\rgb_blur3_inferred__5/i___82_carry__1_n_6 ),
.I1(\rgb_blur3_inferred__5/i___82_carry__1_n_5 ),
.O(i___0_carry__1_i_2__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_2__2
(.I0(\rgb_blur3_inferred__0/i___0_carry__1_n_5 ),
.O(i___0_carry__1_i_2__2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_2__3
(.I0(\rgb_blur3_inferred__3/i___0_carry__1_n_5 ),
.O(i___0_carry__1_i_2__3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_2__4
(.I0(PCIN[10]),
.O(i___0_carry__1_i_2__4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_3
(.I0(rgb_blur3__82_carry__1_n_6),
.O(i___0_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_3__0
(.I0(\rgb_blur3_inferred__0/i___0_carry__1_n_6 ),
.O(i___0_carry__1_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_3__1
(.I0(\rgb_blur3_inferred__2/i___82_carry__1_n_6 ),
.O(i___0_carry__1_i_3__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_3__2
(.I0(\rgb_blur3_inferred__3/i___0_carry__1_n_6 ),
.O(i___0_carry__1_i_3__2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_3__3
(.I0(\rgb_blur3_inferred__5/i___82_carry__1_n_6 ),
.O(i___0_carry__1_i_3__3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__1_i_3__4
(.I0(PCIN[9]),
.O(i___0_carry__1_i_3__4_n_0));
LUT4 #(
.INIT(16'h17E8))
i___0_carry__1_i_4
(.I0(Q[7]),
.I1(rgb_blur3__82_carry__0_n_4),
.I2(\C[7] [7]),
.I3(rgb_blur3__82_carry__1_n_7),
.O(i___0_carry__1_i_4_n_0));
LUT4 #(
.INIT(16'h17E8))
i___0_carry__1_i_4__0
(.I0(\C[7]__0_0 ),
.I1(\B[7]__0 ),
.I2(\rgb_blur3_inferred__0/i___0_carry__0_n_4 ),
.I3(\rgb_blur3_inferred__0/i___0_carry__1_n_7 ),
.O(i___0_carry__1_i_4__0_n_0));
LUT4 #(
.INIT(16'h17E8))
i___0_carry__1_i_4__1
(.I0(\rgb_blur3_inferred__2/i___82_carry__0_n_4 ),
.I1(\C[7]__1 ),
.I2(\B[7]__6 [7]),
.I3(\rgb_blur3_inferred__2/i___82_carry__1_n_7 ),
.O(i___0_carry__1_i_4__1_n_0));
LUT4 #(
.INIT(16'h17E8))
i___0_carry__1_i_4__2
(.I0(\C[7]__2_0 ),
.I1(\B[7]__4 ),
.I2(\rgb_blur3_inferred__3/i___0_carry__0_n_4 ),
.I3(\rgb_blur3_inferred__3/i___0_carry__1_n_7 ),
.O(i___0_carry__1_i_4__2_n_0));
LUT4 #(
.INIT(16'h17E8))
i___0_carry__1_i_4__3
(.I0(\rgb_blur3_inferred__5/i___82_carry__0_n_4 ),
.I1(\C[7]__3 ),
.I2(\B[7]__10 [7]),
.I3(\rgb_blur3_inferred__5/i___82_carry__1_n_7 ),
.O(i___0_carry__1_i_4__3_n_0));
LUT4 #(
.INIT(16'h17E8))
i___0_carry__1_i_4__4
(.I0(\B[7]__8 ),
.I1(PCIN[7]),
.I2(\C[7]__4_0 ),
.I3(PCIN[8]),
.O(i___0_carry__1_i_4__4_n_0));
LUT2 #(
.INIT(4'h6))
i___0_carry__2_i_1
(.I0(rgb_blur3__82_carry__2_n_7),
.I1(rgb_blur3__82_carry__2_n_2),
.O(i___0_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___0_carry__2_i_1__0
(.I0(\rgb_blur3_inferred__2/i___82_carry__2_n_7 ),
.I1(\rgb_blur3_inferred__2/i___82_carry__2_n_2 ),
.O(i___0_carry__2_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___0_carry__2_i_1__1
(.I0(\rgb_blur3_inferred__5/i___82_carry__2_n_7 ),
.I1(\rgb_blur3_inferred__5/i___82_carry__2_n_2 ),
.O(i___0_carry__2_i_1__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_1__2
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__2_i_1__2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_1__3
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__2_i_1__3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_1__4
(.I0(PCIN[31]),
.O(i___0_carry__2_i_1__4_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__2_i_2
(.I0(rgb_blur3__82_carry__1_n_4),
.I1(rgb_blur3__82_carry__2_n_7),
.O(i___0_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__2_i_2__0
(.I0(\rgb_blur3_inferred__2/i___82_carry__1_n_4 ),
.I1(\rgb_blur3_inferred__2/i___82_carry__2_n_7 ),
.O(i___0_carry__2_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
i___0_carry__2_i_2__1
(.I0(\rgb_blur3_inferred__5/i___82_carry__1_n_4 ),
.I1(\rgb_blur3_inferred__5/i___82_carry__2_n_7 ),
.O(i___0_carry__2_i_2__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_2__2
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__2_i_2__2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_2__3
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__2_i_2__3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_2__4
(.I0(PCIN[31]),
.O(i___0_carry__2_i_2__4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_3
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_6 ),
.O(i___0_carry__2_i_3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_3__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_6 ),
.O(i___0_carry__2_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_3__1
(.I0(PCIN[13]),
.O(i___0_carry__2_i_3__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_4
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_7 ),
.O(i___0_carry__2_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_4__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_7 ),
.O(i___0_carry__2_i_4__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__2_i_4__1
(.I0(PCIN[12]),
.O(i___0_carry__2_i_4__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_1
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_1__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_1__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_1__1
(.I0(PCIN[31]),
.O(i___0_carry__3_i_1__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_2
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_2__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_2__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_2__1
(.I0(PCIN[31]),
.O(i___0_carry__3_i_2__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_3
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_3__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_3__1
(.I0(PCIN[31]),
.O(i___0_carry__3_i_3__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_4
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_4__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__3_i_4__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__3_i_4__1
(.I0(PCIN[31]),
.O(i___0_carry__3_i_4__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_1
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_1__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_1__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_1__1
(.I0(PCIN[31]),
.O(i___0_carry__4_i_1__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_2
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_2__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_2__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_2__1
(.I0(PCIN[31]),
.O(i___0_carry__4_i_2__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_3
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_3__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_3__1
(.I0(PCIN[31]),
.O(i___0_carry__4_i_3__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_4
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_4__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__4_i_4__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__4_i_4__1
(.I0(PCIN[31]),
.O(i___0_carry__4_i_4__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_1
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_1__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_1__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_1__1
(.I0(PCIN[31]),
.O(i___0_carry__5_i_1__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_2
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_2__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_2__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_2__1
(.I0(PCIN[31]),
.O(i___0_carry__5_i_2__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_3
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_3__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_3__1
(.I0(PCIN[31]),
.O(i___0_carry__5_i_3__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_4
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_4__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__5_i_4__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__5_i_4__1
(.I0(PCIN[31]),
.O(i___0_carry__5_i_4__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_1
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_1__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_1__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_1__1
(.I0(PCIN[31]),
.O(i___0_carry__6_i_1__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_2
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_2_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_2__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_2__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_2__1
(.I0(PCIN[31]),
.O(i___0_carry__6_i_2__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_3
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_3_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_3__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_3__1
(.I0(PCIN[31]),
.O(i___0_carry__6_i_3__1_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_4
(.I0(\rgb_blur3_inferred__0/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_4__0
(.I0(\rgb_blur3_inferred__3/i___0_carry__2_n_5 ),
.O(i___0_carry__6_i_4__0_n_0));
LUT1 #(
.INIT(2'h2))
i___0_carry__6_i_4__1
(.I0(PCIN[31]),
.O(i___0_carry__6_i_4__1_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_1
(.I0(Q[2]),
.I1(\C[7] [2]),
.I2(rgb_blur3__82_carry_n_5),
.O(i___0_carry_i_1_n_0));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_1__0
(.I0(\rgb_blur3_inferred__0/i___0_carry_n_5 ),
.I1(\B[2]__0 ),
.I2(\C[2]__0_0 ),
.O(i___0_carry_i_1__0_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_1__1
(.I0(\B[7]__6 [2]),
.I1(\C[2]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry_n_5 ),
.O(i___0_carry_i_1__1_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_1__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_5 ),
.I1(\B[2]__4 ),
.I2(\C[2]__2_0 ),
.O(i___0_carry_i_1__2_n_0));
(* HLUTNM = "lutpair28" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_1__3
(.I0(\B[7]__10 [2]),
.I1(\C[2]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry_n_5 ),
.O(i___0_carry_i_1__3_n_0));
(* HLUTNM = "lutpair34" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_1__4
(.I0(\C[2]__4_0 ),
.I1(PCIN[2]),
.I2(\B[2]__8 ),
.O(i___0_carry_i_1__4_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_2
(.I0(Q[1]),
.I1(\C[7] [1]),
.I2(rgb_blur3__82_carry_n_6),
.O(i___0_carry_i_2_n_0));
(* HLUTNM = "lutpair7" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_2__0
(.I0(\B[1]__0 ),
.I1(\C[1]__0_0 ),
.I2(\rgb_blur3_inferred__0/i___0_carry_n_6 ),
.O(i___0_carry_i_2__0_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_2__1
(.I0(\B[7]__6 [1]),
.I1(\C[1]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry_n_6 ),
.O(i___0_carry_i_2__1_n_0));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_2__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_6 ),
.I1(\B[1]__4 ),
.I2(\C[1]__2_0 ),
.O(i___0_carry_i_2__2_n_0));
(* HLUTNM = "lutpair27" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_2__3
(.I0(\B[7]__10 [1]),
.I1(\C[1]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry_n_6 ),
.O(i___0_carry_i_2__3_n_0));
(* HLUTNM = "lutpair33" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_2__4
(.I0(\C[1]__4_0 ),
.I1(PCIN[1]),
.I2(\B[1]__8 ),
.O(i___0_carry_i_2__4_n_0));
(* HLUTNM = "lutpair0" *)
LUT2 #(
.INIT(4'h8))
i___0_carry_i_3
(.I0(\C[7] [0]),
.I1(Q[0]),
.O(i___0_carry_i_3_n_0));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_3__0
(.I0(\C[0]__0_0 ),
.I1(\B[0] ),
.I2(\rgb_blur3_inferred__0/i___0_carry_n_7 ),
.O(i___0_carry_i_3__0_n_0));
(* HLUTNM = "lutpair13" *)
LUT2 #(
.INIT(4'h8))
i___0_carry_i_3__1
(.I0(\B[7]__6 [0]),
.I1(\C[0]__1 ),
.O(i___0_carry_i_3__1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_3__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_7 ),
.I1(\B[0]__3 ),
.I2(\C[0]__2_0 ),
.O(i___0_carry_i_3__2_n_0));
(* HLUTNM = "lutpair26" *)
LUT2 #(
.INIT(4'h8))
i___0_carry_i_3__3
(.I0(\B[7]__10 [0]),
.I1(\C[0]__3 ),
.O(i___0_carry_i_3__3_n_0));
(* HLUTNM = "lutpair32" *)
LUT3 #(
.INIT(8'hE8))
i___0_carry_i_3__4
(.I0(PCIN[0]),
.I1(\B[0]__7 ),
.I2(\C[0]__4_0 ),
.O(i___0_carry_i_3__4_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_4
(.I0(Q[3]),
.I1(\C[7] [3]),
.I2(rgb_blur3__82_carry_n_4),
.I3(i___0_carry_i_1_n_0),
.O(i___0_carry_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_4__0
(.I0(\rgb_blur3_inferred__0/i___0_carry_n_4 ),
.I1(\B[3]__0 ),
.I2(\C[3]__0_0 ),
.I3(i___0_carry_i_1__0_n_0),
.O(i___0_carry_i_4__0_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_4__1
(.I0(\B[7]__6 [3]),
.I1(\C[3]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry_n_4 ),
.I3(i___0_carry_i_1__1_n_0),
.O(i___0_carry_i_4__1_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_4__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_4 ),
.I1(\B[3]__4 ),
.I2(\C[3]__2_0 ),
.I3(i___0_carry_i_1__2_n_0),
.O(i___0_carry_i_4__2_n_0));
(* HLUTNM = "lutpair29" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_4__3
(.I0(\B[7]__10 [3]),
.I1(\C[3]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry_n_4 ),
.I3(i___0_carry_i_1__3_n_0),
.O(i___0_carry_i_4__3_n_0));
(* HLUTNM = "lutpair35" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_4__4
(.I0(\C[3]__4_0 ),
.I1(PCIN[3]),
.I2(\B[3]__8 ),
.I3(i___0_carry_i_1__4_n_0),
.O(i___0_carry_i_4__4_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_5
(.I0(Q[2]),
.I1(\C[7] [2]),
.I2(rgb_blur3__82_carry_n_5),
.I3(i___0_carry_i_2_n_0),
.O(i___0_carry_i_5_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_5__0
(.I0(\rgb_blur3_inferred__0/i___0_carry_n_5 ),
.I1(\B[2]__0 ),
.I2(\C[2]__0_0 ),
.I3(i___0_carry_i_2__0_n_0),
.O(i___0_carry_i_5__0_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_5__1
(.I0(\B[7]__6 [2]),
.I1(\C[2]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry_n_5 ),
.I3(i___0_carry_i_2__1_n_0),
.O(i___0_carry_i_5__1_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_5__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_5 ),
.I1(\B[2]__4 ),
.I2(\C[2]__2_0 ),
.I3(i___0_carry_i_2__2_n_0),
.O(i___0_carry_i_5__2_n_0));
(* HLUTNM = "lutpair28" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_5__3
(.I0(\B[7]__10 [2]),
.I1(\C[2]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry_n_5 ),
.I3(i___0_carry_i_2__3_n_0),
.O(i___0_carry_i_5__3_n_0));
(* HLUTNM = "lutpair34" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_5__4
(.I0(\C[2]__4_0 ),
.I1(PCIN[2]),
.I2(\B[2]__8 ),
.I3(i___0_carry_i_2__4_n_0),
.O(i___0_carry_i_5__4_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_6
(.I0(Q[1]),
.I1(\C[7] [1]),
.I2(rgb_blur3__82_carry_n_6),
.I3(i___0_carry_i_3_n_0),
.O(i___0_carry_i_6_n_0));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_6__0
(.I0(\B[1]__0 ),
.I1(\C[1]__0_0 ),
.I2(\rgb_blur3_inferred__0/i___0_carry_n_6 ),
.I3(i___0_carry_i_3__0_n_0),
.O(i___0_carry_i_6__0_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_6__1
(.I0(\B[7]__6 [1]),
.I1(\C[1]__1 ),
.I2(\rgb_blur3_inferred__2/i___82_carry_n_6 ),
.I3(i___0_carry_i_3__1_n_0),
.O(i___0_carry_i_6__1_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_6__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_6 ),
.I1(\B[1]__4 ),
.I2(\C[1]__2_0 ),
.I3(i___0_carry_i_3__2_n_0),
.O(i___0_carry_i_6__2_n_0));
(* HLUTNM = "lutpair27" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_6__3
(.I0(\B[7]__10 [1]),
.I1(\C[1]__3 ),
.I2(\rgb_blur3_inferred__5/i___82_carry_n_6 ),
.I3(i___0_carry_i_3__3_n_0),
.O(i___0_carry_i_6__3_n_0));
(* HLUTNM = "lutpair33" *)
LUT4 #(
.INIT(16'h6996))
i___0_carry_i_6__4
(.I0(\C[1]__4_0 ),
.I1(PCIN[1]),
.I2(\B[1]__8 ),
.I3(i___0_carry_i_3__4_n_0),
.O(i___0_carry_i_6__4_n_0));
(* HLUTNM = "lutpair0" *)
LUT2 #(
.INIT(4'h6))
i___0_carry_i_7
(.I0(\C[7] [0]),
.I1(Q[0]),
.O(i___0_carry_i_7_n_0));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'h96))
i___0_carry_i_7__0
(.I0(\C[0]__0_0 ),
.I1(\B[0] ),
.I2(\rgb_blur3_inferred__0/i___0_carry_n_7 ),
.O(i___0_carry_i_7__0_n_0));
(* HLUTNM = "lutpair13" *)
LUT2 #(
.INIT(4'h6))
i___0_carry_i_7__1
(.I0(\B[7]__6 [0]),
.I1(\C[0]__1 ),
.O(i___0_carry_i_7__1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'h96))
i___0_carry_i_7__2
(.I0(\rgb_blur3_inferred__3/i___0_carry_n_7 ),
.I1(\B[0]__3 ),
.I2(\C[0]__2_0 ),
.O(i___0_carry_i_7__2_n_0));
(* HLUTNM = "lutpair26" *)
LUT2 #(
.INIT(4'h6))
i___0_carry_i_7__3
(.I0(\B[7]__10 [0]),
.I1(\C[0]__3 ),
.O(i___0_carry_i_7__3_n_0));
(* HLUTNM = "lutpair32" *)
LUT3 #(
.INIT(8'h96))
i___0_carry_i_7__4
(.I0(PCIN[0]),
.I1(\B[0]__7 ),
.I2(\C[0]__4_0 ),
.O(i___0_carry_i_7__4_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_1
(.I0(D[14]),
.I1(\rgb_blur3_inferred__2/i__carry__1_n_7 ),
.O(i___24_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_1__0
(.I0(D[22]),
.I1(\rgb_blur3_inferred__5/i__carry__1_n_7 ),
.O(i___24_carry__0_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_2
(.I0(D[13]),
.I1(\rgb_blur3_inferred__2/i__carry__0_n_4 ),
.O(i___24_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_2__0
(.I0(D[21]),
.I1(\rgb_blur3_inferred__5/i__carry__0_n_4 ),
.O(i___24_carry__0_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_3
(.I0(D[12]),
.I1(\rgb_blur3_inferred__2/i__carry__0_n_5 ),
.O(i___24_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_3__0
(.I0(D[20]),
.I1(\rgb_blur3_inferred__5/i__carry__0_n_5 ),
.O(i___24_carry__0_i_3__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_4
(.I0(D[11]),
.I1(\rgb_blur3_inferred__2/i__carry__0_n_6 ),
.O(i___24_carry__0_i_4_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__0_i_4__0
(.I0(D[19]),
.I1(\rgb_blur3_inferred__5/i__carry__0_n_6 ),
.O(i___24_carry__0_i_4__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__1_i_1
(.I0(D[15]),
.I1(\rgb_blur3_inferred__2/i__carry__1_n_2 ),
.O(i___24_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry__1_i_1__0
(.I0(D[23]),
.I1(\rgb_blur3_inferred__5/i__carry__1_n_2 ),
.O(i___24_carry__1_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry_i_1
(.I0(D[10]),
.I1(\rgb_blur3_inferred__2/i__carry__0_n_7 ),
.O(i___24_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry_i_1__0
(.I0(D[18]),
.I1(\rgb_blur3_inferred__5/i__carry__0_n_7 ),
.O(i___24_carry_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry_i_2
(.I0(D[9]),
.I1(\rgb_blur3_inferred__2/i__carry_n_4 ),
.O(i___24_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry_i_2__0
(.I0(D[17]),
.I1(\rgb_blur3_inferred__5/i__carry_n_4 ),
.O(i___24_carry_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry_i_3
(.I0(D[8]),
.I1(\rgb_blur3_inferred__2/i__carry_n_5 ),
.O(i___24_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
i___24_carry_i_3__0
(.I0(D[16]),
.I1(\rgb_blur3_inferred__5/i__carry_n_5 ),
.O(i___24_carry_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___24_carry_i_4
(.I0(\rgb_blur3_inferred__2/i__carry_n_6 ),
.O(i___24_carry_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___24_carry_i_4__0
(.I0(\rgb_blur3_inferred__5/i__carry_n_6 ),
.O(i___24_carry_i_4__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_1
(.I0(I6[6]),
.I1(\rgb_blur3_inferred__2/i___24_carry__0_n_5 ),
.O(i___50_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_1__0
(.I0(I12[6]),
.I1(\rgb_blur3_inferred__5/i___24_carry__0_n_5 ),
.O(i___50_carry__0_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_2
(.I0(I6[5]),
.I1(\rgb_blur3_inferred__2/i___24_carry__0_n_6 ),
.O(i___50_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_2__0
(.I0(I12[5]),
.I1(\rgb_blur3_inferred__5/i___24_carry__0_n_6 ),
.O(i___50_carry__0_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_3
(.I0(I6[4]),
.I1(\rgb_blur3_inferred__2/i___24_carry__0_n_7 ),
.O(i___50_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_3__0
(.I0(I12[4]),
.I1(\rgb_blur3_inferred__5/i___24_carry__0_n_7 ),
.O(i___50_carry__0_i_3__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_4
(.I0(I6[3]),
.I1(\rgb_blur3_inferred__2/i___24_carry_n_4 ),
.O(i___50_carry__0_i_4_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__0_i_4__0
(.I0(I12[3]),
.I1(\rgb_blur3_inferred__5/i___24_carry_n_4 ),
.O(i___50_carry__0_i_4__0_n_0));
LUT1 #(
.INIT(2'h1))
i___50_carry__1_i_1
(.I0(\rgb_blur3_inferred__2/i___24_carry__1_n_7 ),
.O(i___50_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
i___50_carry__1_i_1__0
(.I0(\rgb_blur3_inferred__5/i___24_carry__1_n_7 ),
.O(i___50_carry__1_i_1__0_n_0));
LUT1 #(
.INIT(2'h1))
i___50_carry__1_i_2
(.I0(\rgb_blur3_inferred__2/i___24_carry__1_n_2 ),
.O(i___50_carry__1_i_2_n_0));
LUT1 #(
.INIT(2'h1))
i___50_carry__1_i_2__0
(.I0(\rgb_blur3_inferred__5/i___24_carry__1_n_2 ),
.O(i___50_carry__1_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
i___50_carry__1_i_3
(.I0(\rgb_blur3_inferred__2/i___24_carry__1_n_7 ),
.I1(\rgb_blur3_inferred__2/i___24_carry__1_n_2 ),
.O(i___50_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
i___50_carry__1_i_3__0
(.I0(\rgb_blur3_inferred__5/i___24_carry__1_n_7 ),
.I1(\rgb_blur3_inferred__5/i___24_carry__1_n_2 ),
.O(i___50_carry__1_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___50_carry__1_i_4
(.I0(\rgb_blur3_inferred__2/i___24_carry__1_n_7 ),
.O(i___50_carry__1_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___50_carry__1_i_4__0
(.I0(\rgb_blur3_inferred__5/i___24_carry__1_n_7 ),
.O(i___50_carry__1_i_4__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__1_i_5
(.I0(I6[7]),
.I1(\rgb_blur3_inferred__2/i___24_carry__0_n_4 ),
.O(i___50_carry__1_i_5_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry__1_i_5__0
(.I0(I12[7]),
.I1(\rgb_blur3_inferred__5/i___24_carry__0_n_4 ),
.O(i___50_carry__1_i_5__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry_i_1
(.I0(I6[2]),
.I1(\rgb_blur3_inferred__2/i___24_carry_n_5 ),
.O(i___50_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry_i_1__0
(.I0(I12[2]),
.I1(\rgb_blur3_inferred__5/i___24_carry_n_5 ),
.O(i___50_carry_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry_i_2
(.I0(I6[1]),
.I1(\rgb_blur3_inferred__2/i___24_carry_n_6 ),
.O(i___50_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry_i_2__0
(.I0(I12[1]),
.I1(\rgb_blur3_inferred__5/i___24_carry_n_6 ),
.O(i___50_carry_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry_i_3
(.I0(I6[0]),
.I1(\rgb_blur3_inferred__2/i___24_carry_n_7 ),
.O(i___50_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
i___50_carry_i_3__0
(.I0(I12[0]),
.I1(\rgb_blur3_inferred__5/i___24_carry_n_7 ),
.O(i___50_carry_i_3__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_1
(.I0(I7[6]),
.I1(C__0[7]),
.O(i___82_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_1__0
(.I0(I13[6]),
.I1(C__1[7]),
.O(i___82_carry__0_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_2
(.I0(I7[5]),
.I1(C__0[6]),
.O(i___82_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_2__0
(.I0(I13[5]),
.I1(C__1[6]),
.O(i___82_carry__0_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_3
(.I0(I7[4]),
.I1(C__0[5]),
.O(i___82_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_3__0
(.I0(I13[4]),
.I1(C__1[5]),
.O(i___82_carry__0_i_3__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_4
(.I0(I7[3]),
.I1(C__0[4]),
.O(i___82_carry__0_i_4_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__0_i_4__0
(.I0(I13[3]),
.I1(C__1[4]),
.O(i___82_carry__0_i_4__0_n_0));
LUT1 #(
.INIT(2'h1))
i___82_carry__1_i_1
(.I0(C__0[9]),
.O(i___82_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
i___82_carry__1_i_1__0
(.I0(C__1[9]),
.O(i___82_carry__1_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
i___82_carry__1_i_2
(.I0(C__0[10]),
.I1(C__0[11]),
.O(i___82_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i___82_carry__1_i_2__0
(.I0(C__1[10]),
.I1(C__1[11]),
.O(i___82_carry__1_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
i___82_carry__1_i_3
(.I0(C__0[9]),
.I1(C__0[10]),
.O(i___82_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
i___82_carry__1_i_3__0
(.I0(C__1[9]),
.I1(C__1[10]),
.O(i___82_carry__1_i_3__0_n_0));
LUT1 #(
.INIT(2'h2))
i___82_carry__1_i_4
(.I0(C__0[9]),
.O(i___82_carry__1_i_4_n_0));
LUT1 #(
.INIT(2'h2))
i___82_carry__1_i_4__0
(.I0(C__1[9]),
.O(i___82_carry__1_i_4__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__1_i_5
(.I0(I7[7]),
.I1(C__0[8]),
.O(i___82_carry__1_i_5_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__1_i_5__0
(.I0(I13[7]),
.I1(C__1[8]),
.O(i___82_carry__1_i_5__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__2_i_1
(.I0(C__0[11]),
.I1(i___82_carry__2_i_2_n_3),
.O(i___82_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry__2_i_1__0
(.I0(C__1[11]),
.I1(i___82_carry__2_i_2__0_n_3),
.O(i___82_carry__2_i_1__0_n_0));
CARRY4 i___82_carry__2_i_2
(.CI(\rgb_blur3_inferred__2/i___50_carry__1_n_0 ),
.CO({NLW_i___82_carry__2_i_2_CO_UNCONNECTED[3:1],i___82_carry__2_i_2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_i___82_carry__2_i_2_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
CARRY4 i___82_carry__2_i_2__0
(.CI(\rgb_blur3_inferred__5/i___50_carry__1_n_0 ),
.CO({NLW_i___82_carry__2_i_2__0_CO_UNCONNECTED[3:1],i___82_carry__2_i_2__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_i___82_carry__2_i_2__0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
LUT2 #(
.INIT(4'h6))
i___82_carry_i_1
(.I0(I7[2]),
.I1(C__0[3]),
.O(i___82_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry_i_1__0
(.I0(I13[2]),
.I1(C__1[3]),
.O(i___82_carry_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry_i_2
(.I0(I7[1]),
.I1(C__0[2]),
.O(i___82_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry_i_2__0
(.I0(I13[1]),
.I1(C__1[2]),
.O(i___82_carry_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry_i_3
(.I0(I7[0]),
.I1(C__0[1]),
.O(i___82_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
i___82_carry_i_3__0
(.I0(I13[0]),
.I1(C__1[1]),
.O(i___82_carry_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__2_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__2_n_5 ),
.O(i__carry__0_i_1_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_1__0
(.I0(rgb_blur3[14]),
.I1(rgb_blur3[15]),
.O(i__carry__0_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_1__1
(.I0(\rgb_buffer_reg[642] [14]),
.I1(\B[7]__5 [6]),
.O(i__carry__0_i_1__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_1__2
(.I0(\rgb_buffer_reg[642] [22]),
.I1(\B[7]__9 [6]),
.O(i__carry__0_i_1__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_2
(.I0(\rgb_blur3_inferred__4/i___0_carry__2_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__2_n_7 ),
.O(i__carry__0_i_2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_2__0
(.I0(rgb_blur3[12]),
.I1(rgb_blur3[13]),
.O(i__carry__0_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_2__1
(.I0(\rgb_buffer_reg[642] [13]),
.I1(\B[7]__5 [5]),
.O(i__carry__0_i_2__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_2__2
(.I0(\rgb_buffer_reg[642] [21]),
.I1(\B[7]__9 [5]),
.O(i__carry__0_i_2__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_3
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__1_n_5 ),
.O(i__carry__0_i_3_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_3__0
(.I0(rgb_blur3[11]),
.I1(rgb_blur3[10]),
.O(i__carry__0_i_3__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_3__1
(.I0(\rgb_buffer_reg[642] [12]),
.I1(\B[7]__5 [4]),
.O(i__carry__0_i_3__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_3__2
(.I0(\rgb_buffer_reg[642] [20]),
.I1(\B[7]__9 [4]),
.O(i__carry__0_i_3__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_4
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__1_n_6 ),
.O(i__carry__0_i_4_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__0_i_4__0
(.I0(rgb_blur3[8]),
.I1(rgb_blur3[9]),
.O(i__carry__0_i_4__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_4__1
(.I0(\rgb_buffer_reg[642] [11]),
.I1(\B[7]__5 [3]),
.O(i__carry__0_i_4__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__0_i_4__2
(.I0(\rgb_buffer_reg[642] [19]),
.I1(\B[7]__9 [3]),
.O(i__carry__0_i_4__2_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry__2_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__2_n_4 ),
.O(i__carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_5__0
(.I0(rgb_blur3[15]),
.I1(rgb_blur3[14]),
.O(i__carry__0_i_5__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry__2_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__2_n_6 ),
.O(i__carry__0_i_6_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_6__0
(.I0(rgb_blur3[13]),
.I1(rgb_blur3[12]),
.O(i__carry__0_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__1_n_4 ),
.O(i__carry__0_i_7_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_7__0
(.I0(rgb_blur3[10]),
.I1(rgb_blur3[11]),
.O(i__carry__0_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_8
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.O(i__carry__0_i_8_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__0_i_8__0
(.I0(rgb_blur3[9]),
.I1(rgb_blur3[8]),
.O(i__carry__0_i_8__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__4_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__4_n_5 ),
.O(i__carry__1_i_1_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_1__0
(.I0(rgb_blur3[22]),
.I1(rgb_blur3[23]),
.O(i__carry__1_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__1_i_1__1
(.I0(\rgb_buffer_reg[642] [15]),
.I1(\B[7]__5 [7]),
.O(i__carry__1_i_1__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry__1_i_1__2
(.I0(\rgb_buffer_reg[642] [23]),
.I1(\B[7]__9 [7]),
.O(i__carry__1_i_1__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_2
(.I0(\rgb_blur3_inferred__4/i___0_carry__4_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__4_n_7 ),
.O(i__carry__1_i_2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_2__0
(.I0(rgb_blur3[20]),
.I1(rgb_blur3[21]),
.O(i__carry__1_i_2__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_3
(.I0(\rgb_blur3_inferred__4/i___0_carry__3_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__3_n_5 ),
.O(i__carry__1_i_3_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_3__0
(.I0(rgb_blur3[18]),
.I1(rgb_blur3[19]),
.O(i__carry__1_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_4
(.I0(\rgb_blur3_inferred__4/i___0_carry__3_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__3_n_7 ),
.O(i__carry__1_i_4_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__1_i_4__0
(.I0(rgb_blur3[16]),
.I1(rgb_blur3[17]),
.O(i__carry__1_i_4__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry__4_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__4_n_4 ),
.O(i__carry__1_i_5_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_5__0
(.I0(rgb_blur3[23]),
.I1(rgb_blur3[22]),
.O(i__carry__1_i_5__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry__4_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__4_n_6 ),
.O(i__carry__1_i_6_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_6__0
(.I0(rgb_blur3[21]),
.I1(rgb_blur3[20]),
.O(i__carry__1_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry__3_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__3_n_4 ),
.O(i__carry__1_i_7_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_7__0
(.I0(rgb_blur3[19]),
.I1(rgb_blur3[18]),
.O(i__carry__1_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_8
(.I0(\rgb_blur3_inferred__4/i___0_carry__3_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__3_n_6 ),
.O(i__carry__1_i_8_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__1_i_8__0
(.I0(rgb_blur3[17]),
.I1(rgb_blur3[16]),
.O(i__carry__1_i_8__0_n_0));
LUT2 #(
.INIT(4'h2))
i__carry__2_i_1
(.I0(rgb_blur3[30]),
.I1(rgb_blur3[31]),
.O(i__carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h2))
i__carry__2_i_1__0
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.O(i__carry__2_i_1__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__2_i_2
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__6_n_7 ),
.O(i__carry__2_i_2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__2_i_2__0
(.I0(rgb_blur3[28]),
.I1(rgb_blur3[29]),
.O(i__carry__2_i_2__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__2_i_3
(.I0(\rgb_blur3_inferred__4/i___0_carry__5_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__5_n_4 ),
.O(i__carry__2_i_3_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__2_i_3__0
(.I0(rgb_blur3[26]),
.I1(rgb_blur3[27]),
.O(i__carry__2_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__2_i_4
(.I0(\rgb_blur3_inferred__4/i___0_carry__5_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__5_n_7 ),
.O(i__carry__2_i_4_n_0));
LUT2 #(
.INIT(4'hE))
i__carry__2_i_4__0
(.I0(rgb_blur3[24]),
.I1(rgb_blur3[25]),
.O(i__carry__2_i_4__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__6_n_5 ),
.O(i__carry__2_i_5_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_5__0
(.I0(rgb_blur3[30]),
.I1(rgb_blur3[31]),
.O(i__carry__2_i_5__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__6_n_6 ),
.O(i__carry__2_i_6_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_6__0
(.I0(rgb_blur3[29]),
.I1(rgb_blur3[28]),
.O(i__carry__2_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry__5_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__5_n_5 ),
.O(i__carry__2_i_7_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_7__0
(.I0(rgb_blur3[27]),
.I1(rgb_blur3[26]),
.O(i__carry__2_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_8
(.I0(\rgb_blur3_inferred__4/i___0_carry__5_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__5_n_6 ),
.O(i__carry__2_i_8_n_0));
LUT2 #(
.INIT(4'h1))
i__carry__2_i_8__0
(.I0(rgb_blur3[25]),
.I1(rgb_blur3[24]),
.O(i__carry__2_i_8__0_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__0_n_4 ),
.O(i__carry_i_1_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_1__0
(.I0(rgb_blur3[6]),
.I1(rgb_blur3[7]),
.O(i__carry_i_1__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry_i_1__1
(.I0(\rgb_buffer_reg[642] [10]),
.I1(\B[7]__5 [2]),
.O(i__carry_i_1__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry_i_1__2
(.I0(\rgb_buffer_reg[642] [18]),
.I1(\B[7]__9 [2]),
.O(i__carry_i_1__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_2
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__0_n_6 ),
.O(i__carry_i_2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_2__0
(.I0(rgb_blur3[4]),
.I1(rgb_blur3[5]),
.O(i__carry_i_2__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry_i_2__1
(.I0(\rgb_buffer_reg[642] [9]),
.I1(\B[7]__5 [1]),
.O(i__carry_i_2__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry_i_2__2
(.I0(\rgb_buffer_reg[642] [17]),
.I1(\B[7]__9 [1]),
.O(i__carry_i_2__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_3
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_5 ),
.I1(\rgb_blur3_inferred__4/i___0_carry_n_4 ),
.O(i__carry_i_3_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_3__0
(.I0(rgb_blur3[2]),
.I1(rgb_blur3[3]),
.O(i__carry_i_3__0_n_0));
LUT2 #(
.INIT(4'h6))
i__carry_i_3__1
(.I0(\rgb_buffer_reg[642] [8]),
.I1(\B[7]__5 [0]),
.O(i__carry_i_3__1_n_0));
LUT2 #(
.INIT(4'h6))
i__carry_i_3__2
(.I0(\rgb_buffer_reg[642] [16]),
.I1(\B[7]__9 [0]),
.O(i__carry_i_3__2_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_4
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry_n_7 ),
.O(i__carry_i_4_n_0));
LUT2 #(
.INIT(4'hE))
i__carry_i_4__0
(.I0(rgb_blur3[0]),
.I1(rgb_blur3[1]),
.O(i__carry_i_4__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__0_n_5 ),
.O(i__carry_i_5_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_5__0
(.I0(rgb_blur3[7]),
.I1(rgb_blur3[6]),
.O(i__carry_i_5__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_6 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.O(i__carry_i_6_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_6__0
(.I0(rgb_blur3[5]),
.I1(rgb_blur3[4]),
.O(i__carry_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_4 ),
.I1(\rgb_blur3_inferred__4/i___0_carry_n_5 ),
.O(i__carry_i_7_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_7__0
(.I0(rgb_blur3[3]),
.I1(rgb_blur3[2]),
.O(i__carry_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_8
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry_n_6 ),
.O(i__carry_i_8_n_0));
LUT2 #(
.INIT(4'h1))
i__carry_i_8__0
(.I0(rgb_blur3[1]),
.I1(rgb_blur3[0]),
.O(i__carry_i_8__0_n_0));
CARRY4 rgb_blur3__24_carry
(.CI(1'b0),
.CO({rgb_blur3__24_carry_n_0,rgb_blur3__24_carry_n_1,rgb_blur3__24_carry_n_2,rgb_blur3__24_carry_n_3}),
.CYINIT(1'b0),
.DI({D[2:0],1'b0}),
.O({rgb_blur3__24_carry_n_4,rgb_blur3__24_carry_n_5,rgb_blur3__24_carry_n_6,rgb_blur3__24_carry_n_7}),
.S({rgb_blur3__24_carry_i_1_n_0,rgb_blur3__24_carry_i_2_n_0,rgb_blur3__24_carry_i_3_n_0,rgb_blur3__24_carry_i_4_n_0}));
CARRY4 rgb_blur3__24_carry__0
(.CI(rgb_blur3__24_carry_n_0),
.CO({rgb_blur3__24_carry__0_n_0,rgb_blur3__24_carry__0_n_1,rgb_blur3__24_carry__0_n_2,rgb_blur3__24_carry__0_n_3}),
.CYINIT(1'b0),
.DI(D[6:3]),
.O({rgb_blur3__24_carry__0_n_4,rgb_blur3__24_carry__0_n_5,rgb_blur3__24_carry__0_n_6,rgb_blur3__24_carry__0_n_7}),
.S({rgb_blur3__24_carry__0_i_1_n_0,rgb_blur3__24_carry__0_i_2_n_0,rgb_blur3__24_carry__0_i_3_n_0,rgb_blur3__24_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry__0_i_1
(.I0(D[6]),
.I1(rgb_blur3_carry__1_n_7),
.O(rgb_blur3__24_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry__0_i_2
(.I0(D[5]),
.I1(rgb_blur3_carry__0_n_4),
.O(rgb_blur3__24_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry__0_i_3
(.I0(D[4]),
.I1(rgb_blur3_carry__0_n_5),
.O(rgb_blur3__24_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry__0_i_4
(.I0(D[3]),
.I1(rgb_blur3_carry__0_n_6),
.O(rgb_blur3__24_carry__0_i_4_n_0));
CARRY4 rgb_blur3__24_carry__1
(.CI(rgb_blur3__24_carry__0_n_0),
.CO({NLW_rgb_blur3__24_carry__1_CO_UNCONNECTED[3:2],rgb_blur3__24_carry__1_n_2,NLW_rgb_blur3__24_carry__1_CO_UNCONNECTED[0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,D[7]}),
.O({NLW_rgb_blur3__24_carry__1_O_UNCONNECTED[3:1],rgb_blur3__24_carry__1_n_7}),
.S({1'b0,1'b0,1'b1,rgb_blur3__24_carry__1_i_1_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry__1_i_1
(.I0(D[7]),
.I1(rgb_blur3_carry__1_n_2),
.O(rgb_blur3__24_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry_i_1
(.I0(D[2]),
.I1(rgb_blur3_carry__0_n_7),
.O(rgb_blur3__24_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry_i_2
(.I0(D[1]),
.I1(rgb_blur3_carry_n_4),
.O(rgb_blur3__24_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__24_carry_i_3
(.I0(D[0]),
.I1(rgb_blur3_carry_n_5),
.O(rgb_blur3__24_carry_i_3_n_0));
LUT1 #(
.INIT(2'h2))
rgb_blur3__24_carry_i_4
(.I0(rgb_blur3_carry_n_6),
.O(rgb_blur3__24_carry_i_4_n_0));
CARRY4 rgb_blur3__50_carry
(.CI(1'b0),
.CO({rgb_blur3__50_carry_n_0,rgb_blur3__50_carry_n_1,rgb_blur3__50_carry_n_2,rgb_blur3__50_carry_n_3}),
.CYINIT(1'b0),
.DI({rgb_blur9[2:0],1'b0}),
.O({C[3:1],NLW_rgb_blur3__50_carry_O_UNCONNECTED[0]}),
.S({rgb_blur3__50_carry_i_1_n_0,rgb_blur3__50_carry_i_2_n_0,rgb_blur3__50_carry_i_3_n_0,1'b0}));
CARRY4 rgb_blur3__50_carry__0
(.CI(rgb_blur3__50_carry_n_0),
.CO({rgb_blur3__50_carry__0_n_0,rgb_blur3__50_carry__0_n_1,rgb_blur3__50_carry__0_n_2,rgb_blur3__50_carry__0_n_3}),
.CYINIT(1'b0),
.DI(rgb_blur9[6:3]),
.O(C[7:4]),
.S({rgb_blur3__50_carry__0_i_1_n_0,rgb_blur3__50_carry__0_i_2_n_0,rgb_blur3__50_carry__0_i_3_n_0,rgb_blur3__50_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry__0_i_1
(.I0(rgb_blur9[6]),
.I1(rgb_blur3__24_carry__0_n_5),
.O(rgb_blur3__50_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry__0_i_2
(.I0(rgb_blur9[5]),
.I1(rgb_blur3__24_carry__0_n_6),
.O(rgb_blur3__50_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry__0_i_3
(.I0(rgb_blur9[4]),
.I1(rgb_blur3__24_carry__0_n_7),
.O(rgb_blur3__50_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry__0_i_4
(.I0(rgb_blur9[3]),
.I1(rgb_blur3__24_carry_n_4),
.O(rgb_blur3__50_carry__0_i_4_n_0));
CARRY4 rgb_blur3__50_carry__1
(.CI(rgb_blur3__50_carry__0_n_0),
.CO({rgb_blur3__50_carry__1_n_0,rgb_blur3__50_carry__1_n_1,rgb_blur3__50_carry__1_n_2,rgb_blur3__50_carry__1_n_3}),
.CYINIT(1'b0),
.DI({rgb_blur3__24_carry__1_n_2,rgb_blur3__24_carry__1_n_7,rgb_blur3__50_carry__1_i_1_n_0,rgb_blur9[7]}),
.O(C[11:8]),
.S({rgb_blur3__50_carry__1_i_2_n_0,rgb_blur3__50_carry__1_i_3_n_0,rgb_blur3__50_carry__1_i_4_n_0,rgb_blur3__50_carry__1_i_5_n_0}));
LUT1 #(
.INIT(2'h1))
rgb_blur3__50_carry__1_i_1
(.I0(rgb_blur3__24_carry__1_n_7),
.O(rgb_blur3__50_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h1))
rgb_blur3__50_carry__1_i_2
(.I0(rgb_blur3__24_carry__1_n_2),
.O(rgb_blur3__50_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
rgb_blur3__50_carry__1_i_3
(.I0(rgb_blur3__24_carry__1_n_7),
.I1(rgb_blur3__24_carry__1_n_2),
.O(rgb_blur3__50_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h2))
rgb_blur3__50_carry__1_i_4
(.I0(rgb_blur3__24_carry__1_n_7),
.O(rgb_blur3__50_carry__1_i_4_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry__1_i_5
(.I0(rgb_blur9[7]),
.I1(rgb_blur3__24_carry__0_n_4),
.O(rgb_blur3__50_carry__1_i_5_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry_i_1
(.I0(rgb_blur9[2]),
.I1(rgb_blur3__24_carry_n_5),
.O(rgb_blur3__50_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry_i_2
(.I0(rgb_blur9[1]),
.I1(rgb_blur3__24_carry_n_6),
.O(rgb_blur3__50_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__50_carry_i_3
(.I0(rgb_blur9[0]),
.I1(rgb_blur3__24_carry_n_7),
.O(rgb_blur3__50_carry_i_3_n_0));
CARRY4 rgb_blur3__82_carry
(.CI(1'b0),
.CO({rgb_blur3__82_carry_n_0,rgb_blur3__82_carry_n_1,rgb_blur3__82_carry_n_2,rgb_blur3__82_carry_n_3}),
.CYINIT(1'b0),
.DI({rgb_blur11[2:0],1'b0}),
.O({rgb_blur3__82_carry_n_4,rgb_blur3__82_carry_n_5,rgb_blur3__82_carry_n_6,NLW_rgb_blur3__82_carry_O_UNCONNECTED[0]}),
.S({rgb_blur3__82_carry_i_1_n_0,rgb_blur3__82_carry_i_2_n_0,rgb_blur3__82_carry_i_3_n_0,1'b0}));
CARRY4 rgb_blur3__82_carry__0
(.CI(rgb_blur3__82_carry_n_0),
.CO({rgb_blur3__82_carry__0_n_0,rgb_blur3__82_carry__0_n_1,rgb_blur3__82_carry__0_n_2,rgb_blur3__82_carry__0_n_3}),
.CYINIT(1'b0),
.DI(rgb_blur11[6:3]),
.O({rgb_blur3__82_carry__0_n_4,rgb_blur3__82_carry__0_n_5,rgb_blur3__82_carry__0_n_6,rgb_blur3__82_carry__0_n_7}),
.S({rgb_blur3__82_carry__0_i_1_n_0,rgb_blur3__82_carry__0_i_2_n_0,rgb_blur3__82_carry__0_i_3_n_0,rgb_blur3__82_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry__0_i_1
(.I0(rgb_blur11[6]),
.I1(C[7]),
.O(rgb_blur3__82_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry__0_i_2
(.I0(rgb_blur11[5]),
.I1(C[6]),
.O(rgb_blur3__82_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry__0_i_3
(.I0(rgb_blur11[4]),
.I1(C[5]),
.O(rgb_blur3__82_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry__0_i_4
(.I0(rgb_blur11[3]),
.I1(C[4]),
.O(rgb_blur3__82_carry__0_i_4_n_0));
CARRY4 rgb_blur3__82_carry__1
(.CI(rgb_blur3__82_carry__0_n_0),
.CO({rgb_blur3__82_carry__1_n_0,rgb_blur3__82_carry__1_n_1,rgb_blur3__82_carry__1_n_2,rgb_blur3__82_carry__1_n_3}),
.CYINIT(1'b0),
.DI({C[10:9],rgb_blur3__82_carry__1_i_1_n_0,rgb_blur11[7]}),
.O({rgb_blur3__82_carry__1_n_4,rgb_blur3__82_carry__1_n_5,rgb_blur3__82_carry__1_n_6,rgb_blur3__82_carry__1_n_7}),
.S({rgb_blur3__82_carry__1_i_2_n_0,rgb_blur3__82_carry__1_i_3_n_0,rgb_blur3__82_carry__1_i_4_n_0,rgb_blur3__82_carry__1_i_5_n_0}));
LUT1 #(
.INIT(2'h1))
rgb_blur3__82_carry__1_i_1
(.I0(C[9]),
.O(rgb_blur3__82_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
rgb_blur3__82_carry__1_i_2
(.I0(C[10]),
.I1(C[11]),
.O(rgb_blur3__82_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
rgb_blur3__82_carry__1_i_3
(.I0(C[9]),
.I1(C[10]),
.O(rgb_blur3__82_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h2))
rgb_blur3__82_carry__1_i_4
(.I0(C[9]),
.O(rgb_blur3__82_carry__1_i_4_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry__1_i_5
(.I0(rgb_blur11[7]),
.I1(C[8]),
.O(rgb_blur3__82_carry__1_i_5_n_0));
CARRY4 rgb_blur3__82_carry__2
(.CI(rgb_blur3__82_carry__1_n_0),
.CO({NLW_rgb_blur3__82_carry__2_CO_UNCONNECTED[3:2],rgb_blur3__82_carry__2_n_2,NLW_rgb_blur3__82_carry__2_CO_UNCONNECTED[0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,C[11]}),
.O({NLW_rgb_blur3__82_carry__2_O_UNCONNECTED[3:1],rgb_blur3__82_carry__2_n_7}),
.S({1'b0,1'b0,1'b1,rgb_blur3__82_carry__2_i_1_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry__2_i_1
(.I0(C[11]),
.I1(rgb_blur3__82_carry__2_i_2_n_3),
.O(rgb_blur3__82_carry__2_i_1_n_0));
CARRY4 rgb_blur3__82_carry__2_i_2
(.CI(rgb_blur3__50_carry__1_n_0),
.CO({NLW_rgb_blur3__82_carry__2_i_2_CO_UNCONNECTED[3:1],rgb_blur3__82_carry__2_i_2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_rgb_blur3__82_carry__2_i_2_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,1'b1}));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry_i_1
(.I0(rgb_blur11[2]),
.I1(C[3]),
.O(rgb_blur3__82_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry_i_2
(.I0(rgb_blur11[1]),
.I1(C[2]),
.O(rgb_blur3__82_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3__82_carry_i_3
(.I0(rgb_blur11[0]),
.I1(C[1]),
.O(rgb_blur3__82_carry_i_3_n_0));
CARRY4 rgb_blur3_carry
(.CI(1'b0),
.CO({rgb_blur3_carry_n_0,rgb_blur3_carry_n_1,rgb_blur3_carry_n_2,rgb_blur3_carry_n_3}),
.CYINIT(1'b0),
.DI({\rgb_buffer_reg[642] [2:0],1'b0}),
.O({rgb_blur3_carry_n_4,rgb_blur3_carry_n_5,rgb_blur3_carry_n_6,NLW_rgb_blur3_carry_O_UNCONNECTED[0]}),
.S({rgb_blur3_carry_i_1_n_0,rgb_blur3_carry_i_2_n_0,rgb_blur3_carry_i_3_n_0,1'b0}));
CARRY4 rgb_blur3_carry__0
(.CI(rgb_blur3_carry_n_0),
.CO({rgb_blur3_carry__0_n_0,rgb_blur3_carry__0_n_1,rgb_blur3_carry__0_n_2,rgb_blur3_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\rgb_buffer_reg[642] [6:3]),
.O({rgb_blur3_carry__0_n_4,rgb_blur3_carry__0_n_5,rgb_blur3_carry__0_n_6,rgb_blur3_carry__0_n_7}),
.S({rgb_blur3_carry__0_i_1_n_0,rgb_blur3_carry__0_i_2_n_0,rgb_blur3_carry__0_i_3_n_0,rgb_blur3_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry__0_i_1
(.I0(\rgb_buffer_reg[642] [6]),
.I1(\B[7]__1 [6]),
.O(rgb_blur3_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry__0_i_2
(.I0(\rgb_buffer_reg[642] [5]),
.I1(\B[7]__1 [5]),
.O(rgb_blur3_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry__0_i_3
(.I0(\rgb_buffer_reg[642] [4]),
.I1(\B[7]__1 [4]),
.O(rgb_blur3_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry__0_i_4
(.I0(\rgb_buffer_reg[642] [3]),
.I1(\B[7]__1 [3]),
.O(rgb_blur3_carry__0_i_4_n_0));
CARRY4 rgb_blur3_carry__1
(.CI(rgb_blur3_carry__0_n_0),
.CO({NLW_rgb_blur3_carry__1_CO_UNCONNECTED[3:2],rgb_blur3_carry__1_n_2,NLW_rgb_blur3_carry__1_CO_UNCONNECTED[0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\rgb_buffer_reg[642] [7]}),
.O({NLW_rgb_blur3_carry__1_O_UNCONNECTED[3:1],rgb_blur3_carry__1_n_7}),
.S({1'b0,1'b0,1'b1,rgb_blur3_carry__1_i_1_n_0}));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry__1_i_1
(.I0(\rgb_buffer_reg[642] [7]),
.I1(\B[7]__1 [7]),
.O(rgb_blur3_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry_i_1
(.I0(\rgb_buffer_reg[642] [2]),
.I1(\B[7]__1 [2]),
.O(rgb_blur3_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry_i_2
(.I0(\rgb_buffer_reg[642] [1]),
.I1(\B[7]__1 [1]),
.O(rgb_blur3_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
rgb_blur3_carry_i_3
(.I0(\rgb_buffer_reg[642] [0]),
.I1(\B[7]__1 [0]),
.O(rgb_blur3_carry_i_3_n_0));
CARRY4 \rgb_blur3_inferred__0/i___0_carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__0/i___0_carry_n_0 ,\rgb_blur3_inferred__0/i___0_carry_n_1 ,\rgb_blur3_inferred__0/i___0_carry_n_2 ,\rgb_blur3_inferred__0/i___0_carry_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry_i_1_n_0,i___0_carry_i_2_n_0,i___0_carry_i_3_n_0,1'b0}),
.O({\rgb_blur3_inferred__0/i___0_carry_n_4 ,\rgb_blur3_inferred__0/i___0_carry_n_5 ,\rgb_blur3_inferred__0/i___0_carry_n_6 ,\rgb_blur3_inferred__0/i___0_carry_n_7 }),
.S({i___0_carry_i_4_n_0,i___0_carry_i_5_n_0,i___0_carry_i_6_n_0,i___0_carry_i_7_n_0}));
CARRY4 \rgb_blur3_inferred__0/i___0_carry__0
(.CI(\rgb_blur3_inferred__0/i___0_carry_n_0 ),
.CO({\rgb_blur3_inferred__0/i___0_carry__0_n_0 ,\rgb_blur3_inferred__0/i___0_carry__0_n_1 ,\rgb_blur3_inferred__0/i___0_carry__0_n_2 ,\rgb_blur3_inferred__0/i___0_carry__0_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry__0_i_1_n_0,i___0_carry__0_i_2_n_0,i___0_carry__0_i_3_n_0,i___0_carry__0_i_4_n_0}),
.O({\rgb_blur3_inferred__0/i___0_carry__0_n_4 ,\rgb_blur3_inferred__0/i___0_carry__0_n_5 ,\rgb_blur3_inferred__0/i___0_carry__0_n_6 ,\rgb_blur3_inferred__0/i___0_carry__0_n_7 }),
.S({i___0_carry__0_i_5_n_0,i___0_carry__0_i_6_n_0,i___0_carry__0_i_7_n_0,i___0_carry__0_i_8_n_0}));
CARRY4 \rgb_blur3_inferred__0/i___0_carry__1
(.CI(\rgb_blur3_inferred__0/i___0_carry__0_n_0 ),
.CO({\rgb_blur3_inferred__0/i___0_carry__1_n_0 ,\rgb_blur3_inferred__0/i___0_carry__1_n_1 ,\rgb_blur3_inferred__0/i___0_carry__1_n_2 ,\rgb_blur3_inferred__0/i___0_carry__1_n_3 }),
.CYINIT(1'b0),
.DI({rgb_blur3__82_carry__1_n_5,rgb_blur3__82_carry__1_n_6,1'b1,rgb_blur3__82_carry__1_n_7}),
.O({\rgb_blur3_inferred__0/i___0_carry__1_n_4 ,\rgb_blur3_inferred__0/i___0_carry__1_n_5 ,\rgb_blur3_inferred__0/i___0_carry__1_n_6 ,\rgb_blur3_inferred__0/i___0_carry__1_n_7 }),
.S({i___0_carry__1_i_1_n_0,i___0_carry__1_i_2_n_0,i___0_carry__1_i_3_n_0,i___0_carry__1_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__0/i___0_carry__2
(.CI(\rgb_blur3_inferred__0/i___0_carry__1_n_0 ),
.CO({\NLW_rgb_blur3_inferred__0/i___0_carry__2_CO_UNCONNECTED [3:2],\rgb_blur3_inferred__0/i___0_carry__2_n_2 ,\rgb_blur3_inferred__0/i___0_carry__2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,rgb_blur3__82_carry__2_n_7,rgb_blur3__82_carry__1_n_4}),
.O({\NLW_rgb_blur3_inferred__0/i___0_carry__2_O_UNCONNECTED [3],\rgb_blur3_inferred__0/i___0_carry__2_n_5 ,\rgb_blur3_inferred__0/i___0_carry__2_n_6 ,\rgb_blur3_inferred__0/i___0_carry__2_n_7 }),
.S({1'b0,1'b1,i___0_carry__2_i_1_n_0,i___0_carry__2_i_2_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__1/i___0_carry_n_0 ,\rgb_blur3_inferred__1/i___0_carry_n_1 ,\rgb_blur3_inferred__1/i___0_carry_n_2 ,\rgb_blur3_inferred__1/i___0_carry_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry_i_1__0_n_0,i___0_carry_i_2__0_n_0,i___0_carry_i_3__0_n_0,1'b0}),
.O({\rgb_blur3_inferred__1/i___0_carry_n_4 ,\rgb_blur3_inferred__1/i___0_carry_n_5 ,\rgb_blur3_inferred__1/i___0_carry_n_6 ,\rgb_blur3_inferred__1/i___0_carry_n_7 }),
.S({i___0_carry_i_4__0_n_0,i___0_carry_i_5__0_n_0,i___0_carry_i_6__0_n_0,i___0_carry_i_7__0_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__0
(.CI(\rgb_blur3_inferred__1/i___0_carry_n_0 ),
.CO({\rgb_blur3_inferred__1/i___0_carry__0_n_0 ,\rgb_blur3_inferred__1/i___0_carry__0_n_1 ,\rgb_blur3_inferred__1/i___0_carry__0_n_2 ,\rgb_blur3_inferred__1/i___0_carry__0_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry__0_i_1__0_n_0,i___0_carry__0_i_2__0_n_0,i___0_carry__0_i_3__0_n_0,i___0_carry__0_i_4__0_n_0}),
.O({\rgb_blur3_inferred__1/i___0_carry__0_n_4 ,\rgb_blur3_inferred__1/i___0_carry__0_n_5 ,\rgb_blur3_inferred__1/i___0_carry__0_n_6 ,\rgb_blur3_inferred__1/i___0_carry__0_n_7 }),
.S({i___0_carry__0_i_5__0_n_0,i___0_carry__0_i_6__0_n_0,i___0_carry__0_i_7__0_n_0,i___0_carry__0_i_8__0_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__1
(.CI(\rgb_blur3_inferred__1/i___0_carry__0_n_0 ),
.CO({\rgb_blur3_inferred__1/i___0_carry__1_n_0 ,\rgb_blur3_inferred__1/i___0_carry__1_n_1 ,\rgb_blur3_inferred__1/i___0_carry__1_n_2 ,\rgb_blur3_inferred__1/i___0_carry__1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\rgb_blur3_inferred__0/i___0_carry__1_n_7 }),
.O({\rgb_blur3_inferred__1/i___0_carry__1_n_4 ,\rgb_blur3_inferred__1/i___0_carry__1_n_5 ,\rgb_blur3_inferred__1/i___0_carry__1_n_6 ,\rgb_blur3_inferred__1/i___0_carry__1_n_7 }),
.S({i___0_carry__1_i_1__2_n_0,i___0_carry__1_i_2__2_n_0,i___0_carry__1_i_3__0_n_0,i___0_carry__1_i_4__0_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__2
(.CI(\rgb_blur3_inferred__1/i___0_carry__1_n_0 ),
.CO({\rgb_blur3_inferred__1/i___0_carry__2_n_0 ,\rgb_blur3_inferred__1/i___0_carry__2_n_1 ,\rgb_blur3_inferred__1/i___0_carry__2_n_2 ,\rgb_blur3_inferred__1/i___0_carry__2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur3_inferred__1/i___0_carry__2_n_4 ,\rgb_blur3_inferred__1/i___0_carry__2_n_5 ,\rgb_blur3_inferred__1/i___0_carry__2_n_6 ,\rgb_blur3_inferred__1/i___0_carry__2_n_7 }),
.S({i___0_carry__2_i_1__2_n_0,i___0_carry__2_i_2__2_n_0,i___0_carry__2_i_3_n_0,i___0_carry__2_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__3
(.CI(\rgb_blur3_inferred__1/i___0_carry__2_n_0 ),
.CO({\rgb_blur3_inferred__1/i___0_carry__3_n_0 ,\rgb_blur3_inferred__1/i___0_carry__3_n_1 ,\rgb_blur3_inferred__1/i___0_carry__3_n_2 ,\rgb_blur3_inferred__1/i___0_carry__3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur3_inferred__1/i___0_carry__3_n_4 ,\rgb_blur3_inferred__1/i___0_carry__3_n_5 ,\rgb_blur3_inferred__1/i___0_carry__3_n_6 ,\rgb_blur3_inferred__1/i___0_carry__3_n_7 }),
.S({i___0_carry__3_i_1_n_0,i___0_carry__3_i_2_n_0,i___0_carry__3_i_3_n_0,i___0_carry__3_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__4
(.CI(\rgb_blur3_inferred__1/i___0_carry__3_n_0 ),
.CO({\rgb_blur3_inferred__1/i___0_carry__4_n_0 ,\rgb_blur3_inferred__1/i___0_carry__4_n_1 ,\rgb_blur3_inferred__1/i___0_carry__4_n_2 ,\rgb_blur3_inferred__1/i___0_carry__4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur3_inferred__1/i___0_carry__4_n_4 ,\rgb_blur3_inferred__1/i___0_carry__4_n_5 ,\rgb_blur3_inferred__1/i___0_carry__4_n_6 ,\rgb_blur3_inferred__1/i___0_carry__4_n_7 }),
.S({i___0_carry__4_i_1_n_0,i___0_carry__4_i_2_n_0,i___0_carry__4_i_3_n_0,i___0_carry__4_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__5
(.CI(\rgb_blur3_inferred__1/i___0_carry__4_n_0 ),
.CO({\rgb_blur3_inferred__1/i___0_carry__5_n_0 ,\rgb_blur3_inferred__1/i___0_carry__5_n_1 ,\rgb_blur3_inferred__1/i___0_carry__5_n_2 ,\rgb_blur3_inferred__1/i___0_carry__5_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur3_inferred__1/i___0_carry__5_n_4 ,\rgb_blur3_inferred__1/i___0_carry__5_n_5 ,\rgb_blur3_inferred__1/i___0_carry__5_n_6 ,\rgb_blur3_inferred__1/i___0_carry__5_n_7 }),
.S({i___0_carry__5_i_1_n_0,i___0_carry__5_i_2_n_0,i___0_carry__5_i_3_n_0,i___0_carry__5_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__1/i___0_carry__6
(.CI(\rgb_blur3_inferred__1/i___0_carry__5_n_0 ),
.CO({\NLW_rgb_blur3_inferred__1/i___0_carry__6_CO_UNCONNECTED [3],\rgb_blur3_inferred__1/i___0_carry__6_n_1 ,\rgb_blur3_inferred__1/i___0_carry__6_n_2 ,\rgb_blur3_inferred__1/i___0_carry__6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur3_inferred__1/i___0_carry__6_n_4 ,\rgb_blur3_inferred__1/i___0_carry__6_n_5 ,\rgb_blur3_inferred__1/i___0_carry__6_n_6 ,\rgb_blur3_inferred__1/i___0_carry__6_n_7 }),
.S({i___0_carry__6_i_1_n_0,i___0_carry__6_i_2_n_0,i___0_carry__6_i_3_n_0,i___0_carry__6_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___24_carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__2/i___24_carry_n_0 ,\rgb_blur3_inferred__2/i___24_carry_n_1 ,\rgb_blur3_inferred__2/i___24_carry_n_2 ,\rgb_blur3_inferred__2/i___24_carry_n_3 }),
.CYINIT(1'b0),
.DI({D[10:8],1'b0}),
.O({\rgb_blur3_inferred__2/i___24_carry_n_4 ,\rgb_blur3_inferred__2/i___24_carry_n_5 ,\rgb_blur3_inferred__2/i___24_carry_n_6 ,\rgb_blur3_inferred__2/i___24_carry_n_7 }),
.S({i___24_carry_i_1_n_0,i___24_carry_i_2_n_0,i___24_carry_i_3_n_0,i___24_carry_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___24_carry__0
(.CI(\rgb_blur3_inferred__2/i___24_carry_n_0 ),
.CO({\rgb_blur3_inferred__2/i___24_carry__0_n_0 ,\rgb_blur3_inferred__2/i___24_carry__0_n_1 ,\rgb_blur3_inferred__2/i___24_carry__0_n_2 ,\rgb_blur3_inferred__2/i___24_carry__0_n_3 }),
.CYINIT(1'b0),
.DI(D[14:11]),
.O({\rgb_blur3_inferred__2/i___24_carry__0_n_4 ,\rgb_blur3_inferred__2/i___24_carry__0_n_5 ,\rgb_blur3_inferred__2/i___24_carry__0_n_6 ,\rgb_blur3_inferred__2/i___24_carry__0_n_7 }),
.S({i___24_carry__0_i_1_n_0,i___24_carry__0_i_2_n_0,i___24_carry__0_i_3_n_0,i___24_carry__0_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___24_carry__1
(.CI(\rgb_blur3_inferred__2/i___24_carry__0_n_0 ),
.CO({\NLW_rgb_blur3_inferred__2/i___24_carry__1_CO_UNCONNECTED [3:2],\rgb_blur3_inferred__2/i___24_carry__1_n_2 ,\NLW_rgb_blur3_inferred__2/i___24_carry__1_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
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.O({\NLW_rgb_blur3_inferred__2/i___24_carry__1_O_UNCONNECTED [3:1],\rgb_blur3_inferred__2/i___24_carry__1_n_7 }),
.S({1'b0,1'b0,1'b1,i___24_carry__1_i_1_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___50_carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__2/i___50_carry_n_0 ,\rgb_blur3_inferred__2/i___50_carry_n_1 ,\rgb_blur3_inferred__2/i___50_carry_n_2 ,\rgb_blur3_inferred__2/i___50_carry_n_3 }),
.CYINIT(1'b0),
.DI({I6[2:0],1'b0}),
.O({C__0[3:1],\NLW_rgb_blur3_inferred__2/i___50_carry_O_UNCONNECTED [0]}),
.S({i___50_carry_i_1_n_0,i___50_carry_i_2_n_0,i___50_carry_i_3_n_0,1'b0}));
CARRY4 \rgb_blur3_inferred__2/i___50_carry__0
(.CI(\rgb_blur3_inferred__2/i___50_carry_n_0 ),
.CO({\rgb_blur3_inferred__2/i___50_carry__0_n_0 ,\rgb_blur3_inferred__2/i___50_carry__0_n_1 ,\rgb_blur3_inferred__2/i___50_carry__0_n_2 ,\rgb_blur3_inferred__2/i___50_carry__0_n_3 }),
.CYINIT(1'b0),
.DI(I6[6:3]),
.O(C__0[7:4]),
.S({i___50_carry__0_i_1_n_0,i___50_carry__0_i_2_n_0,i___50_carry__0_i_3_n_0,i___50_carry__0_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___50_carry__1
(.CI(\rgb_blur3_inferred__2/i___50_carry__0_n_0 ),
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.CYINIT(1'b0),
.DI({\rgb_blur3_inferred__2/i___24_carry__1_n_2 ,\rgb_blur3_inferred__2/i___24_carry__1_n_7 ,i___50_carry__1_i_1_n_0,I6[7]}),
.O(C__0[11:8]),
.S({i___50_carry__1_i_2_n_0,i___50_carry__1_i_3_n_0,i___50_carry__1_i_4_n_0,i___50_carry__1_i_5_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___82_carry
(.CI(1'b0),
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.S({i___82_carry_i_1_n_0,i___82_carry_i_2_n_0,i___82_carry_i_3_n_0,1'b0}));
CARRY4 \rgb_blur3_inferred__2/i___82_carry__0
(.CI(\rgb_blur3_inferred__2/i___82_carry_n_0 ),
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.S({i___82_carry__0_i_1_n_0,i___82_carry__0_i_2_n_0,i___82_carry__0_i_3_n_0,i___82_carry__0_i_4_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___82_carry__1
(.CI(\rgb_blur3_inferred__2/i___82_carry__0_n_0 ),
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.DI({C__0[10:9],i___82_carry__1_i_1_n_0,I7[7]}),
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.S({i___82_carry__1_i_2_n_0,i___82_carry__1_i_3_n_0,i___82_carry__1_i_4_n_0,i___82_carry__1_i_5_n_0}));
CARRY4 \rgb_blur3_inferred__2/i___82_carry__2
(.CI(\rgb_blur3_inferred__2/i___82_carry__1_n_0 ),
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.S({1'b0,1'b0,1'b1,i___82_carry__2_i_1_n_0}));
CARRY4 \rgb_blur3_inferred__2/i__carry
(.CI(1'b0),
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.O({\rgb_blur3_inferred__5/i___82_carry__1_n_4 ,\rgb_blur3_inferred__5/i___82_carry__1_n_5 ,\rgb_blur3_inferred__5/i___82_carry__1_n_6 ,\rgb_blur3_inferred__5/i___82_carry__1_n_7 }),
.S({i___82_carry__1_i_2__0_n_0,i___82_carry__1_i_3__0_n_0,i___82_carry__1_i_4__0_n_0,i___82_carry__1_i_5__0_n_0}));
CARRY4 \rgb_blur3_inferred__5/i___82_carry__2
(.CI(\rgb_blur3_inferred__5/i___82_carry__1_n_0 ),
.CO({\NLW_rgb_blur3_inferred__5/i___82_carry__2_CO_UNCONNECTED [3:2],\rgb_blur3_inferred__5/i___82_carry__2_n_2 ,\NLW_rgb_blur3_inferred__5/i___82_carry__2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
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.O({\NLW_rgb_blur3_inferred__5/i___82_carry__2_O_UNCONNECTED [3:1],\rgb_blur3_inferred__5/i___82_carry__2_n_7 }),
.S({1'b0,1'b0,1'b1,i___82_carry__2_i_1__0_n_0}));
CARRY4 \rgb_blur3_inferred__5/i__carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__5/i__carry_n_0 ,\rgb_blur3_inferred__5/i__carry_n_1 ,\rgb_blur3_inferred__5/i__carry_n_2 ,\rgb_blur3_inferred__5/i__carry_n_3 }),
.CYINIT(1'b0),
.DI({\rgb_buffer_reg[642] [18:16],1'b0}),
.O({\rgb_blur3_inferred__5/i__carry_n_4 ,\rgb_blur3_inferred__5/i__carry_n_5 ,\rgb_blur3_inferred__5/i__carry_n_6 ,\NLW_rgb_blur3_inferred__5/i__carry_O_UNCONNECTED [0]}),
.S({i__carry_i_1__2_n_0,i__carry_i_2__2_n_0,i__carry_i_3__2_n_0,1'b0}));
CARRY4 \rgb_blur3_inferred__5/i__carry__0
(.CI(\rgb_blur3_inferred__5/i__carry_n_0 ),
.CO({\rgb_blur3_inferred__5/i__carry__0_n_0 ,\rgb_blur3_inferred__5/i__carry__0_n_1 ,\rgb_blur3_inferred__5/i__carry__0_n_2 ,\rgb_blur3_inferred__5/i__carry__0_n_3 }),
.CYINIT(1'b0),
.DI(\rgb_buffer_reg[642] [22:19]),
.O({\rgb_blur3_inferred__5/i__carry__0_n_4 ,\rgb_blur3_inferred__5/i__carry__0_n_5 ,\rgb_blur3_inferred__5/i__carry__0_n_6 ,\rgb_blur3_inferred__5/i__carry__0_n_7 }),
.S({i__carry__0_i_1__2_n_0,i__carry__0_i_2__2_n_0,i__carry__0_i_3__2_n_0,i__carry__0_i_4__2_n_0}));
CARRY4 \rgb_blur3_inferred__5/i__carry__1
(.CI(\rgb_blur3_inferred__5/i__carry__0_n_0 ),
.CO({\NLW_rgb_blur3_inferred__5/i__carry__1_CO_UNCONNECTED [3:2],\rgb_blur3_inferred__5/i__carry__1_n_2 ,\NLW_rgb_blur3_inferred__5/i__carry__1_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\rgb_buffer_reg[642] [23]}),
.O({\NLW_rgb_blur3_inferred__5/i__carry__1_O_UNCONNECTED [3:1],\rgb_blur3_inferred__5/i__carry__1_n_7 }),
.S({1'b0,1'b0,1'b1,i__carry__1_i_1__2_n_0}));
CARRY4 \rgb_blur3_inferred__6/i___0_carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__6/i___0_carry_n_0 ,\rgb_blur3_inferred__6/i___0_carry_n_1 ,\rgb_blur3_inferred__6/i___0_carry_n_2 ,\rgb_blur3_inferred__6/i___0_carry_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry_i_1__3_n_0,i___0_carry_i_2__3_n_0,i___0_carry_i_3__3_n_0,1'b0}),
.O(PCIN[3:0]),
.S({i___0_carry_i_4__3_n_0,i___0_carry_i_5__3_n_0,i___0_carry_i_6__3_n_0,i___0_carry_i_7__3_n_0}));
CARRY4 \rgb_blur3_inferred__6/i___0_carry__0
(.CI(\rgb_blur3_inferred__6/i___0_carry_n_0 ),
.CO({\rgb_blur3_inferred__6/i___0_carry__0_n_0 ,\rgb_blur3_inferred__6/i___0_carry__0_n_1 ,\rgb_blur3_inferred__6/i___0_carry__0_n_2 ,\rgb_blur3_inferred__6/i___0_carry__0_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry__0_i_1__3_n_0,i___0_carry__0_i_2__3_n_0,i___0_carry__0_i_3__3_n_0,i___0_carry__0_i_4__3_n_0}),
.O(PCIN[7:4]),
.S({i___0_carry__0_i_5__3_n_0,i___0_carry__0_i_6__3_n_0,i___0_carry__0_i_7__3_n_0,i___0_carry__0_i_8__3_n_0}));
CARRY4 \rgb_blur3_inferred__6/i___0_carry__1
(.CI(\rgb_blur3_inferred__6/i___0_carry__0_n_0 ),
.CO({\rgb_blur3_inferred__6/i___0_carry__1_n_0 ,\rgb_blur3_inferred__6/i___0_carry__1_n_1 ,\rgb_blur3_inferred__6/i___0_carry__1_n_2 ,\rgb_blur3_inferred__6/i___0_carry__1_n_3 }),
.CYINIT(1'b0),
.DI({\rgb_blur3_inferred__5/i___82_carry__1_n_5 ,\rgb_blur3_inferred__5/i___82_carry__1_n_6 ,1'b1,\rgb_blur3_inferred__5/i___82_carry__1_n_7 }),
.O(PCIN[11:8]),
.S({i___0_carry__1_i_1__1_n_0,i___0_carry__1_i_2__1_n_0,i___0_carry__1_i_3__3_n_0,i___0_carry__1_i_4__3_n_0}));
CARRY4 \rgb_blur3_inferred__6/i___0_carry__2
(.CI(\rgb_blur3_inferred__6/i___0_carry__1_n_0 ),
.CO({\NLW_rgb_blur3_inferred__6/i___0_carry__2_CO_UNCONNECTED [3:2],\rgb_blur3_inferred__6/i___0_carry__2_n_2 ,\rgb_blur3_inferred__6/i___0_carry__2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\rgb_blur3_inferred__5/i___82_carry__2_n_7 ,\rgb_blur3_inferred__5/i___82_carry__1_n_4 }),
.O({\NLW_rgb_blur3_inferred__6/i___0_carry__2_O_UNCONNECTED [3],PCIN[31],PCIN[13:12]}),
.S({1'b0,1'b1,i___0_carry__2_i_1__1_n_0,i___0_carry__2_i_2__1_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry
(.CI(1'b0),
.CO({\rgb_blur3_inferred__7/i___0_carry_n_0 ,\rgb_blur3_inferred__7/i___0_carry_n_1 ,\rgb_blur3_inferred__7/i___0_carry_n_2 ,\rgb_blur3_inferred__7/i___0_carry_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry_i_1__4_n_0,i___0_carry_i_2__4_n_0,i___0_carry_i_3__4_n_0,1'b0}),
.O(rgb_blur3[3:0]),
.S({i___0_carry_i_4__4_n_0,i___0_carry_i_5__4_n_0,i___0_carry_i_6__4_n_0,i___0_carry_i_7__4_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__0
(.CI(\rgb_blur3_inferred__7/i___0_carry_n_0 ),
.CO({\rgb_blur3_inferred__7/i___0_carry__0_n_0 ,\rgb_blur3_inferred__7/i___0_carry__0_n_1 ,\rgb_blur3_inferred__7/i___0_carry__0_n_2 ,\rgb_blur3_inferred__7/i___0_carry__0_n_3 }),
.CYINIT(1'b0),
.DI({i___0_carry__0_i_1__4_n_0,i___0_carry__0_i_2__4_n_0,i___0_carry__0_i_3__4_n_0,i___0_carry__0_i_4__4_n_0}),
.O(rgb_blur3[7:4]),
.S({i___0_carry__0_i_5__4_n_0,i___0_carry__0_i_6__4_n_0,i___0_carry__0_i_7__4_n_0,i___0_carry__0_i_8__4_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__1
(.CI(\rgb_blur3_inferred__7/i___0_carry__0_n_0 ),
.CO({\rgb_blur3_inferred__7/i___0_carry__1_n_0 ,\rgb_blur3_inferred__7/i___0_carry__1_n_1 ,\rgb_blur3_inferred__7/i___0_carry__1_n_2 ,\rgb_blur3_inferred__7/i___0_carry__1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,PCIN[8]}),
.O(rgb_blur3[11:8]),
.S({i___0_carry__1_i_1__4_n_0,i___0_carry__1_i_2__4_n_0,i___0_carry__1_i_3__4_n_0,i___0_carry__1_i_4__4_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__2
(.CI(\rgb_blur3_inferred__7/i___0_carry__1_n_0 ),
.CO({\rgb_blur3_inferred__7/i___0_carry__2_n_0 ,\rgb_blur3_inferred__7/i___0_carry__2_n_1 ,\rgb_blur3_inferred__7/i___0_carry__2_n_2 ,\rgb_blur3_inferred__7/i___0_carry__2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(rgb_blur3[15:12]),
.S({i___0_carry__2_i_1__4_n_0,i___0_carry__2_i_2__4_n_0,i___0_carry__2_i_3__1_n_0,i___0_carry__2_i_4__1_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__3
(.CI(\rgb_blur3_inferred__7/i___0_carry__2_n_0 ),
.CO({\rgb_blur3_inferred__7/i___0_carry__3_n_0 ,\rgb_blur3_inferred__7/i___0_carry__3_n_1 ,\rgb_blur3_inferred__7/i___0_carry__3_n_2 ,\rgb_blur3_inferred__7/i___0_carry__3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(rgb_blur3[19:16]),
.S({i___0_carry__3_i_1__1_n_0,i___0_carry__3_i_2__1_n_0,i___0_carry__3_i_3__1_n_0,i___0_carry__3_i_4__1_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__4
(.CI(\rgb_blur3_inferred__7/i___0_carry__3_n_0 ),
.CO({\rgb_blur3_inferred__7/i___0_carry__4_n_0 ,\rgb_blur3_inferred__7/i___0_carry__4_n_1 ,\rgb_blur3_inferred__7/i___0_carry__4_n_2 ,\rgb_blur3_inferred__7/i___0_carry__4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(rgb_blur3[23:20]),
.S({i___0_carry__4_i_1__1_n_0,i___0_carry__4_i_2__1_n_0,i___0_carry__4_i_3__1_n_0,i___0_carry__4_i_4__1_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__5
(.CI(\rgb_blur3_inferred__7/i___0_carry__4_n_0 ),
.CO({\rgb_blur3_inferred__7/i___0_carry__5_n_0 ,\rgb_blur3_inferred__7/i___0_carry__5_n_1 ,\rgb_blur3_inferred__7/i___0_carry__5_n_2 ,\rgb_blur3_inferred__7/i___0_carry__5_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(rgb_blur3[27:24]),
.S({i___0_carry__5_i_1__1_n_0,i___0_carry__5_i_2__1_n_0,i___0_carry__5_i_3__1_n_0,i___0_carry__5_i_4__1_n_0}));
CARRY4 \rgb_blur3_inferred__7/i___0_carry__6
(.CI(\rgb_blur3_inferred__7/i___0_carry__5_n_0 ),
.CO({\NLW_rgb_blur3_inferred__7/i___0_carry__6_CO_UNCONNECTED [3],\rgb_blur3_inferred__7/i___0_carry__6_n_1 ,\rgb_blur3_inferred__7/i___0_carry__6_n_2 ,\rgb_blur3_inferred__7/i___0_carry__6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(rgb_blur3[31:28]),
.S({i___0_carry__6_i_1__1_n_0,i___0_carry__6_i_2__1_n_0,i___0_carry__6_i_3__1_n_0,i___0_carry__6_i_4__1_n_0}));
CARRY4 rgb_blur4_carry
(.CI(1'b0),
.CO({rgb_blur4_carry_n_0,rgb_blur4_carry_n_1,rgb_blur4_carry_n_2,rgb_blur4_carry_n_3}),
.CYINIT(1'b1),
.DI({rgb_blur4_carry_i_1_n_0,rgb_blur4_carry_i_2_n_0,rgb_blur4_carry_i_3_n_0,rgb_blur4_carry_i_4_n_0}),
.O(NLW_rgb_blur4_carry_O_UNCONNECTED[3:0]),
.S({rgb_blur4_carry_i_5_n_0,rgb_blur4_carry_i_6_n_0,rgb_blur4_carry_i_7_n_0,rgb_blur4_carry_i_8_n_0}));
CARRY4 rgb_blur4_carry__0
(.CI(rgb_blur4_carry_n_0),
.CO({rgb_blur4_carry__0_n_0,rgb_blur4_carry__0_n_1,rgb_blur4_carry__0_n_2,rgb_blur4_carry__0_n_3}),
.CYINIT(1'b0),
.DI({rgb_blur4_carry__0_i_1_n_0,rgb_blur4_carry__0_i_2_n_0,rgb_blur4_carry__0_i_3_n_0,rgb_blur4_carry__0_i_4_n_0}),
.O(NLW_rgb_blur4_carry__0_O_UNCONNECTED[3:0]),
.S({rgb_blur4_carry__0_i_5_n_0,rgb_blur4_carry__0_i_6_n_0,rgb_blur4_carry__0_i_7_n_0,rgb_blur4_carry__0_i_8_n_0}));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__0_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__2_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__2_n_4 ),
.O(rgb_blur4_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__0_i_2
(.I0(\rgb_blur3_inferred__1/i___0_carry__2_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__2_n_6 ),
.O(rgb_blur4_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__0_i_3
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__1_n_4 ),
.O(rgb_blur4_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__0_i_4
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__1_n_6 ),
.O(rgb_blur4_carry__0_i_4_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__0_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry__2_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__2_n_5 ),
.O(rgb_blur4_carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__0_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry__2_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__2_n_7 ),
.O(rgb_blur4_carry__0_i_6_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__0_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__1_n_5 ),
.O(rgb_blur4_carry__0_i_7_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__0_i_8
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.O(rgb_blur4_carry__0_i_8_n_0));
CARRY4 rgb_blur4_carry__1
(.CI(rgb_blur4_carry__0_n_0),
.CO({rgb_blur4_carry__1_n_0,rgb_blur4_carry__1_n_1,rgb_blur4_carry__1_n_2,rgb_blur4_carry__1_n_3}),
.CYINIT(1'b0),
.DI({rgb_blur4_carry__1_i_1_n_0,rgb_blur4_carry__1_i_2_n_0,rgb_blur4_carry__1_i_3_n_0,rgb_blur4_carry__1_i_4_n_0}),
.O(NLW_rgb_blur4_carry__1_O_UNCONNECTED[3:0]),
.S({rgb_blur4_carry__1_i_5_n_0,rgb_blur4_carry__1_i_6_n_0,rgb_blur4_carry__1_i_7_n_0,rgb_blur4_carry__1_i_8_n_0}));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__1_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__4_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__4_n_4 ),
.O(rgb_blur4_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__1_i_2
(.I0(\rgb_blur3_inferred__1/i___0_carry__4_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__4_n_6 ),
.O(rgb_blur4_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__1_i_3
(.I0(\rgb_blur3_inferred__1/i___0_carry__3_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__3_n_4 ),
.O(rgb_blur4_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__1_i_4
(.I0(\rgb_blur3_inferred__1/i___0_carry__3_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__3_n_6 ),
.O(rgb_blur4_carry__1_i_4_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__1_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry__4_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__4_n_5 ),
.O(rgb_blur4_carry__1_i_5_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__1_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry__4_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__4_n_7 ),
.O(rgb_blur4_carry__1_i_6_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__1_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry__3_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__3_n_5 ),
.O(rgb_blur4_carry__1_i_7_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__1_i_8
(.I0(\rgb_blur3_inferred__1/i___0_carry__3_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__3_n_7 ),
.O(rgb_blur4_carry__1_i_8_n_0));
CARRY4 rgb_blur4_carry__2
(.CI(rgb_blur4_carry__1_n_0),
.CO({rgb_blur4_carry__2_n_0,rgb_blur4_carry__2_n_1,rgb_blur4_carry__2_n_2,rgb_blur4_carry__2_n_3}),
.CYINIT(1'b0),
.DI({rgb_blur4_carry__2_i_1_n_0,rgb_blur4_carry__2_i_2_n_0,rgb_blur4_carry__2_i_3_n_0,rgb_blur4_carry__2_i_4_n_0}),
.O(NLW_rgb_blur4_carry__2_O_UNCONNECTED[3:0]),
.S({rgb_blur4_carry__2_i_5_n_0,rgb_blur4_carry__2_i_6_n_0,rgb_blur4_carry__2_i_7_n_0,rgb_blur4_carry__2_i_8_n_0}));
LUT2 #(
.INIT(4'h2))
rgb_blur4_carry__2_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.O(rgb_blur4_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__2_i_2
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__6_n_6 ),
.O(rgb_blur4_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__2_i_3
(.I0(\rgb_blur3_inferred__1/i___0_carry__5_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__5_n_4 ),
.O(rgb_blur4_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry__2_i_4
(.I0(\rgb_blur3_inferred__1/i___0_carry__5_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__5_n_6 ),
.O(rgb_blur4_carry__2_i_4_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__2_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.O(rgb_blur4_carry__2_i_5_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__2_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__6_n_7 ),
.O(rgb_blur4_carry__2_i_6_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__2_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry__5_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__5_n_5 ),
.O(rgb_blur4_carry__2_i_7_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry__2_i_8
(.I0(\rgb_blur3_inferred__1/i___0_carry__5_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__5_n_7 ),
.O(rgb_blur4_carry__2_i_8_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__0_n_4 ),
.O(rgb_blur4_carry_i_1_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry_i_2
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__0_n_6 ),
.O(rgb_blur4_carry_i_2_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry_i_3
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_5 ),
.I1(\rgb_blur3_inferred__1/i___0_carry_n_4 ),
.O(rgb_blur4_carry_i_3_n_0));
LUT2 #(
.INIT(4'hE))
rgb_blur4_carry_i_4
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry_n_6 ),
.O(rgb_blur4_carry_i_4_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__0_n_5 ),
.O(rgb_blur4_carry_i_5_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.O(rgb_blur4_carry_i_6_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_4 ),
.I1(\rgb_blur3_inferred__1/i___0_carry_n_5 ),
.O(rgb_blur4_carry_i_7_n_0));
LUT2 #(
.INIT(4'h1))
rgb_blur4_carry_i_8
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_6 ),
.I1(\rgb_blur3_inferred__1/i___0_carry_n_7 ),
.O(rgb_blur4_carry_i_8_n_0));
CARRY4 \rgb_blur4_inferred__0/i__carry
(.CI(1'b0),
.CO({\rgb_blur4_inferred__0/i__carry_n_0 ,\rgb_blur4_inferred__0/i__carry_n_1 ,\rgb_blur4_inferred__0/i__carry_n_2 ,\rgb_blur4_inferred__0/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}),
.O(\NLW_rgb_blur4_inferred__0/i__carry_O_UNCONNECTED [3:0]),
.S({i__carry_i_5_n_0,i__carry_i_6_n_0,i__carry_i_7_n_0,i__carry_i_8_n_0}));
CARRY4 \rgb_blur4_inferred__0/i__carry__0
(.CI(\rgb_blur4_inferred__0/i__carry_n_0 ),
.CO({\rgb_blur4_inferred__0/i__carry__0_n_0 ,\rgb_blur4_inferred__0/i__carry__0_n_1 ,\rgb_blur4_inferred__0/i__carry__0_n_2 ,\rgb_blur4_inferred__0/i__carry__0_n_3 }),
.CYINIT(1'b0),
.DI({i__carry__0_i_1_n_0,i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0}),
.O(\NLW_rgb_blur4_inferred__0/i__carry__0_O_UNCONNECTED [3:0]),
.S({i__carry__0_i_5_n_0,i__carry__0_i_6_n_0,i__carry__0_i_7_n_0,i__carry__0_i_8_n_0}));
CARRY4 \rgb_blur4_inferred__0/i__carry__1
(.CI(\rgb_blur4_inferred__0/i__carry__0_n_0 ),
.CO({\rgb_blur4_inferred__0/i__carry__1_n_0 ,\rgb_blur4_inferred__0/i__carry__1_n_1 ,\rgb_blur4_inferred__0/i__carry__1_n_2 ,\rgb_blur4_inferred__0/i__carry__1_n_3 }),
.CYINIT(1'b0),
.DI({i__carry__1_i_1_n_0,i__carry__1_i_2_n_0,i__carry__1_i_3_n_0,i__carry__1_i_4_n_0}),
.O(\NLW_rgb_blur4_inferred__0/i__carry__1_O_UNCONNECTED [3:0]),
.S({i__carry__1_i_5_n_0,i__carry__1_i_6_n_0,i__carry__1_i_7_n_0,i__carry__1_i_8_n_0}));
CARRY4 \rgb_blur4_inferred__0/i__carry__2
(.CI(\rgb_blur4_inferred__0/i__carry__1_n_0 ),
.CO({\rgb_blur4_inferred__0/i__carry__2_n_0 ,\rgb_blur4_inferred__0/i__carry__2_n_1 ,\rgb_blur4_inferred__0/i__carry__2_n_2 ,\rgb_blur4_inferred__0/i__carry__2_n_3 }),
.CYINIT(1'b0),
.DI({i__carry__2_i_1__0_n_0,i__carry__2_i_2_n_0,i__carry__2_i_3_n_0,i__carry__2_i_4_n_0}),
.O(\NLW_rgb_blur4_inferred__0/i__carry__2_O_UNCONNECTED [3:0]),
.S({i__carry__2_i_5_n_0,i__carry__2_i_6_n_0,i__carry__2_i_7_n_0,i__carry__2_i_8_n_0}));
CARRY4 \rgb_blur4_inferred__1/i__carry
(.CI(1'b0),
.CO({\rgb_blur4_inferred__1/i__carry_n_0 ,\rgb_blur4_inferred__1/i__carry_n_1 ,\rgb_blur4_inferred__1/i__carry_n_2 ,\rgb_blur4_inferred__1/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__0_n_0}),
.O(\NLW_rgb_blur4_inferred__1/i__carry_O_UNCONNECTED [3:0]),
.S({i__carry_i_5__0_n_0,i__carry_i_6__0_n_0,i__carry_i_7__0_n_0,i__carry_i_8__0_n_0}));
CARRY4 \rgb_blur4_inferred__1/i__carry__0
(.CI(\rgb_blur4_inferred__1/i__carry_n_0 ),
.CO({\rgb_blur4_inferred__1/i__carry__0_n_0 ,\rgb_blur4_inferred__1/i__carry__0_n_1 ,\rgb_blur4_inferred__1/i__carry__0_n_2 ,\rgb_blur4_inferred__1/i__carry__0_n_3 }),
.CYINIT(1'b0),
.DI({i__carry__0_i_1__0_n_0,i__carry__0_i_2__0_n_0,i__carry__0_i_3__0_n_0,i__carry__0_i_4__0_n_0}),
.O(\NLW_rgb_blur4_inferred__1/i__carry__0_O_UNCONNECTED [3:0]),
.S({i__carry__0_i_5__0_n_0,i__carry__0_i_6__0_n_0,i__carry__0_i_7__0_n_0,i__carry__0_i_8__0_n_0}));
CARRY4 \rgb_blur4_inferred__1/i__carry__1
(.CI(\rgb_blur4_inferred__1/i__carry__0_n_0 ),
.CO({\rgb_blur4_inferred__1/i__carry__1_n_0 ,\rgb_blur4_inferred__1/i__carry__1_n_1 ,\rgb_blur4_inferred__1/i__carry__1_n_2 ,\rgb_blur4_inferred__1/i__carry__1_n_3 }),
.CYINIT(1'b0),
.DI({i__carry__1_i_1__0_n_0,i__carry__1_i_2__0_n_0,i__carry__1_i_3__0_n_0,i__carry__1_i_4__0_n_0}),
.O(\NLW_rgb_blur4_inferred__1/i__carry__1_O_UNCONNECTED [3:0]),
.S({i__carry__1_i_5__0_n_0,i__carry__1_i_6__0_n_0,i__carry__1_i_7__0_n_0,i__carry__1_i_8__0_n_0}));
CARRY4 \rgb_blur4_inferred__1/i__carry__2
(.CI(\rgb_blur4_inferred__1/i__carry__1_n_0 ),
.CO({rgb_blur4,\rgb_blur4_inferred__1/i__carry__2_n_1 ,\rgb_blur4_inferred__1/i__carry__2_n_2 ,\rgb_blur4_inferred__1/i__carry__2_n_3 }),
.CYINIT(1'b0),
.DI({i__carry__2_i_1_n_0,i__carry__2_i_2__0_n_0,i__carry__2_i_3__0_n_0,i__carry__2_i_4__0_n_0}),
.O(\NLW_rgb_blur4_inferred__1/i__carry__2_O_UNCONNECTED [3:0]),
.S({i__carry__2_i_5__0_n_0,i__carry__2_i_6__0_n_0,i__carry__2_i_7__0_n_0,i__carry__2_i_8__0_n_0}));
LUT3 #(
.INIT(8'hB8))
\rgb_blur[0]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.I1(rgb_blur4_carry__2_n_0),
.I2(\rgb_blur_reg[1]_i_2_n_4 ),
.O(p_7_out[0]));
LUT6 #(
.INIT(64'hFDFDFD020202FD02))
\rgb_blur[10]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur[10]_i_2_n_0 ),
.I2(\rgb_blur[10]_i_3_n_0 ),
.I3(\rgb_blur_reg[12]_i_4_n_6 ),
.I4(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I5(\rgb_blur3_inferred__4/i___0_carry__0_n_5 ),
.O(p_7_out[10]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h01))
\rgb_blur[10]_i_2
(.I0(\rgb_blur_reg[9]_i_2_n_4 ),
.I1(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I2(\rgb_blur_reg[12]_i_4_n_7 ),
.O(\rgb_blur[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h02))
\rgb_blur[10]_i_3
(.I0(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__0_n_6 ),
.I2(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.O(\rgb_blur[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[11]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur[11]_i_2_n_0 ),
.I2(\rgb_blur_reg[12]_i_4_n_5 ),
.I3(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I4(\rgb_blur3_inferred__4/i___0_carry__0_n_4 ),
.O(p_7_out[11]));
LUT6 #(
.INIT(64'h444444444444444F))
\rgb_blur[11]_i_2
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_5 ),
.I1(\rgb_blur[10]_i_3_n_0 ),
.I2(\rgb_blur_reg[12]_i_4_n_6 ),
.I3(\rgb_blur_reg[9]_i_2_n_4 ),
.I4(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I5(\rgb_blur_reg[12]_i_4_n_7 ),
.O(\rgb_blur[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFDFDFD020202FD02))
\rgb_blur[12]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur[12]_i_2_n_0 ),
.I2(\rgb_blur[12]_i_3_n_0 ),
.I3(\rgb_blur_reg[12]_i_4_n_4 ),
.I4(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I5(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.O(p_7_out[12]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00000010))
\rgb_blur[12]_i_2
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__0_n_6 ),
.I2(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I3(\rgb_blur3_inferred__4/i___0_carry__0_n_4 ),
.I4(\rgb_blur3_inferred__4/i___0_carry__0_n_5 ),
.O(\rgb_blur[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00000001))
\rgb_blur[12]_i_3
(.I0(\rgb_blur_reg[12]_i_4_n_6 ),
.I1(\rgb_blur_reg[9]_i_2_n_4 ),
.I2(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I3(\rgb_blur_reg[12]_i_4_n_7 ),
.I4(\rgb_blur_reg[12]_i_4_n_5 ),
.O(\rgb_blur[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[12]_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.O(\rgb_blur[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[12]_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_4 ),
.O(\rgb_blur[12]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[12]_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_5 ),
.O(\rgb_blur[12]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[12]_i_8
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_6 ),
.O(\rgb_blur[12]_i_8_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[13]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur[13]_i_2_n_0 ),
.I2(\rgb_blur_reg[15]_i_3_n_7 ),
.I3(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I4(\rgb_blur3_inferred__4/i___0_carry__1_n_6 ),
.O(p_7_out[13]));
LUT4 #(
.INIT(16'h4F44))
\rgb_blur[13]_i_2
(.I0(\rgb_blur_reg[12]_i_4_n_4 ),
.I1(\rgb_blur[12]_i_3_n_0 ),
.I2(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.I3(\rgb_blur[12]_i_2_n_0 ),
.O(\rgb_blur[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[14]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur[14]_i_2_n_0 ),
.I2(\rgb_blur_reg[15]_i_3_n_6 ),
.I3(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I4(\rgb_blur3_inferred__4/i___0_carry__1_n_5 ),
.O(p_7_out[14]));
LUT6 #(
.INIT(64'h020202FF02020202))
\rgb_blur[14]_i_2
(.I0(\rgb_blur[12]_i_3_n_0 ),
.I1(\rgb_blur_reg[12]_i_4_n_4 ),
.I2(\rgb_blur_reg[15]_i_3_n_7 ),
.I3(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.I4(\rgb_blur3_inferred__4/i___0_carry__1_n_6 ),
.I5(\rgb_blur[12]_i_2_n_0 ),
.O(\rgb_blur[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[15]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur[15]_i_2_n_0 ),
.I2(\rgb_blur_reg[15]_i_3_n_5 ),
.I3(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I4(\rgb_blur3_inferred__4/i___0_carry__1_n_4 ),
.O(p_7_out[15]));
LUT6 #(
.INIT(64'hFFFF000200020002))
\rgb_blur[15]_i_2
(.I0(\rgb_blur[12]_i_2_n_0 ),
.I1(\rgb_blur3_inferred__4/i___0_carry__1_n_6 ),
.I2(\rgb_blur3_inferred__4/i___0_carry__1_n_7 ),
.I3(\rgb_blur3_inferred__4/i___0_carry__1_n_5 ),
.I4(\rgb_blur[12]_i_3_n_0 ),
.I5(\rgb_blur[15]_i_4_n_0 ),
.O(\rgb_blur[15]_i_2_n_0 ));
LUT3 #(
.INIT(8'h01))
\rgb_blur[15]_i_4
(.I0(\rgb_blur_reg[15]_i_3_n_6 ),
.I1(\rgb_blur_reg[15]_i_3_n_7 ),
.I2(\rgb_blur_reg[12]_i_4_n_4 ),
.O(\rgb_blur[15]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[15]_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_4 ),
.O(\rgb_blur[15]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[15]_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_5 ),
.O(\rgb_blur[15]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[15]_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry__1_n_6 ),
.O(\rgb_blur[15]_i_7_n_0 ));
LUT3 #(
.INIT(8'hB8))
\rgb_blur[16]_i_1
(.I0(rgb_blur3[4]),
.I1(rgb_blur4),
.I2(\rgb_blur_reg[17]_i_2_n_4 ),
.O(p_7_out[16]));
LUT6 #(
.INIT(64'h5F5F7788A0A07788))
\rgb_blur[17]_i_1
(.I0(rgb_blur3[31]),
.I1(\rgb_blur_reg[17]_i_2_n_4 ),
.I2(rgb_blur3[4]),
.I3(\rgb_blur_reg[20]_i_4_n_7 ),
.I4(rgb_blur4),
.I5(rgb_blur3[5]),
.O(p_7_out[17]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[17]_i_3
(.I0(rgb_blur3[0]),
.O(p_0_in[0]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[17]_i_4
(.I0(rgb_blur3[4]),
.O(p_0_in[4]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[17]_i_5
(.I0(rgb_blur3[3]),
.O(p_0_in[3]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[17]_i_6
(.I0(rgb_blur3[2]),
.O(p_0_in[2]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[17]_i_7
(.I0(rgb_blur3[1]),
.O(p_0_in[1]));
LUT6 #(
.INIT(64'hFDFDFD020202FD02))
\rgb_blur[18]_i_1
(.I0(rgb_blur3[31]),
.I1(\rgb_blur[18]_i_2_n_0 ),
.I2(\rgb_blur[18]_i_3_n_0 ),
.I3(\rgb_blur_reg[20]_i_4_n_6 ),
.I4(rgb_blur4),
.I5(rgb_blur3[6]),
.O(p_7_out[18]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h01))
\rgb_blur[18]_i_2
(.I0(\rgb_blur_reg[17]_i_2_n_4 ),
.I1(rgb_blur4),
.I2(\rgb_blur_reg[20]_i_4_n_7 ),
.O(\rgb_blur[18]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h02))
\rgb_blur[18]_i_3
(.I0(rgb_blur4),
.I1(rgb_blur3[5]),
.I2(rgb_blur3[4]),
.O(\rgb_blur[18]_i_3_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[19]_i_1
(.I0(rgb_blur3[31]),
.I1(\rgb_blur[19]_i_2_n_0 ),
.I2(\rgb_blur_reg[20]_i_4_n_5 ),
.I3(rgb_blur4),
.I4(rgb_blur3[7]),
.O(p_7_out[19]));
LUT6 #(
.INIT(64'h444444444444444F))
\rgb_blur[19]_i_2
(.I0(rgb_blur3[6]),
.I1(\rgb_blur[18]_i_3_n_0 ),
.I2(\rgb_blur_reg[20]_i_4_n_6 ),
.I3(\rgb_blur_reg[17]_i_2_n_4 ),
.I4(rgb_blur4),
.I5(\rgb_blur_reg[20]_i_4_n_7 ),
.O(\rgb_blur[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h5F5F7788A0A07788))
\rgb_blur[1]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur_reg[1]_i_2_n_4 ),
.I2(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.I3(\rgb_blur_reg[4]_i_4_n_7 ),
.I4(rgb_blur4_carry__2_n_0),
.I5(\rgb_blur3_inferred__1/i___0_carry__0_n_6 ),
.O(p_7_out[1]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[1]_i_3
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_7 ),
.O(\rgb_blur[1]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[1]_i_4
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.O(\rgb_blur[1]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[1]_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_4 ),
.O(\rgb_blur[1]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[1]_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_5 ),
.O(\rgb_blur[1]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[1]_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry_n_6 ),
.O(\rgb_blur[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFDFDFD020202FD02))
\rgb_blur[20]_i_1
(.I0(rgb_blur3[31]),
.I1(\rgb_blur[20]_i_2_n_0 ),
.I2(\rgb_blur[20]_i_3_n_0 ),
.I3(\rgb_blur_reg[20]_i_4_n_4 ),
.I4(rgb_blur4),
.I5(rgb_blur3[8]),
.O(p_7_out[20]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000010))
\rgb_blur[20]_i_2
(.I0(rgb_blur3[4]),
.I1(rgb_blur3[5]),
.I2(rgb_blur4),
.I3(rgb_blur3[7]),
.I4(rgb_blur3[6]),
.O(\rgb_blur[20]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000001))
\rgb_blur[20]_i_3
(.I0(\rgb_blur_reg[20]_i_4_n_6 ),
.I1(\rgb_blur_reg[17]_i_2_n_4 ),
.I2(rgb_blur4),
.I3(\rgb_blur_reg[20]_i_4_n_7 ),
.I4(\rgb_blur_reg[20]_i_4_n_5 ),
.O(\rgb_blur[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[20]_i_5
(.I0(rgb_blur3[8]),
.O(p_0_in[8]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[20]_i_6
(.I0(rgb_blur3[7]),
.O(p_0_in[7]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[20]_i_7
(.I0(rgb_blur3[6]),
.O(p_0_in[6]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[20]_i_8
(.I0(rgb_blur3[5]),
.O(p_0_in[5]));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[21]_i_1
(.I0(rgb_blur3[31]),
.I1(\rgb_blur[21]_i_2_n_0 ),
.I2(\rgb_blur_reg[23]_i_4_n_7 ),
.I3(rgb_blur4),
.I4(rgb_blur3[9]),
.O(p_7_out[21]));
LUT4 #(
.INIT(16'h4F44))
\rgb_blur[21]_i_2
(.I0(\rgb_blur_reg[20]_i_4_n_4 ),
.I1(\rgb_blur[20]_i_3_n_0 ),
.I2(rgb_blur3[8]),
.I3(\rgb_blur[20]_i_2_n_0 ),
.O(\rgb_blur[21]_i_2_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[22]_i_1
(.I0(rgb_blur3[31]),
.I1(\rgb_blur[22]_i_2_n_0 ),
.I2(\rgb_blur_reg[23]_i_4_n_6 ),
.I3(rgb_blur4),
.I4(rgb_blur3[10]),
.O(p_7_out[22]));
LUT6 #(
.INIT(64'h020202FF02020202))
\rgb_blur[22]_i_2
(.I0(\rgb_blur[20]_i_3_n_0 ),
.I1(\rgb_blur_reg[20]_i_4_n_4 ),
.I2(\rgb_blur_reg[23]_i_4_n_7 ),
.I3(rgb_blur3[8]),
.I4(rgb_blur3[9]),
.I5(\rgb_blur[20]_i_2_n_0 ),
.O(\rgb_blur[22]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\rgb_blur[23]_i_1
(.I0(vsync_in),
.I1(hsync_in),
.O(\rgb_blur[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[23]_i_2
(.I0(rgb_blur3[31]),
.I1(\rgb_blur[23]_i_3_n_0 ),
.I2(\rgb_blur_reg[23]_i_4_n_5 ),
.I3(rgb_blur4),
.I4(rgb_blur3[11]),
.O(p_7_out[23]));
LUT6 #(
.INIT(64'hFFFF000200020002))
\rgb_blur[23]_i_3
(.I0(\rgb_blur[20]_i_2_n_0 ),
.I1(rgb_blur3[9]),
.I2(rgb_blur3[8]),
.I3(rgb_blur3[10]),
.I4(\rgb_blur[20]_i_3_n_0 ),
.I5(\rgb_blur[23]_i_5_n_0 ),
.O(\rgb_blur[23]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\rgb_blur[23]_i_5
(.I0(\rgb_blur_reg[23]_i_4_n_6 ),
.I1(\rgb_blur_reg[23]_i_4_n_7 ),
.I2(\rgb_blur_reg[20]_i_4_n_4 ),
.O(\rgb_blur[23]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[23]_i_6
(.I0(rgb_blur3[11]),
.O(p_0_in[11]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[23]_i_7
(.I0(rgb_blur3[10]),
.O(p_0_in[10]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[23]_i_8
(.I0(rgb_blur3[9]),
.O(p_0_in[9]));
LUT6 #(
.INIT(64'hFDFDFD020202FD02))
\rgb_blur[2]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur[2]_i_2_n_0 ),
.I2(\rgb_blur[2]_i_3_n_0 ),
.I3(\rgb_blur_reg[4]_i_4_n_6 ),
.I4(rgb_blur4_carry__2_n_0),
.I5(\rgb_blur3_inferred__1/i___0_carry__0_n_5 ),
.O(p_7_out[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h01))
\rgb_blur[2]_i_2
(.I0(\rgb_blur_reg[1]_i_2_n_4 ),
.I1(rgb_blur4_carry__2_n_0),
.I2(\rgb_blur_reg[4]_i_4_n_7 ),
.O(\rgb_blur[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h02))
\rgb_blur[2]_i_3
(.I0(rgb_blur4_carry__2_n_0),
.I1(\rgb_blur3_inferred__1/i___0_carry__0_n_6 ),
.I2(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.O(\rgb_blur[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[3]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur[3]_i_2_n_0 ),
.I2(\rgb_blur_reg[4]_i_4_n_5 ),
.I3(rgb_blur4_carry__2_n_0),
.I4(\rgb_blur3_inferred__1/i___0_carry__0_n_4 ),
.O(p_7_out[3]));
LUT6 #(
.INIT(64'h444444444444444F))
\rgb_blur[3]_i_2
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_5 ),
.I1(\rgb_blur[2]_i_3_n_0 ),
.I2(\rgb_blur_reg[4]_i_4_n_6 ),
.I3(\rgb_blur_reg[1]_i_2_n_4 ),
.I4(rgb_blur4_carry__2_n_0),
.I5(\rgb_blur_reg[4]_i_4_n_7 ),
.O(\rgb_blur[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFDFDFD020202FD02))
\rgb_blur[4]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur[4]_i_2_n_0 ),
.I2(\rgb_blur[4]_i_3_n_0 ),
.I3(\rgb_blur_reg[4]_i_4_n_4 ),
.I4(rgb_blur4_carry__2_n_0),
.I5(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.O(p_7_out[4]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000010))
\rgb_blur[4]_i_2
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_7 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__0_n_6 ),
.I2(rgb_blur4_carry__2_n_0),
.I3(\rgb_blur3_inferred__1/i___0_carry__0_n_4 ),
.I4(\rgb_blur3_inferred__1/i___0_carry__0_n_5 ),
.O(\rgb_blur[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000001))
\rgb_blur[4]_i_3
(.I0(\rgb_blur_reg[4]_i_4_n_6 ),
.I1(\rgb_blur_reg[1]_i_2_n_4 ),
.I2(rgb_blur4_carry__2_n_0),
.I3(\rgb_blur_reg[4]_i_4_n_7 ),
.I4(\rgb_blur_reg[4]_i_4_n_5 ),
.O(\rgb_blur[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[4]_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.O(\rgb_blur[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[4]_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_4 ),
.O(\rgb_blur[4]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[4]_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_5 ),
.O(\rgb_blur[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[4]_i_8
(.I0(\rgb_blur3_inferred__1/i___0_carry__0_n_6 ),
.O(\rgb_blur[4]_i_8_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[5]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur[5]_i_2_n_0 ),
.I2(\rgb_blur_reg[7]_i_3_n_7 ),
.I3(rgb_blur4_carry__2_n_0),
.I4(\rgb_blur3_inferred__1/i___0_carry__1_n_6 ),
.O(p_7_out[5]));
LUT4 #(
.INIT(16'h4F44))
\rgb_blur[5]_i_2
(.I0(\rgb_blur_reg[4]_i_4_n_4 ),
.I1(\rgb_blur[4]_i_3_n_0 ),
.I2(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.I3(\rgb_blur[4]_i_2_n_0 ),
.O(\rgb_blur[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[6]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur[6]_i_2_n_0 ),
.I2(\rgb_blur_reg[7]_i_3_n_6 ),
.I3(rgb_blur4_carry__2_n_0),
.I4(\rgb_blur3_inferred__1/i___0_carry__1_n_5 ),
.O(p_7_out[6]));
LUT6 #(
.INIT(64'h020202FF02020202))
\rgb_blur[6]_i_2
(.I0(\rgb_blur[4]_i_3_n_0 ),
.I1(\rgb_blur_reg[4]_i_4_n_4 ),
.I2(\rgb_blur_reg[7]_i_3_n_7 ),
.I3(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.I4(\rgb_blur3_inferred__1/i___0_carry__1_n_6 ),
.I5(\rgb_blur[4]_i_2_n_0 ),
.O(\rgb_blur[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'hDDD222D2))
\rgb_blur[7]_i_1
(.I0(\rgb_blur3_inferred__1/i___0_carry__6_n_4 ),
.I1(\rgb_blur[7]_i_2_n_0 ),
.I2(\rgb_blur_reg[7]_i_3_n_5 ),
.I3(rgb_blur4_carry__2_n_0),
.I4(\rgb_blur3_inferred__1/i___0_carry__1_n_4 ),
.O(p_7_out[7]));
LUT6 #(
.INIT(64'hFFFF000200020002))
\rgb_blur[7]_i_2
(.I0(\rgb_blur[4]_i_2_n_0 ),
.I1(\rgb_blur3_inferred__1/i___0_carry__1_n_6 ),
.I2(\rgb_blur3_inferred__1/i___0_carry__1_n_7 ),
.I3(\rgb_blur3_inferred__1/i___0_carry__1_n_5 ),
.I4(\rgb_blur[4]_i_3_n_0 ),
.I5(\rgb_blur[7]_i_4_n_0 ),
.O(\rgb_blur[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'h01))
\rgb_blur[7]_i_4
(.I0(\rgb_blur_reg[7]_i_3_n_6 ),
.I1(\rgb_blur_reg[7]_i_3_n_7 ),
.I2(\rgb_blur_reg[4]_i_4_n_4 ),
.O(\rgb_blur[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[7]_i_5
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_4 ),
.O(\rgb_blur[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[7]_i_6
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_5 ),
.O(\rgb_blur[7]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[7]_i_7
(.I0(\rgb_blur3_inferred__1/i___0_carry__1_n_6 ),
.O(\rgb_blur[7]_i_7_n_0 ));
LUT3 #(
.INIT(8'hB8))
\rgb_blur[8]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.I1(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I2(\rgb_blur_reg[9]_i_2_n_4 ),
.O(p_7_out[8]));
LUT6 #(
.INIT(64'h5F5F7788A0A07788))
\rgb_blur[9]_i_1
(.I0(\rgb_blur3_inferred__4/i___0_carry__6_n_4 ),
.I1(\rgb_blur_reg[9]_i_2_n_4 ),
.I2(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.I3(\rgb_blur_reg[12]_i_4_n_7 ),
.I4(\rgb_blur4_inferred__0/i__carry__2_n_0 ),
.I5(\rgb_blur3_inferred__4/i___0_carry__0_n_6 ),
.O(p_7_out[9]));
LUT1 #(
.INIT(2'h1))
\rgb_blur[9]_i_3
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_7 ),
.O(\rgb_blur[9]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[9]_i_4
(.I0(\rgb_blur3_inferred__4/i___0_carry__0_n_7 ),
.O(\rgb_blur[9]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[9]_i_5
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_4 ),
.O(\rgb_blur[9]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[9]_i_6
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_5 ),
.O(\rgb_blur[9]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\rgb_blur[9]_i_7
(.I0(\rgb_blur3_inferred__4/i___0_carry_n_6 ),
.O(\rgb_blur[9]_i_7_n_0 ));
FDRE \rgb_blur_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[0]),
.Q(rgb_blur[0]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[10]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[10]),
.Q(rgb_blur[10]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[11]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[11]),
.Q(rgb_blur[11]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[12]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[12]),
.Q(rgb_blur[12]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[12]_i_4
(.CI(\rgb_blur_reg[9]_i_2_n_0 ),
.CO({\rgb_blur_reg[12]_i_4_n_0 ,\rgb_blur_reg[12]_i_4_n_1 ,\rgb_blur_reg[12]_i_4_n_2 ,\rgb_blur_reg[12]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur_reg[12]_i_4_n_4 ,\rgb_blur_reg[12]_i_4_n_5 ,\rgb_blur_reg[12]_i_4_n_6 ,\rgb_blur_reg[12]_i_4_n_7 }),
.S({\rgb_blur[12]_i_5_n_0 ,\rgb_blur[12]_i_6_n_0 ,\rgb_blur[12]_i_7_n_0 ,\rgb_blur[12]_i_8_n_0 }));
FDRE \rgb_blur_reg[13]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[13]),
.Q(rgb_blur[13]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[14]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[14]),
.Q(rgb_blur[14]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[15]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[15]),
.Q(rgb_blur[15]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[15]_i_3
(.CI(\rgb_blur_reg[12]_i_4_n_0 ),
.CO({\NLW_rgb_blur_reg[15]_i_3_CO_UNCONNECTED [3:2],\rgb_blur_reg[15]_i_3_n_2 ,\rgb_blur_reg[15]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_rgb_blur_reg[15]_i_3_O_UNCONNECTED [3],\rgb_blur_reg[15]_i_3_n_5 ,\rgb_blur_reg[15]_i_3_n_6 ,\rgb_blur_reg[15]_i_3_n_7 }),
.S({1'b0,\rgb_blur[15]_i_5_n_0 ,\rgb_blur[15]_i_6_n_0 ,\rgb_blur[15]_i_7_n_0 }));
FDRE \rgb_blur_reg[16]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[16]),
.Q(rgb_blur[16]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[17]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[17]),
.Q(rgb_blur[17]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[17]_i_2
(.CI(1'b0),
.CO({\rgb_blur_reg[17]_i_2_n_0 ,\rgb_blur_reg[17]_i_2_n_1 ,\rgb_blur_reg[17]_i_2_n_2 ,\rgb_blur_reg[17]_i_2_n_3 }),
.CYINIT(p_0_in[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur_reg[17]_i_2_n_4 ,\NLW_rgb_blur_reg[17]_i_2_O_UNCONNECTED [2:0]}),
.S(p_0_in[4:1]));
FDRE \rgb_blur_reg[18]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[18]),
.Q(rgb_blur[18]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[19]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[19]),
.Q(rgb_blur[19]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[1]),
.Q(rgb_blur[1]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[1]_i_2
(.CI(1'b0),
.CO({\rgb_blur_reg[1]_i_2_n_0 ,\rgb_blur_reg[1]_i_2_n_1 ,\rgb_blur_reg[1]_i_2_n_2 ,\rgb_blur_reg[1]_i_2_n_3 }),
.CYINIT(\rgb_blur[1]_i_3_n_0 ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur_reg[1]_i_2_n_4 ,\NLW_rgb_blur_reg[1]_i_2_O_UNCONNECTED [2:0]}),
.S({\rgb_blur[1]_i_4_n_0 ,\rgb_blur[1]_i_5_n_0 ,\rgb_blur[1]_i_6_n_0 ,\rgb_blur[1]_i_7_n_0 }));
FDRE \rgb_blur_reg[20]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[20]),
.Q(rgb_blur[20]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[20]_i_4
(.CI(\rgb_blur_reg[17]_i_2_n_0 ),
.CO({\rgb_blur_reg[20]_i_4_n_0 ,\rgb_blur_reg[20]_i_4_n_1 ,\rgb_blur_reg[20]_i_4_n_2 ,\rgb_blur_reg[20]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur_reg[20]_i_4_n_4 ,\rgb_blur_reg[20]_i_4_n_5 ,\rgb_blur_reg[20]_i_4_n_6 ,\rgb_blur_reg[20]_i_4_n_7 }),
.S(p_0_in[8:5]));
FDRE \rgb_blur_reg[21]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[21]),
.Q(rgb_blur[21]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[22]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[22]),
.Q(rgb_blur[22]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[23]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[23]),
.Q(rgb_blur[23]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[23]_i_4
(.CI(\rgb_blur_reg[20]_i_4_n_0 ),
.CO({\NLW_rgb_blur_reg[23]_i_4_CO_UNCONNECTED [3:2],\rgb_blur_reg[23]_i_4_n_2 ,\rgb_blur_reg[23]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_rgb_blur_reg[23]_i_4_O_UNCONNECTED [3],\rgb_blur_reg[23]_i_4_n_5 ,\rgb_blur_reg[23]_i_4_n_6 ,\rgb_blur_reg[23]_i_4_n_7 }),
.S({1'b0,p_0_in[11:9]}));
FDRE \rgb_blur_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[2]),
.Q(rgb_blur[2]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[3]),
.Q(rgb_blur[3]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[4]),
.Q(rgb_blur[4]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[4]_i_4
(.CI(\rgb_blur_reg[1]_i_2_n_0 ),
.CO({\rgb_blur_reg[4]_i_4_n_0 ,\rgb_blur_reg[4]_i_4_n_1 ,\rgb_blur_reg[4]_i_4_n_2 ,\rgb_blur_reg[4]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur_reg[4]_i_4_n_4 ,\rgb_blur_reg[4]_i_4_n_5 ,\rgb_blur_reg[4]_i_4_n_6 ,\rgb_blur_reg[4]_i_4_n_7 }),
.S({\rgb_blur[4]_i_5_n_0 ,\rgb_blur[4]_i_6_n_0 ,\rgb_blur[4]_i_7_n_0 ,\rgb_blur[4]_i_8_n_0 }));
FDRE \rgb_blur_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[5]),
.Q(rgb_blur[5]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[6]),
.Q(rgb_blur[6]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[7]),
.Q(rgb_blur[7]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[7]_i_3
(.CI(\rgb_blur_reg[4]_i_4_n_0 ),
.CO({\NLW_rgb_blur_reg[7]_i_3_CO_UNCONNECTED [3:2],\rgb_blur_reg[7]_i_3_n_2 ,\rgb_blur_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_rgb_blur_reg[7]_i_3_O_UNCONNECTED [3],\rgb_blur_reg[7]_i_3_n_5 ,\rgb_blur_reg[7]_i_3_n_6 ,\rgb_blur_reg[7]_i_3_n_7 }),
.S({1'b0,\rgb_blur[7]_i_5_n_0 ,\rgb_blur[7]_i_6_n_0 ,\rgb_blur[7]_i_7_n_0 }));
FDRE \rgb_blur_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[8]),
.Q(rgb_blur[8]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_blur_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(p_7_out[9]),
.Q(rgb_blur[9]),
.R(\rgb_blur[23]_i_1_n_0 ));
CARRY4 \rgb_blur_reg[9]_i_2
(.CI(1'b0),
.CO({\rgb_blur_reg[9]_i_2_n_0 ,\rgb_blur_reg[9]_i_2_n_1 ,\rgb_blur_reg[9]_i_2_n_2 ,\rgb_blur_reg[9]_i_2_n_3 }),
.CYINIT(\rgb_blur[9]_i_3_n_0 ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\rgb_blur_reg[9]_i_2_n_4 ,\NLW_rgb_blur_reg[9]_i_2_O_UNCONNECTED [2:0]}),
.S({\rgb_blur[9]_i_4_n_0 ,\rgb_blur[9]_i_5_n_0 ,\rgb_blur[9]_i_6_n_0 ,\rgb_blur[9]_i_7_n_0 }));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1026] " *)
(* srl_name = "\U0/rgb_buffer_reg[1026][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1026][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[994][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1026][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1026][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1058] " *)
(* srl_name = "\U0/rgb_buffer_reg[1058][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1058][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1026][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1058][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1058][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1090] " *)
(* srl_name = "\U0/rgb_buffer_reg[1090][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1090][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1058][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1090][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1090][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1122] " *)
(* srl_name = "\U0/rgb_buffer_reg[1122][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1122][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1090][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1122][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1122][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1154] " *)
(* srl_name = "\U0/rgb_buffer_reg[1154][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1154][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1122][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[1154][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[1154][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1186] " *)
(* srl_name = "\U0/rgb_buffer_reg[1186][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1186][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1154][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[1186][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1186][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1218] " *)
(* srl_name = "\U0/rgb_buffer_reg[1218][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1218][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1186][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1218][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1218][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1250] " *)
(* srl_name = "\U0/rgb_buffer_reg[1250][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[1250][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1218][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[1250][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[1250][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][0]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][0]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][0]_srl32_n_1 ),
.Q(\C[0]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][0]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][10]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][10]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][10]_srl32_n_1 ),
.Q(\C[2]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][10]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][11]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][11]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][11]_srl32_n_1 ),
.Q(\C[3]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][11]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][12]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][12]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][12]_srl32_n_1 ),
.Q(\C[4]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][12]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][13]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][13]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][13]_srl32_n_1 ),
.Q(\C[5]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][13]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][14]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][14]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][14]_srl32_n_1 ),
.Q(\C[6]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][14]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][15]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][15]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][15]_srl32_n_1 ),
.Q(\C[7]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][15]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][16]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][16]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][16]_srl32_n_1 ),
.Q(\C[0]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][16]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][17]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][17]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][17]_srl32_n_1 ),
.Q(\C[1]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][17]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][18]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][18]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][18]_srl32_n_1 ),
.Q(\C[2]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][18]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][19]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][19]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][19]_srl32_n_1 ),
.Q(\C[3]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][19]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][1]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][1]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][1]_srl32_n_1 ),
.Q(\C[1]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][1]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][20]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][20]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][20]_srl32_n_1 ),
.Q(\C[4]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][20]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][21]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][21]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][21]_srl32_n_1 ),
.Q(\C[5]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][21]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][22]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][22]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][22]_srl32_n_1 ),
.Q(\C[6]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][22]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][23]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][23]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][23]_srl32_n_1 ),
.Q(\C[7]__4 ),
.Q31(\NLW_rgb_buffer_reg[1279][23]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][2]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][2]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][2]_srl32_n_1 ),
.Q(\C[2]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][2]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][3]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][3]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][3]_srl32_n_1 ),
.Q(\C[3]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][3]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][4]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][4]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][4]_srl32_n_1 ),
.Q(\C[4]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][4]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][5]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][5]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][5]_srl32_n_1 ),
.Q(\C[5]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][5]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][6]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][6]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][6]_srl32_n_1 ),
.Q(\C[6]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][6]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][7]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][7]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][7]_srl32_n_1 ),
.Q(\C[7]__0 ),
.Q31(\NLW_rgb_buffer_reg[1279][7]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][8]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][8]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][8]_srl32_n_1 ),
.Q(\C[0]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][8]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[1279] " *)
(* srl_name = "\U0/rgb_buffer_reg[1279][9]_srl29 " *)
SRLC32E \rgb_buffer_reg[1279][9]_srl29
(.A({1'b1,1'b1,1'b1,1'b0,1'b0}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[1250][9]_srl32_n_1 ),
.Q(\C[1]__2 ),
.Q31(\NLW_rgb_buffer_reg[1279][9]_srl29_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[130] " *)
(* srl_name = "\U0/rgb_buffer_reg[130][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[130][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[98][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[130][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[130][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[162] " *)
(* srl_name = "\U0/rgb_buffer_reg[162][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[162][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[130][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[162][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[162][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[194] " *)
(* srl_name = "\U0/rgb_buffer_reg[194][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[194][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[162][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[194][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[194][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[226] " *)
(* srl_name = "\U0/rgb_buffer_reg[226][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[226][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[194][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[226][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[226][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[258] " *)
(* srl_name = "\U0/rgb_buffer_reg[258][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[258][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[226][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[258][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[258][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[290] " *)
(* srl_name = "\U0/rgb_buffer_reg[290][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[290][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[258][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[290][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[290][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[322] " *)
(* srl_name = "\U0/rgb_buffer_reg[322][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[322][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[290][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[322][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[322][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[0] ),
.Q(\NLW_rgb_buffer_reg[34][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[2]__4 ),
.Q(\NLW_rgb_buffer_reg[34][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[3]__4 ),
.Q(\NLW_rgb_buffer_reg[34][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[4]__4 ),
.Q(\NLW_rgb_buffer_reg[34][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[5]__4 ),
.Q(\NLW_rgb_buffer_reg[34][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[6]__4 ),
.Q(\NLW_rgb_buffer_reg[34][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[7]__4 ),
.Q(\NLW_rgb_buffer_reg[34][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[0]__7 ),
.Q(\NLW_rgb_buffer_reg[34][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[1]__8 ),
.Q(\NLW_rgb_buffer_reg[34][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[2]__8 ),
.Q(\NLW_rgb_buffer_reg[34][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[3]__8 ),
.Q(\NLW_rgb_buffer_reg[34][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[1]__0 ),
.Q(\NLW_rgb_buffer_reg[34][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[4]__8 ),
.Q(\NLW_rgb_buffer_reg[34][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[5]__8 ),
.Q(\NLW_rgb_buffer_reg[34][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[6]__8 ),
.Q(\NLW_rgb_buffer_reg[34][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[7]__8 ),
.Q(\NLW_rgb_buffer_reg[34][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[2]__0 ),
.Q(\NLW_rgb_buffer_reg[34][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[3]__0 ),
.Q(\NLW_rgb_buffer_reg[34][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[4]__0 ),
.Q(\NLW_rgb_buffer_reg[34][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[5]__0 ),
.Q(\NLW_rgb_buffer_reg[34][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[6]__0 ),
.Q(\NLW_rgb_buffer_reg[34][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[7]__0 ),
.Q(\NLW_rgb_buffer_reg[34][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[0]__3 ),
.Q(\NLW_rgb_buffer_reg[34][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[34] " *)
(* srl_name = "\U0/rgb_buffer_reg[34][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[34][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\B[1]__4 ),
.Q(\NLW_rgb_buffer_reg[34][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[34][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[354] " *)
(* srl_name = "\U0/rgb_buffer_reg[354][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[354][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[322][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[354][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[354][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[386] " *)
(* srl_name = "\U0/rgb_buffer_reg[386][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[386][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[354][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[386][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[386][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[418] " *)
(* srl_name = "\U0/rgb_buffer_reg[418][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[418][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[386][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[418][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[418][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[450] " *)
(* srl_name = "\U0/rgb_buffer_reg[450][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[450][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[418][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[450][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[450][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[482] " *)
(* srl_name = "\U0/rgb_buffer_reg[482][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[482][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[450][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[482][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[482][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[514] " *)
(* srl_name = "\U0/rgb_buffer_reg[514][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[514][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[482][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[514][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[514][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[546] " *)
(* srl_name = "\U0/rgb_buffer_reg[546][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[546][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[514][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[546][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[546][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[578] " *)
(* srl_name = "\U0/rgb_buffer_reg[578][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[578][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[546][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[578][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[578][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][0]_srl32_Q_UNCONNECTED ),
.Q31(\A[0]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][10]_srl32_Q_UNCONNECTED ),
.Q31(\A[2]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][11]_srl32_Q_UNCONNECTED ),
.Q31(\A[3]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][12]_srl32_Q_UNCONNECTED ),
.Q31(\A[4]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][13]_srl32_Q_UNCONNECTED ),
.Q31(\A[5]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][14]_srl32_Q_UNCONNECTED ),
.Q31(\A[6]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][15]_srl32_Q_UNCONNECTED ),
.Q31(\A[7]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][16]_srl32_Q_UNCONNECTED ),
.Q31(\A[0]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][17]_srl32_Q_UNCONNECTED ),
.Q31(\A[1]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][18]_srl32_Q_UNCONNECTED ),
.Q31(\A[2]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][19]_srl32_Q_UNCONNECTED ),
.Q31(\A[3]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][1]_srl32_Q_UNCONNECTED ),
.Q31(\A[1]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][20]_srl32_Q_UNCONNECTED ),
.Q31(\A[4]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][21]_srl32_Q_UNCONNECTED ),
.Q31(\A[5]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][22]_srl32_Q_UNCONNECTED ),
.Q31(\A[6]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][23]_srl32_Q_UNCONNECTED ),
.Q31(\A[7]__26 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][2]_srl32_Q_UNCONNECTED ),
.Q31(\A[2]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][3]_srl32_Q_UNCONNECTED ),
.Q31(\A[3]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][4]_srl32_Q_UNCONNECTED ),
.Q31(\A[4]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][5]_srl32_Q_UNCONNECTED ),
.Q31(\A[5]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][6]_srl32_Q_UNCONNECTED ),
.Q31(\A[6]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][7]_srl32_Q_UNCONNECTED ),
.Q31(\A[7]__6 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][8]_srl32_Q_UNCONNECTED ),
.Q31(\A[0]__16 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[610] " *)
(* srl_name = "\U0/rgb_buffer_reg[610][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[610][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[578][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[610][9]_srl32_Q_UNCONNECTED ),
.Q31(\A[1]__16 ));
FDRE \rgb_buffer_reg[642][0]
(.C(clk_25),
.CE(active),
.D(D[0]),
.Q(\rgb_buffer_reg[642] [0]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][10]
(.C(clk_25),
.CE(active),
.D(D[10]),
.Q(\rgb_buffer_reg[642] [10]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][11]
(.C(clk_25),
.CE(active),
.D(D[11]),
.Q(\rgb_buffer_reg[642] [11]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][12]
(.C(clk_25),
.CE(active),
.D(D[12]),
.Q(\rgb_buffer_reg[642] [12]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][13]
(.C(clk_25),
.CE(active),
.D(D[13]),
.Q(\rgb_buffer_reg[642] [13]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][14]
(.C(clk_25),
.CE(active),
.D(D[14]),
.Q(\rgb_buffer_reg[642] [14]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][15]
(.C(clk_25),
.CE(active),
.D(D[15]),
.Q(\rgb_buffer_reg[642] [15]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][16]
(.C(clk_25),
.CE(active),
.D(D[16]),
.Q(\rgb_buffer_reg[642] [16]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][17]
(.C(clk_25),
.CE(active),
.D(D[17]),
.Q(\rgb_buffer_reg[642] [17]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][18]
(.C(clk_25),
.CE(active),
.D(D[18]),
.Q(\rgb_buffer_reg[642] [18]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][19]
(.C(clk_25),
.CE(active),
.D(D[19]),
.Q(\rgb_buffer_reg[642] [19]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][1]
(.C(clk_25),
.CE(active),
.D(D[1]),
.Q(\rgb_buffer_reg[642] [1]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][20]
(.C(clk_25),
.CE(active),
.D(D[20]),
.Q(\rgb_buffer_reg[642] [20]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][21]
(.C(clk_25),
.CE(active),
.D(D[21]),
.Q(\rgb_buffer_reg[642] [21]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][22]
(.C(clk_25),
.CE(active),
.D(D[22]),
.Q(\rgb_buffer_reg[642] [22]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][23]
(.C(clk_25),
.CE(active),
.D(D[23]),
.Q(\rgb_buffer_reg[642] [23]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][2]
(.C(clk_25),
.CE(active),
.D(D[2]),
.Q(\rgb_buffer_reg[642] [2]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][3]
(.C(clk_25),
.CE(active),
.D(D[3]),
.Q(\rgb_buffer_reg[642] [3]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][4]
(.C(clk_25),
.CE(active),
.D(D[4]),
.Q(\rgb_buffer_reg[642] [4]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][5]
(.C(clk_25),
.CE(active),
.D(D[5]),
.Q(\rgb_buffer_reg[642] [5]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][6]
(.C(clk_25),
.CE(active),
.D(D[6]),
.Q(\rgb_buffer_reg[642] [6]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][7]
(.C(clk_25),
.CE(active),
.D(D[7]),
.Q(\rgb_buffer_reg[642] [7]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][8]
(.C(clk_25),
.CE(active),
.D(D[8]),
.Q(\rgb_buffer_reg[642] [8]),
.R(1'b0));
FDRE \rgb_buffer_reg[642][9]
(.C(clk_25),
.CE(active),
.D(D[9]),
.Q(\rgb_buffer_reg[642] [9]),
.R(1'b0));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[66] " *)
(* srl_name = "\U0/rgb_buffer_reg[66][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[66][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[34][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[66][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[66][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [0]),
.Q(\NLW_rgb_buffer_reg[674][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [10]),
.Q(\NLW_rgb_buffer_reg[674][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [11]),
.Q(\NLW_rgb_buffer_reg[674][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [12]),
.Q(\NLW_rgb_buffer_reg[674][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [13]),
.Q(\NLW_rgb_buffer_reg[674][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [14]),
.Q(\NLW_rgb_buffer_reg[674][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [15]),
.Q(\NLW_rgb_buffer_reg[674][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [16]),
.Q(\NLW_rgb_buffer_reg[674][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [17]),
.Q(\NLW_rgb_buffer_reg[674][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [18]),
.Q(\NLW_rgb_buffer_reg[674][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [19]),
.Q(\NLW_rgb_buffer_reg[674][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [1]),
.Q(\NLW_rgb_buffer_reg[674][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [20]),
.Q(\NLW_rgb_buffer_reg[674][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [21]),
.Q(\NLW_rgb_buffer_reg[674][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [22]),
.Q(\NLW_rgb_buffer_reg[674][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [23]),
.Q(\NLW_rgb_buffer_reg[674][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [2]),
.Q(\NLW_rgb_buffer_reg[674][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [3]),
.Q(\NLW_rgb_buffer_reg[674][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [4]),
.Q(\NLW_rgb_buffer_reg[674][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [5]),
.Q(\NLW_rgb_buffer_reg[674][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [6]),
.Q(\NLW_rgb_buffer_reg[674][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [7]),
.Q(\NLW_rgb_buffer_reg[674][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [8]),
.Q(\NLW_rgb_buffer_reg[674][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[674] " *)
(* srl_name = "\U0/rgb_buffer_reg[674][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[674][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[642] [9]),
.Q(\NLW_rgb_buffer_reg[674][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[674][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[706] " *)
(* srl_name = "\U0/rgb_buffer_reg[706][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[706][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[674][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[706][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[706][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[738] " *)
(* srl_name = "\U0/rgb_buffer_reg[738][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[738][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[706][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[738][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[738][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[770] " *)
(* srl_name = "\U0/rgb_buffer_reg[770][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[770][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[738][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[770][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[770][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[802] " *)
(* srl_name = "\U0/rgb_buffer_reg[802][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[802][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[770][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[802][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[802][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[834] " *)
(* srl_name = "\U0/rgb_buffer_reg[834][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[834][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[802][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[834][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[834][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[866] " *)
(* srl_name = "\U0/rgb_buffer_reg[866][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[866][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[834][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[866][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[866][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][0]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][0]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][10]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][10]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][11]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][11]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][12]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][12]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][13]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][13]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][14]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][14]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][15]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][15]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][16]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][16]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][17]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][17]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][18]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][18]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][19]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][19]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][1]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][1]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][20]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][20]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][21]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][21]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][22]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][22]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][23]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][23]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][2]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][2]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][3]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][3]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][4]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][4]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][5]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][5]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][6]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][6]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][7]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][7]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][8]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][8]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[898] " *)
(* srl_name = "\U0/rgb_buffer_reg[898][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[898][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[866][9]_srl32_n_1 ),
.Q(\rgb_buffer_reg[898][9]_srl32_n_0 ),
.Q31(\NLW_rgb_buffer_reg[898][9]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][0]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][10]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][11]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][12]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][13]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][14]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][15]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][16]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][17]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][18]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][19]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][1]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][20]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][21]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][22]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][23]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][2]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][3]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][4]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][5]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][6]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][7]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][8]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[930] " *)
(* srl_name = "\U0/rgb_buffer_reg[930][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[930][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[898][9]_srl32_n_0 ),
.Q(\NLW_rgb_buffer_reg[930][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[930][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[962] " *)
(* srl_name = "\U0/rgb_buffer_reg[962][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[962][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[930][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[962][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[962][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[98] " *)
(* srl_name = "\U0/rgb_buffer_reg[98][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[98][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[66][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[98][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[98][9]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][0]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][0]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][0]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][0]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][0]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][10]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][10]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][10]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][10]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][10]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][11]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][11]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][11]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][11]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][11]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][12]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][12]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][12]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][12]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][12]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][13]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][13]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][13]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][13]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][13]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][14]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][14]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][14]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][14]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][14]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][15]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][15]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][15]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][15]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][15]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][16]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][16]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][16]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][16]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][16]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][17]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][17]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][17]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][17]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][17]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][18]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][18]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][18]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][18]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][18]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][19]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][19]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][19]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][19]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][19]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][1]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][1]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][1]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][1]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][1]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][20]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][20]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][20]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][20]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][20]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][21]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][21]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][21]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][21]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][21]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][22]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][22]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][22]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][22]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][22]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][23]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][23]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][23]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][23]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][23]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][2]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][2]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][2]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][2]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][2]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][3]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][3]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][3]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][3]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][3]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][4]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][4]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][4]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][4]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][4]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][5]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][5]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][5]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][5]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][5]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][6]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][6]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][6]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][6]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][6]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][7]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][7]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][7]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][7]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][7]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][8]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][8]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][8]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][8]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][8]_srl32_n_1 ));
(* srl_bus_name = "\U0/rgb_buffer_reg[994] " *)
(* srl_name = "\U0/rgb_buffer_reg[994][9]_srl32 " *)
SRLC32E \rgb_buffer_reg[994][9]_srl32
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(active),
.CLK(clk_25),
.D(\rgb_buffer_reg[962][9]_srl32_n_1 ),
.Q(\NLW_rgb_buffer_reg[994][9]_srl32_Q_UNCONNECTED ),
.Q31(\rgb_buffer_reg[994][9]_srl32_n_1 ));
FDRE \rgb_pass_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(D[0]),
.Q(rgb_pass[0]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[10]
(.C(clk_25),
.CE(1'b1),
.D(D[10]),
.Q(rgb_pass[10]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[11]
(.C(clk_25),
.CE(1'b1),
.D(D[11]),
.Q(rgb_pass[11]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[12]
(.C(clk_25),
.CE(1'b1),
.D(D[12]),
.Q(rgb_pass[12]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[13]
(.C(clk_25),
.CE(1'b1),
.D(D[13]),
.Q(rgb_pass[13]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[14]
(.C(clk_25),
.CE(1'b1),
.D(D[14]),
.Q(rgb_pass[14]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[15]
(.C(clk_25),
.CE(1'b1),
.D(D[15]),
.Q(rgb_pass[15]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[16]
(.C(clk_25),
.CE(1'b1),
.D(D[16]),
.Q(rgb_pass[16]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[17]
(.C(clk_25),
.CE(1'b1),
.D(D[17]),
.Q(rgb_pass[17]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[18]
(.C(clk_25),
.CE(1'b1),
.D(D[18]),
.Q(rgb_pass[18]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[19]
(.C(clk_25),
.CE(1'b1),
.D(D[19]),
.Q(rgb_pass[19]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(D[1]),
.Q(rgb_pass[1]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[20]
(.C(clk_25),
.CE(1'b1),
.D(D[20]),
.Q(rgb_pass[20]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[21]
(.C(clk_25),
.CE(1'b1),
.D(D[21]),
.Q(rgb_pass[21]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[22]
(.C(clk_25),
.CE(1'b1),
.D(D[22]),
.Q(rgb_pass[22]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[23]
(.C(clk_25),
.CE(1'b1),
.D(D[23]),
.Q(rgb_pass[23]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(D[2]),
.Q(rgb_pass[2]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(D[3]),
.Q(rgb_pass[3]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(D[4]),
.Q(rgb_pass[4]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(D[5]),
.Q(rgb_pass[5]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(D[6]),
.Q(rgb_pass[6]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(D[7]),
.Q(rgb_pass[7]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(D[8]),
.Q(rgb_pass[8]),
.R(\rgb_blur[23]_i_1_n_0 ));
FDRE \rgb_pass_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(D[9]),
.Q(rgb_pass[9]),
.R(\rgb_blur[23]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
|
// ***********************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/fifo/fifo_checksum.v,v 1.8 2014/08/28 22:04:32 neal Exp $
// ***********************************************************
// Description:
//
// Calculates checksums on FIFO wr/rd data.
// ***********************************************************
// $Log: fifo_checksum.v,v $
// Revision 1.8 2014/08/28 22:04:32 neal
// Fixed bus indexes.
//
// Revision 1.7 2014/07/21 18:21:18 neal
// Shrank the checksum logic.
//
// Revision 1.6 2014/07/18 16:59:56 neal
// Added an option to control the checksum delay from write to read.
// Added an optional selram fifo for the clock domain change.
//
// Revision 1.5 2014/07/10 18:20:05 neal
// Increased the size of the shift, to account for different clock rates.
//
// Revision 1.4 2014/07/08 15:20:02 neal
// Added optional output register with REGCE to rams.
// Added option to use RAM's output register.
// Added checksums to all async fifos (enabled by define).
//
// Revision 1.3 2014/07/02 12:54:39 neal
// Disabled some of the extra checksum checks (to make it smaller).
//
// Revision 1.2 2014/07/01 23:03:50 neal
// Fixed an unregistered reset that changes clock domains.
//
// Revision 1.1 2014/07/01 19:18:46 neal
// Added checksums to wr_din and rd_dout with a sticky error bit that can be read back.
//
// ***********************************************************
`ifdef INCL_FIFO_CHECKSUM_V
`else
`define INCL_FIFO_CHECKSUM_V
`ifndef DEBUG_KEEP
`define DEBUG_KEEP (* dont_touch="TRUE", keep="TRUE" *)
`endif // DEBUG_KEEP
(* keep_hierarchy = "yes" *) module fifo_checksum #(
parameter DATA_W = 1,
parameter ONECLOCK = 1,
parameter EXTERNALLY_OUTPUT_REGISTERED = 0,
parameter ERROR_SHIFT_BITS = 4
) (
input wr_reset,
input rd_reset,
input wr_clk,
input wr_en,
input wr_full,
input [DATA_W-1:0] wr_data,
input rd_clk,
input rd_en,
input rd_empty,
input [DATA_W-1:0] rd_data,
`DEBUG_KEEP output reg checksum_error
);
// ******************************************
// Generate running checksum on wr_data.
// Only pay attention to the first 8-bits of the data for the checksum.
// ******************************************
localparam CHECKSUM_W = (DATA_W<16) ? (DATA_W+1)/2 : 4;
reg [CHECKSUM_W-1:0] wr_checksum;
always @(posedge wr_clk) begin
if ((wr_en==1'b1) && (wr_full==1'b0)) begin
wr_checksum <= wr_checksum ^ wr_data ^ (wr_data >> CHECKSUM_W);
end
if (wr_reset ) begin
wr_checksum <= 'b0;
end
end
// ******************************************
// Generate running checksum on rd_data.
// ******************************************
reg [CHECKSUM_W-1:0] rd_checksum;
always @(posedge rd_clk) begin
if ((rd_en==1'b1) && (rd_empty==1'b0)) begin
rd_checksum <= rd_checksum ^ rd_data ^ (rd_data >> CHECKSUM_W);
end
if (rd_reset) begin
rd_checksum <= 'b0;
end
end
// ******************************************
// Compare wr_checksum to rd_checksum when the FIFO is really empty.
// ******************************************
reg error_shift;
reg [ERROR_SHIFT_BITS-1:0] error_counter;
always @(posedge rd_clk) begin
if (
`ifdef USE_SYNC_FIFO_CHECKSUM
`else
ONECLOCK |
`endif
EXTERNALLY_OUTPUT_REGISTERED) begin
// do nothing (i.e. don't create the FFs)
end else begin
error_shift <= 1'b0;
if (rd_empty==1'b1) begin
if (rd_checksum != wr_checksum) begin
error_shift <= 1'b1;
end
end
if (error_shift==1'b1)
error_counter <= error_counter+1'b1;
else
error_counter <= 1'b0;
if (&error_counter) begin
$display("ERROR: %m fifo checksums don't match: %x != %x\n",wr_checksum, rd_checksum);
$stop;
checksum_error <= 1'b1;
end
if (rd_reset) begin
checksum_error <= 1'b0;
error_shift <= 'b0;
error_counter <= 'b0;
end
end
end
endmodule // fifo_checksum
`endif // INCL_FIFO_CHECKSUM_V
|
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
module io_2to1
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src0_clk,
input wire src1_clk,
input wire snk0_clk,
input wire reset,
// SRC_0
`NS_DECLARE_OUT_CHNL(o0),
// SRC_1
`NS_DECLARE_OUT_CHNL(o1),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src0_clk, reset, o0)
`NS_DEBOUNCER_ACK(src1_clk, reset, o1)
`NS_DEBOUNCER_REQ(snk0_clk, reset, i0)
`NS_DECLARE_REG_DBG(rg_dbg)
reg [3:0] cnt_0 = 0;
reg [3:0] cnt_1 = 0;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [0:0] ro0_busy = `NS_OFF;
reg [ASZ-1:0] ro0_src = 0;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [DSZ-1:0] ro0_dat = 0;
reg [RSZ-1:0] ro0_red = 0;
reg [0:0] ro0_req = `NS_OFF;
reg [0:0] ro0_err = `NS_OFF;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
ro0_c_red (ro0_src, ro0_dst, ro0_dat, ro0_redun);
// SRC regs
reg [0:0] ro1_has_dst = `NS_OFF;
reg [0:0] ro1_has_dat = `NS_OFF;
reg [0:0] ro1_has_red = `NS_OFF;
reg [0:0] ro1_busy = `NS_OFF;
reg [ASZ-1:0] ro1_src = 1;
reg [ASZ-1:0] ro1_dst = MIN_ADDR;
reg [DSZ-1:0] ro1_dat = 0;
reg [RSZ-1:0] ro1_red = 0;
reg [0:0] ro1_req = `NS_OFF;
reg [0:0] ro1_err = `NS_OFF;
wire [RSZ-1:0] ro1_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
ro1_c_red (ro1_src, ro1_dst, ro1_dat, ro1_redun);
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
`NS_DECLARE_REG_MSG(inp0)
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_ack = `NS_OFF;
reg [0:0] inp0_err = `NS_OFF;
reg [DSZ-1:0] r_0_ck_dat = 15;
reg [DSZ-1:0] r_1_ck_dat = 15;
reg [0:0] r_0_err = `NS_OFF;
reg [0:0] r_1_err = `NS_OFF;
reg [0:0] r_2_err = `NS_OFF;
//SRC_0
always @(posedge src0_clk)
begin
if((! ro0_req) && (! o0_ckd_ack)) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
ro0_req <= `NS_ON;
end
end
if(ro0_req && o0_ckd_ack) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
//SRC_1
always @(posedge src1_clk)
begin
if((! ro1_req) && (! o1_ckd_ack)) begin
if(! ro1_has_dst) begin
ro1_has_dst <= `NS_ON;
ro1_dst <= `NS_DBG_NXT_ADDR(ro1_dst);
end
else
if(! ro1_has_dat) begin
ro1_has_dat <= `NS_ON;
ro1_dat[3:0] <= cnt_1;
cnt_1 <= cnt_1 + 1;
end
else
if(! ro1_has_red) begin
ro1_has_red <= `NS_ON;
ro1_red <= ro1_redun;
end
if(ro1_has_red) begin
ro1_req <= `NS_ON;
end
end
if(ro1_req && o1_ckd_ack) begin
ro1_has_dst <= `NS_OFF;
ro1_has_dat <= `NS_OFF;
ro1_has_red <= `NS_OFF;
ro1_req <= `NS_OFF;
end
end
//SNK_0
always @(posedge snk0_clk)
begin
if(i0_ckd_req && (! inp0_ack)) begin
if(! has_inp0) begin
has_inp0 <= `NS_ON;
`NS_MOV_REG_MSG(inp0, i0)
end
else
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err) begin
if(! r_0_err && (inp0_src == 0)) begin
if(inp0_red != inp0_redun) begin
inp0_err <= `NS_ON;
r_0_err <= `NS_ON;
end
else
if((r_0_ck_dat <= 14) && ((r_0_ck_dat + 1) != inp0_dat)) begin
r_0_err <= `NS_ON;
end else begin
r_0_ck_dat <= inp0_dat;
end
end
if(! r_1_err && (inp0_src == 1)) begin
if(inp0_red != inp0_redun) begin
inp0_err <= `NS_ON;
r_1_err <= `NS_ON;
end
else
if((r_1_ck_dat <= 14) && ((r_1_ck_dat + 1) != inp0_dat)) begin
r_1_err <= `NS_ON;
end else begin
r_1_ck_dat <= inp0_dat;
end
end
end
end
if(inp0_done_cks) begin
rg_dbg_disp0 <= inp0_dat[3:0];
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
inp0_ack <= `NS_ON;
end
end
else
if((! i0_ckd_req) && inp0_ack) begin
inp0_ack <= `NS_OFF;
end
end
//SRC_0
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SRC_1
`NS_ASSIGN_MSG(o1, ro1)
assign o1_req_out = ro1_req;
//SNK_0
assign i0_ack_out = inp0_ack;
assign dbg_leds[0:0] = r_0_err;
assign dbg_leds[1:1] = r_1_err;
assign dbg_leds[2:2] = (ro0_err || ro1_err || r_2_err);
assign dbg_leds[3:3] = 0;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V |
`timescale 1ns / 1ps
// -*- Mode: Verilog -*-
// Filename : controller.v
// Description : Description of the controller logic for our simplified MIPS processor.
// Author : Pallav Gupta
// Created On : Thu Oct 23 20:34:04 2008
// Last Modified On: Time-stamp: <2009-05-05 17:17:50 pgupta>
// Update Count : 0
// Status : Unknown, Use with caution!
// This module describes a controller for a multicycle MIPS processor like that
// given in Patterson and Hennessy. It contains the control FSM and the
// additional AND/OR logic for branching. It does not contain the alucontrol
// logic.
// Using busses would be cleaner, but is not supported well by the Electric
// Silicon Compiler.
// reference time unit is 1 nanosecond
`timescale 1ns/1ps
module controller(/*AUTOARG*/
// Outputs
memread, memwrite, irwrite3, irwrite2, irwrite1, irwrite0, pcen, regwrite,
aluop1, aluop0, alusrca, alusrcb1, alusrcb0, pcsource1, pcsource0, iord,
memtoreg, regdst,
// Inputs
ph1, ph2, reset, op5, op4, op3, op2, op1, op0, zero
);
input ph1, ph2;
input reset;
input op5, op4, op3, op2, op1, op0;
input zero;
output reg memread;
output reg memwrite;
output reg irwrite3, irwrite2, irwrite1, irwrite0;
output pcen;
output reg regwrite;
output reg aluop1, aluop0;
output reg alusrca;
output reg alusrcb1, alusrcb0;
output reg pcsource1, pcsource0;
output reg iord;
output reg memtoreg;
output reg regdst;
// multicycle state machine state definitions
parameter FETCH1 = 4'b0000; // instruction fetch (4 cycles, 8-bit datapath)
parameter FETCH2 = 4'b0001;
parameter FETCH3 = 4'b0010;
parameter FETCH4 = 4'b0011;
parameter DECODE = 4'b0100; // instruction decode
parameter MEMADR = 4'b0101; // memory address computation
parameter LBRD = 4'b0110; // load byte read
parameter LBWR = 4'b0111; // load byte writeback
parameter SBWR = 4'b1000; // store writeback
parameter RTYPEEX= 4'b1001; // R-type instruction execution
parameter RTYPEWR= 4'b1010; // R-type instruction writeback
parameter BEQEX = 4'b1011; // branch on equal execution
parameter JEX = 4'b1100; // jump execution
// add extra states for ADDI here, use unique code (continue above sequence)
parameter ADDIEX = 4'b1101;
parameter ADDIWR = 4'b1110;
// instruction opcodes (do not modify!)
parameter LB = 6'b100000;
parameter SB = 6'b101000;
parameter RTYPE = 6'b000000;
parameter BEQ = 6'b000100;
parameter J = 6'b000010;
parameter ADDI = 6'b001000;
// internal signals
reg [3:0] nextstate_s2;
reg [3:0] state_s1, state_s2;
reg pcwrite, pcwritecond;
// update state regiter (comprised of master/slave latch)
always @(/*AUTOSENSE*/nextstate_s2 or ph2) // update master latch
if (ph2) state_s1 = nextstate_s2;
always @(/*AUTOSENSE*/ph1 or state_s1) // update slave latch
if (ph1) state_s2 = state_s1;
// next state logic
always @(/*AUTOSENSE*/op0 or op1 or op2 or op3 or op4 or op5 or reset
or state_s2)
// state transition figure is given in the write up
if (reset) nextstate_s2 = FETCH1; // synchronous reset
else case (state_s2)
// fetch
FETCH1: nextstate_s2 = FETCH2;
FETCH2: nextstate_s2 = FETCH3;
FETCH3: nextstate_s2 = FETCH4;
FETCH4: nextstate_s2 = DECODE;
// decode, look at opcode
DECODE: case ({op5, op4, op3, op2, op1, op0})
LB: nextstate_s2 = MEMADR;
SB: nextstate_s2 = MEMADR;
RTYPE: nextstate_s2 = RTYPEEX;
BEQ: nextstate_s2 = BEQEX;
J: nextstate_s2 = JEX;
// add support for ADDI here
default: nextstate_s2 = FETCH1;
endcase // case ({op5, op4, op3, op2, op1, op0})
// memory adress compute (for load/store)
MEMADR: case ({op5, op4, op3, op2, op1, op0}) // synopsys full_case
LB: nextstate_s2 = LBRD;
SB: nextstate_s2 = SBWR;
// no default needed becaus of full_case directive
endcase // case ({op5, op4, op3, op2, op1, op0})
LBRD: nextstate_s2 = LBWR;
LBWR: nextstate_s2 = FETCH1;
SBWR: nextstate_s2 = FETCH1;
RTYPEEX: nextstate_s2 = RTYPEWR;
RTYPEWR: nextstate_s2 = FETCH1;
BEQEX: nextstate_s2 = FETCH1;
JEX: nextstate_s2 = FETCH1;
// add support for ADDI here
default: nextstate_s2 = FETCH1;
endcase
// output logic
always @(/*AUTOSENSE*/state_s2)
begin
// provide default values for signals not specified
memread = 0;
memwrite = 0;
irwrite3 = 0; irwrite2 = 0; irwrite1 = 0; irwrite0 = 0;
pcwrite = 0;
pcwritecond = 0;
regwrite = 0;
alusrca = 0;
alusrcb1 = 0; alusrcb0 = 0;
aluop1 = 0; aluop0 = 0;
pcsource1 = 0; pcsource0 = 0;
iord = 0;
memtoreg = 0;
regdst = 0;
// specify the outputs for reach state according to FSM
case (state_s2)
FETCH1: begin
memread = 1;
alusrca = 0;
iord = 0;
irwrite3 = 1; // endianness
alusrcb1 = 0; alusrcb0 = 1;
aluop1 = 0; aluop0 = 0;
pcwrite = 1;
pcsource1 = 0; pcsource0 = 0;
end
FETCH2: begin
memread = 1;
alusrca = 0;
iord = 0;
irwrite2 = 1; // endianness
alusrcb1 = 0; alusrcb0 = 1;
aluop1 = 0; aluop0 = 0;
pcwrite = 1;
pcsource1 = 0; pcsource0 = 0;
end
FETCH3: begin
memread = 1;
alusrca = 0;
iord = 0;
irwrite1 = 1; // endianness
alusrcb1 = 0; alusrcb0 = 1;
aluop1 = 0; aluop0 = 0;
pcwrite = 1;
pcsource1 = 0; pcsource0 = 0;
end
FETCH4: begin
memread = 1;
alusrca = 0;
iord = 0;
irwrite0 = 1; // endianness
alusrcb1 = 0; alusrcb0 = 1;
aluop1 = 0; aluop0 = 0;
pcwrite = 1;
pcsource1 = 0; pcsource0 = 0;
end
DECODE: begin
alusrca = 0;
alusrcb1 = 1; alusrcb0 = 1;
aluop1 = 0; aluop0 = 0;
end
MEMADR: begin
alusrca = 1;
alusrcb1 = 1; alusrcb0 = 0;
aluop1 = 0; aluop0 = 0;
end
LBRD: begin
memread = 1;
iord = 1;
end
LBWR: begin
regdst = 0;
regwrite = 1;
memtoreg = 1;
end
SBWR: begin
memwrite = 1;
iord = 1;
end
RTYPEEX: begin
alusrca = 1;
alusrcb1 = 0; alusrcb0 = 0;
aluop1 = 1; aluop0 = 0;
end
RTYPEWR: begin
regdst = 1;
regwrite = 1;
memtoreg = 0;
end
BEQEX: begin
alusrca = 1;
alusrcb1 = 0; alusrcb0 = 0;
aluop1 = 0; aluop0 = 1;
pcwritecond = 1;
pcsource1 = 0; pcsource0 = 1;
end
JEX: begin
pcwrite = 1;
aluop0 = 1; // not logically required, but a hack to ensure aluop0
// and pcsource0 aren't always identical. If they
// were identical, Synopsys would optimize one away,
// which confuses the Silicon Compiler.
pcsource1 = 1; pcsource0 = 0;
end
// add support for ADDI here
default: begin
end
endcase // case (state_s2)
end // always @ (state_s2)
// compute pcen, the write enable for the program counter
assign pcen = pcwrite | (pcwritecond & zero);
endmodule
// Controller testbench: Supplies test vectors and dumps the results to file and
// standard output. Do not modify!
module controller_tb;
reg ph1, ph2, reset;
reg [5:0] opcode;
reg zero;
wire memread;
wire memwrite;
wire [3:0] irwrite;
wire pcen;
wire regwrite;
wire [1:0] aluop;
wire alusrca;
wire [1:0] alusrcb;
wire [1:0] pcsource;
wire iord;
wire memtoreg;
wire regdst;
wire pcwritecond;
wire pcwrite;
// instatiate device under test and connect the signals
controller U0(
// inputs
.ph1 (ph1),
.ph2 (ph2),
.reset (reset),
.op5 (opcode[5]), .op4 (opcode[4]), .op3 (opcode[3]),
.op2 (opcode[2]), .op1 (opcode[1]), .op0 (opcode[0]),
.zero (zero),
// ouputs
.memread (memread),
.memwrite (memwrite),
.irwrite3 (irwrite[3]), .irwrite2 (irwrite[2]),
.irwrite1 (irwrite[1]), .irwrite0 (irwrite[0]),
.pcen (pcen),
.regwrite (regwrite),
.aluop1 (aluop[1]), .aluop0 (aluop[0]),
.alusrca (alusrca),
.alusrcb1 (alusrcb[1]), .alusrcb0 (alusrcb[0]),
.pcsource1 (pcsource[1]), .pcsource0 (pcsource[0]),
.iord (iord),
.memtoreg (memtoreg),
.regdst (regdst));
// initialization (reset is high)
initial
begin
ph1 <= 0;
ph2 <= 0;
reset <= 1;
zero = 0;
end
// generate a two-phase non-overlapping clock (period is 8 units)
always begin
#2 ph1 = 1;
#2 ph1 = 0;
#4 ph1 = 0;
end
always begin
#6 ph2 = 1;
#2 ph2 = 0;
end
// dump all the signals info file. use with a waveform viewer to see the signals
initial begin
$dumpfile("controller.vcd");
$dumpvars;
end
initial begin
// bring out of reset and supply the first opcode lb
#2 reset = 0; opcode = 6'b100000;
$display("%s %s %s %s %s %s %s %s %s %s %s %s", "memread", "alusrca", "iord", "irwrite",
"alusrcb", "aluop", "pcen", "pcsource", "regdst", "regwrite",
"memtoreg", "memwrite");
$display("opcode = %b", opcode);
// sb
#72 opcode = 6'b101000;
$display("opcode = %b", opcode);
// r-type instructions
#56 opcode = 6'b000000;
$display("opcode = %b", opcode);
// beq
#56 opcode = 6'b000100;
$display("opcode = %b", opcode);
#40 zero = 1'b1; // check that zero works in BEQEX
// jump
#8 opcode = 6'b000010;
$display("opcode = %b", opcode);
// addi
#48 opcode = 6'b001000;
$display("opcode = %b", opcode);
// terminate simulation
#56 $finish;
end
// print the values of all relevant signals every clock period
always
#8 $display("%5b %6b %6b %6b %7b %5b %4b %8b %7b %6b %8b %7b", memread, alusrca, iord, irwrite, alusrcb, aluop,
pcen, pcsource, regdst, regwrite, memtoreg, memwrite);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:53:54 04/01/2013
// Design Name:
// Module Name: async_fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module async_fifo(
i_push,
i_pop,
i_reset,
i_wclk,
i_rclk,
i_wdata,
o_rdata,
o_full,
o_empty
);
parameter F_WIDTH = 4;
parameter F_SIZE = 1 << F_WIDTH;
parameter F_MAX = 32; // max number of elements we want to store
input i_reset;
input i_rclk;
input i_wclk;
input i_push;
input i_pop;
input [65:0] i_wdata;
output reg [65:0] o_rdata;
output reg o_empty;
output reg o_full;
reg [F_WIDTH-1:0] read_pos;
reg [F_WIDTH-1:0] write_pos;
reg [65:0] memory[F_SIZE -1 : 0];
reg [7:0] total_count; // the number of elements currently in the FIFO
reg [7:0] read_counter;
reg [7:0] write_counter;
// Update empty and full indicators whenever total_count changes
always @(*) begin
total_count = write_counter - read_counter;
o_empty = (total_count == 0);
o_full = (total_count == F_MAX);
end
// Handle writes (push)
always @(posedge i_wclk) begin
if(i_reset) begin
write_counter <= 0;
write_pos <= 0;
end
else if(!o_full && i_push) begin
memory[write_pos] <= i_wdata;
write_pos <= write_pos + 1'b1;
write_counter <= write_counter + 1'b1;
end
end
// Handle reads (pop)
always @(posedge i_rclk) begin
if(i_reset) begin
read_counter <= 0;
read_pos <= 0;
end
else if(!o_empty && i_pop) begin
o_rdata <= memory[read_pos];
read_pos <= read_pos + 1'b1;
read_counter <= read_counter + 1'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_LP_V
`define SKY130_FD_SC_LP__ISO0P_LP_V
/**
* iso0p: ????.
*
* Verilog wrapper for iso0p with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0p_lp (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso0p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0p_lp (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso0p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_LP_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxr_engine_128.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXR Engine (Classic) takes a single stream of TLP
// packets and provides the request packets on the RXR Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "tlp.vh"
module rxr_engine_128
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXR_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXR
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
`include "functions.vh"
/*AUTOWIRE*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1;
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXR Engine
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_STRADDLE_W = 64;
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_FBE_W + `SIG_LBE_W + `SIG_TC_W + `SIG_ATTR_W + `SIG_TAG_W + `SIG_TYPE_W + `SIG_ADDR_W + `SIG_BARDECODE_W + `SIG_REQID_W + `SIG_LEN_W;
// Header Reg Inputs
wire [`SIG_OFFSET_W-1:0] __wRxrStartOffset;
wire [`SIG_OFFSET_W-1:0] __wRxrStraddledStartOffset;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdr;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrStraddled;
wire [`TLP_MAXHDR_W-1:0] __wRxrHdrNotStraddled;
wire __wRxrHdrValid;
wire [`TLP_TYPE_W-1:0] __wRxrHdrType;
wire [`TLP_TYPE_W-1:0] __wRxrHdrTypeStraddled;
wire __wRxrHdrSOP; // Asserted on non-straddle SOP
wire __wRxrHdrSOPStraddle;
wire __wRxrHdr4DWHWDataSF;
// Header Reg Outputs
wire _wRxrHdrValid;
wire [`TLP_MAXHDR_W-1:0] _wRxrHdr;
wire [`SIG_ADDR_W-1:0] _wRxrAddrUnformatted;
wire [`SIG_ADDR_W-1:0] _wRxrAddr;
wire [63:0] _wRxrTlpMetadata;
wire [`TLP_TYPE_W-1:0] _wRxrType;
wire [`TLP_LEN_W-1:0] _wRxrLength;
wire [2:0] _wRxrHdrHdrLen;// TODO:
wire [`SIG_OFFSET_W-1:0] _wRxrHdrStartOffset;// TODO:
wire _wRxrHdrDelayedSOP;
wire _wRxrHdrSOPStraddle;
wire _wRxrHdrSOP;
wire _wRxrHdrSF;
wire _wRxrHdrEF;
wire _wRxrHdrSCP; // Single Cycle Packet
wire _wRxrHdrMCP; // Multi Cycle Packet
wire _wRxrHdrRegSF;
wire _wRxrHdrRegValid;
wire _wRxrHdr4DWHSF;
wire _wRxrHdr4DWHNoDataSF;
wire _wRxrHdr4DWHWDataSF;
wire _wRxrHdr3DWHSF;
wire [2:0] _wRxrHdrDataSoff;
wire [1:0] _wRxrHdrDataEoff;
wire [3:0] _wRxrHdrStartMask;
wire [3:0] _wRxrHdrEndMask;
// Header Reg Outputs
wire wRxrHdrSF;
wire wRxrHdrEF;
wire wRxrHdrValid;
wire [`TLP_MAXHDR_W-1:0] wRxrHdr;
wire [63:0] wRxrMetadata;
wire [`TLP_TYPE_W-1:0] wRxrType;
wire [`TLP_LEN_W-1:0] wRxrLength;
wire [2:0] wRxrHdrLength; // TODO:
wire [`SIG_OFFSET_W-1:0] wRxrHdrStartOffset; // TODO:
wire wRxrHdrSCP; // Single Cycle Packet
wire wRxrHdrMCP; // Multi Cycle Packet
wire [1:0] wRxrHdrDataSoff;
wire [3:0] wRxrHdrStartMask;
wire [3:0] wRxrHdrEndMask;
// Output Register Inputs
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire wRxrDataValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire wRxrDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset;
wire wRxrDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset;
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
wire [`SIG_TC_W-1:0] wRxrMetaTC;
wire [`SIG_ATTR_W-1:0] wRxrMetaAttr;
wire [`SIG_TAG_W-1:0] wRxrMetaTag;
wire [`SIG_TYPE_W-1:0] wRxrMetaType;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [`SIG_BARDECODE_W-1:0] wRxrMetaBarDecoded;
wire [`SIG_REQID_W-1:0] wRxrMetaRequesterId;
wire [`SIG_LEN_W-1:0] wRxrMetaLength;
wire wRxrMetaEP;
reg rStraddledSOP;
reg rStraddledSOPSplit;
reg rRST;
assign DONE_RXR_RST = ~rRST;
// ----- Header Register -----
assign __wRxrHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxrStartOffset[1];
assign __wRxrHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxrStraddledStartOffset[1];
assign __wRxrHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
assign __wRxrHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
assign __wRxrStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
assign __wRxrStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
assign __wRxrHdrValid = __wRxrHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
assign __wRxrHdr4DWHWDataSF = (_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdr[`TLP_PAYBIT_I] & RX_SR_VALID[C_RX_INPUT_STAGES] & _wRxrHdrDelayedSOP);
assign _wRxrHdrHdrLen = {_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I],~_wRxrHdr[`TLP_4DWHBIT_I]};
assign _wRxrHdrDataSoff = {1'b0,_wRxrHdrSOPStraddle,1'b0} + _wRxrHdrHdrLen;
assign _wRxrHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdr4DWHNoDataSF = _wRxrHdr[`TLP_4DWHBIT_I] & ~_wRxrHdr[`TLP_PAYBIT_I] & _wRxrHdrSOP;
assign _wRxrHdr4DWHSF = _wRxrHdr4DWHNoDataSF | (_wRxrHdr4DWHWDataSF & _wRxrHdrRegValid);
assign _wRxrHdr3DWHSF = ~_wRxrHdr[`TLP_4DWHBIT_I] & _wRxrHdrSOP;
assign _wRxrHdrSF = (_wRxrHdr3DWHSF | _wRxrHdr4DWHSF | _wRxrHdrSOPStraddle);
assign _wRxrHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxrHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
assign _wRxrHdrSCP = _wRxrHdrSF & _wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ);
assign _wRxrHdrMCP = (_wRxrHdrSF & ~_wRxrHdrEF & (_wRxrHdr[`TLP_TYPE_R] == `TLP_TYPE_REQ)) |
(wRxrHdrMCP & ~wRxrHdrEF);
assign _wRxrHdrStartMask = {4{_wRxrHdr[`TLP_PAYBIT_I]}} << (_wRxrHdrSF ? _wRxrHdrDataSoff[1:0] : 0);
assign wRxrDataWordEnable = wRxrHdrEndMask & wRxrHdrStartMask & {4{wRxrDataValid}};
assign wRxrDataValid = wRxrHdrSCP | wRxrHdrMCP;
assign wRxrDataStartFlag = wRxrHdrSF;
assign wRxrDataEndFlag = wRxrHdrEF;
assign wRxrDataStartOffset = wRxrHdrDataSoff;
assign wRxrMetaFdwbe = wRxrHdr[`TLP_REQFBE_R];
assign wRxrMetaLdwbe = wRxrHdr[`TLP_REQLBE_R];
assign wRxrMetaTC = wRxrHdr[`TLP_TC_R];
assign wRxrMetaAttr = {wRxrHdr[`TLP_ATTR1_R], wRxrHdr[`TLP_ATTR0_R]};
assign wRxrMetaTag = wRxrHdr[`TLP_REQTAG_R];
assign wRxrMetaAddr = wRxrHdr[`TLP_REQADDRDW0_I +: `TLP_REQADDR_W];/* TODO: REQADDR_R*/
assign wRxrMetaRequesterId = wRxrHdr[`TLP_REQREQID_R];
assign wRxrMetaLength = wRxrHdr[`TLP_LEN_R];
assign wRxrMetaEP = wRxrHdr[`TLP_EP_R];
assign wRxrMetaType = tlp_to_trellis_type({wRxrHdr[`TLP_FMT_R],wRxrHdr[`TLP_TYPE_R]});
assign RXR_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
assign RXR_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
always @(posedge CLK) begin
rStraddledSOP <= __wRxrHdrSOPStraddle;
// Set Straddled SOP Split when there is a straddled packet where the
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.
if(__wRxrHdrSOP | rRST) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (__wRxrHdrSOPStraddle | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
mux
#(
// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (`TLP_MAXHDR_W),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
hdr_mux
(
// Outputs
.MUX_OUTPUT (__wRxrHdr[`TLP_MAXHDR_W-1:0]),
// Inputs
.MUX_INPUTS ({__wRxrHdrStraddled[`TLP_MAXHDR_W-1:0],
__wRxrHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
/*AUTOINST*/);
register
#(
// Parameters
.C_WIDTH (64 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_63_0
(
// Outputs
.RD_DATA ({_wRxrHdr[C_STRADDLE_W-1:0], _wRxrHdrValid}),
// Inputs
.WR_DATA ({__wRxrHdr[C_STRADDLE_W-1:0], __wRxrHdrValid}),
.WR_EN (__wRxrHdrSOP | rStraddledSOP),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sf4dwh
(
// Outputs
.RD_DATA ({_wRxrHdr4DWHWDataSF, _wRxrHdrSOPStraddle,_wRxrHdrSOP}),
// Inputs
.WR_DATA ({__wRxrHdr4DWHWDataSF,rStraddledSOP,__wRxrHdrSOP}),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
delayed_sop
(
// Outputs
.RD_DATA ({_wRxrHdrDelayedSOP}),
// Inputs
.WR_DATA ({__wRxrHdrSOP}),
.WR_EN (RX_SR_VALID[C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (64),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_127_64
(
// Outputs
.RD_DATA (_wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
// Inputs
.WR_DATA (__wRxrHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxrHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// ----- Computation Register -----
register
#(
// Parameters
.C_WIDTH (64 + 4),/* TODO: TLP_METADATA_W*/
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata
(// Outputs
.RD_DATA ({wRxrHdr[`TLP_REQMETADW0_I +: 64],
wRxrHdrSF,wRxrHdrDataSoff,
wRxrHdrEF}),/* TODO: TLP_METADATA_R and other signals*/
// Inputs
.RST_IN (0),
.WR_DATA ({_wRxrHdr[`TLP_REQMETADW0_I +: 64],
_wRxrHdrSF,_wRxrHdrDataSoff[1:0],
_wRxrHdrEF}),/* TODO: TLP_METADATA_R*/
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (3+8),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_valid
(// Output
.RD_DATA ({wRxrHdrValid,
wRxrHdrSCP, wRxrHdrMCP,
wRxrHdrEndMask, wRxrHdrStartMask}),
// Inputs
.RST_IN (0),
.WR_DATA ({_wRxrHdrValid,
_wRxrHdrSCP, _wRxrHdrMCP,
_wRxrHdrEndMask, _wRxrHdrStartMask}),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`SIG_ADDR_W/2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_63_32
(// Outputs
.RD_DATA (wRxrHdr[`TLP_REQADDRHI_R]),
// Inputs
.RST_IN (~_wRxrHdr[`TLP_4DWHBIT_I]),
.WR_DATA (_wRxrHdr[`TLP_REQADDRLO_R]), // Instead of a mux, we'll use the reset
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`SIG_ADDR_W/2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_31_0
(// Outputs
.RD_DATA (wRxrHdr[`TLP_REQADDRLO_R]),
// Inputs
.RST_IN (0),// Never need to reset
.WR_DATA (_wRxrHdr[`TLP_4DWHBIT_I] ? _wRxrHdr[`TLP_REQADDRHI_R] : _wRxrHdr[`TLP_REQADDRLO_R]),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (4)
/*AUTOINSTPARAM*/)
o2m_ef
(// Outputs
.MASK (_wRxrHdrEndMask),
// Inputs
.OFFSET_ENABLE (_wRxrHdrEF),
.OFFSET (_wRxrHdrDataEoff)
/*AUTOINST*/);
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),// TODO:
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({RXR_DATA_WORD_ENABLE, RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET,
RXR_DATA_END_FLAG,
RXR_META_FDWBE, RXR_META_LDWBE, RXR_META_TC,
RXR_META_ATTR, RXR_META_TAG, RXR_META_TYPE,
RXR_META_ADDR, RXR_META_BAR_DECODED, RXR_META_REQUESTER_ID,
RXR_META_LENGTH, RXR_META_EP}),
.RD_DATA_VALID (RXR_DATA_VALID),
// Inputs
.WR_DATA ({wRxrDataWordEnable, wRxrDataStartFlag, wRxrDataStartOffset,
wRxrDataEndFlag,
wRxrMetaFdwbe, wRxrMetaLdwbe, wRxrMetaTC,
wRxrMetaAttr, wRxrMetaTag, wRxrMetaType,
wRxrMetaAddr, wRxrMetaBarDecoded, wRxrMetaRequesterId,
wRxrMetaLength, wRxrMetaEP}),
.WR_DATA_VALID (wRxrDataValid),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
// End:
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1
// RDY_server_reset_response_get O 1 reg
// imem_valid O 1
// imem_is_i32_not_i16 O 1 const
// imem_pc O 64 reg
// imem_instr O 32
// imem_exc O 1
// imem_exc_code O 4 reg
// imem_tval O 64 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 4 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 4 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// dmem_valid O 1
// dmem_word64 O 64
// dmem_st_amo_val O 64
// dmem_exc O 1
// dmem_exc_code O 4 reg
// dmem_master_awvalid O 1 reg
// dmem_master_awid O 4 reg
// dmem_master_awaddr O 64 reg
// dmem_master_awlen O 8 reg
// dmem_master_awsize O 3 reg
// dmem_master_awburst O 2 reg
// dmem_master_awlock O 1 reg
// dmem_master_awcache O 4 reg
// dmem_master_awprot O 3 reg
// dmem_master_awqos O 4 reg
// dmem_master_awregion O 4 reg
// dmem_master_wvalid O 1 reg
// dmem_master_wdata O 64 reg
// dmem_master_wstrb O 8 reg
// dmem_master_wlast O 1 reg
// dmem_master_bready O 1 reg
// dmem_master_arvalid O 1 reg
// dmem_master_arid O 4 reg
// dmem_master_araddr O 64 reg
// dmem_master_arlen O 8 reg
// dmem_master_arsize O 3 reg
// dmem_master_arburst O 2 reg
// dmem_master_arlock O 1 reg
// dmem_master_arcache O 4 reg
// dmem_master_arprot O 3 reg
// dmem_master_arqos O 4 reg
// dmem_master_arregion O 4 reg
// dmem_master_rready O 1 reg
// RDY_server_fence_i_request_put O 1
// RDY_server_fence_i_response_get O 1
// RDY_server_fence_request_put O 1 reg
// RDY_server_fence_response_get O 1
// RDY_sfence_vma O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// imem_req_f3 I 3
// imem_req_addr I 64
// imem_req_priv I 2 reg
// imem_req_sstatus_SUM I 1 reg
// imem_req_mstatus_MXR I 1 reg
// imem_req_satp I 64 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 4 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 4 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// dmem_req_op I 2
// dmem_req_f3 I 3
// dmem_req_amo_funct7 I 7 reg
// dmem_req_addr I 64
// dmem_req_store_value I 64
// dmem_req_priv I 2 reg
// dmem_req_sstatus_SUM I 1 reg
// dmem_req_mstatus_MXR I 1 reg
// dmem_req_satp I 64 reg
// dmem_master_awready I 1
// dmem_master_wready I 1
// dmem_master_bvalid I 1
// dmem_master_bid I 4 reg
// dmem_master_bresp I 2 reg
// dmem_master_arready I 1
// dmem_master_rvalid I 1
// dmem_master_rid I 4 reg
// dmem_master_rdata I 64 reg
// dmem_master_rresp I 2 reg
// dmem_master_rlast I 1 reg
// server_fence_request_put I 8 unused
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_imem_req I 1
// EN_dmem_req I 1
// EN_server_fence_i_request_put I 1
// EN_server_fence_i_response_get I 1
// EN_server_fence_request_put I 1
// EN_server_fence_response_get I 1
// EN_sfence_vma I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkNear_Mem(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
imem_req_f3,
imem_req_addr,
imem_req_priv,
imem_req_sstatus_SUM,
imem_req_mstatus_MXR,
imem_req_satp,
EN_imem_req,
imem_valid,
imem_is_i32_not_i16,
imem_pc,
imem_instr,
imem_exc,
imem_exc_code,
imem_tval,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
dmem_req_op,
dmem_req_f3,
dmem_req_amo_funct7,
dmem_req_addr,
dmem_req_store_value,
dmem_req_priv,
dmem_req_sstatus_SUM,
dmem_req_mstatus_MXR,
dmem_req_satp,
EN_dmem_req,
dmem_valid,
dmem_word64,
dmem_st_amo_val,
dmem_exc,
dmem_exc_code,
dmem_master_awvalid,
dmem_master_awid,
dmem_master_awaddr,
dmem_master_awlen,
dmem_master_awsize,
dmem_master_awburst,
dmem_master_awlock,
dmem_master_awcache,
dmem_master_awprot,
dmem_master_awqos,
dmem_master_awregion,
dmem_master_awready,
dmem_master_wvalid,
dmem_master_wdata,
dmem_master_wstrb,
dmem_master_wlast,
dmem_master_wready,
dmem_master_bvalid,
dmem_master_bid,
dmem_master_bresp,
dmem_master_bready,
dmem_master_arvalid,
dmem_master_arid,
dmem_master_araddr,
dmem_master_arlen,
dmem_master_arsize,
dmem_master_arburst,
dmem_master_arlock,
dmem_master_arcache,
dmem_master_arprot,
dmem_master_arqos,
dmem_master_arregion,
dmem_master_arready,
dmem_master_rvalid,
dmem_master_rid,
dmem_master_rdata,
dmem_master_rresp,
dmem_master_rlast,
dmem_master_rready,
EN_server_fence_i_request_put,
RDY_server_fence_i_request_put,
EN_server_fence_i_response_get,
RDY_server_fence_i_response_get,
server_fence_request_put,
EN_server_fence_request_put,
RDY_server_fence_request_put,
EN_server_fence_response_get,
RDY_server_fence_response_get,
EN_sfence_vma,
RDY_sfence_vma);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method imem_req
input [2 : 0] imem_req_f3;
input [63 : 0] imem_req_addr;
input [1 : 0] imem_req_priv;
input imem_req_sstatus_SUM;
input imem_req_mstatus_MXR;
input [63 : 0] imem_req_satp;
input EN_imem_req;
// value method imem_valid
output imem_valid;
// value method imem_is_i32_not_i16
output imem_is_i32_not_i16;
// value method imem_pc
output [63 : 0] imem_pc;
// value method imem_instr
output [31 : 0] imem_instr;
// value method imem_exc
output imem_exc;
// value method imem_exc_code
output [3 : 0] imem_exc_code;
// value method imem_tval
output [63 : 0] imem_tval;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [3 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [3 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [3 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [3 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// action method dmem_req
input [1 : 0] dmem_req_op;
input [2 : 0] dmem_req_f3;
input [6 : 0] dmem_req_amo_funct7;
input [63 : 0] dmem_req_addr;
input [63 : 0] dmem_req_store_value;
input [1 : 0] dmem_req_priv;
input dmem_req_sstatus_SUM;
input dmem_req_mstatus_MXR;
input [63 : 0] dmem_req_satp;
input EN_dmem_req;
// value method dmem_valid
output dmem_valid;
// value method dmem_word64
output [63 : 0] dmem_word64;
// value method dmem_st_amo_val
output [63 : 0] dmem_st_amo_val;
// value method dmem_exc
output dmem_exc;
// value method dmem_exc_code
output [3 : 0] dmem_exc_code;
// value method dmem_master_m_awvalid
output dmem_master_awvalid;
// value method dmem_master_m_awid
output [3 : 0] dmem_master_awid;
// value method dmem_master_m_awaddr
output [63 : 0] dmem_master_awaddr;
// value method dmem_master_m_awlen
output [7 : 0] dmem_master_awlen;
// value method dmem_master_m_awsize
output [2 : 0] dmem_master_awsize;
// value method dmem_master_m_awburst
output [1 : 0] dmem_master_awburst;
// value method dmem_master_m_awlock
output dmem_master_awlock;
// value method dmem_master_m_awcache
output [3 : 0] dmem_master_awcache;
// value method dmem_master_m_awprot
output [2 : 0] dmem_master_awprot;
// value method dmem_master_m_awqos
output [3 : 0] dmem_master_awqos;
// value method dmem_master_m_awregion
output [3 : 0] dmem_master_awregion;
// value method dmem_master_m_awuser
// action method dmem_master_m_awready
input dmem_master_awready;
// value method dmem_master_m_wvalid
output dmem_master_wvalid;
// value method dmem_master_m_wdata
output [63 : 0] dmem_master_wdata;
// value method dmem_master_m_wstrb
output [7 : 0] dmem_master_wstrb;
// value method dmem_master_m_wlast
output dmem_master_wlast;
// value method dmem_master_m_wuser
// action method dmem_master_m_wready
input dmem_master_wready;
// action method dmem_master_m_bvalid
input dmem_master_bvalid;
input [3 : 0] dmem_master_bid;
input [1 : 0] dmem_master_bresp;
// value method dmem_master_m_bready
output dmem_master_bready;
// value method dmem_master_m_arvalid
output dmem_master_arvalid;
// value method dmem_master_m_arid
output [3 : 0] dmem_master_arid;
// value method dmem_master_m_araddr
output [63 : 0] dmem_master_araddr;
// value method dmem_master_m_arlen
output [7 : 0] dmem_master_arlen;
// value method dmem_master_m_arsize
output [2 : 0] dmem_master_arsize;
// value method dmem_master_m_arburst
output [1 : 0] dmem_master_arburst;
// value method dmem_master_m_arlock
output dmem_master_arlock;
// value method dmem_master_m_arcache
output [3 : 0] dmem_master_arcache;
// value method dmem_master_m_arprot
output [2 : 0] dmem_master_arprot;
// value method dmem_master_m_arqos
output [3 : 0] dmem_master_arqos;
// value method dmem_master_m_arregion
output [3 : 0] dmem_master_arregion;
// value method dmem_master_m_aruser
// action method dmem_master_m_arready
input dmem_master_arready;
// action method dmem_master_m_rvalid
input dmem_master_rvalid;
input [3 : 0] dmem_master_rid;
input [63 : 0] dmem_master_rdata;
input [1 : 0] dmem_master_rresp;
input dmem_master_rlast;
// value method dmem_master_m_rready
output dmem_master_rready;
// action method server_fence_i_request_put
input EN_server_fence_i_request_put;
output RDY_server_fence_i_request_put;
// action method server_fence_i_response_get
input EN_server_fence_i_response_get;
output RDY_server_fence_i_response_get;
// action method server_fence_request_put
input [7 : 0] server_fence_request_put;
input EN_server_fence_request_put;
output RDY_server_fence_request_put;
// action method server_fence_response_get
input EN_server_fence_response_get;
output RDY_server_fence_response_get;
// action method sfence_vma
input EN_sfence_vma;
output RDY_sfence_vma;
// signals for module outputs
wire [63 : 0] dmem_master_araddr,
dmem_master_awaddr,
dmem_master_wdata,
dmem_st_amo_val,
dmem_word64,
imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
imem_pc,
imem_tval;
wire [31 : 0] imem_instr;
wire [7 : 0] dmem_master_arlen,
dmem_master_awlen,
dmem_master_wstrb,
imem_master_arlen,
imem_master_awlen,
imem_master_wstrb;
wire [3 : 0] dmem_exc_code,
dmem_master_arcache,
dmem_master_arid,
dmem_master_arqos,
dmem_master_arregion,
dmem_master_awcache,
dmem_master_awid,
dmem_master_awqos,
dmem_master_awregion,
imem_exc_code,
imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion;
wire [2 : 0] dmem_master_arprot,
dmem_master_arsize,
dmem_master_awprot,
dmem_master_awsize,
imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize;
wire [1 : 0] dmem_master_arburst,
dmem_master_awburst,
imem_master_arburst,
imem_master_awburst;
wire RDY_server_fence_i_request_put,
RDY_server_fence_i_response_get,
RDY_server_fence_request_put,
RDY_server_fence_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_sfence_vma,
dmem_exc,
dmem_master_arlock,
dmem_master_arvalid,
dmem_master_awlock,
dmem_master_awvalid,
dmem_master_bready,
dmem_master_rready,
dmem_master_wlast,
dmem_master_wvalid,
dmem_valid,
imem_exc,
imem_is_i32_not_i16,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
imem_valid;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule dcache
wire [63 : 0] dcache$mem_master_araddr,
dcache$mem_master_awaddr,
dcache$mem_master_rdata,
dcache$mem_master_wdata,
dcache$req_addr,
dcache$req_satp,
dcache$req_st_value,
dcache$st_amo_val,
dcache$word64;
wire [7 : 0] dcache$mem_master_arlen,
dcache$mem_master_awlen,
dcache$mem_master_wstrb;
wire [6 : 0] dcache$req_amo_funct7;
wire [3 : 0] dcache$exc_code,
dcache$mem_master_arcache,
dcache$mem_master_arid,
dcache$mem_master_arqos,
dcache$mem_master_arregion,
dcache$mem_master_awcache,
dcache$mem_master_awid,
dcache$mem_master_awqos,
dcache$mem_master_awregion,
dcache$mem_master_bid,
dcache$mem_master_rid,
dcache$set_verbosity_verbosity;
wire [2 : 0] dcache$mem_master_arprot,
dcache$mem_master_arsize,
dcache$mem_master_awprot,
dcache$mem_master_awsize,
dcache$req_f3;
wire [1 : 0] dcache$mem_master_arburst,
dcache$mem_master_awburst,
dcache$mem_master_bresp,
dcache$mem_master_rresp,
dcache$req_op,
dcache$req_priv;
wire dcache$EN_req,
dcache$EN_server_flush_request_put,
dcache$EN_server_flush_response_get,
dcache$EN_server_reset_request_put,
dcache$EN_server_reset_response_get,
dcache$EN_set_verbosity,
dcache$EN_tlb_flush,
dcache$RDY_server_flush_request_put,
dcache$RDY_server_flush_response_get,
dcache$RDY_server_reset_request_put,
dcache$RDY_server_reset_response_get,
dcache$exc,
dcache$mem_master_arlock,
dcache$mem_master_arready,
dcache$mem_master_arvalid,
dcache$mem_master_awlock,
dcache$mem_master_awready,
dcache$mem_master_awvalid,
dcache$mem_master_bready,
dcache$mem_master_bvalid,
dcache$mem_master_rlast,
dcache$mem_master_rready,
dcache$mem_master_rvalid,
dcache$mem_master_wlast,
dcache$mem_master_wready,
dcache$mem_master_wvalid,
dcache$req_mstatus_MXR,
dcache$req_sstatus_SUM,
dcache$valid;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule icache
wire [63 : 0] icache$addr,
icache$mem_master_araddr,
icache$mem_master_awaddr,
icache$mem_master_rdata,
icache$mem_master_wdata,
icache$req_addr,
icache$req_satp,
icache$req_st_value,
icache$word64;
wire [7 : 0] icache$mem_master_arlen,
icache$mem_master_awlen,
icache$mem_master_wstrb;
wire [6 : 0] icache$req_amo_funct7;
wire [3 : 0] icache$exc_code,
icache$mem_master_arcache,
icache$mem_master_arid,
icache$mem_master_arqos,
icache$mem_master_arregion,
icache$mem_master_awcache,
icache$mem_master_awid,
icache$mem_master_awqos,
icache$mem_master_awregion,
icache$mem_master_bid,
icache$mem_master_rid,
icache$set_verbosity_verbosity;
wire [2 : 0] icache$mem_master_arprot,
icache$mem_master_arsize,
icache$mem_master_awprot,
icache$mem_master_awsize,
icache$req_f3;
wire [1 : 0] icache$mem_master_arburst,
icache$mem_master_awburst,
icache$mem_master_bresp,
icache$mem_master_rresp,
icache$req_op,
icache$req_priv;
wire icache$EN_req,
icache$EN_server_flush_request_put,
icache$EN_server_flush_response_get,
icache$EN_server_reset_request_put,
icache$EN_server_reset_response_get,
icache$EN_set_verbosity,
icache$EN_tlb_flush,
icache$RDY_server_flush_request_put,
icache$RDY_server_flush_response_get,
icache$RDY_server_reset_request_put,
icache$RDY_server_reset_response_get,
icache$exc,
icache$mem_master_arlock,
icache$mem_master_arready,
icache$mem_master_arvalid,
icache$mem_master_awlock,
icache$mem_master_awready,
icache$mem_master_awvalid,
icache$mem_master_bready,
icache$mem_master_bvalid,
icache$mem_master_rlast,
icache$mem_master_rready,
icache$mem_master_rvalid,
icache$mem_master_wlast,
icache$mem_master_wready,
icache$mem_master_wvalid,
icache$req_mstatus_MXR,
icache$req_sstatus_SUM,
icache$valid;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_dmem_master_m_arready,
CAN_FIRE_dmem_master_m_awready,
CAN_FIRE_dmem_master_m_bvalid,
CAN_FIRE_dmem_master_m_rvalid,
CAN_FIRE_dmem_master_m_wready,
CAN_FIRE_dmem_req,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_imem_req,
CAN_FIRE_server_fence_i_request_put,
CAN_FIRE_server_fence_i_response_get,
CAN_FIRE_server_fence_request_put,
CAN_FIRE_server_fence_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_sfence_vma,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_dmem_master_m_arready,
WILL_FIRE_dmem_master_m_awready,
WILL_FIRE_dmem_master_m_bvalid,
WILL_FIRE_dmem_master_m_rvalid,
WILL_FIRE_dmem_master_m_wready,
WILL_FIRE_dmem_req,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_imem_req,
WILL_FIRE_server_fence_i_request_put,
WILL_FIRE_server_fence_i_response_get,
WILL_FIRE_server_fence_request_put,
WILL_FIRE_server_fence_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_sfence_vma;
// inputs to muxes for submodule ports
wire MUX_rg_state$write_1__SEL_2, MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1659;
reg [31 : 0] v__h1810;
reg [31 : 0] v__h1653;
reg [31 : 0] v__h1804;
// synopsys translate_on
// remaining internal signals
wire NOT_cfg_verbosity_read_ULE_1___d9;
// action method server_reset_request_put
assign RDY_server_reset_request_put = rg_state == 2'd2 ;
assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method imem_req
assign CAN_FIRE_imem_req = 1'd1 ;
assign WILL_FIRE_imem_req = EN_imem_req ;
// value method imem_valid
assign imem_valid = icache$valid ;
// value method imem_is_i32_not_i16
assign imem_is_i32_not_i16 = 1'd1 ;
// value method imem_pc
assign imem_pc = icache$addr ;
// value method imem_instr
assign imem_instr = icache$word64[31:0] ;
// value method imem_exc
assign imem_exc = icache$exc ;
// value method imem_exc_code
assign imem_exc_code = icache$exc_code ;
// value method imem_tval
assign imem_tval = icache$addr ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = icache$mem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = icache$mem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = icache$mem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = icache$mem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = icache$mem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = icache$mem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = icache$mem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = icache$mem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = icache$mem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = icache$mem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = icache$mem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = icache$mem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = icache$mem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = icache$mem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = icache$mem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = icache$mem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = icache$mem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = icache$mem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = icache$mem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = icache$mem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = icache$mem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = icache$mem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = icache$mem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = icache$mem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = icache$mem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = icache$mem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = icache$mem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = icache$mem_master_rready ;
// action method dmem_req
assign CAN_FIRE_dmem_req = 1'd1 ;
assign WILL_FIRE_dmem_req = EN_dmem_req ;
// value method dmem_valid
assign dmem_valid = dcache$valid ;
// value method dmem_word64
assign dmem_word64 = dcache$word64 ;
// value method dmem_st_amo_val
assign dmem_st_amo_val = dcache$st_amo_val ;
// value method dmem_exc
assign dmem_exc = dcache$exc ;
// value method dmem_exc_code
assign dmem_exc_code = dcache$exc_code ;
// value method dmem_master_m_awvalid
assign dmem_master_awvalid = dcache$mem_master_awvalid ;
// value method dmem_master_m_awid
assign dmem_master_awid = dcache$mem_master_awid ;
// value method dmem_master_m_awaddr
assign dmem_master_awaddr = dcache$mem_master_awaddr ;
// value method dmem_master_m_awlen
assign dmem_master_awlen = dcache$mem_master_awlen ;
// value method dmem_master_m_awsize
assign dmem_master_awsize = dcache$mem_master_awsize ;
// value method dmem_master_m_awburst
assign dmem_master_awburst = dcache$mem_master_awburst ;
// value method dmem_master_m_awlock
assign dmem_master_awlock = dcache$mem_master_awlock ;
// value method dmem_master_m_awcache
assign dmem_master_awcache = dcache$mem_master_awcache ;
// value method dmem_master_m_awprot
assign dmem_master_awprot = dcache$mem_master_awprot ;
// value method dmem_master_m_awqos
assign dmem_master_awqos = dcache$mem_master_awqos ;
// value method dmem_master_m_awregion
assign dmem_master_awregion = dcache$mem_master_awregion ;
// action method dmem_master_m_awready
assign CAN_FIRE_dmem_master_m_awready = 1'd1 ;
assign WILL_FIRE_dmem_master_m_awready = 1'd1 ;
// value method dmem_master_m_wvalid
assign dmem_master_wvalid = dcache$mem_master_wvalid ;
// value method dmem_master_m_wdata
assign dmem_master_wdata = dcache$mem_master_wdata ;
// value method dmem_master_m_wstrb
assign dmem_master_wstrb = dcache$mem_master_wstrb ;
// value method dmem_master_m_wlast
assign dmem_master_wlast = dcache$mem_master_wlast ;
// action method dmem_master_m_wready
assign CAN_FIRE_dmem_master_m_wready = 1'd1 ;
assign WILL_FIRE_dmem_master_m_wready = 1'd1 ;
// action method dmem_master_m_bvalid
assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ;
// value method dmem_master_m_bready
assign dmem_master_bready = dcache$mem_master_bready ;
// value method dmem_master_m_arvalid
assign dmem_master_arvalid = dcache$mem_master_arvalid ;
// value method dmem_master_m_arid
assign dmem_master_arid = dcache$mem_master_arid ;
// value method dmem_master_m_araddr
assign dmem_master_araddr = dcache$mem_master_araddr ;
// value method dmem_master_m_arlen
assign dmem_master_arlen = dcache$mem_master_arlen ;
// value method dmem_master_m_arsize
assign dmem_master_arsize = dcache$mem_master_arsize ;
// value method dmem_master_m_arburst
assign dmem_master_arburst = dcache$mem_master_arburst ;
// value method dmem_master_m_arlock
assign dmem_master_arlock = dcache$mem_master_arlock ;
// value method dmem_master_m_arcache
assign dmem_master_arcache = dcache$mem_master_arcache ;
// value method dmem_master_m_arprot
assign dmem_master_arprot = dcache$mem_master_arprot ;
// value method dmem_master_m_arqos
assign dmem_master_arqos = dcache$mem_master_arqos ;
// value method dmem_master_m_arregion
assign dmem_master_arregion = dcache$mem_master_arregion ;
// action method dmem_master_m_arready
assign CAN_FIRE_dmem_master_m_arready = 1'd1 ;
assign WILL_FIRE_dmem_master_m_arready = 1'd1 ;
// action method dmem_master_m_rvalid
assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ;
// value method dmem_master_m_rready
assign dmem_master_rready = dcache$mem_master_rready ;
// action method server_fence_i_request_put
assign RDY_server_fence_i_request_put =
dcache$RDY_server_flush_request_put &&
icache$RDY_server_flush_request_put ;
assign CAN_FIRE_server_fence_i_request_put =
dcache$RDY_server_flush_request_put &&
icache$RDY_server_flush_request_put ;
assign WILL_FIRE_server_fence_i_request_put =
EN_server_fence_i_request_put ;
// action method server_fence_i_response_get
assign RDY_server_fence_i_response_get =
dcache$RDY_server_flush_response_get &&
icache$RDY_server_flush_response_get ;
assign CAN_FIRE_server_fence_i_response_get =
dcache$RDY_server_flush_response_get &&
icache$RDY_server_flush_response_get ;
assign WILL_FIRE_server_fence_i_response_get =
EN_server_fence_i_response_get ;
// action method server_fence_request_put
assign RDY_server_fence_request_put = dcache$RDY_server_flush_request_put ;
assign CAN_FIRE_server_fence_request_put =
dcache$RDY_server_flush_request_put ;
assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ;
// action method server_fence_response_get
assign RDY_server_fence_response_get =
dcache$RDY_server_flush_response_get ;
assign CAN_FIRE_server_fence_response_get =
dcache$RDY_server_flush_response_get ;
assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ;
// action method sfence_vma
assign RDY_sfence_vma = 1'd1 ;
assign CAN_FIRE_sfence_vma = 1'd1 ;
assign WILL_FIRE_sfence_vma = EN_sfence_vma ;
// submodule dcache
mkMMU_Cache #(.dmem_not_imem(1'd1)) dcache(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(dcache$mem_master_arready),
.mem_master_awready(dcache$mem_master_awready),
.mem_master_bid(dcache$mem_master_bid),
.mem_master_bresp(dcache$mem_master_bresp),
.mem_master_bvalid(dcache$mem_master_bvalid),
.mem_master_rdata(dcache$mem_master_rdata),
.mem_master_rid(dcache$mem_master_rid),
.mem_master_rlast(dcache$mem_master_rlast),
.mem_master_rresp(dcache$mem_master_rresp),
.mem_master_rvalid(dcache$mem_master_rvalid),
.mem_master_wready(dcache$mem_master_wready),
.req_addr(dcache$req_addr),
.req_amo_funct7(dcache$req_amo_funct7),
.req_f3(dcache$req_f3),
.req_mstatus_MXR(dcache$req_mstatus_MXR),
.req_op(dcache$req_op),
.req_priv(dcache$req_priv),
.req_satp(dcache$req_satp),
.req_sstatus_SUM(dcache$req_sstatus_SUM),
.req_st_value(dcache$req_st_value),
.set_verbosity_verbosity(dcache$set_verbosity_verbosity),
.EN_set_verbosity(dcache$EN_set_verbosity),
.EN_server_reset_request_put(dcache$EN_server_reset_request_put),
.EN_server_reset_response_get(dcache$EN_server_reset_response_get),
.EN_req(dcache$EN_req),
.EN_server_flush_request_put(dcache$EN_server_flush_request_put),
.EN_server_flush_response_get(dcache$EN_server_flush_response_get),
.EN_tlb_flush(dcache$EN_tlb_flush),
.RDY_set_verbosity(),
.RDY_server_reset_request_put(dcache$RDY_server_reset_request_put),
.RDY_server_reset_response_get(dcache$RDY_server_reset_response_get),
.valid(dcache$valid),
.addr(),
.word64(dcache$word64),
.st_amo_val(dcache$st_amo_val),
.exc(dcache$exc),
.exc_code(dcache$exc_code),
.RDY_server_flush_request_put(dcache$RDY_server_flush_request_put),
.RDY_server_flush_response_get(dcache$RDY_server_flush_response_get),
.RDY_tlb_flush(),
.mem_master_awvalid(dcache$mem_master_awvalid),
.mem_master_awid(dcache$mem_master_awid),
.mem_master_awaddr(dcache$mem_master_awaddr),
.mem_master_awlen(dcache$mem_master_awlen),
.mem_master_awsize(dcache$mem_master_awsize),
.mem_master_awburst(dcache$mem_master_awburst),
.mem_master_awlock(dcache$mem_master_awlock),
.mem_master_awcache(dcache$mem_master_awcache),
.mem_master_awprot(dcache$mem_master_awprot),
.mem_master_awqos(dcache$mem_master_awqos),
.mem_master_awregion(dcache$mem_master_awregion),
.mem_master_wvalid(dcache$mem_master_wvalid),
.mem_master_wdata(dcache$mem_master_wdata),
.mem_master_wstrb(dcache$mem_master_wstrb),
.mem_master_wlast(dcache$mem_master_wlast),
.mem_master_bready(dcache$mem_master_bready),
.mem_master_arvalid(dcache$mem_master_arvalid),
.mem_master_arid(dcache$mem_master_arid),
.mem_master_araddr(dcache$mem_master_araddr),
.mem_master_arlen(dcache$mem_master_arlen),
.mem_master_arsize(dcache$mem_master_arsize),
.mem_master_arburst(dcache$mem_master_arburst),
.mem_master_arlock(dcache$mem_master_arlock),
.mem_master_arcache(dcache$mem_master_arcache),
.mem_master_arprot(dcache$mem_master_arprot),
.mem_master_arqos(dcache$mem_master_arqos),
.mem_master_arregion(dcache$mem_master_arregion),
.mem_master_rready(dcache$mem_master_rready));
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule icache
mkMMU_Cache #(.dmem_not_imem(1'd0)) icache(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(icache$mem_master_arready),
.mem_master_awready(icache$mem_master_awready),
.mem_master_bid(icache$mem_master_bid),
.mem_master_bresp(icache$mem_master_bresp),
.mem_master_bvalid(icache$mem_master_bvalid),
.mem_master_rdata(icache$mem_master_rdata),
.mem_master_rid(icache$mem_master_rid),
.mem_master_rlast(icache$mem_master_rlast),
.mem_master_rresp(icache$mem_master_rresp),
.mem_master_rvalid(icache$mem_master_rvalid),
.mem_master_wready(icache$mem_master_wready),
.req_addr(icache$req_addr),
.req_amo_funct7(icache$req_amo_funct7),
.req_f3(icache$req_f3),
.req_mstatus_MXR(icache$req_mstatus_MXR),
.req_op(icache$req_op),
.req_priv(icache$req_priv),
.req_satp(icache$req_satp),
.req_sstatus_SUM(icache$req_sstatus_SUM),
.req_st_value(icache$req_st_value),
.set_verbosity_verbosity(icache$set_verbosity_verbosity),
.EN_set_verbosity(icache$EN_set_verbosity),
.EN_server_reset_request_put(icache$EN_server_reset_request_put),
.EN_server_reset_response_get(icache$EN_server_reset_response_get),
.EN_req(icache$EN_req),
.EN_server_flush_request_put(icache$EN_server_flush_request_put),
.EN_server_flush_response_get(icache$EN_server_flush_response_get),
.EN_tlb_flush(icache$EN_tlb_flush),
.RDY_set_verbosity(),
.RDY_server_reset_request_put(icache$RDY_server_reset_request_put),
.RDY_server_reset_response_get(icache$RDY_server_reset_response_get),
.valid(icache$valid),
.addr(icache$addr),
.word64(icache$word64),
.st_amo_val(),
.exc(icache$exc),
.exc_code(icache$exc_code),
.RDY_server_flush_request_put(icache$RDY_server_flush_request_put),
.RDY_server_flush_response_get(icache$RDY_server_flush_response_get),
.RDY_tlb_flush(),
.mem_master_awvalid(icache$mem_master_awvalid),
.mem_master_awid(icache$mem_master_awid),
.mem_master_awaddr(icache$mem_master_awaddr),
.mem_master_awlen(icache$mem_master_awlen),
.mem_master_awsize(icache$mem_master_awsize),
.mem_master_awburst(icache$mem_master_awburst),
.mem_master_awlock(icache$mem_master_awlock),
.mem_master_awcache(icache$mem_master_awcache),
.mem_master_awprot(icache$mem_master_awprot),
.mem_master_awqos(icache$mem_master_awqos),
.mem_master_awregion(icache$mem_master_awregion),
.mem_master_wvalid(icache$mem_master_wvalid),
.mem_master_wdata(icache$mem_master_wdata),
.mem_master_wstrb(icache$mem_master_wstrb),
.mem_master_wlast(icache$mem_master_wlast),
.mem_master_bready(icache$mem_master_bready),
.mem_master_arvalid(icache$mem_master_arvalid),
.mem_master_arid(icache$mem_master_arid),
.mem_master_araddr(icache$mem_master_araddr),
.mem_master_arlen(icache$mem_master_arlen),
.mem_master_arsize(icache$mem_master_arsize),
.mem_master_arburst(icache$mem_master_arburst),
.mem_master_arlock(icache$mem_master_arlock),
.mem_master_arcache(icache$mem_master_arcache),
.mem_master_arprot(icache$mem_master_arprot),
.mem_master_arqos(icache$mem_master_arqos),
.mem_master_arregion(icache$mem_master_arregion),
.mem_master_rready(icache$mem_master_rready));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset =
dcache$RDY_server_reset_request_put &&
icache$RDY_server_reset_request_put &&
rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset && !EN_server_fence_request_put &&
!EN_server_fence_i_request_put ;
assign MUX_rg_state$write_1__SEL_3 =
dcache$RDY_server_reset_response_get &&
icache$RDY_server_reset_response_get &&
f_reset_rsps$FULL_N &&
rg_state == 2'd1 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete)
begin
case (1'b1) // synopsys parallel_case
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1;
WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset ||
WILL_FIRE_RL_rl_reset_complete ;
// submodule dcache
assign dcache$mem_master_arready = dmem_master_arready ;
assign dcache$mem_master_awready = dmem_master_awready ;
assign dcache$mem_master_bid = dmem_master_bid ;
assign dcache$mem_master_bresp = dmem_master_bresp ;
assign dcache$mem_master_bvalid = dmem_master_bvalid ;
assign dcache$mem_master_rdata = dmem_master_rdata ;
assign dcache$mem_master_rid = dmem_master_rid ;
assign dcache$mem_master_rlast = dmem_master_rlast ;
assign dcache$mem_master_rresp = dmem_master_rresp ;
assign dcache$mem_master_rvalid = dmem_master_rvalid ;
assign dcache$mem_master_wready = dmem_master_wready ;
assign dcache$req_addr = dmem_req_addr ;
assign dcache$req_amo_funct7 = dmem_req_amo_funct7 ;
assign dcache$req_f3 = dmem_req_f3 ;
assign dcache$req_mstatus_MXR = dmem_req_mstatus_MXR ;
assign dcache$req_op = dmem_req_op ;
assign dcache$req_priv = dmem_req_priv ;
assign dcache$req_satp = dmem_req_satp ;
assign dcache$req_sstatus_SUM = dmem_req_sstatus_SUM ;
assign dcache$req_st_value = dmem_req_store_value ;
assign dcache$set_verbosity_verbosity = 4'h0 ;
assign dcache$EN_set_verbosity = 1'b0 ;
assign dcache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ;
assign dcache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ;
assign dcache$EN_req = EN_dmem_req ;
assign dcache$EN_server_flush_request_put =
EN_server_fence_i_request_put || EN_server_fence_request_put ;
assign dcache$EN_server_flush_response_get =
EN_server_fence_i_response_get || EN_server_fence_response_get ;
assign dcache$EN_tlb_flush = EN_sfence_vma ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule icache
assign icache$mem_master_arready = imem_master_arready ;
assign icache$mem_master_awready = imem_master_awready ;
assign icache$mem_master_bid = imem_master_bid ;
assign icache$mem_master_bresp = imem_master_bresp ;
assign icache$mem_master_bvalid = imem_master_bvalid ;
assign icache$mem_master_rdata = imem_master_rdata ;
assign icache$mem_master_rid = imem_master_rid ;
assign icache$mem_master_rlast = imem_master_rlast ;
assign icache$mem_master_rresp = imem_master_rresp ;
assign icache$mem_master_rvalid = imem_master_rvalid ;
assign icache$mem_master_wready = imem_master_wready ;
assign icache$req_addr = imem_req_addr ;
assign icache$req_amo_funct7 = 7'b0101010 /* unspecified value */ ;
assign icache$req_f3 = imem_req_f3 ;
assign icache$req_mstatus_MXR = imem_req_mstatus_MXR ;
assign icache$req_op = 2'd0 ;
assign icache$req_priv = imem_req_priv ;
assign icache$req_satp = imem_req_satp ;
assign icache$req_sstatus_SUM = imem_req_sstatus_SUM ;
assign icache$req_st_value = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign icache$set_verbosity_verbosity = 4'h0 ;
assign icache$EN_set_verbosity = 1'b0 ;
assign icache$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_2 ;
assign icache$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_3 ;
assign icache$EN_req = EN_imem_req ;
assign icache$EN_server_flush_request_put = EN_server_fence_i_request_put ;
assign icache$EN_server_flush_response_get =
EN_server_fence_i_response_get ;
assign icache$EN_tlb_flush = EN_sfence_vma ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign NOT_cfg_verbosity_read_ULE_1___d9 = cfg_verbosity > 4'd1 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9)
begin
v__h1659 = $stime;
#0;
end
v__h1653 = v__h1659 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read_ULE_1___d9)
$display("%0d: Near_Mem.rl_reset", v__h1653);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9)
begin
v__h1810 = $stime;
#0;
end
v__h1804 = v__h1810 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && NOT_cfg_verbosity_read_ULE_1___d9)
$display("%0d: Near_Mem.rl_reset_complete", v__h1804);
end
// synopsys translate_on
endmodule // mkNear_Mem
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V |
// Code ok to distribute
module autoasciienum_auto();
reg [2:0] /* auto enum sm_psm */ sm_psm;
reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
localparam [2:0] // auto enum sm_psm
PSM_IDL = 0,
PSM_RST = 6,
PSM_ZOT = 7;
localparam [2:0] // auto enum sm_ps2
PS2_IDL = 0,
PS2_FOO = 1;
/*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_psm__ascii; // Decode of sm_psm
always @(sm_psm) begin
case ({sm_psm})
PSM_IDL: _sm_psm__ascii = "psmidl";
PSM_RST: _sm_psm__ascii = "psmrst";
PSM_ZOT: _sm_psm__ascii = "psmzot";
default: _sm_psm__ascii = "%Error";
endcase
end
// End of automatics
/*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_ps2__ascii; // Decode of sm_ps2
always @(sm_ps2) begin
case ({sm_ps2})
PS2_IDL: _sm_ps2__ascii = "ps2idl";
PS2_FOO: _sm_ps2__ascii = "ps2foo";
default: _sm_ps2__ascii = "%Error";
endcase
end
// End of automatics
endmodule : autoasciienum_auto
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=4 clk1_duty_cycle=50 clk1_multiply_by=5 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Stratix IV" inclk0_input_frequency=10000 intended_device_family="Stratix IV" lpm_hint="CBX_MODULE_PREFIX=reconfig_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_clk6="PORT_UNUSED" port_clk7="PORT_UNUSED" port_clk8="PORT_UNUSED" port_clk9="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" using_fbmimicbidir_port="OFF" width_clock=10 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 12.1SP1 cbx_altclkbuf 2013:01:31:18:04:58:SJ cbx_altiobuf_bidir 2013:01:31:18:04:58:SJ cbx_altiobuf_in 2013:01:31:18:04:58:SJ cbx_altiobuf_out 2013:01:31:18:04:58:SJ cbx_altpll 2013:01:31:18:04:59:SJ cbx_cycloneii 2013:01:31:18:04:59:SJ cbx_lpm_add_sub 2013:01:31:18:04:59:SJ cbx_lpm_compare 2013:01:31:18:04:59:SJ cbx_lpm_counter 2013:01:31:18:04:59:SJ cbx_lpm_decode 2013:01:31:18:04:59:SJ cbx_lpm_mux 2013:01:31:18:04:59:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:04:59:SJ cbx_stratixii 2013:01:31:18:04:59:SJ cbx_stratixiii 2013:01:31:18:05:00:SJ cbx_stratixv 2013:01:31:18:05:00:SJ cbx_util_mgl 2013:01:31:18:04:59:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE4_Reference_Router_reconfig_pll_reconfig_pll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module reconfig_pll_altpll
(
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
output [9:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
stratixiv_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({4{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 2,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 4,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 5,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 10000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "stratixiv_pll";
assign
clk = wire_pll1_clk,
locked = wire_pll1_locked;
endmodule //reconfig_pll_altpll
//VALID FILE
|
module top(
input LIOB33_SING_X0Y0_IOB_X0Y0_IPAD,
input LIOB33_X0Y1_IOB_X0Y1_IPAD,
output LIOB33_X0Y1_IOB_X0Y2_OPAD
);
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_AO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_AO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_A_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_BO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_BO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_B_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_CO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_CO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_C_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_DO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_DO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X0Y1_D_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_AO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_AO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_A_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_BO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_BO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_B_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_CO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_CO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_C_XOR;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D1;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D2;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D3;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D4;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_DO5;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_DO6;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D_CY;
wire [0:0] CLBLL_L_X2Y1_SLICE_X1Y1_D_XOR;
wire [0:0] LIOB33_SING_X0Y0_IOB_X0Y0_I;
wire [0:0] LIOB33_X0Y1_IOB_X0Y1_I;
wire [0:0] LIOB33_X0Y1_IOB_X0Y2_O;
wire [0:0] LIOI3_SING_X0Y0_ILOGIC_X0Y0_D;
wire [0:0] LIOI3_SING_X0Y0_ILOGIC_X0Y0_O;
wire [0:0] LIOI3_X0Y1_ILOGIC_X0Y1_D;
wire [0:0] LIOI3_X0Y1_ILOGIC_X0Y1_O;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_D1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_OQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_T1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y2_TQ;
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X0Y1_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X0Y1_DO5),
.O6(CLBLL_L_X2Y1_SLICE_X0Y1_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X0Y1_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X0Y1_CO5),
.O6(CLBLL_L_X2Y1_SLICE_X0Y1_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X0Y1_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X0Y1_BO5),
.O6(CLBLL_L_X2Y1_SLICE_X0Y1_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'hf0f00000f0f00000)
) CLBLL_L_X2Y1_SLICE_X0Y1_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(LIOB33_X0Y1_IOB_X0Y1_I),
.I3(1'b1),
.I4(LIOB33_SING_X0Y0_IOB_X0Y0_I),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X0Y1_AO5),
.O6(CLBLL_L_X2Y1_SLICE_X0Y1_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X1Y1_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X1Y1_DO5),
.O6(CLBLL_L_X2Y1_SLICE_X1Y1_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X1Y1_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X1Y1_CO5),
.O6(CLBLL_L_X2Y1_SLICE_X1Y1_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X1Y1_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X1Y1_BO5),
.O6(CLBLL_L_X2Y1_SLICE_X1Y1_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y1_SLICE_X1Y1_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y1_SLICE_X1Y1_AO5),
.O6(CLBLL_L_X2Y1_SLICE_X1Y1_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y1_IOB_X0Y1_IBUF (
.I(LIOB33_X0Y1_IOB_X0Y1_IPAD),
.O(LIOB33_X0Y1_IOB_X0Y1_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y1_IOB_X0Y2_OBUF (
.I(CLBLL_L_X2Y1_SLICE_X0Y1_AO6),
.O(LIOB33_X0Y1_IOB_X0Y2_OPAD)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_SING_X0Y0_IOB_X0Y0_IBUF (
.I(LIOB33_SING_X0Y0_IOB_X0Y0_IPAD),
.O(LIOB33_SING_X0Y0_IOB_X0Y0_I)
);
assign CLBLL_L_X2Y1_SLICE_X0Y1_COUT = CLBLL_L_X2Y1_SLICE_X0Y1_D_CY;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A = CLBLL_L_X2Y1_SLICE_X0Y1_AO6;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B = CLBLL_L_X2Y1_SLICE_X0Y1_BO6;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C = CLBLL_L_X2Y1_SLICE_X0Y1_CO6;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D = CLBLL_L_X2Y1_SLICE_X0Y1_DO6;
assign CLBLL_L_X2Y1_SLICE_X1Y1_COUT = CLBLL_L_X2Y1_SLICE_X1Y1_D_CY;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A = CLBLL_L_X2Y1_SLICE_X1Y1_AO6;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B = CLBLL_L_X2Y1_SLICE_X1Y1_BO6;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C = CLBLL_L_X2Y1_SLICE_X1Y1_CO6;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D = CLBLL_L_X2Y1_SLICE_X1Y1_DO6;
assign LIOI3_X0Y1_ILOGIC_X0Y1_O = LIOB33_X0Y1_IOB_X0Y1_I;
assign LIOI3_X0Y1_OLOGIC_X0Y2_OQ = CLBLL_L_X2Y1_SLICE_X0Y1_AO6;
assign LIOI3_X0Y1_OLOGIC_X0Y2_TQ = 1'b1;
assign LIOI3_SING_X0Y0_ILOGIC_X0Y0_O = LIOB33_SING_X0Y0_IOB_X0Y0_I;
assign LIOB33_X0Y1_IOB_X0Y2_O = CLBLL_L_X2Y1_SLICE_X0Y1_AO6;
assign LIOI3_X0Y1_OLOGIC_X0Y2_D1 = CLBLL_L_X2Y1_SLICE_X0Y1_AO6;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_A6 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_B6 = 1'b1;
assign LIOI3_X0Y1_OLOGIC_X0Y2_T1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_C6 = 1'b1;
assign LIOI3_SING_X0Y0_ILOGIC_X0Y0_D = LIOB33_SING_X0Y0_IOB_X0Y0_I;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X1Y1_D6 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A3 = LIOB33_X0Y1_IOB_X0Y1_I;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A5 = LIOB33_SING_X0Y0_IOB_X0Y0_I;
assign CLBLL_L_X2Y1_SLICE_X0Y1_A6 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_B6 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_C6 = 1'b1;
assign LIOI3_X0Y1_ILOGIC_X0Y1_D = LIOB33_X0Y1_IOB_X0Y1_I;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D1 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D2 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D3 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D4 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D5 = 1'b1;
assign CLBLL_L_X2Y1_SLICE_X0Y1_D6 = 1'b1;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: sys_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.1 Build 150 06/03/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sys_pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => negb b2
| false => true
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match b1 with
| true => andb b2 b3
| false => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros. rewrite H. rewrite H0. reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros. simpl. symmetry. rewrite H. symmetry. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [p | n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros. destruct n as [|n']. simpl. reflexivity.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros. rewrite H . rewrite H. reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros. rewrite H. rewrite H. destruct b. simpl. reflexivity.
reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c. destruct b. simpl. intros. rewrite H. reflexivity.
simpl. intros. rewrite H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin : Type :=
| zero : bin
| twiceN : bin -> bin
| twiceNPlus1 : bin -> bin.
Fixpoint incr (b : bin) :=
match b with
| zero => twiceNPlus1 zero
| twiceN b' => twiceNPlus1 b'
| twiceNPlus1 b' => twiceN (incr b')
end.
Eval compute in incr (twiceNPlus1 (twiceNPlus1 zero)).
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| zero => O
| twiceN b' => 2 * (bin_to_nat b')
| twiceNPlus1 b' => 1 + (2 * (bin_to_nat b'))
end.
Example test_bin_incr1 : incr (twiceNPlus1 (twiceNPlus1 zero)) = twiceN (twiceN (twiceNPlus1 zero)).
Proof. reflexivity. Qed.
Example test_bin_incr2 : incr (zero) = ((twiceNPlus1 zero)).
Proof. reflexivity. Qed.
Example test_bin_incr3 : incr (twiceNPlus1 zero) = (twiceN (twiceNPlus1 zero)).
Proof. reflexivity. Qed.
Example test_bin_incr4 : bin_to_nat ( incr (twiceNPlus1 (twiceNPlus1 zero))) = 4.
Proof. reflexivity. Qed.
Example test_bin_incr5 : bin_to_nat ( incr (twiceN (twiceNPlus1 (twiceNPlus1 zero)))) = 7.
Proof. reflexivity. Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FAHCIN_PP_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_PP_BLACKBOX_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: four_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module four_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/four_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/four_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/four_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module top(
input clk,
input jc1,
input jc3,
input [7:0] sw,
output jc2,
output jc4,
output [7:0] led
);
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_AMUX;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_AO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_AO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_A_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_BO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_BO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_B_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_CLK;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_CO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_CO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_C_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D5Q;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_DMUX;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_DO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_DO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_DX;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X0Y16_D_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_AO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_AO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_A_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_BO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_BO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_B_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_CO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_CO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_C_XOR;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D1;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D2;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D3;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D4;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_DO5;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_DO6;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D_CY;
wire [0:0] CLBLL_L_X2Y16_SLICE_X1Y16_D_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_AO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_AO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_A_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_BO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_BO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_B_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_CO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_CO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_C_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_DO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_DO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X0Y23_D_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_AMUX;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_AO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_AO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_A_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_BO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_BO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_B_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_CLK;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_CO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_CO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_C_XOR;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D1;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D2;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D3;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D4;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D5Q;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_DMUX;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_DO5;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_DO6;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_DX;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D_CY;
wire [0:0] CLBLL_L_X2Y23_SLICE_X1Y23_D_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_AO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_AO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_A_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_BO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_BO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_B_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_CO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_CO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_C_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_DO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_DO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X0Y39_D_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_AMUX;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_AO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_AO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_A_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_BO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_BO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_B_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_CLK;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_CO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_CO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_C_XOR;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D1;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D2;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D3;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D4;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D5Q;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_DMUX;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_DO5;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_DO6;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_DX;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D_CY;
wire [0:0] CLBLL_L_X2Y39_SLICE_X1Y39_D_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_AMUX;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_AO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_AO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_A_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_BMUX;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_BO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_BO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_B_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_CO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_CO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_C_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_DO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_DO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X0Y5_D_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_AO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_AO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_A_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_BO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_BO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_B_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_CO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_CO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_C_XOR;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D1;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D2;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D3;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D4;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_DO5;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_DO6;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D_CY;
wire [0:0] CLBLL_L_X2Y5_SLICE_X1Y5_D_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_AMUX;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_AO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_AO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_A_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_BO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_BO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_B_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_CLK;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_CO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_CO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_C_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D5Q;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_DMUX;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_DO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_DO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_DX;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X0Y7_D_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_AO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_AO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_A_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_BO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_BO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_B_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_CO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_CO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_C_XOR;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D1;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D2;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D3;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D4;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_DO5;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_DO6;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D_CY;
wire [0:0] CLBLL_L_X2Y7_SLICE_X1Y7_D_XOR;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_S1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_S1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE1;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S0;
wire [0:0] CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S1;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBIN;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBOUT;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBOUTB;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBSTOPPED;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKIN1;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKIN2;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKINSEL;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKINSTOPPED;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT0;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT0B;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT1;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT1B;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT2;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT2B;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT3;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT3B;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR0;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR1;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR2;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR3;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR4;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR5;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR6;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DCLK;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DEN;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI0;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI1;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI10;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI11;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI12;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI13;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI14;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI15;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI2;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI3;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI4;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI5;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI6;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI7;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI8;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI9;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO0;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO1;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO10;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO11;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO12;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO13;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO14;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO15;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO2;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO3;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO4;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO5;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO6;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO7;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO8;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO9;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DRDY;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DWE;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_LOCKED;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSCLK;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSDONE;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSEN;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSINCDEC;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PWRDWN;
wire [0:0] CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_RST;
wire [0:0] LIOB33_SING_X0Y0_IOB_X0Y0_O;
wire [0:0] LIOB33_X0Y11_IOB_X0Y11_I;
wire [0:0] LIOB33_X0Y11_IOB_X0Y12_I;
wire [0:0] LIOB33_X0Y17_IOB_X0Y18_O;
wire [0:0] LIOB33_X0Y19_IOB_X0Y19_O;
wire [0:0] LIOB33_X0Y19_IOB_X0Y20_O;
wire [0:0] LIOB33_X0Y1_IOB_X0Y1_O;
wire [0:0] LIOB33_X0Y23_IOB_X0Y24_I;
wire [0:0] LIOB33_X0Y25_IOB_X0Y25_I;
wire [0:0] LIOB33_X0Y25_IOB_X0Y26_O;
wire [0:0] LIOB33_X0Y27_IOB_X0Y28_O;
wire [0:0] LIOB33_X0Y3_IOB_X0Y3_O;
wire [0:0] LIOB33_X0Y3_IOB_X0Y4_O;
wire [0:0] LIOB33_X0Y43_IOB_X0Y43_O;
wire [0:0] LIOB33_X0Y5_IOB_X0Y5_I;
wire [0:0] LIOB33_X0Y5_IOB_X0Y6_I;
wire [0:0] LIOB33_X0Y7_IOB_X0Y7_I;
wire [0:0] LIOB33_X0Y7_IOB_X0Y8_I;
wire [0:0] LIOB33_X0Y9_IOB_X0Y10_I;
wire [0:0] LIOB33_X0Y9_IOB_X0Y9_I;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_D1;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_OQ;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_T1;
wire [0:0] LIOI3_SING_X0Y0_OLOGIC_X0Y0_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1;
wire [0:0] LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_D;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_O;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_D;
wire [0:0] LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_O;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y11_D;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y11_O;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y12_D;
wire [0:0] LIOI3_X0Y11_ILOGIC_X0Y12_O;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_D1;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_OQ;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_T1;
wire [0:0] LIOI3_X0Y17_OLOGIC_X0Y18_TQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_D1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_OQ;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_T1;
wire [0:0] LIOI3_X0Y1_OLOGIC_X0Y1_TQ;
wire [0:0] LIOI3_X0Y23_ILOGIC_X0Y24_D;
wire [0:0] LIOI3_X0Y23_ILOGIC_X0Y24_O;
wire [0:0] LIOI3_X0Y25_ILOGIC_X0Y25_D;
wire [0:0] LIOI3_X0Y25_ILOGIC_X0Y25_O;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_D1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_OQ;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_T1;
wire [0:0] LIOI3_X0Y25_OLOGIC_X0Y26_TQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_D1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_OQ;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_T1;
wire [0:0] LIOI3_X0Y27_OLOGIC_X0Y28_TQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_D1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_OQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_T1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y3_TQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_D1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_OQ;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_T1;
wire [0:0] LIOI3_X0Y3_OLOGIC_X0Y4_TQ;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y5_D;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y5_O;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y6_D;
wire [0:0] LIOI3_X0Y5_ILOGIC_X0Y6_O;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y10_D;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y10_O;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y9_D;
wire [0:0] LIOI3_X0Y9_ILOGIC_X0Y9_O;
wire [0:0] RIOB33_X43Y25_IOB_X1Y26_I;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_D;
wire [0:0] RIOI3_X43Y25_ILOGIC_X1Y26_O;
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y5_SLICE_X0Y5_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X0Y5_DO5),
.O6(CLBLL_L_X2Y5_SLICE_X0Y5_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y5_SLICE_X0Y5_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X0Y5_CO5),
.O6(CLBLL_L_X2Y5_SLICE_X0Y5_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h00000f0f00330033)
) CLBLL_L_X2Y5_SLICE_X0Y5_BLUT (
.I0(1'b1),
.I1(LIOB33_X0Y11_IOB_X0Y11_I),
.I2(LIOB33_X0Y9_IOB_X0Y9_I),
.I3(LIOB33_X0Y11_IOB_X0Y12_I),
.I4(LIOB33_X0Y9_IOB_X0Y10_I),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X0Y5_BO5),
.O6(CLBLL_L_X2Y5_SLICE_X0Y5_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'hfffffffdffffffff)
) CLBLL_L_X2Y5_SLICE_X0Y5_ALUT (
.I0(CLBLL_L_X2Y5_SLICE_X0Y5_BO6),
.I1(LIOB33_X0Y5_IOB_X0Y6_I),
.I2(LIOB33_X0Y5_IOB_X0Y5_I),
.I3(LIOB33_X0Y7_IOB_X0Y8_I),
.I4(LIOB33_X0Y7_IOB_X0Y7_I),
.I5(CLBLL_L_X2Y5_SLICE_X0Y5_BO5),
.O5(CLBLL_L_X2Y5_SLICE_X0Y5_AO5),
.O6(CLBLL_L_X2Y5_SLICE_X0Y5_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y5_SLICE_X1Y5_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X1Y5_DO5),
.O6(CLBLL_L_X2Y5_SLICE_X1Y5_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y5_SLICE_X1Y5_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X1Y5_CO5),
.O6(CLBLL_L_X2Y5_SLICE_X1Y5_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y5_SLICE_X1Y5_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X1Y5_BO5),
.O6(CLBLL_L_X2Y5_SLICE_X1Y5_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y5_SLICE_X1Y5_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y5_SLICE_X1Y5_AO5),
.O6(CLBLL_L_X2Y5_SLICE_X1Y5_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D5FF" *)
FDRE #(
.INIT(1),
.IS_C_INVERTED(0)
) CLBLL_L_X2Y7_SLICE_X0Y7_D5_FDRE (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.CE(1'b1),
.D(CLBLL_L_X2Y7_SLICE_X0Y7_AO5),
.Q(CLBLL_L_X2Y7_SLICE_X0Y7_D5Q),
.R(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X0Y7_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X0Y7_DO5),
.O6(CLBLL_L_X2Y7_SLICE_X0Y7_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X0Y7_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X0Y7_CO5),
.O6(CLBLL_L_X2Y7_SLICE_X0Y7_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X0Y7_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X0Y7_BO5),
.O6(CLBLL_L_X2Y7_SLICE_X0Y7_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h000000000f0f0f0f)
) CLBLL_L_X2Y7_SLICE_X0Y7_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(CLBLL_L_X2Y7_SLICE_X0Y7_D5Q),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X0Y7_AO5),
.O6(CLBLL_L_X2Y7_SLICE_X0Y7_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X1Y7_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X1Y7_DO5),
.O6(CLBLL_L_X2Y7_SLICE_X1Y7_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X1Y7_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X1Y7_CO5),
.O6(CLBLL_L_X2Y7_SLICE_X1Y7_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X1Y7_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X1Y7_BO5),
.O6(CLBLL_L_X2Y7_SLICE_X1Y7_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y7_SLICE_X1Y7_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y7_SLICE_X1Y7_AO5),
.O6(CLBLL_L_X2Y7_SLICE_X1Y7_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D5FF" *)
FDRE #(
.INIT(1),
.IS_C_INVERTED(0)
) CLBLL_L_X2Y16_SLICE_X0Y16_D5_FDRE (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_O),
.CE(1'b1),
.D(CLBLL_L_X2Y16_SLICE_X0Y16_AO5),
.Q(CLBLL_L_X2Y16_SLICE_X0Y16_D5Q),
.R(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X0Y16_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X0Y16_DO5),
.O6(CLBLL_L_X2Y16_SLICE_X0Y16_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X0Y16_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X0Y16_CO5),
.O6(CLBLL_L_X2Y16_SLICE_X0Y16_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X0Y16_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X0Y16_BO5),
.O6(CLBLL_L_X2Y16_SLICE_X0Y16_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h000000000f0f0f0f)
) CLBLL_L_X2Y16_SLICE_X0Y16_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(CLBLL_L_X2Y16_SLICE_X0Y16_D5Q),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X0Y16_AO5),
.O6(CLBLL_L_X2Y16_SLICE_X0Y16_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X1Y16_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X1Y16_DO5),
.O6(CLBLL_L_X2Y16_SLICE_X1Y16_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X1Y16_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X1Y16_CO5),
.O6(CLBLL_L_X2Y16_SLICE_X1Y16_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X1Y16_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X1Y16_BO5),
.O6(CLBLL_L_X2Y16_SLICE_X1Y16_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y16_SLICE_X1Y16_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y16_SLICE_X1Y16_AO5),
.O6(CLBLL_L_X2Y16_SLICE_X1Y16_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X0Y23_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X0Y23_DO5),
.O6(CLBLL_L_X2Y23_SLICE_X0Y23_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X0Y23_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X0Y23_CO5),
.O6(CLBLL_L_X2Y23_SLICE_X0Y23_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X0Y23_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X0Y23_BO5),
.O6(CLBLL_L_X2Y23_SLICE_X0Y23_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X0Y23_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X0Y23_AO5),
.O6(CLBLL_L_X2Y23_SLICE_X0Y23_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D5FF" *)
FDRE #(
.INIT(1),
.IS_C_INVERTED(0)
) CLBLL_L_X2Y23_SLICE_X1Y23_D5_FDRE (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_O),
.CE(1'b1),
.D(CLBLL_L_X2Y23_SLICE_X1Y23_AO5),
.Q(CLBLL_L_X2Y23_SLICE_X1Y23_D5Q),
.R(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X1Y23_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X1Y23_DO5),
.O6(CLBLL_L_X2Y23_SLICE_X1Y23_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X1Y23_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X1Y23_CO5),
.O6(CLBLL_L_X2Y23_SLICE_X1Y23_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y23_SLICE_X1Y23_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X1Y23_BO5),
.O6(CLBLL_L_X2Y23_SLICE_X1Y23_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h000000000f0f0f0f)
) CLBLL_L_X2Y23_SLICE_X1Y23_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(CLBLL_L_X2Y23_SLICE_X1Y23_D5Q),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y23_SLICE_X1Y23_AO5),
.O6(CLBLL_L_X2Y23_SLICE_X1Y23_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X0Y39_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X0Y39_DO5),
.O6(CLBLL_L_X2Y39_SLICE_X0Y39_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X0Y39_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X0Y39_CO5),
.O6(CLBLL_L_X2Y39_SLICE_X0Y39_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X0Y39_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X0Y39_BO5),
.O6(CLBLL_L_X2Y39_SLICE_X0Y39_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X0Y39_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X0Y39_AO5),
.O6(CLBLL_L_X2Y39_SLICE_X0Y39_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "D5FF" *)
FDRE #(
.INIT(1),
.IS_C_INVERTED(0)
) CLBLL_L_X2Y39_SLICE_X1Y39_D5_FDRE (
.C(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.CE(1'b1),
.D(CLBLL_L_X2Y39_SLICE_X1Y39_AO5),
.Q(CLBLL_L_X2Y39_SLICE_X1Y39_D5Q),
.R(1'b0)
);
(* KEEP, DONT_TOUCH, BEL = "D6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X1Y39_DLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X1Y39_DO5),
.O6(CLBLL_L_X2Y39_SLICE_X1Y39_DO6)
);
(* KEEP, DONT_TOUCH, BEL = "C6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X1Y39_CLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X1Y39_CO5),
.O6(CLBLL_L_X2Y39_SLICE_X1Y39_CO6)
);
(* KEEP, DONT_TOUCH, BEL = "B6LUT" *)
LUT6_2 #(
.INIT(64'h0000000000000000)
) CLBLL_L_X2Y39_SLICE_X1Y39_BLUT (
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X1Y39_BO5),
.O6(CLBLL_L_X2Y39_SLICE_X1Y39_BO6)
);
(* KEEP, DONT_TOUCH, BEL = "A6LUT" *)
LUT6_2 #(
.INIT(64'h000000000f0f0f0f)
) CLBLL_L_X2Y39_SLICE_X1Y39_ALUT (
.I0(1'b1),
.I1(1'b1),
.I2(CLBLL_L_X2Y39_SLICE_X1Y39_D5Q),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(CLBLL_L_X2Y39_SLICE_X1Y39_AO5),
.O6(CLBLL_L_X2Y39_SLICE_X1Y39_AO6)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT0),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT1),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT2),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "BUFGCTRL" *)
BUFGCTRL #(
.INIT_OUT(0),
.IS_CE0_INVERTED(0),
.IS_CE1_INVERTED(1),
.IS_IGNORE0_INVERTED(1),
.IS_IGNORE1_INVERTED(0),
.IS_S0_INVERTED(0),
.IS_S1_INVERTED(1),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE")
) CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_BUFGCTRL (
.CE0(1'b1),
.CE1(1'b1),
.I0(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT3),
.I1(1'b1),
.IGNORE0(1'b1),
.IGNORE1(1'b1),
.O(CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_O),
.S0(1'b1),
.S1(1'b1)
);
(* KEEP, DONT_TOUCH, BEL = "MMCME2_ADV" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.500),
.CLKFBOUT_PHASE(0.000),
.CLKIN1_PERIOD(11.667),
.CLKIN2_PERIOD(11.667),
.CLKOUT0_DIVIDE_F(12.500),
.CLKOUT0_DUTY_CYCLE(0.500),
.CLKOUT0_PHASE(43.200),
.CLKOUT1_DIVIDE(32),
.CLKOUT1_DUTY_CYCLE(0.5312),
.CLKOUT1_PHASE(90.000),
.CLKOUT2_DIVIDE(48),
.CLKOUT2_DUTY_CYCLE(0.5000),
.CLKOUT2_PHASE(135.000),
.CLKOUT3_DIVIDE(64),
.CLKOUT3_DUTY_CYCLE(0.5000),
.CLKOUT3_PHASE(45.000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500),
.CLKOUT4_PHASE(0.000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500),
.CLKOUT5_PHASE(0.000),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500),
.CLKOUT6_PHASE(0.000),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b1),
.IS_PSEN_INVERTED(1'b1),
.IS_PSINCDEC_INVERTED(1'b1),
.IS_PWRDWN_INVERTED(1'b1),
.IS_RST_INVERTED(1'b0),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE")
) CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_MMCME2_ADV (
.CLKFBIN(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBOUT),
.CLKFBOUT(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBOUT),
.CLKFBOUTB(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBOUTB),
.CLKFBSTOPPED(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBSTOPPED),
.CLKIN1(RIOB33_X43Y25_IOB_X1Y26_I),
.CLKIN2(RIOB33_X43Y25_IOB_X1Y26_I),
.CLKINSEL(1'b1),
.CLKINSTOPPED(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKINSTOPPED),
.CLKOUT0(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT0),
.CLKOUT0B(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT0B),
.CLKOUT1(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT1),
.CLKOUT1B(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT1B),
.CLKOUT2(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT2),
.CLKOUT2B(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT2B),
.CLKOUT3(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT3),
.CLKOUT3B(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT3B),
.DADDR({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.DO({CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO15, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO14, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO13, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO12, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO11, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO10, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO9, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO8, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO7, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO6, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO5, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO4, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO3, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO2, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO1, CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DO0}),
.DRDY(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DRDY),
.DWE(1'b0),
.LOCKED(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_LOCKED),
.PSCLK(1'b0),
.PSDONE(CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSDONE),
.PSEN(1'b1),
.PSINCDEC(1'b1),
.PWRDWN(1'b1),
.RST(LIOB33_X0Y11_IOB_X0Y11_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y1_IOB_X0Y1_OBUF (
.I(CLBLL_L_X2Y5_SLICE_X0Y5_AO6),
.O(led[7])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y3_IOB_X0Y3_OBUF (
.I(CLBLL_L_X2Y7_SLICE_X0Y7_D5Q),
.O(led[0])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y3_IOB_X0Y4_OBUF (
.I(1'b0),
.O(led[5])
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y5_IOB_X0Y5_IBUF (
.I(sw[6]),
.O(LIOB33_X0Y5_IOB_X0Y5_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y5_IOB_X0Y6_IBUF (
.I(sw[7]),
.O(LIOB33_X0Y5_IOB_X0Y6_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y7_IOB_X0Y7_IBUF (
.I(sw[4]),
.O(LIOB33_X0Y7_IOB_X0Y7_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y7_IOB_X0Y8_IBUF (
.I(sw[5]),
.O(LIOB33_X0Y7_IOB_X0Y8_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y9_IOB_X0Y9_IBUF (
.I(sw[3]),
.O(LIOB33_X0Y9_IOB_X0Y9_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y9_IOB_X0Y10_IBUF (
.I(sw[2]),
.O(LIOB33_X0Y9_IOB_X0Y10_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y11_IOB_X0Y11_IBUF (
.I(sw[0]),
.O(LIOB33_X0Y11_IOB_X0Y11_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y11_IOB_X0Y12_IBUF (
.I(sw[1]),
.O(LIOB33_X0Y11_IOB_X0Y12_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y17_IOB_X0Y18_OBUF (
.I(1'b0),
.O(led[4])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y19_IOB_X0Y19_OBUF (
.I(CLBLL_L_X2Y23_SLICE_X1Y23_D5Q),
.O(led[3])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y19_IOB_X0Y20_OBUF (
.I(CLBLL_L_X2Y16_SLICE_X0Y16_D5Q),
.O(led[2])
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y23_IOB_X0Y24_IBUF (
.I(jc3),
.O(LIOB33_X0Y23_IOB_X0Y24_I)
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) LIOB33_X0Y25_IOB_X0Y25_IBUF (
.I(jc1),
.O(LIOB33_X0Y25_IOB_X0Y25_I)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y25_IOB_X0Y26_OBUF (
.I(LIOB33_X0Y23_IOB_X0Y24_I),
.O(jc4)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y27_IOB_X0Y28_OBUF (
.I(LIOB33_X0Y25_IOB_X0Y25_I),
.O(jc2)
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_X0Y43_IOB_X0Y43_OBUF (
.I(CLBLL_L_X2Y39_SLICE_X1Y39_D5Q),
.O(led[1])
);
(* KEEP, DONT_TOUCH, BEL = "OUTBUF" *)
OBUF #(
.DRIVE("12"),
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) LIOB33_SING_X0Y0_IOB_X0Y0_OBUF (
.I(1'b0),
.O(led[6])
);
(* KEEP, DONT_TOUCH, BEL = "INBUF_EN" *)
IBUF #(
.IOSTANDARD("LVCMOS33")
) RIOB33_X43Y25_IOB_X1Y26_IBUF (
.I(clk),
.O(RIOB33_X43Y25_IOB_X1Y26_I)
);
assign CLBLL_L_X2Y5_SLICE_X0Y5_COUT = CLBLL_L_X2Y5_SLICE_X0Y5_D_CY;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A = CLBLL_L_X2Y5_SLICE_X0Y5_AO6;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B = CLBLL_L_X2Y5_SLICE_X0Y5_BO6;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C = CLBLL_L_X2Y5_SLICE_X0Y5_CO6;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D = CLBLL_L_X2Y5_SLICE_X0Y5_DO6;
assign CLBLL_L_X2Y5_SLICE_X0Y5_AMUX = CLBLL_L_X2Y5_SLICE_X0Y5_AO6;
assign CLBLL_L_X2Y5_SLICE_X0Y5_BMUX = CLBLL_L_X2Y5_SLICE_X0Y5_BO5;
assign CLBLL_L_X2Y5_SLICE_X1Y5_COUT = CLBLL_L_X2Y5_SLICE_X1Y5_D_CY;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A = CLBLL_L_X2Y5_SLICE_X1Y5_AO6;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B = CLBLL_L_X2Y5_SLICE_X1Y5_BO6;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C = CLBLL_L_X2Y5_SLICE_X1Y5_CO6;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D = CLBLL_L_X2Y5_SLICE_X1Y5_DO6;
assign CLBLL_L_X2Y7_SLICE_X0Y7_COUT = CLBLL_L_X2Y7_SLICE_X0Y7_D_CY;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A = CLBLL_L_X2Y7_SLICE_X0Y7_AO6;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B = CLBLL_L_X2Y7_SLICE_X0Y7_BO6;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C = CLBLL_L_X2Y7_SLICE_X0Y7_CO6;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D = CLBLL_L_X2Y7_SLICE_X0Y7_DO6;
assign CLBLL_L_X2Y7_SLICE_X0Y7_AMUX = CLBLL_L_X2Y7_SLICE_X0Y7_AO5;
assign CLBLL_L_X2Y7_SLICE_X0Y7_DMUX = CLBLL_L_X2Y7_SLICE_X0Y7_D5Q;
assign CLBLL_L_X2Y7_SLICE_X1Y7_COUT = CLBLL_L_X2Y7_SLICE_X1Y7_D_CY;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A = CLBLL_L_X2Y7_SLICE_X1Y7_AO6;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B = CLBLL_L_X2Y7_SLICE_X1Y7_BO6;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C = CLBLL_L_X2Y7_SLICE_X1Y7_CO6;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D = CLBLL_L_X2Y7_SLICE_X1Y7_DO6;
assign CLBLL_L_X2Y16_SLICE_X0Y16_COUT = CLBLL_L_X2Y16_SLICE_X0Y16_D_CY;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A = CLBLL_L_X2Y16_SLICE_X0Y16_AO6;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B = CLBLL_L_X2Y16_SLICE_X0Y16_BO6;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C = CLBLL_L_X2Y16_SLICE_X0Y16_CO6;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D = CLBLL_L_X2Y16_SLICE_X0Y16_DO6;
assign CLBLL_L_X2Y16_SLICE_X0Y16_AMUX = CLBLL_L_X2Y16_SLICE_X0Y16_AO5;
assign CLBLL_L_X2Y16_SLICE_X0Y16_DMUX = CLBLL_L_X2Y16_SLICE_X0Y16_D5Q;
assign CLBLL_L_X2Y16_SLICE_X1Y16_COUT = CLBLL_L_X2Y16_SLICE_X1Y16_D_CY;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A = CLBLL_L_X2Y16_SLICE_X1Y16_AO6;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B = CLBLL_L_X2Y16_SLICE_X1Y16_BO6;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C = CLBLL_L_X2Y16_SLICE_X1Y16_CO6;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D = CLBLL_L_X2Y16_SLICE_X1Y16_DO6;
assign CLBLL_L_X2Y23_SLICE_X0Y23_COUT = CLBLL_L_X2Y23_SLICE_X0Y23_D_CY;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A = CLBLL_L_X2Y23_SLICE_X0Y23_AO6;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B = CLBLL_L_X2Y23_SLICE_X0Y23_BO6;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C = CLBLL_L_X2Y23_SLICE_X0Y23_CO6;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D = CLBLL_L_X2Y23_SLICE_X0Y23_DO6;
assign CLBLL_L_X2Y23_SLICE_X1Y23_COUT = CLBLL_L_X2Y23_SLICE_X1Y23_D_CY;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A = CLBLL_L_X2Y23_SLICE_X1Y23_AO6;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B = CLBLL_L_X2Y23_SLICE_X1Y23_BO6;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C = CLBLL_L_X2Y23_SLICE_X1Y23_CO6;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D = CLBLL_L_X2Y23_SLICE_X1Y23_DO6;
assign CLBLL_L_X2Y23_SLICE_X1Y23_AMUX = CLBLL_L_X2Y23_SLICE_X1Y23_AO5;
assign CLBLL_L_X2Y23_SLICE_X1Y23_DMUX = CLBLL_L_X2Y23_SLICE_X1Y23_D5Q;
assign CLBLL_L_X2Y39_SLICE_X0Y39_COUT = CLBLL_L_X2Y39_SLICE_X0Y39_D_CY;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A = CLBLL_L_X2Y39_SLICE_X0Y39_AO6;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B = CLBLL_L_X2Y39_SLICE_X0Y39_BO6;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C = CLBLL_L_X2Y39_SLICE_X0Y39_CO6;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D = CLBLL_L_X2Y39_SLICE_X0Y39_DO6;
assign CLBLL_L_X2Y39_SLICE_X1Y39_COUT = CLBLL_L_X2Y39_SLICE_X1Y39_D_CY;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A = CLBLL_L_X2Y39_SLICE_X1Y39_AO6;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B = CLBLL_L_X2Y39_SLICE_X1Y39_BO6;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C = CLBLL_L_X2Y39_SLICE_X1Y39_CO6;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D = CLBLL_L_X2Y39_SLICE_X1Y39_DO6;
assign CLBLL_L_X2Y39_SLICE_X1Y39_AMUX = CLBLL_L_X2Y39_SLICE_X1Y39_AO5;
assign CLBLL_L_X2Y39_SLICE_X1Y39_DMUX = CLBLL_L_X2Y39_SLICE_X1Y39_D5Q;
assign LIOI3_X0Y1_OLOGIC_X0Y1_OQ = CLBLL_L_X2Y5_SLICE_X0Y5_AO6;
assign LIOI3_X0Y1_OLOGIC_X0Y1_TQ = 1'b1;
assign LIOI3_X0Y3_OLOGIC_X0Y4_OQ = 1'b0;
assign LIOI3_X0Y3_OLOGIC_X0Y4_TQ = 1'b1;
assign LIOI3_X0Y3_OLOGIC_X0Y3_OQ = CLBLL_L_X2Y7_SLICE_X0Y7_D5Q;
assign LIOI3_X0Y3_OLOGIC_X0Y3_TQ = 1'b1;
assign LIOI3_X0Y5_ILOGIC_X0Y6_O = LIOB33_X0Y5_IOB_X0Y6_I;
assign LIOI3_X0Y5_ILOGIC_X0Y5_O = LIOB33_X0Y5_IOB_X0Y5_I;
assign LIOI3_X0Y9_ILOGIC_X0Y10_O = LIOB33_X0Y9_IOB_X0Y10_I;
assign LIOI3_X0Y9_ILOGIC_X0Y9_O = LIOB33_X0Y9_IOB_X0Y9_I;
assign LIOI3_X0Y11_ILOGIC_X0Y12_O = LIOB33_X0Y11_IOB_X0Y12_I;
assign LIOI3_X0Y11_ILOGIC_X0Y11_O = LIOB33_X0Y11_IOB_X0Y11_I;
assign LIOI3_X0Y17_OLOGIC_X0Y18_OQ = 1'b0;
assign LIOI3_X0Y17_OLOGIC_X0Y18_TQ = 1'b1;
assign LIOI3_X0Y23_ILOGIC_X0Y24_O = LIOB33_X0Y23_IOB_X0Y24_I;
assign LIOI3_X0Y25_ILOGIC_X0Y25_O = LIOB33_X0Y25_IOB_X0Y25_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_OQ = LIOB33_X0Y23_IOB_X0Y24_I;
assign LIOI3_X0Y25_OLOGIC_X0Y26_TQ = 1'b1;
assign LIOI3_X0Y27_OLOGIC_X0Y28_OQ = LIOB33_X0Y25_IOB_X0Y25_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_TQ = 1'b1;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_OQ = 1'b0;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_O = LIOB33_X0Y7_IOB_X0Y8_I;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_O = LIOB33_X0Y7_IOB_X0Y7_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_OQ = CLBLL_L_X2Y16_SLICE_X0Y16_D5Q;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_OQ = CLBLL_L_X2Y23_SLICE_X1Y23_D5Q;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_TQ = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_OQ = CLBLL_L_X2Y39_SLICE_X1Y39_D5Q;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_TQ = 1'b1;
assign RIOI3_X43Y25_ILOGIC_X1Y26_O = RIOB33_X43Y25_IOB_X1Y26_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_D1 = CLBLL_L_X2Y16_SLICE_X0Y16_D5Q;
assign LIOI3_X0Y17_OLOGIC_X0Y18_T1 = 1'b1;
assign LIOB33_X0Y1_IOB_X0Y1_O = CLBLL_L_X2Y5_SLICE_X0Y5_AO6;
assign LIOI3_X0Y9_ILOGIC_X0Y10_D = LIOB33_X0Y9_IOB_X0Y10_I;
assign LIOI3_X0Y9_ILOGIC_X0Y9_D = LIOB33_X0Y9_IOB_X0Y9_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A1 = CLBLL_L_X2Y5_SLICE_X0Y5_BO6;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A2 = LIOB33_X0Y5_IOB_X0Y6_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A3 = LIOB33_X0Y5_IOB_X0Y5_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A4 = LIOB33_X0Y7_IOB_X0Y8_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A5 = LIOB33_X0Y7_IOB_X0Y7_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_A6 = CLBLL_L_X2Y5_SLICE_X0Y5_BO5;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B2 = LIOB33_X0Y11_IOB_X0Y11_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B3 = LIOB33_X0Y9_IOB_X0Y9_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B4 = LIOB33_X0Y11_IOB_X0Y12_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B5 = LIOB33_X0Y9_IOB_X0Y10_I;
assign CLBLL_L_X2Y5_SLICE_X0Y5_B6 = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI2 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI3 = 1'b0;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C2 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C3 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C4 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C5 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_C6 = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI4 = 1'b0;
assign LIOB33_SING_X0Y0_IOB_X0Y0_O = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI5 = 1'b0;
assign LIOI3_X0Y25_OLOGIC_X0Y26_D1 = LIOB33_X0Y23_IOB_X0Y24_I;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI6 = 1'b0;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D2 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D3 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D4 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D5 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X0Y5_D6 = 1'b1;
assign LIOI3_X0Y25_OLOGIC_X0Y26_T1 = 1'b1;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_D1 = 1'b0;
assign LIOI3_SING_X0Y0_OLOGIC_X0Y0_T1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A2 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A3 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A4 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A5 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_A6 = 1'b1;
assign LIOB33_X0Y17_IOB_X0Y18_O = 1'b0;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B2 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B3 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B4 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B5 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_B6 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C2 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C3 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C4 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C5 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_C6 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D1 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D2 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D3 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D4 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D5 = 1'b1;
assign CLBLL_L_X2Y5_SLICE_X1Y5_D6 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_S1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_S1 = 1'b1;
assign LIOB33_X0Y3_IOB_X0Y3_O = CLBLL_L_X2Y7_SLICE_X0Y7_D5Q;
assign LIOB33_X0Y3_IOB_X0Y4_O = 1'b0;
assign LIOI3_X0Y5_ILOGIC_X0Y6_D = LIOB33_X0Y5_IOB_X0Y6_I;
assign LIOI3_X0Y5_ILOGIC_X0Y5_D = LIOB33_X0Y5_IOB_X0Y5_I;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y20_T1 = 1'b1;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_D1 = CLBLL_L_X2Y23_SLICE_X1Y23_D5Q;
assign LIOI3_TBYTESRC_X0Y19_OLOGIC_X0Y19_T1 = 1'b1;
assign LIOB33_X0Y25_IOB_X0Y26_O = LIOB33_X0Y23_IOB_X0Y24_I;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_S1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_CE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_CE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_IGNORE0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_IGNORE1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_S0 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_S1 = 1'b1;
assign LIOI3_X0Y3_OLOGIC_X0Y4_D1 = 1'b0;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y7_D = LIOB33_X0Y7_IOB_X0Y7_I;
assign LIOI3_X0Y3_OLOGIC_X0Y4_T1 = 1'b1;
assign LIOI3_X0Y25_ILOGIC_X0Y25_D = LIOB33_X0Y25_IOB_X0Y25_I;
assign LIOI3_X0Y3_OLOGIC_X0Y3_D1 = CLBLL_L_X2Y7_SLICE_X0Y7_D5Q;
assign LIOI3_X0Y3_OLOGIC_X0Y3_T1 = 1'b1;
assign RIOI3_X43Y25_ILOGIC_X1Y26_D = RIOB33_X43Y25_IOB_X1Y26_I;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_D1 = CLBLL_L_X2Y39_SLICE_X1Y39_D5Q;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A3 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_A6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B3 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_B6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C3 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_C6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D6 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A3 = CLBLL_L_X2Y16_SLICE_X0Y16_D5Q;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_A6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X0Y39_D5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B6 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_B3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_C6 = 1'b1;
assign LIOB33_X0Y19_IOB_X0Y19_O = CLBLL_L_X2Y23_SLICE_X1Y23_D5Q;
assign LIOB33_X0Y19_IOB_X0Y20_O = CLBLL_L_X2Y16_SLICE_X0Y16_D5Q;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_D6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A3 = CLBLL_L_X2Y39_SLICE_X1Y39_D5Q;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X0Y16_DX = CLBLL_L_X2Y16_SLICE_X0Y16_AO5;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_A6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B3 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_B6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C3 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_C6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D1 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D2 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_DX = CLBLL_L_X2Y39_SLICE_X1Y39_AO5;
assign CLBLL_L_X2Y16_SLICE_X1Y16_A6 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D4 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D5 = 1'b1;
assign CLBLL_L_X2Y39_SLICE_X1Y39_D6 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_B6 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_C6 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D1 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D2 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D3 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D4 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D5 = 1'b1;
assign CLBLL_L_X2Y16_SLICE_X1Y16_D6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_A6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_B6 = 1'b1;
assign LIOB33_X0Y27_IOB_X0Y28_O = LIOB33_X0Y25_IOB_X0Y25_I;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_C6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X0Y23_D6 = 1'b1;
assign LIOI3_X0Y23_ILOGIC_X0Y24_D = LIOB33_X0Y23_IOB_X0Y24_I;
assign LIOI3_X0Y1_OLOGIC_X0Y1_D1 = CLBLL_L_X2Y5_SLICE_X0Y5_AO6;
assign LIOI3_X0Y1_OLOGIC_X0Y1_T1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A3 = CLBLL_L_X2Y23_SLICE_X1Y23_D5Q;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_A6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_B6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_C6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D1 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D2 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D3 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D4 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D5 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_D6 = 1'b1;
assign CLBLL_L_X2Y23_SLICE_X1Y23_DX = CLBLL_L_X2Y23_SLICE_X1Y23_AO5;
assign LIOI3_X0Y11_ILOGIC_X0Y12_D = LIOB33_X0Y11_IOB_X0Y12_I;
assign LIOI3_X0Y11_ILOGIC_X0Y11_D = LIOB33_X0Y11_IOB_X0Y11_I;
assign LIOI3_TBYTESRC_X0Y7_ILOGIC_X0Y8_D = LIOB33_X0Y7_IOB_X0Y8_I;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A3 = CLBLL_L_X2Y7_SLICE_X0Y7_D5Q;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_A6 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_B6 = 1'b1;
assign LIOI3_TBYTESRC_X0Y43_OLOGIC_X0Y43_T1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_C6 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_D6 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X0Y7_DX = CLBLL_L_X2Y7_SLICE_X0Y7_AO5;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_A6 = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBIN = CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKFBOUT;
assign LIOB33_X0Y43_IOB_X0Y43_O = CLBLL_L_X2Y39_SLICE_X1Y39_D5Q;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_B6 = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKIN1 = RIOB33_X43Y25_IOB_X1Y26_I;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKIN2 = RIOB33_X43Y25_IOB_X1Y26_I;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKINSEL = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_C6 = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR0 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR1 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR2 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR3 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR4 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR5 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DADDR6 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DCLK = 1'b0;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D1 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D2 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D3 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D4 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D5 = 1'b1;
assign CLBLL_L_X2Y7_SLICE_X1Y7_D6 = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DEN = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI0 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI1 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI11 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI12 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI13 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI14 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI15 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI7 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI8 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI9 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DI10 = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_DWE = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSCLK = 1'b0;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSEN = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PSINCDEC = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_PWRDWN = 1'b1;
assign CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_RST = LIOB33_X0Y11_IOB_X0Y11_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_D1 = LIOB33_X0Y25_IOB_X0Y25_I;
assign LIOI3_X0Y27_OLOGIC_X0Y28_T1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I0 = CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT0;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_I1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I0 = CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_I1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_I0 = CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT2;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_I1 = 1'b1;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_I0 = CMT_TOP_L_LOWER_B_X106Y9_MMCME2_ADV_X1Y0_CLKOUT3;
assign CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_I1 = 1'b1;
assign LIOI3_X0Y17_OLOGIC_X0Y18_D1 = 1'b0;
assign CLBLL_L_X2Y23_SLICE_X1Y23_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y11_O;
assign CLBLL_L_X2Y39_SLICE_X1Y39_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y1_O;
assign CLBLL_L_X2Y16_SLICE_X0Y16_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y10_O;
assign CLBLL_L_X2Y7_SLICE_X0Y7_CLK = CLK_BUFG_BOT_R_X60Y48_BUFGCTRL_X0Y0_O;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:44 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_1_stub.v
// Design : zqynq_lab_1_design_xbar_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
Require Import ZArith String List Bool.
Require Import ExtLib.Core.ZDecidables.
Require Import ExtLib.Structures.Monads.
Require Import ExtLib.Data.Monads.OptionMonad.
Require Import ExtLib.Data.Monads.StateMonad.
Require Import ExtLib.Structures.Folds.
Require Import ExtLib.Data.Strings.
Require Import ExtLib.Data.Char.
Require Import ExtLib.Data.Lists.
Require Import ExtLib.Data.Option.
Require Import ExtLib.Core.RelDec.
Require Import ExtLib.Tactics.Consider.
Set Implicit Arguments.
Set Strict Implicit.
(** Provides abstract syntax and "ugly" printer for LLVM assembly code.
I've tried to be relatively complete but there are a few missing
instructions, attributes, etc. that we are very unlikely to use
(e.g., things dealing with concurrency or intrinsics.)
The ugly printer has not been tested at all.
We probably want to provide some some convenience on top of this
for building abstract syntax that provides convenient defaults.
*)
Module LLVM.
Import MonadNotation String.
Local Open Scope string_scope.
Local Open Scope monad_scope.
Definition var := string.
Definition label := string.
Inductive cconv : Type :=
| X86_fastcallcc | C_cc | Fast_cc | Cold_cc | CC10_cc | Num_cc : nat -> cconv.
Inductive linkage : Type :=
| Private | Linker_private | Linker_private_weak | Linker_private_weak_def_auto
| Internal | Available_externally | Linkonce | Weak | Common | Appending | Extern_weak
| Linkonce_odr | Weak_odr | External | Dllimport | Dllexport.
Inductive visibility : Type := | Default_v | Hidden_v | Protected_v.
Inductive param_attr : Type :=
| Zeroext_pattr | Signext_pattr | Inreg_pattr | Byval_pattr | Sret_pattr | Noalias_pattr
| Nocapture_pattr | Nest_pattr.
Inductive fn_attr : Type :=
| Address_safety | Align_stack : nat -> fn_attr | Alwaysinline | Nonlazybind | Inlinehint
| Naked | Noimplicitfloat | Noinline | Noredzone | Noreturn | Nounwind
| Optsize | Readnone | Readonly | Returns_twice | Ssp | Sspreq | Uwtable.
Inductive type : Type :=
| I_t : nat -> type
| Half_t | Float_t | Double_t | X86_fp80_t | Fp128_t | Ppc_fp128_t
| Void_t | Label_t | X86mmx_t | Metadata_t
| Array_t : list nat -> type -> type
| Fn_t : forall (returntype: type) (arg_types : list type) (vararg : bool), type
| Struct_t : forall (packed:bool) (elts : list type), type
| Named_t : string -> type
| Opaque_t : type
| Pointer_t : forall (addrspace:nat), type -> type
| Vector_t : nat -> type -> type.
Inductive constant : Type :=
| True_c
| False_c
| Int_c : Z -> constant
| Float_c : string -> constant
| Null_c : constant
| Global_c : var -> constant
| Undef_c : constant
| Zero_c : constant
| Struct_c : list constant -> constant
| Array_c : list constant -> constant
| Vector_c : list constant -> constant
| Metadata_c : list constant -> constant
| Metastring_c : string -> constant
| Ptrtoint_c : type -> constant -> type -> constant
| Inttoptr_c : type -> constant -> type -> constant
| Bitcast_c : type ->constant -> type -> constant.
Inductive value : Type :=
| Local : var -> value
| Global : var -> value
| AnonLocal : nat -> value
| AnonGlobal : nat -> value
| Constant : constant -> value.
Inductive cond : Type :=
| Eq | Ne | Ugt | Uge | Ult | Ule | Sgt | Sge | Slt | Sle.
Inductive fcond : Type :=
| False_fc | Oeq_fc | Ogt_fc | Oge_fc | Olt_fc | Ole_fc | One_fc | Ord_fc | Ueq_fc
| Ugt_fc | Uge_fc | Ult_fc | Ule_fc | Une_fc | Uno_fc | True_fc.
Inductive exp : Type :=
| Add_e : forall (nuw:bool) (nsw:bool) (ty:type) (op1:value) (op2:value), exp
| Fadd_e : forall (ty:type) (op1:value) (op2:value), exp
| Sub_e : forall (nuw:bool) (nsw:bool) (ty:type) (op1:value) (op2:value), exp
| Fsub_e : forall (ty:type) (op1:value) (op2:value), exp
| Mul_e : forall (nuw:bool) (nsw:bool) (ty:type) (op1:value) (op2:value), exp
| Fmul_e : forall (ty:type) (op1:value) (op2:value), exp
| Udiv_e : forall (exact:bool) (ty:type) (op1 op2:value), exp
| Sdiv_e : forall (exact:bool) (ty:type) (op1 op2:value), exp
| Fdiv_e : forall (ty:type) (op1:value) (op2:value), exp
| Urem_e : forall (ty:type) (op1:value) (op2:value), exp
| Srem_e : forall (ty:type) (op1:value) (op2:value), exp
| Frem_e : forall (ty:type) (op1:value) (op2:value), exp
| Shl_e : forall (nuw:bool) (nsw:bool) (ty:type) (op1:value) (op2:value), exp
| Lshr_e : forall (exact:bool) (ty:type) (op1 op2:value), exp
| Ashr_e : forall (exact:bool) (ty:type) (op1 op2:value), exp
| And_e : forall (ty:type) (op1 op2:value), exp
| Or_e : forall (ty:type) (op1 op2:value), exp
| Xor_e : forall (ty:type) (op1 op2:value), exp
| Extractvalue_e : type -> value -> nat -> list nat -> exp
| Insertvalue_e : type -> value -> type -> value -> nat -> list nat -> exp
| Alloca_e : type -> option (type * nat) -> option nat -> exp
| Load_e : forall (atomic:bool) (volatile:bool) (ty:type) (pointer:value) (align:option nat)
(nontemporal:option nat) (invariant:option nat) (singlethread:bool), exp
| Getelementptr_e : forall (inbounds:bool)(pointer_ty:type) (pointerval: value), list (type * value) -> exp
| Trunc_e : type -> value -> type -> exp
| Zext_e : type -> value -> type -> exp
| Sext_e : type -> value -> type -> exp
| Fptrunc_e : type -> value -> type -> exp
| Fpext_e : type -> value -> type -> exp
| Fptoui_e : type -> value -> type -> exp
| Fptosi_e : type -> value -> type -> exp
| Uitofp_e : type -> value -> type -> exp
| Sitofp_e : type -> value -> type -> exp
| Ptrtoint_e : type -> value -> type -> exp
| Inttoptr_e : type -> value -> type -> exp
| Bitcast_e : type -> value -> type -> exp
| Icmp_e : cond -> type -> value -> value -> exp
| Fcmp_e : fcond -> type -> value -> value -> exp
| Phi_e : type -> list (value * label) -> exp
| Select_e : type -> value -> type -> value -> type -> value -> exp
| Call_e : forall (tail:bool) (convention: option cconv) (ret_attrs:list param_attr) (ty:type)
(fnptrty: option type) (fnptr:value)
(args : list (type * value * (list param_attr)))
(fn_attrs: list fn_attr), exp.
Definition flag(b:bool)(s:string) : string := if b then s else "".
Inductive instr : Type :=
| Comment_i : string -> instr
| Ret_i : option (type * value) -> instr
| Br_cond_i : value -> label -> label -> instr
| Br_uncond_i : label -> instr
| Switch_i : type -> value -> label -> list (type * Z * label) -> instr
| Resume_i : type -> value -> instr
| Unreachable_i : instr
| Assign_i : (option value) -> exp -> instr
| Store_i : forall (atomic:bool) (volatile:bool) (ty:type) (v:value) (ptrty:type) (pointer:value)
(align:option nat) (nontemporal:option nat) (singlethread:bool), instr.
Record fn_header : Type := {
linkage_fh : option linkage ;
visibility_fh : option visibility ;
cconv_fh : option cconv ;
unnamed_addr_fh : bool ;
return_type_fh : type ;
return_type_attrs_fh : list param_attr ;
name_fh : var ;
args_fh : list (type * var * list (param_attr)) ;
attrs_fh : list fn_attr ;
section_fh : option string ;
align_fh : option nat ;
gc_fh : option string
}.
Definition block := ((option label) * (list instr))%type.
Inductive topdecl : Type :=
| Global_d : forall (x:var) (addrspace:option nat) (l:option linkage) (unnamed_addr:bool) (const:bool)
(t:type) (c:constant) (section:option string) (align:option nat), topdecl
| Define_d : fn_header -> list block -> topdecl
| Declare_d : fn_header -> topdecl
| Alias_d : forall (x:var) (l:option linkage) (v:option visibility) (t:type) (e:exp), topdecl
| Metadata_d : forall (x:var), list constant -> topdecl.
Definition module := list topdecl.
Fixpoint eq_type x y : bool :=
match x , y with
| I_t n , I_t n' => eq_dec n n'
| Half_t , Half_t => true
| Float_t , Float_t => true
| Double_t , Double_t => true
| X86_fp80_t , X86_fp80_t => true
| Fp128_t , Fp128_t => true
| Ppc_fp128_t , Ppc_fp128_t => true
| Void_t , Void_t => true
| Label_t , Label_t => true
| X86mmx_t , X86mmx_t => true
| Metadata_t , Metadata_t => true
| Array_t ns t , Array_t ns' t' =>
eq_dec ns ns' && eq_type t t'
| Fn_t r a b , Fn_t r' a' b' =>
eq_type r r' && eq_dec b b' &&
(fix recur l r :=
match l , r with
| nil , nil => true
| cons l ls , cons r rs =>
if eq_type l r then recur ls rs else false
| _ , _ => false
end) a a'
| Struct_t b e , Struct_t b' e' =>
eq_dec b b' &&
(fix recur l r :=
match l , r with
| nil , nil => true
| cons l ls , cons r rs =>
if eq_type l r then recur ls rs else false
| _ , _ => false
end) e e'
| Named_t n , Named_t n' =>
eq_dec n n'
| Pointer_t a t , Pointer_t a' t' =>
eq_dec a a' && eq_type t t'
| Vector_t n t , Vector_t n' t' =>
eq_dec n n' && eq_type t t'
| _ , _ => false
end.
Global Instance RelDec_eq_LLVMtype : RelDec (@eq LLVM.type) :=
{ rel_dec := eq_type }.
Fixpoint eq_constant x y : bool :=
match x , y with
| True_c , True_c
| False_c , False_c
| Null_c , Null_c
| Undef_c , Undef_c
| Zero_c , Zero_c => true
| Int_c i1, Int_c i2 => eq_dec i1 i2
| Float_c c1, Float_c c2 => eq_dec c1 c2
| Global_c v , Global_c v' => eq_dec v v'
| Struct_c v , Struct_c v'
| Array_c v, Array_c v'
| Vector_c v , Vector_c v'
| Metadata_c v , Metadata_c v' =>
(fix rec xs ys : bool :=
match xs , ys with
| nil , nil => true
| x :: xs , y :: ys =>
eq_constant x y && rec xs ys
| _ , _ => false
end) v v'
| Metastring_c v , Metastring_c v' => eq_dec v v'
| Ptrtoint_c t1 c t2 , Ptrtoint_c t1' c' t2' =>
eq_constant c c' && eq_dec t1 t1' && eq_dec t2 t2'
| Inttoptr_c t1 c t2 , Inttoptr_c t1' c' t2' =>
eq_constant c c' && eq_dec t1 t1' && eq_dec t2 t2'
| Bitcast_c t1 c t2 , Bitcast_c t1' c' t2' =>
eq_constant c c' && eq_dec t1 t1' && eq_dec t2 t2'
| _ , _ => false
end.
Global Instance RelDec_eq_constant : RelDec (@eq LLVM.constant) :=
{ rel_dec := eq_constant }.
Global Instance RelDec_eq_value : RelDec (@eq value) :=
{ rel_dec := fun x y =>
match x , y with
| Local v, Local v' => eq_dec v v'
| Global v , Global v' => eq_dec v v'
| AnonLocal v, AnonLocal v' => eq_dec v v'
| AnonGlobal v, AnonGlobal v' => eq_dec v v'
| Constant c, Constant c' => eq_dec c c'
| _ , _ => false
end }.
Section Printing.
Require Import ExtLib.Programming.Show.
Import ShowNotation.
Local Open Scope show_scope.
Global Instance Show_cconv : Show cconv :=
fun c =>
match c with
| X86_fastcallcc => "x86_fastcallcc"
| C_cc => "ccc" | Fast_cc => "fastcc" | Cold_cc => "coldcc" | CC10_cc => "cc 10"
| Num_cc n => "cc " << show n
end.
Global Instance Show_linkage : Show linkage :=
fun l =>
match l with
| Private => "private"
| Linker_private => "linker_private"
| Linker_private_weak => "linker_private_weak"
| Linker_private_weak_def_auto => "linker_private_weak_def_auto"
| Internal => "internal"
| Available_externally => "available_externally"
| Linkonce => "linkonce"
| Weak => "weak"
| Common => "common"
| Appending => "appending"
| Extern_weak => "extern_weak"
| Linkonce_odr => "linkonce_odr"
| Weak_odr => "weak_odr"
| External => "external"
| Dllimport => "dllimport"
| Dllexport => "dllexport"
end.
Global Instance Show_param_attr : Show param_attr :=
fun p =>
match p with
| Zeroext_pattr => "zeroext" | Signext_pattr => "signext" | Inreg_pattr => "inreg"
| Byval_pattr => "byval" | Sret_pattr => "sret" | Noalias_pattr => "noalias"
| Nocapture_pattr => "nocapture" | Nest_pattr => "nest"
end.
Definition double_quote := Ascii.ascii_of_nat 34.
Definition quoted := wrap double_quote double_quote.
Global Instance Show_visibility : Show visibility :=
fun v => quoted
match v with
| Default_v => "default" | Hidden_v => "hidden" | Protected_v => "protected"
end.
Global Instance Show_fn_attr : Show fn_attr :=
fun f =>
match f with
| Address_safety => "address_safety"
| Align_stack n => "alignstack(" << show n << ")"
| Alwaysinline => "alwaysinline"
| Nonlazybind => "nonlazybind"
| Inlinehint => "inlinehint"
| Naked => "naked"
| Noimplicitfloat => "noimplicitfloat"
| Noinline => "noinline"
| Noredzone => "noredzone"
| Noreturn => "noreturn"
| Nounwind => "nounwind"
| Optsize => "optsize"
| Readnone => "readnone"
| Readonly => "readonly"
| Returns_twice => "returns_twice"
| Ssp => "ssp"
| Sspreq => "sspreq"
| Uwtable => "uwtable"
end.
Global Instance Show_type : Show type :=
fix show_type (t : type) : showM :=
match t with
| I_t n => "i" << show n
| Half_t => "half"
| Float_t => "float"
| Double_t => "double"
| X86_fp80_t => "x86_fp80"
| Fp128_t => "fp128"
| Ppc_fp128_t => "ppc_fp128"
| Void_t => "void"
| Label_t => "label"
| X86mmx_t => "x86mmx"
| Metadata_t => "metadata"
| Array_t ns t =>
List.fold_right (fun (i:nat) (t:showM) =>
"[" << show i << " x " << t << "]") (show_type t) ns
| Fn_t t ts vararg =>
show_type t << "(" << sepBy ", " (List.map show_type ts) <<
(if vararg then ",...)" else ")")
| Struct_t packed elts =>
let s := "{" << (sepBy ", " (List.map show_type elts)) << "}" in
if packed then "<" << s << ">" else s
| Named_t x => x
| Opaque_t => "opaque"
| Pointer_t 0 t => show_type t << " *"
| Pointer_t n t => show_type t << "addrspace(" << show n << ") *"
| Vector_t n t => "<" << show n << " x " << show_type t << ">"
end.
Global Instance Show_constant : Show constant :=
fix show_constant c :=
match c return showM with
| True_c => "true"
| False_c => "false"
| Int_c i => show i
| Float_c s => s
| Null_c => "null"
| Global_c v => v
| Undef_c => "undef"
| Zero_c => "zeroinitializer"
| Struct_c cs => "{" << sepBy ", " (List.map show_constant cs) << "}"
| Array_c cs => "[" << sepBy ", " (List.map show_constant cs) << "]"
| Vector_c cs => "<" << sepBy ", " (List.map show_constant cs) << ">"
| Metastring_c s => "!" << quoted s
| Metadata_c cs => "!{" << sepBy ", " (List.map show_constant cs) << "}"
| Ptrtoint_c t1 c t2 => "ptrtoint (" << (show t1) << " " << (show_constant c) << " to " << (show t2) << ")"
| Inttoptr_c t1 c t2 => "inttoptr (" << (show t1) << " " << (show_constant c) << " to " << (show t2) << ")"
| Bitcast_c t1 c t2 => "bitcast (" << (show t1) << " " << (show_constant c) << " to " << (show t2) << ")"
end.
Global Instance Show_value : Show value :=
fun v =>
match v with
| Local x => "%" << x
| Global x => "@" << x
| AnonLocal n => "%" << show n
| AnonGlobal n => "@" << show n
| Constant c => show c
end.
Global Instance Show_cond : Show cond :=
fun c =>
match c with
| Eq => "eq" | Ne => "ne" | Ugt => "ugt" | Uge => "uge" | Ult => "ult" | Ule => "ule"
| Sgt => "sgt" | Sge => "sge" | Slt => "slt" | Sle => "sle"
end.
Global Instance Show_fcond : Show fcond :=
fun f =>
match f with
| False_fc => "false" | Oeq_fc => "oeq" | Ogt_fc => "ogt" | Oge_fc => "oge" | Olt_fc => "olt"
| Ole_fc => "ole" | One_fc => "one" | Ord_fc => "ord" | Ueq_fc => "ueq" | Ugt_fc => "ugt"
| Uge_fc => "uge" | Ult_fc => "ult" | Ule_fc => "ule" | Une_fc => "une" | Uno_fc => "uno"
| True_fc => "true"
end.
Definition option_show (T : Type) (f : T -> showM) (o : option T) : showM :=
match o with
| None => empty
| Some x => f x
end.
Global Instance Show_option (T : Type) {S : Show T} : Show (option T) :=
fun x => option_show show x.
Definition show_fn_header (drop_vars:bool) (fh:fn_header) : showM :=
show (linkage_fh fh) << " " <<
show (visibility_fh fh) << " " <<
show (cconv_fh fh) << " " <<
(if (unnamed_addr_fh fh) then "unnamed_addr " else empty) <<
show (return_type_fh fh) << " " <<
iter_show (map (fun x => show x << " ") (return_type_attrs_fh fh)) <<
"@" << name_fh fh << "(" <<
sepBy ", "
(map (fun (p : type * var * list param_attr) =>
let '(t, x, attrs) := p in
show t <<
(if drop_vars then empty else " %"%string << x) <<
iter_show (map (fun x => show x << " ") attrs))
(args_fh fh)) <<
") " <<
iter_show (map (fun x => show x << " ") (attrs_fh fh)) <<
option_show (fun s : string => ", section " << quoted s << " ") (section_fh fh) <<
option_show (fun n => ", align " << show n << " ") (align_fh fh) <<
option_show (fun s : string => "gc " << quoted s << " ") (gc_fh fh).
Definition show_arith(opcode:string)(nuw nsw:bool)(ty:type)(op1 op2:value) : showM :=
opcode << " " << flag nuw "nuw " << flag nsw "nsw " << show ty << " " <<
show op1 << ", " << show op2.
Definition show_binop(opcode:string)(ty:type)(op1 op2:value) : showM :=
show_arith opcode false false ty op1 op2.
Definition show_logical(opcode:string)(ex:bool)(ty:type)(op1 op2:value) : showM :=
opcode << " " << flag ex "exact " << show ty << " " << show op1 << ", " << show op2.
Definition show_conv(opcode:string)(ty1:type)(op:value)(ty2:type) : showM :=
opcode << " " << show ty1 << " " << show op << " to " << show ty2.
Definition show_alloca (ty : type) (opttynum : option (type * nat)) (optalign : option nat) : showM :=
"alloca " << show ty <<
match opttynum return showM with
| None => ""
| Some (ty,n) => ", " << show ty << " " << show n
end <<
match optalign return showM with
| None => ""
| Some n => ", align " << show n
end.
Definition show_call (tail : bool) (conv : option cconv) (ret_attrs : list param_attr)
(ty : type) (fnptrty : option type) (fnptr : value) (args : list (type * value * list param_attr)) (fnattrs : list fn_attr) : showM :=
flag tail "tail " << "call " << option_show show conv << " " <<
sepBy " " (List.map show ret_attrs) << " " <<
show ty << " " << option_show show fnptrty <<
show fnptr << "(" <<
(sepBy ", " (List.map (fun x => match x with | (t,v,a) =>
(show t) << " " << (show v) <<
(sepBy " " (List.map show a))
end) args))
<< ") " << sepBy " " (List.map show fnattrs).
Global Instance Show_exp : Show exp :=
{ show := fun e =>
match e with
| Add_e nuw nsw ty op1 op2 => show_arith "add" nuw nsw ty op1 op2
| Fadd_e ty op1 op2 => show_binop "fadd" ty op1 op2
| Sub_e nuw nsw ty op1 op2 => show_arith "sub" nuw nsw ty op1 op2
| Fsub_e ty op1 op2 => show_binop "fsub" ty op1 op2
| Mul_e nuw nsw ty op1 op2 => show_arith "mul" nuw nsw ty op1 op2
| Fmul_e ty op1 op2 => show_binop "fmul" ty op1 op2
| Udiv_e ex ty op1 op2 => show_logical "udiv" ex ty op1 op2
| Sdiv_e ex ty op1 op2 => show_logical "sdiv" ex ty op1 op2
| Fdiv_e ty op1 op2 => show_binop "fdiv" ty op1 op2
| Urem_e ty op1 op2 => show_binop "urem" ty op1 op2
| Srem_e ty op1 op2 => show_binop "srem" ty op1 op2
| Frem_e ty op1 op2 => show_binop "frem" ty op1 op2
| Shl_e nuw nsw ty op1 op2 => show_arith "shl" nuw nsw ty op1 op2
| Lshr_e ex ty op1 op2 => show_logical "lshr" ex ty op1 op2
| Ashr_e ex ty op1 op2 => show_logical "ashr" ex ty op1 op2
| And_e ty op1 op2 => show_binop "and" ty op1 op2
| Or_e ty op1 op2 => show_binop "or" ty op1 op2
| Xor_e ty op1 op2 => show_binop "xor" ty op1 op2
| Extractvalue_e ty op n ns =>
"extractvalue " << show ty << " " << show op << ", " <<
sepBy ", " (List.map show (n::ns))
| Insertvalue_e ty1 op1 ty2 op2 n ns =>
"insertvalue " << show ty1 << " " << show op1 << ", " <<
show ty2 << " " << show op2 << ", " <<
sepBy ", " (List.map show (n::ns))
| Alloca_e ty opttynum optalign => show_alloca ty opttynum optalign
| Load_e atomic volatile ty pointer align nontemporal invariant singlethread =>
(* fixme: just doing the simple stuff here *)
"load " << flag atomic "atomic " << flag volatile "volatile " <<
show ty << " " << show pointer << " " << flag singlethread "singlethread " <<
match align return showM with
| None => ""
| Some n => ", align " << show n
end
| Getelementptr_e inbounds ty v indexes =>
"getelementptr " << (flag inbounds "inbounds ") << (show ty) << " " <<
(sepBy ", " ((show v)::
(List.map (fun p => (show (fst p)) << " " << (show (snd p))) indexes)))
| Trunc_e ty1 v ty2 => show_conv "trunc" ty1 v ty2
| Zext_e ty1 v ty2 => show_conv "zext" ty1 v ty2
| Sext_e ty1 v ty2 => show_conv "sext" ty1 v ty2
| Fptrunc_e ty1 v ty2 => show_conv "fptrunc" ty1 v ty2
| Fpext_e ty1 v ty2 => show_conv "fpext" ty1 v ty2
| Fptoui_e ty1 v ty2 => show_conv "fptoui" ty1 v ty2
| Fptosi_e ty1 v ty2 => show_conv "fptosi" ty1 v ty2
| Uitofp_e ty1 v ty2 => show_conv "uitofp" ty1 v ty2
| Sitofp_e ty1 v ty2 => show_conv "sitofp" ty1 v ty2
| Ptrtoint_e ty1 v ty2 => show_conv "ptrtoint" ty1 v ty2
| Inttoptr_e ty1 v ty2 => show_conv "inttoptr" ty1 v ty2
| Bitcast_e ty1 v ty2 => show_conv "bitcast" ty1 v ty2
| Icmp_e cond ty v1 v2 => "icmp " << (show cond) << " " << (show ty) <<
(show v1) << ", " << (show v2)
| Fcmp_e cond ty v1 v2 => "fcmp " << (show cond) << " " << (show ty) <<
(show v1) << ", " << (show v2)
| Phi_e ty vls =>
"phi " << show ty << " " <<
sepBy ", " (List.map (fun p : (value * label) => "[ " << show (fst p) << ", %" << (snd p) << " ]") vls)
| Select_e ty1 v1 ty2 v2 ty3 v3 =>
"select " << (show ty1) << " " << (show v1) << ", " <<
(show ty2) << " " << (show v2) << ", " <<
(show ty3) << " " << (show v3)
| Call_e tail conv ret_attrs ty fnptrty fnptr args fnattrs =>
show_call tail conv ret_attrs ty fnptrty fnptr args fnattrs
end }.
Global Instance Show_instr : Show instr :=
fun i =>
match i with
| Comment_i s => "; " << s
| Ret_i vopt =>
"ret " <<
option_show (fun p => show (fst p) << " " << show (snd p)) vopt
| Br_cond_i v l1 l2 =>
"br i1 " << show v << ", label %" << l1 << ", label %" << l2
| Br_uncond_i l =>
"br label %"<< l
| Switch_i t v def arms =>
"switch " << show t << " " << show v << ", label %" << def << " [" <<
sepBy " " (List.map (fun p : type * Z * label =>
let '(t,i,l) := p in
show t << " " << show i << ", label %" << l) arms) << " ]"
| Resume_i t v =>
"resume " << show t << " " << show v
| Unreachable_i => "unreachable"
| Assign_i (Some x) e => show x << " = " << show e
| Assign_i None e => show e
| Store_i atomic volatile ty v ptrty pointer align nontemporal singlethread =>
(* fix -- doesn't do nontemporal or ordering *)
"store " << flag atomic "atomic " << flag volatile "volatile " << show ty << " " <<
show v << ", " << show ptrty << " " << show pointer << " " <<
flag singlethread "singlethread " <<
option_show (fun n => ", align " << show n << " ") align
end.
Global Instance Show_block : Show block :=
fun b =>
match fst b with
| None => " "
| Some l =>
l << ":" << chr_newline << " "
end
<< indent " " (sepBy Char.chr_newline (map show (snd b))).
Global Instance Show_topdecl : Show topdecl :=
fun t =>
match t return showM with
| Global_d x a l u c t v s al =>
x << " = " <<
option_show (fun n => "addrspace(" << show n << ")") a <<
option_show show l <<
(if u then "unnamed_addr " else empty) <<
(if c then "constant " else empty) <<
show t << " " <<
show v << " " <<
option_show (fun s : string => ", section " << quoted s << " ") s <<
option_show (fun n => ", align " << show n << " ") al <<
chr_newline
| Define_d fh bs => "define " <<
show_fn_header false fh << " {" << indent " " (chr_newline << sepBy Char.chr_newline (map show bs)) << chr_newline << "}" << chr_newline
| Declare_d fh => "declare " << show_fn_header true fh << chr_newline
| Alias_d x l v t e =>
x << " = alias " <<
show l <<
show v <<
show t << " " <<
show e << chr_newline
| Metadata_d x cs =>
x << " = metadata !{" << sepBy ", " (List.map show cs) <<
"}" << chr_newline
end.
Global Instance Show_module : Show module :=
fun m => sepBy Char.chr_newline (map show m).
Definition string_of_module (m : module) : string := runShow (show m) "".
Definition string_of_topdecl (t : topdecl) : string := runShow (show t) "".
Definition string_of_fn_header (b : bool) (h : fn_header) : string := runShow (show_fn_header b h) "".
End Printing.
End LLVM.
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC top for ML501 board ////
/// ////
/// Instantiates modules, depending on ORPSoC defines file ////
/// ////
/// Julius Baxter, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
module orpsoc_top
(
GPIO_LED_0, GPIO_LED_1,
`ifdef JTAG_DEBUG
tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i, jtag_gnd, jtag_vdd,
`elsif ADV_DEBUG
tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i, jtag_gnd, jtag_vdd,
`endif
`ifdef XILINX_DDR2
ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n,
ddr2_cs_n, ddr2_odt, ddr2_cke, ddr2_dm,
ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_ck, ddr2_ck_n,
`endif
`ifdef XILINX_SSRAM
sram_clk, sram_clk_fb, sram_flash_addr, sram_flash_data,
sram_cen, sram_flash_oe_n, sram_flash_we_n, sram_bw,
sram_adv_ld_n, sram_mode,
`endif
`ifdef UART0
uart0_srx_pad_i, uart0_stx_pad_o,
uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o,
`endif
`ifdef SPI0
spi0_mosi_o, spi0_ss_o,/* spi0_sck_o, spi0_miso_i,via STARTUP_VIRTEX5*/
`endif
`ifdef I2C0
i2c0_sda_io, i2c0_scl_io,
`endif
`ifdef I2C1
i2c1_sda_io, i2c1_scl_io,
`endif
`ifdef GPIO0
gpio0_io,
`endif
`ifdef ETH0
eth0_tx_clk, eth0_tx_data, eth0_tx_en, eth0_tx_er,
eth0_rx_clk, eth0_rx_data, eth0_dv, eth0_rx_er,
eth0_col, eth0_crs,
eth0_mdc_pad_o, eth0_md_pad_io,
`ifdef ETH0_PHY_RST
eth0_rst_n_o,
`endif
`endif
sys_clk_in_p,sys_clk_in_n,
rst_n_pad_i
);
`include "orpsoc-params.v"
input sys_clk_in_p,sys_clk_in_n;
input rst_n_pad_i;
output GPIO_LED_0;
output GPIO_LED_1;
`ifdef JTAG_DEBUG
output tdo_pad_o;
input tms_pad_i;
input tck_pad_i;
input tdi_pad_i;
output jtag_gnd;
output jtag_vdd;
`elsif ADV_DEBUG
output tdo_pad_o;
input tms_pad_i;
input tck_pad_i;
input tdi_pad_i;
output jtag_gnd;
output jtag_vdd;
`endif
`ifdef XILINX_DDR2
output [12:0] ddr2_a;
output [1:0] ddr2_ba;
output ddr2_ras_n;
output ddr2_cas_n;
output ddr2_we_n;
output [1:0] ddr2_cs_n;
output [1:0] ddr2_odt;
output [1:0] ddr2_cke;
output [7:0] ddr2_dm;
inout [63:0] ddr2_dq;
inout [7:0] ddr2_dqs;
inout [7:0] ddr2_dqs_n;
output [1:0] ddr2_ck;
output [1:0] ddr2_ck_n;
`endif
`ifdef XILINX_SSRAM
// ZBT SSRAM
output sram_clk;
input sram_clk_fb;
output [21:1] sram_flash_addr;
inout [31:0] sram_flash_data;
output sram_cen;
output sram_flash_oe_n;
output sram_flash_we_n;
output [3:0] sram_bw;
output sram_adv_ld_n;
output sram_mode;
`endif
`ifdef UART0
input uart0_srx_pad_i;
output uart0_stx_pad_o;
// Duplicates of the UART signals, this time to the USB debug cable
input uart0_srx_expheader_pad_i;
output uart0_stx_expheader_pad_o;
`endif
`ifdef SPI0
output spi0_mosi_o;
output [spi0_ss_width-1:0] spi0_ss_o;
/* via STARTUP_VIRTEX5
output spi0_sck_o;
input spi0_miso_i;
*/
`endif
`ifdef I2C0
inout i2c0_sda_io, i2c0_scl_io;
`endif
`ifdef I2C1
inout i2c1_sda_io, i2c1_scl_io;
`endif
`ifdef GPIO0
inout [gpio0_io_width-1:0] gpio0_io;
`endif
`ifdef ETH0
input eth0_tx_clk;
output [3:0] eth0_tx_data;
output eth0_tx_en;
output eth0_tx_er;
input eth0_rx_clk;
input [3:0] eth0_rx_data;
input eth0_dv;
input eth0_rx_er;
input eth0_col;
input eth0_crs;
output eth0_mdc_pad_o;
inout eth0_md_pad_io;
`ifdef ETH0_PHY_RST
output eth0_rst_n_o;
`endif
`endif // `ifdef ETH0
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation module
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire wb_clk, wb_rst;
wire ddr2_if_clk, ddr2_if_rst;
wire clk200;
wire dbg_tck;
clkgen clkgen0
(
.sys_clk_in_p (sys_clk_in_p),
.sys_clk_in_n (sys_clk_in_n),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
`ifdef JTAG_DEBUG
.tck_pad_i (tck_pad_i),
.dbg_tck_o (dbg_tck),
`endif
`ifdef XILINX_DDR2
.ddr2_if_clk_o (ddr2_if_clk),
.ddr2_if_rst_o (ddr2_if_rst),
.clk200_o (clk200),
`endif
// Asynchronous active low reset
.rst_n_pad_i (rst_n_pad_i)
);
////////////////////////////////////////////////////////////////////////
//
// Arbiter
//
////////////////////////////////////////////////////////////////////////
// Wire naming convention:
// First: wishbone master or slave (wbm/wbs)
// Second: Which bus it's on instruction or data (i/d)
// Third: Between which module and the arbiter the wires are
// Fourth: Signal name
// Fifth: Direction relative to module (not bus/arbiter!)
// ie. wbm_d_or12_adr_o is address OUT from the or1200
// OR1200 instruction bus wires
wire [wb_aw-1:0] wbm_i_or12_adr_o;
wire [wb_dw-1:0] wbm_i_or12_dat_o;
wire [3:0] wbm_i_or12_sel_o;
wire wbm_i_or12_we_o;
wire wbm_i_or12_cyc_o;
wire wbm_i_or12_stb_o;
wire [2:0] wbm_i_or12_cti_o;
wire [1:0] wbm_i_or12_bte_o;
wire [wb_dw-1:0] wbm_i_or12_dat_i;
wire wbm_i_or12_ack_i;
wire wbm_i_or12_err_i;
wire wbm_i_or12_rty_i;
// OR1200 data bus wires
wire [wb_aw-1:0] wbm_d_or12_adr_o;
wire [wb_dw-1:0] wbm_d_or12_dat_o;
wire [3:0] wbm_d_or12_sel_o;
wire wbm_d_or12_we_o;
wire wbm_d_or12_cyc_o;
wire wbm_d_or12_stb_o;
wire [2:0] wbm_d_or12_cti_o;
wire [1:0] wbm_d_or12_bte_o;
wire [wb_dw-1:0] wbm_d_or12_dat_i;
wire wbm_d_or12_ack_i;
wire wbm_d_or12_err_i;
wire wbm_d_or12_rty_i;
// Debug interface bus wires
wire [wb_aw-1:0] wbm_d_dbg_adr_o;
wire [wb_dw-1:0] wbm_d_dbg_dat_o;
wire [3:0] wbm_d_dbg_sel_o;
wire wbm_d_dbg_we_o;
wire wbm_d_dbg_cyc_o;
wire wbm_d_dbg_stb_o;
wire [2:0] wbm_d_dbg_cti_o;
wire [1:0] wbm_d_dbg_bte_o;
wire [wb_dw-1:0] wbm_d_dbg_dat_i;
wire wbm_d_dbg_ack_i;
wire wbm_d_dbg_err_i;
wire wbm_d_dbg_rty_i;
// Byte bus bridge master signals
wire [wb_aw-1:0] wbm_b_d_adr_o;
wire [wb_dw-1:0] wbm_b_d_dat_o;
wire [3:0] wbm_b_d_sel_o;
wire wbm_b_d_we_o;
wire wbm_b_d_cyc_o;
wire wbm_b_d_stb_o;
wire [2:0] wbm_b_d_cti_o;
wire [1:0] wbm_b_d_bte_o;
wire [wb_dw-1:0] wbm_b_d_dat_i;
wire wbm_b_d_ack_i;
wire wbm_b_d_err_i;
wire wbm_b_d_rty_i;
// Instruction bus slave wires //
// ram0 instruction bus wires
wire [31:0] wbs_i_ram0_adr_i;
wire [wbs_i_rom0_data_width-1:0] wbs_i_ram0_dat_i;
wire [3:0] wbs_i_ram0_sel_i;
wire wbs_i_ram0_we_i;
wire wbs_i_ram0_cyc_i;
wire wbs_i_ram0_stb_i;
wire [2:0] wbs_i_ram0_cti_i;
wire [1:0] wbs_i_ram0_bte_i;
wire [wbs_i_rom0_data_width-1:0] wbs_i_ram0_dat_o;
wire wbs_i_ram0_ack_o;
wire wbs_i_ram0_err_o;
wire wbs_i_ram0_rty_o;
// mc0 instruction bus wires
wire [31:0] wbs_i_mc0_adr_i;
wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_i;
wire [3:0] wbs_i_mc0_sel_i;
wire wbs_i_mc0_we_i;
wire wbs_i_mc0_cyc_i;
wire wbs_i_mc0_stb_i;
wire [2:0] wbs_i_mc0_cti_i;
wire [1:0] wbs_i_mc0_bte_i;
wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_o;
wire wbs_i_mc0_ack_o;
wire wbs_i_mc0_err_o;
wire wbs_i_mc0_rty_o;
// Data bus slave wires //
// ram0 data bus wires
wire [31:0] wbs_d_ram0_adr_i;
wire [wbs_d_rom0_data_width-1:0] wbs_d_ram0_dat_i;
wire [3:0] wbs_d_ram0_sel_i;
wire wbs_d_ram0_we_i;
wire wbs_d_ram0_cyc_i;
wire wbs_d_ram0_stb_i;
wire [2:0] wbs_d_ram0_cti_i;
wire [1:0] wbs_d_ram0_bte_i;
wire [wbs_d_rom0_data_width-1:0] wbs_d_ram0_dat_o;
wire wbs_d_ram0_ack_o;
wire wbs_d_ram0_err_o;
wire wbs_d_ram0_rty_o;
// mc0 data bus wires
wire [31:0] wbs_d_mc0_adr_i;
wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_i;
wire [3:0] wbs_d_mc0_sel_i;
wire wbs_d_mc0_we_i;
wire wbs_d_mc0_cyc_i;
wire wbs_d_mc0_stb_i;
wire [2:0] wbs_d_mc0_cti_i;
wire [1:0] wbs_d_mc0_bte_i;
wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_o;
wire wbs_d_mc0_ack_o;
wire wbs_d_mc0_err_o;
wire wbs_d_mc0_rty_o;
// i2c0 wires
wire [31:0] wbs_d_i2c0_adr_i;
wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i;
wire [3:0] wbs_d_i2c0_sel_i;
wire wbs_d_i2c0_we_i;
wire wbs_d_i2c0_cyc_i;
wire wbs_d_i2c0_stb_i;
wire [2:0] wbs_d_i2c0_cti_i;
wire [1:0] wbs_d_i2c0_bte_i;
wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o;
wire wbs_d_i2c0_ack_o;
wire wbs_d_i2c0_err_o;
wire wbs_d_i2c0_rty_o;
// i2c1 wires
wire [31:0] wbs_d_i2c1_adr_i;
wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i;
wire [3:0] wbs_d_i2c1_sel_i;
wire wbs_d_i2c1_we_i;
wire wbs_d_i2c1_cyc_i;
wire wbs_d_i2c1_stb_i;
wire [2:0] wbs_d_i2c1_cti_i;
wire [1:0] wbs_d_i2c1_bte_i;
wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o;
wire wbs_d_i2c1_ack_o;
wire wbs_d_i2c1_err_o;
wire wbs_d_i2c1_rty_o;
// spi0 wires
wire [31:0] wbs_d_spi0_adr_i;
wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i;
wire [3:0] wbs_d_spi0_sel_i;
wire wbs_d_spi0_we_i;
wire wbs_d_spi0_cyc_i;
wire wbs_d_spi0_stb_i;
wire [2:0] wbs_d_spi0_cti_i;
wire [1:0] wbs_d_spi0_bte_i;
wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o;
wire wbs_d_spi0_ack_o;
wire wbs_d_spi0_err_o;
wire wbs_d_spi0_rty_o;
// uart0 wires
wire [31:0] wbs_d_uart0_adr_i;
wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i;
wire [3:0] wbs_d_uart0_sel_i;
wire wbs_d_uart0_we_i;
wire wbs_d_uart0_cyc_i;
wire wbs_d_uart0_stb_i;
wire [2:0] wbs_d_uart0_cti_i;
wire [1:0] wbs_d_uart0_bte_i;
wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o;
wire wbs_d_uart0_ack_o;
wire wbs_d_uart0_err_o;
wire wbs_d_uart0_rty_o;
// gpio0 wires
wire [31:0] wbs_d_gpio0_adr_i;
wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i;
wire [3:0] wbs_d_gpio0_sel_i;
wire wbs_d_gpio0_we_i;
wire wbs_d_gpio0_cyc_i;
wire wbs_d_gpio0_stb_i;
wire [2:0] wbs_d_gpio0_cti_i;
wire [1:0] wbs_d_gpio0_bte_i;
wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o;
wire wbs_d_gpio0_ack_o;
wire wbs_d_gpio0_err_o;
wire wbs_d_gpio0_rty_o;
// eth0 slave wires
wire [31:0] wbs_d_eth0_adr_i;
wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_i;
wire [3:0] wbs_d_eth0_sel_i;
wire wbs_d_eth0_we_i;
wire wbs_d_eth0_cyc_i;
wire wbs_d_eth0_stb_i;
wire [2:0] wbs_d_eth0_cti_i;
wire [1:0] wbs_d_eth0_bte_i;
wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_o;
wire wbs_d_eth0_ack_o;
wire wbs_d_eth0_err_o;
wire wbs_d_eth0_rty_o;
// eth0 master wires
wire [wbm_eth0_addr_width-1:0] wbm_eth0_adr_o;
wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_o;
wire [3:0] wbm_eth0_sel_o;
wire wbm_eth0_we_o;
wire wbm_eth0_cyc_o;
wire wbm_eth0_stb_o;
wire [2:0] wbm_eth0_cti_o;
wire [1:0] wbm_eth0_bte_o;
wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_i;
wire wbm_eth0_ack_i;
wire wbm_eth0_err_i;
wire wbm_eth0_rty_i;
//
// Wishbone instruction bus arbiter
//
arbiter_ibus arbiter_ibus0
(
// Instruction Bus Master
// Inputs to arbiter from master
.wbm_adr_o (wbm_i_or12_adr_o),
.wbm_dat_o (wbm_i_or12_dat_o),
.wbm_sel_o (wbm_i_or12_sel_o),
.wbm_we_o (wbm_i_or12_we_o),
.wbm_cyc_o (wbm_i_or12_cyc_o),
.wbm_stb_o (wbm_i_or12_stb_o),
.wbm_cti_o (wbm_i_or12_cti_o),
.wbm_bte_o (wbm_i_or12_bte_o),
// Outputs to master from arbiter
.wbm_dat_i (wbm_i_or12_dat_i),
.wbm_ack_i (wbm_i_or12_ack_i),
.wbm_err_i (wbm_i_or12_err_i),
.wbm_rty_i (wbm_i_or12_rty_i),
// Slave 0
// Inputs to slave from arbiter
.wbs0_adr_i (wbs_i_ram0_adr_i),
.wbs0_dat_i (wbs_i_ram0_dat_i),
.wbs0_sel_i (wbs_i_ram0_sel_i),
.wbs0_we_i (wbs_i_ram0_we_i),
.wbs0_cyc_i (wbs_i_ram0_cyc_i),
.wbs0_stb_i (wbs_i_ram0_stb_i),
.wbs0_cti_i (wbs_i_ram0_cti_i),
.wbs0_bte_i (wbs_i_ram0_bte_i),
// Outputs from slave to arbiter
.wbs0_dat_o (wbs_i_ram0_dat_o),
.wbs0_ack_o (wbs_i_ram0_ack_o),
.wbs0_err_o (wbs_i_ram0_err_o),
.wbs0_rty_o (wbs_i_ram0_rty_o),
// Slave 1
// Inputs to slave from arbiter
.wbs1_adr_i (wbs_i_mc0_adr_i),
.wbs1_dat_i (wbs_i_mc0_dat_i),
.wbs1_sel_i (wbs_i_mc0_sel_i),
.wbs1_we_i (wbs_i_mc0_we_i),
.wbs1_cyc_i (wbs_i_mc0_cyc_i),
.wbs1_stb_i (wbs_i_mc0_stb_i),
.wbs1_cti_i (wbs_i_mc0_cti_i),
.wbs1_bte_i (wbs_i_mc0_bte_i),
// Outputs from slave to arbiter
.wbs1_dat_o (wbs_i_mc0_dat_o),
.wbs1_ack_o (wbs_i_mc0_ack_o),
.wbs1_err_o (wbs_i_mc0_err_o),
.wbs1_rty_o (wbs_i_mc0_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam arbiter_ibus0.slave0_addr_width = ibus_arb_slave0_addr_width;
defparam arbiter_ibus0.slave1_addr_width = ibus_arb_slave1_addr_width;
//
// Wishbone data bus arbiter
//
arbiter_dbus arbiter_dbus0
(
// Master 0
// Inputs to arbiter from master
.wbm0_adr_o (wbm_d_or12_adr_o),
.wbm0_dat_o (wbm_d_or12_dat_o),
.wbm0_sel_o (wbm_d_or12_sel_o),
.wbm0_we_o (wbm_d_or12_we_o),
.wbm0_cyc_o (wbm_d_or12_cyc_o),
.wbm0_stb_o (wbm_d_or12_stb_o),
.wbm0_cti_o (wbm_d_or12_cti_o),
.wbm0_bte_o (wbm_d_or12_bte_o),
// Outputs to master from arbiter
.wbm0_dat_i (wbm_d_or12_dat_i),
.wbm0_ack_i (wbm_d_or12_ack_i),
.wbm0_err_i (wbm_d_or12_err_i),
.wbm0_rty_i (wbm_d_or12_rty_i),
// Master 0
// Inputs to arbiter from master
.wbm1_adr_o (wbm_d_dbg_adr_o),
.wbm1_dat_o (wbm_d_dbg_dat_o),
.wbm1_we_o (wbm_d_dbg_we_o),
.wbm1_cyc_o (wbm_d_dbg_cyc_o),
.wbm1_sel_o (wbm_d_dbg_sel_o),
.wbm1_stb_o (wbm_d_dbg_stb_o),
.wbm1_cti_o (wbm_d_dbg_cti_o),
.wbm1_bte_o (wbm_d_dbg_bte_o),
// Outputs to master from arbiter
.wbm1_dat_i (wbm_d_dbg_dat_i),
.wbm1_ack_i (wbm_d_dbg_ack_i),
.wbm1_err_i (wbm_d_dbg_err_i),
.wbm1_rty_i (wbm_d_dbg_rty_i),
// Slaves
.wbs0_adr_i (wbs_d_mc0_adr_i),
.wbs0_dat_i (wbs_d_mc0_dat_i),
.wbs0_sel_i (wbs_d_mc0_sel_i),
.wbs0_we_i (wbs_d_mc0_we_i),
.wbs0_cyc_i (wbs_d_mc0_cyc_i),
.wbs0_stb_i (wbs_d_mc0_stb_i),
.wbs0_cti_i (wbs_d_mc0_cti_i),
.wbs0_bte_i (wbs_d_mc0_bte_i),
.wbs0_dat_o (wbs_d_mc0_dat_o),
.wbs0_ack_o (wbs_d_mc0_ack_o),
.wbs0_err_o (wbs_d_mc0_err_o),
.wbs0_rty_o (wbs_d_mc0_rty_o),
.wbs1_adr_i (wbs_d_eth0_adr_i),
.wbs1_dat_i (wbs_d_eth0_dat_i),
.wbs1_sel_i (wbs_d_eth0_sel_i),
.wbs1_we_i (wbs_d_eth0_we_i),
.wbs1_cyc_i (wbs_d_eth0_cyc_i),
.wbs1_stb_i (wbs_d_eth0_stb_i),
.wbs1_cti_i (wbs_d_eth0_cti_i),
.wbs1_bte_i (wbs_d_eth0_bte_i),
.wbs1_dat_o (wbs_d_eth0_dat_o),
.wbs1_ack_o (wbs_d_eth0_ack_o),
.wbs1_err_o (wbs_d_eth0_err_o),
.wbs1_rty_o (wbs_d_eth0_rty_o),
.wbs2_adr_i (wbm_b_d_adr_o),
.wbs2_dat_i (wbm_b_d_dat_o),
.wbs2_sel_i (wbm_b_d_sel_o),
.wbs2_we_i (wbm_b_d_we_o),
.wbs2_cyc_i (wbm_b_d_cyc_o),
.wbs2_stb_i (wbm_b_d_stb_o),
.wbs2_cti_i (wbm_b_d_cti_o),
.wbs2_bte_i (wbm_b_d_bte_o),
.wbs2_dat_o (wbm_b_d_dat_i),
.wbs2_ack_o (wbm_b_d_ack_i),
.wbs2_err_o (wbm_b_d_err_i),
.wbs2_rty_o (wbm_b_d_rty_i),
.wbs3_adr_i (wbs_d_ram0_adr_i),
.wbs3_dat_i (wbs_d_ram0_dat_i),
.wbs3_sel_i (wbs_d_ram0_sel_i),
.wbs3_we_i (wbs_d_ram0_we_i),
.wbs3_cyc_i (wbs_d_ram0_cyc_i),
.wbs3_stb_i (wbs_d_ram0_stb_i),
.wbs3_cti_i (wbs_d_ram0_cti_i),
.wbs3_bte_i (wbs_d_ram0_bte_i),
.wbs3_dat_o (wbs_d_ram0_dat_o),
.wbs3_ack_o (wbs_d_ram0_ack_o),
.wbs3_err_o (wbs_d_ram0_err_o),
.wbs3_rty_o (wbs_d_ram0_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
// These settings are from top level params file
defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width;
defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves;
defparam arbiter_dbus0.slave0_addr_width = dbus_arb_slave0_addr_width;
defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr;
defparam arbiter_dbus0.slave2_addr_width = dbus_arb_slave2_addr_width;
defparam arbiter_dbus0.slave3_addr_width = dbus_arb_slave3_addr_width;
//
// Wishbone byte-wide bus arbiter
//
arbiter_bytebus arbiter_bytebus0
(
// Master 0
// Inputs to arbiter from master
.wbm0_adr_o (wbm_b_d_adr_o),
.wbm0_dat_o (wbm_b_d_dat_o),
.wbm0_sel_o (wbm_b_d_sel_o),
.wbm0_we_o (wbm_b_d_we_o),
.wbm0_cyc_o (wbm_b_d_cyc_o),
.wbm0_stb_o (wbm_b_d_stb_o),
.wbm0_cti_o (wbm_b_d_cti_o),
.wbm0_bte_o (wbm_b_d_bte_o),
// Outputs to master from arbiter
.wbm0_dat_i (wbm_b_d_dat_i),
.wbm0_ack_i (wbm_b_d_ack_i),
.wbm0_err_i (wbm_b_d_err_i),
.wbm0_rty_i (wbm_b_d_rty_i),
// Byte bus slaves
.wbs0_adr_i (wbs_d_uart0_adr_i),
.wbs0_dat_i (wbs_d_uart0_dat_i),
.wbs0_we_i (wbs_d_uart0_we_i),
.wbs0_cyc_i (wbs_d_uart0_cyc_i),
.wbs0_stb_i (wbs_d_uart0_stb_i),
.wbs0_cti_i (wbs_d_uart0_cti_i),
.wbs0_bte_i (wbs_d_uart0_bte_i),
.wbs0_dat_o (wbs_d_uart0_dat_o),
.wbs0_ack_o (wbs_d_uart0_ack_o),
.wbs0_err_o (wbs_d_uart0_err_o),
.wbs0_rty_o (wbs_d_uart0_rty_o),
.wbs1_adr_i (wbs_d_gpio0_adr_i),
.wbs1_dat_i (wbs_d_gpio0_dat_i),
.wbs1_we_i (wbs_d_gpio0_we_i),
.wbs1_cyc_i (wbs_d_gpio0_cyc_i),
.wbs1_stb_i (wbs_d_gpio0_stb_i),
.wbs1_cti_i (wbs_d_gpio0_cti_i),
.wbs1_bte_i (wbs_d_gpio0_bte_i),
.wbs1_dat_o (wbs_d_gpio0_dat_o),
.wbs1_ack_o (wbs_d_gpio0_ack_o),
.wbs1_err_o (wbs_d_gpio0_err_o),
.wbs1_rty_o (wbs_d_gpio0_rty_o),
.wbs2_adr_i (wbs_d_i2c0_adr_i),
.wbs2_dat_i (wbs_d_i2c0_dat_i),
.wbs2_we_i (wbs_d_i2c0_we_i),
.wbs2_cyc_i (wbs_d_i2c0_cyc_i),
.wbs2_stb_i (wbs_d_i2c0_stb_i),
.wbs2_cti_i (wbs_d_i2c0_cti_i),
.wbs2_bte_i (wbs_d_i2c0_bte_i),
.wbs2_dat_o (wbs_d_i2c0_dat_o),
.wbs2_ack_o (wbs_d_i2c0_ack_o),
.wbs2_err_o (wbs_d_i2c0_err_o),
.wbs2_rty_o (wbs_d_i2c0_rty_o),
.wbs3_adr_i (wbs_d_i2c1_adr_i),
.wbs3_dat_i (wbs_d_i2c1_dat_i),
.wbs3_we_i (wbs_d_i2c1_we_i),
.wbs3_cyc_i (wbs_d_i2c1_cyc_i),
.wbs3_stb_i (wbs_d_i2c1_stb_i),
.wbs3_cti_i (wbs_d_i2c1_cti_i),
.wbs3_bte_i (wbs_d_i2c1_bte_i),
.wbs3_dat_o (wbs_d_i2c1_dat_o),
.wbs3_ack_o (wbs_d_i2c1_ack_o),
.wbs3_err_o (wbs_d_i2c1_err_o),
.wbs3_rty_o (wbs_d_i2c1_rty_o),
.wbs4_adr_i (wbs_d_spi0_adr_i),
.wbs4_dat_i (wbs_d_spi0_dat_i),
.wbs4_we_i (wbs_d_spi0_we_i),
.wbs4_cyc_i (wbs_d_spi0_cyc_i),
.wbs4_stb_i (wbs_d_spi0_stb_i),
.wbs4_cti_i (wbs_d_spi0_cti_i),
.wbs4_bte_i (wbs_d_spi0_bte_i),
.wbs4_dat_o (wbs_d_spi0_dat_o),
.wbs4_ack_o (wbs_d_spi0_ack_o),
.wbs4_err_o (wbs_d_spi0_err_o),
.wbs4_rty_o (wbs_d_spi0_rty_o),
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width;
defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves;
defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr;
defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr;
defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr;
defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr;
defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr;
//
// Wires
//
wire [30:0] or1200_pic_ints;
wire [31:0] or1200_dbg_dat_i;
wire [31:0] or1200_dbg_adr_i;
wire or1200_dbg_we_i;
wire or1200_dbg_stb_i;
wire or1200_dbg_ack_o;
wire [31:0] or1200_dbg_dat_o;
wire or1200_dbg_stall_i;
wire or1200_dbg_ewt_i;
wire [3:0] or1200_dbg_lss_o;
wire [1:0] or1200_dbg_is_o;
wire [10:0] or1200_dbg_wp_o;
wire or1200_dbg_bp_o;
wire or1200_dbg_rst;
wire or1200_clk, or1200_rst;
wire sig_tick;
`ifdef JTAG_DEBUG
assign jtag_gnd = 0;
assign jtag_vdd = 1;
////////////////////////////////////////////////////////////////////////
//
// JTAG TAP
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr, jtag_tap_pause_dr,
jtag_tap_upate_dr, jtag_tap_capture_dr;
//
// Instantiation
//
jtag_tap jtag_tap0
(
// Ports to pads
.tdo_pad_o (tdo_pad_o),
.tms_pad_i (tms_pad_i),
.tck_pad_i (dbg_tck),
.trst_pad_i (async_rst),
.tdi_pad_i (tdi_pad_i),
.tdo_padoe_o (tdo_padoe_o),
.tdo_o (jtag_tap_tdo),
.shift_dr_o (jtag_tap_shift_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.capture_dr_o (jtag_tap_capture_dr),
.extest_select_o (),
.sample_preload_select_o (),
.mbist_select_o (),
.debug_select_o (dbg_if_select),
.bs_chain_tdi_i (1'b0),
.mbist_tdi_i (1'b0),
.debug_tdi_i (dbg_if_tdo)
);
////////////////////////////////////////////////////////////////////////
//
// OR1200 Debug Interface
//
////////////////////////////////////////////////////////////////////////
dbg_if dbg_if0
(
// OR1200 interface
.cpu0_clk_i (or1200_clk),
.cpu0_rst_o (or1200_dbg_rst),
.cpu0_addr_o (or1200_dbg_adr_i),
.cpu0_data_o (or1200_dbg_dat_i),
.cpu0_stb_o (or1200_dbg_stb_i),
.cpu0_we_o (or1200_dbg_we_i),
.cpu0_data_i (or1200_dbg_dat_o),
.cpu0_ack_i (or1200_dbg_ack_o),
.cpu0_stall_o (or1200_dbg_stall_i),
.cpu0_bp_i (or1200_dbg_bp_o),
// TAP interface
.tck_i (dbg_tck),
.tdi_i (jtag_tap_tdo),
.tdo_o (dbg_if_tdo),
.rst_i (wb_rst),
.shift_dr_i (jtag_tap_shift_dr),
.pause_dr_i (jtag_tap_pause_dr),
.update_dr_i (jtag_tap_update_dr),
.debug_select_i (dbg_if_select),
// Wishbone debug master
.wb_clk_i (wb_clk),
.wb_dat_i (wbm_d_dbg_dat_i),
.wb_ack_i (wbm_d_dbg_ack_i),
.wb_err_i (wbm_d_dbg_err_i),
.wb_adr_o (wbm_d_dbg_adr_o),
.wb_dat_o (wbm_d_dbg_dat_o),
.wb_cyc_o (wbm_d_dbg_cyc_o),
.wb_stb_o (wbm_d_dbg_stb_o),
.wb_sel_o (wbm_d_dbg_sel_o),
.wb_we_o (wbm_d_dbg_we_o ),
.wb_cti_o (wbm_d_dbg_cti_o),
.wb_cab_o (/* UNUSED */),
.wb_bte_o (wbm_d_dbg_bte_o)
);
`elsif ADV_DEBUG
wire jtag_tck;
wire debug_tdi;
wire debug_tdo;
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire debug_select;
wire test_logic_reset;
adbg_top dbg_top(
// JTAG pins
.tck_i ( jtag_tck ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( test_logic_reset ), //cable without rst
// Boundary Scan signals
.capture_dr_i ( capture_dr ),
.shift_dr_i ( shift_dr ),
.pause_dr_i ( pause_dr ),
.update_dr_i ( update_dr ),
.debug_select_i( debug_select ),
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
// WISHBONE master interface
.wb_adr_o ( wbm_d_dbg_adr_o ),
.wb_dat_i ( wbm_d_dbg_dat_i ),
.wb_dat_o ( wbm_d_dbg_dat_o ),
.wb_sel_o ( wbm_d_dbg_sel_o ),
.wb_we_o ( wbm_d_dbg_we_o ),
.wb_stb_o ( wbm_d_dbg_stb_o ),
.wb_cyc_o ( wbm_d_dbg_cyc_o ),
.wb_ack_i ( wbm_d_dbg_ack_i ),
.wb_err_i ( wbm_d_dbg_err_i ),
.wb_cti_o ( wbm_d_dbg_cti_o ),
.wb_bte_o ( wbm_d_dbg_bte_o ),
// RISC signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( or1200_dbg_adr_i ),
.cpu0_data_i ( or1200_dbg_dat_o ),
.cpu0_data_o ( or1200_dbg_dat_i ),
.cpu0_bp_i ( or1200_dbg_bp_o ),
.cpu0_stall_o( or1200_dbg_stall_i ),
.cpu0_stb_o ( or1200_dbg_stb_i ),
.cpu0_we_o ( or1200_dbg_we_i ),
.cpu0_ack_i ( or1200_dbg_ack_o ),
.cpu0_rst_o ( or1200_dbg_rst)
);
xilinx_internal_jtag tap_top(
.tck_o( jtag_tck ),
.debug_tdo_i( debug_tdo ),
.tdi_o( debug_tdi ),
.test_logic_reset_o( test_logic_reset ),
.run_test_idle_o( ),
.shift_dr_o( shift_dr ),
.capture_dr_o( capture_dr ),
.pause_dr_o( pause_dr ),
.update_dr_o( update_dr ),
.debug_select_o( debug_select )
);
assign tdo_pad_o = 0;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef JTAG_DEBUG !`ifdef ADV_DEBUG
assign wbm_d_dbg_adr_o = 0;
assign wbm_d_dbg_dat_o = 0;
assign wbm_d_dbg_cyc_o = 0;
assign wbm_d_dbg_stb_o = 0;
assign wbm_d_dbg_sel_o = 0;
assign wbm_d_dbg_we_o = 0;
assign wbm_d_dbg_cti_o = 0;
assign wbm_d_dbg_bte_o = 0;
assign or1200_dbg_adr_i = 0;
assign or1200_dbg_dat_i = 0;
assign or1200_dbg_stb_i = 0;
assign or1200_dbg_we_i = 0;
assign or1200_dbg_stall_i = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef JTAG_DEBUG and ! `ifdef ADV_DEBUG
////////////////////////////////////////////////////////////////////////
//
// OpenRISC processor
//
////////////////////////////////////////////////////////////////////////
//
// Assigns
//
assign or1200_clk = wb_clk;
assign or1200_rst = wb_rst | or1200_dbg_rst;
wire sp_refresh_disable;
//
// Instantiation
//
or1200_top or1200_top0
(
// Instruction bus, clocks, reset
.iwb_clk_i (wb_clk),
.iwb_rst_i (wb_rst),
.iwb_ack_i (wbm_i_or12_ack_i),
.iwb_err_i (wbm_i_or12_err_i),
.iwb_rty_i (wbm_i_or12_rty_i),
.iwb_dat_i (wbm_i_or12_dat_i),
.iwb_cyc_o (wbm_i_or12_cyc_o),
.iwb_adr_o (wbm_i_or12_adr_o),
.iwb_stb_o (wbm_i_or12_stb_o),
.iwb_we_o (wbm_i_or12_we_o),
.iwb_sel_o (wbm_i_or12_sel_o),
.iwb_dat_o (wbm_i_or12_dat_o),
.iwb_cti_o (wbm_i_or12_cti_o),
.iwb_bte_o (wbm_i_or12_bte_o),
// Data bus, clocks, reset
.dwb_clk_i (wb_clk),
.dwb_rst_i (wb_rst),
.dwb_ack_i (wbm_d_or12_ack_i),
.dwb_err_i (wbm_d_or12_err_i),
.dwb_rty_i (wbm_d_or12_rty_i),
.dwb_dat_i (wbm_d_or12_dat_i),
.dwb_cyc_o (wbm_d_or12_cyc_o),
.dwb_adr_o (wbm_d_or12_adr_o),
.dwb_stb_o (wbm_d_or12_stb_o),
.dwb_we_o (wbm_d_or12_we_o),
.dwb_sel_o (wbm_d_or12_sel_o),
.dwb_dat_o (wbm_d_or12_dat_o),
.dwb_cti_o (wbm_d_or12_cti_o),
.dwb_bte_o (wbm_d_or12_bte_o),
// Debug interface ports
.dbg_stall_i (or1200_dbg_stall_i),
//.dbg_ewt_i (or1200_dbg_ewt_i),
.dbg_ewt_i (1'b0),
.dbg_lss_o (or1200_dbg_lss_o),
.dbg_is_o (or1200_dbg_is_o),
.dbg_wp_o (or1200_dbg_wp_o),
.dbg_bp_o (or1200_dbg_bp_o),
.dbg_adr_i (or1200_dbg_adr_i),
.dbg_we_i (or1200_dbg_we_i ),
.dbg_stb_i (or1200_dbg_stb_i),
.dbg_dat_i (or1200_dbg_dat_i),
.dbg_dat_o (or1200_dbg_dat_o),
.dbg_ack_o (or1200_dbg_ack_o),
.pm_clksd_o (),
.pm_dc_gate_o (),
.pm_ic_gate_o (),
.pm_dmmu_gate_o (),
.pm_immu_gate_o (),
.pm_tt_gate_o (),
.pm_cpu_gate_o (),
.pm_wakeup_o (),
.pm_lvolt_o (),
// Core clocks, resets
.clk_i (or1200_clk),
.rst_i (or1200_rst),
.clmode_i (2'b00),
// Interrupts
.pic_ints_i (or1200_pic_ints),
.sig_tick(sig_tick),
/*
.mbist_so_o (),
.mbist_si_i (0),
.mbist_ctrl_i (0),
*/
.pm_cpustall_i (1'b0)
, .sp_refresh_disable(sp_refresh_disable)
);
////////////////////////////////////////////////////////////////////////
`ifdef XILINX_DDR2
wire [2:0] ba_from_ctrl;
////////////////////////////////////////////////////////////////////////
//
// Xilinx MIG DDR2 controller, Wishbone interface
//
////////////////////////////////////////////////////////////////////////
xilinx_ddr2 xilinx_ddr2_0
(
.wbm0_adr_i (wbm_eth0_adr_o),
.wbm0_bte_i (wbm_eth0_bte_o),
.wbm0_cti_i (wbm_eth0_cti_o),
.wbm0_cyc_i (wbm_eth0_cyc_o),
.wbm0_dat_i (wbm_eth0_dat_o),
.wbm0_sel_i (wbm_eth0_sel_o),
.wbm0_stb_i (wbm_eth0_stb_o),
.wbm0_we_i (wbm_eth0_we_o),
.wbm0_ack_o (wbm_eth0_ack_i),
.wbm0_err_o (wbm_eth0_err_i),
.wbm0_rty_o (wbm_eth0_rty_i),
.wbm0_dat_o (wbm_eth0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
.wbm1_bte_i (wbs_d_mc0_bte_i),
.wbm1_cti_i (wbs_d_mc0_cti_i),
.wbm1_cyc_i (wbs_d_mc0_cyc_i),
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_sel_i (wbs_d_mc0_sel_i),
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_we_i (wbs_d_mc0_we_i),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm2_adr_i (wbs_i_mc0_adr_i),
.wbm2_bte_i (wbs_i_mc0_bte_i),
.wbm2_cti_i (wbs_i_mc0_cti_i),
.wbm2_cyc_i (wbs_i_mc0_cyc_i),
.wbm2_dat_i (wbs_i_mc0_dat_i),
.wbm2_sel_i (wbs_i_mc0_sel_i),
.wbm2_stb_i (wbs_i_mc0_stb_i),
.wbm2_we_i (wbs_i_mc0_we_i),
.wbm2_ack_o (wbs_i_mc0_ack_o),
.wbm2_err_o (wbs_i_mc0_err_o),
.wbm2_rty_o (wbs_i_mc0_rty_o),
.wbm2_dat_o (wbs_i_mc0_dat_o),
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.ddr2_a (ddr2_a[12:0]),
.ddr2_ba (ba_from_ctrl),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm[7:0]),
.ddr2_ck (ddr2_ck[1:0]),
.ddr2_ck_n (ddr2_ck_n[1:0]),
.ddr2_dq (ddr2_dq[63:0]),
.ddr2_dqs (ddr2_dqs[7:0]),
.ddr2_dqs_n (ddr2_dqs_n[7:0]),
.ddr2_if_clk (ddr2_if_clk),
.clk200 (clk200),
.ddr2_if_rst (ddr2_if_rst)
, .sp_refresh_disable(sp_refresh_disable)
);
assign ddr2_ba = 2'b0;
assign GPIO_LED_0 = ba_from_ctrl[0];
assign GPIO_LED_1 = ba_from_ctrl[1];
`endif
`ifdef ROM_WB
////////////////////////////////////////////////////////////////////////
//
// ROM
//
////////////////////////////////////////////////////////////////////////
rom rom0
(
.wb_dat_o (wbs_i_rom0_dat_o),
.wb_ack_o (wbs_i_rom0_ack_o),
.wb_adr_i (wbs_i_rom0_adr_i[(wbs_i_rom0_addr_width+2)-1:2]),
.wb_stb_i (wbs_i_rom0_stb_i),
.wb_cyc_i (wbs_i_rom0_cyc_i),
.wb_cti_i (wbs_i_rom0_cti_i),
.wb_bte_i (wbs_i_rom0_bte_i),
.wb_clk (wb_clk),
.wb_rst (wb_rst));
defparam rom0.addr_width = wbs_i_rom0_addr_width;
`else // !`ifdef ROM_WB
assign wbs_i_rom0_dat_o = 0;
assign wbs_i_rom0_ack_o = 0;
`endif // !`ifdef ROM_WB
assign wbs_i_rom0_err_o = 0;
assign wbs_i_rom0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`ifdef RAM_WB
////////////////////////////////////////////////////////////////////////
//
// Generic RAM
//
////////////////////////////////////////////////////////////////////////
ram_wb ram_wb0
(
// Wishbone slave interface 0
.wbm0_dat_i (wbs_i_ram0_dat_i),
.wbm0_adr_i (wbs_i_ram0_adr_i),
.wbm0_sel_i (wbs_i_ram0_sel_i),
.wbm0_cti_i (wbs_i_ram0_cti_i),
.wbm0_bte_i (wbs_i_ram0_bte_i),
.wbm0_we_i (wbs_i_ram0_we_i ),
.wbm0_cyc_i (wbs_i_ram0_cyc_i),
.wbm0_stb_i (wbs_i_ram0_stb_i),
.wbm0_dat_o (wbs_i_ram0_dat_o),
.wbm0_ack_o (wbs_i_ram0_ack_o),
.wbm0_err_o (wbs_i_ram0_err_o),
.wbm0_rty_o (wbs_i_ram0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_ram0_dat_i),
.wbm1_adr_i (wbs_d_ram0_adr_i),
.wbm1_sel_i (wbs_d_ram0_sel_i),
.wbm1_cti_i (wbs_d_ram0_cti_i),
.wbm1_bte_i (wbs_d_ram0_bte_i),
.wbm1_we_i (wbs_d_ram0_we_i ),
.wbm1_cyc_i (wbs_d_ram0_cyc_i),
.wbm1_stb_i (wbs_d_ram0_stb_i),
.wbm1_dat_o (wbs_d_ram0_dat_o),
.wbm1_ack_o (wbs_d_ram0_ack_o),
.wbm1_err_o (wbs_d_ram0_err_o),
.wbm1_rty_o (wbs_d_ram0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (32'b0),
.wbm2_adr_i (32'b0),
.wbm2_sel_i (4'b0),
.wbm2_cti_i (3'b0),
.wbm2_bte_i (2'b0),
.wbm2_we_i (1'b0),
.wbm2_cyc_i (1'b0),
.wbm2_stb_i (1'b0),
.wbm2_dat_o (),
.wbm2_ack_o (),
.wbm2_err_o (),
.wbm2_rty_o (),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_size_bytes = 1 << wbs_i_rom0_addr_width;
defparam ram_wb0.mem_adr_width = wbs_i_rom0_addr_width; // log2(8192*1024)
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
`ifdef ETH0
//
// Wires
//
wire eth0_irq;
wire [3:0] eth0_mtxd;
wire eth0_mtxen;
wire eth0_mtxerr;
wire eth0_mtx_clk;
wire eth0_mrx_clk;
wire [3:0] eth0_mrxd;
wire eth0_mrxdv;
wire eth0_mrxerr;
wire eth0_mcoll;
wire eth0_mcrs;
wire eth0_speed;
wire eth0_duplex;
wire eth0_link;
// Management interface wires
wire eth0_md_i;
wire eth0_md_o;
wire eth0_md_oe;
//
// assigns
// Hook up MII wires
assign eth0_mtx_clk = eth0_tx_clk;
assign eth0_tx_data = eth0_mtxd[3:0];
assign eth0_tx_en = eth0_mtxen;
assign eth0_tx_er = eth0_mtxerr;
assign eth0_mrxd[3:0] = eth0_rx_data;
assign eth0_mrxdv = eth0_dv;
assign eth0_mrxerr = eth0_rx_er;
assign eth0_mrx_clk = eth0_rx_clk;
assign eth0_mcoll = eth0_col;
assign eth0_mcrs = eth0_crs;
`ifdef XILINX
// Xilinx primitive for MDIO tristate
IOBUF iobuf_phy_smi_data
(
// Outputs
.O (eth0_md_i),
// Inouts
.IO (eth0_md_pad_io),
// Inputs
.I (eth0_md_o),
.T (!eth0_md_oe));
`else // !`ifdef XILINX
// Generic technology tristate control for management interface
assign eth0_md_pad_io = eth0_md_oe ? eth0_md_o : 1'bz;
assign eth0_md_i = eth0_md_pad_io;
`endif // !`ifdef XILINX
`ifdef ETH0_PHY_RST
assign eth0_rst_n_o = !wb_rst;
`endif
ethmac ethmac0
(
// Wishbone Slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_dat_i (wbs_d_eth0_dat_i[31:0]),
.wb_adr_i (wbs_d_eth0_adr_i[wbs_d_eth0_addr_width-1:2]),
.wb_sel_i (wbs_d_eth0_sel_i[3:0]),
.wb_we_i (wbs_d_eth0_we_i),
.wb_cyc_i (wbs_d_eth0_cyc_i),
.wb_stb_i (wbs_d_eth0_stb_i),
.wb_dat_o (wbs_d_eth0_dat_o[31:0]),
.wb_err_o (wbs_d_eth0_err_o),
.wb_ack_o (wbs_d_eth0_ack_o),
// Wishbone Master Interface
.m_wb_adr_o (wbm_eth0_adr_o[31:0]),
.m_wb_sel_o (wbm_eth0_sel_o[3:0]),
.m_wb_we_o (wbm_eth0_we_o),
.m_wb_dat_o (wbm_eth0_dat_o[31:0]),
.m_wb_cyc_o (wbm_eth0_cyc_o),
.m_wb_stb_o (wbm_eth0_stb_o),
.m_wb_cti_o (wbm_eth0_cti_o[2:0]),
.m_wb_bte_o (wbm_eth0_bte_o[1:0]),
.m_wb_dat_i (wbm_eth0_dat_i[31:0]),
.m_wb_ack_i (wbm_eth0_ack_i),
.m_wb_err_i (wbm_eth0_err_i),
// Ethernet MII interface
// Transmit
.mtxd_pad_o (eth0_mtxd[3:0]),
.mtxen_pad_o (eth0_mtxen),
.mtxerr_pad_o (eth0_mtxerr),
.mtx_clk_pad_i (eth0_mtx_clk),
// Receive
.mrx_clk_pad_i (eth0_mrx_clk),
.mrxd_pad_i (eth0_mrxd[3:0]),
.mrxdv_pad_i (eth0_mrxdv),
.mrxerr_pad_i (eth0_mrxerr),
.mcoll_pad_i (eth0_mcoll),
.mcrs_pad_i (eth0_mcrs),
// Management interface
.md_pad_i (eth0_md_i),
.mdc_pad_o (eth0_mdc_pad_o),
.md_pad_o (eth0_md_o),
.md_padoe_o (eth0_md_oe),
// Processor interrupt
.int_o (eth0_irq)
/*
.mbist_so_o (),
.mbist_si_i (),
.mbist_ctrl_i ()
*/
);
assign wbs_d_eth0_rty_o = 0;
`else
assign wbs_d_eth0_dat_o = 0;
assign wbs_d_eth0_err_o = 0;
assign wbs_d_eth0_ack_o = 0;
assign wbs_d_eth0_rty_o = 0;
assign wbm_eth0_adr_o = 0;
assign wbm_eth0_sel_o = 0;
assign wbm_eth0_we_o = 0;
assign wbm_eth0_dat_o = 0;
assign wbm_eth0_cyc_o = 0;
assign wbm_eth0_stb_o = 0;
assign wbm_eth0_cti_o = 0;
assign wbm_eth0_bte_o = 0;
`endif
`ifdef UART0
////////////////////////////////////////////////////////////////////////
//
// UART0
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire uart0_srx;
wire uart0_stx;
wire uart0_irq;
//
// Assigns
//
assign wbs_d_uart0_err_o = 0;
assign wbs_d_uart0_rty_o = 0;
// Two UART lines coming to single one (ensure they go high when unconnected)
assign uart0_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i;
assign uart0_stx_pad_o = uart0_stx;
assign uart0_stx_expheader_pad_o = uart0_stx;
uart_top uart16550_0
(
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wbs_d_uart0_adr_i[uart0_addr_width-1:0]),
.wb_dat_i (wbs_d_uart0_dat_i),
.wb_we_i (wbs_d_uart0_we_i),
.wb_stb_i (wbs_d_uart0_stb_i),
.wb_cyc_i (wbs_d_uart0_cyc_i),
.wb_sel_i (4'hF),
.wb_dat_o (wbs_d_uart0_dat_o),
.wb_ack_o (wbs_d_uart0_ack_o),
.int_o (uart0_irq),
.stx_pad_o (uart0_stx),
.rts_pad_o (),
.dtr_pad_o (),
// .baud_o (),
// Inputs
.srx_pad_i (uart0_srx),
.cts_pad_i (1'b0),
.dsr_pad_i (1'b0),
.ri_pad_i (1'b0),
.dcd_pad_i (1'b0));
////////////////////////////////////////////////////////////////////////
`else // !`ifdef UART0
//
// Assigns
//
assign wbs_d_uart0_err_o = 0;
assign wbs_d_uart0_rty_o = 0;
assign wbs_d_uart0_ack_o = 0;
assign wbs_d_uart0_dat_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef UART0
`ifdef SPI0
////////////////////////////////////////////////////////////////////////
//
// SPI0 controller
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire spi0_irq;
//
// Assigns
//
assign wbs_d_spi0_err_o = 0;
assign wbs_d_spi0_rty_o = 0;
//assign spi0_hold_n_o = 1;
//assign spi0_w_n_o = 1;
simple_spi spi0
(
// Wishbone slave interface
.clk_i (wb_clk),
.rst_i (wb_rst),
.cyc_i (wbs_d_spi0_cyc_i),
.stb_i (wbs_d_spi0_stb_i),
.adr_i (wbs_d_spi0_adr_i[spi0_wb_adr_width-1:0]),
.we_i (wbs_d_spi0_we_i),
.dat_i (wbs_d_spi0_dat_i),
.dat_o (wbs_d_spi0_dat_o),
.ack_o (wbs_d_spi0_ack_o),
// SPI IRQ
.inta_o (spi0_irq),
// External SPI interface
.sck_o (spi0_sck_o),
.ss_o (spi0_ss_o),
.mosi_o (spi0_mosi_o),
.miso_i (spi0_miso_i)
);
defparam spi0.slave_select_width = spi0_ss_width;
// SPI clock and MISO lines must go through STARTUP_VIRTEX5 block.
STARTUP_VIRTEX5 startup_virtex5
(
.CFGCLK(),
.CFGMCLK(),
.DINSPI(spi0_miso_i),
.EOS(),
.TCKSPI(),
.CLK(),
.GSR(1'b0),
.GTS(1'b0),
.USRCCLKO(spi0_sck_o),
.USRCCLKTS(1'b0),
.USRDONEO(),
.USRDONETS()
);
////////////////////////////////////////////////////////////////////////
`else // !`ifdef SPI0
//
// Assigns
//
assign wbs_d_spi0_dat_o = 0;
assign wbs_d_spi0_ack_o = 0;
assign wbs_d_spi0_err_o = 0;
assign wbs_d_spi0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef SPI0
`ifdef I2C0
////////////////////////////////////////////////////////////////////////
//
// i2c controller 0
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire i2c0_irq;
wire scl0_pad_o;
wire scl0_padoen_o;
wire sda0_pad_o;
wire sda0_padoen_o;
i2c_master_slave
#
(
.DEFAULT_SLAVE_ADDR(HV0_SADR)
)
i2c_master_slave0
(
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.arst_i (wb_rst),
.wb_adr_i (wbs_d_i2c0_adr_i[i2c_0_wb_adr_width-1:0]),
.wb_dat_i (wbs_d_i2c0_dat_i),
.wb_we_i (wbs_d_i2c0_we_i ),
.wb_cyc_i (wbs_d_i2c0_cyc_i),
.wb_stb_i (wbs_d_i2c0_stb_i),
.wb_dat_o (wbs_d_i2c0_dat_o),
.wb_ack_o (wbs_d_i2c0_ack_o),
.scl_pad_i (i2c0_scl_io ),
.scl_pad_o (scl0_pad_o ),
.scl_padoen_o (scl0_padoen_o ),
.sda_pad_i (i2c0_sda_io ),
.sda_pad_o (sda0_pad_o ),
.sda_padoen_o (sda0_padoen_o ),
// Interrupt
.wb_inta_o (i2c0_irq)
);
assign wbs_d_i2c0_err_o = 0;
assign wbs_d_i2c0_rty_o = 0;
// i2c phy lines
assign i2c0_scl_io = scl0_padoen_o ? 1'bz : scl0_pad_o;
assign i2c0_sda_io = sda0_padoen_o ? 1'bz : sda0_pad_o;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef I2C0
assign wbs_d_i2c0_dat_o = 0;
assign wbs_d_i2c0_ack_o = 0;
assign wbs_d_i2c0_err_o = 0;
assign wbs_d_i2c0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef I2C0
`ifdef I2C1
////////////////////////////////////////////////////////////////////////
//
// i2c controller 1
//
////////////////////////////////////////////////////////////////////////
//
// Wires
//
wire i2c1_irq;
wire scl1_pad_o;
wire scl1_padoen_o;
wire sda1_pad_o;
wire sda1_padoen_o;
i2c_master_slave
#
(
.DEFAULT_SLAVE_ADDR(HV1_SADR)
)
i2c_master_slave1
(
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.arst_i (wb_rst),
.wb_adr_i (wbs_d_i2c1_adr_i[i2c_1_wb_adr_width-1:0]),
.wb_dat_i (wbs_d_i2c1_dat_i),
.wb_we_i (wbs_d_i2c1_we_i ),
.wb_cyc_i (wbs_d_i2c1_cyc_i),
.wb_stb_i (wbs_d_i2c1_stb_i),
.wb_dat_o (wbs_d_i2c1_dat_o),
.wb_ack_o (wbs_d_i2c1_ack_o),
.scl_pad_i (i2c1_scl_io ),
.scl_pad_o (scl1_pad_o ),
.scl_padoen_o (scl1_padoen_o ),
.sda_pad_i (i2c1_sda_io ),
.sda_pad_o (sda1_pad_o ),
.sda_padoen_o (sda1_padoen_o ),
// Interrupt
.wb_inta_o (i2c1_irq)
);
assign wbs_d_i2c1_err_o = 0;
assign wbs_d_i2c1_rty_o = 0;
// i2c phy lines
assign i2c1_scl_io = scl1_padoen_o ? 1'bz : scl1_pad_o;
assign i2c1_sda_io = sda1_padoen_o ? 1'bz : sda1_pad_o;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef I2C1
assign wbs_d_i2c1_dat_o = 0;
assign wbs_d_i2c1_ack_o = 0;
assign wbs_d_i2c1_err_o = 0;
assign wbs_d_i2c1_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef I2C1
`ifdef GPIO0
////////////////////////////////////////////////////////////////////////
//
// GPIO 0
//
////////////////////////////////////////////////////////////////////////
gpio gpio0
(
// GPIO bus
.gpio_io (gpio0_io[gpio0_io_width-1:0]),
// Wishbone slave interface
.wb_adr_i (wbs_d_gpio0_adr_i[gpio0_wb_adr_width-1:0]),
.wb_dat_i (wbs_d_gpio0_dat_i),
.wb_we_i (wbs_d_gpio0_we_i),
.wb_cyc_i (wbs_d_gpio0_cyc_i),
.wb_stb_i (wbs_d_gpio0_stb_i),
.wb_cti_i (wbs_d_gpio0_cti_i),
.wb_bte_i (wbs_d_gpio0_bte_i),
.wb_dat_o (wbs_d_gpio0_dat_o),
.wb_ack_o (wbs_d_gpio0_ack_o),
.wb_err_o (wbs_d_gpio0_err_o),
.wb_rty_o (wbs_d_gpio0_rty_o),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
defparam gpio0.gpio_io_width = gpio0_io_width;
defparam gpio0.gpio_dir_reset_val = gpio0_dir_reset_val;
defparam gpio0.gpio_o_reset_val = gpio0_o_reset_val;
////////////////////////////////////////////////////////////////////////
`else // !`ifdef GPIO0
assign wbs_d_gpio0_dat_o = 0;
assign wbs_d_gpio0_ack_o = 0;
assign wbs_d_gpio0_err_o = 0;
assign wbs_d_gpio0_rty_o = 0;
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef GPIO0
////////////////////////////////////////////////////////////////////////
//
// OR1200 Interrupt assignment
//
////////////////////////////////////////////////////////////////////////
assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200
assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200
`ifdef UART0
assign or1200_pic_ints[2] = uart0_irq;
`else
assign or1200_pic_ints[2] = 0;
`endif
assign or1200_pic_ints[3] = 0;
`ifdef ETH0
assign or1200_pic_ints[4] = eth0_irq;
`else
assign or1200_pic_ints[4] = 0;
`endif
assign or1200_pic_ints[5] = 0;
`ifdef SPI0
assign or1200_pic_ints[6] = spi0_irq;
`else
assign or1200_pic_ints[6] = 0;
`endif
assign or1200_pic_ints[7] = 0;
assign or1200_pic_ints[8] = 0;
assign or1200_pic_ints[9] = 0;
`ifdef I2C0
assign or1200_pic_ints[10] = i2c0_irq;
`else
assign or1200_pic_ints[10] = 0;
`endif
`ifdef I2C1
assign or1200_pic_ints[11] = i2c1_irq;
`else
assign or1200_pic_ints[11] = 0;
`endif
assign or1200_pic_ints[12] = 0;
assign or1200_pic_ints[13] = 0;
assign or1200_pic_ints[14] = 0;
assign or1200_pic_ints[15] = 0;
assign or1200_pic_ints[16] = 0;
assign or1200_pic_ints[17] = 0;
assign or1200_pic_ints[18] = 0;
assign or1200_pic_ints[19] = 0;
assign or1200_pic_ints[20] = 0;
assign or1200_pic_ints[21] = 0;
assign or1200_pic_ints[22] = 0;
assign or1200_pic_ints[23] = 0;
assign or1200_pic_ints[24] = 0;
assign or1200_pic_ints[25] = 0;
assign or1200_pic_ints[26] = 0;
assign or1200_pic_ints[27] = 0;
assign or1200_pic_ints[28] = 0;
assign or1200_pic_ints[29] = 0;
assign or1200_pic_ints[30] = 0;
endmodule // orpsoc_top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_HD__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_NSR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_DFF_NSR_PP_PG_N_SYMBOL_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$NSR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
input SET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_NSR_PP_PG_N_SYMBOL_V
|
module cla_adder(
input [31:0] A,
input [31:0] B,
input Cin,
output [31:0] Sum,
output Cout
);
wire [31:0] a_plus_b_cin_0;
wire [31:0] a_plus_b_cin_1;
full_adder fa_00_cin_0
full_adder fa_01_cin_0
full_adder fa_02_cin_0
full_adder fa_03_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
endmodule |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: buffer.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module buffer (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_2_V
`define SKY130_FD_SC_MS__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_2_V
|
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